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be663ab6 WYG |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
31 | ||
32 | #include <linux/kernel.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/pci-aspm.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/sched.h> | |
41 | #include <linux/skbuff.h> | |
42 | #include <linux/netdevice.h> | |
be663ab6 WYG |
43 | #include <linux/firmware.h> |
44 | #include <linux/etherdevice.h> | |
45 | #include <linux/if_arp.h> | |
46 | ||
47 | #include <net/mac80211.h> | |
48 | ||
49 | #include <asm/div64.h> | |
50 | ||
51 | #define DRV_NAME "iwl4965" | |
52 | ||
53 | #include "iwl-eeprom.h" | |
54 | #include "iwl-dev.h" | |
55 | #include "iwl-core.h" | |
56 | #include "iwl-io.h" | |
57 | #include "iwl-helpers.h" | |
58 | #include "iwl-sta.h" | |
59 | #include "iwl-4965-calib.h" | |
60 | #include "iwl-4965.h" | |
61 | #include "iwl-4965-led.h" | |
62 | ||
63 | ||
64 | /****************************************************************************** | |
65 | * | |
66 | * module boiler plate | |
67 | * | |
68 | ******************************************************************************/ | |
69 | ||
70 | /* | |
71 | * module name, copyright, version, etc. | |
72 | */ | |
73 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux" | |
74 | ||
d3175167 | 75 | #ifdef CONFIG_IWLEGACY_DEBUG |
be663ab6 WYG |
76 | #define VD "d" |
77 | #else | |
78 | #define VD | |
79 | #endif | |
80 | ||
81 | #define DRV_VERSION IWLWIFI_VERSION VD | |
82 | ||
83 | ||
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); | |
87 | MODULE_LICENSE("GPL"); | |
88 | MODULE_ALIAS("iwl4965"); | |
89 | ||
46bc8d4b | 90 | void il4965_update_chain_flags(struct il_priv *il) |
be663ab6 | 91 | { |
e2ebc833 | 92 | struct il_rxon_context *ctx; |
be663ab6 | 93 | |
46bc8d4b SG |
94 | if (il->cfg->ops->hcmd->set_rxon_chain) { |
95 | for_each_context(il, ctx) { | |
96 | il->cfg->ops->hcmd->set_rxon_chain(il, ctx); | |
be663ab6 | 97 | if (ctx->active.rx_chain != ctx->staging.rx_chain) |
46bc8d4b | 98 | il_commit_rxon(il, ctx); |
be663ab6 WYG |
99 | } |
100 | } | |
101 | } | |
102 | ||
46bc8d4b | 103 | static void il4965_clear_free_frames(struct il_priv *il) |
be663ab6 WYG |
104 | { |
105 | struct list_head *element; | |
106 | ||
58de00a4 | 107 | D_INFO("%d frames on pre-allocated heap on clear.\n", |
46bc8d4b | 108 | il->frames_count); |
be663ab6 | 109 | |
46bc8d4b SG |
110 | while (!list_empty(&il->free_frames)) { |
111 | element = il->free_frames.next; | |
be663ab6 | 112 | list_del(element); |
e2ebc833 | 113 | kfree(list_entry(element, struct il_frame, list)); |
46bc8d4b | 114 | il->frames_count--; |
be663ab6 WYG |
115 | } |
116 | ||
46bc8d4b | 117 | if (il->frames_count) { |
9406f797 | 118 | IL_WARN("%d frames still in use. Did we lose one?\n", |
46bc8d4b SG |
119 | il->frames_count); |
120 | il->frames_count = 0; | |
be663ab6 WYG |
121 | } |
122 | } | |
123 | ||
46bc8d4b | 124 | static struct il_frame *il4965_get_free_frame(struct il_priv *il) |
be663ab6 | 125 | { |
e2ebc833 | 126 | struct il_frame *frame; |
be663ab6 | 127 | struct list_head *element; |
46bc8d4b | 128 | if (list_empty(&il->free_frames)) { |
be663ab6 WYG |
129 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); |
130 | if (!frame) { | |
9406f797 | 131 | IL_ERR("Could not allocate frame!\n"); |
be663ab6 WYG |
132 | return NULL; |
133 | } | |
134 | ||
46bc8d4b | 135 | il->frames_count++; |
be663ab6 WYG |
136 | return frame; |
137 | } | |
138 | ||
46bc8d4b | 139 | element = il->free_frames.next; |
be663ab6 | 140 | list_del(element); |
e2ebc833 | 141 | return list_entry(element, struct il_frame, list); |
be663ab6 WYG |
142 | } |
143 | ||
46bc8d4b | 144 | static void il4965_free_frame(struct il_priv *il, struct il_frame *frame) |
be663ab6 WYG |
145 | { |
146 | memset(frame, 0, sizeof(*frame)); | |
46bc8d4b | 147 | list_add(&frame->list, &il->free_frames); |
be663ab6 WYG |
148 | } |
149 | ||
46bc8d4b | 150 | static u32 il4965_fill_beacon_frame(struct il_priv *il, |
be663ab6 WYG |
151 | struct ieee80211_hdr *hdr, |
152 | int left) | |
153 | { | |
46bc8d4b | 154 | lockdep_assert_held(&il->mutex); |
be663ab6 | 155 | |
46bc8d4b | 156 | if (!il->beacon_skb) |
be663ab6 WYG |
157 | return 0; |
158 | ||
46bc8d4b | 159 | if (il->beacon_skb->len > left) |
be663ab6 WYG |
160 | return 0; |
161 | ||
46bc8d4b | 162 | memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len); |
be663ab6 | 163 | |
46bc8d4b | 164 | return il->beacon_skb->len; |
be663ab6 WYG |
165 | } |
166 | ||
167 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ | |
46bc8d4b | 168 | static void il4965_set_beacon_tim(struct il_priv *il, |
e2ebc833 | 169 | struct il_tx_beacon_cmd *tx_beacon_cmd, |
be663ab6 WYG |
170 | u8 *beacon, u32 frame_size) |
171 | { | |
172 | u16 tim_idx; | |
173 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
174 | ||
175 | /* | |
176 | * The index is relative to frame start but we start looking at the | |
177 | * variable-length part of the beacon. | |
178 | */ | |
179 | tim_idx = mgmt->u.beacon.variable - beacon; | |
180 | ||
181 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
182 | while ((tim_idx < (frame_size - 2)) && | |
183 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
184 | tim_idx += beacon[tim_idx+1] + 2; | |
185 | ||
186 | /* If TIM field was found, set variables */ | |
187 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
188 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
189 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
190 | } else | |
9406f797 | 191 | IL_WARN("Unable to find TIM Element in beacon\n"); |
be663ab6 WYG |
192 | } |
193 | ||
46bc8d4b | 194 | static unsigned int il4965_hw_get_beacon_cmd(struct il_priv *il, |
e2ebc833 | 195 | struct il_frame *frame) |
be663ab6 | 196 | { |
e2ebc833 | 197 | struct il_tx_beacon_cmd *tx_beacon_cmd; |
be663ab6 WYG |
198 | u32 frame_size; |
199 | u32 rate_flags; | |
200 | u32 rate; | |
201 | /* | |
202 | * We have to set up the TX command, the TX Beacon command, and the | |
203 | * beacon contents. | |
204 | */ | |
205 | ||
46bc8d4b | 206 | lockdep_assert_held(&il->mutex); |
be663ab6 | 207 | |
46bc8d4b | 208 | if (!il->beacon_ctx) { |
9406f797 | 209 | IL_ERR("trying to build beacon w/o beacon context!\n"); |
be663ab6 WYG |
210 | return 0; |
211 | } | |
212 | ||
213 | /* Initialize memory */ | |
214 | tx_beacon_cmd = &frame->u.beacon; | |
215 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
216 | ||
217 | /* Set up TX beacon contents */ | |
46bc8d4b | 218 | frame_size = il4965_fill_beacon_frame(il, tx_beacon_cmd->frame, |
be663ab6 WYG |
219 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
220 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) | |
221 | return 0; | |
222 | if (!frame_size) | |
223 | return 0; | |
224 | ||
225 | /* Set up TX command fields */ | |
226 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | |
46bc8d4b | 227 | tx_beacon_cmd->tx.sta_id = il->beacon_ctx->bcast_sta_id; |
be663ab6 WYG |
228 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
229 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
230 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
231 | ||
232 | /* Set up TX beacon command fields */ | |
46bc8d4b | 233 | il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame, |
be663ab6 WYG |
234 | frame_size); |
235 | ||
236 | /* Set up packet rate and flags */ | |
46bc8d4b SG |
237 | rate = il_get_lowest_plcp(il, il->beacon_ctx); |
238 | il->mgmt_tx_ant = il4965_toggle_tx_ant(il, il->mgmt_tx_ant, | |
239 | il->hw_params.valid_tx_ant); | |
240 | rate_flags = il4965_ant_idx_to_flags(il->mgmt_tx_ant); | |
e2ebc833 | 241 | if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE)) |
be663ab6 | 242 | rate_flags |= RATE_MCS_CCK_MSK; |
e2ebc833 | 243 | tx_beacon_cmd->tx.rate_n_flags = il4965_hw_set_rate_n_flags(rate, |
be663ab6 WYG |
244 | rate_flags); |
245 | ||
246 | return sizeof(*tx_beacon_cmd) + frame_size; | |
247 | } | |
248 | ||
46bc8d4b | 249 | int il4965_send_beacon_cmd(struct il_priv *il) |
be663ab6 | 250 | { |
e2ebc833 | 251 | struct il_frame *frame; |
be663ab6 WYG |
252 | unsigned int frame_size; |
253 | int rc; | |
254 | ||
46bc8d4b | 255 | frame = il4965_get_free_frame(il); |
be663ab6 | 256 | if (!frame) { |
9406f797 | 257 | IL_ERR("Could not obtain free frame buffer for beacon " |
be663ab6 WYG |
258 | "command.\n"); |
259 | return -ENOMEM; | |
260 | } | |
261 | ||
46bc8d4b | 262 | frame_size = il4965_hw_get_beacon_cmd(il, frame); |
be663ab6 | 263 | if (!frame_size) { |
9406f797 | 264 | IL_ERR("Error configuring the beacon command\n"); |
46bc8d4b | 265 | il4965_free_frame(il, frame); |
be663ab6 WYG |
266 | return -EINVAL; |
267 | } | |
268 | ||
46bc8d4b | 269 | rc = il_send_cmd_pdu(il, REPLY_TX_BEACON, frame_size, |
be663ab6 WYG |
270 | &frame->u.cmd[0]); |
271 | ||
46bc8d4b | 272 | il4965_free_frame(il, frame); |
be663ab6 WYG |
273 | |
274 | return rc; | |
275 | } | |
276 | ||
e2ebc833 | 277 | static inline dma_addr_t il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx) |
be663ab6 | 278 | { |
e2ebc833 | 279 | struct il_tfd_tb *tb = &tfd->tbs[idx]; |
be663ab6 WYG |
280 | |
281 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
282 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
283 | addr |= | |
284 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
285 | ||
286 | return addr; | |
287 | } | |
288 | ||
e2ebc833 | 289 | static inline u16 il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx) |
be663ab6 | 290 | { |
e2ebc833 | 291 | struct il_tfd_tb *tb = &tfd->tbs[idx]; |
be663ab6 WYG |
292 | |
293 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
294 | } | |
295 | ||
e2ebc833 | 296 | static inline void il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, |
be663ab6 WYG |
297 | dma_addr_t addr, u16 len) |
298 | { | |
e2ebc833 | 299 | struct il_tfd_tb *tb = &tfd->tbs[idx]; |
be663ab6 WYG |
300 | u16 hi_n_len = len << 4; |
301 | ||
302 | put_unaligned_le32(addr, &tb->lo); | |
303 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
304 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
305 | ||
306 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
307 | ||
308 | tfd->num_tbs = idx + 1; | |
309 | } | |
310 | ||
e2ebc833 | 311 | static inline u8 il4965_tfd_get_num_tbs(struct il_tfd *tfd) |
be663ab6 WYG |
312 | { |
313 | return tfd->num_tbs & 0x1f; | |
314 | } | |
315 | ||
316 | /** | |
e2ebc833 | 317 | * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] |
46bc8d4b | 318 | * @il - driver ilate data |
be663ab6 WYG |
319 | * @txq - tx queue |
320 | * | |
321 | * Does NOT advance any TFD circular buffer read/write indexes | |
322 | * Does NOT free the TFD itself (which is within circular buffer) | |
323 | */ | |
46bc8d4b | 324 | void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq) |
be663ab6 | 325 | { |
e2ebc833 SG |
326 | struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds; |
327 | struct il_tfd *tfd; | |
46bc8d4b | 328 | struct pci_dev *dev = il->pci_dev; |
be663ab6 WYG |
329 | int index = txq->q.read_ptr; |
330 | int i; | |
331 | int num_tbs; | |
332 | ||
333 | tfd = &tfd_tmp[index]; | |
334 | ||
335 | /* Sanity check on number of chunks */ | |
e2ebc833 | 336 | num_tbs = il4965_tfd_get_num_tbs(tfd); |
be663ab6 | 337 | |
e2ebc833 | 338 | if (num_tbs >= IL_NUM_OF_TBS) { |
9406f797 | 339 | IL_ERR("Too many chunks: %i\n", num_tbs); |
be663ab6 WYG |
340 | /* @todo issue fatal error, it is quite serious situation */ |
341 | return; | |
342 | } | |
343 | ||
344 | /* Unmap tx_cmd */ | |
345 | if (num_tbs) | |
346 | pci_unmap_single(dev, | |
347 | dma_unmap_addr(&txq->meta[index], mapping), | |
348 | dma_unmap_len(&txq->meta[index], len), | |
349 | PCI_DMA_BIDIRECTIONAL); | |
350 | ||
351 | /* Unmap chunks, if any. */ | |
352 | for (i = 1; i < num_tbs; i++) | |
e2ebc833 SG |
353 | pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i), |
354 | il4965_tfd_tb_get_len(tfd, i), | |
be663ab6 WYG |
355 | PCI_DMA_TODEVICE); |
356 | ||
357 | /* free SKB */ | |
358 | if (txq->txb) { | |
359 | struct sk_buff *skb; | |
360 | ||
361 | skb = txq->txb[txq->q.read_ptr].skb; | |
362 | ||
363 | /* can be called from irqs-disabled context */ | |
364 | if (skb) { | |
365 | dev_kfree_skb_any(skb); | |
366 | txq->txb[txq->q.read_ptr].skb = NULL; | |
367 | } | |
368 | } | |
369 | } | |
370 | ||
46bc8d4b | 371 | int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, |
e2ebc833 | 372 | struct il_tx_queue *txq, |
be663ab6 WYG |
373 | dma_addr_t addr, u16 len, |
374 | u8 reset, u8 pad) | |
375 | { | |
e2ebc833 SG |
376 | struct il_queue *q; |
377 | struct il_tfd *tfd, *tfd_tmp; | |
be663ab6 WYG |
378 | u32 num_tbs; |
379 | ||
380 | q = &txq->q; | |
e2ebc833 | 381 | tfd_tmp = (struct il_tfd *)txq->tfds; |
be663ab6 WYG |
382 | tfd = &tfd_tmp[q->write_ptr]; |
383 | ||
384 | if (reset) | |
385 | memset(tfd, 0, sizeof(*tfd)); | |
386 | ||
e2ebc833 | 387 | num_tbs = il4965_tfd_get_num_tbs(tfd); |
be663ab6 WYG |
388 | |
389 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
e2ebc833 | 390 | if (num_tbs >= IL_NUM_OF_TBS) { |
9406f797 | 391 | IL_ERR("Error can not send more than %d chunks\n", |
e2ebc833 | 392 | IL_NUM_OF_TBS); |
be663ab6 WYG |
393 | return -EINVAL; |
394 | } | |
395 | ||
396 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
e2ebc833 | 397 | if (unlikely(addr & ~IL_TX_DMA_MASK)) |
9406f797 | 398 | IL_ERR("Unaligned address = %llx\n", |
be663ab6 WYG |
399 | (unsigned long long)addr); |
400 | ||
e2ebc833 | 401 | il4965_tfd_set_tb(tfd, num_tbs, addr, len); |
be663ab6 WYG |
402 | |
403 | return 0; | |
404 | } | |
405 | ||
406 | /* | |
407 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
408 | * given Tx queue, and enable the DMA channel used for that queue. | |
409 | * | |
410 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
411 | * channels supported in hardware. | |
412 | */ | |
46bc8d4b | 413 | int il4965_hw_tx_queue_init(struct il_priv *il, |
e2ebc833 | 414 | struct il_tx_queue *txq) |
be663ab6 WYG |
415 | { |
416 | int txq_id = txq->q.id; | |
417 | ||
418 | /* Circular buffer (TFD queue in DRAM) physical base address */ | |
0c1a94e2 | 419 | il_wr(il, FH_MEM_CBBC_QUEUE(txq_id), |
be663ab6 WYG |
420 | txq->q.dma_addr >> 8); |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
425 | /****************************************************************************** | |
426 | * | |
427 | * Generic RX handler implementations | |
428 | * | |
429 | ******************************************************************************/ | |
46bc8d4b | 430 | static void il4965_rx_reply_alive(struct il_priv *il, |
e2ebc833 | 431 | struct il_rx_mem_buffer *rxb) |
be663ab6 | 432 | { |
dcae1c64 | 433 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e2ebc833 | 434 | struct il_alive_resp *palive; |
be663ab6 WYG |
435 | struct delayed_work *pwork; |
436 | ||
437 | palive = &pkt->u.alive_frame; | |
438 | ||
58de00a4 | 439 | D_INFO("Alive ucode status 0x%08X revision " |
be663ab6 WYG |
440 | "0x%01X 0x%01X\n", |
441 | palive->is_valid, palive->ver_type, | |
442 | palive->ver_subtype); | |
443 | ||
444 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
58de00a4 | 445 | D_INFO("Initialization Alive received.\n"); |
46bc8d4b | 446 | memcpy(&il->card_alive_init, |
be663ab6 | 447 | &pkt->u.alive_frame, |
e2ebc833 | 448 | sizeof(struct il_init_alive_resp)); |
46bc8d4b | 449 | pwork = &il->init_alive_start; |
be663ab6 | 450 | } else { |
58de00a4 | 451 | D_INFO("Runtime Alive received.\n"); |
46bc8d4b | 452 | memcpy(&il->card_alive, &pkt->u.alive_frame, |
e2ebc833 | 453 | sizeof(struct il_alive_resp)); |
46bc8d4b | 454 | pwork = &il->alive_start; |
be663ab6 WYG |
455 | } |
456 | ||
457 | /* We delay the ALIVE response by 5ms to | |
458 | * give the HW RF Kill time to activate... */ | |
459 | if (palive->is_valid == UCODE_VALID_OK) | |
46bc8d4b | 460 | queue_delayed_work(il->workqueue, pwork, |
be663ab6 WYG |
461 | msecs_to_jiffies(5)); |
462 | else | |
9406f797 | 463 | IL_WARN("uCode did not respond OK.\n"); |
be663ab6 WYG |
464 | } |
465 | ||
466 | /** | |
e2ebc833 | 467 | * il4965_bg_statistics_periodic - Timer callback to queue statistics |
be663ab6 WYG |
468 | * |
469 | * This callback is provided in order to send a statistics request. | |
470 | * | |
471 | * This timer function is continually reset to execute within | |
472 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
473 | * was received. We need to ensure we receive the statistics in order | |
474 | * to update the temperature used for calibrating the TXPOWER. | |
475 | */ | |
e2ebc833 | 476 | static void il4965_bg_statistics_periodic(unsigned long data) |
be663ab6 | 477 | { |
46bc8d4b | 478 | struct il_priv *il = (struct il_priv *)data; |
be663ab6 | 479 | |
46bc8d4b | 480 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
481 | return; |
482 | ||
483 | /* dont send host command if rf-kill is on */ | |
46bc8d4b | 484 | if (!il_is_ready_rf(il)) |
be663ab6 WYG |
485 | return; |
486 | ||
46bc8d4b | 487 | il_send_statistics_request(il, CMD_ASYNC, false); |
be663ab6 WYG |
488 | } |
489 | ||
46bc8d4b | 490 | static void il4965_rx_beacon_notif(struct il_priv *il, |
e2ebc833 | 491 | struct il_rx_mem_buffer *rxb) |
be663ab6 | 492 | { |
dcae1c64 | 493 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e2ebc833 SG |
494 | struct il4965_beacon_notif *beacon = |
495 | (struct il4965_beacon_notif *)pkt->u.raw; | |
d3175167 | 496 | #ifdef CONFIG_IWLEGACY_DEBUG |
e2ebc833 | 497 | u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
be663ab6 | 498 | |
58de00a4 | 499 | D_RX("beacon status %x retries %d iss %d " |
be663ab6 WYG |
500 | "tsf %d %d rate %d\n", |
501 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, | |
502 | beacon->beacon_notify_hdr.failure_frame, | |
503 | le32_to_cpu(beacon->ibss_mgr_status), | |
504 | le32_to_cpu(beacon->high_tsf), | |
505 | le32_to_cpu(beacon->low_tsf), rate); | |
506 | #endif | |
507 | ||
46bc8d4b | 508 | il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); |
be663ab6 WYG |
509 | } |
510 | ||
46bc8d4b | 511 | static void il4965_perform_ct_kill_task(struct il_priv *il) |
be663ab6 WYG |
512 | { |
513 | unsigned long flags; | |
514 | ||
58de00a4 | 515 | D_POWER("Stop all queues\n"); |
be663ab6 | 516 | |
46bc8d4b SG |
517 | if (il->mac80211_registered) |
518 | ieee80211_stop_queues(il->hw); | |
be663ab6 | 519 | |
841b2cca | 520 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, |
be663ab6 | 521 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
841b2cca | 522 | _il_rd(il, CSR_UCODE_DRV_GP1); |
be663ab6 | 523 | |
46bc8d4b | 524 | spin_lock_irqsave(&il->reg_lock, flags); |
13882269 SG |
525 | if (!_il_grab_nic_access(il)) |
526 | _il_release_nic_access(il); | |
46bc8d4b | 527 | spin_unlock_irqrestore(&il->reg_lock, flags); |
be663ab6 WYG |
528 | } |
529 | ||
530 | /* Handle notification from uCode that card's power state is changing | |
531 | * due to software, hardware, or critical temperature RFKILL */ | |
46bc8d4b | 532 | static void il4965_rx_card_state_notif(struct il_priv *il, |
e2ebc833 | 533 | struct il_rx_mem_buffer *rxb) |
be663ab6 | 534 | { |
dcae1c64 | 535 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
be663ab6 | 536 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
46bc8d4b | 537 | unsigned long status = il->status; |
be663ab6 | 538 | |
58de00a4 | 539 | D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n", |
be663ab6 WYG |
540 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
541 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", | |
542 | (flags & CT_CARD_DISABLED) ? | |
543 | "Reached" : "Not reached"); | |
544 | ||
545 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
546 | CT_CARD_DISABLED)) { | |
547 | ||
841b2cca | 548 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, |
be663ab6 WYG |
549 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
550 | ||
0c1a94e2 | 551 | il_wr(il, HBUS_TARG_MBX_C, |
be663ab6 WYG |
552 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
553 | ||
554 | if (!(flags & RXON_CARD_DISABLED)) { | |
841b2cca | 555 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, |
be663ab6 | 556 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
0c1a94e2 | 557 | il_wr(il, HBUS_TARG_MBX_C, |
be663ab6 WYG |
558 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
559 | } | |
560 | } | |
561 | ||
562 | if (flags & CT_CARD_DISABLED) | |
46bc8d4b | 563 | il4965_perform_ct_kill_task(il); |
be663ab6 WYG |
564 | |
565 | if (flags & HW_CARD_DISABLED) | |
46bc8d4b | 566 | set_bit(STATUS_RF_KILL_HW, &il->status); |
be663ab6 | 567 | else |
46bc8d4b | 568 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
be663ab6 WYG |
569 | |
570 | if (!(flags & RXON_CARD_DISABLED)) | |
46bc8d4b | 571 | il_scan_cancel(il); |
be663ab6 WYG |
572 | |
573 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
46bc8d4b SG |
574 | test_bit(STATUS_RF_KILL_HW, &il->status))) |
575 | wiphy_rfkill_set_hw_state(il->hw->wiphy, | |
576 | test_bit(STATUS_RF_KILL_HW, &il->status)); | |
be663ab6 | 577 | else |
46bc8d4b | 578 | wake_up(&il->wait_command_queue); |
be663ab6 WYG |
579 | } |
580 | ||
581 | /** | |
e2ebc833 | 582 | * il4965_setup_rx_handlers - Initialize Rx handler callbacks |
be663ab6 WYG |
583 | * |
584 | * Setup the RX handlers for each of the reply types sent from the uCode | |
585 | * to the host. | |
586 | * | |
587 | * This function chains into the hardware specific files for them to setup | |
588 | * any hardware specific handlers as well. | |
589 | */ | |
46bc8d4b | 590 | static void il4965_setup_rx_handlers(struct il_priv *il) |
be663ab6 | 591 | { |
46bc8d4b SG |
592 | il->rx_handlers[REPLY_ALIVE] = il4965_rx_reply_alive; |
593 | il->rx_handlers[REPLY_ERROR] = il_rx_reply_error; | |
594 | il->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = il_rx_csa; | |
595 | il->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = | |
e2ebc833 | 596 | il_rx_spectrum_measure_notif; |
46bc8d4b SG |
597 | il->rx_handlers[PM_SLEEP_NOTIFICATION] = il_rx_pm_sleep_notif; |
598 | il->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = | |
e2ebc833 | 599 | il_rx_pm_debug_statistics_notif; |
46bc8d4b | 600 | il->rx_handlers[BEACON_NOTIFICATION] = il4965_rx_beacon_notif; |
be663ab6 WYG |
601 | |
602 | /* | |
603 | * The same handler is used for both the REPLY to a discrete | |
604 | * statistics request from the host as well as for the periodic | |
605 | * statistics notifications (after received beacons) from the uCode. | |
606 | */ | |
46bc8d4b SG |
607 | il->rx_handlers[REPLY_STATISTICS_CMD] = il4965_reply_statistics; |
608 | il->rx_handlers[STATISTICS_NOTIFICATION] = il4965_rx_statistics; | |
be663ab6 | 609 | |
46bc8d4b | 610 | il_setup_rx_scan_handlers(il); |
be663ab6 WYG |
611 | |
612 | /* status change handler */ | |
46bc8d4b | 613 | il->rx_handlers[CARD_STATE_NOTIFICATION] = |
e2ebc833 | 614 | il4965_rx_card_state_notif; |
be663ab6 | 615 | |
46bc8d4b | 616 | il->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
e2ebc833 | 617 | il4965_rx_missed_beacon_notif; |
be663ab6 | 618 | /* Rx handlers */ |
46bc8d4b SG |
619 | il->rx_handlers[REPLY_RX_PHY_CMD] = il4965_rx_reply_rx_phy; |
620 | il->rx_handlers[REPLY_RX_MPDU_CMD] = il4965_rx_reply_rx; | |
be663ab6 | 621 | /* block ack */ |
46bc8d4b | 622 | il->rx_handlers[REPLY_COMPRESSED_BA] = il4965_rx_reply_compressed_ba; |
be663ab6 | 623 | /* Set up hardware specific Rx handlers */ |
46bc8d4b | 624 | il->cfg->ops->lib->rx_handler_setup(il); |
be663ab6 WYG |
625 | } |
626 | ||
627 | /** | |
e2ebc833 | 628 | * il4965_rx_handle - Main entry function for receiving responses from uCode |
be663ab6 | 629 | * |
46bc8d4b | 630 | * Uses the il->rx_handlers callback function array to invoke |
be663ab6 WYG |
631 | * the appropriate handlers, including command responses, |
632 | * frame-received notifications, and other notifications. | |
633 | */ | |
46bc8d4b | 634 | void il4965_rx_handle(struct il_priv *il) |
be663ab6 | 635 | { |
e2ebc833 | 636 | struct il_rx_mem_buffer *rxb; |
dcae1c64 | 637 | struct il_rx_pkt *pkt; |
46bc8d4b | 638 | struct il_rx_queue *rxq = &il->rxq; |
be663ab6 WYG |
639 | u32 r, i; |
640 | int reclaim; | |
641 | unsigned long flags; | |
642 | u8 fill_rx = 0; | |
643 | u32 count = 8; | |
644 | int total_empty; | |
645 | ||
646 | /* uCode's read index (stored in shared DRAM) indicates the last Rx | |
647 | * buffer that the driver may process (last buffer filled by ucode). */ | |
648 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; | |
649 | i = rxq->read; | |
650 | ||
651 | /* Rx interrupt, but nothing sent from uCode */ | |
652 | if (i == r) | |
58de00a4 | 653 | D_RX("r = %d, i = %d\n", r, i); |
be663ab6 WYG |
654 | |
655 | /* calculate total frames need to be restock after handling RX */ | |
656 | total_empty = r - rxq->write_actual; | |
657 | if (total_empty < 0) | |
658 | total_empty += RX_QUEUE_SIZE; | |
659 | ||
660 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
661 | fill_rx = 1; | |
662 | ||
663 | while (i != r) { | |
664 | int len; | |
665 | ||
666 | rxb = rxq->queue[i]; | |
667 | ||
668 | /* If an RXB doesn't have a Rx queue slot associated with it, | |
669 | * then a bug has been introduced in the queue refilling | |
670 | * routines -- catch it here */ | |
671 | BUG_ON(rxb == NULL); | |
672 | ||
673 | rxq->queue[i] = NULL; | |
674 | ||
46bc8d4b SG |
675 | pci_unmap_page(il->pci_dev, rxb->page_dma, |
676 | PAGE_SIZE << il->hw_params.rx_page_order, | |
be663ab6 WYG |
677 | PCI_DMA_FROMDEVICE); |
678 | pkt = rxb_addr(rxb); | |
679 | ||
680 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; | |
681 | len += sizeof(u32); /* account for status word */ | |
be663ab6 WYG |
682 | |
683 | /* Reclaim a command buffer only if this packet is a response | |
684 | * to a (driver-originated) command. | |
685 | * If the packet (e.g. Rx frame) originated from uCode, | |
686 | * there is no command buffer to reclaim. | |
687 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
688 | * but apparently a few don't get set; catch them here. */ | |
689 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
690 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
691 | (pkt->hdr.cmd != REPLY_RX) && | |
692 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && | |
693 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && | |
694 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && | |
695 | (pkt->hdr.cmd != REPLY_TX); | |
696 | ||
697 | /* Based on type of command response or notification, | |
698 | * handle those that need handling via function in | |
e2ebc833 | 699 | * rx_handlers table. See il4965_setup_rx_handlers() */ |
46bc8d4b | 700 | if (il->rx_handlers[pkt->hdr.cmd]) { |
58de00a4 | 701 | D_RX("r = %d, i = %d, %s, 0x%02x\n", r, |
e2ebc833 | 702 | i, il_get_cmd_string(pkt->hdr.cmd), |
be663ab6 | 703 | pkt->hdr.cmd); |
46bc8d4b SG |
704 | il->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
705 | il->rx_handlers[pkt->hdr.cmd] (il, rxb); | |
be663ab6 WYG |
706 | } else { |
707 | /* No handling needed */ | |
58de00a4 | 708 | D_RX( |
be663ab6 | 709 | "r %d i %d No handler needed for %s, 0x%02x\n", |
e2ebc833 | 710 | r, i, il_get_cmd_string(pkt->hdr.cmd), |
be663ab6 WYG |
711 | pkt->hdr.cmd); |
712 | } | |
713 | ||
714 | /* | |
715 | * XXX: After here, we should always check rxb->page | |
716 | * against NULL before touching it or its virtual | |
717 | * memory (pkt). Because some rx_handler might have | |
718 | * already taken or freed the pages. | |
719 | */ | |
720 | ||
721 | if (reclaim) { | |
722 | /* Invoke any callbacks, transfer the buffer to caller, | |
e2ebc833 | 723 | * and fire off the (possibly) blocking il_send_cmd() |
be663ab6 WYG |
724 | * as we reclaim the driver command queue */ |
725 | if (rxb->page) | |
46bc8d4b | 726 | il_tx_cmd_complete(il, rxb); |
be663ab6 | 727 | else |
9406f797 | 728 | IL_WARN("Claim null rxb?\n"); |
be663ab6 WYG |
729 | } |
730 | ||
731 | /* Reuse the page if possible. For notification packets and | |
732 | * SKBs that fail to Rx correctly, add them back into the | |
733 | * rx_free list for reuse later. */ | |
734 | spin_lock_irqsave(&rxq->lock, flags); | |
735 | if (rxb->page != NULL) { | |
46bc8d4b SG |
736 | rxb->page_dma = pci_map_page(il->pci_dev, rxb->page, |
737 | 0, PAGE_SIZE << il->hw_params.rx_page_order, | |
be663ab6 WYG |
738 | PCI_DMA_FROMDEVICE); |
739 | list_add_tail(&rxb->list, &rxq->rx_free); | |
740 | rxq->free_count++; | |
741 | } else | |
742 | list_add_tail(&rxb->list, &rxq->rx_used); | |
743 | ||
744 | spin_unlock_irqrestore(&rxq->lock, flags); | |
745 | ||
746 | i = (i + 1) & RX_QUEUE_MASK; | |
747 | /* If there are a lot of unused frames, | |
748 | * restock the Rx queue so ucode wont assert. */ | |
749 | if (fill_rx) { | |
750 | count++; | |
751 | if (count >= 8) { | |
752 | rxq->read = i; | |
46bc8d4b | 753 | il4965_rx_replenish_now(il); |
be663ab6 WYG |
754 | count = 0; |
755 | } | |
756 | } | |
757 | } | |
758 | ||
759 | /* Backtrack one entry */ | |
760 | rxq->read = i; | |
761 | if (fill_rx) | |
46bc8d4b | 762 | il4965_rx_replenish_now(il); |
be663ab6 | 763 | else |
46bc8d4b | 764 | il4965_rx_queue_restock(il); |
be663ab6 WYG |
765 | } |
766 | ||
767 | /* call this function to flush any scheduled tasklet */ | |
46bc8d4b | 768 | static inline void il4965_synchronize_irq(struct il_priv *il) |
be663ab6 WYG |
769 | { |
770 | /* wait to make sure we flush pending tasklet*/ | |
46bc8d4b SG |
771 | synchronize_irq(il->pci_dev->irq); |
772 | tasklet_kill(&il->irq_tasklet); | |
be663ab6 WYG |
773 | } |
774 | ||
46bc8d4b | 775 | static void il4965_irq_tasklet(struct il_priv *il) |
be663ab6 WYG |
776 | { |
777 | u32 inta, handled = 0; | |
778 | u32 inta_fh; | |
779 | unsigned long flags; | |
780 | u32 i; | |
d3175167 | 781 | #ifdef CONFIG_IWLEGACY_DEBUG |
be663ab6 WYG |
782 | u32 inta_mask; |
783 | #endif | |
784 | ||
46bc8d4b | 785 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 WYG |
786 | |
787 | /* Ack/clear/reset pending uCode interrupts. | |
788 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
789 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
841b2cca SG |
790 | inta = _il_rd(il, CSR_INT); |
791 | _il_wr(il, CSR_INT, inta); | |
be663ab6 WYG |
792 | |
793 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
794 | * Any new interrupts that happen after this, either while we're | |
795 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
841b2cca SG |
796 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); |
797 | _il_wr(il, CSR_FH_INT_STATUS, inta_fh); | |
be663ab6 | 798 | |
d3175167 | 799 | #ifdef CONFIG_IWLEGACY_DEBUG |
46bc8d4b | 800 | if (il_get_debug_level(il) & IL_DL_ISR) { |
be663ab6 | 801 | /* just for debug */ |
841b2cca | 802 | inta_mask = _il_rd(il, CSR_INT_MASK); |
58de00a4 | 803 | D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
be663ab6 WYG |
804 | inta, inta_mask, inta_fh); |
805 | } | |
806 | #endif | |
807 | ||
46bc8d4b | 808 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 WYG |
809 | |
810 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
811 | * atomic, make sure that inta covers all the interrupts that | |
812 | * we've discovered, even if FH interrupt came in just after | |
813 | * reading CSR_INT. */ | |
814 | if (inta_fh & CSR49_FH_INT_RX_MASK) | |
815 | inta |= CSR_INT_BIT_FH_RX; | |
816 | if (inta_fh & CSR49_FH_INT_TX_MASK) | |
817 | inta |= CSR_INT_BIT_FH_TX; | |
818 | ||
819 | /* Now service all interrupt bits discovered above. */ | |
820 | if (inta & CSR_INT_BIT_HW_ERR) { | |
9406f797 | 821 | IL_ERR("Hardware error detected. Restarting.\n"); |
be663ab6 WYG |
822 | |
823 | /* Tell the device to stop sending interrupts */ | |
46bc8d4b | 824 | il_disable_interrupts(il); |
be663ab6 | 825 | |
46bc8d4b SG |
826 | il->isr_stats.hw++; |
827 | il_irq_handle_error(il); | |
be663ab6 WYG |
828 | |
829 | handled |= CSR_INT_BIT_HW_ERR; | |
830 | ||
831 | return; | |
832 | } | |
833 | ||
d3175167 | 834 | #ifdef CONFIG_IWLEGACY_DEBUG |
46bc8d4b | 835 | if (il_get_debug_level(il) & (IL_DL_ISR)) { |
be663ab6 WYG |
836 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
837 | if (inta & CSR_INT_BIT_SCD) { | |
58de00a4 | 838 | D_ISR("Scheduler finished to transmit " |
be663ab6 | 839 | "the frame/frames.\n"); |
46bc8d4b | 840 | il->isr_stats.sch++; |
be663ab6 WYG |
841 | } |
842 | ||
843 | /* Alive notification via Rx interrupt will do the real work */ | |
844 | if (inta & CSR_INT_BIT_ALIVE) { | |
58de00a4 | 845 | D_ISR("Alive interrupt\n"); |
46bc8d4b | 846 | il->isr_stats.alive++; |
be663ab6 WYG |
847 | } |
848 | } | |
849 | #endif | |
850 | /* Safely ignore these bits for debug checks below */ | |
851 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
852 | ||
853 | /* HW RF KILL switch toggled */ | |
854 | if (inta & CSR_INT_BIT_RF_KILL) { | |
855 | int hw_rf_kill = 0; | |
841b2cca | 856 | if (!(_il_rd(il, CSR_GP_CNTRL) & |
be663ab6 WYG |
857 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
858 | hw_rf_kill = 1; | |
859 | ||
9406f797 | 860 | IL_WARN("RF_KILL bit toggled to %s.\n", |
be663ab6 WYG |
861 | hw_rf_kill ? "disable radio" : "enable radio"); |
862 | ||
46bc8d4b | 863 | il->isr_stats.rfkill++; |
be663ab6 WYG |
864 | |
865 | /* driver only loads ucode once setting the interface up. | |
866 | * the driver allows loading the ucode even if the radio | |
867 | * is killed. Hence update the killswitch state here. The | |
868 | * rfkill handler will care about restarting if needed. | |
869 | */ | |
46bc8d4b | 870 | if (!test_bit(STATUS_ALIVE, &il->status)) { |
be663ab6 | 871 | if (hw_rf_kill) |
46bc8d4b | 872 | set_bit(STATUS_RF_KILL_HW, &il->status); |
be663ab6 | 873 | else |
46bc8d4b SG |
874 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
875 | wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill); | |
be663ab6 WYG |
876 | } |
877 | ||
878 | handled |= CSR_INT_BIT_RF_KILL; | |
879 | } | |
880 | ||
881 | /* Chip got too hot and stopped itself */ | |
882 | if (inta & CSR_INT_BIT_CT_KILL) { | |
9406f797 | 883 | IL_ERR("Microcode CT kill error detected.\n"); |
46bc8d4b | 884 | il->isr_stats.ctkill++; |
be663ab6 WYG |
885 | handled |= CSR_INT_BIT_CT_KILL; |
886 | } | |
887 | ||
888 | /* Error detected by uCode */ | |
889 | if (inta & CSR_INT_BIT_SW_ERR) { | |
9406f797 | 890 | IL_ERR("Microcode SW error detected. " |
be663ab6 | 891 | " Restarting 0x%X.\n", inta); |
46bc8d4b SG |
892 | il->isr_stats.sw++; |
893 | il_irq_handle_error(il); | |
be663ab6 WYG |
894 | handled |= CSR_INT_BIT_SW_ERR; |
895 | } | |
896 | ||
897 | /* | |
898 | * uCode wakes up after power-down sleep. | |
899 | * Tell device about any new tx or host commands enqueued, | |
900 | * and about any Rx buffers made available while asleep. | |
901 | */ | |
902 | if (inta & CSR_INT_BIT_WAKEUP) { | |
58de00a4 | 903 | D_ISR("Wakeup interrupt\n"); |
46bc8d4b SG |
904 | il_rx_queue_update_write_ptr(il, &il->rxq); |
905 | for (i = 0; i < il->hw_params.max_txq_num; i++) | |
906 | il_txq_update_write_ptr(il, &il->txq[i]); | |
907 | il->isr_stats.wakeup++; | |
be663ab6 WYG |
908 | handled |= CSR_INT_BIT_WAKEUP; |
909 | } | |
910 | ||
911 | /* All uCode command responses, including Tx command responses, | |
912 | * Rx "responses" (frame-received notification), and other | |
913 | * notifications from uCode come through here*/ | |
914 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
46bc8d4b SG |
915 | il4965_rx_handle(il); |
916 | il->isr_stats.rx++; | |
be663ab6 WYG |
917 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
918 | } | |
919 | ||
920 | /* This "Tx" DMA channel is used only for loading uCode */ | |
921 | if (inta & CSR_INT_BIT_FH_TX) { | |
58de00a4 | 922 | D_ISR("uCode load interrupt\n"); |
46bc8d4b | 923 | il->isr_stats.tx++; |
be663ab6 WYG |
924 | handled |= CSR_INT_BIT_FH_TX; |
925 | /* Wake up uCode load routine, now that load is complete */ | |
46bc8d4b SG |
926 | il->ucode_write_complete = 1; |
927 | wake_up(&il->wait_command_queue); | |
be663ab6 WYG |
928 | } |
929 | ||
930 | if (inta & ~handled) { | |
9406f797 | 931 | IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled); |
46bc8d4b | 932 | il->isr_stats.unhandled++; |
be663ab6 WYG |
933 | } |
934 | ||
46bc8d4b | 935 | if (inta & ~(il->inta_mask)) { |
9406f797 | 936 | IL_WARN("Disabled INTA bits 0x%08x were pending\n", |
46bc8d4b | 937 | inta & ~il->inta_mask); |
9406f797 | 938 | IL_WARN(" with FH_INT = 0x%08x\n", inta_fh); |
be663ab6 WYG |
939 | } |
940 | ||
941 | /* Re-enable all interrupts */ | |
93fd74e3 | 942 | /* only Re-enable if disabled by irq */ |
46bc8d4b SG |
943 | if (test_bit(STATUS_INT_ENABLED, &il->status)) |
944 | il_enable_interrupts(il); | |
a078a1fd SG |
945 | /* Re-enable RF_KILL if it occurred */ |
946 | else if (handled & CSR_INT_BIT_RF_KILL) | |
46bc8d4b | 947 | il_enable_rfkill_int(il); |
be663ab6 | 948 | |
d3175167 | 949 | #ifdef CONFIG_IWLEGACY_DEBUG |
46bc8d4b | 950 | if (il_get_debug_level(il) & (IL_DL_ISR)) { |
841b2cca SG |
951 | inta = _il_rd(il, CSR_INT); |
952 | inta_mask = _il_rd(il, CSR_INT_MASK); | |
953 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); | |
58de00a4 | 954 | D_ISR( |
be663ab6 WYG |
955 | "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
956 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
957 | } | |
958 | #endif | |
959 | } | |
960 | ||
961 | /***************************************************************************** | |
962 | * | |
963 | * sysfs attributes | |
964 | * | |
965 | *****************************************************************************/ | |
966 | ||
d3175167 | 967 | #ifdef CONFIG_IWLEGACY_DEBUG |
be663ab6 WYG |
968 | |
969 | /* | |
970 | * The following adds a new attribute to the sysfs representation | |
971 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) | |
972 | * used for controlling the debug level. | |
973 | * | |
974 | * See the level definitions in iwl for details. | |
975 | * | |
976 | * The debug_level being managed using sysfs below is a per device debug | |
977 | * level that is used instead of the global debug level if it (the per | |
978 | * device debug level) is set. | |
979 | */ | |
e2ebc833 | 980 | static ssize_t il4965_show_debug_level(struct device *d, |
be663ab6 WYG |
981 | struct device_attribute *attr, char *buf) |
982 | { | |
46bc8d4b SG |
983 | struct il_priv *il = dev_get_drvdata(d); |
984 | return sprintf(buf, "0x%08X\n", il_get_debug_level(il)); | |
be663ab6 | 985 | } |
e2ebc833 | 986 | static ssize_t il4965_store_debug_level(struct device *d, |
be663ab6 WYG |
987 | struct device_attribute *attr, |
988 | const char *buf, size_t count) | |
989 | { | |
46bc8d4b | 990 | struct il_priv *il = dev_get_drvdata(d); |
be663ab6 WYG |
991 | unsigned long val; |
992 | int ret; | |
993 | ||
994 | ret = strict_strtoul(buf, 0, &val); | |
995 | if (ret) | |
9406f797 | 996 | IL_ERR("%s is not in hex or decimal form.\n", buf); |
be663ab6 | 997 | else { |
46bc8d4b SG |
998 | il->debug_level = val; |
999 | if (il_alloc_traffic_mem(il)) | |
9406f797 | 1000 | IL_ERR( |
be663ab6 WYG |
1001 | "Not enough memory to generate traffic log\n"); |
1002 | } | |
1003 | return strnlen(buf, count); | |
1004 | } | |
1005 | ||
1006 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
e2ebc833 | 1007 | il4965_show_debug_level, il4965_store_debug_level); |
be663ab6 WYG |
1008 | |
1009 | ||
d3175167 | 1010 | #endif /* CONFIG_IWLEGACY_DEBUG */ |
be663ab6 WYG |
1011 | |
1012 | ||
e2ebc833 | 1013 | static ssize_t il4965_show_temperature(struct device *d, |
be663ab6 WYG |
1014 | struct device_attribute *attr, char *buf) |
1015 | { | |
46bc8d4b | 1016 | struct il_priv *il = dev_get_drvdata(d); |
be663ab6 | 1017 | |
46bc8d4b | 1018 | if (!il_is_alive(il)) |
be663ab6 WYG |
1019 | return -EAGAIN; |
1020 | ||
46bc8d4b | 1021 | return sprintf(buf, "%d\n", il->temperature); |
be663ab6 WYG |
1022 | } |
1023 | ||
e2ebc833 | 1024 | static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL); |
be663ab6 | 1025 | |
e2ebc833 | 1026 | static ssize_t il4965_show_tx_power(struct device *d, |
be663ab6 WYG |
1027 | struct device_attribute *attr, char *buf) |
1028 | { | |
46bc8d4b | 1029 | struct il_priv *il = dev_get_drvdata(d); |
be663ab6 | 1030 | |
46bc8d4b | 1031 | if (!il_is_ready_rf(il)) |
be663ab6 WYG |
1032 | return sprintf(buf, "off\n"); |
1033 | else | |
46bc8d4b | 1034 | return sprintf(buf, "%d\n", il->tx_power_user_lmt); |
be663ab6 WYG |
1035 | } |
1036 | ||
e2ebc833 | 1037 | static ssize_t il4965_store_tx_power(struct device *d, |
be663ab6 WYG |
1038 | struct device_attribute *attr, |
1039 | const char *buf, size_t count) | |
1040 | { | |
46bc8d4b | 1041 | struct il_priv *il = dev_get_drvdata(d); |
be663ab6 WYG |
1042 | unsigned long val; |
1043 | int ret; | |
1044 | ||
1045 | ret = strict_strtoul(buf, 10, &val); | |
1046 | if (ret) | |
9406f797 | 1047 | IL_INFO("%s is not in decimal form.\n", buf); |
be663ab6 | 1048 | else { |
46bc8d4b | 1049 | ret = il_set_tx_power(il, val, false); |
be663ab6 | 1050 | if (ret) |
9406f797 | 1051 | IL_ERR("failed setting tx power (0x%d).\n", |
be663ab6 WYG |
1052 | ret); |
1053 | else | |
1054 | ret = count; | |
1055 | } | |
1056 | return ret; | |
1057 | } | |
1058 | ||
1059 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, | |
e2ebc833 | 1060 | il4965_show_tx_power, il4965_store_tx_power); |
be663ab6 | 1061 | |
e2ebc833 | 1062 | static struct attribute *il_sysfs_entries[] = { |
be663ab6 WYG |
1063 | &dev_attr_temperature.attr, |
1064 | &dev_attr_tx_power.attr, | |
d3175167 | 1065 | #ifdef CONFIG_IWLEGACY_DEBUG |
be663ab6 WYG |
1066 | &dev_attr_debug_level.attr, |
1067 | #endif | |
1068 | NULL | |
1069 | }; | |
1070 | ||
e2ebc833 | 1071 | static struct attribute_group il_attribute_group = { |
be663ab6 | 1072 | .name = NULL, /* put in device directory */ |
e2ebc833 | 1073 | .attrs = il_sysfs_entries, |
be663ab6 WYG |
1074 | }; |
1075 | ||
1076 | /****************************************************************************** | |
1077 | * | |
1078 | * uCode download functions | |
1079 | * | |
1080 | ******************************************************************************/ | |
1081 | ||
46bc8d4b | 1082 | static void il4965_dealloc_ucode_pci(struct il_priv *il) |
be663ab6 | 1083 | { |
46bc8d4b SG |
1084 | il_free_fw_desc(il->pci_dev, &il->ucode_code); |
1085 | il_free_fw_desc(il->pci_dev, &il->ucode_data); | |
1086 | il_free_fw_desc(il->pci_dev, &il->ucode_data_backup); | |
1087 | il_free_fw_desc(il->pci_dev, &il->ucode_init); | |
1088 | il_free_fw_desc(il->pci_dev, &il->ucode_init_data); | |
1089 | il_free_fw_desc(il->pci_dev, &il->ucode_boot); | |
be663ab6 WYG |
1090 | } |
1091 | ||
46bc8d4b | 1092 | static void il4965_nic_start(struct il_priv *il) |
be663ab6 WYG |
1093 | { |
1094 | /* Remove all resets to allow NIC to operate */ | |
841b2cca | 1095 | _il_wr(il, CSR_RESET, 0); |
be663ab6 WYG |
1096 | } |
1097 | ||
e2ebc833 | 1098 | static void il4965_ucode_callback(const struct firmware *ucode_raw, |
be663ab6 | 1099 | void *context); |
46bc8d4b | 1100 | static int il4965_mac_setup_register(struct il_priv *il, |
be663ab6 WYG |
1101 | u32 max_probe_length); |
1102 | ||
46bc8d4b | 1103 | static int __must_check il4965_request_firmware(struct il_priv *il, bool first) |
be663ab6 | 1104 | { |
46bc8d4b | 1105 | const char *name_pre = il->cfg->fw_name_pre; |
be663ab6 WYG |
1106 | char tag[8]; |
1107 | ||
1108 | if (first) { | |
46bc8d4b SG |
1109 | il->fw_index = il->cfg->ucode_api_max; |
1110 | sprintf(tag, "%d", il->fw_index); | |
be663ab6 | 1111 | } else { |
46bc8d4b SG |
1112 | il->fw_index--; |
1113 | sprintf(tag, "%d", il->fw_index); | |
be663ab6 WYG |
1114 | } |
1115 | ||
46bc8d4b | 1116 | if (il->fw_index < il->cfg->ucode_api_min) { |
9406f797 | 1117 | IL_ERR("no suitable firmware found!\n"); |
be663ab6 WYG |
1118 | return -ENOENT; |
1119 | } | |
1120 | ||
46bc8d4b | 1121 | sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); |
be663ab6 | 1122 | |
58de00a4 | 1123 | D_INFO("attempting to load firmware '%s'\n", |
46bc8d4b | 1124 | il->firmware_name); |
be663ab6 | 1125 | |
46bc8d4b SG |
1126 | return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name, |
1127 | &il->pci_dev->dev, GFP_KERNEL, il, | |
e2ebc833 | 1128 | il4965_ucode_callback); |
be663ab6 WYG |
1129 | } |
1130 | ||
e2ebc833 | 1131 | struct il4965_firmware_pieces { |
be663ab6 WYG |
1132 | const void *inst, *data, *init, *init_data, *boot; |
1133 | size_t inst_size, data_size, init_size, init_data_size, boot_size; | |
1134 | }; | |
1135 | ||
46bc8d4b | 1136 | static int il4965_load_firmware(struct il_priv *il, |
be663ab6 | 1137 | const struct firmware *ucode_raw, |
e2ebc833 | 1138 | struct il4965_firmware_pieces *pieces) |
be663ab6 | 1139 | { |
e2ebc833 | 1140 | struct il_ucode_header *ucode = (void *)ucode_raw->data; |
be663ab6 WYG |
1141 | u32 api_ver, hdr_size; |
1142 | const u8 *src; | |
1143 | ||
46bc8d4b SG |
1144 | il->ucode_ver = le32_to_cpu(ucode->ver); |
1145 | api_ver = IL_UCODE_API(il->ucode_ver); | |
be663ab6 WYG |
1146 | |
1147 | switch (api_ver) { | |
1148 | default: | |
1149 | case 0: | |
1150 | case 1: | |
1151 | case 2: | |
1152 | hdr_size = 24; | |
1153 | if (ucode_raw->size < hdr_size) { | |
9406f797 | 1154 | IL_ERR("File size too small!\n"); |
be663ab6 WYG |
1155 | return -EINVAL; |
1156 | } | |
1157 | pieces->inst_size = le32_to_cpu(ucode->v1.inst_size); | |
1158 | pieces->data_size = le32_to_cpu(ucode->v1.data_size); | |
1159 | pieces->init_size = le32_to_cpu(ucode->v1.init_size); | |
1160 | pieces->init_data_size = | |
1161 | le32_to_cpu(ucode->v1.init_data_size); | |
1162 | pieces->boot_size = le32_to_cpu(ucode->v1.boot_size); | |
1163 | src = ucode->v1.data; | |
1164 | break; | |
1165 | } | |
1166 | ||
1167 | /* Verify size of file vs. image size info in file's header */ | |
1168 | if (ucode_raw->size != hdr_size + pieces->inst_size + | |
1169 | pieces->data_size + pieces->init_size + | |
1170 | pieces->init_data_size + pieces->boot_size) { | |
1171 | ||
9406f797 | 1172 | IL_ERR( |
be663ab6 WYG |
1173 | "uCode file size %d does not match expected size\n", |
1174 | (int)ucode_raw->size); | |
1175 | return -EINVAL; | |
1176 | } | |
1177 | ||
1178 | pieces->inst = src; | |
1179 | src += pieces->inst_size; | |
1180 | pieces->data = src; | |
1181 | src += pieces->data_size; | |
1182 | pieces->init = src; | |
1183 | src += pieces->init_size; | |
1184 | pieces->init_data = src; | |
1185 | src += pieces->init_data_size; | |
1186 | pieces->boot = src; | |
1187 | src += pieces->boot_size; | |
1188 | ||
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | /** | |
e2ebc833 | 1193 | * il4965_ucode_callback - callback when firmware was loaded |
be663ab6 WYG |
1194 | * |
1195 | * If loaded successfully, copies the firmware into buffers | |
1196 | * for the card to fetch (via DMA). | |
1197 | */ | |
1198 | static void | |
e2ebc833 | 1199 | il4965_ucode_callback(const struct firmware *ucode_raw, void *context) |
be663ab6 | 1200 | { |
46bc8d4b | 1201 | struct il_priv *il = context; |
e2ebc833 | 1202 | struct il_ucode_header *ucode; |
be663ab6 | 1203 | int err; |
e2ebc833 | 1204 | struct il4965_firmware_pieces pieces; |
46bc8d4b SG |
1205 | const unsigned int api_max = il->cfg->ucode_api_max; |
1206 | const unsigned int api_min = il->cfg->ucode_api_min; | |
be663ab6 WYG |
1207 | u32 api_ver; |
1208 | ||
1209 | u32 max_probe_length = 200; | |
1210 | u32 standard_phy_calibration_size = | |
e2ebc833 | 1211 | IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE; |
be663ab6 WYG |
1212 | |
1213 | memset(&pieces, 0, sizeof(pieces)); | |
1214 | ||
1215 | if (!ucode_raw) { | |
46bc8d4b | 1216 | if (il->fw_index <= il->cfg->ucode_api_max) |
9406f797 | 1217 | IL_ERR( |
be663ab6 | 1218 | "request for firmware file '%s' failed.\n", |
46bc8d4b | 1219 | il->firmware_name); |
be663ab6 WYG |
1220 | goto try_again; |
1221 | } | |
1222 | ||
58de00a4 | 1223 | D_INFO("Loaded firmware file '%s' (%zd bytes).\n", |
46bc8d4b | 1224 | il->firmware_name, ucode_raw->size); |
be663ab6 WYG |
1225 | |
1226 | /* Make sure that we got at least the API version number */ | |
1227 | if (ucode_raw->size < 4) { | |
9406f797 | 1228 | IL_ERR("File size way too small!\n"); |
be663ab6 WYG |
1229 | goto try_again; |
1230 | } | |
1231 | ||
1232 | /* Data from ucode file: header followed by uCode images */ | |
e2ebc833 | 1233 | ucode = (struct il_ucode_header *)ucode_raw->data; |
be663ab6 | 1234 | |
46bc8d4b | 1235 | err = il4965_load_firmware(il, ucode_raw, &pieces); |
be663ab6 WYG |
1236 | |
1237 | if (err) | |
1238 | goto try_again; | |
1239 | ||
46bc8d4b | 1240 | api_ver = IL_UCODE_API(il->ucode_ver); |
be663ab6 WYG |
1241 | |
1242 | /* | |
1243 | * api_ver should match the api version forming part of the | |
1244 | * firmware filename ... but we don't check for that and only rely | |
1245 | * on the API version read from firmware header from here on forward | |
1246 | */ | |
1247 | if (api_ver < api_min || api_ver > api_max) { | |
9406f797 | 1248 | IL_ERR( |
be663ab6 WYG |
1249 | "Driver unable to support your firmware API. " |
1250 | "Driver supports v%u, firmware is v%u.\n", | |
1251 | api_max, api_ver); | |
1252 | goto try_again; | |
1253 | } | |
1254 | ||
1255 | if (api_ver != api_max) | |
9406f797 | 1256 | IL_ERR( |
be663ab6 WYG |
1257 | "Firmware has old API version. Expected v%u, " |
1258 | "got v%u. New firmware can be obtained " | |
1259 | "from http://www.intellinuxwireless.org.\n", | |
1260 | api_max, api_ver); | |
1261 | ||
9406f797 | 1262 | IL_INFO("loaded firmware version %u.%u.%u.%u\n", |
46bc8d4b SG |
1263 | IL_UCODE_MAJOR(il->ucode_ver), |
1264 | IL_UCODE_MINOR(il->ucode_ver), | |
1265 | IL_UCODE_API(il->ucode_ver), | |
1266 | IL_UCODE_SERIAL(il->ucode_ver)); | |
be663ab6 | 1267 | |
46bc8d4b SG |
1268 | snprintf(il->hw->wiphy->fw_version, |
1269 | sizeof(il->hw->wiphy->fw_version), | |
be663ab6 | 1270 | "%u.%u.%u.%u", |
46bc8d4b SG |
1271 | IL_UCODE_MAJOR(il->ucode_ver), |
1272 | IL_UCODE_MINOR(il->ucode_ver), | |
1273 | IL_UCODE_API(il->ucode_ver), | |
1274 | IL_UCODE_SERIAL(il->ucode_ver)); | |
be663ab6 WYG |
1275 | |
1276 | /* | |
1277 | * For any of the failures below (before allocating pci memory) | |
1278 | * we will try to load a version with a smaller API -- maybe the | |
1279 | * user just got a corrupted version of the latest API. | |
1280 | */ | |
1281 | ||
58de00a4 | 1282 | D_INFO("f/w package hdr ucode version raw = 0x%x\n", |
46bc8d4b | 1283 | il->ucode_ver); |
58de00a4 | 1284 | D_INFO("f/w package hdr runtime inst size = %Zd\n", |
be663ab6 | 1285 | pieces.inst_size); |
58de00a4 | 1286 | D_INFO("f/w package hdr runtime data size = %Zd\n", |
be663ab6 | 1287 | pieces.data_size); |
58de00a4 | 1288 | D_INFO("f/w package hdr init inst size = %Zd\n", |
be663ab6 | 1289 | pieces.init_size); |
58de00a4 | 1290 | D_INFO("f/w package hdr init data size = %Zd\n", |
be663ab6 | 1291 | pieces.init_data_size); |
58de00a4 | 1292 | D_INFO("f/w package hdr boot inst size = %Zd\n", |
be663ab6 WYG |
1293 | pieces.boot_size); |
1294 | ||
1295 | /* Verify that uCode images will fit in card's SRAM */ | |
46bc8d4b | 1296 | if (pieces.inst_size > il->hw_params.max_inst_size) { |
9406f797 | 1297 | IL_ERR("uCode instr len %Zd too large to fit in\n", |
be663ab6 WYG |
1298 | pieces.inst_size); |
1299 | goto try_again; | |
1300 | } | |
1301 | ||
46bc8d4b | 1302 | if (pieces.data_size > il->hw_params.max_data_size) { |
9406f797 | 1303 | IL_ERR("uCode data len %Zd too large to fit in\n", |
be663ab6 WYG |
1304 | pieces.data_size); |
1305 | goto try_again; | |
1306 | } | |
1307 | ||
46bc8d4b | 1308 | if (pieces.init_size > il->hw_params.max_inst_size) { |
9406f797 | 1309 | IL_ERR("uCode init instr len %Zd too large to fit in\n", |
be663ab6 WYG |
1310 | pieces.init_size); |
1311 | goto try_again; | |
1312 | } | |
1313 | ||
46bc8d4b | 1314 | if (pieces.init_data_size > il->hw_params.max_data_size) { |
9406f797 | 1315 | IL_ERR("uCode init data len %Zd too large to fit in\n", |
be663ab6 WYG |
1316 | pieces.init_data_size); |
1317 | goto try_again; | |
1318 | } | |
1319 | ||
46bc8d4b | 1320 | if (pieces.boot_size > il->hw_params.max_bsm_size) { |
9406f797 | 1321 | IL_ERR("uCode boot instr len %Zd too large to fit in\n", |
be663ab6 WYG |
1322 | pieces.boot_size); |
1323 | goto try_again; | |
1324 | } | |
1325 | ||
1326 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1327 | ||
1328 | /* Runtime instructions and 2 copies of data: | |
1329 | * 1) unmodified from disk | |
1330 | * 2) backup cache for save/restore during power-downs */ | |
46bc8d4b SG |
1331 | il->ucode_code.len = pieces.inst_size; |
1332 | il_alloc_fw_desc(il->pci_dev, &il->ucode_code); | |
be663ab6 | 1333 | |
46bc8d4b SG |
1334 | il->ucode_data.len = pieces.data_size; |
1335 | il_alloc_fw_desc(il->pci_dev, &il->ucode_data); | |
be663ab6 | 1336 | |
46bc8d4b SG |
1337 | il->ucode_data_backup.len = pieces.data_size; |
1338 | il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup); | |
be663ab6 | 1339 | |
46bc8d4b SG |
1340 | if (!il->ucode_code.v_addr || !il->ucode_data.v_addr || |
1341 | !il->ucode_data_backup.v_addr) | |
be663ab6 WYG |
1342 | goto err_pci_alloc; |
1343 | ||
1344 | /* Initialization instructions and data */ | |
1345 | if (pieces.init_size && pieces.init_data_size) { | |
46bc8d4b SG |
1346 | il->ucode_init.len = pieces.init_size; |
1347 | il_alloc_fw_desc(il->pci_dev, &il->ucode_init); | |
be663ab6 | 1348 | |
46bc8d4b SG |
1349 | il->ucode_init_data.len = pieces.init_data_size; |
1350 | il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data); | |
be663ab6 | 1351 | |
46bc8d4b | 1352 | if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr) |
be663ab6 WYG |
1353 | goto err_pci_alloc; |
1354 | } | |
1355 | ||
1356 | /* Bootstrap (instructions only, no data) */ | |
1357 | if (pieces.boot_size) { | |
46bc8d4b SG |
1358 | il->ucode_boot.len = pieces.boot_size; |
1359 | il_alloc_fw_desc(il->pci_dev, &il->ucode_boot); | |
be663ab6 | 1360 | |
46bc8d4b | 1361 | if (!il->ucode_boot.v_addr) |
be663ab6 WYG |
1362 | goto err_pci_alloc; |
1363 | } | |
1364 | ||
1365 | /* Now that we can no longer fail, copy information */ | |
1366 | ||
46bc8d4b | 1367 | il->sta_key_max_num = STA_KEY_MAX_NUM; |
be663ab6 WYG |
1368 | |
1369 | /* Copy images into buffers for card's bus-master reads ... */ | |
1370 | ||
1371 | /* Runtime instructions (first block of data in file) */ | |
58de00a4 | 1372 | D_INFO("Copying (but not loading) uCode instr len %Zd\n", |
be663ab6 | 1373 | pieces.inst_size); |
46bc8d4b | 1374 | memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size); |
be663ab6 | 1375 | |
58de00a4 | 1376 | D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
46bc8d4b | 1377 | il->ucode_code.v_addr, (u32)il->ucode_code.p_addr); |
be663ab6 WYG |
1378 | |
1379 | /* | |
1380 | * Runtime data | |
e2ebc833 | 1381 | * NOTE: Copy into backup buffer will be done in il_up() |
be663ab6 | 1382 | */ |
58de00a4 | 1383 | D_INFO("Copying (but not loading) uCode data len %Zd\n", |
be663ab6 | 1384 | pieces.data_size); |
46bc8d4b SG |
1385 | memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size); |
1386 | memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size); | |
be663ab6 WYG |
1387 | |
1388 | /* Initialization instructions */ | |
1389 | if (pieces.init_size) { | |
58de00a4 | 1390 | D_INFO( |
be663ab6 WYG |
1391 | "Copying (but not loading) init instr len %Zd\n", |
1392 | pieces.init_size); | |
46bc8d4b | 1393 | memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size); |
be663ab6 WYG |
1394 | } |
1395 | ||
1396 | /* Initialization data */ | |
1397 | if (pieces.init_data_size) { | |
58de00a4 | 1398 | D_INFO( |
be663ab6 WYG |
1399 | "Copying (but not loading) init data len %Zd\n", |
1400 | pieces.init_data_size); | |
46bc8d4b | 1401 | memcpy(il->ucode_init_data.v_addr, pieces.init_data, |
be663ab6 WYG |
1402 | pieces.init_data_size); |
1403 | } | |
1404 | ||
1405 | /* Bootstrap instructions */ | |
58de00a4 | 1406 | D_INFO("Copying (but not loading) boot instr len %Zd\n", |
be663ab6 | 1407 | pieces.boot_size); |
46bc8d4b | 1408 | memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size); |
be663ab6 WYG |
1409 | |
1410 | /* | |
1411 | * figure out the offset of chain noise reset and gain commands | |
1412 | * base on the size of standard phy calibration commands table size | |
1413 | */ | |
46bc8d4b | 1414 | il->_4965.phy_calib_chain_noise_reset_cmd = |
be663ab6 | 1415 | standard_phy_calibration_size; |
46bc8d4b | 1416 | il->_4965.phy_calib_chain_noise_gain_cmd = |
be663ab6 WYG |
1417 | standard_phy_calibration_size + 1; |
1418 | ||
1419 | /************************************************** | |
1420 | * This is still part of probe() in a sense... | |
1421 | * | |
1422 | * 9. Setup and register with mac80211 and debugfs | |
1423 | **************************************************/ | |
46bc8d4b | 1424 | err = il4965_mac_setup_register(il, max_probe_length); |
be663ab6 WYG |
1425 | if (err) |
1426 | goto out_unbind; | |
1427 | ||
46bc8d4b | 1428 | err = il_dbgfs_register(il, DRV_NAME); |
be663ab6 | 1429 | if (err) |
9406f797 | 1430 | IL_ERR( |
be663ab6 WYG |
1431 | "failed to create debugfs files. Ignoring error: %d\n", err); |
1432 | ||
46bc8d4b | 1433 | err = sysfs_create_group(&il->pci_dev->dev.kobj, |
e2ebc833 | 1434 | &il_attribute_group); |
be663ab6 | 1435 | if (err) { |
9406f797 | 1436 | IL_ERR("failed to create sysfs device attributes\n"); |
be663ab6 WYG |
1437 | goto out_unbind; |
1438 | } | |
1439 | ||
1440 | /* We have our copies now, allow OS release its copies */ | |
1441 | release_firmware(ucode_raw); | |
46bc8d4b | 1442 | complete(&il->_4965.firmware_loading_complete); |
be663ab6 WYG |
1443 | return; |
1444 | ||
1445 | try_again: | |
1446 | /* try next, if any */ | |
46bc8d4b | 1447 | if (il4965_request_firmware(il, false)) |
be663ab6 WYG |
1448 | goto out_unbind; |
1449 | release_firmware(ucode_raw); | |
1450 | return; | |
1451 | ||
1452 | err_pci_alloc: | |
9406f797 | 1453 | IL_ERR("failed to allocate pci memory\n"); |
46bc8d4b | 1454 | il4965_dealloc_ucode_pci(il); |
be663ab6 | 1455 | out_unbind: |
46bc8d4b SG |
1456 | complete(&il->_4965.firmware_loading_complete); |
1457 | device_release_driver(&il->pci_dev->dev); | |
be663ab6 WYG |
1458 | release_firmware(ucode_raw); |
1459 | } | |
1460 | ||
1461 | static const char * const desc_lookup_text[] = { | |
1462 | "OK", | |
1463 | "FAIL", | |
1464 | "BAD_PARAM", | |
1465 | "BAD_CHECKSUM", | |
1466 | "NMI_INTERRUPT_WDG", | |
1467 | "SYSASSERT", | |
1468 | "FATAL_ERROR", | |
1469 | "BAD_COMMAND", | |
1470 | "HW_ERROR_TUNE_LOCK", | |
1471 | "HW_ERROR_TEMPERATURE", | |
1472 | "ILLEGAL_CHAN_FREQ", | |
1473 | "VCC_NOT_STABLE", | |
1474 | "FH_ERROR", | |
1475 | "NMI_INTERRUPT_HOST", | |
1476 | "NMI_INTERRUPT_ACTION_PT", | |
1477 | "NMI_INTERRUPT_UNKNOWN", | |
1478 | "UCODE_VERSION_MISMATCH", | |
1479 | "HW_ERROR_ABS_LOCK", | |
1480 | "HW_ERROR_CAL_LOCK_FAIL", | |
1481 | "NMI_INTERRUPT_INST_ACTION_PT", | |
1482 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
1483 | "NMI_TRM_HW_ER", | |
1484 | "NMI_INTERRUPT_TRM", | |
861d9c3f | 1485 | "NMI_INTERRUPT_BREAK_POINT", |
be663ab6 WYG |
1486 | "DEBUG_0", |
1487 | "DEBUG_1", | |
1488 | "DEBUG_2", | |
1489 | "DEBUG_3", | |
1490 | }; | |
1491 | ||
1492 | static struct { char *name; u8 num; } advanced_lookup[] = { | |
1493 | { "NMI_INTERRUPT_WDG", 0x34 }, | |
1494 | { "SYSASSERT", 0x35 }, | |
1495 | { "UCODE_VERSION_MISMATCH", 0x37 }, | |
1496 | { "BAD_COMMAND", 0x38 }, | |
1497 | { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, | |
1498 | { "FATAL_ERROR", 0x3D }, | |
1499 | { "NMI_TRM_HW_ERR", 0x46 }, | |
1500 | { "NMI_INTERRUPT_TRM", 0x4C }, | |
1501 | { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, | |
1502 | { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, | |
1503 | { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, | |
1504 | { "NMI_INTERRUPT_HOST", 0x66 }, | |
1505 | { "NMI_INTERRUPT_ACTION_PT", 0x7C }, | |
1506 | { "NMI_INTERRUPT_UNKNOWN", 0x84 }, | |
1507 | { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, | |
1508 | { "ADVANCED_SYSASSERT", 0 }, | |
1509 | }; | |
1510 | ||
e2ebc833 | 1511 | static const char *il4965_desc_lookup(u32 num) |
be663ab6 WYG |
1512 | { |
1513 | int i; | |
1514 | int max = ARRAY_SIZE(desc_lookup_text); | |
1515 | ||
1516 | if (num < max) | |
1517 | return desc_lookup_text[num]; | |
1518 | ||
1519 | max = ARRAY_SIZE(advanced_lookup) - 1; | |
1520 | for (i = 0; i < max; i++) { | |
1521 | if (advanced_lookup[i].num == num) | |
1522 | break; | |
1523 | } | |
1524 | return advanced_lookup[i].name; | |
1525 | } | |
1526 | ||
1527 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1528 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1529 | ||
46bc8d4b | 1530 | void il4965_dump_nic_error_log(struct il_priv *il) |
be663ab6 WYG |
1531 | { |
1532 | u32 data2, line; | |
1533 | u32 desc, time, count, base, data1; | |
1534 | u32 blink1, blink2, ilink1, ilink2; | |
1535 | u32 pc, hcmd; | |
1536 | ||
46bc8d4b SG |
1537 | if (il->ucode_type == UCODE_INIT) { |
1538 | base = le32_to_cpu(il->card_alive_init.error_event_table_ptr); | |
be663ab6 | 1539 | } else { |
46bc8d4b | 1540 | base = le32_to_cpu(il->card_alive.error_event_table_ptr); |
be663ab6 WYG |
1541 | } |
1542 | ||
46bc8d4b | 1543 | if (!il->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
9406f797 | 1544 | IL_ERR( |
be663ab6 | 1545 | "Not valid error log pointer 0x%08X for %s uCode\n", |
46bc8d4b | 1546 | base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT"); |
be663ab6 WYG |
1547 | return; |
1548 | } | |
1549 | ||
46bc8d4b | 1550 | count = il_read_targ_mem(il, base); |
be663ab6 WYG |
1551 | |
1552 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
9406f797 SG |
1553 | IL_ERR("Start IWL Error Log Dump:\n"); |
1554 | IL_ERR("Status: 0x%08lX, count: %d\n", | |
46bc8d4b SG |
1555 | il->status, count); |
1556 | } | |
1557 | ||
1558 | desc = il_read_targ_mem(il, base + 1 * sizeof(u32)); | |
1559 | il->isr_stats.err_code = desc; | |
1560 | pc = il_read_targ_mem(il, base + 2 * sizeof(u32)); | |
1561 | blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32)); | |
1562 | blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32)); | |
1563 | ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32)); | |
1564 | ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32)); | |
1565 | data1 = il_read_targ_mem(il, base + 7 * sizeof(u32)); | |
1566 | data2 = il_read_targ_mem(il, base + 8 * sizeof(u32)); | |
1567 | line = il_read_targ_mem(il, base + 9 * sizeof(u32)); | |
1568 | time = il_read_targ_mem(il, base + 11 * sizeof(u32)); | |
1569 | hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32)); | |
1570 | ||
9406f797 | 1571 | IL_ERR("Desc Time " |
be663ab6 | 1572 | "data1 data2 line\n"); |
9406f797 | 1573 | IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", |
e2ebc833 | 1574 | il4965_desc_lookup(desc), desc, time, data1, data2, line); |
9406f797 SG |
1575 | IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n"); |
1576 | IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", | |
be663ab6 WYG |
1577 | pc, blink1, blink2, ilink1, ilink2, hcmd); |
1578 | } | |
1579 | ||
46bc8d4b | 1580 | static void il4965_rf_kill_ct_config(struct il_priv *il) |
be663ab6 | 1581 | { |
e2ebc833 | 1582 | struct il_ct_kill_config cmd; |
be663ab6 WYG |
1583 | unsigned long flags; |
1584 | int ret = 0; | |
1585 | ||
46bc8d4b | 1586 | spin_lock_irqsave(&il->lock, flags); |
841b2cca | 1587 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, |
be663ab6 | 1588 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
46bc8d4b | 1589 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 WYG |
1590 | |
1591 | cmd.critical_temperature_R = | |
46bc8d4b | 1592 | cpu_to_le32(il->hw_params.ct_kill_threshold); |
be663ab6 | 1593 | |
46bc8d4b | 1594 | ret = il_send_cmd_pdu(il, REPLY_CT_KILL_CONFIG_CMD, |
be663ab6 WYG |
1595 | sizeof(cmd), &cmd); |
1596 | if (ret) | |
9406f797 | 1597 | IL_ERR("REPLY_CT_KILL_CONFIG_CMD failed\n"); |
be663ab6 | 1598 | else |
58de00a4 | 1599 | D_INFO("REPLY_CT_KILL_CONFIG_CMD " |
be663ab6 WYG |
1600 | "succeeded, " |
1601 | "critical temperature is %d\n", | |
46bc8d4b | 1602 | il->hw_params.ct_kill_threshold); |
be663ab6 WYG |
1603 | } |
1604 | ||
1605 | static const s8 default_queue_to_tx_fifo[] = { | |
e2ebc833 SG |
1606 | IL_TX_FIFO_VO, |
1607 | IL_TX_FIFO_VI, | |
1608 | IL_TX_FIFO_BE, | |
1609 | IL_TX_FIFO_BK, | |
d3175167 | 1610 | IL49_CMD_FIFO_NUM, |
e2ebc833 SG |
1611 | IL_TX_FIFO_UNUSED, |
1612 | IL_TX_FIFO_UNUSED, | |
be663ab6 WYG |
1613 | }; |
1614 | ||
46bc8d4b | 1615 | static int il4965_alive_notify(struct il_priv *il) |
be663ab6 WYG |
1616 | { |
1617 | u32 a; | |
1618 | unsigned long flags; | |
1619 | int i, chan; | |
1620 | u32 reg_val; | |
1621 | ||
46bc8d4b | 1622 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 WYG |
1623 | |
1624 | /* Clear 4965's internal Tx Scheduler data base */ | |
db54eb57 | 1625 | il->scd_base_addr = il_rd_prph(il, |
d3175167 SG |
1626 | IL49_SCD_SRAM_BASE_ADDR); |
1627 | a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET; | |
1628 | for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4) | |
46bc8d4b | 1629 | il_write_targ_mem(il, a, 0); |
d3175167 | 1630 | for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4) |
46bc8d4b SG |
1631 | il_write_targ_mem(il, a, 0); |
1632 | for (; a < il->scd_base_addr + | |
d3175167 | 1633 | IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num); a += 4) |
46bc8d4b | 1634 | il_write_targ_mem(il, a, 0); |
be663ab6 WYG |
1635 | |
1636 | /* Tel 4965 where to find Tx byte count tables */ | |
d3175167 | 1637 | il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, |
46bc8d4b | 1638 | il->scd_bc_tbls.dma >> 10); |
be663ab6 WYG |
1639 | |
1640 | /* Enable DMA channel */ | |
1641 | for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++) | |
0c1a94e2 | 1642 | il_wr(il, |
be663ab6 WYG |
1643 | FH_TCSR_CHNL_TX_CONFIG_REG(chan), |
1644 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
1645 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
1646 | ||
1647 | /* Update FH chicken bits */ | |
0c1a94e2 SG |
1648 | reg_val = il_rd(il, FH_TX_CHICKEN_BITS_REG); |
1649 | il_wr(il, FH_TX_CHICKEN_BITS_REG, | |
be663ab6 WYG |
1650 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
1651 | ||
1652 | /* Disable chain mode for all queues */ | |
d3175167 | 1653 | il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0); |
be663ab6 WYG |
1654 | |
1655 | /* Initialize each Tx queue (including the command queue) */ | |
46bc8d4b | 1656 | for (i = 0; i < il->hw_params.max_txq_num; i++) { |
be663ab6 WYG |
1657 | |
1658 | /* TFD circular buffer read/write indexes */ | |
d3175167 | 1659 | il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0); |
0c1a94e2 | 1660 | il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8)); |
be663ab6 WYG |
1661 | |
1662 | /* Max Tx Window size for Scheduler-ACK mode */ | |
46bc8d4b | 1663 | il_write_targ_mem(il, il->scd_base_addr + |
d3175167 | 1664 | IL49_SCD_CONTEXT_QUEUE_OFFSET(i), |
be663ab6 | 1665 | (SCD_WIN_SIZE << |
d3175167 SG |
1666 | IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & |
1667 | IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); | |
be663ab6 WYG |
1668 | |
1669 | /* Frame limit */ | |
46bc8d4b | 1670 | il_write_targ_mem(il, il->scd_base_addr + |
d3175167 | 1671 | IL49_SCD_CONTEXT_QUEUE_OFFSET(i) + |
be663ab6 WYG |
1672 | sizeof(u32), |
1673 | (SCD_FRAME_LIMIT << | |
d3175167 SG |
1674 | IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & |
1675 | IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); | |
be663ab6 WYG |
1676 | |
1677 | } | |
d3175167 | 1678 | il_wr_prph(il, IL49_SCD_INTERRUPT_MASK, |
46bc8d4b | 1679 | (1 << il->hw_params.max_txq_num) - 1); |
be663ab6 WYG |
1680 | |
1681 | /* Activate all Tx DMA/FIFO channels */ | |
46bc8d4b | 1682 | il4965_txq_set_sched(il, IL_MASK(0, 6)); |
be663ab6 | 1683 | |
46bc8d4b | 1684 | il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0); |
be663ab6 WYG |
1685 | |
1686 | /* make sure all queue are not stopped */ | |
46bc8d4b | 1687 | memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped)); |
be663ab6 | 1688 | for (i = 0; i < 4; i++) |
46bc8d4b | 1689 | atomic_set(&il->queue_stop_count[i], 0); |
be663ab6 WYG |
1690 | |
1691 | /* reset to 0 to enable all the queue first */ | |
46bc8d4b | 1692 | il->txq_ctx_active_msk = 0; |
be663ab6 WYG |
1693 | /* Map each Tx/cmd queue to its corresponding fifo */ |
1694 | BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7); | |
1695 | ||
1696 | for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) { | |
1697 | int ac = default_queue_to_tx_fifo[i]; | |
1698 | ||
46bc8d4b | 1699 | il_txq_ctx_activate(il, i); |
be663ab6 | 1700 | |
e2ebc833 | 1701 | if (ac == IL_TX_FIFO_UNUSED) |
be663ab6 WYG |
1702 | continue; |
1703 | ||
46bc8d4b | 1704 | il4965_tx_queue_set_status(il, &il->txq[i], ac, 0); |
be663ab6 WYG |
1705 | } |
1706 | ||
46bc8d4b | 1707 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 WYG |
1708 | |
1709 | return 0; | |
1710 | } | |
1711 | ||
1712 | /** | |
e2ebc833 | 1713 | * il4965_alive_start - called after REPLY_ALIVE notification received |
be663ab6 | 1714 | * from protocol/runtime uCode (initialization uCode's |
e2ebc833 | 1715 | * Alive gets handled by il_init_alive_start()). |
be663ab6 | 1716 | */ |
46bc8d4b | 1717 | static void il4965_alive_start(struct il_priv *il) |
be663ab6 WYG |
1718 | { |
1719 | int ret = 0; | |
7c2cde2e | 1720 | struct il_rxon_context *ctx = &il->ctx; |
be663ab6 | 1721 | |
58de00a4 | 1722 | D_INFO("Runtime Alive received.\n"); |
be663ab6 | 1723 | |
46bc8d4b | 1724 | if (il->card_alive.is_valid != UCODE_VALID_OK) { |
be663ab6 WYG |
1725 | /* We had an error bringing up the hardware, so take it |
1726 | * all the way back down so we can try again */ | |
58de00a4 | 1727 | D_INFO("Alive failed.\n"); |
be663ab6 WYG |
1728 | goto restart; |
1729 | } | |
1730 | ||
1731 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
1732 | * This is a paranoid check, because we would not have gotten the | |
1733 | * "runtime" alive if code weren't properly loaded. */ | |
46bc8d4b | 1734 | if (il4965_verify_ucode(il)) { |
be663ab6 WYG |
1735 | /* Runtime instruction load was bad; |
1736 | * take it all the way back down so we can try again */ | |
58de00a4 | 1737 | D_INFO("Bad runtime uCode load.\n"); |
be663ab6 WYG |
1738 | goto restart; |
1739 | } | |
1740 | ||
46bc8d4b | 1741 | ret = il4965_alive_notify(il); |
be663ab6 | 1742 | if (ret) { |
9406f797 | 1743 | IL_WARN( |
be663ab6 WYG |
1744 | "Could not complete ALIVE transition [ntf]: %d\n", ret); |
1745 | goto restart; | |
1746 | } | |
1747 | ||
1748 | ||
1749 | /* After the ALIVE response, we can send host commands to the uCode */ | |
46bc8d4b | 1750 | set_bit(STATUS_ALIVE, &il->status); |
be663ab6 WYG |
1751 | |
1752 | /* Enable watchdog to monitor the driver tx queues */ | |
46bc8d4b | 1753 | il_setup_watchdog(il); |
be663ab6 | 1754 | |
46bc8d4b | 1755 | if (il_is_rfkill(il)) |
be663ab6 WYG |
1756 | return; |
1757 | ||
46bc8d4b | 1758 | ieee80211_wake_queues(il->hw); |
be663ab6 | 1759 | |
46bc8d4b | 1760 | il->active_rate = IL_RATES_MASK; |
be663ab6 | 1761 | |
e2ebc833 SG |
1762 | if (il_is_associated_ctx(ctx)) { |
1763 | struct il_rxon_cmd *active_rxon = | |
1764 | (struct il_rxon_cmd *)&ctx->active; | |
be663ab6 WYG |
1765 | /* apply any changes in staging */ |
1766 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
1767 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
1768 | } else { | |
e2ebc833 | 1769 | struct il_rxon_context *tmp; |
be663ab6 | 1770 | /* Initialize our rx_config data */ |
46bc8d4b SG |
1771 | for_each_context(il, tmp) |
1772 | il_connection_init_rx_config(il, tmp); | |
be663ab6 | 1773 | |
46bc8d4b SG |
1774 | if (il->cfg->ops->hcmd->set_rxon_chain) |
1775 | il->cfg->ops->hcmd->set_rxon_chain(il, ctx); | |
be663ab6 WYG |
1776 | } |
1777 | ||
1778 | /* Configure bluetooth coexistence if enabled */ | |
46bc8d4b | 1779 | il_send_bt_config(il); |
be663ab6 | 1780 | |
46bc8d4b | 1781 | il4965_reset_run_time_calib(il); |
be663ab6 | 1782 | |
46bc8d4b | 1783 | set_bit(STATUS_READY, &il->status); |
be663ab6 WYG |
1784 | |
1785 | /* Configure the adapter for unassociated operation */ | |
46bc8d4b | 1786 | il_commit_rxon(il, ctx); |
be663ab6 WYG |
1787 | |
1788 | /* At this point, the NIC is initialized and operational */ | |
46bc8d4b | 1789 | il4965_rf_kill_ct_config(il); |
be663ab6 | 1790 | |
58de00a4 | 1791 | D_INFO("ALIVE processing complete.\n"); |
46bc8d4b | 1792 | wake_up(&il->wait_command_queue); |
be663ab6 | 1793 | |
46bc8d4b | 1794 | il_power_update_mode(il, true); |
58de00a4 | 1795 | D_INFO("Updated power mode\n"); |
be663ab6 WYG |
1796 | |
1797 | return; | |
1798 | ||
1799 | restart: | |
46bc8d4b | 1800 | queue_work(il->workqueue, &il->restart); |
be663ab6 WYG |
1801 | } |
1802 | ||
46bc8d4b | 1803 | static void il4965_cancel_deferred_work(struct il_priv *il); |
be663ab6 | 1804 | |
46bc8d4b | 1805 | static void __il4965_down(struct il_priv *il) |
be663ab6 WYG |
1806 | { |
1807 | unsigned long flags; | |
ab42b404 | 1808 | int exit_pending; |
be663ab6 | 1809 | |
58de00a4 | 1810 | D_INFO(DRV_NAME " is going down\n"); |
be663ab6 | 1811 | |
46bc8d4b | 1812 | il_scan_cancel_timeout(il, 200); |
be663ab6 | 1813 | |
46bc8d4b | 1814 | exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &il->status); |
be663ab6 WYG |
1815 | |
1816 | /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set | |
1817 | * to prevent rearm timer */ | |
46bc8d4b | 1818 | del_timer_sync(&il->watchdog); |
be663ab6 | 1819 | |
46bc8d4b SG |
1820 | il_clear_ucode_stations(il, NULL); |
1821 | il_dealloc_bcast_stations(il); | |
1822 | il_clear_driver_stations(il); | |
be663ab6 WYG |
1823 | |
1824 | /* Unblock any waiting calls */ | |
46bc8d4b | 1825 | wake_up_all(&il->wait_command_queue); |
be663ab6 WYG |
1826 | |
1827 | /* Wipe out the EXIT_PENDING status bit if we are not actually | |
1828 | * exiting the module */ | |
1829 | if (!exit_pending) | |
46bc8d4b | 1830 | clear_bit(STATUS_EXIT_PENDING, &il->status); |
be663ab6 WYG |
1831 | |
1832 | /* stop and reset the on-board processor */ | |
841b2cca | 1833 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
be663ab6 WYG |
1834 | |
1835 | /* tell the device to stop sending interrupts */ | |
46bc8d4b SG |
1836 | spin_lock_irqsave(&il->lock, flags); |
1837 | il_disable_interrupts(il); | |
1838 | spin_unlock_irqrestore(&il->lock, flags); | |
1839 | il4965_synchronize_irq(il); | |
be663ab6 | 1840 | |
46bc8d4b SG |
1841 | if (il->mac80211_registered) |
1842 | ieee80211_stop_queues(il->hw); | |
be663ab6 | 1843 | |
e2ebc833 | 1844 | /* If we have not previously called il_init() then |
be663ab6 | 1845 | * clear all bits but the RF Kill bit and return */ |
46bc8d4b SG |
1846 | if (!il_is_init(il)) { |
1847 | il->status = test_bit(STATUS_RF_KILL_HW, &il->status) << | |
be663ab6 | 1848 | STATUS_RF_KILL_HW | |
46bc8d4b | 1849 | test_bit(STATUS_GEO_CONFIGURED, &il->status) << |
be663ab6 | 1850 | STATUS_GEO_CONFIGURED | |
46bc8d4b | 1851 | test_bit(STATUS_EXIT_PENDING, &il->status) << |
be663ab6 WYG |
1852 | STATUS_EXIT_PENDING; |
1853 | goto exit; | |
1854 | } | |
1855 | ||
1856 | /* ...otherwise clear out all the status bits but the RF Kill | |
1857 | * bit and continue taking the NIC down. */ | |
46bc8d4b | 1858 | il->status &= test_bit(STATUS_RF_KILL_HW, &il->status) << |
be663ab6 | 1859 | STATUS_RF_KILL_HW | |
46bc8d4b | 1860 | test_bit(STATUS_GEO_CONFIGURED, &il->status) << |
be663ab6 | 1861 | STATUS_GEO_CONFIGURED | |
46bc8d4b | 1862 | test_bit(STATUS_FW_ERROR, &il->status) << |
be663ab6 | 1863 | STATUS_FW_ERROR | |
46bc8d4b | 1864 | test_bit(STATUS_EXIT_PENDING, &il->status) << |
be663ab6 WYG |
1865 | STATUS_EXIT_PENDING; |
1866 | ||
46bc8d4b SG |
1867 | il4965_txq_ctx_stop(il); |
1868 | il4965_rxq_stop(il); | |
be663ab6 WYG |
1869 | |
1870 | /* Power-down device's busmaster DMA clocks */ | |
db54eb57 | 1871 | il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
be663ab6 WYG |
1872 | udelay(5); |
1873 | ||
1874 | /* Make sure (redundant) we've released our request to stay awake */ | |
46bc8d4b | 1875 | il_clear_bit(il, CSR_GP_CNTRL, |
be663ab6 WYG |
1876 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
1877 | ||
1878 | /* Stop the device, and put it in low power state */ | |
46bc8d4b | 1879 | il_apm_stop(il); |
be663ab6 WYG |
1880 | |
1881 | exit: | |
46bc8d4b | 1882 | memset(&il->card_alive, 0, sizeof(struct il_alive_resp)); |
be663ab6 | 1883 | |
46bc8d4b SG |
1884 | dev_kfree_skb(il->beacon_skb); |
1885 | il->beacon_skb = NULL; | |
be663ab6 WYG |
1886 | |
1887 | /* clear out any free frames */ | |
46bc8d4b | 1888 | il4965_clear_free_frames(il); |
be663ab6 WYG |
1889 | } |
1890 | ||
46bc8d4b | 1891 | static void il4965_down(struct il_priv *il) |
be663ab6 | 1892 | { |
46bc8d4b SG |
1893 | mutex_lock(&il->mutex); |
1894 | __il4965_down(il); | |
1895 | mutex_unlock(&il->mutex); | |
be663ab6 | 1896 | |
46bc8d4b | 1897 | il4965_cancel_deferred_work(il); |
be663ab6 WYG |
1898 | } |
1899 | ||
1900 | #define HW_READY_TIMEOUT (50) | |
1901 | ||
46bc8d4b | 1902 | static int il4965_set_hw_ready(struct il_priv *il) |
be663ab6 WYG |
1903 | { |
1904 | int ret = 0; | |
1905 | ||
46bc8d4b | 1906 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, |
be663ab6 WYG |
1907 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
1908 | ||
1909 | /* See if we got it */ | |
142b343f | 1910 | ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, |
be663ab6 WYG |
1911 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, |
1912 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
1913 | HW_READY_TIMEOUT); | |
1914 | if (ret != -ETIMEDOUT) | |
46bc8d4b | 1915 | il->hw_ready = true; |
be663ab6 | 1916 | else |
46bc8d4b | 1917 | il->hw_ready = false; |
be663ab6 | 1918 | |
58de00a4 | 1919 | D_INFO("hardware %s\n", |
46bc8d4b | 1920 | (il->hw_ready == 1) ? "ready" : "not ready"); |
be663ab6 WYG |
1921 | return ret; |
1922 | } | |
1923 | ||
46bc8d4b | 1924 | static int il4965_prepare_card_hw(struct il_priv *il) |
be663ab6 WYG |
1925 | { |
1926 | int ret = 0; | |
1927 | ||
58de00a4 | 1928 | D_INFO("il4965_prepare_card_hw enter\n"); |
be663ab6 | 1929 | |
46bc8d4b SG |
1930 | ret = il4965_set_hw_ready(il); |
1931 | if (il->hw_ready) | |
be663ab6 WYG |
1932 | return ret; |
1933 | ||
1934 | /* If HW is not ready, prepare the conditions to check again */ | |
46bc8d4b | 1935 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, |
be663ab6 WYG |
1936 | CSR_HW_IF_CONFIG_REG_PREPARE); |
1937 | ||
142b343f | 1938 | ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, |
be663ab6 WYG |
1939 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, |
1940 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
1941 | ||
1942 | /* HW should be ready by now, check again. */ | |
1943 | if (ret != -ETIMEDOUT) | |
46bc8d4b | 1944 | il4965_set_hw_ready(il); |
be663ab6 WYG |
1945 | |
1946 | return ret; | |
1947 | } | |
1948 | ||
1949 | #define MAX_HW_RESTARTS 5 | |
1950 | ||
46bc8d4b | 1951 | static int __il4965_up(struct il_priv *il) |
be663ab6 | 1952 | { |
e2ebc833 | 1953 | struct il_rxon_context *ctx; |
be663ab6 WYG |
1954 | int i; |
1955 | int ret; | |
1956 | ||
46bc8d4b | 1957 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) { |
9406f797 | 1958 | IL_WARN("Exit pending; will not bring the NIC up\n"); |
be663ab6 WYG |
1959 | return -EIO; |
1960 | } | |
1961 | ||
46bc8d4b | 1962 | if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) { |
9406f797 | 1963 | IL_ERR("ucode not available for device bringup\n"); |
be663ab6 WYG |
1964 | return -EIO; |
1965 | } | |
1966 | ||
46bc8d4b SG |
1967 | for_each_context(il, ctx) { |
1968 | ret = il4965_alloc_bcast_station(il, ctx); | |
be663ab6 | 1969 | if (ret) { |
46bc8d4b | 1970 | il_dealloc_bcast_stations(il); |
be663ab6 WYG |
1971 | return ret; |
1972 | } | |
1973 | } | |
1974 | ||
46bc8d4b | 1975 | il4965_prepare_card_hw(il); |
be663ab6 | 1976 | |
46bc8d4b | 1977 | if (!il->hw_ready) { |
9406f797 | 1978 | IL_WARN("Exit HW not ready\n"); |
be663ab6 WYG |
1979 | return -EIO; |
1980 | } | |
1981 | ||
1982 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
841b2cca | 1983 | if (_il_rd(il, |
be663ab6 | 1984 | CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
46bc8d4b | 1985 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
be663ab6 | 1986 | else |
46bc8d4b | 1987 | set_bit(STATUS_RF_KILL_HW, &il->status); |
be663ab6 | 1988 | |
46bc8d4b SG |
1989 | if (il_is_rfkill(il)) { |
1990 | wiphy_rfkill_set_hw_state(il->hw->wiphy, true); | |
be663ab6 | 1991 | |
46bc8d4b | 1992 | il_enable_interrupts(il); |
9406f797 | 1993 | IL_WARN("Radio disabled by HW RF Kill switch\n"); |
be663ab6 WYG |
1994 | return 0; |
1995 | } | |
1996 | ||
841b2cca | 1997 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
be663ab6 | 1998 | |
e2ebc833 | 1999 | /* must be initialised before il_hw_nic_init */ |
46bc8d4b | 2000 | il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM; |
be663ab6 | 2001 | |
46bc8d4b | 2002 | ret = il4965_hw_nic_init(il); |
be663ab6 | 2003 | if (ret) { |
9406f797 | 2004 | IL_ERR("Unable to init nic\n"); |
be663ab6 WYG |
2005 | return ret; |
2006 | } | |
2007 | ||
2008 | /* make sure rfkill handshake bits are cleared */ | |
841b2cca SG |
2009 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2010 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, | |
be663ab6 WYG |
2011 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2012 | ||
2013 | /* clear (again), then enable host interrupts */ | |
841b2cca | 2014 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
46bc8d4b | 2015 | il_enable_interrupts(il); |
be663ab6 WYG |
2016 | |
2017 | /* really make sure rfkill handshake bits are cleared */ | |
841b2cca SG |
2018 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2019 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
be663ab6 WYG |
2020 | |
2021 | /* Copy original ucode data image from disk into backup cache. | |
2022 | * This will be used to initialize the on-board processor's | |
2023 | * data SRAM for a clean start when the runtime program first loads. */ | |
46bc8d4b SG |
2024 | memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr, |
2025 | il->ucode_data.len); | |
be663ab6 WYG |
2026 | |
2027 | for (i = 0; i < MAX_HW_RESTARTS; i++) { | |
2028 | ||
2029 | /* load bootstrap state machine, | |
2030 | * load bootstrap program into processor's memory, | |
2031 | * prepare to load the "initialize" uCode */ | |
46bc8d4b | 2032 | ret = il->cfg->ops->lib->load_ucode(il); |
be663ab6 WYG |
2033 | |
2034 | if (ret) { | |
9406f797 | 2035 | IL_ERR("Unable to set up bootstrap uCode: %d\n", |
be663ab6 WYG |
2036 | ret); |
2037 | continue; | |
2038 | } | |
2039 | ||
2040 | /* start card; "initialize" will load runtime ucode */ | |
46bc8d4b | 2041 | il4965_nic_start(il); |
be663ab6 | 2042 | |
58de00a4 | 2043 | D_INFO(DRV_NAME " is coming up\n"); |
be663ab6 WYG |
2044 | |
2045 | return 0; | |
2046 | } | |
2047 | ||
46bc8d4b SG |
2048 | set_bit(STATUS_EXIT_PENDING, &il->status); |
2049 | __il4965_down(il); | |
2050 | clear_bit(STATUS_EXIT_PENDING, &il->status); | |
be663ab6 WYG |
2051 | |
2052 | /* tried to restart and config the device for as long as our | |
2053 | * patience could withstand */ | |
9406f797 | 2054 | IL_ERR("Unable to initialize device after %d attempts.\n", i); |
be663ab6 WYG |
2055 | return -EIO; |
2056 | } | |
2057 | ||
2058 | ||
2059 | /***************************************************************************** | |
2060 | * | |
2061 | * Workqueue callbacks | |
2062 | * | |
2063 | *****************************************************************************/ | |
2064 | ||
e2ebc833 | 2065 | static void il4965_bg_init_alive_start(struct work_struct *data) |
be663ab6 | 2066 | { |
46bc8d4b | 2067 | struct il_priv *il = |
e2ebc833 | 2068 | container_of(data, struct il_priv, init_alive_start.work); |
be663ab6 | 2069 | |
46bc8d4b SG |
2070 | mutex_lock(&il->mutex); |
2071 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) | |
28a6e577 | 2072 | goto out; |
be663ab6 | 2073 | |
46bc8d4b | 2074 | il->cfg->ops->lib->init_alive_start(il); |
28a6e577 | 2075 | out: |
46bc8d4b | 2076 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
2077 | } |
2078 | ||
e2ebc833 | 2079 | static void il4965_bg_alive_start(struct work_struct *data) |
be663ab6 | 2080 | { |
46bc8d4b | 2081 | struct il_priv *il = |
e2ebc833 | 2082 | container_of(data, struct il_priv, alive_start.work); |
be663ab6 | 2083 | |
46bc8d4b SG |
2084 | mutex_lock(&il->mutex); |
2085 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) | |
28a6e577 | 2086 | goto out; |
be663ab6 | 2087 | |
46bc8d4b | 2088 | il4965_alive_start(il); |
28a6e577 | 2089 | out: |
46bc8d4b | 2090 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
2091 | } |
2092 | ||
e2ebc833 | 2093 | static void il4965_bg_run_time_calib_work(struct work_struct *work) |
be663ab6 | 2094 | { |
46bc8d4b | 2095 | struct il_priv *il = container_of(work, struct il_priv, |
be663ab6 WYG |
2096 | run_time_calib_work); |
2097 | ||
46bc8d4b | 2098 | mutex_lock(&il->mutex); |
be663ab6 | 2099 | |
46bc8d4b SG |
2100 | if (test_bit(STATUS_EXIT_PENDING, &il->status) || |
2101 | test_bit(STATUS_SCANNING, &il->status)) { | |
2102 | mutex_unlock(&il->mutex); | |
be663ab6 WYG |
2103 | return; |
2104 | } | |
2105 | ||
46bc8d4b SG |
2106 | if (il->start_calib) { |
2107 | il4965_chain_noise_calibration(il, | |
2108 | (void *)&il->_4965.statistics); | |
2109 | il4965_sensitivity_calibration(il, | |
2110 | (void *)&il->_4965.statistics); | |
be663ab6 WYG |
2111 | } |
2112 | ||
46bc8d4b | 2113 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
2114 | } |
2115 | ||
e2ebc833 | 2116 | static void il4965_bg_restart(struct work_struct *data) |
be663ab6 | 2117 | { |
46bc8d4b | 2118 | struct il_priv *il = container_of(data, struct il_priv, restart); |
be663ab6 | 2119 | |
46bc8d4b | 2120 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
2121 | return; |
2122 | ||
46bc8d4b | 2123 | if (test_and_clear_bit(STATUS_FW_ERROR, &il->status)) { |
e2ebc833 | 2124 | struct il_rxon_context *ctx; |
be663ab6 | 2125 | |
46bc8d4b SG |
2126 | mutex_lock(&il->mutex); |
2127 | for_each_context(il, ctx) | |
be663ab6 | 2128 | ctx->vif = NULL; |
46bc8d4b | 2129 | il->is_open = 0; |
be663ab6 | 2130 | |
46bc8d4b | 2131 | __il4965_down(il); |
be663ab6 | 2132 | |
46bc8d4b SG |
2133 | mutex_unlock(&il->mutex); |
2134 | il4965_cancel_deferred_work(il); | |
2135 | ieee80211_restart_hw(il->hw); | |
be663ab6 | 2136 | } else { |
46bc8d4b | 2137 | il4965_down(il); |
be663ab6 | 2138 | |
46bc8d4b SG |
2139 | mutex_lock(&il->mutex); |
2140 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) { | |
2141 | mutex_unlock(&il->mutex); | |
be663ab6 | 2142 | return; |
28a6e577 | 2143 | } |
be663ab6 | 2144 | |
46bc8d4b SG |
2145 | __il4965_up(il); |
2146 | mutex_unlock(&il->mutex); | |
be663ab6 WYG |
2147 | } |
2148 | } | |
2149 | ||
e2ebc833 | 2150 | static void il4965_bg_rx_replenish(struct work_struct *data) |
be663ab6 | 2151 | { |
46bc8d4b | 2152 | struct il_priv *il = |
e2ebc833 | 2153 | container_of(data, struct il_priv, rx_replenish); |
be663ab6 | 2154 | |
46bc8d4b | 2155 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
2156 | return; |
2157 | ||
46bc8d4b SG |
2158 | mutex_lock(&il->mutex); |
2159 | il4965_rx_replenish(il); | |
2160 | mutex_unlock(&il->mutex); | |
be663ab6 WYG |
2161 | } |
2162 | ||
2163 | /***************************************************************************** | |
2164 | * | |
2165 | * mac80211 entry point functions | |
2166 | * | |
2167 | *****************************************************************************/ | |
2168 | ||
2169 | #define UCODE_READY_TIMEOUT (4 * HZ) | |
2170 | ||
2171 | /* | |
2172 | * Not a mac80211 entry point function, but it fits in with all the | |
2173 | * other mac80211 functions grouped here. | |
2174 | */ | |
46bc8d4b | 2175 | static int il4965_mac_setup_register(struct il_priv *il, |
be663ab6 WYG |
2176 | u32 max_probe_length) |
2177 | { | |
2178 | int ret; | |
46bc8d4b | 2179 | struct ieee80211_hw *hw = il->hw; |
e2ebc833 | 2180 | struct il_rxon_context *ctx; |
be663ab6 WYG |
2181 | |
2182 | hw->rate_control_algorithm = "iwl-4965-rs"; | |
2183 | ||
2184 | /* Tell mac80211 our characteristics */ | |
2185 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
2186 | IEEE80211_HW_AMPDU_AGGREGATION | | |
2187 | IEEE80211_HW_NEED_DTIM_PERIOD | | |
2188 | IEEE80211_HW_SPECTRUM_MGMT | | |
2189 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
2190 | ||
46bc8d4b | 2191 | if (il->cfg->sku & IL_SKU_N) |
be663ab6 WYG |
2192 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | |
2193 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
2194 | ||
e2ebc833 SG |
2195 | hw->sta_data_size = sizeof(struct il_station_priv); |
2196 | hw->vif_data_size = sizeof(struct il_vif_priv); | |
be663ab6 | 2197 | |
46bc8d4b | 2198 | for_each_context(il, ctx) { |
be663ab6 WYG |
2199 | hw->wiphy->interface_modes |= ctx->interface_modes; |
2200 | hw->wiphy->interface_modes |= ctx->exclusive_interface_modes; | |
2201 | } | |
2202 | ||
2203 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | | |
2204 | WIPHY_FLAG_DISABLE_BEACON_HINTS; | |
2205 | ||
2206 | /* | |
2207 | * For now, disable PS by default because it affects | |
2208 | * RX performance significantly. | |
2209 | */ | |
2210 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
2211 | ||
2212 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; | |
2213 | /* we create the 802.11 header and a zero-length SSID element */ | |
2214 | hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2; | |
2215 | ||
2216 | /* Default value; 4 EDCA QOS priorities */ | |
2217 | hw->queues = 4; | |
2218 | ||
e2ebc833 | 2219 | hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL; |
be663ab6 | 2220 | |
46bc8d4b SG |
2221 | if (il->bands[IEEE80211_BAND_2GHZ].n_channels) |
2222 | il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
2223 | &il->bands[IEEE80211_BAND_2GHZ]; | |
2224 | if (il->bands[IEEE80211_BAND_5GHZ].n_channels) | |
2225 | il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
2226 | &il->bands[IEEE80211_BAND_5GHZ]; | |
be663ab6 | 2227 | |
46bc8d4b | 2228 | il_leds_init(il); |
be663ab6 | 2229 | |
46bc8d4b | 2230 | ret = ieee80211_register_hw(il->hw); |
be663ab6 | 2231 | if (ret) { |
9406f797 | 2232 | IL_ERR("Failed to register hw (error %d)\n", ret); |
be663ab6 WYG |
2233 | return ret; |
2234 | } | |
46bc8d4b | 2235 | il->mac80211_registered = 1; |
be663ab6 WYG |
2236 | |
2237 | return 0; | |
2238 | } | |
2239 | ||
2240 | ||
e2ebc833 | 2241 | int il4965_mac_start(struct ieee80211_hw *hw) |
be663ab6 | 2242 | { |
46bc8d4b | 2243 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
2244 | int ret; |
2245 | ||
58de00a4 | 2246 | D_MAC80211("enter\n"); |
be663ab6 WYG |
2247 | |
2248 | /* we should be verifying the device is ready to be opened */ | |
46bc8d4b SG |
2249 | mutex_lock(&il->mutex); |
2250 | ret = __il4965_up(il); | |
2251 | mutex_unlock(&il->mutex); | |
be663ab6 WYG |
2252 | |
2253 | if (ret) | |
2254 | return ret; | |
2255 | ||
46bc8d4b | 2256 | if (il_is_rfkill(il)) |
be663ab6 WYG |
2257 | goto out; |
2258 | ||
58de00a4 | 2259 | D_INFO("Start UP work done.\n"); |
be663ab6 WYG |
2260 | |
2261 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from | |
2262 | * mac80211 will not be run successfully. */ | |
46bc8d4b SG |
2263 | ret = wait_event_timeout(il->wait_command_queue, |
2264 | test_bit(STATUS_READY, &il->status), | |
be663ab6 WYG |
2265 | UCODE_READY_TIMEOUT); |
2266 | if (!ret) { | |
46bc8d4b | 2267 | if (!test_bit(STATUS_READY, &il->status)) { |
9406f797 | 2268 | IL_ERR("START_ALIVE timeout after %dms.\n", |
be663ab6 WYG |
2269 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
2270 | return -ETIMEDOUT; | |
2271 | } | |
2272 | } | |
2273 | ||
46bc8d4b | 2274 | il4965_led_enable(il); |
be663ab6 WYG |
2275 | |
2276 | out: | |
46bc8d4b | 2277 | il->is_open = 1; |
58de00a4 | 2278 | D_MAC80211("leave\n"); |
be663ab6 WYG |
2279 | return 0; |
2280 | } | |
2281 | ||
e2ebc833 | 2282 | void il4965_mac_stop(struct ieee80211_hw *hw) |
be663ab6 | 2283 | { |
46bc8d4b | 2284 | struct il_priv *il = hw->priv; |
be663ab6 | 2285 | |
58de00a4 | 2286 | D_MAC80211("enter\n"); |
be663ab6 | 2287 | |
46bc8d4b | 2288 | if (!il->is_open) |
be663ab6 WYG |
2289 | return; |
2290 | ||
46bc8d4b | 2291 | il->is_open = 0; |
be663ab6 | 2292 | |
46bc8d4b | 2293 | il4965_down(il); |
be663ab6 | 2294 | |
46bc8d4b | 2295 | flush_workqueue(il->workqueue); |
be663ab6 | 2296 | |
a078a1fd SG |
2297 | /* User space software may expect getting rfkill changes |
2298 | * even if interface is down */ | |
841b2cca | 2299 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
46bc8d4b | 2300 | il_enable_rfkill_int(il); |
be663ab6 | 2301 | |
58de00a4 | 2302 | D_MAC80211("leave\n"); |
be663ab6 WYG |
2303 | } |
2304 | ||
e2ebc833 | 2305 | void il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
be663ab6 | 2306 | { |
46bc8d4b | 2307 | struct il_priv *il = hw->priv; |
be663ab6 | 2308 | |
58de00a4 | 2309 | D_MACDUMP("enter\n"); |
be663ab6 | 2310 | |
58de00a4 | 2311 | D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
be663ab6 WYG |
2312 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
2313 | ||
46bc8d4b | 2314 | if (il4965_tx_skb(il, skb)) |
be663ab6 WYG |
2315 | dev_kfree_skb_any(skb); |
2316 | ||
58de00a4 | 2317 | D_MACDUMP("leave\n"); |
be663ab6 WYG |
2318 | } |
2319 | ||
e2ebc833 | 2320 | void il4965_mac_update_tkip_key(struct ieee80211_hw *hw, |
be663ab6 WYG |
2321 | struct ieee80211_vif *vif, |
2322 | struct ieee80211_key_conf *keyconf, | |
2323 | struct ieee80211_sta *sta, | |
2324 | u32 iv32, u16 *phase1key) | |
2325 | { | |
46bc8d4b | 2326 | struct il_priv *il = hw->priv; |
e2ebc833 | 2327 | struct il_vif_priv *vif_priv = (void *)vif->drv_priv; |
be663ab6 | 2328 | |
58de00a4 | 2329 | D_MAC80211("enter\n"); |
be663ab6 | 2330 | |
46bc8d4b | 2331 | il4965_update_tkip_key(il, vif_priv->ctx, keyconf, sta, |
be663ab6 WYG |
2332 | iv32, phase1key); |
2333 | ||
58de00a4 | 2334 | D_MAC80211("leave\n"); |
be663ab6 WYG |
2335 | } |
2336 | ||
e2ebc833 | 2337 | int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
be663ab6 WYG |
2338 | struct ieee80211_vif *vif, struct ieee80211_sta *sta, |
2339 | struct ieee80211_key_conf *key) | |
2340 | { | |
46bc8d4b | 2341 | struct il_priv *il = hw->priv; |
e2ebc833 SG |
2342 | struct il_vif_priv *vif_priv = (void *)vif->drv_priv; |
2343 | struct il_rxon_context *ctx = vif_priv->ctx; | |
be663ab6 WYG |
2344 | int ret; |
2345 | u8 sta_id; | |
2346 | bool is_default_wep_key = false; | |
2347 | ||
58de00a4 | 2348 | D_MAC80211("enter\n"); |
be663ab6 | 2349 | |
46bc8d4b | 2350 | if (il->cfg->mod_params->sw_crypto) { |
58de00a4 | 2351 | D_MAC80211("leave - hwcrypto disabled\n"); |
be663ab6 WYG |
2352 | return -EOPNOTSUPP; |
2353 | } | |
2354 | ||
46bc8d4b | 2355 | sta_id = il_sta_id_or_broadcast(il, vif_priv->ctx, sta); |
e2ebc833 | 2356 | if (sta_id == IL_INVALID_STATION) |
be663ab6 WYG |
2357 | return -EINVAL; |
2358 | ||
46bc8d4b SG |
2359 | mutex_lock(&il->mutex); |
2360 | il_scan_cancel_timeout(il, 100); | |
be663ab6 WYG |
2361 | |
2362 | /* | |
2363 | * If we are getting WEP group key and we didn't receive any key mapping | |
2364 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
2365 | * in 1X mode. | |
2366 | * In legacy wep mode, we use another host command to the uCode. | |
2367 | */ | |
2368 | if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || | |
2369 | key->cipher == WLAN_CIPHER_SUITE_WEP104) && | |
2370 | !sta) { | |
2371 | if (cmd == SET_KEY) | |
2372 | is_default_wep_key = !ctx->key_mapping_keys; | |
2373 | else | |
2374 | is_default_wep_key = | |
2375 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
2376 | } | |
2377 | ||
2378 | switch (cmd) { | |
2379 | case SET_KEY: | |
2380 | if (is_default_wep_key) | |
46bc8d4b | 2381 | ret = il4965_set_default_wep_key(il, |
be663ab6 WYG |
2382 | vif_priv->ctx, key); |
2383 | else | |
46bc8d4b | 2384 | ret = il4965_set_dynamic_key(il, vif_priv->ctx, |
be663ab6 WYG |
2385 | key, sta_id); |
2386 | ||
58de00a4 | 2387 | D_MAC80211("enable hwcrypto key\n"); |
be663ab6 WYG |
2388 | break; |
2389 | case DISABLE_KEY: | |
2390 | if (is_default_wep_key) | |
46bc8d4b | 2391 | ret = il4965_remove_default_wep_key(il, ctx, key); |
be663ab6 | 2392 | else |
46bc8d4b | 2393 | ret = il4965_remove_dynamic_key(il, ctx, |
be663ab6 WYG |
2394 | key, sta_id); |
2395 | ||
58de00a4 | 2396 | D_MAC80211("disable hwcrypto key\n"); |
be663ab6 WYG |
2397 | break; |
2398 | default: | |
2399 | ret = -EINVAL; | |
2400 | } | |
2401 | ||
46bc8d4b | 2402 | mutex_unlock(&il->mutex); |
58de00a4 | 2403 | D_MAC80211("leave\n"); |
be663ab6 WYG |
2404 | |
2405 | return ret; | |
2406 | } | |
2407 | ||
e2ebc833 | 2408 | int il4965_mac_ampdu_action(struct ieee80211_hw *hw, |
be663ab6 WYG |
2409 | struct ieee80211_vif *vif, |
2410 | enum ieee80211_ampdu_mlme_action action, | |
2411 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, | |
2412 | u8 buf_size) | |
2413 | { | |
46bc8d4b | 2414 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
2415 | int ret = -EINVAL; |
2416 | ||
58de00a4 | 2417 | D_HT("A-MPDU action on addr %pM tid %d\n", |
be663ab6 WYG |
2418 | sta->addr, tid); |
2419 | ||
46bc8d4b | 2420 | if (!(il->cfg->sku & IL_SKU_N)) |
be663ab6 WYG |
2421 | return -EACCES; |
2422 | ||
46bc8d4b | 2423 | mutex_lock(&il->mutex); |
be663ab6 WYG |
2424 | |
2425 | switch (action) { | |
2426 | case IEEE80211_AMPDU_RX_START: | |
58de00a4 | 2427 | D_HT("start Rx\n"); |
46bc8d4b | 2428 | ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn); |
be663ab6 WYG |
2429 | break; |
2430 | case IEEE80211_AMPDU_RX_STOP: | |
58de00a4 | 2431 | D_HT("stop Rx\n"); |
46bc8d4b SG |
2432 | ret = il4965_sta_rx_agg_stop(il, sta, tid); |
2433 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) | |
be663ab6 WYG |
2434 | ret = 0; |
2435 | break; | |
2436 | case IEEE80211_AMPDU_TX_START: | |
58de00a4 | 2437 | D_HT("start Tx\n"); |
46bc8d4b | 2438 | ret = il4965_tx_agg_start(il, vif, sta, tid, ssn); |
be663ab6 WYG |
2439 | break; |
2440 | case IEEE80211_AMPDU_TX_STOP: | |
58de00a4 | 2441 | D_HT("stop Tx\n"); |
46bc8d4b SG |
2442 | ret = il4965_tx_agg_stop(il, vif, sta, tid); |
2443 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) | |
be663ab6 WYG |
2444 | ret = 0; |
2445 | break; | |
2446 | case IEEE80211_AMPDU_TX_OPERATIONAL: | |
2447 | ret = 0; | |
2448 | break; | |
2449 | } | |
46bc8d4b | 2450 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
2451 | |
2452 | return ret; | |
2453 | } | |
2454 | ||
e2ebc833 | 2455 | int il4965_mac_sta_add(struct ieee80211_hw *hw, |
be663ab6 WYG |
2456 | struct ieee80211_vif *vif, |
2457 | struct ieee80211_sta *sta) | |
2458 | { | |
46bc8d4b | 2459 | struct il_priv *il = hw->priv; |
e2ebc833 SG |
2460 | struct il_station_priv *sta_priv = (void *)sta->drv_priv; |
2461 | struct il_vif_priv *vif_priv = (void *)vif->drv_priv; | |
be663ab6 WYG |
2462 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
2463 | int ret; | |
2464 | u8 sta_id; | |
2465 | ||
58de00a4 | 2466 | D_INFO("received request to add station %pM\n", |
be663ab6 | 2467 | sta->addr); |
46bc8d4b | 2468 | mutex_lock(&il->mutex); |
58de00a4 | 2469 | D_INFO("proceeding to add station %pM\n", |
be663ab6 | 2470 | sta->addr); |
e2ebc833 | 2471 | sta_priv->common.sta_id = IL_INVALID_STATION; |
be663ab6 WYG |
2472 | |
2473 | atomic_set(&sta_priv->pending_frames, 0); | |
2474 | ||
46bc8d4b | 2475 | ret = il_add_station_common(il, vif_priv->ctx, sta->addr, |
be663ab6 WYG |
2476 | is_ap, sta, &sta_id); |
2477 | if (ret) { | |
9406f797 | 2478 | IL_ERR("Unable to add station %pM (%d)\n", |
be663ab6 WYG |
2479 | sta->addr, ret); |
2480 | /* Should we return success if return code is EEXIST ? */ | |
46bc8d4b | 2481 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
2482 | return ret; |
2483 | } | |
2484 | ||
2485 | sta_priv->common.sta_id = sta_id; | |
2486 | ||
2487 | /* Initialize rate scaling */ | |
58de00a4 | 2488 | D_INFO("Initializing rate scaling for station %pM\n", |
be663ab6 | 2489 | sta->addr); |
46bc8d4b SG |
2490 | il4965_rs_rate_init(il, sta, sta_id); |
2491 | mutex_unlock(&il->mutex); | |
be663ab6 WYG |
2492 | |
2493 | return 0; | |
2494 | } | |
2495 | ||
e2ebc833 | 2496 | void il4965_mac_channel_switch(struct ieee80211_hw *hw, |
be663ab6 WYG |
2497 | struct ieee80211_channel_switch *ch_switch) |
2498 | { | |
46bc8d4b | 2499 | struct il_priv *il = hw->priv; |
e2ebc833 | 2500 | const struct il_channel_info *ch_info; |
be663ab6 WYG |
2501 | struct ieee80211_conf *conf = &hw->conf; |
2502 | struct ieee80211_channel *channel = ch_switch->channel; | |
46bc8d4b | 2503 | struct il_ht_config *ht_conf = &il->current_ht_config; |
be663ab6 | 2504 | |
7c2cde2e | 2505 | struct il_rxon_context *ctx = &il->ctx; |
be663ab6 | 2506 | u16 ch; |
be663ab6 | 2507 | |
58de00a4 | 2508 | D_MAC80211("enter\n"); |
be663ab6 | 2509 | |
46bc8d4b | 2510 | mutex_lock(&il->mutex); |
28a6e577 | 2511 | |
46bc8d4b | 2512 | if (il_is_rfkill(il)) |
28a6e577 | 2513 | goto out; |
be663ab6 | 2514 | |
46bc8d4b SG |
2515 | if (test_bit(STATUS_EXIT_PENDING, &il->status) || |
2516 | test_bit(STATUS_SCANNING, &il->status) || | |
2517 | test_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status)) | |
28a6e577 | 2518 | goto out; |
be663ab6 | 2519 | |
e2ebc833 | 2520 | if (!il_is_associated_ctx(ctx)) |
28a6e577 | 2521 | goto out; |
be663ab6 | 2522 | |
46bc8d4b | 2523 | if (!il->cfg->ops->lib->set_channel_switch) |
7f1f9742 | 2524 | goto out; |
be663ab6 | 2525 | |
7f1f9742 SG |
2526 | ch = channel->hw_value; |
2527 | if (le16_to_cpu(ctx->active.channel) == ch) | |
2528 | goto out; | |
2529 | ||
46bc8d4b | 2530 | ch_info = il_get_channel_info(il, channel->band, ch); |
e2ebc833 | 2531 | if (!il_is_channel_valid(ch_info)) { |
58de00a4 | 2532 | D_MAC80211("invalid channel\n"); |
7f1f9742 SG |
2533 | goto out; |
2534 | } | |
2535 | ||
46bc8d4b | 2536 | spin_lock_irq(&il->lock); |
7f1f9742 | 2537 | |
46bc8d4b | 2538 | il->current_ht_config.smps = conf->smps_mode; |
7f1f9742 SG |
2539 | |
2540 | /* Configure HT40 channels */ | |
2541 | ctx->ht.enabled = conf_is_ht(conf); | |
2542 | if (ctx->ht.enabled) { | |
2543 | if (conf_is_ht40_minus(conf)) { | |
2544 | ctx->ht.extension_chan_offset = | |
2545 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; | |
2546 | ctx->ht.is_40mhz = true; | |
2547 | } else if (conf_is_ht40_plus(conf)) { | |
2548 | ctx->ht.extension_chan_offset = | |
2549 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; | |
2550 | ctx->ht.is_40mhz = true; | |
2551 | } else { | |
2552 | ctx->ht.extension_chan_offset = | |
2553 | IEEE80211_HT_PARAM_CHA_SEC_NONE; | |
2554 | ctx->ht.is_40mhz = false; | |
be663ab6 | 2555 | } |
7f1f9742 SG |
2556 | } else |
2557 | ctx->ht.is_40mhz = false; | |
2558 | ||
2559 | if ((le16_to_cpu(ctx->staging.channel) != ch)) | |
2560 | ctx->staging.flags = 0; | |
2561 | ||
46bc8d4b SG |
2562 | il_set_rxon_channel(il, channel, ctx); |
2563 | il_set_rxon_ht(il, ht_conf); | |
2564 | il_set_flags_for_band(il, ctx, channel->band, ctx->vif); | |
7f1f9742 | 2565 | |
46bc8d4b | 2566 | spin_unlock_irq(&il->lock); |
7f1f9742 | 2567 | |
46bc8d4b | 2568 | il_set_rate(il); |
7f1f9742 SG |
2569 | /* |
2570 | * at this point, staging_rxon has the | |
2571 | * configuration for channel switch | |
2572 | */ | |
46bc8d4b SG |
2573 | set_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status); |
2574 | il->switch_channel = cpu_to_le16(ch); | |
2575 | if (il->cfg->ops->lib->set_channel_switch(il, ch_switch)) { | |
2576 | clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status); | |
2577 | il->switch_channel = 0; | |
7f1f9742 | 2578 | ieee80211_chswitch_done(ctx->vif, false); |
be663ab6 | 2579 | } |
7f1f9742 | 2580 | |
be663ab6 | 2581 | out: |
46bc8d4b | 2582 | mutex_unlock(&il->mutex); |
58de00a4 | 2583 | D_MAC80211("leave\n"); |
be663ab6 WYG |
2584 | } |
2585 | ||
e2ebc833 | 2586 | void il4965_configure_filter(struct ieee80211_hw *hw, |
be663ab6 WYG |
2587 | unsigned int changed_flags, |
2588 | unsigned int *total_flags, | |
2589 | u64 multicast) | |
2590 | { | |
46bc8d4b | 2591 | struct il_priv *il = hw->priv; |
be663ab6 | 2592 | __le32 filter_or = 0, filter_nand = 0; |
e2ebc833 | 2593 | struct il_rxon_context *ctx; |
be663ab6 WYG |
2594 | |
2595 | #define CHK(test, flag) do { \ | |
2596 | if (*total_flags & (test)) \ | |
2597 | filter_or |= (flag); \ | |
2598 | else \ | |
2599 | filter_nand |= (flag); \ | |
2600 | } while (0) | |
2601 | ||
58de00a4 | 2602 | D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", |
be663ab6 WYG |
2603 | changed_flags, *total_flags); |
2604 | ||
2605 | CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); | |
2606 | /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */ | |
2607 | CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); | |
2608 | CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); | |
2609 | ||
2610 | #undef CHK | |
2611 | ||
46bc8d4b | 2612 | mutex_lock(&il->mutex); |
be663ab6 | 2613 | |
46bc8d4b | 2614 | for_each_context(il, ctx) { |
be663ab6 WYG |
2615 | ctx->staging.filter_flags &= ~filter_nand; |
2616 | ctx->staging.filter_flags |= filter_or; | |
2617 | ||
2618 | /* | |
2619 | * Not committing directly because hardware can perform a scan, | |
2620 | * but we'll eventually commit the filter flags change anyway. | |
2621 | */ | |
2622 | } | |
2623 | ||
46bc8d4b | 2624 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
2625 | |
2626 | /* | |
2627 | * Receiving all multicast frames is always enabled by the | |
e2ebc833 | 2628 | * default flags setup in il_connection_init_rx_config() |
be663ab6 WYG |
2629 | * since we currently do not support programming multicast |
2630 | * filters into the device. | |
2631 | */ | |
2632 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
2633 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
2634 | } | |
2635 | ||
2636 | /***************************************************************************** | |
2637 | * | |
2638 | * driver setup and teardown | |
2639 | * | |
2640 | *****************************************************************************/ | |
2641 | ||
e2ebc833 | 2642 | static void il4965_bg_txpower_work(struct work_struct *work) |
be663ab6 | 2643 | { |
46bc8d4b | 2644 | struct il_priv *il = container_of(work, struct il_priv, |
be663ab6 WYG |
2645 | txpower_work); |
2646 | ||
46bc8d4b | 2647 | mutex_lock(&il->mutex); |
f325757a | 2648 | |
be663ab6 WYG |
2649 | /* If a scan happened to start before we got here |
2650 | * then just return; the statistics notification will | |
2651 | * kick off another scheduled work to compensate for | |
2652 | * any temperature delta we missed here. */ | |
46bc8d4b SG |
2653 | if (test_bit(STATUS_EXIT_PENDING, &il->status) || |
2654 | test_bit(STATUS_SCANNING, &il->status)) | |
f325757a | 2655 | goto out; |
be663ab6 WYG |
2656 | |
2657 | /* Regardless of if we are associated, we must reconfigure the | |
2658 | * TX power since frames can be sent on non-radar channels while | |
2659 | * not associated */ | |
46bc8d4b | 2660 | il->cfg->ops->lib->send_tx_power(il); |
be663ab6 WYG |
2661 | |
2662 | /* Update last_temperature to keep is_calib_needed from running | |
2663 | * when it isn't needed... */ | |
46bc8d4b | 2664 | il->last_temperature = il->temperature; |
f325757a | 2665 | out: |
46bc8d4b | 2666 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
2667 | } |
2668 | ||
46bc8d4b | 2669 | static void il4965_setup_deferred_work(struct il_priv *il) |
be663ab6 | 2670 | { |
46bc8d4b | 2671 | il->workqueue = create_singlethread_workqueue(DRV_NAME); |
be663ab6 | 2672 | |
46bc8d4b | 2673 | init_waitqueue_head(&il->wait_command_queue); |
be663ab6 | 2674 | |
46bc8d4b SG |
2675 | INIT_WORK(&il->restart, il4965_bg_restart); |
2676 | INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish); | |
2677 | INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work); | |
2678 | INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start); | |
2679 | INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start); | |
be663ab6 | 2680 | |
46bc8d4b | 2681 | il_setup_scan_deferred_work(il); |
be663ab6 | 2682 | |
46bc8d4b | 2683 | INIT_WORK(&il->txpower_work, il4965_bg_txpower_work); |
be663ab6 | 2684 | |
46bc8d4b SG |
2685 | init_timer(&il->statistics_periodic); |
2686 | il->statistics_periodic.data = (unsigned long)il; | |
2687 | il->statistics_periodic.function = il4965_bg_statistics_periodic; | |
be663ab6 | 2688 | |
46bc8d4b SG |
2689 | init_timer(&il->watchdog); |
2690 | il->watchdog.data = (unsigned long)il; | |
2691 | il->watchdog.function = il_bg_watchdog; | |
be663ab6 | 2692 | |
46bc8d4b SG |
2693 | tasklet_init(&il->irq_tasklet, (void (*)(unsigned long)) |
2694 | il4965_irq_tasklet, (unsigned long)il); | |
be663ab6 WYG |
2695 | } |
2696 | ||
46bc8d4b | 2697 | static void il4965_cancel_deferred_work(struct il_priv *il) |
be663ab6 | 2698 | { |
46bc8d4b SG |
2699 | cancel_work_sync(&il->txpower_work); |
2700 | cancel_delayed_work_sync(&il->init_alive_start); | |
2701 | cancel_delayed_work(&il->alive_start); | |
2702 | cancel_work_sync(&il->run_time_calib_work); | |
be663ab6 | 2703 | |
46bc8d4b | 2704 | il_cancel_scan_deferred_work(il); |
be663ab6 | 2705 | |
46bc8d4b | 2706 | del_timer_sync(&il->statistics_periodic); |
be663ab6 WYG |
2707 | } |
2708 | ||
46bc8d4b | 2709 | static void il4965_init_hw_rates(struct il_priv *il, |
be663ab6 WYG |
2710 | struct ieee80211_rate *rates) |
2711 | { | |
2712 | int i; | |
2713 | ||
e2ebc833 | 2714 | for (i = 0; i < IL_RATE_COUNT_LEGACY; i++) { |
d2ddf621 | 2715 | rates[i].bitrate = il_rates[i].ieee * 5; |
be663ab6 WYG |
2716 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ |
2717 | rates[i].hw_value_short = i; | |
2718 | rates[i].flags = 0; | |
e2ebc833 | 2719 | if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) { |
be663ab6 WYG |
2720 | /* |
2721 | * If CCK != 1M then set short preamble rate flag. | |
2722 | */ | |
2723 | rates[i].flags |= | |
d2ddf621 | 2724 | (il_rates[i].plcp == IL_RATE_1M_PLCP) ? |
be663ab6 WYG |
2725 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; |
2726 | } | |
2727 | } | |
2728 | } | |
2729 | /* | |
46bc8d4b | 2730 | * Acquire il->lock before calling this function ! |
be663ab6 | 2731 | */ |
46bc8d4b | 2732 | void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 index) |
be663ab6 | 2733 | { |
0c1a94e2 | 2734 | il_wr(il, HBUS_TARG_WRPTR, |
be663ab6 | 2735 | (index & 0xff) | (txq_id << 8)); |
d3175167 | 2736 | il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), index); |
be663ab6 WYG |
2737 | } |
2738 | ||
46bc8d4b | 2739 | void il4965_tx_queue_set_status(struct il_priv *il, |
e2ebc833 | 2740 | struct il_tx_queue *txq, |
be663ab6 WYG |
2741 | int tx_fifo_id, int scd_retry) |
2742 | { | |
2743 | int txq_id = txq->q.id; | |
2744 | ||
2745 | /* Find out whether to activate Tx queue */ | |
46bc8d4b | 2746 | int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0; |
be663ab6 WYG |
2747 | |
2748 | /* Set up and activate */ | |
d3175167 SG |
2749 | il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id), |
2750 | (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
2751 | (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) | | |
2752 | (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) | | |
2753 | (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) | | |
2754 | IL49_SCD_QUEUE_STTS_REG_MSK); | |
be663ab6 WYG |
2755 | |
2756 | txq->sched_retry = scd_retry; | |
2757 | ||
58de00a4 | 2758 | D_INFO("%s %s Queue %d on AC %d\n", |
be663ab6 WYG |
2759 | active ? "Activate" : "Deactivate", |
2760 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); | |
2761 | } | |
2762 | ||
2763 | ||
46bc8d4b | 2764 | static int il4965_init_drv(struct il_priv *il) |
be663ab6 WYG |
2765 | { |
2766 | int ret; | |
2767 | ||
46bc8d4b SG |
2768 | spin_lock_init(&il->sta_lock); |
2769 | spin_lock_init(&il->hcmd_lock); | |
be663ab6 | 2770 | |
46bc8d4b | 2771 | INIT_LIST_HEAD(&il->free_frames); |
be663ab6 | 2772 | |
46bc8d4b | 2773 | mutex_init(&il->mutex); |
be663ab6 | 2774 | |
46bc8d4b SG |
2775 | il->ieee_channels = NULL; |
2776 | il->ieee_rates = NULL; | |
2777 | il->band = IEEE80211_BAND_2GHZ; | |
be663ab6 | 2778 | |
46bc8d4b SG |
2779 | il->iw_mode = NL80211_IFTYPE_STATION; |
2780 | il->current_ht_config.smps = IEEE80211_SMPS_STATIC; | |
2781 | il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF; | |
be663ab6 WYG |
2782 | |
2783 | /* initialize force reset */ | |
46bc8d4b | 2784 | il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD; |
be663ab6 WYG |
2785 | |
2786 | /* Choose which receivers/antennas to use */ | |
46bc8d4b SG |
2787 | if (il->cfg->ops->hcmd->set_rxon_chain) |
2788 | il->cfg->ops->hcmd->set_rxon_chain(il, | |
7c2cde2e | 2789 | &il->ctx); |
be663ab6 | 2790 | |
46bc8d4b | 2791 | il_init_scan_params(il); |
be663ab6 | 2792 | |
46bc8d4b | 2793 | ret = il_init_channel_map(il); |
be663ab6 | 2794 | if (ret) { |
9406f797 | 2795 | IL_ERR("initializing regulatory failed: %d\n", ret); |
be663ab6 WYG |
2796 | goto err; |
2797 | } | |
2798 | ||
46bc8d4b | 2799 | ret = il_init_geos(il); |
be663ab6 | 2800 | if (ret) { |
9406f797 | 2801 | IL_ERR("initializing geos failed: %d\n", ret); |
be663ab6 WYG |
2802 | goto err_free_channel_map; |
2803 | } | |
46bc8d4b | 2804 | il4965_init_hw_rates(il, il->ieee_rates); |
be663ab6 WYG |
2805 | |
2806 | return 0; | |
2807 | ||
2808 | err_free_channel_map: | |
46bc8d4b | 2809 | il_free_channel_map(il); |
be663ab6 WYG |
2810 | err: |
2811 | return ret; | |
2812 | } | |
2813 | ||
46bc8d4b | 2814 | static void il4965_uninit_drv(struct il_priv *il) |
be663ab6 | 2815 | { |
46bc8d4b SG |
2816 | il4965_calib_free_results(il); |
2817 | il_free_geos(il); | |
2818 | il_free_channel_map(il); | |
2819 | kfree(il->scan_cmd); | |
be663ab6 WYG |
2820 | } |
2821 | ||
46bc8d4b | 2822 | static void il4965_hw_detect(struct il_priv *il) |
be663ab6 | 2823 | { |
841b2cca SG |
2824 | il->hw_rev = _il_rd(il, CSR_HW_REV); |
2825 | il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG); | |
46bc8d4b | 2826 | il->rev_id = il->pci_dev->revision; |
58de00a4 | 2827 | D_INFO("HW Revision ID = 0x%X\n", il->rev_id); |
be663ab6 WYG |
2828 | } |
2829 | ||
46bc8d4b | 2830 | static int il4965_set_hw_params(struct il_priv *il) |
be663ab6 | 2831 | { |
46bc8d4b SG |
2832 | il->hw_params.max_rxq_size = RX_QUEUE_SIZE; |
2833 | il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
2834 | if (il->cfg->mod_params->amsdu_size_8K) | |
2835 | il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K); | |
be663ab6 | 2836 | else |
46bc8d4b | 2837 | il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K); |
be663ab6 | 2838 | |
46bc8d4b | 2839 | il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL; |
be663ab6 | 2840 | |
46bc8d4b SG |
2841 | if (il->cfg->mod_params->disable_11n) |
2842 | il->cfg->sku &= ~IL_SKU_N; | |
be663ab6 WYG |
2843 | |
2844 | /* Device-specific setup */ | |
46bc8d4b | 2845 | return il->cfg->ops->lib->set_hw_params(il); |
be663ab6 WYG |
2846 | } |
2847 | ||
e2ebc833 SG |
2848 | static const u8 il4965_bss_ac_to_fifo[] = { |
2849 | IL_TX_FIFO_VO, | |
2850 | IL_TX_FIFO_VI, | |
2851 | IL_TX_FIFO_BE, | |
2852 | IL_TX_FIFO_BK, | |
be663ab6 WYG |
2853 | }; |
2854 | ||
e2ebc833 | 2855 | static const u8 il4965_bss_ac_to_queue[] = { |
be663ab6 WYG |
2856 | 0, 1, 2, 3, |
2857 | }; | |
2858 | ||
2859 | static int | |
e2ebc833 | 2860 | il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
be663ab6 | 2861 | { |
7c2cde2e | 2862 | int err = 0; |
46bc8d4b | 2863 | struct il_priv *il; |
be663ab6 | 2864 | struct ieee80211_hw *hw; |
e2ebc833 | 2865 | struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data); |
be663ab6 WYG |
2866 | unsigned long flags; |
2867 | u16 pci_cmd; | |
2868 | ||
2869 | /************************ | |
2870 | * 1. Allocating HW data | |
2871 | ************************/ | |
2872 | ||
e2ebc833 | 2873 | hw = il_alloc_all(cfg); |
be663ab6 WYG |
2874 | if (!hw) { |
2875 | err = -ENOMEM; | |
2876 | goto out; | |
2877 | } | |
46bc8d4b SG |
2878 | il = hw->priv; |
2879 | /* At this point both hw and il are allocated. */ | |
be663ab6 | 2880 | |
7c2cde2e SG |
2881 | il->ctx.ctxid = 0; |
2882 | ||
2883 | il->ctx.always_active = true; | |
2884 | il->ctx.is_active = true; | |
2885 | il->ctx.rxon_cmd = REPLY_RXON; | |
2886 | il->ctx.rxon_timing_cmd = REPLY_RXON_TIMING; | |
2887 | il->ctx.rxon_assoc_cmd = REPLY_RXON_ASSOC; | |
2888 | il->ctx.qos_cmd = REPLY_QOS_PARAM; | |
2889 | il->ctx.ap_sta_id = IL_AP_ID; | |
2890 | il->ctx.wep_key_cmd = REPLY_WEPKEY; | |
2891 | il->ctx.ac_to_fifo = il4965_bss_ac_to_fifo; | |
2892 | il->ctx.ac_to_queue = il4965_bss_ac_to_queue; | |
2893 | il->ctx.exclusive_interface_modes = | |
be663ab6 | 2894 | BIT(NL80211_IFTYPE_ADHOC); |
7c2cde2e | 2895 | il->ctx.interface_modes = |
be663ab6 | 2896 | BIT(NL80211_IFTYPE_STATION); |
7c2cde2e SG |
2897 | il->ctx.ap_devtype = RXON_DEV_TYPE_AP; |
2898 | il->ctx.ibss_devtype = RXON_DEV_TYPE_IBSS; | |
2899 | il->ctx.station_devtype = RXON_DEV_TYPE_ESS; | |
2900 | il->ctx.unused_devtype = RXON_DEV_TYPE_ESS; | |
be663ab6 WYG |
2901 | |
2902 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
2903 | ||
58de00a4 | 2904 | D_INFO("*** LOAD DRIVER ***\n"); |
46bc8d4b SG |
2905 | il->cfg = cfg; |
2906 | il->pci_dev = pdev; | |
2907 | il->inta_mask = CSR_INI_SET_MASK; | |
be663ab6 | 2908 | |
46bc8d4b | 2909 | if (il_alloc_traffic_mem(il)) |
9406f797 | 2910 | IL_ERR("Not enough memory to generate traffic log\n"); |
be663ab6 WYG |
2911 | |
2912 | /************************** | |
2913 | * 2. Initializing PCI bus | |
2914 | **************************/ | |
2915 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
2916 | PCIE_LINK_STATE_CLKPM); | |
2917 | ||
2918 | if (pci_enable_device(pdev)) { | |
2919 | err = -ENODEV; | |
2920 | goto out_ieee80211_free_hw; | |
2921 | } | |
2922 | ||
2923 | pci_set_master(pdev); | |
2924 | ||
2925 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2926 | if (!err) | |
2927 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
2928 | if (err) { | |
2929 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2930 | if (!err) | |
2931 | err = pci_set_consistent_dma_mask(pdev, | |
2932 | DMA_BIT_MASK(32)); | |
2933 | /* both attempts failed: */ | |
2934 | if (err) { | |
9406f797 | 2935 | IL_WARN("No suitable DMA available.\n"); |
be663ab6 WYG |
2936 | goto out_pci_disable_device; |
2937 | } | |
2938 | } | |
2939 | ||
2940 | err = pci_request_regions(pdev, DRV_NAME); | |
2941 | if (err) | |
2942 | goto out_pci_disable_device; | |
2943 | ||
46bc8d4b | 2944 | pci_set_drvdata(pdev, il); |
be663ab6 WYG |
2945 | |
2946 | ||
2947 | /*********************** | |
2948 | * 3. Read REV register | |
2949 | ***********************/ | |
46bc8d4b SG |
2950 | il->hw_base = pci_iomap(pdev, 0, 0); |
2951 | if (!il->hw_base) { | |
be663ab6 WYG |
2952 | err = -ENODEV; |
2953 | goto out_pci_release_regions; | |
2954 | } | |
2955 | ||
58de00a4 | 2956 | D_INFO("pci_resource_len = 0x%08llx\n", |
be663ab6 | 2957 | (unsigned long long) pci_resource_len(pdev, 0)); |
58de00a4 | 2958 | D_INFO("pci_resource_base = %p\n", il->hw_base); |
be663ab6 WYG |
2959 | |
2960 | /* these spin locks will be used in apm_ops.init and EEPROM access | |
2961 | * we should init now | |
2962 | */ | |
46bc8d4b SG |
2963 | spin_lock_init(&il->reg_lock); |
2964 | spin_lock_init(&il->lock); | |
be663ab6 WYG |
2965 | |
2966 | /* | |
2967 | * stop and reset the on-board processor just in case it is in a | |
2968 | * strange state ... like being left stranded by a primary kernel | |
2969 | * and this is now the kdump kernel trying to start up | |
2970 | */ | |
841b2cca | 2971 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
be663ab6 | 2972 | |
46bc8d4b | 2973 | il4965_hw_detect(il); |
9406f797 | 2974 | IL_INFO("Detected %s, REV=0x%X\n", |
46bc8d4b | 2975 | il->cfg->name, il->hw_rev); |
be663ab6 WYG |
2976 | |
2977 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
2978 | * PCI Tx retries from interfering with C3 CPU state */ | |
2979 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2980 | ||
46bc8d4b SG |
2981 | il4965_prepare_card_hw(il); |
2982 | if (!il->hw_ready) { | |
9406f797 | 2983 | IL_WARN("Failed, HW not ready\n"); |
be663ab6 WYG |
2984 | goto out_iounmap; |
2985 | } | |
2986 | ||
2987 | /***************** | |
2988 | * 4. Read EEPROM | |
2989 | *****************/ | |
2990 | /* Read the EEPROM */ | |
46bc8d4b | 2991 | err = il_eeprom_init(il); |
be663ab6 | 2992 | if (err) { |
9406f797 | 2993 | IL_ERR("Unable to init EEPROM\n"); |
be663ab6 WYG |
2994 | goto out_iounmap; |
2995 | } | |
46bc8d4b | 2996 | err = il4965_eeprom_check_version(il); |
be663ab6 WYG |
2997 | if (err) |
2998 | goto out_free_eeprom; | |
2999 | ||
3000 | if (err) | |
3001 | goto out_free_eeprom; | |
3002 | ||
3003 | /* extract MAC Address */ | |
46bc8d4b | 3004 | il4965_eeprom_get_mac(il, il->addresses[0].addr); |
58de00a4 | 3005 | D_INFO("MAC address: %pM\n", il->addresses[0].addr); |
46bc8d4b SG |
3006 | il->hw->wiphy->addresses = il->addresses; |
3007 | il->hw->wiphy->n_addresses = 1; | |
be663ab6 WYG |
3008 | |
3009 | /************************ | |
3010 | * 5. Setup HW constants | |
3011 | ************************/ | |
46bc8d4b | 3012 | if (il4965_set_hw_params(il)) { |
9406f797 | 3013 | IL_ERR("failed to set hw parameters\n"); |
be663ab6 WYG |
3014 | goto out_free_eeprom; |
3015 | } | |
3016 | ||
3017 | /******************* | |
46bc8d4b | 3018 | * 6. Setup il |
be663ab6 WYG |
3019 | *******************/ |
3020 | ||
46bc8d4b | 3021 | err = il4965_init_drv(il); |
be663ab6 WYG |
3022 | if (err) |
3023 | goto out_free_eeprom; | |
46bc8d4b | 3024 | /* At this point both hw and il are initialized. */ |
be663ab6 WYG |
3025 | |
3026 | /******************** | |
3027 | * 7. Setup services | |
3028 | ********************/ | |
46bc8d4b SG |
3029 | spin_lock_irqsave(&il->lock, flags); |
3030 | il_disable_interrupts(il); | |
3031 | spin_unlock_irqrestore(&il->lock, flags); | |
be663ab6 | 3032 | |
46bc8d4b | 3033 | pci_enable_msi(il->pci_dev); |
be663ab6 | 3034 | |
46bc8d4b SG |
3035 | err = request_irq(il->pci_dev->irq, il_isr, |
3036 | IRQF_SHARED, DRV_NAME, il); | |
be663ab6 | 3037 | if (err) { |
9406f797 | 3038 | IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq); |
be663ab6 WYG |
3039 | goto out_disable_msi; |
3040 | } | |
3041 | ||
46bc8d4b SG |
3042 | il4965_setup_deferred_work(il); |
3043 | il4965_setup_rx_handlers(il); | |
be663ab6 WYG |
3044 | |
3045 | /********************************************* | |
3046 | * 8. Enable interrupts and read RFKILL state | |
3047 | *********************************************/ | |
3048 | ||
a078a1fd | 3049 | /* enable rfkill interrupt: hw bug w/a */ |
46bc8d4b | 3050 | pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd); |
be663ab6 WYG |
3051 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { |
3052 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
46bc8d4b | 3053 | pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd); |
be663ab6 WYG |
3054 | } |
3055 | ||
46bc8d4b | 3056 | il_enable_rfkill_int(il); |
be663ab6 WYG |
3057 | |
3058 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
841b2cca | 3059 | if (_il_rd(il, CSR_GP_CNTRL) & |
be663ab6 | 3060 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
46bc8d4b | 3061 | clear_bit(STATUS_RF_KILL_HW, &il->status); |
be663ab6 | 3062 | else |
46bc8d4b | 3063 | set_bit(STATUS_RF_KILL_HW, &il->status); |
be663ab6 | 3064 | |
46bc8d4b SG |
3065 | wiphy_rfkill_set_hw_state(il->hw->wiphy, |
3066 | test_bit(STATUS_RF_KILL_HW, &il->status)); | |
be663ab6 | 3067 | |
46bc8d4b | 3068 | il_power_initialize(il); |
be663ab6 | 3069 | |
46bc8d4b | 3070 | init_completion(&il->_4965.firmware_loading_complete); |
be663ab6 | 3071 | |
46bc8d4b | 3072 | err = il4965_request_firmware(il, true); |
be663ab6 WYG |
3073 | if (err) |
3074 | goto out_destroy_workqueue; | |
3075 | ||
3076 | return 0; | |
3077 | ||
3078 | out_destroy_workqueue: | |
46bc8d4b SG |
3079 | destroy_workqueue(il->workqueue); |
3080 | il->workqueue = NULL; | |
3081 | free_irq(il->pci_dev->irq, il); | |
be663ab6 | 3082 | out_disable_msi: |
46bc8d4b SG |
3083 | pci_disable_msi(il->pci_dev); |
3084 | il4965_uninit_drv(il); | |
be663ab6 | 3085 | out_free_eeprom: |
46bc8d4b | 3086 | il_eeprom_free(il); |
be663ab6 | 3087 | out_iounmap: |
46bc8d4b | 3088 | pci_iounmap(pdev, il->hw_base); |
be663ab6 WYG |
3089 | out_pci_release_regions: |
3090 | pci_set_drvdata(pdev, NULL); | |
3091 | pci_release_regions(pdev); | |
3092 | out_pci_disable_device: | |
3093 | pci_disable_device(pdev); | |
3094 | out_ieee80211_free_hw: | |
46bc8d4b SG |
3095 | il_free_traffic_mem(il); |
3096 | ieee80211_free_hw(il->hw); | |
be663ab6 WYG |
3097 | out: |
3098 | return err; | |
3099 | } | |
3100 | ||
e2ebc833 | 3101 | static void __devexit il4965_pci_remove(struct pci_dev *pdev) |
be663ab6 | 3102 | { |
46bc8d4b | 3103 | struct il_priv *il = pci_get_drvdata(pdev); |
be663ab6 WYG |
3104 | unsigned long flags; |
3105 | ||
46bc8d4b | 3106 | if (!il) |
be663ab6 WYG |
3107 | return; |
3108 | ||
46bc8d4b | 3109 | wait_for_completion(&il->_4965.firmware_loading_complete); |
be663ab6 | 3110 | |
58de00a4 | 3111 | D_INFO("*** UNLOAD DRIVER ***\n"); |
be663ab6 | 3112 | |
46bc8d4b | 3113 | il_dbgfs_unregister(il); |
e2ebc833 | 3114 | sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group); |
be663ab6 | 3115 | |
e2ebc833 SG |
3116 | /* ieee80211_unregister_hw call wil cause il_mac_stop to |
3117 | * to be called and il4965_down since we are removing the device | |
be663ab6 WYG |
3118 | * we need to set STATUS_EXIT_PENDING bit. |
3119 | */ | |
46bc8d4b | 3120 | set_bit(STATUS_EXIT_PENDING, &il->status); |
be663ab6 | 3121 | |
46bc8d4b | 3122 | il_leds_exit(il); |
be663ab6 | 3123 | |
46bc8d4b SG |
3124 | if (il->mac80211_registered) { |
3125 | ieee80211_unregister_hw(il->hw); | |
3126 | il->mac80211_registered = 0; | |
be663ab6 | 3127 | } else { |
46bc8d4b | 3128 | il4965_down(il); |
be663ab6 WYG |
3129 | } |
3130 | ||
3131 | /* | |
3132 | * Make sure device is reset to low power before unloading driver. | |
e2ebc833 SG |
3133 | * This may be redundant with il4965_down(), but there are paths to |
3134 | * run il4965_down() without calling apm_ops.stop(), and there are | |
3135 | * paths to avoid running il4965_down() at all before leaving driver. | |
be663ab6 WYG |
3136 | * This (inexpensive) call *makes sure* device is reset. |
3137 | */ | |
46bc8d4b | 3138 | il_apm_stop(il); |
be663ab6 WYG |
3139 | |
3140 | /* make sure we flush any pending irq or | |
3141 | * tasklet for the driver | |
3142 | */ | |
46bc8d4b SG |
3143 | spin_lock_irqsave(&il->lock, flags); |
3144 | il_disable_interrupts(il); | |
3145 | spin_unlock_irqrestore(&il->lock, flags); | |
be663ab6 | 3146 | |
46bc8d4b | 3147 | il4965_synchronize_irq(il); |
be663ab6 | 3148 | |
46bc8d4b | 3149 | il4965_dealloc_ucode_pci(il); |
be663ab6 | 3150 | |
46bc8d4b SG |
3151 | if (il->rxq.bd) |
3152 | il4965_rx_queue_free(il, &il->rxq); | |
3153 | il4965_hw_txq_ctx_free(il); | |
be663ab6 | 3154 | |
46bc8d4b | 3155 | il_eeprom_free(il); |
be663ab6 WYG |
3156 | |
3157 | ||
3158 | /*netif_stop_queue(dev); */ | |
46bc8d4b | 3159 | flush_workqueue(il->workqueue); |
be663ab6 | 3160 | |
e2ebc833 | 3161 | /* ieee80211_unregister_hw calls il_mac_stop, which flushes |
46bc8d4b | 3162 | * il->workqueue... so we can't take down the workqueue |
be663ab6 | 3163 | * until now... */ |
46bc8d4b SG |
3164 | destroy_workqueue(il->workqueue); |
3165 | il->workqueue = NULL; | |
3166 | il_free_traffic_mem(il); | |
be663ab6 | 3167 | |
46bc8d4b SG |
3168 | free_irq(il->pci_dev->irq, il); |
3169 | pci_disable_msi(il->pci_dev); | |
3170 | pci_iounmap(pdev, il->hw_base); | |
be663ab6 WYG |
3171 | pci_release_regions(pdev); |
3172 | pci_disable_device(pdev); | |
3173 | pci_set_drvdata(pdev, NULL); | |
3174 | ||
46bc8d4b | 3175 | il4965_uninit_drv(il); |
be663ab6 | 3176 | |
46bc8d4b | 3177 | dev_kfree_skb(il->beacon_skb); |
be663ab6 | 3178 | |
46bc8d4b | 3179 | ieee80211_free_hw(il->hw); |
be663ab6 WYG |
3180 | } |
3181 | ||
3182 | /* | |
3183 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
46bc8d4b | 3184 | * must be called under il->lock and mac access |
be663ab6 | 3185 | */ |
46bc8d4b | 3186 | void il4965_txq_set_sched(struct il_priv *il, u32 mask) |
be663ab6 | 3187 | { |
d3175167 | 3188 | il_wr_prph(il, IL49_SCD_TXFACT, mask); |
be663ab6 WYG |
3189 | } |
3190 | ||
3191 | /***************************************************************************** | |
3192 | * | |
3193 | * driver and module entry point | |
3194 | * | |
3195 | *****************************************************************************/ | |
3196 | ||
3197 | /* Hardware specific file defines the PCI IDs table for that hardware module */ | |
e2ebc833 | 3198 | static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = { |
e2ebc833 SG |
3199 | {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)}, |
3200 | {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)}, | |
be663ab6 WYG |
3201 | {0} |
3202 | }; | |
e2ebc833 | 3203 | MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids); |
be663ab6 | 3204 | |
e2ebc833 | 3205 | static struct pci_driver il4965_driver = { |
be663ab6 | 3206 | .name = DRV_NAME, |
e2ebc833 SG |
3207 | .id_table = il4965_hw_card_ids, |
3208 | .probe = il4965_pci_probe, | |
3209 | .remove = __devexit_p(il4965_pci_remove), | |
3210 | .driver.pm = IL_LEGACY_PM_OPS, | |
be663ab6 WYG |
3211 | }; |
3212 | ||
e2ebc833 | 3213 | static int __init il4965_init(void) |
be663ab6 WYG |
3214 | { |
3215 | ||
3216 | int ret; | |
3217 | pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3218 | pr_info(DRV_COPYRIGHT "\n"); | |
3219 | ||
e2ebc833 | 3220 | ret = il4965_rate_control_register(); |
be663ab6 WYG |
3221 | if (ret) { |
3222 | pr_err("Unable to register rate control algorithm: %d\n", ret); | |
3223 | return ret; | |
3224 | } | |
3225 | ||
e2ebc833 | 3226 | ret = pci_register_driver(&il4965_driver); |
be663ab6 WYG |
3227 | if (ret) { |
3228 | pr_err("Unable to initialize PCI module\n"); | |
3229 | goto error_register; | |
3230 | } | |
3231 | ||
3232 | return ret; | |
3233 | ||
3234 | error_register: | |
e2ebc833 | 3235 | il4965_rate_control_unregister(); |
be663ab6 WYG |
3236 | return ret; |
3237 | } | |
3238 | ||
e2ebc833 | 3239 | static void __exit il4965_exit(void) |
be663ab6 | 3240 | { |
e2ebc833 SG |
3241 | pci_unregister_driver(&il4965_driver); |
3242 | il4965_rate_control_unregister(); | |
be663ab6 WYG |
3243 | } |
3244 | ||
e2ebc833 SG |
3245 | module_exit(il4965_exit); |
3246 | module_init(il4965_init); | |
be663ab6 | 3247 | |
d3175167 | 3248 | #ifdef CONFIG_IWLEGACY_DEBUG |
d2ddf621 | 3249 | module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR); |
be663ab6 WYG |
3250 | MODULE_PARM_DESC(debug, "debug output mask"); |
3251 | #endif | |
3252 | ||
e2ebc833 | 3253 | module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO); |
be663ab6 | 3254 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); |
e2ebc833 | 3255 | module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO); |
be663ab6 | 3256 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
e2ebc833 | 3257 | module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO); |
be663ab6 | 3258 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); |
e2ebc833 | 3259 | module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, |
be663ab6 WYG |
3260 | int, S_IRUGO); |
3261 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
e2ebc833 | 3262 | module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO); |
be663ab6 | 3263 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); |