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iwlwifi: implement iwl_debug_report_frame for iwlagn
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
82b9a121 41#include "iwl-3945-core.h"
b481de9c 42#include "iwl-3945.h"
5d08cd1d 43#include "iwl-helpers.h"
b481de9c
ZY		 44#include "iwl-3945-rs.h"
45
46#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_##r##M_IEEE, \
49 IWL_RATE_##ip##M_INDEX, \
50 IWL_RATE_##in##M_INDEX, \
51 IWL_RATE_##rp##M_INDEX, \
52 IWL_RATE_##rn##M_INDEX, \
53 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 54 IWL_RATE_##np##M_INDEX, \
55 IWL_RATE_##r##M_INDEX_TABLE, \
56 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 57
58/*
59 * Parameter order:
60 * rate, prev rate, next rate, prev tgg rate, next tgg rate
61 *
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
64 *
65 */
bb8c093b 66const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
14577f23
MA		 67 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 71 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 79};
80
bb8c093b 81/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 82#define IWL_EVT_DISABLE (0)
83#define IWL_EVT_DISABLE_SIZE (1532/32)
84
85/**
bb8c093b 86 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 87 *
88 * Disable an event by writing "1"s into "disable"
89 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
90 * Default values of 0 enable uCode events to be logged.
91 * Use for only special debugging. This function is just a placeholder as-is,
92 * you'll need to provide the special bits! ...
93 * ... and set IWL_EVT_DISABLE to 1. */
bb8c093b 94void iwl3945_disable_events(struct iwl3945_priv *priv)
b481de9c 95{
af7cca2a 96 int ret;
b481de9c
ZY		 97 int i;
98 u32 base; /* SRAM address of event log header */
99 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
100 u32 array_size; /* # of u32 entries in array */
101 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
102 0x00000000, /* 31 - 0 Event id numbers */
103 0x00000000, /* 63 - 32 */
104 0x00000000, /* 95 - 64 */
105 0x00000000, /* 127 - 96 */
106 0x00000000, /* 159 - 128 */
107 0x00000000, /* 191 - 160 */
108 0x00000000, /* 223 - 192 */
109 0x00000000, /* 255 - 224 */
110 0x00000000, /* 287 - 256 */
111 0x00000000, /* 319 - 288 */
112 0x00000000, /* 351 - 320 */
113 0x00000000, /* 383 - 352 */
114 0x00000000, /* 415 - 384 */
115 0x00000000, /* 447 - 416 */
116 0x00000000, /* 479 - 448 */
117 0x00000000, /* 511 - 480 */
118 0x00000000, /* 543 - 512 */
119 0x00000000, /* 575 - 544 */
120 0x00000000, /* 607 - 576 */
121 0x00000000, /* 639 - 608 */
122 0x00000000, /* 671 - 640 */
123 0x00000000, /* 703 - 672 */
124 0x00000000, /* 735 - 704 */
125 0x00000000, /* 767 - 736 */
126 0x00000000, /* 799 - 768 */
127 0x00000000, /* 831 - 800 */
128 0x00000000, /* 863 - 832 */
129 0x00000000, /* 895 - 864 */
130 0x00000000, /* 927 - 896 */
131 0x00000000, /* 959 - 928 */
132 0x00000000, /* 991 - 960 */
133 0x00000000, /* 1023 - 992 */
134 0x00000000, /* 1055 - 1024 */
135 0x00000000, /* 1087 - 1056 */
136 0x00000000, /* 1119 - 1088 */
137 0x00000000, /* 1151 - 1120 */
138 0x00000000, /* 1183 - 1152 */
139 0x00000000, /* 1215 - 1184 */
140 0x00000000, /* 1247 - 1216 */
141 0x00000000, /* 1279 - 1248 */
142 0x00000000, /* 1311 - 1280 */
143 0x00000000, /* 1343 - 1312 */
144 0x00000000, /* 1375 - 1344 */
145 0x00000000, /* 1407 - 1376 */
146 0x00000000, /* 1439 - 1408 */
147 0x00000000, /* 1471 - 1440 */
148 0x00000000, /* 1503 - 1472 */
149 };
150
151 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 152 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 153 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
154 return;
155 }
156
bb8c093b 157 ret = iwl3945_grab_nic_access(priv);
af7cca2a 158 if (ret) {
b481de9c
ZY		 159 IWL_WARNING("Can not read from adapter at this time.\n");
160 return;
161 }
162
bb8c093b
CH		 163 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
165 iwl3945_release_nic_access(priv);
b481de9c
ZY		 166
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
168 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
169 disable_ptr);
bb8c093b 170 ret = iwl3945_grab_nic_access(priv);
b481de9c 171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
bb8c093b 172 iwl3945_write_targ_mem(priv,
af7cca2a
TW		 173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
b481de9c 175
bb8c093b 176 iwl3945_release_nic_access(priv);
b481de9c
ZY		 177 } else {
178 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
179 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
180 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
181 disable_ptr, array_size);
182 }
183
184}
185
17744ff6
TW		 186static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
187{
188 int idx;
189
190 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
191 if (iwl3945_rates[idx].plcp == plcp)
192 return idx;
193 return -1;
194}
195
b481de9c
ZY		 196/**
197 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
198 * @priv: eeprom and antenna fields are used to determine antenna flags
199 *
200 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
201 * priv->antenna specifies the antenna diversity mode:
202 *
a96a27f9 203 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
b481de9c
ZY		 204 * IWL_ANTENNA_MAIN - Force MAIN antenna
205 * IWL_ANTENNA_AUX - Force AUX antenna
206 */
bb8c093b 207__le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
b481de9c
ZY		 208{
209 switch (priv->antenna) {
210 case IWL_ANTENNA_DIVERSITY:
211 return 0;
212
213 case IWL_ANTENNA_MAIN:
214 if (priv->eeprom.antenna_switch_type)
215 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
216 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
217
218 case IWL_ANTENNA_AUX:
219 if (priv->eeprom.antenna_switch_type)
220 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
221 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
222 }
223
224 /* bad antenna selector value */
225 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
226 return 0; /* "diversity" is default if error */
227}
228
91c066f2
TW		 229#ifdef CONFIG_IWL3945_DEBUG
230#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
231
232static const char *iwl3945_get_tx_fail_reason(u32 status)
233{
234 switch (status & TX_STATUS_MSK) {
235 case TX_STATUS_SUCCESS:
236 return "SUCCESS";
237 TX_STATUS_ENTRY(SHORT_LIMIT);
238 TX_STATUS_ENTRY(LONG_LIMIT);
239 TX_STATUS_ENTRY(FIFO_UNDERRUN);
240 TX_STATUS_ENTRY(MGMNT_ABORT);
241 TX_STATUS_ENTRY(NEXT_FRAG);
242 TX_STATUS_ENTRY(LIFE_EXPIRE);
243 TX_STATUS_ENTRY(DEST_PS);
244 TX_STATUS_ENTRY(ABORTED);
245 TX_STATUS_ENTRY(BT_RETRY);
246 TX_STATUS_ENTRY(STA_INVALID);
247 TX_STATUS_ENTRY(FRAG_DROPPED);
248 TX_STATUS_ENTRY(TID_DISABLE);
249 TX_STATUS_ENTRY(FRAME_FLUSHED);
250 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
251 TX_STATUS_ENTRY(TX_LOCKED);
252 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
253 }
254
255 return "UNKNOWN";
256}
257#else
258static inline const char *iwl3945_get_tx_fail_reason(u32 status)
259{
260 return "";
261}
262#endif
263
e6a9854b
JB		 264/*
265 * get ieee prev rate from rate scale table.
266 * for A and B mode we need to overright prev
267 * value
268 */
269int iwl3945_rs_next_rate(struct iwl3945_priv *priv, int rate)
270{
271 int next_rate = iwl3945_get_prev_ieee_rate(rate);
272
273 switch (priv->band) {
274 case IEEE80211_BAND_5GHZ:
275 if (rate == IWL_RATE_12M_INDEX)
276 next_rate = IWL_RATE_9M_INDEX;
277 else if (rate == IWL_RATE_6M_INDEX)
278 next_rate = IWL_RATE_6M_INDEX;
279 break;
280/* XXX cannot be invoked in current mac80211 so not a regression
281 case MODE_IEEE80211B:
282 if (rate == IWL_RATE_11M_INDEX_TABLE)
283 next_rate = IWL_RATE_5M_INDEX_TABLE;
284 break;
285 */
286 default:
287 break;
288 }
289
290 return next_rate;
291}
292
91c066f2
TW		 293
294/**
295 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
296 *
297 * When FW advances 'R' index, all entries between old and new 'R' index
298 * need to be reclaimed. As result, some free space forms. If there is
299 * enough free space (> low mark), wake the stack that feeds us.
300 */
301static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
302 int txq_id, int index)
303{
304 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
305 struct iwl3945_queue *q = &txq->q;
306 struct iwl3945_tx_info *tx_info;
307
308 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
309
310 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
311 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
312
313 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 314 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2
TW		 315 tx_info->skb[0] = NULL;
316 iwl3945_hw_txq_free_tfd(priv, txq);
317 }
318
319 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
320 (txq_id != IWL_CMD_QUEUE_NUM) &&
321 priv->mac80211_registered)
322 ieee80211_wake_queue(priv->hw, txq_id);
323}
324
325/**
326 * iwl3945_rx_reply_tx - Handle Tx response
327 */
328static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
329 struct iwl3945_rx_mem_buffer *rxb)
330{
331 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
332 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
333 int txq_id = SEQ_TO_QUEUE(sequence);
334 int index = SEQ_TO_INDEX(sequence);
335 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 336 struct ieee80211_tx_info *info;
91c066f2
TW		 337 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
338 u32 status = le32_to_cpu(tx_resp->status);
339 int rate_idx;
74221d07 340 int fail;
91c066f2
TW		 341
342 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
343 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
344 "is out of range [0-%d] %d %d\n", txq_id,
345 index, txq->q.n_bd, txq->q.write_ptr,
346 txq->q.read_ptr);
347 return;
348 }
349
e039fa4a 350 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 351 ieee80211_tx_info_clear_status(info);
352
353 /* Fill the MRR chain with some info about on-chip retransmissions */
354 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
355 if (info->band == IEEE80211_BAND_5GHZ)
356 rate_idx -= IWL_FIRST_OFDM_RATE;
357
358 fail = tx_resp->failure_frame;
74221d07
AM		 359
360 info->status.rates[0].idx = rate_idx;
361 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 362
91c066f2 363 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 364 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
365 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 366
367 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
368 txq_id, iwl3945_get_tx_fail_reason(status), status,
369 tx_resp->rate, tx_resp->failure_frame);
370
91c066f2
TW		 371 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
372 iwl3945_tx_queue_reclaim(priv, txq_id, index);
373
374 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
375 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
376}
377
378
379
b481de9c
ZY		 380/*****************************************************************************
381 *
382 * Intel PRO/Wireless 3945ABG/BG Network Connection
383 *
384 * RX handler implementations
385 *
b481de9c
ZY		 386 *****************************************************************************/
387
bb8c093b 388void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 389{
bb8c093b 390 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 391 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 392 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 393 le32_to_cpu(pkt->len));
394
395 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
396
ab53d8af
MA		 397 iwl3945_led_background(priv);
398
b481de9c
ZY		 399 priv->last_statistics_time = jiffies;
400}
401
17744ff6
TW		 402/******************************************************************************
403 *
404 * Misc. internal state and helper functions
405 *
406 ******************************************************************************/
407#ifdef CONFIG_IWL3945_DEBUG
408
409/**
410 * iwl3945_report_frame - dump frame to syslog during debug sessions
411 *
412 * You may hack this function to show different aspects of received frames,
413 * including selective frame dumps.
414 * group100 parameter selects whether to show 1 out of 100 good frames.
415 */
416static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
417 struct iwl3945_rx_packet *pkt,
418 struct ieee80211_hdr *header, int group100)
419{
420 u32 to_us;
421 u32 print_summary = 0;
422 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
423 u32 hundred = 0;
424 u32 dataframe = 0;
fd7c8a40 425 __le16 fc;
17744ff6
TW		 426 u16 seq_ctl;
427 u16 channel;
428 u16 phy_flags;
429 u16 length;
430 u16 status;
431 u16 bcn_tmr;
432 u32 tsf_low;
433 u64 tsf;
434 u8 rssi;
435 u8 agc;
436 u16 sig_avg;
437 u16 noise_diff;
438 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
439 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
440 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
441 u8 *data = IWL_RX_DATA(pkt);
442
443 /* MAC header */
fd7c8a40 444 fc = header->frame_control;
17744ff6
TW		 445 seq_ctl = le16_to_cpu(header->seq_ctrl);
446
447 /* metadata */
448 channel = le16_to_cpu(rx_hdr->channel);
449 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
450 length = le16_to_cpu(rx_hdr->len);
451
452 /* end-of-frame status and timestamp */
453 status = le32_to_cpu(rx_end->status);
454 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
455 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
456 tsf = le64_to_cpu(rx_end->timestamp);
457
458 /* signal statistics */
459 rssi = rx_stats->rssi;
460 agc = rx_stats->agc;
461 sig_avg = le16_to_cpu(rx_stats->sig_avg);
462 noise_diff = le16_to_cpu(rx_stats->noise_diff);
463
464 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
465
466 /* if data frame is to us and all is good,
467 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 468 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
469 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 470 dataframe = 1;
471 if (!group100)
472 print_summary = 1; /* print each frame */
473 else if (priv->framecnt_to_us < 100) {
474 priv->framecnt_to_us++;
475 print_summary = 0;
476 } else {
477 priv->framecnt_to_us = 0;
478 print_summary = 1;
479 hundred = 1;
480 }
481 } else {
482 /* print summary for all other frames */
483 print_summary = 1;
484 }
485
486 if (print_summary) {
487 char *title;
0ff1cca0 488 int rate;
17744ff6
TW		 489
490 if (hundred)
491 title = "100Frames";
fd7c8a40 492 else if (ieee80211_has_retry(fc))
17744ff6 493 title = "Retry";
fd7c8a40 494 else if (ieee80211_is_assoc_resp(fc))
17744ff6 495 title = "AscRsp";
fd7c8a40 496 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 497 title = "RasRsp";
fd7c8a40 498 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 499 title = "PrbRsp";
500 print_dump = 1; /* dump frame contents */
501 } else if (ieee80211_is_beacon(fc)) {
502 title = "Beacon";
503 print_dump = 1; /* dump frame contents */
504 } else if (ieee80211_is_atim(fc))
505 title = "ATIM";
506 else if (ieee80211_is_auth(fc))
507 title = "Auth";
508 else if (ieee80211_is_deauth(fc))
509 title = "DeAuth";
510 else if (ieee80211_is_disassoc(fc))
511 title = "DisAssoc";
512 else
513 title = "Frame";
514
515 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
516 if (rate == -1)
517 rate = 0;
518 else
519 rate = iwl3945_rates[rate].ieee / 2;
520
521 /* print frame summary.
522 * MAC addresses show just the last byte (for brevity),
523 * but you can hack it to show more, if you'd like to. */
524 if (dataframe)
525 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 526 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 527 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 528 length, rssi, channel, rate);
529 else {
530 /* src/dst addresses assume managed mode */
531 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
532 "src=0x%02x, rssi=%u, tim=%lu usec, "
533 "phy=0x%02x, chnl=%d\n",
fd7c8a40 534 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 535 header->addr3[5], rssi,
536 tsf_low - priv->scan_start_tsf,
537 phy_flags, channel);
538 }
539 }
540 if (print_dump)
541 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
542}
543#else
544static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
545 struct iwl3945_rx_packet *pkt,
546 struct ieee80211_hdr *header, int group100)
547{
548}
549#endif
550
4bd9b4f3
AG		 551/* This is necessary only for a number of statistics, see the caller. */
552static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
553 struct ieee80211_hdr *header)
554{
555 /* Filter incoming packets to determine if they are targeted toward
556 * this network, discarding packets coming from ourselves */
557 switch (priv->iw_mode) {
05c914fe 558 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 559 /* packets to our IBSS update information */
560 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 561 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 562 /* packets to our IBSS update information */
563 return !compare_ether_addr(header->addr2, priv->bssid);
564 default:
565 return 1;
566 }
567}
17744ff6 568
4bd9b4f3 569static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
bb8c093b 570 struct iwl3945_rx_mem_buffer *rxb,
12342c47 571 struct ieee80211_rx_status *stats)
b481de9c 572{
bb8c093b 573 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
699669f3 574#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 575 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 576#endif
bb8c093b
CH		 577 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
578 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 579 short len = le16_to_cpu(rx_hdr->len);
580
581 /* We received data from the HW, so stop the watchdog */
582 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
583 IWL_DEBUG_DROP("Corruption detected!\n");
584 return;
585 }
586
587 /* We only process data packets if the interface is open */
588 if (unlikely(!priv->is_open)) {
589 IWL_DEBUG_DROP_LIMIT
590 ("Dropping packet while interface is not open.\n");
591 return;
592 }
b481de9c
ZY		 593
594 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
595 /* Set the size of the skb to the size of the frame */
596 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
597
bb8c093b
CH		 598 if (iwl3945_param_hwcrypto)
599 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 600 le32_to_cpu(rx_end->status), stats);
601
ab53d8af 602#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 603 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 604 priv->rxtxpackets += len;
605#endif
b481de9c
ZY		 606 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
607 rxb->skb = NULL;
608}
609
7878a5a4
MA		 610#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
611
bb8c093b
CH		 612static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
613 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 614{
17744ff6
TW		 615 struct ieee80211_hdr *header;
616 struct ieee80211_rx_status rx_status;
bb8c093b
CH		 617 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
618 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
619 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
620 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 621 int snr;
b481de9c
ZY		 622 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
623 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 624 u8 network_packet;
17744ff6 625
17744ff6
TW		 626 rx_status.flag = 0;
627 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 628 rx_status.freq =
c0186078 629 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 630 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
631 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
632
633 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 634 if (rx_status.band == IEEE80211_BAND_5GHZ)
635 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 636
6f0a2c4d
BR		 637 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
638 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
639
640 /* set the preamble flag if appropriate */
641 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
642 rx_status.flag |= RX_FLAG_SHORTPRE;
643
b481de9c
ZY		 644 if ((unlikely(rx_stats->phy_count > 20))) {
645 IWL_DEBUG_DROP
646 ("dsp size out of range [0,20]: "
647 "%d/n", rx_stats->phy_count);
648 return;
649 }
650
651 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
652 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
653 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
654 return;
655 }
656
56decd3c 657
b481de9c
ZY		 658
659 /* Convert 3945's rssi indicator to dBm */
566bfe5a 660 rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
b481de9c
ZY		 661
662 /* Set default noise value to -127 */
663 if (priv->last_rx_noise == 0)
664 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
665
666 /* 3945 provides noise info for OFDM frames only.
667 * sig_avg and noise_diff are measured by the 3945's digital signal
668 * processor (DSP), and indicate linear levels of signal level and
669 * distortion/noise within the packet preamble after
670 * automatic gain control (AGC). sig_avg should stay fairly
671 * constant if the radio's AGC is working well.
672 * Since these values are linear (not dB or dBm), linear
673 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
674 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
675 * to obtain noise level in dBm.
17744ff6 676 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 677 if (rx_stats_noise_diff) {
678 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 679 rx_status.noise = rx_status.signal -
17744ff6 680 iwl3945_calc_db_from_ratio(snr);
566bfe5a 681 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 682 rx_status.noise);
b481de9c
ZY		 683
684 /* If noise info not available, calculate signal quality indicator (%)
685 * using just the dBm signal level. */
686 } else {
17744ff6 687 rx_status.noise = priv->last_rx_noise;
566bfe5a 688 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 689 }
690
691
692 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 693 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 694 rx_stats_sig_avg, rx_stats_noise_diff);
695
b481de9c
ZY		 696 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
697
bb8c093b 698 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 699
17744ff6
TW		 700 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
701 network_packet ? '*' : ' ',
702 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 703 rx_status.signal, rx_status.signal,
704 rx_status.noise, rx_status.rate_idx);
b481de9c 705
17744ff6 706#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 707 if (iwl3945_debug_level & (IWL_DL_RX))
b481de9c 708 /* Set "1" to report good data frames in groups of 100 */
17744ff6 709 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 710#endif
711
712 if (network_packet) {
713 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
714 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 715 priv->last_rx_rssi = rx_status.signal;
17744ff6 716 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 717 }
718
12e5e22d 719 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 720}
721
bb8c093b 722int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
b481de9c
ZY		 723 dma_addr_t addr, u16 len)
724{
725 int count;
726 u32 pad;
bb8c093b 727 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 728
729 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
730 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
731
732 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
733 IWL_ERROR("Error can not send more than %d chunks\n",
734 NUM_TFD_CHUNKS);
735 return -EINVAL;
736 }
737
738 tfd->pa[count].addr = cpu_to_le32(addr);
739 tfd->pa[count].len = cpu_to_le32(len);
740
741 count++;
742
743 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
744 TFD_CTL_PAD_SET(pad));
745
746 return 0;
747}
748
749/**
bb8c093b 750 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 751 *
752 * Does NOT advance any indexes
753 */
bb8c093b 754int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 755{
bb8c093b
CH		 756 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
757 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 758 struct pci_dev *dev = priv->pci_dev;
759 int i;
760 int counter;
761
762 /* classify bd */
763 if (txq->q.id == IWL_CMD_QUEUE_NUM)
764 /* nothing to cleanup after for host commands */
765 return 0;
766
767 /* sanity check */
768 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
769 if (counter > NUM_TFD_CHUNKS) {
770 IWL_ERROR("Too many chunks: %i\n", counter);
771 /* @todo issue fatal error, it is quite serious situation */
772 return 0;
773 }
774
775 /* unmap chunks if any */
776
777 for (i = 1; i < counter; i++) {
778 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
779 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 780 if (txq->txb[txq->q.read_ptr].skb[0]) {
781 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
782 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 783 /* Can be called from interrupt context */
784 dev_kfree_skb_any(skb);
fc4b6853 785 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 786 }
787 }
788 }
789 return 0;
790}
791
bb8c093b 792u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
b481de9c 793{
c93007ef 794 int i, start = IWL_AP_ID;
b481de9c
ZY		 795 int ret = IWL_INVALID_STATION;
796 unsigned long flags;
797
c93007ef
SO		 798 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
799 (priv->iw_mode == NL80211_IFTYPE_AP))
800 start = IWL_STA_ID;
801
802 if (is_broadcast_ether_addr(addr))
803 return priv->hw_setting.bcast_sta_id;
804
b481de9c 805 spin_lock_irqsave(&priv->sta_lock, flags);
c93007ef 806 for (i = start; i < priv->hw_setting.max_stations; i++)
b481de9c
ZY		 807 if ((priv->stations[i].used) &&
808 (!compare_ether_addr
809 (priv->stations[i].sta.sta.addr, addr))) {
810 ret = i;
811 goto out;
812 }
813
e174961c
JB		 814 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
815 addr, priv->num_stations);
b481de9c
ZY		 816 out:
817 spin_unlock_irqrestore(&priv->sta_lock, flags);
818 return ret;
819}
820
821/**
bb8c093b 822 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 823 *
824*/
bb8c093b
CH		 825void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
826 struct iwl3945_cmd *cmd,
e039fa4a 827 struct ieee80211_tx_info *info,
b481de9c
ZY		 828 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
829{
830 unsigned long flags;
e039fa4a 831 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 832 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 833 u16 rate_mask;
834 int rate;
835 u8 rts_retry_limit;
836 u8 data_retry_limit;
837 __le32 tx_flags;
fd7c8a40 838 __le16 fc = hdr->frame_control;
b481de9c 839
bb8c093b 840 rate = iwl3945_rates[rate_index].plcp;
b481de9c
ZY		 841 tx_flags = cmd->cmd.tx.tx_flags;
842
843 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 844 * in this running context */
b481de9c
ZY		 845 rate_mask = IWL_RATES_MASK;
846
847 spin_lock_irqsave(&priv->sta_lock, flags);
848
849 priv->stations[sta_id].current_rate.rate_n_flags = rate;
850
05c914fe 851 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
a4062b8f 852 (sta_id != priv->hw_setting.bcast_sta_id) &&
b481de9c
ZY		 853 (sta_id != IWL_MULTICAST_ID))
854 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
855
856 spin_unlock_irqrestore(&priv->sta_lock, flags);
857
858 if (tx_id >= IWL_CMD_QUEUE_NUM)
859 rts_retry_limit = 3;
860 else
861 rts_retry_limit = 7;
862
fd7c8a40 863 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 864 data_retry_limit = 3;
865 if (data_retry_limit < rts_retry_limit)
866 rts_retry_limit = data_retry_limit;
867 } else
868 data_retry_limit = IWL_DEFAULT_TX_RETRY;
869
870 if (priv->data_retry_limit != -1)
871 data_retry_limit = priv->data_retry_limit;
872
fd7c8a40
HH		 873 if (ieee80211_is_mgmt(fc)) {
874 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
875 case cpu_to_le16(IEEE80211_STYPE_AUTH):
876 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
877 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
878 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 879 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
880 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
881 tx_flags |= TX_CMD_FLG_CTS_MSK;
882 }
883 break;
884 default:
885 break;
886 }
887 }
888
889 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
890 cmd->cmd.tx.data_retry_limit = data_retry_limit;
891 cmd->cmd.tx.rate = rate;
892 cmd->cmd.tx.tx_flags = tx_flags;
893
894 /* OFDM */
14577f23
MA		 895 cmd->cmd.tx.supp_rates[0] =
896 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 897
898 /* CCK */
14577f23 899 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 900
901 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
902 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
903 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
904 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
905}
906
bb8c093b 907u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 908{
909 unsigned long flags_spin;
bb8c093b 910 struct iwl3945_station_entry *station;
b481de9c
ZY		 911
912 if (sta_id == IWL_INVALID_STATION)
913 return IWL_INVALID_STATION;
914
915 spin_lock_irqsave(&priv->sta_lock, flags_spin);
916 station = &priv->stations[sta_id];
917
918 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
919 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
920 station->current_rate.rate_n_flags = tx_rate;
921 station->sta.mode = STA_CONTROL_MODIFY_MSK;
922
923 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
924
bb8c093b 925 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 926 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
927 sta_id, tx_rate);
928 return sta_id;
929}
930
bb8c093b 931static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
b481de9c
ZY		 932{
933 int rc;
934 unsigned long flags;
935
936 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 937 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 938 if (rc) {
939 spin_unlock_irqrestore(&priv->lock, flags);
940 return rc;
941 }
942
943 if (!pwr_max) {
944 u32 val;
945
946 rc = pci_read_config_dword(priv->pci_dev,
947 PCI_POWER_SOURCE, &val);
948 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
bb8c093b 949 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 950 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
951 ~APMG_PS_CTRL_MSK_PWR_SRC);
bb8c093b 952 iwl3945_release_nic_access(priv);
b481de9c 953
bb8c093b 954 iwl3945_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 955 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
956 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
957 } else
bb8c093b 958 iwl3945_release_nic_access(priv);
b481de9c 959 } else {
bb8c093b 960 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 961 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
962 ~APMG_PS_CTRL_MSK_PWR_SRC);
963
bb8c093b
CH		 964 iwl3945_release_nic_access(priv);
965 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 966 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
967 }
968 spin_unlock_irqrestore(&priv->lock, flags);
969
970 return rc;
971}
972
bb8c093b 973static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 974{
975 int rc;
976 unsigned long flags;
977
978 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 979 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 980 if (rc) {
981 spin_unlock_irqrestore(&priv->lock, flags);
982 return rc;
983 }
984
bb8c093b
CH		 985 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
986 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
b481de9c 987 priv->hw_setting.shared_phys +
bb8c093b
CH		 988 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
989 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
990 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
b481de9c
ZY		 991 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
992 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
993 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
994 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
995 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
996 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
997 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
998 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
999
1000 /* fake read to flush all prev I/O */
bb8c093b 1001 iwl3945_read_direct32(priv, FH_RSSR_CTRL);
b481de9c 1002
bb8c093b 1003 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1004 spin_unlock_irqrestore(&priv->lock, flags);
1005
1006 return 0;
1007}
1008
bb8c093b 1009static int iwl3945_tx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1010{
1011 int rc;
1012 unsigned long flags;
1013
1014 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1015 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1016 if (rc) {
1017 spin_unlock_irqrestore(&priv->lock, flags);
1018 return rc;
1019 }
1020
1021 /* bypass mode */
bb8c093b 1022 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1023
1024 /* RA 0 is active */
bb8c093b 1025 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1026
1027 /* all 6 fifo are active */
bb8c093b 1028 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1029
bb8c093b
CH		 1030 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1031 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1032 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1033 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1034
bb8c093b 1035 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
b481de9c
ZY		 1036 priv->hw_setting.shared_phys);
1037
bb8c093b 1038 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
b481de9c
ZY		 1039 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1040 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1041 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1042 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1043 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1044 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1045 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1046
bb8c093b 1047 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1048 spin_unlock_irqrestore(&priv->lock, flags);
1049
1050 return 0;
1051}
1052
1053/**
1054 * iwl3945_txq_ctx_reset - Reset TX queue context
1055 *
1056 * Destroys all DMA structures and initialize them again
1057 */
bb8c093b 1058static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1059{
1060 int rc;
1061 int txq_id, slots_num;
1062
bb8c093b 1063 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1064
1065 /* Tx CMD queue */
1066 rc = iwl3945_tx_reset(priv);
1067 if (rc)
1068 goto error;
1069
1070 /* Tx queue(s) */
1071 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1072 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1073 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 1074 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 1075 txq_id);
1076 if (rc) {
1077 IWL_ERROR("Tx %d queue init failed\n", txq_id);
1078 goto error;
1079 }
1080 }
1081
1082 return rc;
1083
1084 error:
bb8c093b 1085 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1086 return rc;
1087}
1088
bb8c093b 1089int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
b481de9c
ZY		 1090{
1091 u8 rev_id;
1092 int rc;
1093 unsigned long flags;
bb8c093b 1094 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 1095
bb8c093b 1096 iwl3945_power_init_handle(priv);
b481de9c
ZY		 1097
1098 spin_lock_irqsave(&priv->lock, flags);
a693f187 1099 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
bb8c093b 1100 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 1101 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1102
bb8c093b
CH		 1103 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1104 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1105 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1106 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1107 if (rc < 0) {
1108 spin_unlock_irqrestore(&priv->lock, flags);
1109 IWL_DEBUG_INFO("Failed to init the card\n");
1110 return rc;
1111 }
1112
bb8c093b 1113 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1114 if (rc) {
1115 spin_unlock_irqrestore(&priv->lock, flags);
1116 return rc;
1117 }
bb8c093b 1118 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1119 APMG_CLK_VAL_DMA_CLK_RQT |
1120 APMG_CLK_VAL_BSM_CLK_RQT);
1121 udelay(20);
bb8c093b 1122 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c 1123 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
bb8c093b 1124 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1125 spin_unlock_irqrestore(&priv->lock, flags);
1126
1127 /* Determine HW type */
1128 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1129 if (rc)
1130 return rc;
1131 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1132
1133 iwl3945_nic_set_pwr_src(priv, 1);
1134 spin_lock_irqsave(&priv->lock, flags);
1135
1136 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1137 IWL_DEBUG_INFO("RTP type \n");
1138 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1139 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
bb8c093b 1140 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1141 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1142 } else {
6f83eaa1 1143 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
bb8c093b 1144 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1145 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1146 }
1147
b481de9c
ZY		 1148 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1149 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
bb8c093b 1150 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1151 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1152 } else
1153 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1154
1155 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1156 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1157 priv->eeprom.board_revision);
bb8c093b 1158 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1159 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1160 } else {
1161 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1162 priv->eeprom.board_revision);
bb8c093b 1163 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1164 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1165 }
1166
1167 if (priv->eeprom.almgor_m_version <= 1) {
bb8c093b 1168 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1169 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c
ZY		 1170 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1171 priv->eeprom.almgor_m_version);
1172 } else {
1173 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1174 priv->eeprom.almgor_m_version);
bb8c093b 1175 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1176 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1177 }
1178 spin_unlock_irqrestore(&priv->lock, flags);
1179
1180 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1181 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1182
1183 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1184 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1185
1186 /* Allocate the RX queue, or reset if it is already allocated */
1187 if (!rxq->bd) {
bb8c093b 1188 rc = iwl3945_rx_queue_alloc(priv);
b481de9c
ZY		 1189 if (rc) {
1190 IWL_ERROR("Unable to initialize Rx queue\n");
1191 return -ENOMEM;
1192 }
1193 } else
bb8c093b 1194 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1195
bb8c093b 1196 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1197
1198 iwl3945_rx_init(priv, rxq);
1199
1200 spin_lock_irqsave(&priv->lock, flags);
1201
1202 /* Look at using this instead:
1203 rxq->need_update = 1;
bb8c093b 1204 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1205 */
1206
bb8c093b 1207 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1208 if (rc) {
1209 spin_unlock_irqrestore(&priv->lock, flags);
1210 return rc;
1211 }
bb8c093b
CH		 1212 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1213 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1214
1215 spin_unlock_irqrestore(&priv->lock, flags);
1216
1217 rc = iwl3945_txq_ctx_reset(priv);
1218 if (rc)
1219 return rc;
1220
1221 set_bit(STATUS_INIT, &priv->status);
1222
1223 return 0;
1224}
1225
1226/**
bb8c093b 1227 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1228 *
1229 * Destroy all TX DMA queues and structures
1230 */
bb8c093b 1231void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
b481de9c
ZY		 1232{
1233 int txq_id;
1234
1235 /* Tx queues */
1236 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
bb8c093b 1237 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c
ZY		 1238}
1239
bb8c093b 1240void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 1241{
1242 int queue;
1243 unsigned long flags;
1244
1245 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1246 if (iwl3945_grab_nic_access(priv)) {
b481de9c 1247 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1248 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1249 return;
1250 }
1251
1252 /* stop SCD */
bb8c093b 1253 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1254
1255 /* reset TFD queues */
1256 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
bb8c093b
CH		 1257 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1258 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
b481de9c
ZY		 1259 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1260 1000);
1261 }
1262
bb8c093b 1263 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1264 spin_unlock_irqrestore(&priv->lock, flags);
1265
bb8c093b 1266 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1267}
1268
bb8c093b 1269int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
b481de9c
ZY		 1270{
1271 int rc = 0;
1272 u32 reg_val;
1273 unsigned long flags;
1274
1275 spin_lock_irqsave(&priv->lock, flags);
1276
1277 /* set stop master bit */
bb8c093b 1278 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1279
bb8c093b 1280 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 1281
1282 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1283 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1284 IWL_DEBUG_INFO("Card in power save, master is already "
1285 "stopped\n");
1286 else {
bb8c093b 1287 rc = iwl3945_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 1288 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1289 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1290 if (rc < 0) {
1291 spin_unlock_irqrestore(&priv->lock, flags);
1292 return rc;
1293 }
1294 }
1295
1296 spin_unlock_irqrestore(&priv->lock, flags);
1297 IWL_DEBUG_INFO("stop master\n");
1298
1299 return rc;
1300}
1301
bb8c093b 1302int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1303{
1304 int rc;
1305 unsigned long flags;
1306
bb8c093b 1307 iwl3945_hw_nic_stop_master(priv);
b481de9c
ZY		 1308
1309 spin_lock_irqsave(&priv->lock, flags);
1310
bb8c093b 1311 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1312
bb8c093b 1313 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1314 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1315 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1316
bb8c093b 1317 rc = iwl3945_grab_nic_access(priv);
b481de9c 1318 if (!rc) {
bb8c093b 1319 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1320 APMG_CLK_VAL_BSM_CLK_RQT);
1321
1322 udelay(10);
1323
bb8c093b 1324 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1325 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1326
bb8c093b
CH		 1327 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1328 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1329 0xFFFFFFFF);
1330
1331 /* enable DMA */
bb8c093b 1332 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1333 APMG_CLK_VAL_DMA_CLK_RQT |
1334 APMG_CLK_VAL_BSM_CLK_RQT);
1335 udelay(10);
1336
bb8c093b 1337 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1338 APMG_PS_CTRL_VAL_RESET_REQ);
1339 udelay(5);
bb8c093b 1340 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1341 APMG_PS_CTRL_VAL_RESET_REQ);
bb8c093b 1342 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1343 }
1344
1345 /* Clear the 'host command active' bit... */
1346 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1347
1348 wake_up_interruptible(&priv->wait_command_queue);
1349 spin_unlock_irqrestore(&priv->lock, flags);
1350
1351 return rc;
1352}
1353
1354/**
bb8c093b 1355 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1356 * return index delta into power gain settings table
1357*/
bb8c093b 1358static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1359{
1360 return (new_reading - old_reading) * (-11) / 100;
1361}
1362
1363/**
bb8c093b 1364 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1365 */
bb8c093b 1366static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1367{
3ac7f146 1368 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1369}
1370
bb8c093b 1371int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
b481de9c 1372{
bb8c093b 1373 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1374}
1375
1376/**
bb8c093b 1377 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1378 * get the current temperature by reading from NIC
1379*/
bb8c093b 1380static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
b481de9c
ZY		 1381{
1382 int temperature;
1383
bb8c093b 1384 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1385
1386 /* driver's okay range is -260 to +25.
1387 * human readable okay range is 0 to +285 */
1388 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1389
1390 /* handle insane temp reading */
bb8c093b 1391 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
b481de9c
ZY		 1392 IWL_ERROR("Error bad temperature value %d\n", temperature);
1393
1394 /* if really really hot(?),
1395 * substitute the 3rd band/group's temp measured at factory */
1396 if (priv->last_temperature > 100)
1397 temperature = priv->eeprom.groups[2].temperature;
1398 else /* else use most recent "sane" value from driver */
1399 temperature = priv->last_temperature;
1400 }
1401
1402 return temperature; /* raw, not "human readable" */
1403}
1404
1405/* Adjust Txpower only if temperature variance is greater than threshold.
1406 *
1407 * Both are lower than older versions' 9 degrees */
1408#define IWL_TEMPERATURE_LIMIT_TIMER 6
1409
1410/**
1411 * is_temp_calib_needed - determines if new calibration is needed
1412 *
1413 * records new temperature in tx_mgr->temperature.
1414 * replaces tx_mgr->last_temperature *only* if calib needed
1415 * (assumes caller will actually do the calibration!). */
bb8c093b 1416static int is_temp_calib_needed(struct iwl3945_priv *priv)
b481de9c
ZY		 1417{
1418 int temp_diff;
1419
bb8c093b 1420 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1421 temp_diff = priv->temperature - priv->last_temperature;
1422
1423 /* get absolute value */
1424 if (temp_diff < 0) {
1425 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1426 temp_diff = -temp_diff;
1427 } else if (temp_diff == 0)
1428 IWL_DEBUG_POWER("Same temp,\n");
1429 else
1430 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1431
1432 /* if we don't need calibration, *don't* update last_temperature */
1433 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1434 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1435 return 0;
1436 }
1437
1438 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1439
1440 /* assume that caller will actually do calib ...
1441 * update the "last temperature" value */
1442 priv->last_temperature = priv->temperature;
1443 return 1;
1444}
1445
1446#define IWL_MAX_GAIN_ENTRIES 78
1447#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1448#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1449
1450/* radio and DSP power table, each step is 1/2 dB.
1451 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1452static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1453 {
1454 {251, 127}, /* 2.4 GHz, highest power */
1455 {251, 127},
1456 {251, 127},
1457 {251, 127},
1458 {251, 125},
1459 {251, 110},
1460 {251, 105},
1461 {251, 98},
1462 {187, 125},
1463 {187, 115},
1464 {187, 108},
1465 {187, 99},
1466 {243, 119},
1467 {243, 111},
1468 {243, 105},
1469 {243, 97},
1470 {243, 92},
1471 {211, 106},
1472 {211, 100},
1473 {179, 120},
1474 {179, 113},
1475 {179, 107},
1476 {147, 125},
1477 {147, 119},
1478 {147, 112},
1479 {147, 106},
1480 {147, 101},
1481 {147, 97},
1482 {147, 91},
1483 {115, 107},
1484 {235, 121},
1485 {235, 115},
1486 {235, 109},
1487 {203, 127},
1488 {203, 121},
1489 {203, 115},
1490 {203, 108},
1491 {203, 102},
1492 {203, 96},
1493 {203, 92},
1494 {171, 110},
1495 {171, 104},
1496 {171, 98},
1497 {139, 116},
1498 {227, 125},
1499 {227, 119},
1500 {227, 113},
1501 {227, 107},
1502 {227, 101},
1503 {227, 96},
1504 {195, 113},
1505 {195, 106},
1506 {195, 102},
1507 {195, 95},
1508 {163, 113},
1509 {163, 106},
1510 {163, 102},
1511 {163, 95},
1512 {131, 113},
1513 {131, 106},
1514 {131, 102},
1515 {131, 95},
1516 {99, 113},
1517 {99, 106},
1518 {99, 102},
1519 {99, 95},
1520 {67, 113},
1521 {67, 106},
1522 {67, 102},
1523 {67, 95},
1524 {35, 113},
1525 {35, 106},
1526 {35, 102},
1527 {35, 95},
1528 {3, 113},
1529 {3, 106},
1530 {3, 102},
1531 {3, 95} }, /* 2.4 GHz, lowest power */
1532 {
1533 {251, 127}, /* 5.x GHz, highest power */
1534 {251, 120},
1535 {251, 114},
1536 {219, 119},
1537 {219, 101},
1538 {187, 113},
1539 {187, 102},
1540 {155, 114},
1541 {155, 103},
1542 {123, 117},
1543 {123, 107},
1544 {123, 99},
1545 {123, 92},
1546 {91, 108},
1547 {59, 125},
1548 {59, 118},
1549 {59, 109},
1550 {59, 102},
1551 {59, 96},
1552 {59, 90},
1553 {27, 104},
1554 {27, 98},
1555 {27, 92},
1556 {115, 118},
1557 {115, 111},
1558 {115, 104},
1559 {83, 126},
1560 {83, 121},
1561 {83, 113},
1562 {83, 105},
1563 {83, 99},
1564 {51, 118},
1565 {51, 111},
1566 {51, 104},
1567 {51, 98},
1568 {19, 116},
1569 {19, 109},
1570 {19, 102},
1571 {19, 98},
1572 {19, 93},
1573 {171, 113},
1574 {171, 107},
1575 {171, 99},
1576 {139, 120},
1577 {139, 113},
1578 {139, 107},
1579 {139, 99},
1580 {107, 120},
1581 {107, 113},
1582 {107, 107},
1583 {107, 99},
1584 {75, 120},
1585 {75, 113},
1586 {75, 107},
1587 {75, 99},
1588 {43, 120},
1589 {43, 113},
1590 {43, 107},
1591 {43, 99},
1592 {11, 120},
1593 {11, 113},
1594 {11, 107},
1595 {11, 99},
1596 {131, 107},
1597 {131, 99},
1598 {99, 120},
1599 {99, 113},
1600 {99, 107},
1601 {99, 99},
1602 {67, 120},
1603 {67, 113},
1604 {67, 107},
1605 {67, 99},
1606 {35, 120},
1607 {35, 113},
1608 {35, 107},
1609 {35, 99},
1610 {3, 120} } /* 5.x GHz, lowest power */
1611};
1612
bb8c093b 1613static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1614{
1615 if (index < 0)
1616 return 0;
1617 if (index >= IWL_MAX_GAIN_ENTRIES)
1618 return IWL_MAX_GAIN_ENTRIES - 1;
1619 return (u8) index;
1620}
1621
1622/* Kick off thermal recalibration check every 60 seconds */
1623#define REG_RECALIB_PERIOD (60)
1624
1625/**
bb8c093b 1626 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1627 *
1628 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1629 * or 6 Mbit (OFDM) rates.
1630 */
bb8c093b 1631static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
b481de9c 1632 s32 rate_index, const s8 *clip_pwrs,
bb8c093b 1633 struct iwl3945_channel_info *ch_info,
b481de9c
ZY		 1634 int band_index)
1635{
bb8c093b 1636 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1637 s8 power;
1638 u8 power_index;
1639
1640 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1641
1642 /* use this channel group's 6Mbit clipping/saturation pwr,
1643 * but cap at regulatory scan power restriction (set during init
1644 * based on eeprom channel data) for this channel. */
14577f23 1645 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1646
1647 /* further limit to user's max power preference.
1648 * FIXME: Other spectrum management power limitations do not
1649 * seem to apply?? */
1650 power = min(power, priv->user_txpower_limit);
1651 scan_power_info->requested_power = power;
1652
1653 /* find difference between new scan *power* and current "normal"
1654 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1655 * current "normal" temperature-compensated Tx power *index* for
1656 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1657 * *index*. */
1658 power_index = ch_info->power_info[rate_index].power_table_index
1659 - (power - ch_info->power_info
14577f23 1660 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1661
1662 /* store reference index that we use when adjusting *all* scan
1663 * powers. So we can accommodate user (all channel) or spectrum
1664 * management (single channel) power changes "between" temperature
1665 * feedback compensation procedures.
1666 * don't force fit this reference index into gain table; it may be a
1667 * negative number. This will help avoid errors when we're at
1668 * the lower bounds (highest gains, for warmest temperatures)
1669 * of the table. */
1670
1671 /* don't exceed table bounds for "real" setting */
bb8c093b 1672 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1673
1674 scan_power_info->power_table_index = power_index;
1675 scan_power_info->tpc.tx_gain =
1676 power_gain_table[band_index][power_index].tx_gain;
1677 scan_power_info->tpc.dsp_atten =
1678 power_gain_table[band_index][power_index].dsp_atten;
1679}
1680
1681/**
bb8c093b 1682 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1683 *
1684 * Configures power settings for all rates for the current channel,
1685 * using values from channel info struct, and send to NIC
1686 */
bb8c093b 1687int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
b481de9c 1688{
14577f23 1689 int rate_idx, i;
bb8c093b
CH		 1690 const struct iwl3945_channel_info *ch_info = NULL;
1691 struct iwl3945_txpowertable_cmd txpower = {
b481de9c
ZY		 1692 .channel = priv->active_rxon.channel,
1693 };
1694
8318d78a 1695 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1696 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1697 priv->band,
b481de9c
ZY		 1698 le16_to_cpu(priv->active_rxon.channel));
1699 if (!ch_info) {
1700 IWL_ERROR
1701 ("Failed to get channel info for channel %d [%d]\n",
8318d78a 1702 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1703 return -EINVAL;
1704 }
1705
1706 if (!is_channel_valid(ch_info)) {
1707 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1708 "non-Tx channel.\n");
1709 return 0;
1710 }
1711
1712 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1713 /* Fill OFDM rate */
1714 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1715 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1716
1717 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1718 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1719
1720 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1721 le16_to_cpu(txpower.channel),
1722 txpower.band,
14577f23
MA		 1723 txpower.power[i].tpc.tx_gain,
1724 txpower.power[i].tpc.dsp_atten,
1725 txpower.power[i].rate);
1726 }
1727 /* Fill CCK rates */
1728 for (rate_idx = IWL_FIRST_CCK_RATE;
1729 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1730 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1731 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1732
1733 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1734 le16_to_cpu(txpower.channel),
1735 txpower.band,
1736 txpower.power[i].tpc.tx_gain,
1737 txpower.power[i].tpc.dsp_atten,
1738 txpower.power[i].rate);
b481de9c
ZY		 1739 }
1740
bb8c093b
CH		 1741 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1742 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1743
1744}
1745
1746/**
bb8c093b 1747 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1748 * @ch_info: Channel to update. Uses power_info.requested_power.
1749 *
1750 * Replace requested_power and base_power_index ch_info fields for
1751 * one channel.
1752 *
1753 * Called if user or spectrum management changes power preferences.
1754 * Takes into account h/w and modulation limitations (clip power).
1755 *
1756 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1757 *
1758 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1759 * properly fill out the scan powers, and actual h/w gain settings,
1760 * and send changes to NIC
1761 */
bb8c093b
CH		 1762static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1763 struct iwl3945_channel_info *ch_info)
b481de9c 1764{
bb8c093b 1765 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1766 int power_changed = 0;
1767 int i;
1768 const s8 *clip_pwrs;
1769 int power;
1770
1771 /* Get this chnlgrp's rate-to-max/clip-powers table */
1772 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1773
1774 /* Get this channel's rate-to-current-power settings table */
1775 power_info = ch_info->power_info;
1776
1777 /* update OFDM Txpower settings */
14577f23 1778 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1779 i++, ++power_info) {
1780 int delta_idx;
1781
1782 /* limit new power to be no more than h/w capability */
1783 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1784 if (power == power_info->requested_power)
1785 continue;
1786
1787 /* find difference between old and new requested powers,
1788 * update base (non-temp-compensated) power index */
1789 delta_idx = (power - power_info->requested_power) * 2;
1790 power_info->base_power_index -= delta_idx;
1791
1792 /* save new requested power value */
1793 power_info->requested_power = power;
1794
1795 power_changed = 1;
1796 }
1797
1798 /* update CCK Txpower settings, based on OFDM 12M setting ...
1799 * ... all CCK power settings for a given channel are the *same*. */
1800 if (power_changed) {
1801 power =
14577f23 1802 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1803 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1804
bb8c093b 1805 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1806 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1807 power_info->requested_power = power;
1808 power_info->base_power_index =
14577f23 1809 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1810 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1811 ++power_info;
1812 }
1813 }
1814
1815 return 0;
1816}
1817
1818/**
bb8c093b 1819 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1820 *
1821 * NOTE: Returned power limit may be less (but not more) than requested,
1822 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1823 * (no consideration for h/w clipping limitations).
1824 */
bb8c093b 1825static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
b481de9c
ZY		 1826{
1827 s8 max_power;
1828
1829#if 0
1830 /* if we're using TGd limits, use lower of TGd or EEPROM */
1831 if (ch_info->tgd_data.max_power != 0)
1832 max_power = min(ch_info->tgd_data.max_power,
1833 ch_info->eeprom.max_power_avg);
1834
1835 /* else just use EEPROM limits */
1836 else
1837#endif
1838 max_power = ch_info->eeprom.max_power_avg;
1839
1840 return min(max_power, ch_info->max_power_avg);
1841}
1842
1843/**
bb8c093b 1844 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1845 *
1846 * Compensate txpower settings of *all* channels for temperature.
1847 * This only accounts for the difference between current temperature
1848 * and the factory calibration temperatures, and bases the new settings
1849 * on the channel's base_power_index.
1850 *
1851 * If RxOn is "associated", this sends the new Txpower to NIC!
1852 */
bb8c093b 1853static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
b481de9c 1854{
bb8c093b 1855 struct iwl3945_channel_info *ch_info = NULL;
b481de9c
ZY		 1856 int delta_index;
1857 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1858 u8 a_band;
1859 u8 rate_index;
1860 u8 scan_tbl_index;
1861 u8 i;
1862 int ref_temp;
1863 int temperature = priv->temperature;
1864
1865 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1866 for (i = 0; i < priv->channel_count; i++) {
1867 ch_info = &priv->channel_info[i];
1868 a_band = is_channel_a_band(ch_info);
1869
1870 /* Get this chnlgrp's factory calibration temperature */
1871 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1872 temperature;
1873
a96a27f9 1874 /* get power index adjustment based on current and factory
b481de9c 1875 * temps */
bb8c093b 1876 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1877 ref_temp);
1878
1879 /* set tx power value for all rates, OFDM and CCK */
1880 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1881 rate_index++) {
1882 int power_idx =
1883 ch_info->power_info[rate_index].base_power_index;
1884
1885 /* temperature compensate */
1886 power_idx += delta_index;
1887
1888 /* stay within table range */
bb8c093b 1889 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1890 ch_info->power_info[rate_index].
1891 power_table_index = (u8) power_idx;
1892 ch_info->power_info[rate_index].tpc =
1893 power_gain_table[a_band][power_idx];
1894 }
1895
1896 /* Get this chnlgrp's rate-to-max/clip-powers table */
1897 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1898
1899 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1900 for (scan_tbl_index = 0;
1901 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1902 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1903 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1904 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1905 actual_index, clip_pwrs,
1906 ch_info, a_band);
1907 }
1908 }
1909
1910 /* send Txpower command for current channel to ucode */
bb8c093b 1911 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1912}
1913
bb8c093b 1914int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
b481de9c 1915{
bb8c093b 1916 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 1917 s8 max_power;
1918 u8 a_band;
1919 u8 i;
1920
1921 if (priv->user_txpower_limit == power) {
1922 IWL_DEBUG_POWER("Requested Tx power same as current "
1923 "limit: %ddBm.\n", power);
1924 return 0;
1925 }
1926
1927 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1928 priv->user_txpower_limit = power;
1929
1930 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1931
1932 for (i = 0; i < priv->channel_count; i++) {
1933 ch_info = &priv->channel_info[i];
1934 a_band = is_channel_a_band(ch_info);
1935
1936 /* find minimum power of all user and regulatory constraints
1937 * (does not consider h/w clipping limitations) */
bb8c093b 1938 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1939 max_power = min(power, max_power);
1940 if (max_power != ch_info->curr_txpow) {
1941 ch_info->curr_txpow = max_power;
1942
1943 /* this considers the h/w clipping limitations */
bb8c093b 1944 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1945 }
1946 }
1947
1948 /* update txpower settings for all channels,
1949 * send to NIC if associated. */
1950 is_temp_calib_needed(priv);
bb8c093b 1951 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1952
1953 return 0;
1954}
1955
1956/* will add 3945 channel switch cmd handling later */
bb8c093b 1957int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
b481de9c
ZY		 1958{
1959 return 0;
1960}
1961
1962/**
1963 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1964 *
1965 * -- reset periodic timer
1966 * -- see if temp has changed enough to warrant re-calibration ... if so:
1967 * -- correct coeffs for temp (can reset temp timer)
1968 * -- save this temp as "last",
1969 * -- send new set of gain settings to NIC
1970 * NOTE: This should continue working, even when we're not associated,
1971 * so we can keep our internal table of scan powers current. */
bb8c093b 1972void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
b481de9c
ZY		 1973{
1974 /* This will kick in the "brute force"
bb8c093b 1975 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1976 if (!is_temp_calib_needed(priv))
1977 goto reschedule;
1978
1979 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1980 * This is based *only* on current temperature,
1981 * ignoring any previous power measurements */
bb8c093b 1982 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1983
1984 reschedule:
1985 queue_delayed_work(priv->workqueue,
1986 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1987}
1988
416e1438 1989static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1990{
bb8c093b 1991 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
b481de9c
ZY		 1992 thermal_periodic.work);
1993
1994 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1995 return;
1996
1997 mutex_lock(&priv->mutex);
1998 iwl3945_reg_txpower_periodic(priv);
1999 mutex_unlock(&priv->mutex);
2000}
2001
2002/**
bb8c093b 2003 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2004 * for the channel.
2005 *
2006 * This function is used when initializing channel-info structs.
2007 *
2008 * NOTE: These channel groups do *NOT* match the bands above!
2009 * These channel groups are based on factory-tested channels;
2010 * on A-band, EEPROM's "group frequency" entries represent the top
2011 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2012 */
bb8c093b
CH		 2013static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
2014 const struct iwl3945_channel_info *ch_info)
b481de9c 2015{
bb8c093b 2016 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
b481de9c
ZY		 2017 u8 group;
2018 u16 group_index = 0; /* based on factory calib frequencies */
2019 u8 grp_channel;
2020
2021 /* Find the group index for the channel ... don't use index 1(?) */
2022 if (is_channel_a_band(ch_info)) {
2023 for (group = 1; group < 5; group++) {
2024 grp_channel = ch_grp[group].group_channel;
2025 if (ch_info->channel <= grp_channel) {
2026 group_index = group;
2027 break;
2028 }
2029 }
2030 /* group 4 has a few channels *above* its factory cal freq */
2031 if (group == 5)
2032 group_index = 4;
2033 } else
2034 group_index = 0; /* 2.4 GHz, group 0 */
2035
2036 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2037 group_index);
2038 return group_index;
2039}
2040
2041/**
bb8c093b 2042 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2043 *
2044 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2045 * into radio/DSP gain settings table for requested power.
2046 */
bb8c093b 2047static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
b481de9c
ZY		 2048 s8 requested_power,
2049 s32 setting_index, s32 *new_index)
2050{
bb8c093b 2051 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 2052 s32 index0, index1;
2053 s32 power = 2 * requested_power;
2054 s32 i;
bb8c093b 2055 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2056 s32 gains0, gains1;
2057 s32 res;
2058 s32 denominator;
2059
2060 chnl_grp = &priv->eeprom.groups[setting_index];
2061 samples = chnl_grp->samples;
2062 for (i = 0; i < 5; i++) {
2063 if (power == samples[i].power) {
2064 *new_index = samples[i].gain_index;
2065 return 0;
2066 }
2067 }
2068
2069 if (power > samples[1].power) {
2070 index0 = 0;
2071 index1 = 1;
2072 } else if (power > samples[2].power) {
2073 index0 = 1;
2074 index1 = 2;
2075 } else if (power > samples[3].power) {
2076 index0 = 2;
2077 index1 = 3;
2078 } else {
2079 index0 = 3;
2080 index1 = 4;
2081 }
2082
2083 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2084 if (denominator == 0)
2085 return -EINVAL;
2086 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2087 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2088 res = gains0 + (gains1 - gains0) *
2089 ((s32) power - (s32) samples[index0].power) / denominator +
2090 (1 << 18);
2091 *new_index = res >> 19;
2092 return 0;
2093}
2094
bb8c093b 2095static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
b481de9c
ZY		 2096{
2097 u32 i;
2098 s32 rate_index;
bb8c093b 2099 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2100
2101 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2102
2103 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2104 s8 *clip_pwrs; /* table of power levels for each rate */
2105 s8 satur_pwr; /* saturation power for each chnl group */
2106 group = &priv->eeprom.groups[i];
2107
2108 /* sanity check on factory saturation power value */
2109 if (group->saturation_power < 40) {
2110 IWL_WARNING("Error: saturation power is %d, "
2111 "less than minimum expected 40\n",
2112 group->saturation_power);
2113 return;
2114 }
2115
2116 /*
2117 * Derive requested power levels for each rate, based on
2118 * hardware capabilities (saturation power for band).
2119 * Basic value is 3dB down from saturation, with further
2120 * power reductions for highest 3 data rates. These
2121 * backoffs provide headroom for high rate modulation
2122 * power peaks, without too much distortion (clipping).
2123 */
2124 /* we'll fill in this array with h/w max power levels */
2125 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
2126
2127 /* divide factory saturation power by 2 to find -3dB level */
2128 satur_pwr = (s8) (group->saturation_power >> 1);
2129
2130 /* fill in channel group's nominal powers for each rate */
2131 for (rate_index = 0;
2132 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2133 switch (rate_index) {
14577f23 2134 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2135 if (i == 0) /* B/G */
2136 *clip_pwrs = satur_pwr;
2137 else /* A */
2138 *clip_pwrs = satur_pwr - 5;
2139 break;
14577f23 2140 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2141 if (i == 0)
2142 *clip_pwrs = satur_pwr - 7;
2143 else
2144 *clip_pwrs = satur_pwr - 10;
2145 break;
14577f23 2146 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2147 if (i == 0)
2148 *clip_pwrs = satur_pwr - 9;
2149 else
2150 *clip_pwrs = satur_pwr - 12;
2151 break;
2152 default:
2153 *clip_pwrs = satur_pwr;
2154 break;
2155 }
2156 }
2157 }
2158}
2159
2160/**
2161 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2162 *
2163 * Second pass (during init) to set up priv->channel_info
2164 *
2165 * Set up Tx-power settings in our channel info database for each VALID
2166 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2167 * and current temperature.
2168 *
2169 * Since this is based on current temperature (at init time), these values may
2170 * not be valid for very long, but it gives us a starting/default point,
2171 * and allows us to active (i.e. using Tx) scan.
2172 *
2173 * This does *not* write values to NIC, just sets up our internal table.
2174 */
bb8c093b 2175int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
b481de9c 2176{
bb8c093b
CH		 2177 struct iwl3945_channel_info *ch_info = NULL;
2178 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2179 int delta_index;
2180 u8 rate_index;
2181 u8 scan_tbl_index;
2182 const s8 *clip_pwrs; /* array of power levels for each rate */
2183 u8 gain, dsp_atten;
2184 s8 power;
2185 u8 pwr_index, base_pwr_index, a_band;
2186 u8 i;
2187 int temperature;
2188
2189 /* save temperature reference,
2190 * so we can determine next time to calibrate */
bb8c093b 2191 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2192 priv->last_temperature = temperature;
2193
bb8c093b 2194 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2195
2196 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2197 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2198 i++, ch_info++) {
2199 a_band = is_channel_a_band(ch_info);
2200 if (!is_channel_valid(ch_info))
2201 continue;
2202
2203 /* find this channel's channel group (*not* "band") index */
2204 ch_info->group_index =
bb8c093b 2205 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2206
2207 /* Get this chnlgrp's rate->max/clip-powers table */
2208 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2209
2210 /* calculate power index *adjustment* value according to
2211 * diff between current temperature and factory temperature */
bb8c093b 2212 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 2213 priv->eeprom.groups[ch_info->group_index].
2214 temperature);
2215
2216 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2217 ch_info->channel, delta_index, temperature +
2218 IWL_TEMP_CONVERT);
2219
2220 /* set tx power value for all OFDM rates */
2221 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2222 rate_index++) {
2223 s32 power_idx;
2224 int rc;
2225
2226 /* use channel group's clip-power table,
2227 * but don't exceed channel's max power */
2228 s8 pwr = min(ch_info->max_power_avg,
2229 clip_pwrs[rate_index]);
2230
2231 pwr_info = &ch_info->power_info[rate_index];
2232
2233 /* get base (i.e. at factory-measured temperature)
2234 * power table index for this rate's power */
bb8c093b 2235 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2236 ch_info->group_index,
2237 &power_idx);
2238 if (rc) {
2239 IWL_ERROR("Invalid power index\n");
2240 return rc;
2241 }
2242 pwr_info->base_power_index = (u8) power_idx;
2243
2244 /* temperature compensate */
2245 power_idx += delta_index;
2246
2247 /* stay within range of gain table */
bb8c093b 2248 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2249
bb8c093b 2250 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2251 pwr_info->requested_power = pwr;
2252 pwr_info->power_table_index = (u8) power_idx;
2253 pwr_info->tpc.tx_gain =
2254 power_gain_table[a_band][power_idx].tx_gain;
2255 pwr_info->tpc.dsp_atten =
2256 power_gain_table[a_band][power_idx].dsp_atten;
2257 }
2258
2259 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2260 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2261 power = pwr_info->requested_power +
2262 IWL_CCK_FROM_OFDM_POWER_DIFF;
2263 pwr_index = pwr_info->power_table_index +
2264 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2265 base_pwr_index = pwr_info->base_power_index +
2266 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2267
2268 /* stay within table range */
bb8c093b 2269 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2270 gain = power_gain_table[a_band][pwr_index].tx_gain;
2271 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2272
bb8c093b 2273 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2274 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2275 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2276 for (rate_index = 0;
2277 rate_index < IWL_CCK_RATES; rate_index++) {
2278 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2279 pwr_info->requested_power = power;
2280 pwr_info->power_table_index = pwr_index;
2281 pwr_info->base_power_index = base_pwr_index;
2282 pwr_info->tpc.tx_gain = gain;
2283 pwr_info->tpc.dsp_atten = dsp_atten;
2284 }
2285
2286 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2287 for (scan_tbl_index = 0;
2288 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2289 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2290 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2291 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2292 actual_index, clip_pwrs, ch_info, a_band);
2293 }
2294 }
2295
2296 return 0;
2297}
2298
bb8c093b 2299int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 2300{
2301 int rc;
2302 unsigned long flags;
2303
2304 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2305 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2306 if (rc) {
2307 spin_unlock_irqrestore(&priv->lock, flags);
2308 return rc;
2309 }
2310
bb8c093b
CH		 2311 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2312 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
b481de9c
ZY		 2313 if (rc < 0)
2314 IWL_ERROR("Can't stop Rx DMA.\n");
2315
bb8c093b 2316 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2317 spin_unlock_irqrestore(&priv->lock, flags);
2318
2319 return 0;
2320}
2321
bb8c093b 2322int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2323{
2324 int rc;
2325 unsigned long flags;
2326 int txq_id = txq->q.id;
2327
bb8c093b 2328 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2329
2330 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2331
2332 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2333 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2334 if (rc) {
2335 spin_unlock_irqrestore(&priv->lock, flags);
2336 return rc;
2337 }
bb8c093b
CH		 2338 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2339 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
b481de9c 2340
bb8c093b 2341 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
b481de9c
ZY		 2342 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2343 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2344 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2345 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2346 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
bb8c093b 2347 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2348
2349 /* fake read to flush all prev. writes */
bb8c093b 2350 iwl3945_read32(priv, FH_TSSR_CBB_BASE);
b481de9c
ZY		 2351 spin_unlock_irqrestore(&priv->lock, flags);
2352
2353 return 0;
2354}
2355
bb8c093b 2356int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
b481de9c 2357{
bb8c093b 2358 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2359
2360 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2361}
2362
2363/**
2364 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2365 */
bb8c093b 2366int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
b481de9c 2367{
14577f23 2368 int rc, i, index, prev_index;
bb8c093b 2369 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2370 .reserved = {0, 0, 0},
2371 };
bb8c093b 2372 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2373
bb8c093b
CH		 2374 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2375 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2376
2377 table[index].rate_n_flags =
bb8c093b 2378 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2379 table[index].try_cnt = priv->retry_rate;
bb8c093b
CH		 2380 prev_index = iwl3945_get_prev_ieee_rate(i);
2381 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2382 }
2383
8318d78a
JB		 2384 switch (priv->band) {
2385 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2386 IWL_DEBUG_RATE("Select A mode rate scale\n");
2387 /* If one of the following CCK rates is used,
2388 * have it fall back to the 6M OFDM rate */
14577f23 2389 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
bb8c093b 2390 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2391
2392 /* Don't fall back to CCK rates */
14577f23 2393 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2394
2395 /* Don't drop out of OFDM rates */
14577f23 2396 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2397 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2398 break;
2399
8318d78a
JB		 2400 case IEEE80211_BAND_2GHZ:
2401 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2402 /* If an OFDM rate is used, have it fall back to the
2403 * 1M CCK rates */
14577f23 2404 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
bb8c093b 2405 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
b481de9c
ZY		 2406
2407 /* CCK shouldn't fall back to OFDM... */
14577f23 2408 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
b481de9c
ZY		 2409 break;
2410
2411 default:
8318d78a 2412 WARN_ON(1);
b481de9c
ZY		 2413 break;
2414 }
2415
2416 /* Update the rate scaling for control frame Tx */
2417 rate_cmd.table_id = 0;
bb8c093b 2418 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2419 &rate_cmd);
2420 if (rc)
2421 return rc;
2422
2423 /* Update the rate scaling for data frame Tx */
2424 rate_cmd.table_id = 1;
bb8c093b 2425 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2426 &rate_cmd);
2427}
2428
796083cb 2429/* Called when initializing driver */
bb8c093b 2430int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 2431{
2432 memset((void *)&priv->hw_setting, 0,
bb8c093b 2433 sizeof(struct iwl3945_driver_hw_info));
b481de9c
ZY		 2434
2435 priv->hw_setting.shared_virt =
2436 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2437 sizeof(struct iwl3945_shared),
b481de9c
ZY		 2438 &priv->hw_setting.shared_phys);
2439
2440 if (!priv->hw_setting.shared_virt) {
2441 IWL_ERROR("failed to allocate pci memory\n");
2442 mutex_unlock(&priv->mutex);
2443 return -ENOMEM;
2444 }
2445
9ee1ba47
RR		 2446 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2447 priv->hw_setting.max_pkt_size = 2342;
bb8c093b 2448 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
b481de9c
ZY		 2449 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2450 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
b481de9c
ZY		 2451 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2452 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822
TW		 2453
2454 priv->hw_setting.tx_ant_num = 2;
b481de9c
ZY		 2455 return 0;
2456}
2457
bb8c093b
CH		 2458unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2459 struct iwl3945_frame *frame, u8 rate)
b481de9c 2460{
bb8c093b 2461 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2462 unsigned int frame_size;
2463
bb8c093b 2464 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2465 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2466
a4062b8f 2467 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 2468 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2469
bb8c093b 2470 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2471 tx_beacon_cmd->frame,
bb8c093b 2472 iwl3945_broadcast_addr,
b481de9c
ZY		 2473 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2474
2475 BUG_ON(frame_size > MAX_MPDU_SIZE);
2476 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2477
2478 tx_beacon_cmd->tx.rate = rate;
2479 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2480 TX_CMD_FLG_TSF_MSK);
2481
14577f23
MA		 2482 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2483 tx_beacon_cmd->tx.supp_rates[0] =
2484 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2485
b481de9c 2486 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2487 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2488
3ac7f146 2489 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2490}
2491
bb8c093b 2492void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
b481de9c 2493{
91c066f2 2494 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2495 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2496}
2497
bb8c093b 2498void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2499{
2500 INIT_DELAYED_WORK(&priv->thermal_periodic,
2501 iwl3945_bg_reg_txpower_periodic);
2502}
2503
bb8c093b 2504void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2505{
2506 cancel_delayed_work(&priv->thermal_periodic);
2507}
2508
82b9a121
TW		 2509static struct iwl_3945_cfg iwl3945_bg_cfg = {
2510 .name = "3945BG",
a0987a8d
RC		 2511 .fw_name_pre = IWL3945_FW_PRE,
2512 .ucode_api_max = IWL3945_UCODE_API_MAX,
2513 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121
TW		 2514 .sku = IWL_SKU_G,
2515};
2516
2517static struct iwl_3945_cfg iwl3945_abg_cfg = {
2518 .name = "3945ABG",
a0987a8d
RC		 2519 .fw_name_pre = IWL3945_FW_PRE,
2520 .ucode_api_max = IWL3945_UCODE_API_MAX,
2521 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121
TW		 2522 .sku = IWL_SKU_A|IWL_SKU_G,
2523};
2524
bb8c093b 2525struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2526 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2527 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2528 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2529 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2530 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2531 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2532 {0}
2533};
2534
bb8c093b 2535MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux kernel - Deliverables
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