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iwlwifi: rename iwl4965-base.c to iwl-agn.c
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47
ZY		 39#include <asm/unaligned.h>
40#include <net/mac80211.h>
b481de9c 41
82b9a121 42#include "iwl-3945-core.h"
b481de9c 43#include "iwl-3945.h"
5d08cd1d 44#include "iwl-helpers.h"
b481de9c
ZY		 45#include "iwl-3945-rs.h"
46
47#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
48 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
49 IWL_RATE_##r##M_IEEE, \
50 IWL_RATE_##ip##M_INDEX, \
51 IWL_RATE_##in##M_INDEX, \
52 IWL_RATE_##rp##M_INDEX, \
53 IWL_RATE_##rn##M_INDEX, \
54 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 55 IWL_RATE_##np##M_INDEX, \
56 IWL_RATE_##r##M_INDEX_TABLE, \
57 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 58
59/*
60 * Parameter order:
61 * rate, prev rate, next rate, prev tgg rate, next tgg rate
62 *
63 * If there isn't a valid next or previous rate then INV is used which
64 * maps to IWL_RATE_INVALID
65 *
66 */
bb8c093b 67const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
14577f23
MA		 68 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
69 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
70 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
71 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 72 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
73 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
74 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
75 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
76 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
77 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
78 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
79 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 80};
81
bb8c093b 82/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 83#define IWL_EVT_DISABLE (0)
84#define IWL_EVT_DISABLE_SIZE (1532/32)
85
86/**
bb8c093b 87 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 88 *
89 * Disable an event by writing "1"s into "disable"
90 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
91 * Default values of 0 enable uCode events to be logged.
92 * Use for only special debugging. This function is just a placeholder as-is,
93 * you'll need to provide the special bits! ...
94 * ... and set IWL_EVT_DISABLE to 1. */
bb8c093b 95void iwl3945_disable_events(struct iwl3945_priv *priv)
b481de9c 96{
af7cca2a 97 int ret;
b481de9c
ZY		 98 int i;
99 u32 base; /* SRAM address of event log header */
100 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
101 u32 array_size; /* # of u32 entries in array */
102 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
103 0x00000000, /* 31 - 0 Event id numbers */
104 0x00000000, /* 63 - 32 */
105 0x00000000, /* 95 - 64 */
106 0x00000000, /* 127 - 96 */
107 0x00000000, /* 159 - 128 */
108 0x00000000, /* 191 - 160 */
109 0x00000000, /* 223 - 192 */
110 0x00000000, /* 255 - 224 */
111 0x00000000, /* 287 - 256 */
112 0x00000000, /* 319 - 288 */
113 0x00000000, /* 351 - 320 */
114 0x00000000, /* 383 - 352 */
115 0x00000000, /* 415 - 384 */
116 0x00000000, /* 447 - 416 */
117 0x00000000, /* 479 - 448 */
118 0x00000000, /* 511 - 480 */
119 0x00000000, /* 543 - 512 */
120 0x00000000, /* 575 - 544 */
121 0x00000000, /* 607 - 576 */
122 0x00000000, /* 639 - 608 */
123 0x00000000, /* 671 - 640 */
124 0x00000000, /* 703 - 672 */
125 0x00000000, /* 735 - 704 */
126 0x00000000, /* 767 - 736 */
127 0x00000000, /* 799 - 768 */
128 0x00000000, /* 831 - 800 */
129 0x00000000, /* 863 - 832 */
130 0x00000000, /* 895 - 864 */
131 0x00000000, /* 927 - 896 */
132 0x00000000, /* 959 - 928 */
133 0x00000000, /* 991 - 960 */
134 0x00000000, /* 1023 - 992 */
135 0x00000000, /* 1055 - 1024 */
136 0x00000000, /* 1087 - 1056 */
137 0x00000000, /* 1119 - 1088 */
138 0x00000000, /* 1151 - 1120 */
139 0x00000000, /* 1183 - 1152 */
140 0x00000000, /* 1215 - 1184 */
141 0x00000000, /* 1247 - 1216 */
142 0x00000000, /* 1279 - 1248 */
143 0x00000000, /* 1311 - 1280 */
144 0x00000000, /* 1343 - 1312 */
145 0x00000000, /* 1375 - 1344 */
146 0x00000000, /* 1407 - 1376 */
147 0x00000000, /* 1439 - 1408 */
148 0x00000000, /* 1471 - 1440 */
149 0x00000000, /* 1503 - 1472 */
150 };
151
152 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 153 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 154 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
155 return;
156 }
157
bb8c093b 158 ret = iwl3945_grab_nic_access(priv);
af7cca2a 159 if (ret) {
b481de9c
ZY		 160 IWL_WARNING("Can not read from adapter at this time.\n");
161 return;
162 }
163
bb8c093b
CH		 164 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
165 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
166 iwl3945_release_nic_access(priv);
b481de9c
ZY		 167
168 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
169 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
170 disable_ptr);
bb8c093b 171 ret = iwl3945_grab_nic_access(priv);
b481de9c 172 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
bb8c093b 173 iwl3945_write_targ_mem(priv,
af7cca2a
TW		 174 disable_ptr + (i * sizeof(u32)),
175 evt_disable[i]);
b481de9c 176
bb8c093b 177 iwl3945_release_nic_access(priv);
b481de9c
ZY		 178 } else {
179 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
180 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
181 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
182 disable_ptr, array_size);
183 }
184
185}
186
17744ff6
TW		 187static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
188{
189 int idx;
190
191 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
192 if (iwl3945_rates[idx].plcp == plcp)
193 return idx;
194 return -1;
195}
196
b481de9c
ZY		 197/**
198 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
199 * @priv: eeprom and antenna fields are used to determine antenna flags
200 *
201 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
202 * priv->antenna specifies the antenna diversity mode:
203 *
204 * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
205 * IWL_ANTENNA_MAIN - Force MAIN antenna
206 * IWL_ANTENNA_AUX - Force AUX antenna
207 */
bb8c093b 208__le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
b481de9c
ZY		 209{
210 switch (priv->antenna) {
211 case IWL_ANTENNA_DIVERSITY:
212 return 0;
213
214 case IWL_ANTENNA_MAIN:
215 if (priv->eeprom.antenna_switch_type)
216 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
217 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
218
219 case IWL_ANTENNA_AUX:
220 if (priv->eeprom.antenna_switch_type)
221 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
222 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
223 }
224
225 /* bad antenna selector value */
226 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
227 return 0; /* "diversity" is default if error */
228}
229
91c066f2
TW		 230#ifdef CONFIG_IWL3945_DEBUG
231#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
232
233static const char *iwl3945_get_tx_fail_reason(u32 status)
234{
235 switch (status & TX_STATUS_MSK) {
236 case TX_STATUS_SUCCESS:
237 return "SUCCESS";
238 TX_STATUS_ENTRY(SHORT_LIMIT);
239 TX_STATUS_ENTRY(LONG_LIMIT);
240 TX_STATUS_ENTRY(FIFO_UNDERRUN);
241 TX_STATUS_ENTRY(MGMNT_ABORT);
242 TX_STATUS_ENTRY(NEXT_FRAG);
243 TX_STATUS_ENTRY(LIFE_EXPIRE);
244 TX_STATUS_ENTRY(DEST_PS);
245 TX_STATUS_ENTRY(ABORTED);
246 TX_STATUS_ENTRY(BT_RETRY);
247 TX_STATUS_ENTRY(STA_INVALID);
248 TX_STATUS_ENTRY(FRAG_DROPPED);
249 TX_STATUS_ENTRY(TID_DISABLE);
250 TX_STATUS_ENTRY(FRAME_FLUSHED);
251 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
252 TX_STATUS_ENTRY(TX_LOCKED);
253 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
254 }
255
256 return "UNKNOWN";
257}
258#else
259static inline const char *iwl3945_get_tx_fail_reason(u32 status)
260{
261 return "";
262}
263#endif
264
265
266/**
267 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
268 *
269 * When FW advances 'R' index, all entries between old and new 'R' index
270 * need to be reclaimed. As result, some free space forms. If there is
271 * enough free space (> low mark), wake the stack that feeds us.
272 */
273static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
274 int txq_id, int index)
275{
276 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
277 struct iwl3945_queue *q = &txq->q;
278 struct iwl3945_tx_info *tx_info;
279
280 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
281
282 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
283 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
284
285 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 286 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2
TW		 287 tx_info->skb[0] = NULL;
288 iwl3945_hw_txq_free_tfd(priv, txq);
289 }
290
291 if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
292 (txq_id != IWL_CMD_QUEUE_NUM) &&
293 priv->mac80211_registered)
294 ieee80211_wake_queue(priv->hw, txq_id);
295}
296
297/**
298 * iwl3945_rx_reply_tx - Handle Tx response
299 */
300static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
301 struct iwl3945_rx_mem_buffer *rxb)
302{
303 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
304 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
305 int txq_id = SEQ_TO_QUEUE(sequence);
306 int index = SEQ_TO_INDEX(sequence);
307 struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 308 struct ieee80211_tx_info *info;
91c066f2
TW		 309 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
310 u32 status = le32_to_cpu(tx_resp->status);
311 int rate_idx;
312
313 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
314 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
315 "is out of range [0-%d] %d %d\n", txq_id,
316 index, txq->q.n_bd, txq->q.write_ptr,
317 txq->q.read_ptr);
318 return;
319 }
320
e039fa4a
JB		 321 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
322 memset(&info->status, 0, sizeof(info->status));
91c066f2 323
e039fa4a 324 info->status.retry_count = tx_resp->failure_frame;
91c066f2 325 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 326 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
327 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 328
329 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
330 txq_id, iwl3945_get_tx_fail_reason(status), status,
331 tx_resp->rate, tx_resp->failure_frame);
332
333 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
e039fa4a 334 if (info->band == IEEE80211_BAND_5GHZ)
2e92e6f2 335 rate_idx -= IWL_FIRST_OFDM_RATE;
e039fa4a 336 info->tx_rate_idx = rate_idx;
91c066f2
TW		 337 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
338 iwl3945_tx_queue_reclaim(priv, txq_id, index);
339
340 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
341 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
342}
343
344
345
b481de9c
ZY		 346/*****************************************************************************
347 *
348 * Intel PRO/Wireless 3945ABG/BG Network Connection
349 *
350 * RX handler implementations
351 *
b481de9c
ZY		 352 *****************************************************************************/
353
bb8c093b 354void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 355{
bb8c093b 356 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 357 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 358 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 359 le32_to_cpu(pkt->len));
360
361 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
362
ab53d8af
MA		 363 iwl3945_led_background(priv);
364
b481de9c
ZY		 365 priv->last_statistics_time = jiffies;
366}
367
17744ff6
TW		 368/******************************************************************************
369 *
370 * Misc. internal state and helper functions
371 *
372 ******************************************************************************/
373#ifdef CONFIG_IWL3945_DEBUG
374
375/**
376 * iwl3945_report_frame - dump frame to syslog during debug sessions
377 *
378 * You may hack this function to show different aspects of received frames,
379 * including selective frame dumps.
380 * group100 parameter selects whether to show 1 out of 100 good frames.
381 */
382static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
383 struct iwl3945_rx_packet *pkt,
384 struct ieee80211_hdr *header, int group100)
385{
386 u32 to_us;
387 u32 print_summary = 0;
388 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
389 u32 hundred = 0;
390 u32 dataframe = 0;
fd7c8a40 391 __le16 fc;
17744ff6
TW		 392 u16 seq_ctl;
393 u16 channel;
394 u16 phy_flags;
395 u16 length;
396 u16 status;
397 u16 bcn_tmr;
398 u32 tsf_low;
399 u64 tsf;
400 u8 rssi;
401 u8 agc;
402 u16 sig_avg;
403 u16 noise_diff;
404 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
405 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
406 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
407 u8 *data = IWL_RX_DATA(pkt);
408
409 /* MAC header */
fd7c8a40 410 fc = header->frame_control;
17744ff6
TW		 411 seq_ctl = le16_to_cpu(header->seq_ctrl);
412
413 /* metadata */
414 channel = le16_to_cpu(rx_hdr->channel);
415 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
416 length = le16_to_cpu(rx_hdr->len);
417
418 /* end-of-frame status and timestamp */
419 status = le32_to_cpu(rx_end->status);
420 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
421 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
422 tsf = le64_to_cpu(rx_end->timestamp);
423
424 /* signal statistics */
425 rssi = rx_stats->rssi;
426 agc = rx_stats->agc;
427 sig_avg = le16_to_cpu(rx_stats->sig_avg);
428 noise_diff = le16_to_cpu(rx_stats->noise_diff);
429
430 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
431
432 /* if data frame is to us and all is good,
433 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 434 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
435 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 436 dataframe = 1;
437 if (!group100)
438 print_summary = 1; /* print each frame */
439 else if (priv->framecnt_to_us < 100) {
440 priv->framecnt_to_us++;
441 print_summary = 0;
442 } else {
443 priv->framecnt_to_us = 0;
444 print_summary = 1;
445 hundred = 1;
446 }
447 } else {
448 /* print summary for all other frames */
449 print_summary = 1;
450 }
451
452 if (print_summary) {
453 char *title;
0ff1cca0 454 int rate;
17744ff6
TW		 455
456 if (hundred)
457 title = "100Frames";
fd7c8a40 458 else if (ieee80211_has_retry(fc))
17744ff6 459 title = "Retry";
fd7c8a40 460 else if (ieee80211_is_assoc_resp(fc))
17744ff6 461 title = "AscRsp";
fd7c8a40 462 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 463 title = "RasRsp";
fd7c8a40 464 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 465 title = "PrbRsp";
466 print_dump = 1; /* dump frame contents */
467 } else if (ieee80211_is_beacon(fc)) {
468 title = "Beacon";
469 print_dump = 1; /* dump frame contents */
470 } else if (ieee80211_is_atim(fc))
471 title = "ATIM";
472 else if (ieee80211_is_auth(fc))
473 title = "Auth";
474 else if (ieee80211_is_deauth(fc))
475 title = "DeAuth";
476 else if (ieee80211_is_disassoc(fc))
477 title = "DisAssoc";
478 else
479 title = "Frame";
480
481 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
482 if (rate == -1)
483 rate = 0;
484 else
485 rate = iwl3945_rates[rate].ieee / 2;
486
487 /* print frame summary.
488 * MAC addresses show just the last byte (for brevity),
489 * but you can hack it to show more, if you'd like to. */
490 if (dataframe)
491 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 492 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 493 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 494 length, rssi, channel, rate);
495 else {
496 /* src/dst addresses assume managed mode */
497 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
498 "src=0x%02x, rssi=%u, tim=%lu usec, "
499 "phy=0x%02x, chnl=%d\n",
fd7c8a40 500 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 501 header->addr3[5], rssi,
502 tsf_low - priv->scan_start_tsf,
503 phy_flags, channel);
504 }
505 }
506 if (print_dump)
507 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
508}
509#else
510static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
511 struct iwl3945_rx_packet *pkt,
512 struct ieee80211_hdr *header, int group100)
513{
514}
515#endif
516
4bd9b4f3
AG		 517/* This is necessary only for a number of statistics, see the caller. */
518static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
519 struct ieee80211_hdr *header)
520{
521 /* Filter incoming packets to determine if they are targeted toward
522 * this network, discarding packets coming from ourselves */
523 switch (priv->iw_mode) {
524 case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
525 /* packets to our IBSS update information */
526 return !compare_ether_addr(header->addr3, priv->bssid);
527 case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
528 /* packets to our IBSS update information */
529 return !compare_ether_addr(header->addr2, priv->bssid);
530 default:
531 return 1;
532 }
533}
17744ff6 534
bd8a040e
RR		 535static void iwl3945_add_radiotap(struct iwl3945_priv *priv,
536 struct sk_buff *skb,
537 struct iwl3945_rx_frame_hdr *rx_hdr,
538 struct ieee80211_rx_status *stats)
12342c47
ZY		 539{
540 /* First cache any information we need before we overwrite
541 * the information provided in the skb from the hardware */
566bfe5a 542 s8 signal = stats->signal;
12342c47 543 s8 noise = 0;
8318d78a 544 int rate = stats->rate_idx;
12342c47 545 u64 tsf = stats->mactime;
a0b484fe 546 __le16 phy_flags_hw = rx_hdr->phy_flags, antenna;
12342c47
ZY		 547
548 struct iwl3945_rt_rx_hdr {
549 struct ieee80211_radiotap_header rt_hdr;
550 __le64 rt_tsf; /* TSF */
551 u8 rt_flags; /* radiotap packet flags */
552 u8 rt_rate; /* rate in 500kb/s */
553 __le16 rt_channelMHz; /* channel in MHz */
554 __le16 rt_chbitmask; /* channel bitfield */
555 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
556 s8 rt_dbmnoise;
557 u8 rt_antenna; /* antenna number */
558 } __attribute__ ((packed)) *iwl3945_rt;
559
560 if (skb_headroom(skb) < sizeof(*iwl3945_rt)) {
561 if (net_ratelimit())
562 printk(KERN_ERR "not enough headroom [%d] for "
d2594d07 563 "radiotap head [%zd]\n",
12342c47
ZY		 564 skb_headroom(skb), sizeof(*iwl3945_rt));
565 return;
566 }
567
568 /* put radiotap header in front of 802.11 header and data */
569 iwl3945_rt = (void *)skb_push(skb, sizeof(*iwl3945_rt));
570
571 /* initialise radiotap header */
572 iwl3945_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
573 iwl3945_rt->rt_hdr.it_pad = 0;
574
575 /* total header + data */
533dd1b0 576 put_unaligned_le16(sizeof(*iwl3945_rt), &iwl3945_rt->rt_hdr.it_len);
12342c47
ZY		 577
578 /* Indicate all the fields we add to the radiotap header */
533dd1b0
HH		 579 put_unaligned_le32((1 << IEEE80211_RADIOTAP_TSFT) |
580 (1 << IEEE80211_RADIOTAP_FLAGS) |
581 (1 << IEEE80211_RADIOTAP_RATE) |
582 (1 << IEEE80211_RADIOTAP_CHANNEL) |
583 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
584 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
585 (1 << IEEE80211_RADIOTAP_ANTENNA),
586 &iwl3945_rt->rt_hdr.it_present);
12342c47
ZY		 587
588 /* Zero the flags, we'll add to them as we go */
589 iwl3945_rt->rt_flags = 0;
590
533dd1b0 591 put_unaligned_le64(tsf, &iwl3945_rt->rt_tsf);
12342c47
ZY		 592
593 iwl3945_rt->rt_dbmsignal = signal;
594 iwl3945_rt->rt_dbmnoise = noise;
595
596 /* Convert the channel frequency and set the flags */
533dd1b0 597 put_unaligned_le16(stats->freq, &iwl3945_rt->rt_channelMHz);
12342c47 598 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
533dd1b0 599 put_unaligned_le16(IEEE80211_CHAN_OFDM | IEEE80211_CHAN_5GHZ,
12342c47
ZY		 600 &iwl3945_rt->rt_chbitmask);
601 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
533dd1b0 602 put_unaligned_le16(IEEE80211_CHAN_CCK | IEEE80211_CHAN_2GHZ,
12342c47
ZY		 603 &iwl3945_rt->rt_chbitmask);
604 else /* 802.11g */
533dd1b0 605 put_unaligned_le16(IEEE80211_CHAN_OFDM | IEEE80211_CHAN_2GHZ,
12342c47
ZY		 606 &iwl3945_rt->rt_chbitmask);
607
12342c47
ZY		 608 if (rate == -1)
609 iwl3945_rt->rt_rate = 0;
ec04fd60
RF		 610 else {
611 if (stats->band == IEEE80211_BAND_5GHZ)
612 rate += IWL_FIRST_OFDM_RATE;
613
12342c47 614 iwl3945_rt->rt_rate = iwl3945_rates[rate].ieee;
ec04fd60 615 }
12342c47
ZY		 616
617 /* antenna number */
a0b484fe
JB		 618 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
619 iwl3945_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 620
621 /* set the preamble flag if we have it */
622 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
623 iwl3945_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
624
625 stats->flag |= RX_FLAG_RADIOTAP;
626}
627
4bd9b4f3 628static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
bb8c093b 629 struct iwl3945_rx_mem_buffer *rxb,
12342c47 630 struct ieee80211_rx_status *stats)
b481de9c 631{
bb8c093b 632 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
699669f3 633#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 634 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 635#endif
bb8c093b
CH		 636 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
637 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 638 short len = le16_to_cpu(rx_hdr->len);
639
640 /* We received data from the HW, so stop the watchdog */
641 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
642 IWL_DEBUG_DROP("Corruption detected!\n");
643 return;
644 }
645
646 /* We only process data packets if the interface is open */
647 if (unlikely(!priv->is_open)) {
648 IWL_DEBUG_DROP_LIMIT
649 ("Dropping packet while interface is not open.\n");
650 return;
651 }
b481de9c
ZY		 652
653 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
654 /* Set the size of the skb to the size of the frame */
655 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
656
bb8c093b
CH		 657 if (iwl3945_param_hwcrypto)
658 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 659 le32_to_cpu(rx_end->status), stats);
660
12342c47
ZY		 661 if (priv->add_radiotap)
662 iwl3945_add_radiotap(priv, rxb->skb, rx_hdr, stats);
663
ab53d8af 664#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 665 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 666 priv->rxtxpackets += len;
667#endif
b481de9c
ZY		 668 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
669 rxb->skb = NULL;
670}
671
7878a5a4
MA		 672#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
673
bb8c093b
CH		 674static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
675 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 676{
17744ff6
TW		 677 struct ieee80211_hdr *header;
678 struct ieee80211_rx_status rx_status;
bb8c093b
CH		 679 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
680 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
681 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
682 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 683 int snr;
b481de9c
ZY		 684 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
685 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 686 u8 network_packet;
17744ff6
TW		 687
688 rx_status.antenna = 0;
689 rx_status.flag = 0;
690 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 691 rx_status.freq =
c0186078 692 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 693 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
694 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
695
696 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 697 if (rx_status.band == IEEE80211_BAND_5GHZ)
698 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c
ZY		 699
700 if ((unlikely(rx_stats->phy_count > 20))) {
701 IWL_DEBUG_DROP
702 ("dsp size out of range [0,20]: "
703 "%d/n", rx_stats->phy_count);
704 return;
705 }
706
707 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
708 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
709 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
710 return;
711 }
712
56decd3c 713
b481de9c
ZY		 714
715 /* Convert 3945's rssi indicator to dBm */
566bfe5a 716 rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
b481de9c
ZY		 717
718 /* Set default noise value to -127 */
719 if (priv->last_rx_noise == 0)
720 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
721
722 /* 3945 provides noise info for OFDM frames only.
723 * sig_avg and noise_diff are measured by the 3945's digital signal
724 * processor (DSP), and indicate linear levels of signal level and
725 * distortion/noise within the packet preamble after
726 * automatic gain control (AGC). sig_avg should stay fairly
727 * constant if the radio's AGC is working well.
728 * Since these values are linear (not dB or dBm), linear
729 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
730 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
731 * to obtain noise level in dBm.
17744ff6 732 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 733 if (rx_stats_noise_diff) {
734 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 735 rx_status.noise = rx_status.signal -
17744ff6 736 iwl3945_calc_db_from_ratio(snr);
566bfe5a 737 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 738 rx_status.noise);
b481de9c
ZY		 739
740 /* If noise info not available, calculate signal quality indicator (%)
741 * using just the dBm signal level. */
742 } else {
17744ff6 743 rx_status.noise = priv->last_rx_noise;
566bfe5a 744 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 745 }
746
747
748 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 749 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 750 rx_stats_sig_avg, rx_stats_noise_diff);
751
b481de9c
ZY		 752 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
753
bb8c093b 754 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 755
17744ff6
TW		 756 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
757 network_packet ? '*' : ' ',
758 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 759 rx_status.signal, rx_status.signal,
760 rx_status.noise, rx_status.rate_idx);
b481de9c 761
17744ff6 762#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 763 if (iwl3945_debug_level & (IWL_DL_RX))
b481de9c 764 /* Set "1" to report good data frames in groups of 100 */
17744ff6 765 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 766#endif
767
768 if (network_packet) {
769 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
770 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 771 priv->last_rx_rssi = rx_status.signal;
17744ff6 772 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 773 }
774
56decd3c
ML		 775 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
776 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
777 return;
778 }
779
b481de9c
ZY		 780 switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) {
781 case IEEE80211_FTYPE_MGMT:
782 switch (le16_to_cpu(header->frame_control) &
783 IEEE80211_FCTL_STYPE) {
784 case IEEE80211_STYPE_PROBE_RESP:
785 case IEEE80211_STYPE_BEACON:{
786 /* If this is a beacon or probe response for
787 * our network then cache the beacon
788 * timestamp */
789 if ((((priv->iw_mode == IEEE80211_IF_TYPE_STA)
790 && !compare_ether_addr(header->addr2,
791 priv->bssid)) ||
792 ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
793 && !compare_ether_addr(header->addr3,
794 priv->bssid)))) {
795 struct ieee80211_mgmt *mgmt =
796 (struct ieee80211_mgmt *)header;
797 __le32 *pos;
798 pos =
799 (__le32 *) & mgmt->u.beacon.
800 timestamp;
801 priv->timestamp0 = le32_to_cpu(pos[0]);
802 priv->timestamp1 = le32_to_cpu(pos[1]);
803 priv->beacon_int = le16_to_cpu(
804 mgmt->u.beacon.beacon_int);
805 if (priv->call_post_assoc_from_beacon &&
806 (priv->iw_mode ==
807 IEEE80211_IF_TYPE_STA))
808 queue_work(priv->workqueue,
809 &priv->post_associate.work);
810
811 priv->call_post_assoc_from_beacon = 0;
812 }
813
814 break;
815 }
816
817 case IEEE80211_STYPE_ACTION:
818 /* TODO: Parse 802.11h frames for CSA... */
819 break;
820
821 /*
471b3efd
JB		 822 * TODO: Use the new callback function from
823 * mac80211 instead of sniffing these packets.
b481de9c
ZY		 824 */
825 case IEEE80211_STYPE_ASSOC_RESP:
826 case IEEE80211_STYPE_REASSOC_RESP:{
827 struct ieee80211_mgmt *mgnt =
828 (struct ieee80211_mgmt *)header;
7878a5a4
MA		 829
830 /* We have just associated, give some
831 * time for the 4-way handshake if
832 * any. Don't start scan too early. */
833 priv->next_scan_jiffies = jiffies +
834 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
835
b481de9c
ZY		 836 priv->assoc_id = (~((1 << 15) | (1 << 14)) &
837 le16_to_cpu(mgnt->u.
838 assoc_resp.aid));
839 priv->assoc_capability =
840 le16_to_cpu(mgnt->u.assoc_resp.capab_info);
841 if (priv->beacon_int)
842 queue_work(priv->workqueue,
843 &priv->post_associate.work);
844 else
845 priv->call_post_assoc_from_beacon = 1;
846 break;
847 }
848
849 case IEEE80211_STYPE_PROBE_REQ:{
0795af57
JP		 850 DECLARE_MAC_BUF(mac1);
851 DECLARE_MAC_BUF(mac2);
852 DECLARE_MAC_BUF(mac3);
b481de9c
ZY		 853 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
854 IWL_DEBUG_DROP
0795af57
JP		 855 ("Dropping (non network): %s"
856 ", %s, %s\n",
857 print_mac(mac1, header->addr1),
858 print_mac(mac2, header->addr2),
859 print_mac(mac3, header->addr3));
b481de9c
ZY		 860 return;
861 }
862 }
863
4bd9b4f3
AG		 864 case IEEE80211_FTYPE_DATA:
865 /* fall through */
866 default:
867 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c 868 break;
0795af57 869 }
b481de9c
ZY		 870}
871
bb8c093b 872int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
b481de9c
ZY		 873 dma_addr_t addr, u16 len)
874{
875 int count;
876 u32 pad;
bb8c093b 877 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 878
879 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
880 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
881
882 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
883 IWL_ERROR("Error can not send more than %d chunks\n",
884 NUM_TFD_CHUNKS);
885 return -EINVAL;
886 }
887
888 tfd->pa[count].addr = cpu_to_le32(addr);
889 tfd->pa[count].len = cpu_to_le32(len);
890
891 count++;
892
893 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
894 TFD_CTL_PAD_SET(pad));
895
896 return 0;
897}
898
899/**
bb8c093b 900 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 901 *
902 * Does NOT advance any indexes
903 */
bb8c093b 904int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 905{
bb8c093b
CH		 906 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
907 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 908 struct pci_dev *dev = priv->pci_dev;
909 int i;
910 int counter;
911
912 /* classify bd */
913 if (txq->q.id == IWL_CMD_QUEUE_NUM)
914 /* nothing to cleanup after for host commands */
915 return 0;
916
917 /* sanity check */
918 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
919 if (counter > NUM_TFD_CHUNKS) {
920 IWL_ERROR("Too many chunks: %i\n", counter);
921 /* @todo issue fatal error, it is quite serious situation */
922 return 0;
923 }
924
925 /* unmap chunks if any */
926
927 for (i = 1; i < counter; i++) {
928 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
929 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 930 if (txq->txb[txq->q.read_ptr].skb[0]) {
931 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
932 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 933 /* Can be called from interrupt context */
934 dev_kfree_skb_any(skb);
fc4b6853 935 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 936 }
937 }
938 }
939 return 0;
940}
941
bb8c093b 942u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
b481de9c
ZY		 943{
944 int i;
945 int ret = IWL_INVALID_STATION;
946 unsigned long flags;
0795af57 947 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 948
949 spin_lock_irqsave(&priv->sta_lock, flags);
950 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
951 if ((priv->stations[i].used) &&
952 (!compare_ether_addr
953 (priv->stations[i].sta.sta.addr, addr))) {
954 ret = i;
955 goto out;
956 }
957
0795af57
JP		 958 IWL_DEBUG_INFO("can not find STA %s (total %d)\n",
959 print_mac(mac, addr), priv->num_stations);
b481de9c
ZY		 960 out:
961 spin_unlock_irqrestore(&priv->sta_lock, flags);
962 return ret;
963}
964
965/**
bb8c093b 966 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 967 *
968*/
bb8c093b
CH		 969void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
970 struct iwl3945_cmd *cmd,
e039fa4a 971 struct ieee80211_tx_info *info,
b481de9c
ZY		 972 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
973{
974 unsigned long flags;
e039fa4a 975 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 976 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 977 u16 rate_mask;
978 int rate;
979 u8 rts_retry_limit;
980 u8 data_retry_limit;
981 __le32 tx_flags;
fd7c8a40 982 __le16 fc = hdr->frame_control;
b481de9c 983
bb8c093b 984 rate = iwl3945_rates[rate_index].plcp;
b481de9c
ZY		 985 tx_flags = cmd->cmd.tx.tx_flags;
986
987 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 988 * in this running context */
b481de9c
ZY		 989 rate_mask = IWL_RATES_MASK;
990
991 spin_lock_irqsave(&priv->sta_lock, flags);
992
993 priv->stations[sta_id].current_rate.rate_n_flags = rate;
994
995 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
a4062b8f 996 (sta_id != priv->hw_setting.bcast_sta_id) &&
b481de9c
ZY		 997 (sta_id != IWL_MULTICAST_ID))
998 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
999
1000 spin_unlock_irqrestore(&priv->sta_lock, flags);
1001
1002 if (tx_id >= IWL_CMD_QUEUE_NUM)
1003 rts_retry_limit = 3;
1004 else
1005 rts_retry_limit = 7;
1006
fd7c8a40 1007 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 1008 data_retry_limit = 3;
1009 if (data_retry_limit < rts_retry_limit)
1010 rts_retry_limit = data_retry_limit;
1011 } else
1012 data_retry_limit = IWL_DEFAULT_TX_RETRY;
1013
1014 if (priv->data_retry_limit != -1)
1015 data_retry_limit = priv->data_retry_limit;
1016
fd7c8a40
HH		 1017 if (ieee80211_is_mgmt(fc)) {
1018 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
1019 case cpu_to_le16(IEEE80211_STYPE_AUTH):
1020 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
1021 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
1022 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 1023 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
1024 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
1025 tx_flags |= TX_CMD_FLG_CTS_MSK;
1026 }
1027 break;
1028 default:
1029 break;
1030 }
1031 }
1032
1033 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
1034 cmd->cmd.tx.data_retry_limit = data_retry_limit;
1035 cmd->cmd.tx.rate = rate;
1036 cmd->cmd.tx.tx_flags = tx_flags;
1037
1038 /* OFDM */
14577f23
MA		 1039 cmd->cmd.tx.supp_rates[0] =
1040 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 1041
1042 /* CCK */
14577f23 1043 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 1044
1045 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
1046 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
1047 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
1048 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
1049}
1050
bb8c093b 1051u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 1052{
1053 unsigned long flags_spin;
bb8c093b 1054 struct iwl3945_station_entry *station;
b481de9c
ZY		 1055
1056 if (sta_id == IWL_INVALID_STATION)
1057 return IWL_INVALID_STATION;
1058
1059 spin_lock_irqsave(&priv->sta_lock, flags_spin);
1060 station = &priv->stations[sta_id];
1061
1062 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
1063 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
1064 station->current_rate.rate_n_flags = tx_rate;
1065 station->sta.mode = STA_CONTROL_MODIFY_MSK;
1066
1067 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
1068
bb8c093b 1069 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 1070 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
1071 sta_id, tx_rate);
1072 return sta_id;
1073}
1074
bb8c093b 1075static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
b481de9c
ZY		 1076{
1077 int rc;
1078 unsigned long flags;
1079
1080 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1081 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1082 if (rc) {
1083 spin_unlock_irqrestore(&priv->lock, flags);
1084 return rc;
1085 }
1086
1087 if (!pwr_max) {
1088 u32 val;
1089
1090 rc = pci_read_config_dword(priv->pci_dev,
1091 PCI_POWER_SOURCE, &val);
1092 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
bb8c093b 1093 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1094 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
1095 ~APMG_PS_CTRL_MSK_PWR_SRC);
bb8c093b 1096 iwl3945_release_nic_access(priv);
b481de9c 1097
bb8c093b 1098 iwl3945_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 1099 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
1100 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
1101 } else
bb8c093b 1102 iwl3945_release_nic_access(priv);
b481de9c 1103 } else {
bb8c093b 1104 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1105 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
1106 ~APMG_PS_CTRL_MSK_PWR_SRC);
1107
bb8c093b
CH		 1108 iwl3945_release_nic_access(priv);
1109 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 1110 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
1111 }
1112 spin_unlock_irqrestore(&priv->lock, flags);
1113
1114 return rc;
1115}
1116
bb8c093b 1117static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 1118{
1119 int rc;
1120 unsigned long flags;
1121
1122 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1123 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1124 if (rc) {
1125 spin_unlock_irqrestore(&priv->lock, flags);
1126 return rc;
1127 }
1128
bb8c093b
CH		 1129 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
1130 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
b481de9c 1131 priv->hw_setting.shared_phys +
bb8c093b
CH		 1132 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
1133 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
1134 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
b481de9c
ZY		 1135 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
1136 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
1137 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
1138 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
1139 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
1140 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
1141 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
1142 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
1143
1144 /* fake read to flush all prev I/O */
bb8c093b 1145 iwl3945_read_direct32(priv, FH_RSSR_CTRL);
b481de9c 1146
bb8c093b 1147 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1148 spin_unlock_irqrestore(&priv->lock, flags);
1149
1150 return 0;
1151}
1152
bb8c093b 1153static int iwl3945_tx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1154{
1155 int rc;
1156 unsigned long flags;
1157
1158 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1159 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1160 if (rc) {
1161 spin_unlock_irqrestore(&priv->lock, flags);
1162 return rc;
1163 }
1164
1165 /* bypass mode */
bb8c093b 1166 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1167
1168 /* RA 0 is active */
bb8c093b 1169 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1170
1171 /* all 6 fifo are active */
bb8c093b 1172 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1173
bb8c093b
CH		 1174 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1175 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1176 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1177 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1178
bb8c093b 1179 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
b481de9c
ZY		 1180 priv->hw_setting.shared_phys);
1181
bb8c093b 1182 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
b481de9c
ZY		 1183 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1184 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1185 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1186 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1187 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1188 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1189 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1190
bb8c093b 1191 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1192 spin_unlock_irqrestore(&priv->lock, flags);
1193
1194 return 0;
1195}
1196
1197/**
1198 * iwl3945_txq_ctx_reset - Reset TX queue context
1199 *
1200 * Destroys all DMA structures and initialize them again
1201 */
bb8c093b 1202static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1203{
1204 int rc;
1205 int txq_id, slots_num;
1206
bb8c093b 1207 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1208
1209 /* Tx CMD queue */
1210 rc = iwl3945_tx_reset(priv);
1211 if (rc)
1212 goto error;
1213
1214 /* Tx queue(s) */
1215 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1216 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1217 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 1218 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 1219 txq_id);
1220 if (rc) {
1221 IWL_ERROR("Tx %d queue init failed\n", txq_id);
1222 goto error;
1223 }
1224 }
1225
1226 return rc;
1227
1228 error:
bb8c093b 1229 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1230 return rc;
1231}
1232
bb8c093b 1233int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
b481de9c
ZY		 1234{
1235 u8 rev_id;
1236 int rc;
1237 unsigned long flags;
bb8c093b 1238 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 1239
bb8c093b 1240 iwl3945_power_init_handle(priv);
b481de9c
ZY		 1241
1242 spin_lock_irqsave(&priv->lock, flags);
a693f187 1243 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
bb8c093b 1244 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 1245 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1246
bb8c093b
CH		 1247 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1248 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1249 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1250 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1251 if (rc < 0) {
1252 spin_unlock_irqrestore(&priv->lock, flags);
1253 IWL_DEBUG_INFO("Failed to init the card\n");
1254 return rc;
1255 }
1256
bb8c093b 1257 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1258 if (rc) {
1259 spin_unlock_irqrestore(&priv->lock, flags);
1260 return rc;
1261 }
bb8c093b 1262 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1263 APMG_CLK_VAL_DMA_CLK_RQT |
1264 APMG_CLK_VAL_BSM_CLK_RQT);
1265 udelay(20);
bb8c093b 1266 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c 1267 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
bb8c093b 1268 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1269 spin_unlock_irqrestore(&priv->lock, flags);
1270
1271 /* Determine HW type */
1272 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1273 if (rc)
1274 return rc;
1275 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1276
1277 iwl3945_nic_set_pwr_src(priv, 1);
1278 spin_lock_irqsave(&priv->lock, flags);
1279
1280 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1281 IWL_DEBUG_INFO("RTP type \n");
1282 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1283 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
bb8c093b 1284 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1285 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1286 } else {
6f83eaa1 1287 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
bb8c093b 1288 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1289 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1290 }
1291
b481de9c
ZY		 1292 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1293 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
bb8c093b 1294 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1295 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1296 } else
1297 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1298
1299 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1300 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1301 priv->eeprom.board_revision);
bb8c093b 1302 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1303 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1304 } else {
1305 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1306 priv->eeprom.board_revision);
bb8c093b 1307 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1308 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1309 }
1310
1311 if (priv->eeprom.almgor_m_version <= 1) {
bb8c093b 1312 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1313 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c
ZY		 1314 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1315 priv->eeprom.almgor_m_version);
1316 } else {
1317 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1318 priv->eeprom.almgor_m_version);
bb8c093b 1319 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1320 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1321 }
1322 spin_unlock_irqrestore(&priv->lock, flags);
1323
1324 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1325 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1326
1327 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1328 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1329
1330 /* Allocate the RX queue, or reset if it is already allocated */
1331 if (!rxq->bd) {
bb8c093b 1332 rc = iwl3945_rx_queue_alloc(priv);
b481de9c
ZY		 1333 if (rc) {
1334 IWL_ERROR("Unable to initialize Rx queue\n");
1335 return -ENOMEM;
1336 }
1337 } else
bb8c093b 1338 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1339
bb8c093b 1340 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1341
1342 iwl3945_rx_init(priv, rxq);
1343
1344 spin_lock_irqsave(&priv->lock, flags);
1345
1346 /* Look at using this instead:
1347 rxq->need_update = 1;
bb8c093b 1348 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1349 */
1350
bb8c093b 1351 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1352 if (rc) {
1353 spin_unlock_irqrestore(&priv->lock, flags);
1354 return rc;
1355 }
bb8c093b
CH		 1356 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1357 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1358
1359 spin_unlock_irqrestore(&priv->lock, flags);
1360
1361 rc = iwl3945_txq_ctx_reset(priv);
1362 if (rc)
1363 return rc;
1364
1365 set_bit(STATUS_INIT, &priv->status);
1366
1367 return 0;
1368}
1369
1370/**
bb8c093b 1371 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1372 *
1373 * Destroy all TX DMA queues and structures
1374 */
bb8c093b 1375void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
b481de9c
ZY		 1376{
1377 int txq_id;
1378
1379 /* Tx queues */
1380 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
bb8c093b 1381 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c
ZY		 1382}
1383
bb8c093b 1384void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 1385{
1386 int queue;
1387 unsigned long flags;
1388
1389 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1390 if (iwl3945_grab_nic_access(priv)) {
b481de9c 1391 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1392 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1393 return;
1394 }
1395
1396 /* stop SCD */
bb8c093b 1397 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1398
1399 /* reset TFD queues */
1400 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
bb8c093b
CH		 1401 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1402 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
b481de9c
ZY		 1403 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1404 1000);
1405 }
1406
bb8c093b 1407 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1408 spin_unlock_irqrestore(&priv->lock, flags);
1409
bb8c093b 1410 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1411}
1412
bb8c093b 1413int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
b481de9c
ZY		 1414{
1415 int rc = 0;
1416 u32 reg_val;
1417 unsigned long flags;
1418
1419 spin_lock_irqsave(&priv->lock, flags);
1420
1421 /* set stop master bit */
bb8c093b 1422 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1423
bb8c093b 1424 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 1425
1426 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1427 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1428 IWL_DEBUG_INFO("Card in power save, master is already "
1429 "stopped\n");
1430 else {
bb8c093b 1431 rc = iwl3945_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 1432 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1433 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1434 if (rc < 0) {
1435 spin_unlock_irqrestore(&priv->lock, flags);
1436 return rc;
1437 }
1438 }
1439
1440 spin_unlock_irqrestore(&priv->lock, flags);
1441 IWL_DEBUG_INFO("stop master\n");
1442
1443 return rc;
1444}
1445
bb8c093b 1446int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1447{
1448 int rc;
1449 unsigned long flags;
1450
bb8c093b 1451 iwl3945_hw_nic_stop_master(priv);
b481de9c
ZY		 1452
1453 spin_lock_irqsave(&priv->lock, flags);
1454
bb8c093b 1455 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1456
bb8c093b 1457 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1458 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1459 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1460
bb8c093b 1461 rc = iwl3945_grab_nic_access(priv);
b481de9c 1462 if (!rc) {
bb8c093b 1463 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1464 APMG_CLK_VAL_BSM_CLK_RQT);
1465
1466 udelay(10);
1467
bb8c093b 1468 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1469 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1470
bb8c093b
CH		 1471 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1472 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1473 0xFFFFFFFF);
1474
1475 /* enable DMA */
bb8c093b 1476 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1477 APMG_CLK_VAL_DMA_CLK_RQT |
1478 APMG_CLK_VAL_BSM_CLK_RQT);
1479 udelay(10);
1480
bb8c093b 1481 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1482 APMG_PS_CTRL_VAL_RESET_REQ);
1483 udelay(5);
bb8c093b 1484 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1485 APMG_PS_CTRL_VAL_RESET_REQ);
bb8c093b 1486 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1487 }
1488
1489 /* Clear the 'host command active' bit... */
1490 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1491
1492 wake_up_interruptible(&priv->wait_command_queue);
1493 spin_unlock_irqrestore(&priv->lock, flags);
1494
1495 return rc;
1496}
1497
1498/**
bb8c093b 1499 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1500 * return index delta into power gain settings table
1501*/
bb8c093b 1502static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1503{
1504 return (new_reading - old_reading) * (-11) / 100;
1505}
1506
1507/**
bb8c093b 1508 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1509 */
bb8c093b 1510static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c
ZY		 1511{
1512 return (((temperature < -260) || (temperature > 25)) ? 1 : 0);
1513}
1514
bb8c093b 1515int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
b481de9c 1516{
bb8c093b 1517 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1518}
1519
1520/**
bb8c093b 1521 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1522 * get the current temperature by reading from NIC
1523*/
bb8c093b 1524static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
b481de9c
ZY		 1525{
1526 int temperature;
1527
bb8c093b 1528 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1529
1530 /* driver's okay range is -260 to +25.
1531 * human readable okay range is 0 to +285 */
1532 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1533
1534 /* handle insane temp reading */
bb8c093b 1535 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
b481de9c
ZY		 1536 IWL_ERROR("Error bad temperature value %d\n", temperature);
1537
1538 /* if really really hot(?),
1539 * substitute the 3rd band/group's temp measured at factory */
1540 if (priv->last_temperature > 100)
1541 temperature = priv->eeprom.groups[2].temperature;
1542 else /* else use most recent "sane" value from driver */
1543 temperature = priv->last_temperature;
1544 }
1545
1546 return temperature; /* raw, not "human readable" */
1547}
1548
1549/* Adjust Txpower only if temperature variance is greater than threshold.
1550 *
1551 * Both are lower than older versions' 9 degrees */
1552#define IWL_TEMPERATURE_LIMIT_TIMER 6
1553
1554/**
1555 * is_temp_calib_needed - determines if new calibration is needed
1556 *
1557 * records new temperature in tx_mgr->temperature.
1558 * replaces tx_mgr->last_temperature *only* if calib needed
1559 * (assumes caller will actually do the calibration!). */
bb8c093b 1560static int is_temp_calib_needed(struct iwl3945_priv *priv)
b481de9c
ZY		 1561{
1562 int temp_diff;
1563
bb8c093b 1564 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1565 temp_diff = priv->temperature - priv->last_temperature;
1566
1567 /* get absolute value */
1568 if (temp_diff < 0) {
1569 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1570 temp_diff = -temp_diff;
1571 } else if (temp_diff == 0)
1572 IWL_DEBUG_POWER("Same temp,\n");
1573 else
1574 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1575
1576 /* if we don't need calibration, *don't* update last_temperature */
1577 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1578 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1579 return 0;
1580 }
1581
1582 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1583
1584 /* assume that caller will actually do calib ...
1585 * update the "last temperature" value */
1586 priv->last_temperature = priv->temperature;
1587 return 1;
1588}
1589
1590#define IWL_MAX_GAIN_ENTRIES 78
1591#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1592#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1593
1594/* radio and DSP power table, each step is 1/2 dB.
1595 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1596static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1597 {
1598 {251, 127}, /* 2.4 GHz, highest power */
1599 {251, 127},
1600 {251, 127},
1601 {251, 127},
1602 {251, 125},
1603 {251, 110},
1604 {251, 105},
1605 {251, 98},
1606 {187, 125},
1607 {187, 115},
1608 {187, 108},
1609 {187, 99},
1610 {243, 119},
1611 {243, 111},
1612 {243, 105},
1613 {243, 97},
1614 {243, 92},
1615 {211, 106},
1616 {211, 100},
1617 {179, 120},
1618 {179, 113},
1619 {179, 107},
1620 {147, 125},
1621 {147, 119},
1622 {147, 112},
1623 {147, 106},
1624 {147, 101},
1625 {147, 97},
1626 {147, 91},
1627 {115, 107},
1628 {235, 121},
1629 {235, 115},
1630 {235, 109},
1631 {203, 127},
1632 {203, 121},
1633 {203, 115},
1634 {203, 108},
1635 {203, 102},
1636 {203, 96},
1637 {203, 92},
1638 {171, 110},
1639 {171, 104},
1640 {171, 98},
1641 {139, 116},
1642 {227, 125},
1643 {227, 119},
1644 {227, 113},
1645 {227, 107},
1646 {227, 101},
1647 {227, 96},
1648 {195, 113},
1649 {195, 106},
1650 {195, 102},
1651 {195, 95},
1652 {163, 113},
1653 {163, 106},
1654 {163, 102},
1655 {163, 95},
1656 {131, 113},
1657 {131, 106},
1658 {131, 102},
1659 {131, 95},
1660 {99, 113},
1661 {99, 106},
1662 {99, 102},
1663 {99, 95},
1664 {67, 113},
1665 {67, 106},
1666 {67, 102},
1667 {67, 95},
1668 {35, 113},
1669 {35, 106},
1670 {35, 102},
1671 {35, 95},
1672 {3, 113},
1673 {3, 106},
1674 {3, 102},
1675 {3, 95} }, /* 2.4 GHz, lowest power */
1676 {
1677 {251, 127}, /* 5.x GHz, highest power */
1678 {251, 120},
1679 {251, 114},
1680 {219, 119},
1681 {219, 101},
1682 {187, 113},
1683 {187, 102},
1684 {155, 114},
1685 {155, 103},
1686 {123, 117},
1687 {123, 107},
1688 {123, 99},
1689 {123, 92},
1690 {91, 108},
1691 {59, 125},
1692 {59, 118},
1693 {59, 109},
1694 {59, 102},
1695 {59, 96},
1696 {59, 90},
1697 {27, 104},
1698 {27, 98},
1699 {27, 92},
1700 {115, 118},
1701 {115, 111},
1702 {115, 104},
1703 {83, 126},
1704 {83, 121},
1705 {83, 113},
1706 {83, 105},
1707 {83, 99},
1708 {51, 118},
1709 {51, 111},
1710 {51, 104},
1711 {51, 98},
1712 {19, 116},
1713 {19, 109},
1714 {19, 102},
1715 {19, 98},
1716 {19, 93},
1717 {171, 113},
1718 {171, 107},
1719 {171, 99},
1720 {139, 120},
1721 {139, 113},
1722 {139, 107},
1723 {139, 99},
1724 {107, 120},
1725 {107, 113},
1726 {107, 107},
1727 {107, 99},
1728 {75, 120},
1729 {75, 113},
1730 {75, 107},
1731 {75, 99},
1732 {43, 120},
1733 {43, 113},
1734 {43, 107},
1735 {43, 99},
1736 {11, 120},
1737 {11, 113},
1738 {11, 107},
1739 {11, 99},
1740 {131, 107},
1741 {131, 99},
1742 {99, 120},
1743 {99, 113},
1744 {99, 107},
1745 {99, 99},
1746 {67, 120},
1747 {67, 113},
1748 {67, 107},
1749 {67, 99},
1750 {35, 120},
1751 {35, 113},
1752 {35, 107},
1753 {35, 99},
1754 {3, 120} } /* 5.x GHz, lowest power */
1755};
1756
bb8c093b 1757static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1758{
1759 if (index < 0)
1760 return 0;
1761 if (index >= IWL_MAX_GAIN_ENTRIES)
1762 return IWL_MAX_GAIN_ENTRIES - 1;
1763 return (u8) index;
1764}
1765
1766/* Kick off thermal recalibration check every 60 seconds */
1767#define REG_RECALIB_PERIOD (60)
1768
1769/**
bb8c093b 1770 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1771 *
1772 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1773 * or 6 Mbit (OFDM) rates.
1774 */
bb8c093b 1775static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
b481de9c 1776 s32 rate_index, const s8 *clip_pwrs,
bb8c093b 1777 struct iwl3945_channel_info *ch_info,
b481de9c
ZY		 1778 int band_index)
1779{
bb8c093b 1780 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1781 s8 power;
1782 u8 power_index;
1783
1784 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1785
1786 /* use this channel group's 6Mbit clipping/saturation pwr,
1787 * but cap at regulatory scan power restriction (set during init
1788 * based on eeprom channel data) for this channel. */
14577f23 1789 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1790
1791 /* further limit to user's max power preference.
1792 * FIXME: Other spectrum management power limitations do not
1793 * seem to apply?? */
1794 power = min(power, priv->user_txpower_limit);
1795 scan_power_info->requested_power = power;
1796
1797 /* find difference between new scan *power* and current "normal"
1798 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1799 * current "normal" temperature-compensated Tx power *index* for
1800 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1801 * *index*. */
1802 power_index = ch_info->power_info[rate_index].power_table_index
1803 - (power - ch_info->power_info
14577f23 1804 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1805
1806 /* store reference index that we use when adjusting *all* scan
1807 * powers. So we can accommodate user (all channel) or spectrum
1808 * management (single channel) power changes "between" temperature
1809 * feedback compensation procedures.
1810 * don't force fit this reference index into gain table; it may be a
1811 * negative number. This will help avoid errors when we're at
1812 * the lower bounds (highest gains, for warmest temperatures)
1813 * of the table. */
1814
1815 /* don't exceed table bounds for "real" setting */
bb8c093b 1816 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1817
1818 scan_power_info->power_table_index = power_index;
1819 scan_power_info->tpc.tx_gain =
1820 power_gain_table[band_index][power_index].tx_gain;
1821 scan_power_info->tpc.dsp_atten =
1822 power_gain_table[band_index][power_index].dsp_atten;
1823}
1824
1825/**
bb8c093b 1826 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1827 *
1828 * Configures power settings for all rates for the current channel,
1829 * using values from channel info struct, and send to NIC
1830 */
bb8c093b 1831int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
b481de9c 1832{
14577f23 1833 int rate_idx, i;
bb8c093b
CH		 1834 const struct iwl3945_channel_info *ch_info = NULL;
1835 struct iwl3945_txpowertable_cmd txpower = {
b481de9c
ZY		 1836 .channel = priv->active_rxon.channel,
1837 };
1838
8318d78a 1839 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1840 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1841 priv->band,
b481de9c
ZY		 1842 le16_to_cpu(priv->active_rxon.channel));
1843 if (!ch_info) {
1844 IWL_ERROR
1845 ("Failed to get channel info for channel %d [%d]\n",
8318d78a 1846 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1847 return -EINVAL;
1848 }
1849
1850 if (!is_channel_valid(ch_info)) {
1851 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1852 "non-Tx channel.\n");
1853 return 0;
1854 }
1855
1856 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1857 /* Fill OFDM rate */
1858 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1859 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1860
1861 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1862 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1863
1864 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1865 le16_to_cpu(txpower.channel),
1866 txpower.band,
14577f23
MA		 1867 txpower.power[i].tpc.tx_gain,
1868 txpower.power[i].tpc.dsp_atten,
1869 txpower.power[i].rate);
1870 }
1871 /* Fill CCK rates */
1872 for (rate_idx = IWL_FIRST_CCK_RATE;
1873 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1874 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1875 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1876
1877 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1878 le16_to_cpu(txpower.channel),
1879 txpower.band,
1880 txpower.power[i].tpc.tx_gain,
1881 txpower.power[i].tpc.dsp_atten,
1882 txpower.power[i].rate);
b481de9c
ZY		 1883 }
1884
bb8c093b
CH		 1885 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1886 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1887
1888}
1889
1890/**
bb8c093b 1891 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1892 * @ch_info: Channel to update. Uses power_info.requested_power.
1893 *
1894 * Replace requested_power and base_power_index ch_info fields for
1895 * one channel.
1896 *
1897 * Called if user or spectrum management changes power preferences.
1898 * Takes into account h/w and modulation limitations (clip power).
1899 *
1900 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1901 *
1902 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1903 * properly fill out the scan powers, and actual h/w gain settings,
1904 * and send changes to NIC
1905 */
bb8c093b
CH		 1906static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1907 struct iwl3945_channel_info *ch_info)
b481de9c 1908{
bb8c093b 1909 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1910 int power_changed = 0;
1911 int i;
1912 const s8 *clip_pwrs;
1913 int power;
1914
1915 /* Get this chnlgrp's rate-to-max/clip-powers table */
1916 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1917
1918 /* Get this channel's rate-to-current-power settings table */
1919 power_info = ch_info->power_info;
1920
1921 /* update OFDM Txpower settings */
14577f23 1922 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1923 i++, ++power_info) {
1924 int delta_idx;
1925
1926 /* limit new power to be no more than h/w capability */
1927 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1928 if (power == power_info->requested_power)
1929 continue;
1930
1931 /* find difference between old and new requested powers,
1932 * update base (non-temp-compensated) power index */
1933 delta_idx = (power - power_info->requested_power) * 2;
1934 power_info->base_power_index -= delta_idx;
1935
1936 /* save new requested power value */
1937 power_info->requested_power = power;
1938
1939 power_changed = 1;
1940 }
1941
1942 /* update CCK Txpower settings, based on OFDM 12M setting ...
1943 * ... all CCK power settings for a given channel are the *same*. */
1944 if (power_changed) {
1945 power =
14577f23 1946 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1947 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1948
bb8c093b 1949 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1950 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1951 power_info->requested_power = power;
1952 power_info->base_power_index =
14577f23 1953 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1954 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1955 ++power_info;
1956 }
1957 }
1958
1959 return 0;
1960}
1961
1962/**
bb8c093b 1963 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1964 *
1965 * NOTE: Returned power limit may be less (but not more) than requested,
1966 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1967 * (no consideration for h/w clipping limitations).
1968 */
bb8c093b 1969static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
b481de9c
ZY		 1970{
1971 s8 max_power;
1972
1973#if 0
1974 /* if we're using TGd limits, use lower of TGd or EEPROM */
1975 if (ch_info->tgd_data.max_power != 0)
1976 max_power = min(ch_info->tgd_data.max_power,
1977 ch_info->eeprom.max_power_avg);
1978
1979 /* else just use EEPROM limits */
1980 else
1981#endif
1982 max_power = ch_info->eeprom.max_power_avg;
1983
1984 return min(max_power, ch_info->max_power_avg);
1985}
1986
1987/**
bb8c093b 1988 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1989 *
1990 * Compensate txpower settings of *all* channels for temperature.
1991 * This only accounts for the difference between current temperature
1992 * and the factory calibration temperatures, and bases the new settings
1993 * on the channel's base_power_index.
1994 *
1995 * If RxOn is "associated", this sends the new Txpower to NIC!
1996 */
bb8c093b 1997static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
b481de9c 1998{
bb8c093b 1999 struct iwl3945_channel_info *ch_info = NULL;
b481de9c
ZY		 2000 int delta_index;
2001 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
2002 u8 a_band;
2003 u8 rate_index;
2004 u8 scan_tbl_index;
2005 u8 i;
2006 int ref_temp;
2007 int temperature = priv->temperature;
2008
2009 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
2010 for (i = 0; i < priv->channel_count; i++) {
2011 ch_info = &priv->channel_info[i];
2012 a_band = is_channel_a_band(ch_info);
2013
2014 /* Get this chnlgrp's factory calibration temperature */
2015 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
2016 temperature;
2017
2018 /* get power index adjustment based on curr and factory
2019 * temps */
bb8c093b 2020 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 2021 ref_temp);
2022
2023 /* set tx power value for all rates, OFDM and CCK */
2024 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
2025 rate_index++) {
2026 int power_idx =
2027 ch_info->power_info[rate_index].base_power_index;
2028
2029 /* temperature compensate */
2030 power_idx += delta_index;
2031
2032 /* stay within table range */
bb8c093b 2033 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 2034 ch_info->power_info[rate_index].
2035 power_table_index = (u8) power_idx;
2036 ch_info->power_info[rate_index].tpc =
2037 power_gain_table[a_band][power_idx];
2038 }
2039
2040 /* Get this chnlgrp's rate-to-max/clip-powers table */
2041 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2042
2043 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2044 for (scan_tbl_index = 0;
2045 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2046 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2047 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2048 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2049 actual_index, clip_pwrs,
2050 ch_info, a_band);
2051 }
2052 }
2053
2054 /* send Txpower command for current channel to ucode */
bb8c093b 2055 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 2056}
2057
bb8c093b 2058int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
b481de9c 2059{
bb8c093b 2060 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 2061 s8 max_power;
2062 u8 a_band;
2063 u8 i;
2064
2065 if (priv->user_txpower_limit == power) {
2066 IWL_DEBUG_POWER("Requested Tx power same as current "
2067 "limit: %ddBm.\n", power);
2068 return 0;
2069 }
2070
2071 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
2072 priv->user_txpower_limit = power;
2073
2074 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
2075
2076 for (i = 0; i < priv->channel_count; i++) {
2077 ch_info = &priv->channel_info[i];
2078 a_band = is_channel_a_band(ch_info);
2079
2080 /* find minimum power of all user and regulatory constraints
2081 * (does not consider h/w clipping limitations) */
bb8c093b 2082 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 2083 max_power = min(power, max_power);
2084 if (max_power != ch_info->curr_txpow) {
2085 ch_info->curr_txpow = max_power;
2086
2087 /* this considers the h/w clipping limitations */
bb8c093b 2088 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 2089 }
2090 }
2091
2092 /* update txpower settings for all channels,
2093 * send to NIC if associated. */
2094 is_temp_calib_needed(priv);
bb8c093b 2095 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2096
2097 return 0;
2098}
2099
2100/* will add 3945 channel switch cmd handling later */
bb8c093b 2101int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
b481de9c
ZY		 2102{
2103 return 0;
2104}
2105
2106/**
2107 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
2108 *
2109 * -- reset periodic timer
2110 * -- see if temp has changed enough to warrant re-calibration ... if so:
2111 * -- correct coeffs for temp (can reset temp timer)
2112 * -- save this temp as "last",
2113 * -- send new set of gain settings to NIC
2114 * NOTE: This should continue working, even when we're not associated,
2115 * so we can keep our internal table of scan powers current. */
bb8c093b 2116void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
b481de9c
ZY		 2117{
2118 /* This will kick in the "brute force"
bb8c093b 2119 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2120 if (!is_temp_calib_needed(priv))
2121 goto reschedule;
2122
2123 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2124 * This is based *only* on current temperature,
2125 * ignoring any previous power measurements */
bb8c093b 2126 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2127
2128 reschedule:
2129 queue_delayed_work(priv->workqueue,
2130 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2131}
2132
416e1438 2133static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2134{
bb8c093b 2135 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
b481de9c
ZY		 2136 thermal_periodic.work);
2137
2138 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2139 return;
2140
2141 mutex_lock(&priv->mutex);
2142 iwl3945_reg_txpower_periodic(priv);
2143 mutex_unlock(&priv->mutex);
2144}
2145
2146/**
bb8c093b 2147 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2148 * for the channel.
2149 *
2150 * This function is used when initializing channel-info structs.
2151 *
2152 * NOTE: These channel groups do *NOT* match the bands above!
2153 * These channel groups are based on factory-tested channels;
2154 * on A-band, EEPROM's "group frequency" entries represent the top
2155 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2156 */
bb8c093b
CH		 2157static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
2158 const struct iwl3945_channel_info *ch_info)
b481de9c 2159{
bb8c093b 2160 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
b481de9c
ZY		 2161 u8 group;
2162 u16 group_index = 0; /* based on factory calib frequencies */
2163 u8 grp_channel;
2164
2165 /* Find the group index for the channel ... don't use index 1(?) */
2166 if (is_channel_a_band(ch_info)) {
2167 for (group = 1; group < 5; group++) {
2168 grp_channel = ch_grp[group].group_channel;
2169 if (ch_info->channel <= grp_channel) {
2170 group_index = group;
2171 break;
2172 }
2173 }
2174 /* group 4 has a few channels *above* its factory cal freq */
2175 if (group == 5)
2176 group_index = 4;
2177 } else
2178 group_index = 0; /* 2.4 GHz, group 0 */
2179
2180 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2181 group_index);
2182 return group_index;
2183}
2184
2185/**
bb8c093b 2186 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2187 *
2188 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2189 * into radio/DSP gain settings table for requested power.
2190 */
bb8c093b 2191static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
b481de9c
ZY		 2192 s8 requested_power,
2193 s32 setting_index, s32 *new_index)
2194{
bb8c093b 2195 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 2196 s32 index0, index1;
2197 s32 power = 2 * requested_power;
2198 s32 i;
bb8c093b 2199 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2200 s32 gains0, gains1;
2201 s32 res;
2202 s32 denominator;
2203
2204 chnl_grp = &priv->eeprom.groups[setting_index];
2205 samples = chnl_grp->samples;
2206 for (i = 0; i < 5; i++) {
2207 if (power == samples[i].power) {
2208 *new_index = samples[i].gain_index;
2209 return 0;
2210 }
2211 }
2212
2213 if (power > samples[1].power) {
2214 index0 = 0;
2215 index1 = 1;
2216 } else if (power > samples[2].power) {
2217 index0 = 1;
2218 index1 = 2;
2219 } else if (power > samples[3].power) {
2220 index0 = 2;
2221 index1 = 3;
2222 } else {
2223 index0 = 3;
2224 index1 = 4;
2225 }
2226
2227 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2228 if (denominator == 0)
2229 return -EINVAL;
2230 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2231 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2232 res = gains0 + (gains1 - gains0) *
2233 ((s32) power - (s32) samples[index0].power) / denominator +
2234 (1 << 18);
2235 *new_index = res >> 19;
2236 return 0;
2237}
2238
bb8c093b 2239static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
b481de9c
ZY		 2240{
2241 u32 i;
2242 s32 rate_index;
bb8c093b 2243 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2244
2245 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2246
2247 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2248 s8 *clip_pwrs; /* table of power levels for each rate */
2249 s8 satur_pwr; /* saturation power for each chnl group */
2250 group = &priv->eeprom.groups[i];
2251
2252 /* sanity check on factory saturation power value */
2253 if (group->saturation_power < 40) {
2254 IWL_WARNING("Error: saturation power is %d, "
2255 "less than minimum expected 40\n",
2256 group->saturation_power);
2257 return;
2258 }
2259
2260 /*
2261 * Derive requested power levels for each rate, based on
2262 * hardware capabilities (saturation power for band).
2263 * Basic value is 3dB down from saturation, with further
2264 * power reductions for highest 3 data rates. These
2265 * backoffs provide headroom for high rate modulation
2266 * power peaks, without too much distortion (clipping).
2267 */
2268 /* we'll fill in this array with h/w max power levels */
2269 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
2270
2271 /* divide factory saturation power by 2 to find -3dB level */
2272 satur_pwr = (s8) (group->saturation_power >> 1);
2273
2274 /* fill in channel group's nominal powers for each rate */
2275 for (rate_index = 0;
2276 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2277 switch (rate_index) {
14577f23 2278 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2279 if (i == 0) /* B/G */
2280 *clip_pwrs = satur_pwr;
2281 else /* A */
2282 *clip_pwrs = satur_pwr - 5;
2283 break;
14577f23 2284 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2285 if (i == 0)
2286 *clip_pwrs = satur_pwr - 7;
2287 else
2288 *clip_pwrs = satur_pwr - 10;
2289 break;
14577f23 2290 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2291 if (i == 0)
2292 *clip_pwrs = satur_pwr - 9;
2293 else
2294 *clip_pwrs = satur_pwr - 12;
2295 break;
2296 default:
2297 *clip_pwrs = satur_pwr;
2298 break;
2299 }
2300 }
2301 }
2302}
2303
2304/**
2305 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2306 *
2307 * Second pass (during init) to set up priv->channel_info
2308 *
2309 * Set up Tx-power settings in our channel info database for each VALID
2310 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2311 * and current temperature.
2312 *
2313 * Since this is based on current temperature (at init time), these values may
2314 * not be valid for very long, but it gives us a starting/default point,
2315 * and allows us to active (i.e. using Tx) scan.
2316 *
2317 * This does *not* write values to NIC, just sets up our internal table.
2318 */
bb8c093b 2319int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
b481de9c 2320{
bb8c093b
CH		 2321 struct iwl3945_channel_info *ch_info = NULL;
2322 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2323 int delta_index;
2324 u8 rate_index;
2325 u8 scan_tbl_index;
2326 const s8 *clip_pwrs; /* array of power levels for each rate */
2327 u8 gain, dsp_atten;
2328 s8 power;
2329 u8 pwr_index, base_pwr_index, a_band;
2330 u8 i;
2331 int temperature;
2332
2333 /* save temperature reference,
2334 * so we can determine next time to calibrate */
bb8c093b 2335 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2336 priv->last_temperature = temperature;
2337
bb8c093b 2338 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2339
2340 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2341 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2342 i++, ch_info++) {
2343 a_band = is_channel_a_band(ch_info);
2344 if (!is_channel_valid(ch_info))
2345 continue;
2346
2347 /* find this channel's channel group (*not* "band") index */
2348 ch_info->group_index =
bb8c093b 2349 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2350
2351 /* Get this chnlgrp's rate->max/clip-powers table */
2352 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2353
2354 /* calculate power index *adjustment* value according to
2355 * diff between current temperature and factory temperature */
bb8c093b 2356 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 2357 priv->eeprom.groups[ch_info->group_index].
2358 temperature);
2359
2360 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2361 ch_info->channel, delta_index, temperature +
2362 IWL_TEMP_CONVERT);
2363
2364 /* set tx power value for all OFDM rates */
2365 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2366 rate_index++) {
2367 s32 power_idx;
2368 int rc;
2369
2370 /* use channel group's clip-power table,
2371 * but don't exceed channel's max power */
2372 s8 pwr = min(ch_info->max_power_avg,
2373 clip_pwrs[rate_index]);
2374
2375 pwr_info = &ch_info->power_info[rate_index];
2376
2377 /* get base (i.e. at factory-measured temperature)
2378 * power table index for this rate's power */
bb8c093b 2379 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2380 ch_info->group_index,
2381 &power_idx);
2382 if (rc) {
2383 IWL_ERROR("Invalid power index\n");
2384 return rc;
2385 }
2386 pwr_info->base_power_index = (u8) power_idx;
2387
2388 /* temperature compensate */
2389 power_idx += delta_index;
2390
2391 /* stay within range of gain table */
bb8c093b 2392 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2393
bb8c093b 2394 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2395 pwr_info->requested_power = pwr;
2396 pwr_info->power_table_index = (u8) power_idx;
2397 pwr_info->tpc.tx_gain =
2398 power_gain_table[a_band][power_idx].tx_gain;
2399 pwr_info->tpc.dsp_atten =
2400 power_gain_table[a_band][power_idx].dsp_atten;
2401 }
2402
2403 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2404 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2405 power = pwr_info->requested_power +
2406 IWL_CCK_FROM_OFDM_POWER_DIFF;
2407 pwr_index = pwr_info->power_table_index +
2408 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2409 base_pwr_index = pwr_info->base_power_index +
2410 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2411
2412 /* stay within table range */
bb8c093b 2413 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2414 gain = power_gain_table[a_band][pwr_index].tx_gain;
2415 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2416
bb8c093b 2417 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2418 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2419 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2420 for (rate_index = 0;
2421 rate_index < IWL_CCK_RATES; rate_index++) {
2422 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2423 pwr_info->requested_power = power;
2424 pwr_info->power_table_index = pwr_index;
2425 pwr_info->base_power_index = base_pwr_index;
2426 pwr_info->tpc.tx_gain = gain;
2427 pwr_info->tpc.dsp_atten = dsp_atten;
2428 }
2429
2430 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2431 for (scan_tbl_index = 0;
2432 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2433 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2434 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2435 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2436 actual_index, clip_pwrs, ch_info, a_band);
2437 }
2438 }
2439
2440 return 0;
2441}
2442
bb8c093b 2443int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 2444{
2445 int rc;
2446 unsigned long flags;
2447
2448 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2449 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2450 if (rc) {
2451 spin_unlock_irqrestore(&priv->lock, flags);
2452 return rc;
2453 }
2454
bb8c093b
CH		 2455 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2456 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
b481de9c
ZY		 2457 if (rc < 0)
2458 IWL_ERROR("Can't stop Rx DMA.\n");
2459
bb8c093b 2460 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2461 spin_unlock_irqrestore(&priv->lock, flags);
2462
2463 return 0;
2464}
2465
bb8c093b 2466int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2467{
2468 int rc;
2469 unsigned long flags;
2470 int txq_id = txq->q.id;
2471
bb8c093b 2472 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2473
2474 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2475
2476 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2477 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2478 if (rc) {
2479 spin_unlock_irqrestore(&priv->lock, flags);
2480 return rc;
2481 }
bb8c093b
CH		 2482 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2483 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
b481de9c 2484
bb8c093b 2485 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
b481de9c
ZY		 2486 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2487 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2488 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2489 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2490 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
bb8c093b 2491 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2492
2493 /* fake read to flush all prev. writes */
bb8c093b 2494 iwl3945_read32(priv, FH_TSSR_CBB_BASE);
b481de9c
ZY		 2495 spin_unlock_irqrestore(&priv->lock, flags);
2496
2497 return 0;
2498}
2499
bb8c093b 2500int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
b481de9c 2501{
bb8c093b 2502 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2503
2504 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2505}
2506
2507/**
2508 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2509 */
bb8c093b 2510int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
b481de9c 2511{
14577f23 2512 int rc, i, index, prev_index;
bb8c093b 2513 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2514 .reserved = {0, 0, 0},
2515 };
bb8c093b 2516 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2517
bb8c093b
CH		 2518 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2519 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2520
2521 table[index].rate_n_flags =
bb8c093b 2522 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2523 table[index].try_cnt = priv->retry_rate;
bb8c093b
CH		 2524 prev_index = iwl3945_get_prev_ieee_rate(i);
2525 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2526 }
2527
8318d78a
JB		 2528 switch (priv->band) {
2529 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2530 IWL_DEBUG_RATE("Select A mode rate scale\n");
2531 /* If one of the following CCK rates is used,
2532 * have it fall back to the 6M OFDM rate */
14577f23 2533 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
bb8c093b 2534 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2535
2536 /* Don't fall back to CCK rates */
14577f23 2537 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2538
2539 /* Don't drop out of OFDM rates */
14577f23 2540 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2541 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2542 break;
2543
8318d78a
JB		 2544 case IEEE80211_BAND_2GHZ:
2545 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2546 /* If an OFDM rate is used, have it fall back to the
2547 * 1M CCK rates */
14577f23 2548 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
bb8c093b 2549 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
b481de9c
ZY		 2550
2551 /* CCK shouldn't fall back to OFDM... */
14577f23 2552 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
b481de9c
ZY		 2553 break;
2554
2555 default:
8318d78a 2556 WARN_ON(1);
b481de9c
ZY		 2557 break;
2558 }
2559
2560 /* Update the rate scaling for control frame Tx */
2561 rate_cmd.table_id = 0;
bb8c093b 2562 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2563 &rate_cmd);
2564 if (rc)
2565 return rc;
2566
2567 /* Update the rate scaling for data frame Tx */
2568 rate_cmd.table_id = 1;
bb8c093b 2569 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2570 &rate_cmd);
2571}
2572
796083cb 2573/* Called when initializing driver */
bb8c093b 2574int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 2575{
2576 memset((void *)&priv->hw_setting, 0,
bb8c093b 2577 sizeof(struct iwl3945_driver_hw_info));
b481de9c
ZY		 2578
2579 priv->hw_setting.shared_virt =
2580 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2581 sizeof(struct iwl3945_shared),
b481de9c
ZY		 2582 &priv->hw_setting.shared_phys);
2583
2584 if (!priv->hw_setting.shared_virt) {
2585 IWL_ERROR("failed to allocate pci memory\n");
2586 mutex_unlock(&priv->mutex);
2587 return -ENOMEM;
2588 }
2589
9ee1ba47
RR		 2590 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2591 priv->hw_setting.max_pkt_size = 2342;
bb8c093b 2592 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
b481de9c
ZY		 2593 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2594 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
b481de9c
ZY		 2595 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2596 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822
TW		 2597
2598 priv->hw_setting.tx_ant_num = 2;
b481de9c
ZY		 2599 return 0;
2600}
2601
bb8c093b
CH		 2602unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2603 struct iwl3945_frame *frame, u8 rate)
b481de9c 2604{
bb8c093b 2605 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2606 unsigned int frame_size;
2607
bb8c093b 2608 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2609 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2610
a4062b8f 2611 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 2612 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2613
bb8c093b 2614 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2615 tx_beacon_cmd->frame,
bb8c093b 2616 iwl3945_broadcast_addr,
b481de9c
ZY		 2617 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2618
2619 BUG_ON(frame_size > MAX_MPDU_SIZE);
2620 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2621
2622 tx_beacon_cmd->tx.rate = rate;
2623 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2624 TX_CMD_FLG_TSF_MSK);
2625
14577f23
MA		 2626 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2627 tx_beacon_cmd->tx.supp_rates[0] =
2628 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2629
b481de9c 2630 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2631 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2632
bb8c093b 2633 return (sizeof(struct iwl3945_tx_beacon_cmd) + frame_size);
b481de9c
ZY		 2634}
2635
bb8c093b 2636void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
b481de9c 2637{
91c066f2 2638 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2639 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2640}
2641
bb8c093b 2642void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2643{
2644 INIT_DELAYED_WORK(&priv->thermal_periodic,
2645 iwl3945_bg_reg_txpower_periodic);
2646}
2647
bb8c093b 2648void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2649{
2650 cancel_delayed_work(&priv->thermal_periodic);
2651}
2652
82b9a121
TW		 2653static struct iwl_3945_cfg iwl3945_bg_cfg = {
2654 .name = "3945BG",
4bf775cd 2655 .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
82b9a121
TW		 2656 .sku = IWL_SKU_G,
2657};
2658
2659static struct iwl_3945_cfg iwl3945_abg_cfg = {
2660 .name = "3945ABG",
4bf775cd 2661 .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
82b9a121
TW		 2662 .sku = IWL_SKU_A|IWL_SKU_G,
2663};
2664
bb8c093b 2665struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2666 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2667 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2668 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2669 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2670 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2671 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2672 {0}
2673};
2674
bb8c093b 2675MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux kernel - Deliverables
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