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iwlwifi: remove device type checking for tx power in debugfs
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
d43c36dc 33#include <linux/sched.h>
b481de9c
ZY		 34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47
ZY		 39#include <asm/unaligned.h>
40#include <net/mac80211.h>
b481de9c 41
dbb6654c 42#include "iwl-fh.h"
bddadf86 43#include "iwl-3945-fh.h"
600c0e11 44#include "iwl-commands.h"
17f841cd 45#include "iwl-sta.h"
b481de9c 46#include "iwl-3945.h"
e6148917 47#include "iwl-eeprom.h"
5747d47f 48#include "iwl-core.h"
4a6547c7 49#include "iwl-helpers.h"
e932a609
JB		 50#include "iwl-led.h"
51#include "iwl-3945-led.h"
17f36fc6 52#include "iwl-3945-debugfs.h"
b481de9c
ZY		 53
54#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
55 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
56 IWL_RATE_##r##M_IEEE, \
57 IWL_RATE_##ip##M_INDEX, \
58 IWL_RATE_##in##M_INDEX, \
59 IWL_RATE_##rp##M_INDEX, \
60 IWL_RATE_##rn##M_INDEX, \
61 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 62 IWL_RATE_##np##M_INDEX, \
63 IWL_RATE_##r##M_INDEX_TABLE, \
64 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 65
66/*
67 * Parameter order:
68 * rate, prev rate, next rate, prev tgg rate, next tgg rate
69 *
70 * If there isn't a valid next or previous rate then INV is used which
71 * maps to IWL_RATE_INVALID
72 *
73 */
d9829a67 74const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 75 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
76 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
77 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
78 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 79 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
80 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
81 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
82 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
83 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
84 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
85 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
86 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 87};
88
bb8c093b 89/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 90#define IWL_EVT_DISABLE (0)
91#define IWL_EVT_DISABLE_SIZE (1532/32)
92
93/**
bb8c093b 94 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 95 *
96 * Disable an event by writing "1"s into "disable"
97 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
98 * Default values of 0 enable uCode events to be logged.
99 * Use for only special debugging. This function is just a placeholder as-is,
100 * you'll need to provide the special bits! ...
101 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 102void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 103{
b481de9c
ZY		 104 int i;
105 u32 base; /* SRAM address of event log header */
106 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
107 u32 array_size; /* # of u32 entries in array */
108 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
109 0x00000000, /* 31 - 0 Event id numbers */
110 0x00000000, /* 63 - 32 */
111 0x00000000, /* 95 - 64 */
112 0x00000000, /* 127 - 96 */
113 0x00000000, /* 159 - 128 */
114 0x00000000, /* 191 - 160 */
115 0x00000000, /* 223 - 192 */
116 0x00000000, /* 255 - 224 */
117 0x00000000, /* 287 - 256 */
118 0x00000000, /* 319 - 288 */
119 0x00000000, /* 351 - 320 */
120 0x00000000, /* 383 - 352 */
121 0x00000000, /* 415 - 384 */
122 0x00000000, /* 447 - 416 */
123 0x00000000, /* 479 - 448 */
124 0x00000000, /* 511 - 480 */
125 0x00000000, /* 543 - 512 */
126 0x00000000, /* 575 - 544 */
127 0x00000000, /* 607 - 576 */
128 0x00000000, /* 639 - 608 */
129 0x00000000, /* 671 - 640 */
130 0x00000000, /* 703 - 672 */
131 0x00000000, /* 735 - 704 */
132 0x00000000, /* 767 - 736 */
133 0x00000000, /* 799 - 768 */
134 0x00000000, /* 831 - 800 */
135 0x00000000, /* 863 - 832 */
136 0x00000000, /* 895 - 864 */
137 0x00000000, /* 927 - 896 */
138 0x00000000, /* 959 - 928 */
139 0x00000000, /* 991 - 960 */
140 0x00000000, /* 1023 - 992 */
141 0x00000000, /* 1055 - 1024 */
142 0x00000000, /* 1087 - 1056 */
143 0x00000000, /* 1119 - 1088 */
144 0x00000000, /* 1151 - 1120 */
145 0x00000000, /* 1183 - 1152 */
146 0x00000000, /* 1215 - 1184 */
147 0x00000000, /* 1247 - 1216 */
148 0x00000000, /* 1279 - 1248 */
149 0x00000000, /* 1311 - 1280 */
150 0x00000000, /* 1343 - 1312 */
151 0x00000000, /* 1375 - 1344 */
152 0x00000000, /* 1407 - 1376 */
153 0x00000000, /* 1439 - 1408 */
154 0x00000000, /* 1471 - 1440 */
155 0x00000000, /* 1503 - 1472 */
156 };
157
158 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 159 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 160 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 161 return;
162 }
163
5d49f498
AK		 164 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
165 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 166
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 168 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 169 disable_ptr);
b481de9c 170 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 171 iwl_write_targ_mem(priv,
af7cca2a
TW		 172 disable_ptr + (i * sizeof(u32)),
173 evt_disable[i]);
b481de9c 174
b481de9c 175 } else {
e1623446
TW		 176 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
177 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
178 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 179 disable_ptr, array_size);
180 }
181
182}
183
17744ff6
TW		 184static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
185{
186 int idx;
187
1d79e53c 188 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
17744ff6
TW		 189 if (iwl3945_rates[idx].plcp == plcp)
190 return idx;
191 return -1;
192}
193
d08853a3 194#ifdef CONFIG_IWLWIFI_DEBUG
04569cbe 195#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
91c066f2
TW		 196
197static const char *iwl3945_get_tx_fail_reason(u32 status)
198{
199 switch (status & TX_STATUS_MSK) {
04569cbe 200 case TX_3945_STATUS_SUCCESS:
91c066f2
TW		 201 return "SUCCESS";
202 TX_STATUS_ENTRY(SHORT_LIMIT);
203 TX_STATUS_ENTRY(LONG_LIMIT);
204 TX_STATUS_ENTRY(FIFO_UNDERRUN);
205 TX_STATUS_ENTRY(MGMNT_ABORT);
206 TX_STATUS_ENTRY(NEXT_FRAG);
207 TX_STATUS_ENTRY(LIFE_EXPIRE);
208 TX_STATUS_ENTRY(DEST_PS);
209 TX_STATUS_ENTRY(ABORTED);
210 TX_STATUS_ENTRY(BT_RETRY);
211 TX_STATUS_ENTRY(STA_INVALID);
212 TX_STATUS_ENTRY(FRAG_DROPPED);
213 TX_STATUS_ENTRY(TID_DISABLE);
214 TX_STATUS_ENTRY(FRAME_FLUSHED);
215 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
216 TX_STATUS_ENTRY(TX_LOCKED);
217 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
218 }
219
220 return "UNKNOWN";
221}
222#else
223static inline const char *iwl3945_get_tx_fail_reason(u32 status)
224{
225 return "";
226}
227#endif
228
e6a9854b
JB		 229/*
230 * get ieee prev rate from rate scale table.
231 * for A and B mode we need to overright prev
232 * value
233 */
4a8a4322 234int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 235{
236 int next_rate = iwl3945_get_prev_ieee_rate(rate);
237
238 switch (priv->band) {
239 case IEEE80211_BAND_5GHZ:
240 if (rate == IWL_RATE_12M_INDEX)
241 next_rate = IWL_RATE_9M_INDEX;
242 else if (rate == IWL_RATE_6M_INDEX)
243 next_rate = IWL_RATE_6M_INDEX;
244 break;
7262796a 245 case IEEE80211_BAND_2GHZ:
ee525d13 246 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 247 iwl_is_associated(priv)) {
7262796a
AM		 248 if (rate == IWL_RATE_11M_INDEX)
249 next_rate = IWL_RATE_5M_INDEX;
250 }
e6a9854b 251 break;
7262796a 252
e6a9854b
JB		 253 default:
254 break;
255 }
256
257 return next_rate;
258}
259
91c066f2
TW		 260
261/**
262 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
263 *
264 * When FW advances 'R' index, all entries between old and new 'R' index
265 * need to be reclaimed. As result, some free space forms. If there is
266 * enough free space (> low mark), wake the stack that feeds us.
267 */
4a8a4322 268static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 269 int txq_id, int index)
270{
188cf6c7 271 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 272 struct iwl_queue *q = &txq->q;
dbb6654c 273 struct iwl_tx_info *tx_info;
91c066f2
TW		 274
275 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
276
277 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
278 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
279
280 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 281 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 282 tx_info->skb[0] = NULL;
7aaa1d79 283 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 284 }
285
d20b3c65 286 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 287 (txq_id != IWL_CMD_QUEUE_NUM) &&
288 priv->mac80211_registered)
e4e72fb4 289 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 290}
291
292/**
293 * iwl3945_rx_reply_tx - Handle Tx response
294 */
4a8a4322 295static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
17f36fc6 296 struct iwl_rx_mem_buffer *rxb)
91c066f2 297{
2f301227 298 struct iwl_rx_packet *pkt = rxb_addr(rxb);
91c066f2
TW		 299 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
300 int txq_id = SEQ_TO_QUEUE(sequence);
301 int index = SEQ_TO_INDEX(sequence);
188cf6c7 302 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 303 struct ieee80211_tx_info *info;
91c066f2
TW		 304 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
305 u32 status = le32_to_cpu(tx_resp->status);
306 int rate_idx;
74221d07 307 int fail;
91c066f2 308
625a381a 309 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 310 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 311 "is out of range [0-%d] %d %d\n", txq_id,
312 index, txq->q.n_bd, txq->q.write_ptr,
313 txq->q.read_ptr);
314 return;
315 }
316
e039fa4a 317 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 318 ieee80211_tx_info_clear_status(info);
319
320 /* Fill the MRR chain with some info about on-chip retransmissions */
321 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
322 if (info->band == IEEE80211_BAND_5GHZ)
323 rate_idx -= IWL_FIRST_OFDM_RATE;
324
325 fail = tx_resp->failure_frame;
74221d07
AM		 326
327 info->status.rates[0].idx = rate_idx;
328 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 329
91c066f2 330 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 331 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
332 IEEE80211_TX_STAT_ACK : 0;
91c066f2 333
e1623446 334 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 335 txq_id, iwl3945_get_tx_fail_reason(status), status,
336 tx_resp->rate, tx_resp->failure_frame);
337
e1623446 338 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 339 iwl3945_tx_queue_reclaim(priv, txq_id, index);
340
341 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 342 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 343}
344
345
346
b481de9c
ZY		 347/*****************************************************************************
348 *
349 * Intel PRO/Wireless 3945ABG/BG Network Connection
350 *
351 * RX handler implementations
352 *
b481de9c 353 *****************************************************************************/
17f36fc6
AK		 354#ifdef CONFIG_IWLWIFI_DEBUG
355/*
356 * based on the assumption of all statistics counter are in DWORD
357 * FIXME: This function is for debugging, do not deal with
358 * the case of counters roll-over.
359 */
360static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
361 __le32 *stats)
362{
363 int i;
364 __le32 *prev_stats;
365 u32 *accum_stats;
366 u32 *delta, *max_delta;
367
368 prev_stats = (__le32 *)&priv->_3945.statistics;
369 accum_stats = (u32 *)&priv->_3945.accum_statistics;
370 delta = (u32 *)&priv->_3945.delta_statistics;
371 max_delta = (u32 *)&priv->_3945.max_delta;
372
373 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
374 i += sizeof(__le32), stats++, prev_stats++, delta++,
375 max_delta++, accum_stats++) {
376 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
377 *delta = (le32_to_cpu(*stats) -
378 le32_to_cpu(*prev_stats));
379 *accum_stats += *delta;
380 if (*delta > *max_delta)
381 *max_delta = *delta;
382 }
383 }
384
385 /* reset accumulative statistics for "no-counter" type statistics */
386 priv->_3945.accum_statistics.general.temperature =
387 priv->_3945.statistics.general.temperature;
388 priv->_3945.accum_statistics.general.ttl_timestamp =
389 priv->_3945.statistics.general.ttl_timestamp;
390}
391#endif
b481de9c 392
396887a2
DH		 393void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
394 struct iwl_rx_mem_buffer *rxb)
b481de9c 395{
2f301227 396 struct iwl_rx_packet *pkt = rxb_addr(rxb);
17f36fc6 397
e1623446 398 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 399 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 400 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
17f36fc6
AK		 401#ifdef CONFIG_IWLWIFI_DEBUG
402 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
403#endif
b481de9c 404
ee525d13 405 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
b481de9c
ZY		 406}
407
17f36fc6
AK		 408void iwl3945_reply_statistics(struct iwl_priv *priv,
409 struct iwl_rx_mem_buffer *rxb)
410{
411 struct iwl_rx_packet *pkt = rxb_addr(rxb);
412 __le32 *flag = (__le32 *)&pkt->u.raw;
413
414 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
415#ifdef CONFIG_IWLWIFI_DEBUG
416 memset(&priv->_3945.accum_statistics, 0,
417 sizeof(struct iwl3945_notif_statistics));
418 memset(&priv->_3945.delta_statistics, 0,
419 sizeof(struct iwl3945_notif_statistics));
420 memset(&priv->_3945.max_delta, 0,
421 sizeof(struct iwl3945_notif_statistics));
422#endif
423 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
424 }
425 iwl3945_hw_rx_statistics(priv, rxb);
426}
427
428
17744ff6
TW		 429/******************************************************************************
430 *
431 * Misc. internal state and helper functions
432 *
433 ******************************************************************************/
d08853a3 434#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 435
436/**
437 * iwl3945_report_frame - dump frame to syslog during debug sessions
438 *
439 * You may hack this function to show different aspects of received frames,
440 * including selective frame dumps.
441 * group100 parameter selects whether to show 1 out of 100 good frames.
442 */
d08853a3 443static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 444 struct iwl_rx_packet *pkt,
17744ff6
TW		 445 struct ieee80211_hdr *header, int group100)
446{
447 u32 to_us;
448 u32 print_summary = 0;
449 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
450 u32 hundred = 0;
451 u32 dataframe = 0;
fd7c8a40 452 __le16 fc;
17744ff6
TW		 453 u16 seq_ctl;
454 u16 channel;
455 u16 phy_flags;
456 u16 length;
457 u16 status;
458 u16 bcn_tmr;
459 u32 tsf_low;
460 u64 tsf;
461 u8 rssi;
462 u8 agc;
463 u16 sig_avg;
464 u16 noise_diff;
465 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
466 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
467 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
468 u8 *data = IWL_RX_DATA(pkt);
469
470 /* MAC header */
fd7c8a40 471 fc = header->frame_control;
17744ff6
TW		 472 seq_ctl = le16_to_cpu(header->seq_ctrl);
473
474 /* metadata */
475 channel = le16_to_cpu(rx_hdr->channel);
476 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
477 length = le16_to_cpu(rx_hdr->len);
478
479 /* end-of-frame status and timestamp */
480 status = le32_to_cpu(rx_end->status);
481 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
482 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
483 tsf = le64_to_cpu(rx_end->timestamp);
484
485 /* signal statistics */
486 rssi = rx_stats->rssi;
487 agc = rx_stats->agc;
488 sig_avg = le16_to_cpu(rx_stats->sig_avg);
489 noise_diff = le16_to_cpu(rx_stats->noise_diff);
490
491 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
492
493 /* if data frame is to us and all is good,
494 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 495 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
496 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 497 dataframe = 1;
498 if (!group100)
499 print_summary = 1; /* print each frame */
500 else if (priv->framecnt_to_us < 100) {
501 priv->framecnt_to_us++;
502 print_summary = 0;
503 } else {
504 priv->framecnt_to_us = 0;
505 print_summary = 1;
506 hundred = 1;
507 }
508 } else {
509 /* print summary for all other frames */
510 print_summary = 1;
511 }
512
513 if (print_summary) {
514 char *title;
0ff1cca0 515 int rate;
17744ff6
TW		 516
517 if (hundred)
518 title = "100Frames";
fd7c8a40 519 else if (ieee80211_has_retry(fc))
17744ff6 520 title = "Retry";
fd7c8a40 521 else if (ieee80211_is_assoc_resp(fc))
17744ff6 522 title = "AscRsp";
fd7c8a40 523 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 524 title = "RasRsp";
fd7c8a40 525 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 526 title = "PrbRsp";
527 print_dump = 1; /* dump frame contents */
528 } else if (ieee80211_is_beacon(fc)) {
529 title = "Beacon";
530 print_dump = 1; /* dump frame contents */
531 } else if (ieee80211_is_atim(fc))
532 title = "ATIM";
533 else if (ieee80211_is_auth(fc))
534 title = "Auth";
535 else if (ieee80211_is_deauth(fc))
536 title = "DeAuth";
537 else if (ieee80211_is_disassoc(fc))
538 title = "DisAssoc";
539 else
540 title = "Frame";
541
542 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
543 if (rate == -1)
544 rate = 0;
545 else
546 rate = iwl3945_rates[rate].ieee / 2;
547
548 /* print frame summary.
549 * MAC addresses show just the last byte (for brevity),
550 * but you can hack it to show more, if you'd like to. */
551 if (dataframe)
e1623446 552 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
91dd6c27 553 "len=%u, rssi=%d, chnl=%d, rate=%d,\n",
fd7c8a40 554 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 555 length, rssi, channel, rate);
556 else {
557 /* src/dst addresses assume managed mode */
e1623446 558 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 559 "src=0x%02x, rssi=%u, tim=%lu usec, "
560 "phy=0x%02x, chnl=%d\n",
fd7c8a40 561 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 562 header->addr3[5], rssi,
563 tsf_low - priv->scan_start_tsf,
564 phy_flags, channel);
565 }
566 }
567 if (print_dump)
3d816c77 568 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 569}
d08853a3
SO		 570
571static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
572 struct iwl_rx_packet *pkt,
573 struct ieee80211_hdr *header, int group100)
574{
3d816c77 575 if (iwl_get_debug_level(priv) & IWL_DL_RX)
d08853a3
SO		 576 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
577}
578
17744ff6 579#else
4a8a4322 580static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 581 struct iwl_rx_packet *pkt,
17744ff6
TW		 582 struct ieee80211_hdr *header, int group100)
583{
584}
585#endif
586
4bd9b4f3 587/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 588static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 589 struct ieee80211_hdr *header)
590{
591 /* Filter incoming packets to determine if they are targeted toward
592 * this network, discarding packets coming from ourselves */
593 switch (priv->iw_mode) {
05c914fe 594 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 595 /* packets to our IBSS update information */
596 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 597 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 598 /* packets to our IBSS update information */
599 return !compare_ether_addr(header->addr2, priv->bssid);
600 default:
601 return 1;
602 }
603}
17744ff6 604
4a8a4322 605static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 606 struct iwl_rx_mem_buffer *rxb,
12342c47 607 struct ieee80211_rx_status *stats)
b481de9c 608{
2f301227 609 struct iwl_rx_packet *pkt = rxb_addr(rxb);
4bd9b4f3 610 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 611 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
612 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
2f301227
ZY		 613 u16 len = le16_to_cpu(rx_hdr->len);
614 struct sk_buff *skb;
29b1b268 615 __le16 fc = hdr->frame_control;
b481de9c
ZY		 616
617 /* We received data from the HW, so stop the watchdog */
2f301227
ZY		 618 if (unlikely(len + IWL39_RX_FRAME_SIZE >
619 PAGE_SIZE << priv->hw_params.rx_page_order)) {
e1623446 620 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 621 return;
622 }
623
624 /* We only process data packets if the interface is open */
625 if (unlikely(!priv->is_open)) {
e1623446
TW		 626 IWL_DEBUG_DROP_LIMIT(priv,
627 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 628 return;
629 }
b481de9c 630
ecdf94b8 631 skb = dev_alloc_skb(128);
2f301227 632 if (!skb) {
ecdf94b8 633 IWL_ERR(priv, "dev_alloc_skb failed\n");
2f301227
ZY		 634 return;
635 }
b481de9c 636
9c74d9fb 637 if (!iwl3945_mod_params.sw_crypto)
8ccde88a 638 iwl_set_decrypted_flag(priv,
2f301227 639 (struct ieee80211_hdr *)rxb_addr(rxb),
b481de9c
ZY		 640 le32_to_cpu(rx_end->status), stats);
641
2f301227
ZY		 642 skb_add_rx_frag(skb, 0, rxb->page,
643 (void *)rx_hdr->payload - (void *)pkt, len);
644
29b1b268 645 iwl_update_stats(priv, false, fc, len);
2f301227 646 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
2f301227 647
29b1b268 648 ieee80211_rx(priv->hw, skb);
2f301227
ZY		 649 priv->alloc_rxb_page--;
650 rxb->page = NULL;
b481de9c
ZY		 651}
652
7878a5a4
MA		 653#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
654
4a8a4322 655static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 656 struct iwl_rx_mem_buffer *rxb)
b481de9c 657{
17744ff6
TW		 658 struct ieee80211_hdr *header;
659 struct ieee80211_rx_status rx_status;
2f301227 660 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b
CH		 661 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
662 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
663 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
f875f518
RC		 664 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
665 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
b481de9c 666 u8 network_packet;
17744ff6 667
17744ff6
TW		 668 rx_status.flag = 0;
669 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 670 rx_status.freq =
c0186078 671 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 672 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
673 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
674
675 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 676 if (rx_status.band == IEEE80211_BAND_5GHZ)
677 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 678
9024adf5 679 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 680 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
681
682 /* set the preamble flag if appropriate */
683 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
684 rx_status.flag |= RX_FLAG_SHORTPRE;
685
b481de9c 686 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 687 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
688 rx_stats->phy_count);
b481de9c
ZY		 689 return;
690 }
691
692 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
693 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 694 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 695 return;
696 }
697
56decd3c 698
b481de9c
ZY		 699
700 /* Convert 3945's rssi indicator to dBm */
250bdd21 701 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c 702
ed1b6e99
JB		 703 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
704 rx_status.signal, rx_stats_sig_avg,
705 rx_stats_noise_diff);
b481de9c 706
b481de9c
ZY		 707 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
708
bb8c093b 709 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 710
ed1b6e99 711 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
17744ff6
TW		 712 network_packet ? '*' : ' ',
713 le16_to_cpu(rx_hdr->channel),
566bfe5a 714 rx_status.signal, rx_status.signal,
ed1b6e99 715 rx_status.rate_idx);
b481de9c 716
d08853a3
SO		 717 /* Set "1" to report good data frames in groups of 100 */
718 iwl3945_dbg_report_frame(priv, pkt, header, 1);
20594eb0 719 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 720
721 if (network_packet) {
e99f168c
JB		 722 priv->_3945.last_beacon_time =
723 le32_to_cpu(rx_end->beacon_timestamp);
724 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
725 priv->_3945.last_rx_rssi = rx_status.signal;
b481de9c
ZY		 726 }
727
12e5e22d 728 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 729}
730
7aaa1d79
SO		 731int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
732 struct iwl_tx_queue *txq,
733 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 734{
735 int count;
7aaa1d79 736 struct iwl_queue *q;
59606ffa 737 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 738
739 q = &txq->q;
59606ffa
SO		 740 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
741 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 742
743 if (reset)
744 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 745
746 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 747
748 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 749 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 750 NUM_TFD_CHUNKS);
751 return -EINVAL;
752 }
753
dbb6654c
WT		 754 tfd->tbs[count].addr = cpu_to_le32(addr);
755 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 756
757 count++;
758
759 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
760 TFD_CTL_PAD_SET(pad));
761
762 return 0;
763}
764
765/**
bb8c093b 766 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 767 *
768 * Does NOT advance any indexes
769 */
7aaa1d79 770void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 771{
59606ffa 772 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 773 int index = txq->q.read_ptr;
774 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 775 struct pci_dev *dev = priv->pci_dev;
776 int i;
777 int counter;
778
b481de9c 779 /* sanity check */
dbb6654c 780 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 781 if (counter > NUM_TFD_CHUNKS) {
15b1687c 782 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 783 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 784 return;
b481de9c
ZY		 785 }
786
fd9377ee
RC		 787 /* Unmap tx_cmd */
788 if (counter)
789 pci_unmap_single(dev,
c2acea8e
JB		 790 pci_unmap_addr(&txq->meta[index], mapping),
791 pci_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 792 PCI_DMA_TODEVICE);
793
b481de9c
ZY		 794 /* unmap chunks if any */
795
796 for (i = 1; i < counter; i++) {
dbb6654c
WT		 797 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
798 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 799 if (txq->txb[txq->q.read_ptr].skb[0]) {
800 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
801 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 802 /* Can be called from interrupt context */
803 dev_kfree_skb_any(skb);
fc4b6853 804 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 805 }
806 }
807 }
7aaa1d79 808 return ;
b481de9c
ZY		 809}
810
b481de9c 811/**
bb8c093b 812 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 813 *
814*/
c2acea8e
JB		 815void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
816 struct iwl_device_cmd *cmd,
817 struct ieee80211_tx_info *info,
818 struct ieee80211_hdr *hdr,
819 int sta_id, int tx_id)
b481de9c 820{
e039fa4a 821 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
1d79e53c 822 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
b481de9c
ZY		 823 u16 rate_mask;
824 int rate;
825 u8 rts_retry_limit;
826 u8 data_retry_limit;
827 __le32 tx_flags;
fd7c8a40 828 __le16 fc = hdr->frame_control;
9744c91f 829 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 830
bb8c093b 831 rate = iwl3945_rates[rate_index].plcp;
9744c91f 832 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 833
834 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 835 * in this running context */
b481de9c
ZY		 836 rate_mask = IWL_RATES_MASK;
837
768db982
AK		 838
839 /* Set retry limit on DATA packets and Probe Responses*/
840 if (ieee80211_is_probe_resp(fc))
841 data_retry_limit = 3;
842 else
843 data_retry_limit = IWL_DEFAULT_TX_RETRY;
844 tx_cmd->data_retry_limit = data_retry_limit;
845
b481de9c
ZY		 846 if (tx_id >= IWL_CMD_QUEUE_NUM)
847 rts_retry_limit = 3;
848 else
849 rts_retry_limit = 7;
850
768db982
AK		 851 if (data_retry_limit < rts_retry_limit)
852 rts_retry_limit = data_retry_limit;
853 tx_cmd->rts_retry_limit = rts_retry_limit;
b481de9c 854
fd7c8a40
HH		 855 if (ieee80211_is_mgmt(fc)) {
856 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
857 case cpu_to_le16(IEEE80211_STYPE_AUTH):
858 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
859 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
860 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 861 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
862 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
863 tx_flags |= TX_CMD_FLG_CTS_MSK;
864 }
865 break;
866 default:
867 break;
868 }
869 }
870
9744c91f
AK		 871 tx_cmd->rate = rate;
872 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 873
874 /* OFDM */
9744c91f 875 tx_cmd->supp_rates[0] =
14577f23 876 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 877
878 /* CCK */
9744c91f 879 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 880
e1623446 881 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 882 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
9744c91f
AK		 883 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
884 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
b481de9c
ZY		 885}
886
4a8a4322 887u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 888{
889 unsigned long flags_spin;
c587de0b 890 struct iwl_station_entry *station;
b481de9c
ZY		 891
892 if (sta_id == IWL_INVALID_STATION)
893 return IWL_INVALID_STATION;
894
895 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 896 station = &priv->stations[sta_id];
b481de9c
ZY		 897
898 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
899 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 900 station->sta.mode = STA_CONTROL_MODIFY_MSK;
901
902 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
903
c587de0b 904 iwl_send_add_sta(priv, &station->sta, flags);
e1623446 905 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 906 sta_id, tx_rate);
907 return sta_id;
908}
909
854682ed 910static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 911{
854682ed 912 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 913 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 914 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 915 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
916 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 917
5d49f498 918 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 919 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
920 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 921 }
b481de9c 922 } else {
5d49f498 923 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 924 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
925 ~APMG_PS_CTRL_MSK_PWR_SRC);
926
5d49f498 927 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 928 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
929 }
b481de9c 930
a8b50a0a 931 return 0;
b481de9c
ZY		 932}
933
4a8a4322 934static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 935{
5d49f498 936 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 937 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 938 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
939 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 940 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
941 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
942 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
943 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
944 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
945 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
946 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
947 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 948
949 /* fake read to flush all prev I/O */
5d49f498 950 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 951
b481de9c
ZY		 952 return 0;
953}
954
4a8a4322 955static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 956{
b481de9c
ZY		 957
958 /* bypass mode */
5d49f498 959 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 960
961 /* RA 0 is active */
5d49f498 962 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 963
964 /* all 6 fifo are active */
5d49f498 965 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 966
5d49f498
AK		 967 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
968 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
969 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
970 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 971
5d49f498 972 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
ee525d13 973 priv->_3945.shared_phys);
b481de9c 974
5d49f498 975 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 976 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
977 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
978 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
979 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
980 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
981 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
982 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 983
b481de9c
ZY		 984
985 return 0;
986}
987
988/**
989 * iwl3945_txq_ctx_reset - Reset TX queue context
990 *
991 * Destroys all DMA structures and initialize them again
992 */
4a8a4322 993static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 994{
995 int rc;
996 int txq_id, slots_num;
997
bb8c093b 998 iwl3945_hw_txq_ctx_free(priv);
b481de9c 999
88804e2b
WYG		 1000 /* allocate tx queue structure */
1001 rc = iwl_alloc_txq_mem(priv);
1002 if (rc)
1003 return rc;
1004
b481de9c
ZY		 1005 /* Tx CMD queue */
1006 rc = iwl3945_tx_reset(priv);
1007 if (rc)
1008 goto error;
1009
1010 /* Tx queue(s) */
5905a1aa 1011 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 1012 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1013 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 1014 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1015 txq_id);
b481de9c 1016 if (rc) {
15b1687c 1017 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1018 goto error;
1019 }
1020 }
1021
1022 return rc;
1023
1024 error:
bb8c093b 1025 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1026 return rc;
1027}
1028
fadb3582 1029
f33269b8 1030/*
fadb3582
BC		 1031 * Start up 3945's basic functionality after it has been reset
1032 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
f33269b8
BC		 1033 * NOTE: This does not load uCode nor start the embedded processor
1034 */
01ec616d 1035static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1036{
fadb3582 1037 int ret = iwl_apm_init(priv);
01ec616d 1038
f33269b8
BC		 1039 /* Clear APMG (NIC's internal power management) interrupts */
1040 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1041 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1042
1043 /* Reset radio chip */
1044 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1045 udelay(5);
1046 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1047
01ec616d
KA		 1048 return ret;
1049}
b481de9c 1050
01ec616d
KA		 1051static void iwl3945_nic_config(struct iwl_priv *priv)
1052{
e6148917 1053 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1054 unsigned long flags;
1055 u8 rev_id = 0;
b481de9c 1056
b481de9c
ZY		 1057 spin_lock_irqsave(&priv->lock, flags);
1058
43121432
AK		 1059 /* Determine HW type */
1060 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1061
1062 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1063
b481de9c 1064 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
91dd6c27 1065 IWL_DEBUG_INFO(priv, "RTP type\n");
b481de9c 1066 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1067 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1068 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1069 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1070 } else {
e1623446 1071 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1072 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1073 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1074 }
1075
e6148917 1076 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1077 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1078 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1079 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1080 } else
e1623446 1081 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1082
e6148917 1083 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1084 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1085 eeprom->board_revision);
5d49f498 1086 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1087 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1088 } else {
e1623446 1089 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1090 eeprom->board_revision);
5d49f498 1091 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1092 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1093 }
1094
e6148917 1095 if (eeprom->almgor_m_version <= 1) {
5d49f498 1096 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1097 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1098 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1099 eeprom->almgor_m_version);
b481de9c 1100 } else {
e1623446 1101 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1102 eeprom->almgor_m_version);
5d49f498 1103 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1104 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1105 }
1106 spin_unlock_irqrestore(&priv->lock, flags);
1107
e6148917 1108 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1109 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1110
e6148917 1111 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1112 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1113}
1114
1115int iwl3945_hw_nic_init(struct iwl_priv *priv)
1116{
01ec616d
KA		 1117 int rc;
1118 unsigned long flags;
1119 struct iwl_rx_queue *rxq = &priv->rxq;
1120
1121 spin_lock_irqsave(&priv->lock, flags);
1122 priv->cfg->ops->lib->apm_ops.init(priv);
1123 spin_unlock_irqrestore(&priv->lock, flags);
1124
854682ed 1125 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1126 if (rc)
854682ed
KA		 1127 return rc;
1128
01ec616d 1129 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1130
1131 /* Allocate the RX queue, or reset if it is already allocated */
1132 if (!rxq->bd) {
51af3d3f 1133 rc = iwl_rx_queue_alloc(priv);
b481de9c 1134 if (rc) {
15b1687c 1135 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1136 return -ENOMEM;
1137 }
1138 } else
df833b1d 1139 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1140
bb8c093b 1141 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1142
1143 iwl3945_rx_init(priv, rxq);
1144
b481de9c
ZY		 1145
1146 /* Look at using this instead:
1147 rxq->need_update = 1;
141c43a3 1148 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1149 */
1150
5d49f498 1151 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1152
1153 rc = iwl3945_txq_ctx_reset(priv);
1154 if (rc)
1155 return rc;
1156
1157 set_bit(STATUS_INIT, &priv->status);
1158
1159 return 0;
1160}
1161
1162/**
bb8c093b 1163 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1164 *
1165 * Destroy all TX DMA queues and structures
1166 */
4a8a4322 1167void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1168{
1169 int txq_id;
1170
1171 /* Tx queues */
88804e2b
WYG		 1172 if (priv->txq)
1173 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1174 txq_id++)
1175 if (txq_id == IWL_CMD_QUEUE_NUM)
1176 iwl_cmd_queue_free(priv);
1177 else
1178 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1179
88804e2b
WYG		 1180 /* free tx queue structure */
1181 iwl_free_txq_mem(priv);
b481de9c
ZY		 1182}
1183
4a8a4322 1184void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1185{
bddadf86 1186 int txq_id;
b481de9c
ZY		 1187
1188 /* stop SCD */
5d49f498 1189 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1f80989e 1190 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
b481de9c
ZY		 1191
1192 /* reset TFD queues */
5905a1aa 1193 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1194 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1195 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1196 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1197 1000);
1198 }
1199
bb8c093b 1200 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1201}
1202
b481de9c 1203/**
bb8c093b 1204 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1205 * return index delta into power gain settings table
1206*/
bb8c093b 1207static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1208{
1209 return (new_reading - old_reading) * (-11) / 100;
1210}
1211
1212/**
bb8c093b 1213 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1214 */
bb8c093b 1215static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1216{
3ac7f146 1217 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1218}
1219
4a8a4322 1220int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1221{
5d49f498 1222 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1223}
1224
1225/**
bb8c093b 1226 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1227 * get the current temperature by reading from NIC
1228*/
4a8a4322 1229static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1230{
e6148917 1231 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1232 int temperature;
1233
bb8c093b 1234 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1235
1236 /* driver's okay range is -260 to +25.
1237 * human readable okay range is 0 to +285 */
e1623446 1238 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1239
1240 /* handle insane temp reading */
bb8c093b 1241 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1242 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1243
1244 /* if really really hot(?),
1245 * substitute the 3rd band/group's temp measured at factory */
1246 if (priv->last_temperature > 100)
e6148917 1247 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1248 else /* else use most recent "sane" value from driver */
1249 temperature = priv->last_temperature;
1250 }
1251
1252 return temperature; /* raw, not "human readable" */
1253}
1254
1255/* Adjust Txpower only if temperature variance is greater than threshold.
1256 *
1257 * Both are lower than older versions' 9 degrees */
1258#define IWL_TEMPERATURE_LIMIT_TIMER 6
1259
1260/**
1261 * is_temp_calib_needed - determines if new calibration is needed
1262 *
1263 * records new temperature in tx_mgr->temperature.
1264 * replaces tx_mgr->last_temperature *only* if calib needed
1265 * (assumes caller will actually do the calibration!). */
4a8a4322 1266static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1267{
1268 int temp_diff;
1269
bb8c093b 1270 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1271 temp_diff = priv->temperature - priv->last_temperature;
1272
1273 /* get absolute value */
1274 if (temp_diff < 0) {
e1623446 1275 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1276 temp_diff = -temp_diff;
1277 } else if (temp_diff == 0)
e1623446 1278 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1279 else
e1623446 1280 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1281
1282 /* if we don't need calibration, *don't* update last_temperature */
1283 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1284 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1285 return 0;
1286 }
1287
e1623446 1288 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1289
1290 /* assume that caller will actually do calib ...
1291 * update the "last temperature" value */
1292 priv->last_temperature = priv->temperature;
1293 return 1;
1294}
1295
1296#define IWL_MAX_GAIN_ENTRIES 78
1297#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1298#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1299
1300/* radio and DSP power table, each step is 1/2 dB.
1301 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1302static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1303 {
1304 {251, 127}, /* 2.4 GHz, highest power */
1305 {251, 127},
1306 {251, 127},
1307 {251, 127},
1308 {251, 125},
1309 {251, 110},
1310 {251, 105},
1311 {251, 98},
1312 {187, 125},
1313 {187, 115},
1314 {187, 108},
1315 {187, 99},
1316 {243, 119},
1317 {243, 111},
1318 {243, 105},
1319 {243, 97},
1320 {243, 92},
1321 {211, 106},
1322 {211, 100},
1323 {179, 120},
1324 {179, 113},
1325 {179, 107},
1326 {147, 125},
1327 {147, 119},
1328 {147, 112},
1329 {147, 106},
1330 {147, 101},
1331 {147, 97},
1332 {147, 91},
1333 {115, 107},
1334 {235, 121},
1335 {235, 115},
1336 {235, 109},
1337 {203, 127},
1338 {203, 121},
1339 {203, 115},
1340 {203, 108},
1341 {203, 102},
1342 {203, 96},
1343 {203, 92},
1344 {171, 110},
1345 {171, 104},
1346 {171, 98},
1347 {139, 116},
1348 {227, 125},
1349 {227, 119},
1350 {227, 113},
1351 {227, 107},
1352 {227, 101},
1353 {227, 96},
1354 {195, 113},
1355 {195, 106},
1356 {195, 102},
1357 {195, 95},
1358 {163, 113},
1359 {163, 106},
1360 {163, 102},
1361 {163, 95},
1362 {131, 113},
1363 {131, 106},
1364 {131, 102},
1365 {131, 95},
1366 {99, 113},
1367 {99, 106},
1368 {99, 102},
1369 {99, 95},
1370 {67, 113},
1371 {67, 106},
1372 {67, 102},
1373 {67, 95},
1374 {35, 113},
1375 {35, 106},
1376 {35, 102},
1377 {35, 95},
1378 {3, 113},
1379 {3, 106},
1380 {3, 102},
1381 {3, 95} }, /* 2.4 GHz, lowest power */
1382 {
1383 {251, 127}, /* 5.x GHz, highest power */
1384 {251, 120},
1385 {251, 114},
1386 {219, 119},
1387 {219, 101},
1388 {187, 113},
1389 {187, 102},
1390 {155, 114},
1391 {155, 103},
1392 {123, 117},
1393 {123, 107},
1394 {123, 99},
1395 {123, 92},
1396 {91, 108},
1397 {59, 125},
1398 {59, 118},
1399 {59, 109},
1400 {59, 102},
1401 {59, 96},
1402 {59, 90},
1403 {27, 104},
1404 {27, 98},
1405 {27, 92},
1406 {115, 118},
1407 {115, 111},
1408 {115, 104},
1409 {83, 126},
1410 {83, 121},
1411 {83, 113},
1412 {83, 105},
1413 {83, 99},
1414 {51, 118},
1415 {51, 111},
1416 {51, 104},
1417 {51, 98},
1418 {19, 116},
1419 {19, 109},
1420 {19, 102},
1421 {19, 98},
1422 {19, 93},
1423 {171, 113},
1424 {171, 107},
1425 {171, 99},
1426 {139, 120},
1427 {139, 113},
1428 {139, 107},
1429 {139, 99},
1430 {107, 120},
1431 {107, 113},
1432 {107, 107},
1433 {107, 99},
1434 {75, 120},
1435 {75, 113},
1436 {75, 107},
1437 {75, 99},
1438 {43, 120},
1439 {43, 113},
1440 {43, 107},
1441 {43, 99},
1442 {11, 120},
1443 {11, 113},
1444 {11, 107},
1445 {11, 99},
1446 {131, 107},
1447 {131, 99},
1448 {99, 120},
1449 {99, 113},
1450 {99, 107},
1451 {99, 99},
1452 {67, 120},
1453 {67, 113},
1454 {67, 107},
1455 {67, 99},
1456 {35, 120},
1457 {35, 113},
1458 {35, 107},
1459 {35, 99},
1460 {3, 120} } /* 5.x GHz, lowest power */
1461};
1462
bb8c093b 1463static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1464{
1465 if (index < 0)
1466 return 0;
1467 if (index >= IWL_MAX_GAIN_ENTRIES)
1468 return IWL_MAX_GAIN_ENTRIES - 1;
1469 return (u8) index;
1470}
1471
1472/* Kick off thermal recalibration check every 60 seconds */
1473#define REG_RECALIB_PERIOD (60)
1474
1475/**
bb8c093b 1476 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1477 *
1478 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1479 * or 6 Mbit (OFDM) rates.
1480 */
4a8a4322 1481static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1482 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1483 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1484 int band_index)
1485{
bb8c093b 1486 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1487 s8 power;
1488 u8 power_index;
1489
1490 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1491
1492 /* use this channel group's 6Mbit clipping/saturation pwr,
1493 * but cap at regulatory scan power restriction (set during init
1494 * based on eeprom channel data) for this channel. */
14577f23 1495 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1496
1497 /* further limit to user's max power preference.
1498 * FIXME: Other spectrum management power limitations do not
1499 * seem to apply?? */
62ea9c5b 1500 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1501 scan_power_info->requested_power = power;
1502
1503 /* find difference between new scan *power* and current "normal"
1504 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1505 * current "normal" temperature-compensated Tx power *index* for
1506 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1507 * *index*. */
1508 power_index = ch_info->power_info[rate_index].power_table_index
1509 - (power - ch_info->power_info
14577f23 1510 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1511
1512 /* store reference index that we use when adjusting *all* scan
1513 * powers. So we can accommodate user (all channel) or spectrum
1514 * management (single channel) power changes "between" temperature
1515 * feedback compensation procedures.
1516 * don't force fit this reference index into gain table; it may be a
1517 * negative number. This will help avoid errors when we're at
1518 * the lower bounds (highest gains, for warmest temperatures)
1519 * of the table. */
1520
1521 /* don't exceed table bounds for "real" setting */
bb8c093b 1522 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1523
1524 scan_power_info->power_table_index = power_index;
1525 scan_power_info->tpc.tx_gain =
1526 power_gain_table[band_index][power_index].tx_gain;
1527 scan_power_info->tpc.dsp_atten =
1528 power_gain_table[band_index][power_index].dsp_atten;
1529}
1530
1531/**
75bcfae9 1532 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1533 *
1534 * Configures power settings for all rates for the current channel,
1535 * using values from channel info struct, and send to NIC
1536 */
dfb39e82 1537static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1538{
14577f23 1539 int rate_idx, i;
d20b3c65 1540 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1541 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1542 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1543 };
1544
8318d78a 1545 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1546 ch_info = iwl_get_channel_info(priv,
8318d78a 1547 priv->band,
8ccde88a 1548 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1549 if (!ch_info) {
15b1687c
WT		 1550 IWL_ERR(priv,
1551 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1552 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1553 return -EINVAL;
1554 }
1555
1556 if (!is_channel_valid(ch_info)) {
e1623446 1557 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1558 "non-Tx channel.\n");
1559 return 0;
1560 }
1561
1562 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1563 /* Fill OFDM rate */
1564 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1565 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1566
1567 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1568 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1569
e1623446 1570 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1571 le16_to_cpu(txpower.channel),
1572 txpower.band,
14577f23
MA		 1573 txpower.power[i].tpc.tx_gain,
1574 txpower.power[i].tpc.dsp_atten,
1575 txpower.power[i].rate);
1576 }
1577 /* Fill CCK rates */
1578 for (rate_idx = IWL_FIRST_CCK_RATE;
1579 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1580 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1581 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1582
e1623446 1583 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1584 le16_to_cpu(txpower.channel),
1585 txpower.band,
1586 txpower.power[i].tpc.tx_gain,
1587 txpower.power[i].tpc.dsp_atten,
1588 txpower.power[i].rate);
b481de9c
ZY		 1589 }
1590
518099a8
SO		 1591 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1592 sizeof(struct iwl3945_txpowertable_cmd),
1593 &txpower);
b481de9c
ZY		 1594
1595}
1596
1597/**
bb8c093b 1598 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1599 * @ch_info: Channel to update. Uses power_info.requested_power.
1600 *
1601 * Replace requested_power and base_power_index ch_info fields for
1602 * one channel.
1603 *
1604 * Called if user or spectrum management changes power preferences.
1605 * Takes into account h/w and modulation limitations (clip power).
1606 *
1607 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1608 *
1609 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1610 * properly fill out the scan powers, and actual h/w gain settings,
1611 * and send changes to NIC
1612 */
4a8a4322 1613static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1614 struct iwl_channel_info *ch_info)
b481de9c 1615{
bb8c093b 1616 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1617 int power_changed = 0;
1618 int i;
1619 const s8 *clip_pwrs;
1620 int power;
1621
1622 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1623 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1624
1625 /* Get this channel's rate-to-current-power settings table */
1626 power_info = ch_info->power_info;
1627
1628 /* update OFDM Txpower settings */
14577f23 1629 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1630 i++, ++power_info) {
1631 int delta_idx;
1632
1633 /* limit new power to be no more than h/w capability */
1634 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1635 if (power == power_info->requested_power)
1636 continue;
1637
1638 /* find difference between old and new requested powers,
1639 * update base (non-temp-compensated) power index */
1640 delta_idx = (power - power_info->requested_power) * 2;
1641 power_info->base_power_index -= delta_idx;
1642
1643 /* save new requested power value */
1644 power_info->requested_power = power;
1645
1646 power_changed = 1;
1647 }
1648
1649 /* update CCK Txpower settings, based on OFDM 12M setting ...
1650 * ... all CCK power settings for a given channel are the *same*. */
1651 if (power_changed) {
1652 power =
14577f23 1653 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1654 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1655
bb8c093b 1656 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1657 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1658 power_info->requested_power = power;
1659 power_info->base_power_index =
14577f23 1660 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1661 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1662 ++power_info;
1663 }
1664 }
1665
1666 return 0;
1667}
1668
1669/**
bb8c093b 1670 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1671 *
1672 * NOTE: Returned power limit may be less (but not more) than requested,
1673 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1674 * (no consideration for h/w clipping limitations).
1675 */
d20b3c65 1676static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1677{
1678 s8 max_power;
1679
1680#if 0
1681 /* if we're using TGd limits, use lower of TGd or EEPROM */
1682 if (ch_info->tgd_data.max_power != 0)
1683 max_power = min(ch_info->tgd_data.max_power,
1684 ch_info->eeprom.max_power_avg);
1685
1686 /* else just use EEPROM limits */
1687 else
1688#endif
1689 max_power = ch_info->eeprom.max_power_avg;
1690
1691 return min(max_power, ch_info->max_power_avg);
1692}
1693
1694/**
bb8c093b 1695 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1696 *
1697 * Compensate txpower settings of *all* channels for temperature.
1698 * This only accounts for the difference between current temperature
1699 * and the factory calibration temperatures, and bases the new settings
1700 * on the channel's base_power_index.
1701 *
1702 * If RxOn is "associated", this sends the new Txpower to NIC!
1703 */
4a8a4322 1704static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1705{
d20b3c65 1706 struct iwl_channel_info *ch_info = NULL;
e6148917 1707 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1708 int delta_index;
1709 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1710 u8 a_band;
1711 u8 rate_index;
1712 u8 scan_tbl_index;
1713 u8 i;
1714 int ref_temp;
1715 int temperature = priv->temperature;
1716
4e7033ef
WYG		 1717 if (priv->disable_tx_power_cal ||
1718 test_bit(STATUS_SCANNING, &priv->status)) {
1719 /* do not perform tx power calibration */
1720 return 0;
1721 }
b481de9c
ZY		 1722 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1723 for (i = 0; i < priv->channel_count; i++) {
1724 ch_info = &priv->channel_info[i];
1725 a_band = is_channel_a_band(ch_info);
1726
1727 /* Get this chnlgrp's factory calibration temperature */
e6148917 1728 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1729 temperature;
1730
a96a27f9 1731 /* get power index adjustment based on current and factory
b481de9c 1732 * temps */
bb8c093b 1733 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1734 ref_temp);
1735
1736 /* set tx power value for all rates, OFDM and CCK */
1737 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1738 rate_index++) {
1739 int power_idx =
1740 ch_info->power_info[rate_index].base_power_index;
1741
1742 /* temperature compensate */
1743 power_idx += delta_index;
1744
1745 /* stay within table range */
bb8c093b 1746 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1747 ch_info->power_info[rate_index].
1748 power_table_index = (u8) power_idx;
1749 ch_info->power_info[rate_index].tpc =
1750 power_gain_table[a_band][power_idx];
1751 }
1752
1753 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1754 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1755
1756 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1757 for (scan_tbl_index = 0;
1758 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1759 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1760 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1761 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1762 actual_index, clip_pwrs,
1763 ch_info, a_band);
1764 }
1765 }
1766
1767 /* send Txpower command for current channel to ucode */
75bcfae9 1768 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1769}
1770
4a8a4322 1771int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1772{
d20b3c65 1773 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1774 s8 max_power;
1775 u8 a_band;
1776 u8 i;
1777
62ea9c5b 1778 if (priv->tx_power_user_lmt == power) {
e1623446 1779 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1780 "limit: %ddBm.\n", power);
1781 return 0;
1782 }
1783
e1623446 1784 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1785 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1786
1787 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1788
1789 for (i = 0; i < priv->channel_count; i++) {
1790 ch_info = &priv->channel_info[i];
1791 a_band = is_channel_a_band(ch_info);
1792
1793 /* find minimum power of all user and regulatory constraints
1794 * (does not consider h/w clipping limitations) */
bb8c093b 1795 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1796 max_power = min(power, max_power);
1797 if (max_power != ch_info->curr_txpow) {
1798 ch_info->curr_txpow = max_power;
1799
1800 /* this considers the h/w clipping limitations */
bb8c093b 1801 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1802 }
1803 }
1804
1805 /* update txpower settings for all channels,
1806 * send to NIC if associated. */
1807 is_temp_calib_needed(priv);
bb8c093b 1808 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1809
1810 return 0;
1811}
1812
5bbe233b
AK		 1813static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1814{
1815 int rc = 0;
2f301227 1816 struct iwl_rx_packet *pkt;
5bbe233b
AK		 1817 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1818 struct iwl_host_cmd cmd = {
1819 .id = REPLY_RXON_ASSOC,
1820 .len = sizeof(rxon_assoc),
c2acea8e 1821 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1822 .data = &rxon_assoc,
1823 };
1824 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1825 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1826
1827 if ((rxon1->flags == rxon2->flags) &&
1828 (rxon1->filter_flags == rxon2->filter_flags) &&
1829 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1830 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1831 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1832 return 0;
1833 }
1834
1835 rxon_assoc.flags = priv->staging_rxon.flags;
1836 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1837 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1838 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1839 rxon_assoc.reserved = 0;
1840
1841 rc = iwl_send_cmd_sync(priv, &cmd);
1842 if (rc)
1843 return rc;
1844
2f301227
ZY		 1845 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1846 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
5bbe233b
AK		 1847 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1848 rc = -EIO;
1849 }
1850
64a76b50 1851 iwl_free_pages(priv, cmd.reply_page);
5bbe233b
AK		 1852
1853 return rc;
1854}
1855
e0158e61
AK		 1856/**
1857 * iwl3945_commit_rxon - commit staging_rxon to hardware
1858 *
1859 * The RXON command in staging_rxon is committed to the hardware and
1860 * the active_rxon structure is updated with the new data. This
1861 * function correctly transitions out of the RXON_ASSOC_MSK state if
1862 * a HW tune is required based on the RXON structure changes.
1863 */
1864static int iwl3945_commit_rxon(struct iwl_priv *priv)
1865{
1866 /* cast away the const for active_rxon in this function */
1867 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1868 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1869 int rc = 0;
1870 bool new_assoc =
1871 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1872
1873 if (!iwl_is_alive(priv))
1874 return -1;
1875
1876 /* always get timestamp with Rx frame */
1877 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1878
1879 /* select antenna */
1880 staging_rxon->flags &=
1881 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1882 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1883
1884 rc = iwl_check_rxon_cmd(priv);
1885 if (rc) {
1886 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1887 return -EINVAL;
1888 }
1889
1890 /* If we don't need to send a full RXON, we can use
1891 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1892 * and other flags for the current radio configuration. */
1893 if (!iwl_full_rxon_required(priv)) {
1894 rc = iwl_send_rxon_assoc(priv);
1895 if (rc) {
1896 IWL_ERR(priv, "Error setting RXON_ASSOC "
1897 "configuration (%d).\n", rc);
1898 return rc;
1899 }
1900
1901 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1902
1903 return 0;
1904 }
1905
1906 /* If we are currently associated and the new config requires
1907 * an RXON_ASSOC and the new config wants the associated mask enabled,
1908 * we must clear the associated from the active configuration
1909 * before we apply the new config */
1910 if (iwl_is_associated(priv) && new_assoc) {
1911 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1912 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1913
1914 /*
1915 * reserved4 and 5 could have been filled by the iwlcore code.
1916 * Let's clear them before pushing to the 3945.
1917 */
1918 active_rxon->reserved4 = 0;
1919 active_rxon->reserved5 = 0;
1920 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1921 sizeof(struct iwl3945_rxon_cmd),
1922 &priv->active_rxon);
1923
1924 /* If the mask clearing failed then we set
1925 * active_rxon back to what it was previously */
1926 if (rc) {
1927 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1928 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1929 "configuration (%d).\n", rc);
1930 return rc;
1931 }
7e246191
RC		 1932 iwl_clear_ucode_stations(priv, false);
1933 iwl_restore_stations(priv);
e0158e61
AK		 1934 }
1935
1936 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1937 "* with%s RXON_FILTER_ASSOC_MSK\n"
1938 "* channel = %d\n"
1939 "* bssid = %pM\n",
1940 (new_assoc ? "" : "out"),
1941 le16_to_cpu(staging_rxon->channel),
1942 staging_rxon->bssid_addr);
1943
1944 /*
1945 * reserved4 and 5 could have been filled by the iwlcore code.
1946 * Let's clear them before pushing to the 3945.
1947 */
1948 staging_rxon->reserved4 = 0;
1949 staging_rxon->reserved5 = 0;
1950
90e8e424 1951 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1952
1953 /* Apply the new configuration */
1954 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1955 sizeof(struct iwl3945_rxon_cmd),
1956 staging_rxon);
1957 if (rc) {
1958 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1959 return rc;
1960 }
1961
1962 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1963
7e246191
RC		 1964 if (!new_assoc) {
1965 iwl_clear_ucode_stations(priv, false);
1966 iwl_restore_stations(priv);
1967 }
e0158e61
AK		 1968
1969 /* If we issue a new RXON command which required a tune then we must
1970 * send a new TXPOWER command or we won't be able to Tx any frames */
1971 rc = priv->cfg->ops->lib->send_tx_power(priv);
1972 if (rc) {
1973 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1974 return rc;
1975 }
1976
e0158e61
AK		 1977 /* Init the hardware's rate fallback order based on the band */
1978 rc = iwl3945_init_hw_rate_table(priv);
1979 if (rc) {
1980 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1981 return -EIO;
1982 }
1983
1984 return 0;
1985}
1986
b481de9c
ZY		 1987/**
1988 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1989 *
1990 * -- reset periodic timer
1991 * -- see if temp has changed enough to warrant re-calibration ... if so:
1992 * -- correct coeffs for temp (can reset temp timer)
1993 * -- save this temp as "last",
1994 * -- send new set of gain settings to NIC
1995 * NOTE: This should continue working, even when we're not associated,
1996 * so we can keep our internal table of scan powers current. */
4a8a4322 1997void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1998{
1999 /* This will kick in the "brute force"
bb8c093b 2000 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2001 if (!is_temp_calib_needed(priv))
2002 goto reschedule;
2003
2004 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2005 * This is based *only* on current temperature,
2006 * ignoring any previous power measurements */
bb8c093b 2007 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2008
2009 reschedule:
2010 queue_delayed_work(priv->workqueue,
ee525d13 2011 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
b481de9c
ZY		 2012}
2013
416e1438 2014static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2015{
4a8a4322 2016 struct iwl_priv *priv = container_of(work, struct iwl_priv,
ee525d13 2017 _3945.thermal_periodic.work);
b481de9c
ZY		 2018
2019 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2020 return;
2021
2022 mutex_lock(&priv->mutex);
2023 iwl3945_reg_txpower_periodic(priv);
2024 mutex_unlock(&priv->mutex);
2025}
2026
2027/**
bb8c093b 2028 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2029 * for the channel.
2030 *
2031 * This function is used when initializing channel-info structs.
2032 *
2033 * NOTE: These channel groups do *NOT* match the bands above!
2034 * These channel groups are based on factory-tested channels;
2035 * on A-band, EEPROM's "group frequency" entries represent the top
2036 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2037 */
4a8a4322 2038static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2039 const struct iwl_channel_info *ch_info)
b481de9c 2040{
e6148917
SO		 2041 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2042 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2043 u8 group;
2044 u16 group_index = 0; /* based on factory calib frequencies */
2045 u8 grp_channel;
2046
2047 /* Find the group index for the channel ... don't use index 1(?) */
2048 if (is_channel_a_band(ch_info)) {
2049 for (group = 1; group < 5; group++) {
2050 grp_channel = ch_grp[group].group_channel;
2051 if (ch_info->channel <= grp_channel) {
2052 group_index = group;
2053 break;
2054 }
2055 }
2056 /* group 4 has a few channels *above* its factory cal freq */
2057 if (group == 5)
2058 group_index = 4;
2059 } else
2060 group_index = 0; /* 2.4 GHz, group 0 */
2061
e1623446 2062 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2063 group_index);
2064 return group_index;
2065}
2066
2067/**
bb8c093b 2068 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2069 *
2070 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2071 * into radio/DSP gain settings table for requested power.
2072 */
4a8a4322 2073static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2074 s8 requested_power,
2075 s32 setting_index, s32 *new_index)
2076{
bb8c093b 2077 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2078 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2079 s32 index0, index1;
2080 s32 power = 2 * requested_power;
2081 s32 i;
bb8c093b 2082 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2083 s32 gains0, gains1;
2084 s32 res;
2085 s32 denominator;
2086
e6148917 2087 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2088 samples = chnl_grp->samples;
2089 for (i = 0; i < 5; i++) {
2090 if (power == samples[i].power) {
2091 *new_index = samples[i].gain_index;
2092 return 0;
2093 }
2094 }
2095
2096 if (power > samples[1].power) {
2097 index0 = 0;
2098 index1 = 1;
2099 } else if (power > samples[2].power) {
2100 index0 = 1;
2101 index1 = 2;
2102 } else if (power > samples[3].power) {
2103 index0 = 2;
2104 index1 = 3;
2105 } else {
2106 index0 = 3;
2107 index1 = 4;
2108 }
2109
2110 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2111 if (denominator == 0)
2112 return -EINVAL;
2113 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2114 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2115 res = gains0 + (gains1 - gains0) *
2116 ((s32) power - (s32) samples[index0].power) / denominator +
2117 (1 << 18);
2118 *new_index = res >> 19;
2119 return 0;
2120}
2121
4a8a4322 2122static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2123{
2124 u32 i;
2125 s32 rate_index;
e6148917 2126 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2127 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2128
e1623446 2129 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2130
2131 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2132 s8 *clip_pwrs; /* table of power levels for each rate */
2133 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2134 group = &eeprom->groups[i];
b481de9c
ZY		 2135
2136 /* sanity check on factory saturation power value */
2137 if (group->saturation_power < 40) {
39aadf8c 2138 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2139 "less than minimum expected 40\n",
2140 group->saturation_power);
2141 return;
2142 }
2143
2144 /*
2145 * Derive requested power levels for each rate, based on
2146 * hardware capabilities (saturation power for band).
2147 * Basic value is 3dB down from saturation, with further
2148 * power reductions for highest 3 data rates. These
2149 * backoffs provide headroom for high rate modulation
2150 * power peaks, without too much distortion (clipping).
2151 */
2152 /* we'll fill in this array with h/w max power levels */
67d613ae 2153 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
b481de9c
ZY		 2154
2155 /* divide factory saturation power by 2 to find -3dB level */
2156 satur_pwr = (s8) (group->saturation_power >> 1);
2157
2158 /* fill in channel group's nominal powers for each rate */
2159 for (rate_index = 0;
1d79e53c 2160 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
b481de9c 2161 switch (rate_index) {
14577f23 2162 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2163 if (i == 0) /* B/G */
2164 *clip_pwrs = satur_pwr;
2165 else /* A */
2166 *clip_pwrs = satur_pwr - 5;
2167 break;
14577f23 2168 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2169 if (i == 0)
2170 *clip_pwrs = satur_pwr - 7;
2171 else
2172 *clip_pwrs = satur_pwr - 10;
2173 break;
14577f23 2174 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2175 if (i == 0)
2176 *clip_pwrs = satur_pwr - 9;
2177 else
2178 *clip_pwrs = satur_pwr - 12;
2179 break;
2180 default:
2181 *clip_pwrs = satur_pwr;
2182 break;
2183 }
2184 }
2185 }
2186}
2187
2188/**
2189 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2190 *
2191 * Second pass (during init) to set up priv->channel_info
2192 *
2193 * Set up Tx-power settings in our channel info database for each VALID
2194 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2195 * and current temperature.
2196 *
2197 * Since this is based on current temperature (at init time), these values may
2198 * not be valid for very long, but it gives us a starting/default point,
2199 * and allows us to active (i.e. using Tx) scan.
2200 *
2201 * This does *not* write values to NIC, just sets up our internal table.
2202 */
4a8a4322 2203int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2204{
d20b3c65 2205 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2206 struct iwl3945_channel_power_info *pwr_info;
e6148917 2207 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2208 int delta_index;
2209 u8 rate_index;
2210 u8 scan_tbl_index;
2211 const s8 *clip_pwrs; /* array of power levels for each rate */
2212 u8 gain, dsp_atten;
2213 s8 power;
2214 u8 pwr_index, base_pwr_index, a_band;
2215 u8 i;
2216 int temperature;
2217
2218 /* save temperature reference,
2219 * so we can determine next time to calibrate */
bb8c093b 2220 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2221 priv->last_temperature = temperature;
2222
bb8c093b 2223 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2224
2225 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2226 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2227 i++, ch_info++) {
2228 a_band = is_channel_a_band(ch_info);
2229 if (!is_channel_valid(ch_info))
2230 continue;
2231
2232 /* find this channel's channel group (*not* "band") index */
2233 ch_info->group_index =
bb8c093b 2234 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2235
2236 /* Get this chnlgrp's rate->max/clip-powers table */
67d613ae 2237 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2238
2239 /* calculate power index *adjustment* value according to
2240 * diff between current temperature and factory temperature */
bb8c093b 2241 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2242 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2243 temperature);
2244
e1623446 2245 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2246 ch_info->channel, delta_index, temperature +
2247 IWL_TEMP_CONVERT);
2248
2249 /* set tx power value for all OFDM rates */
2250 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2251 rate_index++) {
25a4ccea 2252 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2253 int rc;
2254
2255 /* use channel group's clip-power table,
2256 * but don't exceed channel's max power */
2257 s8 pwr = min(ch_info->max_power_avg,
2258 clip_pwrs[rate_index]);
2259
2260 pwr_info = &ch_info->power_info[rate_index];
2261
2262 /* get base (i.e. at factory-measured temperature)
2263 * power table index for this rate's power */
bb8c093b 2264 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2265 ch_info->group_index,
2266 &power_idx);
2267 if (rc) {
15b1687c 2268 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2269 return rc;
2270 }
2271 pwr_info->base_power_index = (u8) power_idx;
2272
2273 /* temperature compensate */
2274 power_idx += delta_index;
2275
2276 /* stay within range of gain table */
bb8c093b 2277 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2278
bb8c093b 2279 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2280 pwr_info->requested_power = pwr;
2281 pwr_info->power_table_index = (u8) power_idx;
2282 pwr_info->tpc.tx_gain =
2283 power_gain_table[a_band][power_idx].tx_gain;
2284 pwr_info->tpc.dsp_atten =
2285 power_gain_table[a_band][power_idx].dsp_atten;
2286 }
2287
2288 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2289 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2290 power = pwr_info->requested_power +
2291 IWL_CCK_FROM_OFDM_POWER_DIFF;
2292 pwr_index = pwr_info->power_table_index +
2293 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2294 base_pwr_index = pwr_info->base_power_index +
2295 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2296
2297 /* stay within table range */
bb8c093b 2298 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2299 gain = power_gain_table[a_band][pwr_index].tx_gain;
2300 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2301
bb8c093b 2302 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2303 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2304 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2305 for (rate_index = 0;
2306 rate_index < IWL_CCK_RATES; rate_index++) {
2307 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2308 pwr_info->requested_power = power;
2309 pwr_info->power_table_index = pwr_index;
2310 pwr_info->base_power_index = base_pwr_index;
2311 pwr_info->tpc.tx_gain = gain;
2312 pwr_info->tpc.dsp_atten = dsp_atten;
2313 }
2314
2315 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2316 for (scan_tbl_index = 0;
2317 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2318 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2319 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2320 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2321 actual_index, clip_pwrs, ch_info, a_band);
2322 }
2323 }
2324
2325 return 0;
2326}
2327
4a8a4322 2328int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2329{
2330 int rc;
b481de9c 2331
5d49f498
AK		 2332 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2333 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2334 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2335 if (rc < 0)
15b1687c 2336 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2337
b481de9c
ZY		 2338 return 0;
2339}
2340
188cf6c7 2341int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2342{
b481de9c
ZY		 2343 int txq_id = txq->q.id;
2344
ee525d13 2345 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
b481de9c
ZY		 2346
2347 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2348
5d49f498
AK		 2349 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2350 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2351
5d49f498 2352 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2353 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2354 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2355 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2356 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2357 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2358
2359 /* fake read to flush all prev. writes */
5d49f498 2360 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2361
2362 return 0;
2363}
2364
42427b4e
KA		 2365/*
2366 * HCMD utils
2367 */
2368static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2369{
2370 switch (cmd_id) {
2371 case REPLY_RXON:
d25aabb0
WT		 2372 return sizeof(struct iwl3945_rxon_cmd);
2373 case POWER_TABLE_CMD:
2374 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2375 default:
2376 return len;
2377 }
2378}
2379
c587de0b 2380
17f841cd
SO		 2381static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2382{
c587de0b
TW		 2383 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2384 addsta->mode = cmd->mode;
2385 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2386 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2387 addsta->station_flags = cmd->station_flags;
2388 addsta->station_flags_msk = cmd->station_flags_msk;
2389 addsta->tid_disable_tx = cpu_to_le16(0);
2390 addsta->rate_n_flags = cmd->rate_n_flags;
2391 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2392 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2393 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2394
2395 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2396}
2397
c587de0b 2398
b481de9c
ZY		 2399/**
2400 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2401 */
4a8a4322 2402int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2403{
14577f23 2404 int rc, i, index, prev_index;
bb8c093b 2405 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2406 .reserved = {0, 0, 0},
2407 };
bb8c093b 2408 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2409
bb8c093b
CH		 2410 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2411 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2412
2413 table[index].rate_n_flags =
bb8c093b 2414 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2415 table[index].try_cnt = priv->retry_rate;
bb8c093b 2416 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2417 table[index].next_rate_index =
2418 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2419 }
2420
8318d78a
JB		 2421 switch (priv->band) {
2422 case IEEE80211_BAND_5GHZ:
e1623446 2423 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2424 /* If one of the following CCK rates is used,
2425 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2426 for (i = IWL_RATE_1M_INDEX_TABLE;
2427 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2428 table[i].next_rate_index =
2429 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2430
2431 /* Don't fall back to CCK rates */
7262796a
AM		 2432 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2433 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2434
2435 /* Don't drop out of OFDM rates */
14577f23 2436 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2437 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2438 break;
2439
8318d78a 2440 case IEEE80211_BAND_2GHZ:
e1623446 2441 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2442 /* If an OFDM rate is used, have it fall back to the
2443 * 1M CCK rates */
b481de9c 2444
ee525d13 2445 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2446 iwl_is_associated(priv)) {
7262796a
AM		 2447
2448 index = IWL_FIRST_CCK_RATE;
2449 for (i = IWL_RATE_6M_INDEX_TABLE;
2450 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2451 table[i].next_rate_index =
2452 iwl3945_rates[index].table_rs_index;
2453
2454 index = IWL_RATE_11M_INDEX_TABLE;
2455 /* CCK shouldn't fall back to OFDM... */
2456 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2457 }
b481de9c
ZY		 2458 break;
2459
2460 default:
8318d78a 2461 WARN_ON(1);
b481de9c
ZY		 2462 break;
2463 }
2464
2465 /* Update the rate scaling for control frame Tx */
2466 rate_cmd.table_id = 0;
518099a8 2467 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2468 &rate_cmd);
2469 if (rc)
2470 return rc;
2471
2472 /* Update the rate scaling for data frame Tx */
2473 rate_cmd.table_id = 1;
518099a8 2474 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2475 &rate_cmd);
2476}
2477
796083cb 2478/* Called when initializing driver */
4a8a4322 2479int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2480{
3832ec9d
AK		 2481 memset((void *)&priv->hw_params, 0,
2482 sizeof(struct iwl_hw_params));
b481de9c 2483
ee525d13
JB		 2484 priv->_3945.shared_virt =
2485 dma_alloc_coherent(&priv->pci_dev->dev,
2486 sizeof(struct iwl3945_shared),
2487 &priv->_3945.shared_phys, GFP_KERNEL);
2488 if (!priv->_3945.shared_virt) {
15b1687c 2489 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2490 return -ENOMEM;
2491 }
2492
21c02a1a 2493 /* Assign number of Usable TX queues */
88804e2b 2494 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2495
a8e74e27 2496 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2f301227 2497 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
3832ec9d
AK		 2498 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2499 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2500 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2501 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2502
141c43a3 2503 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2504 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
141c43a3 2505
b481de9c
ZY		 2506 return 0;
2507}
2508
4a8a4322 2509unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2510 struct iwl3945_frame *frame, u8 rate)
b481de9c 2511{
bb8c093b 2512 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2513 unsigned int frame_size;
2514
bb8c093b 2515 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2516 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2517
3832ec9d 2518 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2519 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2520
bb8c093b 2521 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2522 tx_beacon_cmd->frame,
b481de9c
ZY		 2523 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2524
2525 BUG_ON(frame_size > MAX_MPDU_SIZE);
2526 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2527
2528 tx_beacon_cmd->tx.rate = rate;
2529 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2530 TX_CMD_FLG_TSF_MSK);
2531
14577f23
MA		 2532 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2533 tx_beacon_cmd->tx.supp_rates[0] =
2534 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2535
b481de9c 2536 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2537 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2538
3ac7f146 2539 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2540}
2541
4a8a4322 2542void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2543{
91c066f2 2544 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2545 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2546}
2547
4a8a4322 2548void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2549{
ee525d13 2550 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
b481de9c
ZY		 2551 iwl3945_bg_reg_txpower_periodic);
2552}
2553
4a8a4322 2554void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2555{
ee525d13 2556 cancel_delayed_work(&priv->_3945.thermal_periodic);
b481de9c
ZY		 2557}
2558
0164b9b4
KA		 2559/* check contents of special bootstrap uCode SRAM */
2560static int iwl3945_verify_bsm(struct iwl_priv *priv)
2561 {
2562 __le32 *image = priv->ucode_boot.v_addr;
2563 u32 len = priv->ucode_boot.len;
2564 u32 reg;
2565 u32 val;
2566
e1623446 2567 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2568
2569 /* verify BSM SRAM contents */
2570 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2571 for (reg = BSM_SRAM_LOWER_BOUND;
2572 reg < BSM_SRAM_LOWER_BOUND + len;
2573 reg += sizeof(u32), image++) {
2574 val = iwl_read_prph(priv, reg);
2575 if (val != le32_to_cpu(*image)) {
2576 IWL_ERR(priv, "BSM uCode verification failed at "
2577 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2578 BSM_SRAM_LOWER_BOUND,
2579 reg - BSM_SRAM_LOWER_BOUND, len,
2580 val, le32_to_cpu(*image));
2581 return -EIO;
2582 }
2583 }
2584
e1623446 2585 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2586
2587 return 0;
2588}
2589
e6148917
SO		 2590
2591/******************************************************************************
2592 *
2593 * EEPROM related functions
2594 *
2595 ******************************************************************************/
2596
2597/*
2598 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2599 * embedded controller) as EEPROM reader; each read is a series of pulses
2600 * to/from the EEPROM chip, not a single event, so even reads could conflict
2601 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2602 * simply claims ownership, which should be safe when this function is called
2603 * (i.e. before loading uCode!).
2604 */
2605static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2606{
2607 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2608 return 0;
2609}
2610
2611
2612static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2613{
2614 return;
2615}
2616
0164b9b4
KA		 2617 /**
2618 * iwl3945_load_bsm - Load bootstrap instructions
2619 *
2620 * BSM operation:
2621 *
2622 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2623 * in special SRAM that does not power down during RFKILL. When powering back
2624 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2625 * the bootstrap program into the on-board processor, and starts it.
2626 *
2627 * The bootstrap program loads (via DMA) instructions and data for a new
2628 * program from host DRAM locations indicated by the host driver in the
2629 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2630 * automatically.
2631 *
2632 * When initializing the NIC, the host driver points the BSM to the
2633 * "initialize" uCode image. This uCode sets up some internal data, then
2634 * notifies host via "initialize alive" that it is complete.
2635 *
2636 * The host then replaces the BSM_DRAM_* pointer values to point to the
2637 * normal runtime uCode instructions and a backup uCode data cache buffer
2638 * (filled initially with starting data values for the on-board processor),
2639 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2640 * which begins normal operation.
2641 *
2642 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2643 * the backup data cache in DRAM before SRAM is powered down.
2644 *
2645 * When powering back up, the BSM loads the bootstrap program. This reloads
2646 * the runtime uCode instructions and the backup data cache into SRAM,
2647 * and re-launches the runtime uCode from where it left off.
2648 */
2649static int iwl3945_load_bsm(struct iwl_priv *priv)
2650{
2651 __le32 *image = priv->ucode_boot.v_addr;
2652 u32 len = priv->ucode_boot.len;
2653 dma_addr_t pinst;
2654 dma_addr_t pdata;
2655 u32 inst_len;
2656 u32 data_len;
2657 int rc;
2658 int i;
2659 u32 done;
2660 u32 reg_offset;
2661
e1623446 2662 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2663
2664 /* make sure bootstrap program is no larger than BSM's SRAM size */
2665 if (len > IWL39_MAX_BSM_SIZE)
2666 return -EINVAL;
2667
2668 /* Tell bootstrap uCode where to find the "Initialize" uCode
2669 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2670 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2671 * after the "initialize" uCode has run, to point to
2672 * runtime/protocol instructions and backup data cache. */
2673 pinst = priv->ucode_init.p_addr;
2674 pdata = priv->ucode_init_data.p_addr;
2675 inst_len = priv->ucode_init.len;
2676 data_len = priv->ucode_init_data.len;
2677
0164b9b4
KA		 2678 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2679 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2680 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2681 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2682
2683 /* Fill BSM memory with bootstrap instructions */
2684 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2685 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2686 reg_offset += sizeof(u32), image++)
2687 _iwl_write_prph(priv, reg_offset,
2688 le32_to_cpu(*image));
2689
2690 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2691 if (rc)
0164b9b4 2692 return rc;
0164b9b4
KA		 2693
2694 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2695 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2696 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2697 IWL39_RTC_INST_LOWER_BOUND);
2698 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2699
2700 /* Load bootstrap code into instruction SRAM now,
2701 * to prepare to load "initialize" uCode */
2702 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2703 BSM_WR_CTRL_REG_BIT_START);
2704
2705 /* Wait for load of bootstrap uCode to finish */
2706 for (i = 0; i < 100; i++) {
2707 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2708 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2709 break;
2710 udelay(10);
2711 }
2712 if (i < 100)
e1623446 2713 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2714 else {
2715 IWL_ERR(priv, "BSM write did not complete!\n");
2716 return -EIO;
2717 }
2718
2719 /* Enable future boot loads whenever power management unit triggers it
2720 * (e.g. when powering back up after power-save shutdown) */
2721 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2722 BSM_WR_CTRL_REG_BIT_START_EN);
2723
0164b9b4
KA		 2724 return 0;
2725}
2726
cc0f555d
JS		 2727#define IWL3945_UCODE_GET(item) \
2728static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2729 u32 api_ver) \
2730{ \
2731 return le32_to_cpu(ucode->u.v1.item); \
2732}
2733
2734static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2735{
2736 return UCODE_HEADER_SIZE(1);
2737}
2738static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2739 u32 api_ver)
2740{
2741 return 0;
2742}
2743static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2744 u32 api_ver)
2745{
2746 return (u8 *) ucode->u.v1.data;
2747}
2748
2749IWL3945_UCODE_GET(inst_size);
2750IWL3945_UCODE_GET(data_size);
2751IWL3945_UCODE_GET(init_size);
2752IWL3945_UCODE_GET(init_data_size);
2753IWL3945_UCODE_GET(boot_size);
2754
5bbe233b
AK		 2755static struct iwl_hcmd_ops iwl3945_hcmd = {
2756 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2757 .commit_rxon = iwl3945_commit_rxon,
65b52bde 2758 .send_bt_config = iwl_send_bt_config,
5bbe233b
AK		 2759};
2760
cc0f555d
JS		 2761static struct iwl_ucode_ops iwl3945_ucode = {
2762 .get_header_size = iwl3945_ucode_get_header_size,
2763 .get_build = iwl3945_ucode_get_build,
2764 .get_inst_size = iwl3945_ucode_get_inst_size,
2765 .get_data_size = iwl3945_ucode_get_data_size,
2766 .get_init_size = iwl3945_ucode_get_init_size,
2767 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2768 .get_boot_size = iwl3945_ucode_get_boot_size,
2769 .get_data = iwl3945_ucode_get_data,
2770};
2771
0164b9b4 2772static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2773 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2774 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2775 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2776 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2777 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2778 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2779 .apm_ops = {
2780 .init = iwl3945_apm_init,
d68b603c 2781 .stop = iwl_apm_stop,
01ec616d 2782 .config = iwl3945_nic_config,
854682ed 2783 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2784 },
e6148917
SO		 2785 .eeprom_ops = {
2786 .regulatory_bands = {
2787 EEPROM_REGULATORY_BAND_1_CHANNELS,
2788 EEPROM_REGULATORY_BAND_2_CHANNELS,
2789 EEPROM_REGULATORY_BAND_3_CHANNELS,
2790 EEPROM_REGULATORY_BAND_4_CHANNELS,
2791 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2792 EEPROM_REGULATORY_BAND_NO_HT40,
2793 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2794 },
2795 .verify_signature = iwlcore_eeprom_verify_signature,
2796 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2797 .release_semaphore = iwl3945_eeprom_release_semaphore,
2798 .query_addr = iwlcore_eeprom_query_addr,
2799 },
75bcfae9 2800 .send_tx_power = iwl3945_send_tx_power,
c2436980 2801 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2802 .post_associate = iwl3945_post_associate,
ef850d7c 2803 .isr = iwl_isr_legacy,
60690a6a 2804 .config_ap = iwl3945_config_ap,
3459ab5a 2805 .add_bcast_station = iwl3945_add_bcast_station,
17f36fc6
AK		 2806
2807 .debugfs_ops = {
2808 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2809 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2810 .general_stats_read = iwl3945_ucode_general_stats_read,
2811 },
0164b9b4
KA		 2812};
2813
42427b4e
KA		 2814static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2815 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2816 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
37dc70fe 2817 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
b6e4c55a 2818 .request_scan = iwl3945_request_scan,
42427b4e
KA		 2819};
2820
45d5d805 2821static const struct iwl_ops iwl3945_ops = {
cc0f555d 2822 .ucode = &iwl3945_ucode,
0164b9b4 2823 .lib = &iwl3945_lib,
5bbe233b 2824 .hcmd = &iwl3945_hcmd,
42427b4e 2825 .utils = &iwl3945_hcmd_utils,
e932a609 2826 .led = &iwl3945_led_ops,
0164b9b4
KA		 2827};
2828
c0f20d91 2829static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2830 .name = "3945BG",
a0987a8d
RC		 2831 .fw_name_pre = IWL3945_FW_PRE,
2832 .ucode_api_max = IWL3945_UCODE_API_MAX,
2833 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2834 .sku = IWL_SKU_G,
e6148917
SO		 2835 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2836 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2837 .ops = &iwl3945_ops,
88804e2b 2838 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2839 .mod_params = &iwl3945_mod_params,
fadb3582
BC		 2840 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2841 .set_l0s = false,
2842 .use_bsm = true,
b261793d
DH		 2843 .use_isr_legacy = true,
2844 .ht_greenfield_support = false,
f2d0d0e2 2845 .led_compensation = 64,
bc45a670 2846 .broken_powersave = true,
3e4fb5fa 2847 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
b74e31a9 2848 .monitor_recover_period = IWL_MONITORING_PERIOD,
678b385d 2849 .max_event_log_size = 512,
4e7033ef 2850 .tx_power_by_driver = true,
82b9a121
TW		 2851};
2852
c0f20d91 2853static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2854 .name = "3945ABG",
a0987a8d
RC		 2855 .fw_name_pre = IWL3945_FW_PRE,
2856 .ucode_api_max = IWL3945_UCODE_API_MAX,
2857 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2858 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2859 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2860 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2861 .ops = &iwl3945_ops,
88804e2b 2862 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2863 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2864 .use_isr_legacy = true,
2865 .ht_greenfield_support = false,
f2d0d0e2 2866 .led_compensation = 64,
bc45a670 2867 .broken_powersave = true,
3e4fb5fa 2868 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
b74e31a9 2869 .monitor_recover_period = IWL_MONITORING_PERIOD,
678b385d 2870 .max_event_log_size = 512,
4e7033ef 2871 .tx_power_by_driver = true,
82b9a121
TW		 2872};
2873
a3aa1884 2874DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
82b9a121
TW		 2875 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2876 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2877 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2878 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2879 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2880 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2881 {0}
2882};
2883
bb8c093b 2884MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux kernel - Deliverables
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