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Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelv...
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
17f841cd 44#include "iwl-sta.h"
b481de9c 45#include "iwl-3945.h"
e6148917 46#include "iwl-eeprom.h"
5d08cd1d 47#include "iwl-helpers.h"
5747d47f 48#include "iwl-core.h"
d9829a67 49#include "iwl-agn-rs.h"
b481de9c
ZY		 50
51#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
52 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
53 IWL_RATE_##r##M_IEEE, \
54 IWL_RATE_##ip##M_INDEX, \
55 IWL_RATE_##in##M_INDEX, \
56 IWL_RATE_##rp##M_INDEX, \
57 IWL_RATE_##rn##M_INDEX, \
58 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 59 IWL_RATE_##np##M_INDEX, \
60 IWL_RATE_##r##M_INDEX_TABLE, \
61 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 62
63/*
64 * Parameter order:
65 * rate, prev rate, next rate, prev tgg rate, next tgg rate
66 *
67 * If there isn't a valid next or previous rate then INV is used which
68 * maps to IWL_RATE_INVALID
69 *
70 */
d9829a67 71const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 72 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
73 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
74 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
75 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 76 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
77 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
78 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
79 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
80 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
81 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
82 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
83 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 84};
85
bb8c093b 86/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 87#define IWL_EVT_DISABLE (0)
88#define IWL_EVT_DISABLE_SIZE (1532/32)
89
90/**
bb8c093b 91 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 92 *
93 * Disable an event by writing "1"s into "disable"
94 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
95 * Default values of 0 enable uCode events to be logged.
96 * Use for only special debugging. This function is just a placeholder as-is,
97 * you'll need to provide the special bits! ...
98 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 99void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 100{
b481de9c
ZY		 101 int i;
102 u32 base; /* SRAM address of event log header */
103 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
104 u32 array_size; /* # of u32 entries in array */
105 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
106 0x00000000, /* 31 - 0 Event id numbers */
107 0x00000000, /* 63 - 32 */
108 0x00000000, /* 95 - 64 */
109 0x00000000, /* 127 - 96 */
110 0x00000000, /* 159 - 128 */
111 0x00000000, /* 191 - 160 */
112 0x00000000, /* 223 - 192 */
113 0x00000000, /* 255 - 224 */
114 0x00000000, /* 287 - 256 */
115 0x00000000, /* 319 - 288 */
116 0x00000000, /* 351 - 320 */
117 0x00000000, /* 383 - 352 */
118 0x00000000, /* 415 - 384 */
119 0x00000000, /* 447 - 416 */
120 0x00000000, /* 479 - 448 */
121 0x00000000, /* 511 - 480 */
122 0x00000000, /* 543 - 512 */
123 0x00000000, /* 575 - 544 */
124 0x00000000, /* 607 - 576 */
125 0x00000000, /* 639 - 608 */
126 0x00000000, /* 671 - 640 */
127 0x00000000, /* 703 - 672 */
128 0x00000000, /* 735 - 704 */
129 0x00000000, /* 767 - 736 */
130 0x00000000, /* 799 - 768 */
131 0x00000000, /* 831 - 800 */
132 0x00000000, /* 863 - 832 */
133 0x00000000, /* 895 - 864 */
134 0x00000000, /* 927 - 896 */
135 0x00000000, /* 959 - 928 */
136 0x00000000, /* 991 - 960 */
137 0x00000000, /* 1023 - 992 */
138 0x00000000, /* 1055 - 1024 */
139 0x00000000, /* 1087 - 1056 */
140 0x00000000, /* 1119 - 1088 */
141 0x00000000, /* 1151 - 1120 */
142 0x00000000, /* 1183 - 1152 */
143 0x00000000, /* 1215 - 1184 */
144 0x00000000, /* 1247 - 1216 */
145 0x00000000, /* 1279 - 1248 */
146 0x00000000, /* 1311 - 1280 */
147 0x00000000, /* 1343 - 1312 */
148 0x00000000, /* 1375 - 1344 */
149 0x00000000, /* 1407 - 1376 */
150 0x00000000, /* 1439 - 1408 */
151 0x00000000, /* 1471 - 1440 */
152 0x00000000, /* 1503 - 1472 */
153 };
154
155 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 156 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 157 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 158 return;
159 }
160
5d49f498
AK		 161 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
162 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 163
164 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 165 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 166 disable_ptr);
b481de9c 167 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 168 iwl_write_targ_mem(priv,
af7cca2a
TW		 169 disable_ptr + (i * sizeof(u32)),
170 evt_disable[i]);
b481de9c 171
b481de9c 172 } else {
e1623446
TW		 173 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
174 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
175 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 176 disable_ptr, array_size);
177 }
178
179}
180
17744ff6
TW		 181static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
182{
183 int idx;
184
185 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
186 if (iwl3945_rates[idx].plcp == plcp)
187 return idx;
188 return -1;
189}
190
d08853a3 191#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 192#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
193
194static const char *iwl3945_get_tx_fail_reason(u32 status)
195{
196 switch (status & TX_STATUS_MSK) {
197 case TX_STATUS_SUCCESS:
198 return "SUCCESS";
199 TX_STATUS_ENTRY(SHORT_LIMIT);
200 TX_STATUS_ENTRY(LONG_LIMIT);
201 TX_STATUS_ENTRY(FIFO_UNDERRUN);
202 TX_STATUS_ENTRY(MGMNT_ABORT);
203 TX_STATUS_ENTRY(NEXT_FRAG);
204 TX_STATUS_ENTRY(LIFE_EXPIRE);
205 TX_STATUS_ENTRY(DEST_PS);
206 TX_STATUS_ENTRY(ABORTED);
207 TX_STATUS_ENTRY(BT_RETRY);
208 TX_STATUS_ENTRY(STA_INVALID);
209 TX_STATUS_ENTRY(FRAG_DROPPED);
210 TX_STATUS_ENTRY(TID_DISABLE);
211 TX_STATUS_ENTRY(FRAME_FLUSHED);
212 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
213 TX_STATUS_ENTRY(TX_LOCKED);
214 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
215 }
216
217 return "UNKNOWN";
218}
219#else
220static inline const char *iwl3945_get_tx_fail_reason(u32 status)
221{
222 return "";
223}
224#endif
225
e6a9854b
JB		 226/*
227 * get ieee prev rate from rate scale table.
228 * for A and B mode we need to overright prev
229 * value
230 */
4a8a4322 231int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 232{
233 int next_rate = iwl3945_get_prev_ieee_rate(rate);
234
235 switch (priv->band) {
236 case IEEE80211_BAND_5GHZ:
237 if (rate == IWL_RATE_12M_INDEX)
238 next_rate = IWL_RATE_9M_INDEX;
239 else if (rate == IWL_RATE_6M_INDEX)
240 next_rate = IWL_RATE_6M_INDEX;
241 break;
7262796a
AM		 242 case IEEE80211_BAND_2GHZ:
243 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 244 iwl_is_associated(priv)) {
7262796a
AM		 245 if (rate == IWL_RATE_11M_INDEX)
246 next_rate = IWL_RATE_5M_INDEX;
247 }
e6a9854b 248 break;
7262796a 249
e6a9854b
JB		 250 default:
251 break;
252 }
253
254 return next_rate;
255}
256
91c066f2
TW		 257
258/**
259 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
260 *
261 * When FW advances 'R' index, all entries between old and new 'R' index
262 * need to be reclaimed. As result, some free space forms. If there is
263 * enough free space (> low mark), wake the stack that feeds us.
264 */
4a8a4322 265static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 266 int txq_id, int index)
267{
188cf6c7 268 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 269 struct iwl_queue *q = &txq->q;
dbb6654c 270 struct iwl_tx_info *tx_info;
91c066f2
TW		 271
272 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
273
274 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
275 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
276
277 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 278 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 279 tx_info->skb[0] = NULL;
7aaa1d79 280 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 281 }
282
d20b3c65 283 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 284 (txq_id != IWL_CMD_QUEUE_NUM) &&
285 priv->mac80211_registered)
e4e72fb4 286 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 287}
288
289/**
290 * iwl3945_rx_reply_tx - Handle Tx response
291 */
4a8a4322 292static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 293 struct iwl_rx_mem_buffer *rxb)
91c066f2 294{
3d24a9f7 295 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 296 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
297 int txq_id = SEQ_TO_QUEUE(sequence);
298 int index = SEQ_TO_INDEX(sequence);
188cf6c7 299 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 300 struct ieee80211_tx_info *info;
91c066f2
TW		 301 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
302 u32 status = le32_to_cpu(tx_resp->status);
303 int rate_idx;
74221d07 304 int fail;
91c066f2 305
625a381a 306 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 307 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 308 "is out of range [0-%d] %d %d\n", txq_id,
309 index, txq->q.n_bd, txq->q.write_ptr,
310 txq->q.read_ptr);
311 return;
312 }
313
e039fa4a 314 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 315 ieee80211_tx_info_clear_status(info);
316
317 /* Fill the MRR chain with some info about on-chip retransmissions */
318 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
319 if (info->band == IEEE80211_BAND_5GHZ)
320 rate_idx -= IWL_FIRST_OFDM_RATE;
321
322 fail = tx_resp->failure_frame;
74221d07
AM		 323
324 info->status.rates[0].idx = rate_idx;
325 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 326
91c066f2 327 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 328 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
329 IEEE80211_TX_STAT_ACK : 0;
91c066f2 330
e1623446 331 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 332 txq_id, iwl3945_get_tx_fail_reason(status), status,
333 tx_resp->rate, tx_resp->failure_frame);
334
e1623446 335 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 336 iwl3945_tx_queue_reclaim(priv, txq_id, index);
337
338 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 339 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 340}
341
342
343
b481de9c
ZY		 344/*****************************************************************************
345 *
346 * Intel PRO/Wireless 3945ABG/BG Network Connection
347 *
348 * RX handler implementations
349 *
b481de9c
ZY		 350 *****************************************************************************/
351
4a8a4322 352void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 353{
3d24a9f7 354 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
e1623446 355 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 356 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 357 le32_to_cpu(pkt->len));
358
f2c7e521 359 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 360
ab53d8af
MA		 361 iwl3945_led_background(priv);
362
b481de9c
ZY		 363 priv->last_statistics_time = jiffies;
364}
365
17744ff6
TW		 366/******************************************************************************
367 *
368 * Misc. internal state and helper functions
369 *
370 ******************************************************************************/
d08853a3 371#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 372
373/**
374 * iwl3945_report_frame - dump frame to syslog during debug sessions
375 *
376 * You may hack this function to show different aspects of received frames,
377 * including selective frame dumps.
378 * group100 parameter selects whether to show 1 out of 100 good frames.
379 */
d08853a3 380static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 381 struct iwl_rx_packet *pkt,
17744ff6
TW		 382 struct ieee80211_hdr *header, int group100)
383{
384 u32 to_us;
385 u32 print_summary = 0;
386 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
387 u32 hundred = 0;
388 u32 dataframe = 0;
fd7c8a40 389 __le16 fc;
17744ff6
TW		 390 u16 seq_ctl;
391 u16 channel;
392 u16 phy_flags;
393 u16 length;
394 u16 status;
395 u16 bcn_tmr;
396 u32 tsf_low;
397 u64 tsf;
398 u8 rssi;
399 u8 agc;
400 u16 sig_avg;
401 u16 noise_diff;
402 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
403 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
404 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
405 u8 *data = IWL_RX_DATA(pkt);
406
407 /* MAC header */
fd7c8a40 408 fc = header->frame_control;
17744ff6
TW		 409 seq_ctl = le16_to_cpu(header->seq_ctrl);
410
411 /* metadata */
412 channel = le16_to_cpu(rx_hdr->channel);
413 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
414 length = le16_to_cpu(rx_hdr->len);
415
416 /* end-of-frame status and timestamp */
417 status = le32_to_cpu(rx_end->status);
418 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
419 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
420 tsf = le64_to_cpu(rx_end->timestamp);
421
422 /* signal statistics */
423 rssi = rx_stats->rssi;
424 agc = rx_stats->agc;
425 sig_avg = le16_to_cpu(rx_stats->sig_avg);
426 noise_diff = le16_to_cpu(rx_stats->noise_diff);
427
428 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
429
430 /* if data frame is to us and all is good,
431 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 432 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
433 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 434 dataframe = 1;
435 if (!group100)
436 print_summary = 1; /* print each frame */
437 else if (priv->framecnt_to_us < 100) {
438 priv->framecnt_to_us++;
439 print_summary = 0;
440 } else {
441 priv->framecnt_to_us = 0;
442 print_summary = 1;
443 hundred = 1;
444 }
445 } else {
446 /* print summary for all other frames */
447 print_summary = 1;
448 }
449
450 if (print_summary) {
451 char *title;
0ff1cca0 452 int rate;
17744ff6
TW		 453
454 if (hundred)
455 title = "100Frames";
fd7c8a40 456 else if (ieee80211_has_retry(fc))
17744ff6 457 title = "Retry";
fd7c8a40 458 else if (ieee80211_is_assoc_resp(fc))
17744ff6 459 title = "AscRsp";
fd7c8a40 460 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 461 title = "RasRsp";
fd7c8a40 462 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 463 title = "PrbRsp";
464 print_dump = 1; /* dump frame contents */
465 } else if (ieee80211_is_beacon(fc)) {
466 title = "Beacon";
467 print_dump = 1; /* dump frame contents */
468 } else if (ieee80211_is_atim(fc))
469 title = "ATIM";
470 else if (ieee80211_is_auth(fc))
471 title = "Auth";
472 else if (ieee80211_is_deauth(fc))
473 title = "DeAuth";
474 else if (ieee80211_is_disassoc(fc))
475 title = "DisAssoc";
476 else
477 title = "Frame";
478
479 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
480 if (rate == -1)
481 rate = 0;
482 else
483 rate = iwl3945_rates[rate].ieee / 2;
484
485 /* print frame summary.
486 * MAC addresses show just the last byte (for brevity),
487 * but you can hack it to show more, if you'd like to. */
488 if (dataframe)
e1623446 489 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 490 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 491 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 492 length, rssi, channel, rate);
493 else {
494 /* src/dst addresses assume managed mode */
e1623446 495 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 496 "src=0x%02x, rssi=%u, tim=%lu usec, "
497 "phy=0x%02x, chnl=%d\n",
fd7c8a40 498 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 499 header->addr3[5], rssi,
500 tsf_low - priv->scan_start_tsf,
501 phy_flags, channel);
502 }
503 }
504 if (print_dump)
40b8ec0b 505 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 506}
d08853a3
SO		 507
508static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
509 struct iwl_rx_packet *pkt,
510 struct ieee80211_hdr *header, int group100)
511{
512 if (priv->debug_level & IWL_DL_RX)
513 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
514}
515
17744ff6 516#else
4a8a4322 517static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 518 struct iwl_rx_packet *pkt,
17744ff6
TW		 519 struct ieee80211_hdr *header, int group100)
520{
521}
522#endif
523
4bd9b4f3 524/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 525static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 526 struct ieee80211_hdr *header)
527{
528 /* Filter incoming packets to determine if they are targeted toward
529 * this network, discarding packets coming from ourselves */
530 switch (priv->iw_mode) {
05c914fe 531 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 532 /* packets to our IBSS update information */
533 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 534 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 535 /* packets to our IBSS update information */
536 return !compare_ether_addr(header->addr2, priv->bssid);
537 default:
538 return 1;
539 }
540}
17744ff6 541
4a8a4322 542static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 543 struct iwl_rx_mem_buffer *rxb,
12342c47 544 struct ieee80211_rx_status *stats)
b481de9c 545{
3d24a9f7 546 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
5c8df2d5 547#ifdef CONFIG_IWLWIFI_LEDS
4bd9b4f3 548 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 549#endif
bb8c093b
CH		 550 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
551 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 552 short len = le16_to_cpu(rx_hdr->len);
553
554 /* We received data from the HW, so stop the watchdog */
3d24a9f7 555 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
e1623446 556 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 557 return;
558 }
559
560 /* We only process data packets if the interface is open */
561 if (unlikely(!priv->is_open)) {
e1623446
TW		 562 IWL_DEBUG_DROP_LIMIT(priv,
563 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 564 return;
565 }
b481de9c
ZY		 566
567 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
568 /* Set the size of the skb to the size of the frame */
569 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
570
9c74d9fb 571 if (!iwl3945_mod_params.sw_crypto)
8ccde88a
SO		 572 iwl_set_decrypted_flag(priv,
573 (struct ieee80211_hdr *)rxb->skb->data,
b481de9c
ZY		 574 le32_to_cpu(rx_end->status), stats);
575
5c8df2d5 576#ifdef CONFIG_IWLWIFI_LEDS
4bd9b4f3 577 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 578 priv->rxtxpackets += len;
579#endif
b481de9c
ZY		 580 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
581 rxb->skb = NULL;
582}
583
7878a5a4
MA		 584#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
585
4a8a4322 586static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 587 struct iwl_rx_mem_buffer *rxb)
b481de9c 588{
17744ff6
TW		 589 struct ieee80211_hdr *header;
590 struct ieee80211_rx_status rx_status;
3d24a9f7 591 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 592 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
593 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
594 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 595 int snr;
b481de9c
ZY		 596 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
597 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 598 u8 network_packet;
17744ff6 599
17744ff6
TW		 600 rx_status.flag = 0;
601 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 602 rx_status.freq =
c0186078 603 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 604 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
605 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
606
607 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 608 if (rx_status.band == IEEE80211_BAND_5GHZ)
609 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 610
6f0a2c4d
BR		 611 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
612 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
613
614 /* set the preamble flag if appropriate */
615 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
616 rx_status.flag |= RX_FLAG_SHORTPRE;
617
b481de9c 618 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 619 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
620 rx_stats->phy_count);
b481de9c
ZY		 621 return;
622 }
623
624 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
625 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 626 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 627 return;
628 }
629
56decd3c 630
b481de9c
ZY		 631
632 /* Convert 3945's rssi indicator to dBm */
250bdd21 633 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 634
635 /* Set default noise value to -127 */
636 if (priv->last_rx_noise == 0)
637 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
638
639 /* 3945 provides noise info for OFDM frames only.
640 * sig_avg and noise_diff are measured by the 3945's digital signal
641 * processor (DSP), and indicate linear levels of signal level and
642 * distortion/noise within the packet preamble after
643 * automatic gain control (AGC). sig_avg should stay fairly
644 * constant if the radio's AGC is working well.
645 * Since these values are linear (not dB or dBm), linear
646 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
647 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
648 * to obtain noise level in dBm.
17744ff6 649 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 650 if (rx_stats_noise_diff) {
651 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 652 rx_status.noise = rx_status.signal -
17744ff6 653 iwl3945_calc_db_from_ratio(snr);
566bfe5a 654 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 655 rx_status.noise);
b481de9c
ZY		 656
657 /* If noise info not available, calculate signal quality indicator (%)
658 * using just the dBm signal level. */
659 } else {
17744ff6 660 rx_status.noise = priv->last_rx_noise;
566bfe5a 661 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 662 }
663
664
e1623446 665 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 666 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 667 rx_stats_sig_avg, rx_stats_noise_diff);
668
b481de9c
ZY		 669 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
670
bb8c093b 671 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 672
e1623446 673 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
17744ff6
TW		 674 network_packet ? '*' : ' ',
675 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 676 rx_status.signal, rx_status.signal,
677 rx_status.noise, rx_status.rate_idx);
b481de9c 678
d08853a3
SO		 679 /* Set "1" to report good data frames in groups of 100 */
680 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 681
682 if (network_packet) {
683 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
684 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 685 priv->last_rx_rssi = rx_status.signal;
17744ff6 686 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 687 }
688
12e5e22d 689 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 690}
691
7aaa1d79
SO		 692int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
693 struct iwl_tx_queue *txq,
694 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 695{
696 int count;
7aaa1d79 697 struct iwl_queue *q;
59606ffa 698 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 699
700 q = &txq->q;
59606ffa
SO		 701 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
702 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 703
704 if (reset)
705 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 706
707 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 708
709 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 710 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 711 NUM_TFD_CHUNKS);
712 return -EINVAL;
713 }
714
dbb6654c
WT		 715 tfd->tbs[count].addr = cpu_to_le32(addr);
716 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 717
718 count++;
719
720 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
721 TFD_CTL_PAD_SET(pad));
722
723 return 0;
724}
725
726/**
bb8c093b 727 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 728 *
729 * Does NOT advance any indexes
730 */
7aaa1d79 731void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 732{
59606ffa 733 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 734 int index = txq->q.read_ptr;
735 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 736 struct pci_dev *dev = priv->pci_dev;
737 int i;
738 int counter;
739
b481de9c 740 /* sanity check */
dbb6654c 741 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 742 if (counter > NUM_TFD_CHUNKS) {
15b1687c 743 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 744 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 745 return;
b481de9c
ZY		 746 }
747
fd9377ee
RC		 748 /* Unmap tx_cmd */
749 if (counter)
750 pci_unmap_single(dev,
751 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
752 pci_unmap_len(&txq->cmd[index]->meta, len),
753 PCI_DMA_TODEVICE);
754
b481de9c
ZY		 755 /* unmap chunks if any */
756
757 for (i = 1; i < counter; i++) {
dbb6654c
WT		 758 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
759 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 760 if (txq->txb[txq->q.read_ptr].skb[0]) {
761 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
762 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 763 /* Can be called from interrupt context */
764 dev_kfree_skb_any(skb);
fc4b6853 765 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 766 }
767 }
768 }
7aaa1d79 769 return ;
b481de9c
ZY		 770}
771
b481de9c 772/**
bb8c093b 773 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 774 *
775*/
c2d79b48 776void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
e039fa4a 777 struct ieee80211_tx_info *info,
b481de9c
ZY		 778 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
779{
e039fa4a 780 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 781 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 782 u16 rate_mask;
783 int rate;
784 u8 rts_retry_limit;
785 u8 data_retry_limit;
786 __le32 tx_flags;
fd7c8a40 787 __le16 fc = hdr->frame_control;
c2d79b48 788 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 789
bb8c093b 790 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 791 tx_flags = tx->tx_flags;
b481de9c
ZY		 792
793 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 794 * in this running context */
b481de9c
ZY		 795 rate_mask = IWL_RATES_MASK;
796
b481de9c
ZY		 797 if (tx_id >= IWL_CMD_QUEUE_NUM)
798 rts_retry_limit = 3;
799 else
800 rts_retry_limit = 7;
801
fd7c8a40 802 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 803 data_retry_limit = 3;
804 if (data_retry_limit < rts_retry_limit)
805 rts_retry_limit = data_retry_limit;
806 } else
807 data_retry_limit = IWL_DEFAULT_TX_RETRY;
808
809 if (priv->data_retry_limit != -1)
810 data_retry_limit = priv->data_retry_limit;
811
fd7c8a40
HH		 812 if (ieee80211_is_mgmt(fc)) {
813 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
814 case cpu_to_le16(IEEE80211_STYPE_AUTH):
815 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
816 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
817 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 818 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
819 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
820 tx_flags |= TX_CMD_FLG_CTS_MSK;
821 }
822 break;
823 default:
824 break;
825 }
826 }
827
c2d79b48
WT		 828 tx->rts_retry_limit = rts_retry_limit;
829 tx->data_retry_limit = data_retry_limit;
830 tx->rate = rate;
831 tx->tx_flags = tx_flags;
b481de9c
ZY		 832
833 /* OFDM */
c2d79b48 834 tx->supp_rates[0] =
14577f23 835 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 836
837 /* CCK */
c2d79b48 838 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c 839
e1623446 840 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 841 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 842 tx->rate, le32_to_cpu(tx->tx_flags),
843 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 844}
845
4a8a4322 846u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 847{
848 unsigned long flags_spin;
c587de0b 849 struct iwl_station_entry *station;
b481de9c
ZY		 850
851 if (sta_id == IWL_INVALID_STATION)
852 return IWL_INVALID_STATION;
853
854 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 855 station = &priv->stations[sta_id];
b481de9c
ZY		 856
857 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
858 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 859 station->sta.mode = STA_CONTROL_MODIFY_MSK;
860
861 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
862
c587de0b 863 iwl_send_add_sta(priv, &station->sta, flags);
e1623446 864 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 865 sta_id, tx_rate);
866 return sta_id;
867}
868
854682ed 869static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 870{
854682ed 871 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 872 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 873 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 874 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
875 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 876
5d49f498 877 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 878 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
879 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 880 }
b481de9c 881 } else {
5d49f498 882 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 883 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
884 ~APMG_PS_CTRL_MSK_PWR_SRC);
885
5d49f498 886 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 887 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
888 }
b481de9c 889
a8b50a0a 890 return 0;
b481de9c
ZY		 891}
892
4a8a4322 893static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 894{
5d49f498 895 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 896 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 897 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
898 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 899 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
900 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
901 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
902 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
903 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
904 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
905 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
906 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 907
908 /* fake read to flush all prev I/O */
5d49f498 909 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 910
b481de9c
ZY		 911 return 0;
912}
913
4a8a4322 914static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 915{
b481de9c
ZY		 916
917 /* bypass mode */
5d49f498 918 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 919
920 /* RA 0 is active */
5d49f498 921 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 922
923 /* all 6 fifo are active */
5d49f498 924 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 925
5d49f498
AK		 926 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
927 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
928 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
929 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 930
5d49f498 931 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 932 priv->shared_phys);
b481de9c 933
5d49f498 934 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 935 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
936 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
937 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
938 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
939 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
940 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
941 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 942
b481de9c
ZY		 943
944 return 0;
945}
946
947/**
948 * iwl3945_txq_ctx_reset - Reset TX queue context
949 *
950 * Destroys all DMA structures and initialize them again
951 */
4a8a4322 952static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 953{
954 int rc;
955 int txq_id, slots_num;
956
bb8c093b 957 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 958
959 /* Tx CMD queue */
960 rc = iwl3945_tx_reset(priv);
961 if (rc)
962 goto error;
963
964 /* Tx queue(s) */
21c02a1a 965 for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 966 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
967 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 968 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
969 txq_id);
b481de9c 970 if (rc) {
15b1687c 971 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 972 goto error;
973 }
974 }
975
976 return rc;
977
978 error:
bb8c093b 979 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 980 return rc;
981}
982
01ec616d 983static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 984{
a8b50a0a 985 int ret;
b481de9c 986
d25aabb0 987 iwl_power_initialize(priv);
b481de9c 988
5d49f498 989 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 990 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
991
992 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
993 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
994 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 995
01ec616d
KA		 996 /* set "initialization complete" bit to move adapter
997 * D0U* --> D0A* state */
5d49f498 998 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d 999
ddcb5c78 1000 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
01ec616d
KA		 1001 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1002 if (ret < 0) {
e1623446 1003 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
01ec616d 1004 goto out;
b481de9c
ZY		 1005 }
1006
01ec616d
KA		 1007 /* enable DMA */
1008 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1009 APMG_CLK_VAL_BSM_CLK_RQT);
1010
b481de9c 1011 udelay(20);
01ec616d
KA		 1012
1013 /* disable L1-Active */
5d49f498 1014 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1015 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1016
01ec616d
KA		 1017out:
1018 return ret;
1019}
b481de9c 1020
01ec616d
KA		 1021static void iwl3945_nic_config(struct iwl_priv *priv)
1022{
e6148917 1023 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1024 unsigned long flags;
1025 u8 rev_id = 0;
b481de9c 1026
b481de9c
ZY		 1027 spin_lock_irqsave(&priv->lock, flags);
1028
43121432
AK		 1029 /* Determine HW type */
1030 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1031
1032 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1033
b481de9c 1034 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
e1623446 1035 IWL_DEBUG_INFO(priv, "RTP type \n");
b481de9c 1036 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1037 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1038 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1039 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1040 } else {
e1623446 1041 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1042 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1043 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1044 }
1045
e6148917 1046 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1047 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1048 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1049 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1050 } else
e1623446 1051 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1052
e6148917 1053 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1054 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1055 eeprom->board_revision);
5d49f498 1056 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1057 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1058 } else {
e1623446 1059 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1060 eeprom->board_revision);
5d49f498 1061 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1062 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1063 }
1064
e6148917 1065 if (eeprom->almgor_m_version <= 1) {
5d49f498 1066 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1067 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1068 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1069 eeprom->almgor_m_version);
b481de9c 1070 } else {
e1623446 1071 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1072 eeprom->almgor_m_version);
5d49f498 1073 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1074 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1075 }
1076 spin_unlock_irqrestore(&priv->lock, flags);
1077
e6148917 1078 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1079 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1080
e6148917 1081 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1082 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1083}
1084
1085int iwl3945_hw_nic_init(struct iwl_priv *priv)
1086{
01ec616d
KA		 1087 int rc;
1088 unsigned long flags;
1089 struct iwl_rx_queue *rxq = &priv->rxq;
1090
1091 spin_lock_irqsave(&priv->lock, flags);
1092 priv->cfg->ops->lib->apm_ops.init(priv);
1093 spin_unlock_irqrestore(&priv->lock, flags);
1094
854682ed 1095 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1096 if (rc)
854682ed
KA		 1097 return rc;
1098
01ec616d 1099 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1100
1101 /* Allocate the RX queue, or reset if it is already allocated */
1102 if (!rxq->bd) {
51af3d3f 1103 rc = iwl_rx_queue_alloc(priv);
b481de9c 1104 if (rc) {
15b1687c 1105 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1106 return -ENOMEM;
1107 }
1108 } else
df833b1d 1109 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1110
bb8c093b 1111 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1112
1113 iwl3945_rx_init(priv, rxq);
1114
b481de9c
ZY		 1115
1116 /* Look at using this instead:
1117 rxq->need_update = 1;
141c43a3 1118 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1119 */
1120
5d49f498 1121 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1122
1123 rc = iwl3945_txq_ctx_reset(priv);
1124 if (rc)
1125 return rc;
1126
1127 set_bit(STATUS_INIT, &priv->status);
1128
1129 return 0;
1130}
1131
1132/**
bb8c093b 1133 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1134 *
1135 * Destroy all TX DMA queues and structures
1136 */
4a8a4322 1137void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1138{
1139 int txq_id;
1140
1141 /* Tx queues */
21c02a1a 1142 for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++)
3e5d238f
AK		 1143 if (txq_id == IWL_CMD_QUEUE_NUM)
1144 iwl_cmd_queue_free(priv);
1145 else
1146 iwl_tx_queue_free(priv, txq_id);
1147
b481de9c
ZY		 1148}
1149
4a8a4322 1150void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1151{
bddadf86 1152 int txq_id;
b481de9c
ZY		 1153
1154 /* stop SCD */
5d49f498 1155 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1156
1157 /* reset TFD queues */
21c02a1a 1158 for (txq_id = 0; txq_id <= priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1159 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1160 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1161 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1162 1000);
1163 }
1164
bb8c093b 1165 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1166}
1167
01ec616d 1168static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1169{
01ec616d 1170 int ret = 0;
b481de9c
ZY		 1171 unsigned long flags;
1172
1173 spin_lock_irqsave(&priv->lock, flags);
1174
1175 /* set stop master bit */
5d49f498 1176 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1177
01ec616d
KA		 1178 iwl_poll_direct_bit(priv, CSR_RESET,
1179 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1180
01ec616d
KA		 1181 if (ret < 0)
1182 goto out;
b481de9c 1183
01ec616d 1184out:
b481de9c 1185 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 1186 IWL_DEBUG_INFO(priv, "stop master\n");
b481de9c 1187
01ec616d
KA		 1188 return ret;
1189}
1190
1191static void iwl3945_apm_stop(struct iwl_priv *priv)
1192{
1193 unsigned long flags;
1194
1195 iwl3945_apm_stop_master(priv);
1196
1197 spin_lock_irqsave(&priv->lock, flags);
1198
1199 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1200
1201 udelay(10);
1202 /* clear "init complete" move adapter D0A* --> D0U state */
1203 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1204 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1205}
1206
e52119c5 1207static int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c 1208{
01ec616d 1209 iwl3945_apm_stop_master(priv);
b481de9c 1210
b481de9c 1211
5d49f498 1212 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
e9414b6b
AM		 1213 udelay(10);
1214
1215 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 1216
5d49f498 1217 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1218 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1219
a8b50a0a
MA		 1220 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1221 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 1222
a8b50a0a
MA		 1223 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1224 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1225 0xFFFFFFFF);
1226
a8b50a0a
MA		 1227 /* enable DMA */
1228 iwl_write_prph(priv, APMG_CLK_EN_REG,
1229 APMG_CLK_VAL_DMA_CLK_RQT |
1230 APMG_CLK_VAL_BSM_CLK_RQT);
1231 udelay(10);
b481de9c 1232
a8b50a0a 1233 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1234 APMG_PS_CTRL_VAL_RESET_REQ);
a8b50a0a
MA		 1235 udelay(5);
1236 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1237 APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c
ZY		 1238
1239 /* Clear the 'host command active' bit... */
1240 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1241
1242 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1243
a8b50a0a 1244 return 0;
b481de9c
ZY		 1245}
1246
1247/**
bb8c093b 1248 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1249 * return index delta into power gain settings table
1250*/
bb8c093b 1251static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1252{
1253 return (new_reading - old_reading) * (-11) / 100;
1254}
1255
1256/**
bb8c093b 1257 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1258 */
bb8c093b 1259static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1260{
3ac7f146 1261 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1262}
1263
4a8a4322 1264int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1265{
5d49f498 1266 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1267}
1268
1269/**
bb8c093b 1270 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1271 * get the current temperature by reading from NIC
1272*/
4a8a4322 1273static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1274{
e6148917 1275 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1276 int temperature;
1277
bb8c093b 1278 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1279
1280 /* driver's okay range is -260 to +25.
1281 * human readable okay range is 0 to +285 */
e1623446 1282 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1283
1284 /* handle insane temp reading */
bb8c093b 1285 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1286 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1287
1288 /* if really really hot(?),
1289 * substitute the 3rd band/group's temp measured at factory */
1290 if (priv->last_temperature > 100)
e6148917 1291 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1292 else /* else use most recent "sane" value from driver */
1293 temperature = priv->last_temperature;
1294 }
1295
1296 return temperature; /* raw, not "human readable" */
1297}
1298
1299/* Adjust Txpower only if temperature variance is greater than threshold.
1300 *
1301 * Both are lower than older versions' 9 degrees */
1302#define IWL_TEMPERATURE_LIMIT_TIMER 6
1303
1304/**
1305 * is_temp_calib_needed - determines if new calibration is needed
1306 *
1307 * records new temperature in tx_mgr->temperature.
1308 * replaces tx_mgr->last_temperature *only* if calib needed
1309 * (assumes caller will actually do the calibration!). */
4a8a4322 1310static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1311{
1312 int temp_diff;
1313
bb8c093b 1314 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1315 temp_diff = priv->temperature - priv->last_temperature;
1316
1317 /* get absolute value */
1318 if (temp_diff < 0) {
e1623446 1319 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1320 temp_diff = -temp_diff;
1321 } else if (temp_diff == 0)
e1623446 1322 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1323 else
e1623446 1324 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1325
1326 /* if we don't need calibration, *don't* update last_temperature */
1327 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1328 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1329 return 0;
1330 }
1331
e1623446 1332 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1333
1334 /* assume that caller will actually do calib ...
1335 * update the "last temperature" value */
1336 priv->last_temperature = priv->temperature;
1337 return 1;
1338}
1339
1340#define IWL_MAX_GAIN_ENTRIES 78
1341#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1342#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1343
1344/* radio and DSP power table, each step is 1/2 dB.
1345 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1346static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1347 {
1348 {251, 127}, /* 2.4 GHz, highest power */
1349 {251, 127},
1350 {251, 127},
1351 {251, 127},
1352 {251, 125},
1353 {251, 110},
1354 {251, 105},
1355 {251, 98},
1356 {187, 125},
1357 {187, 115},
1358 {187, 108},
1359 {187, 99},
1360 {243, 119},
1361 {243, 111},
1362 {243, 105},
1363 {243, 97},
1364 {243, 92},
1365 {211, 106},
1366 {211, 100},
1367 {179, 120},
1368 {179, 113},
1369 {179, 107},
1370 {147, 125},
1371 {147, 119},
1372 {147, 112},
1373 {147, 106},
1374 {147, 101},
1375 {147, 97},
1376 {147, 91},
1377 {115, 107},
1378 {235, 121},
1379 {235, 115},
1380 {235, 109},
1381 {203, 127},
1382 {203, 121},
1383 {203, 115},
1384 {203, 108},
1385 {203, 102},
1386 {203, 96},
1387 {203, 92},
1388 {171, 110},
1389 {171, 104},
1390 {171, 98},
1391 {139, 116},
1392 {227, 125},
1393 {227, 119},
1394 {227, 113},
1395 {227, 107},
1396 {227, 101},
1397 {227, 96},
1398 {195, 113},
1399 {195, 106},
1400 {195, 102},
1401 {195, 95},
1402 {163, 113},
1403 {163, 106},
1404 {163, 102},
1405 {163, 95},
1406 {131, 113},
1407 {131, 106},
1408 {131, 102},
1409 {131, 95},
1410 {99, 113},
1411 {99, 106},
1412 {99, 102},
1413 {99, 95},
1414 {67, 113},
1415 {67, 106},
1416 {67, 102},
1417 {67, 95},
1418 {35, 113},
1419 {35, 106},
1420 {35, 102},
1421 {35, 95},
1422 {3, 113},
1423 {3, 106},
1424 {3, 102},
1425 {3, 95} }, /* 2.4 GHz, lowest power */
1426 {
1427 {251, 127}, /* 5.x GHz, highest power */
1428 {251, 120},
1429 {251, 114},
1430 {219, 119},
1431 {219, 101},
1432 {187, 113},
1433 {187, 102},
1434 {155, 114},
1435 {155, 103},
1436 {123, 117},
1437 {123, 107},
1438 {123, 99},
1439 {123, 92},
1440 {91, 108},
1441 {59, 125},
1442 {59, 118},
1443 {59, 109},
1444 {59, 102},
1445 {59, 96},
1446 {59, 90},
1447 {27, 104},
1448 {27, 98},
1449 {27, 92},
1450 {115, 118},
1451 {115, 111},
1452 {115, 104},
1453 {83, 126},
1454 {83, 121},
1455 {83, 113},
1456 {83, 105},
1457 {83, 99},
1458 {51, 118},
1459 {51, 111},
1460 {51, 104},
1461 {51, 98},
1462 {19, 116},
1463 {19, 109},
1464 {19, 102},
1465 {19, 98},
1466 {19, 93},
1467 {171, 113},
1468 {171, 107},
1469 {171, 99},
1470 {139, 120},
1471 {139, 113},
1472 {139, 107},
1473 {139, 99},
1474 {107, 120},
1475 {107, 113},
1476 {107, 107},
1477 {107, 99},
1478 {75, 120},
1479 {75, 113},
1480 {75, 107},
1481 {75, 99},
1482 {43, 120},
1483 {43, 113},
1484 {43, 107},
1485 {43, 99},
1486 {11, 120},
1487 {11, 113},
1488 {11, 107},
1489 {11, 99},
1490 {131, 107},
1491 {131, 99},
1492 {99, 120},
1493 {99, 113},
1494 {99, 107},
1495 {99, 99},
1496 {67, 120},
1497 {67, 113},
1498 {67, 107},
1499 {67, 99},
1500 {35, 120},
1501 {35, 113},
1502 {35, 107},
1503 {35, 99},
1504 {3, 120} } /* 5.x GHz, lowest power */
1505};
1506
bb8c093b 1507static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1508{
1509 if (index < 0)
1510 return 0;
1511 if (index >= IWL_MAX_GAIN_ENTRIES)
1512 return IWL_MAX_GAIN_ENTRIES - 1;
1513 return (u8) index;
1514}
1515
1516/* Kick off thermal recalibration check every 60 seconds */
1517#define REG_RECALIB_PERIOD (60)
1518
1519/**
bb8c093b 1520 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1521 *
1522 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1523 * or 6 Mbit (OFDM) rates.
1524 */
4a8a4322 1525static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1526 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1527 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1528 int band_index)
1529{
bb8c093b 1530 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1531 s8 power;
1532 u8 power_index;
1533
1534 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1535
1536 /* use this channel group's 6Mbit clipping/saturation pwr,
1537 * but cap at regulatory scan power restriction (set during init
1538 * based on eeprom channel data) for this channel. */
14577f23 1539 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1540
1541 /* further limit to user's max power preference.
1542 * FIXME: Other spectrum management power limitations do not
1543 * seem to apply?? */
62ea9c5b 1544 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1545 scan_power_info->requested_power = power;
1546
1547 /* find difference between new scan *power* and current "normal"
1548 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1549 * current "normal" temperature-compensated Tx power *index* for
1550 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1551 * *index*. */
1552 power_index = ch_info->power_info[rate_index].power_table_index
1553 - (power - ch_info->power_info
14577f23 1554 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1555
1556 /* store reference index that we use when adjusting *all* scan
1557 * powers. So we can accommodate user (all channel) or spectrum
1558 * management (single channel) power changes "between" temperature
1559 * feedback compensation procedures.
1560 * don't force fit this reference index into gain table; it may be a
1561 * negative number. This will help avoid errors when we're at
1562 * the lower bounds (highest gains, for warmest temperatures)
1563 * of the table. */
1564
1565 /* don't exceed table bounds for "real" setting */
bb8c093b 1566 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1567
1568 scan_power_info->power_table_index = power_index;
1569 scan_power_info->tpc.tx_gain =
1570 power_gain_table[band_index][power_index].tx_gain;
1571 scan_power_info->tpc.dsp_atten =
1572 power_gain_table[band_index][power_index].dsp_atten;
1573}
1574
1575/**
75bcfae9 1576 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1577 *
1578 * Configures power settings for all rates for the current channel,
1579 * using values from channel info struct, and send to NIC
1580 */
dfb39e82 1581static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1582{
14577f23 1583 int rate_idx, i;
d20b3c65 1584 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1585 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1586 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1587 };
1588
8318d78a 1589 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1590 ch_info = iwl_get_channel_info(priv,
8318d78a 1591 priv->band,
8ccde88a 1592 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1593 if (!ch_info) {
15b1687c
WT		 1594 IWL_ERR(priv,
1595 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1596 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1597 return -EINVAL;
1598 }
1599
1600 if (!is_channel_valid(ch_info)) {
e1623446 1601 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1602 "non-Tx channel.\n");
1603 return 0;
1604 }
1605
1606 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1607 /* Fill OFDM rate */
1608 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1609 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1610
1611 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1612 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1613
e1623446 1614 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1615 le16_to_cpu(txpower.channel),
1616 txpower.band,
14577f23
MA		 1617 txpower.power[i].tpc.tx_gain,
1618 txpower.power[i].tpc.dsp_atten,
1619 txpower.power[i].rate);
1620 }
1621 /* Fill CCK rates */
1622 for (rate_idx = IWL_FIRST_CCK_RATE;
1623 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1624 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1625 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1626
e1623446 1627 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1628 le16_to_cpu(txpower.channel),
1629 txpower.band,
1630 txpower.power[i].tpc.tx_gain,
1631 txpower.power[i].tpc.dsp_atten,
1632 txpower.power[i].rate);
b481de9c
ZY		 1633 }
1634
518099a8
SO		 1635 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1636 sizeof(struct iwl3945_txpowertable_cmd),
1637 &txpower);
b481de9c
ZY		 1638
1639}
1640
1641/**
bb8c093b 1642 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1643 * @ch_info: Channel to update. Uses power_info.requested_power.
1644 *
1645 * Replace requested_power and base_power_index ch_info fields for
1646 * one channel.
1647 *
1648 * Called if user or spectrum management changes power preferences.
1649 * Takes into account h/w and modulation limitations (clip power).
1650 *
1651 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1652 *
1653 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1654 * properly fill out the scan powers, and actual h/w gain settings,
1655 * and send changes to NIC
1656 */
4a8a4322 1657static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1658 struct iwl_channel_info *ch_info)
b481de9c 1659{
bb8c093b 1660 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1661 int power_changed = 0;
1662 int i;
1663 const s8 *clip_pwrs;
1664 int power;
1665
1666 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1667 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1668
1669 /* Get this channel's rate-to-current-power settings table */
1670 power_info = ch_info->power_info;
1671
1672 /* update OFDM Txpower settings */
14577f23 1673 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1674 i++, ++power_info) {
1675 int delta_idx;
1676
1677 /* limit new power to be no more than h/w capability */
1678 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1679 if (power == power_info->requested_power)
1680 continue;
1681
1682 /* find difference between old and new requested powers,
1683 * update base (non-temp-compensated) power index */
1684 delta_idx = (power - power_info->requested_power) * 2;
1685 power_info->base_power_index -= delta_idx;
1686
1687 /* save new requested power value */
1688 power_info->requested_power = power;
1689
1690 power_changed = 1;
1691 }
1692
1693 /* update CCK Txpower settings, based on OFDM 12M setting ...
1694 * ... all CCK power settings for a given channel are the *same*. */
1695 if (power_changed) {
1696 power =
14577f23 1697 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1698 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1699
bb8c093b 1700 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1701 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1702 power_info->requested_power = power;
1703 power_info->base_power_index =
14577f23 1704 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1705 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1706 ++power_info;
1707 }
1708 }
1709
1710 return 0;
1711}
1712
1713/**
bb8c093b 1714 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1715 *
1716 * NOTE: Returned power limit may be less (but not more) than requested,
1717 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1718 * (no consideration for h/w clipping limitations).
1719 */
d20b3c65 1720static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1721{
1722 s8 max_power;
1723
1724#if 0
1725 /* if we're using TGd limits, use lower of TGd or EEPROM */
1726 if (ch_info->tgd_data.max_power != 0)
1727 max_power = min(ch_info->tgd_data.max_power,
1728 ch_info->eeprom.max_power_avg);
1729
1730 /* else just use EEPROM limits */
1731 else
1732#endif
1733 max_power = ch_info->eeprom.max_power_avg;
1734
1735 return min(max_power, ch_info->max_power_avg);
1736}
1737
1738/**
bb8c093b 1739 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1740 *
1741 * Compensate txpower settings of *all* channels for temperature.
1742 * This only accounts for the difference between current temperature
1743 * and the factory calibration temperatures, and bases the new settings
1744 * on the channel's base_power_index.
1745 *
1746 * If RxOn is "associated", this sends the new Txpower to NIC!
1747 */
4a8a4322 1748static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1749{
d20b3c65 1750 struct iwl_channel_info *ch_info = NULL;
e6148917 1751 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1752 int delta_index;
1753 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1754 u8 a_band;
1755 u8 rate_index;
1756 u8 scan_tbl_index;
1757 u8 i;
1758 int ref_temp;
1759 int temperature = priv->temperature;
1760
1761 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1762 for (i = 0; i < priv->channel_count; i++) {
1763 ch_info = &priv->channel_info[i];
1764 a_band = is_channel_a_band(ch_info);
1765
1766 /* Get this chnlgrp's factory calibration temperature */
e6148917 1767 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1768 temperature;
1769
a96a27f9 1770 /* get power index adjustment based on current and factory
b481de9c 1771 * temps */
bb8c093b 1772 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1773 ref_temp);
1774
1775 /* set tx power value for all rates, OFDM and CCK */
1776 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1777 rate_index++) {
1778 int power_idx =
1779 ch_info->power_info[rate_index].base_power_index;
1780
1781 /* temperature compensate */
1782 power_idx += delta_index;
1783
1784 /* stay within table range */
bb8c093b 1785 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1786 ch_info->power_info[rate_index].
1787 power_table_index = (u8) power_idx;
1788 ch_info->power_info[rate_index].tpc =
1789 power_gain_table[a_band][power_idx];
1790 }
1791
1792 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1793 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1794
1795 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1796 for (scan_tbl_index = 0;
1797 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1798 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1799 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1800 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1801 actual_index, clip_pwrs,
1802 ch_info, a_band);
1803 }
1804 }
1805
1806 /* send Txpower command for current channel to ucode */
75bcfae9 1807 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1808}
1809
4a8a4322 1810int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1811{
d20b3c65 1812 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1813 s8 max_power;
1814 u8 a_band;
1815 u8 i;
1816
62ea9c5b 1817 if (priv->tx_power_user_lmt == power) {
e1623446 1818 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1819 "limit: %ddBm.\n", power);
1820 return 0;
1821 }
1822
e1623446 1823 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1824 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1825
1826 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1827
1828 for (i = 0; i < priv->channel_count; i++) {
1829 ch_info = &priv->channel_info[i];
1830 a_band = is_channel_a_band(ch_info);
1831
1832 /* find minimum power of all user and regulatory constraints
1833 * (does not consider h/w clipping limitations) */
bb8c093b 1834 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1835 max_power = min(power, max_power);
1836 if (max_power != ch_info->curr_txpow) {
1837 ch_info->curr_txpow = max_power;
1838
1839 /* this considers the h/w clipping limitations */
bb8c093b 1840 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1841 }
1842 }
1843
1844 /* update txpower settings for all channels,
1845 * send to NIC if associated. */
1846 is_temp_calib_needed(priv);
bb8c093b 1847 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1848
1849 return 0;
1850}
1851
5bbe233b
AK		 1852static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1853{
1854 int rc = 0;
1855 struct iwl_rx_packet *res = NULL;
1856 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1857 struct iwl_host_cmd cmd = {
1858 .id = REPLY_RXON_ASSOC,
1859 .len = sizeof(rxon_assoc),
1860 .meta.flags = CMD_WANT_SKB,
1861 .data = &rxon_assoc,
1862 };
1863 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1864 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1865
1866 if ((rxon1->flags == rxon2->flags) &&
1867 (rxon1->filter_flags == rxon2->filter_flags) &&
1868 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1869 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1870 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1871 return 0;
1872 }
1873
1874 rxon_assoc.flags = priv->staging_rxon.flags;
1875 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1876 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1877 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1878 rxon_assoc.reserved = 0;
1879
1880 rc = iwl_send_cmd_sync(priv, &cmd);
1881 if (rc)
1882 return rc;
1883
1884 res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
1885 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1886 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1887 rc = -EIO;
1888 }
1889
1890 priv->alloc_rxb_skb--;
1891 dev_kfree_skb_any(cmd.meta.u.skb);
1892
1893 return rc;
1894}
1895
e0158e61
AK		 1896/**
1897 * iwl3945_commit_rxon - commit staging_rxon to hardware
1898 *
1899 * The RXON command in staging_rxon is committed to the hardware and
1900 * the active_rxon structure is updated with the new data. This
1901 * function correctly transitions out of the RXON_ASSOC_MSK state if
1902 * a HW tune is required based on the RXON structure changes.
1903 */
1904static int iwl3945_commit_rxon(struct iwl_priv *priv)
1905{
1906 /* cast away the const for active_rxon in this function */
1907 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1908 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1909 int rc = 0;
1910 bool new_assoc =
1911 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1912
1913 if (!iwl_is_alive(priv))
1914 return -1;
1915
1916 /* always get timestamp with Rx frame */
1917 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1918
1919 /* select antenna */
1920 staging_rxon->flags &=
1921 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1922 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1923
1924 rc = iwl_check_rxon_cmd(priv);
1925 if (rc) {
1926 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1927 return -EINVAL;
1928 }
1929
1930 /* If we don't need to send a full RXON, we can use
1931 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1932 * and other flags for the current radio configuration. */
1933 if (!iwl_full_rxon_required(priv)) {
1934 rc = iwl_send_rxon_assoc(priv);
1935 if (rc) {
1936 IWL_ERR(priv, "Error setting RXON_ASSOC "
1937 "configuration (%d).\n", rc);
1938 return rc;
1939 }
1940
1941 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1942
1943 return 0;
1944 }
1945
1946 /* If we are currently associated and the new config requires
1947 * an RXON_ASSOC and the new config wants the associated mask enabled,
1948 * we must clear the associated from the active configuration
1949 * before we apply the new config */
1950 if (iwl_is_associated(priv) && new_assoc) {
1951 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1952 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1953
1954 /*
1955 * reserved4 and 5 could have been filled by the iwlcore code.
1956 * Let's clear them before pushing to the 3945.
1957 */
1958 active_rxon->reserved4 = 0;
1959 active_rxon->reserved5 = 0;
1960 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1961 sizeof(struct iwl3945_rxon_cmd),
1962 &priv->active_rxon);
1963
1964 /* If the mask clearing failed then we set
1965 * active_rxon back to what it was previously */
1966 if (rc) {
1967 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1968 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1969 "configuration (%d).\n", rc);
1970 return rc;
1971 }
1972 }
1973
1974 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1975 "* with%s RXON_FILTER_ASSOC_MSK\n"
1976 "* channel = %d\n"
1977 "* bssid = %pM\n",
1978 (new_assoc ? "" : "out"),
1979 le16_to_cpu(staging_rxon->channel),
1980 staging_rxon->bssid_addr);
1981
1982 /*
1983 * reserved4 and 5 could have been filled by the iwlcore code.
1984 * Let's clear them before pushing to the 3945.
1985 */
1986 staging_rxon->reserved4 = 0;
1987 staging_rxon->reserved5 = 0;
1988
1989 iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
1990
1991 /* Apply the new configuration */
1992 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1993 sizeof(struct iwl3945_rxon_cmd),
1994 staging_rxon);
1995 if (rc) {
1996 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1997 return rc;
1998 }
1999
2000 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
2001
c587de0b 2002 iwl_clear_stations_table(priv);
e0158e61
AK		 2003
2004 /* If we issue a new RXON command which required a tune then we must
2005 * send a new TXPOWER command or we won't be able to Tx any frames */
2006 rc = priv->cfg->ops->lib->send_tx_power(priv);
2007 if (rc) {
2008 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
2009 return rc;
2010 }
2011
2012 /* Add the broadcast address so we can send broadcast frames */
c587de0b 2013 if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
e0158e61
AK		 2014 IWL_INVALID_STATION) {
2015 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
2016 return -EIO;
2017 }
2018
2019 /* If we have set the ASSOC_MSK and we are in BSS mode then
2020 * add the IWL_AP_ID to the station rate table */
2021 if (iwl_is_associated(priv) &&
2022 (priv->iw_mode == NL80211_IFTYPE_STATION))
c587de0b
TW		 2023 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
2024 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
e0158e61
AK		 2025 IWL_ERR(priv, "Error adding AP address for transmit\n");
2026 return -EIO;
2027 }
2028
2029 /* Init the hardware's rate fallback order based on the band */
2030 rc = iwl3945_init_hw_rate_table(priv);
2031 if (rc) {
2032 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
2033 return -EIO;
2034 }
2035
2036 return 0;
2037}
2038
b481de9c 2039/* will add 3945 channel switch cmd handling later */
4a8a4322 2040int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2041{
2042 return 0;
2043}
2044
2045/**
2046 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
2047 *
2048 * -- reset periodic timer
2049 * -- see if temp has changed enough to warrant re-calibration ... if so:
2050 * -- correct coeffs for temp (can reset temp timer)
2051 * -- save this temp as "last",
2052 * -- send new set of gain settings to NIC
2053 * NOTE: This should continue working, even when we're not associated,
2054 * so we can keep our internal table of scan powers current. */
4a8a4322 2055void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 2056{
2057 /* This will kick in the "brute force"
bb8c093b 2058 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2059 if (!is_temp_calib_needed(priv))
2060 goto reschedule;
2061
2062 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2063 * This is based *only* on current temperature,
2064 * ignoring any previous power measurements */
bb8c093b 2065 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2066
2067 reschedule:
2068 queue_delayed_work(priv->workqueue,
2069 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2070}
2071
416e1438 2072static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2073{
4a8a4322 2074 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2075 thermal_periodic.work);
2076
2077 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2078 return;
2079
2080 mutex_lock(&priv->mutex);
2081 iwl3945_reg_txpower_periodic(priv);
2082 mutex_unlock(&priv->mutex);
2083}
2084
2085/**
bb8c093b 2086 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2087 * for the channel.
2088 *
2089 * This function is used when initializing channel-info structs.
2090 *
2091 * NOTE: These channel groups do *NOT* match the bands above!
2092 * These channel groups are based on factory-tested channels;
2093 * on A-band, EEPROM's "group frequency" entries represent the top
2094 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2095 */
4a8a4322 2096static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2097 const struct iwl_channel_info *ch_info)
b481de9c 2098{
e6148917
SO		 2099 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2100 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2101 u8 group;
2102 u16 group_index = 0; /* based on factory calib frequencies */
2103 u8 grp_channel;
2104
2105 /* Find the group index for the channel ... don't use index 1(?) */
2106 if (is_channel_a_band(ch_info)) {
2107 for (group = 1; group < 5; group++) {
2108 grp_channel = ch_grp[group].group_channel;
2109 if (ch_info->channel <= grp_channel) {
2110 group_index = group;
2111 break;
2112 }
2113 }
2114 /* group 4 has a few channels *above* its factory cal freq */
2115 if (group == 5)
2116 group_index = 4;
2117 } else
2118 group_index = 0; /* 2.4 GHz, group 0 */
2119
e1623446 2120 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2121 group_index);
2122 return group_index;
2123}
2124
2125/**
bb8c093b 2126 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2127 *
2128 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2129 * into radio/DSP gain settings table for requested power.
2130 */
4a8a4322 2131static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2132 s8 requested_power,
2133 s32 setting_index, s32 *new_index)
2134{
bb8c093b 2135 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2136 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2137 s32 index0, index1;
2138 s32 power = 2 * requested_power;
2139 s32 i;
bb8c093b 2140 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2141 s32 gains0, gains1;
2142 s32 res;
2143 s32 denominator;
2144
e6148917 2145 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2146 samples = chnl_grp->samples;
2147 for (i = 0; i < 5; i++) {
2148 if (power == samples[i].power) {
2149 *new_index = samples[i].gain_index;
2150 return 0;
2151 }
2152 }
2153
2154 if (power > samples[1].power) {
2155 index0 = 0;
2156 index1 = 1;
2157 } else if (power > samples[2].power) {
2158 index0 = 1;
2159 index1 = 2;
2160 } else if (power > samples[3].power) {
2161 index0 = 2;
2162 index1 = 3;
2163 } else {
2164 index0 = 3;
2165 index1 = 4;
2166 }
2167
2168 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2169 if (denominator == 0)
2170 return -EINVAL;
2171 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2172 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2173 res = gains0 + (gains1 - gains0) *
2174 ((s32) power - (s32) samples[index0].power) / denominator +
2175 (1 << 18);
2176 *new_index = res >> 19;
2177 return 0;
2178}
2179
4a8a4322 2180static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2181{
2182 u32 i;
2183 s32 rate_index;
e6148917 2184 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2185 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2186
e1623446 2187 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2188
2189 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2190 s8 *clip_pwrs; /* table of power levels for each rate */
2191 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2192 group = &eeprom->groups[i];
b481de9c
ZY		 2193
2194 /* sanity check on factory saturation power value */
2195 if (group->saturation_power < 40) {
39aadf8c 2196 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2197 "less than minimum expected 40\n",
2198 group->saturation_power);
2199 return;
2200 }
2201
2202 /*
2203 * Derive requested power levels for each rate, based on
2204 * hardware capabilities (saturation power for band).
2205 * Basic value is 3dB down from saturation, with further
2206 * power reductions for highest 3 data rates. These
2207 * backoffs provide headroom for high rate modulation
2208 * power peaks, without too much distortion (clipping).
2209 */
2210 /* we'll fill in this array with h/w max power levels */
f2c7e521 2211 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2212
2213 /* divide factory saturation power by 2 to find -3dB level */
2214 satur_pwr = (s8) (group->saturation_power >> 1);
2215
2216 /* fill in channel group's nominal powers for each rate */
2217 for (rate_index = 0;
2218 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2219 switch (rate_index) {
14577f23 2220 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2221 if (i == 0) /* B/G */
2222 *clip_pwrs = satur_pwr;
2223 else /* A */
2224 *clip_pwrs = satur_pwr - 5;
2225 break;
14577f23 2226 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2227 if (i == 0)
2228 *clip_pwrs = satur_pwr - 7;
2229 else
2230 *clip_pwrs = satur_pwr - 10;
2231 break;
14577f23 2232 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2233 if (i == 0)
2234 *clip_pwrs = satur_pwr - 9;
2235 else
2236 *clip_pwrs = satur_pwr - 12;
2237 break;
2238 default:
2239 *clip_pwrs = satur_pwr;
2240 break;
2241 }
2242 }
2243 }
2244}
2245
2246/**
2247 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2248 *
2249 * Second pass (during init) to set up priv->channel_info
2250 *
2251 * Set up Tx-power settings in our channel info database for each VALID
2252 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2253 * and current temperature.
2254 *
2255 * Since this is based on current temperature (at init time), these values may
2256 * not be valid for very long, but it gives us a starting/default point,
2257 * and allows us to active (i.e. using Tx) scan.
2258 *
2259 * This does *not* write values to NIC, just sets up our internal table.
2260 */
4a8a4322 2261int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2262{
d20b3c65 2263 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2264 struct iwl3945_channel_power_info *pwr_info;
e6148917 2265 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2266 int delta_index;
2267 u8 rate_index;
2268 u8 scan_tbl_index;
2269 const s8 *clip_pwrs; /* array of power levels for each rate */
2270 u8 gain, dsp_atten;
2271 s8 power;
2272 u8 pwr_index, base_pwr_index, a_band;
2273 u8 i;
2274 int temperature;
2275
2276 /* save temperature reference,
2277 * so we can determine next time to calibrate */
bb8c093b 2278 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2279 priv->last_temperature = temperature;
2280
bb8c093b 2281 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2282
2283 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2284 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2285 i++, ch_info++) {
2286 a_band = is_channel_a_band(ch_info);
2287 if (!is_channel_valid(ch_info))
2288 continue;
2289
2290 /* find this channel's channel group (*not* "band") index */
2291 ch_info->group_index =
bb8c093b 2292 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2293
2294 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2295 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2296
2297 /* calculate power index *adjustment* value according to
2298 * diff between current temperature and factory temperature */
bb8c093b 2299 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2300 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2301 temperature);
2302
e1623446 2303 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2304 ch_info->channel, delta_index, temperature +
2305 IWL_TEMP_CONVERT);
2306
2307 /* set tx power value for all OFDM rates */
2308 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2309 rate_index++) {
25a4ccea 2310 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2311 int rc;
2312
2313 /* use channel group's clip-power table,
2314 * but don't exceed channel's max power */
2315 s8 pwr = min(ch_info->max_power_avg,
2316 clip_pwrs[rate_index]);
2317
2318 pwr_info = &ch_info->power_info[rate_index];
2319
2320 /* get base (i.e. at factory-measured temperature)
2321 * power table index for this rate's power */
bb8c093b 2322 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2323 ch_info->group_index,
2324 &power_idx);
2325 if (rc) {
15b1687c 2326 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2327 return rc;
2328 }
2329 pwr_info->base_power_index = (u8) power_idx;
2330
2331 /* temperature compensate */
2332 power_idx += delta_index;
2333
2334 /* stay within range of gain table */
bb8c093b 2335 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2336
bb8c093b 2337 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2338 pwr_info->requested_power = pwr;
2339 pwr_info->power_table_index = (u8) power_idx;
2340 pwr_info->tpc.tx_gain =
2341 power_gain_table[a_band][power_idx].tx_gain;
2342 pwr_info->tpc.dsp_atten =
2343 power_gain_table[a_band][power_idx].dsp_atten;
2344 }
2345
2346 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2347 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2348 power = pwr_info->requested_power +
2349 IWL_CCK_FROM_OFDM_POWER_DIFF;
2350 pwr_index = pwr_info->power_table_index +
2351 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2352 base_pwr_index = pwr_info->base_power_index +
2353 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2354
2355 /* stay within table range */
bb8c093b 2356 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2357 gain = power_gain_table[a_band][pwr_index].tx_gain;
2358 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2359
bb8c093b 2360 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2361 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2362 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2363 for (rate_index = 0;
2364 rate_index < IWL_CCK_RATES; rate_index++) {
2365 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2366 pwr_info->requested_power = power;
2367 pwr_info->power_table_index = pwr_index;
2368 pwr_info->base_power_index = base_pwr_index;
2369 pwr_info->tpc.tx_gain = gain;
2370 pwr_info->tpc.dsp_atten = dsp_atten;
2371 }
2372
2373 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2374 for (scan_tbl_index = 0;
2375 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2376 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2377 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2378 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2379 actual_index, clip_pwrs, ch_info, a_band);
2380 }
2381 }
2382
2383 return 0;
2384}
2385
4a8a4322 2386int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2387{
2388 int rc;
b481de9c 2389
5d49f498
AK		 2390 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2391 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2392 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2393 if (rc < 0)
15b1687c 2394 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2395
b481de9c
ZY		 2396 return 0;
2397}
2398
188cf6c7 2399int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2400{
b481de9c
ZY		 2401 int txq_id = txq->q.id;
2402
3832ec9d 2403 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2404
2405 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2406
5d49f498
AK		 2407 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2408 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2409
5d49f498 2410 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2411 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2412 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2413 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2414 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2415 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2416
2417 /* fake read to flush all prev. writes */
5d49f498 2418 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2419
2420 return 0;
2421}
2422
42427b4e
KA		 2423/*
2424 * HCMD utils
2425 */
2426static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2427{
2428 switch (cmd_id) {
2429 case REPLY_RXON:
d25aabb0
WT		 2430 return sizeof(struct iwl3945_rxon_cmd);
2431 case POWER_TABLE_CMD:
2432 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2433 default:
2434 return len;
2435 }
2436}
2437
c587de0b 2438
17f841cd
SO		 2439static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2440{
c587de0b
TW		 2441 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2442 addsta->mode = cmd->mode;
2443 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2444 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2445 addsta->station_flags = cmd->station_flags;
2446 addsta->station_flags_msk = cmd->station_flags_msk;
2447 addsta->tid_disable_tx = cpu_to_le16(0);
2448 addsta->rate_n_flags = cmd->rate_n_flags;
2449 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2450 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2451 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2452
2453 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2454}
2455
c587de0b 2456
b481de9c
ZY		 2457/**
2458 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2459 */
4a8a4322 2460int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2461{
14577f23 2462 int rc, i, index, prev_index;
bb8c093b 2463 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2464 .reserved = {0, 0, 0},
2465 };
bb8c093b 2466 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2467
bb8c093b
CH		 2468 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2469 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2470
2471 table[index].rate_n_flags =
bb8c093b 2472 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2473 table[index].try_cnt = priv->retry_rate;
bb8c093b 2474 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2475 table[index].next_rate_index =
2476 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2477 }
2478
8318d78a
JB		 2479 switch (priv->band) {
2480 case IEEE80211_BAND_5GHZ:
e1623446 2481 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2482 /* If one of the following CCK rates is used,
2483 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2484 for (i = IWL_RATE_1M_INDEX_TABLE;
2485 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2486 table[i].next_rate_index =
2487 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2488
2489 /* Don't fall back to CCK rates */
7262796a
AM		 2490 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2491 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2492
2493 /* Don't drop out of OFDM rates */
14577f23 2494 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2495 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2496 break;
2497
8318d78a 2498 case IEEE80211_BAND_2GHZ:
e1623446 2499 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2500 /* If an OFDM rate is used, have it fall back to the
2501 * 1M CCK rates */
b481de9c 2502
7262796a 2503 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2504 iwl_is_associated(priv)) {
7262796a
AM		 2505
2506 index = IWL_FIRST_CCK_RATE;
2507 for (i = IWL_RATE_6M_INDEX_TABLE;
2508 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2509 table[i].next_rate_index =
2510 iwl3945_rates[index].table_rs_index;
2511
2512 index = IWL_RATE_11M_INDEX_TABLE;
2513 /* CCK shouldn't fall back to OFDM... */
2514 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2515 }
b481de9c
ZY		 2516 break;
2517
2518 default:
8318d78a 2519 WARN_ON(1);
b481de9c
ZY		 2520 break;
2521 }
2522
2523 /* Update the rate scaling for control frame Tx */
2524 rate_cmd.table_id = 0;
518099a8 2525 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2526 &rate_cmd);
2527 if (rc)
2528 return rc;
2529
2530 /* Update the rate scaling for data frame Tx */
2531 rate_cmd.table_id = 1;
518099a8 2532 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2533 &rate_cmd);
2534}
2535
796083cb 2536/* Called when initializing driver */
4a8a4322 2537int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2538{
3832ec9d
AK		 2539 memset((void *)&priv->hw_params, 0,
2540 sizeof(struct iwl_hw_params));
b481de9c 2541
3832ec9d 2542 priv->shared_virt =
b481de9c 2543 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2544 sizeof(struct iwl3945_shared),
3832ec9d 2545 &priv->shared_phys);
b481de9c 2546
3832ec9d 2547 if (!priv->shared_virt) {
15b1687c 2548 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2549 mutex_unlock(&priv->mutex);
2550 return -ENOMEM;
2551 }
2552
21c02a1a
AK		 2553 /* Assign number of Usable TX queues */
2554 priv->hw_params.max_txq_num = TFD_QUEUE_MAX;
2555
a8e74e27 2556 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
1e33dc64 2557 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
3832ec9d
AK		 2558 priv->hw_params.max_pkt_size = 2342;
2559 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2560 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2561 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2562 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2563
141c43a3
WT		 2564 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2565
b481de9c
ZY		 2566 return 0;
2567}
2568
4a8a4322 2569unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2570 struct iwl3945_frame *frame, u8 rate)
b481de9c 2571{
bb8c093b 2572 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2573 unsigned int frame_size;
2574
bb8c093b 2575 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2576 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2577
3832ec9d 2578 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2579 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2580
bb8c093b 2581 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2582 tx_beacon_cmd->frame,
b481de9c
ZY		 2583 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2584
2585 BUG_ON(frame_size > MAX_MPDU_SIZE);
2586 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2587
2588 tx_beacon_cmd->tx.rate = rate;
2589 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2590 TX_CMD_FLG_TSF_MSK);
2591
14577f23
MA		 2592 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2593 tx_beacon_cmd->tx.supp_rates[0] =
2594 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2595
b481de9c 2596 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2597 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2598
3ac7f146 2599 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2600}
2601
4a8a4322 2602void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2603{
91c066f2 2604 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2605 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2606}
2607
4a8a4322 2608void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2609{
2610 INIT_DELAYED_WORK(&priv->thermal_periodic,
2611 iwl3945_bg_reg_txpower_periodic);
2612}
2613
4a8a4322 2614void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2615{
2616 cancel_delayed_work(&priv->thermal_periodic);
2617}
2618
0164b9b4
KA		 2619/* check contents of special bootstrap uCode SRAM */
2620static int iwl3945_verify_bsm(struct iwl_priv *priv)
2621 {
2622 __le32 *image = priv->ucode_boot.v_addr;
2623 u32 len = priv->ucode_boot.len;
2624 u32 reg;
2625 u32 val;
2626
e1623446 2627 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2628
2629 /* verify BSM SRAM contents */
2630 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2631 for (reg = BSM_SRAM_LOWER_BOUND;
2632 reg < BSM_SRAM_LOWER_BOUND + len;
2633 reg += sizeof(u32), image++) {
2634 val = iwl_read_prph(priv, reg);
2635 if (val != le32_to_cpu(*image)) {
2636 IWL_ERR(priv, "BSM uCode verification failed at "
2637 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2638 BSM_SRAM_LOWER_BOUND,
2639 reg - BSM_SRAM_LOWER_BOUND, len,
2640 val, le32_to_cpu(*image));
2641 return -EIO;
2642 }
2643 }
2644
e1623446 2645 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2646
2647 return 0;
2648}
2649
e6148917
SO		 2650
2651/******************************************************************************
2652 *
2653 * EEPROM related functions
2654 *
2655 ******************************************************************************/
2656
2657/*
2658 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2659 * embedded controller) as EEPROM reader; each read is a series of pulses
2660 * to/from the EEPROM chip, not a single event, so even reads could conflict
2661 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2662 * simply claims ownership, which should be safe when this function is called
2663 * (i.e. before loading uCode!).
2664 */
2665static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2666{
2667 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2668 return 0;
2669}
2670
2671
2672static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2673{
2674 return;
2675}
2676
0164b9b4
KA		 2677 /**
2678 * iwl3945_load_bsm - Load bootstrap instructions
2679 *
2680 * BSM operation:
2681 *
2682 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2683 * in special SRAM that does not power down during RFKILL. When powering back
2684 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2685 * the bootstrap program into the on-board processor, and starts it.
2686 *
2687 * The bootstrap program loads (via DMA) instructions and data for a new
2688 * program from host DRAM locations indicated by the host driver in the
2689 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2690 * automatically.
2691 *
2692 * When initializing the NIC, the host driver points the BSM to the
2693 * "initialize" uCode image. This uCode sets up some internal data, then
2694 * notifies host via "initialize alive" that it is complete.
2695 *
2696 * The host then replaces the BSM_DRAM_* pointer values to point to the
2697 * normal runtime uCode instructions and a backup uCode data cache buffer
2698 * (filled initially with starting data values for the on-board processor),
2699 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2700 * which begins normal operation.
2701 *
2702 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2703 * the backup data cache in DRAM before SRAM is powered down.
2704 *
2705 * When powering back up, the BSM loads the bootstrap program. This reloads
2706 * the runtime uCode instructions and the backup data cache into SRAM,
2707 * and re-launches the runtime uCode from where it left off.
2708 */
2709static int iwl3945_load_bsm(struct iwl_priv *priv)
2710{
2711 __le32 *image = priv->ucode_boot.v_addr;
2712 u32 len = priv->ucode_boot.len;
2713 dma_addr_t pinst;
2714 dma_addr_t pdata;
2715 u32 inst_len;
2716 u32 data_len;
2717 int rc;
2718 int i;
2719 u32 done;
2720 u32 reg_offset;
2721
e1623446 2722 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2723
2724 /* make sure bootstrap program is no larger than BSM's SRAM size */
2725 if (len > IWL39_MAX_BSM_SIZE)
2726 return -EINVAL;
2727
2728 /* Tell bootstrap uCode where to find the "Initialize" uCode
2729 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2730 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2731 * after the "initialize" uCode has run, to point to
2732 * runtime/protocol instructions and backup data cache. */
2733 pinst = priv->ucode_init.p_addr;
2734 pdata = priv->ucode_init_data.p_addr;
2735 inst_len = priv->ucode_init.len;
2736 data_len = priv->ucode_init_data.len;
2737
0164b9b4
KA		 2738 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2739 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2740 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2741 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2742
2743 /* Fill BSM memory with bootstrap instructions */
2744 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2745 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2746 reg_offset += sizeof(u32), image++)
2747 _iwl_write_prph(priv, reg_offset,
2748 le32_to_cpu(*image));
2749
2750 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2751 if (rc)
0164b9b4 2752 return rc;
0164b9b4
KA		 2753
2754 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2755 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2756 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2757 IWL39_RTC_INST_LOWER_BOUND);
2758 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2759
2760 /* Load bootstrap code into instruction SRAM now,
2761 * to prepare to load "initialize" uCode */
2762 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2763 BSM_WR_CTRL_REG_BIT_START);
2764
2765 /* Wait for load of bootstrap uCode to finish */
2766 for (i = 0; i < 100; i++) {
2767 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2768 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2769 break;
2770 udelay(10);
2771 }
2772 if (i < 100)
e1623446 2773 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2774 else {
2775 IWL_ERR(priv, "BSM write did not complete!\n");
2776 return -EIO;
2777 }
2778
2779 /* Enable future boot loads whenever power management unit triggers it
2780 * (e.g. when powering back up after power-save shutdown) */
2781 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2782 BSM_WR_CTRL_REG_BIT_START_EN);
2783
0164b9b4
KA		 2784 return 0;
2785}
2786
5bbe233b
AK		 2787static struct iwl_hcmd_ops iwl3945_hcmd = {
2788 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2789 .commit_rxon = iwl3945_commit_rxon,
5bbe233b
AK		 2790};
2791
0164b9b4 2792static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2793 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2794 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2795 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2796 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2797 .apm_ops = {
2798 .init = iwl3945_apm_init,
2799 .reset = iwl3945_apm_reset,
2800 .stop = iwl3945_apm_stop,
2801 .config = iwl3945_nic_config,
854682ed 2802 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2803 },
e6148917
SO		 2804 .eeprom_ops = {
2805 .regulatory_bands = {
2806 EEPROM_REGULATORY_BAND_1_CHANNELS,
2807 EEPROM_REGULATORY_BAND_2_CHANNELS,
2808 EEPROM_REGULATORY_BAND_3_CHANNELS,
2809 EEPROM_REGULATORY_BAND_4_CHANNELS,
2810 EEPROM_REGULATORY_BAND_5_CHANNELS,
a89d03c4
RC		 2811 EEPROM_REGULATORY_BAND_NO_FAT,
2812 EEPROM_REGULATORY_BAND_NO_FAT,
e6148917
SO		 2813 },
2814 .verify_signature = iwlcore_eeprom_verify_signature,
2815 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2816 .release_semaphore = iwl3945_eeprom_release_semaphore,
2817 .query_addr = iwlcore_eeprom_query_addr,
2818 },
75bcfae9 2819 .send_tx_power = iwl3945_send_tx_power,
c2436980 2820 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2821 .post_associate = iwl3945_post_associate,
ef850d7c 2822 .isr = iwl_isr_legacy,
60690a6a 2823 .config_ap = iwl3945_config_ap,
0164b9b4
KA		 2824};
2825
42427b4e
KA		 2826static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2827 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2828 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
42427b4e
KA		 2829};
2830
0164b9b4
KA		 2831static struct iwl_ops iwl3945_ops = {
2832 .lib = &iwl3945_lib,
5bbe233b 2833 .hcmd = &iwl3945_hcmd,
42427b4e 2834 .utils = &iwl3945_hcmd_utils,
0164b9b4
KA		 2835};
2836
c0f20d91 2837static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2838 .name = "3945BG",
a0987a8d
RC		 2839 .fw_name_pre = IWL3945_FW_PRE,
2840 .ucode_api_max = IWL3945_UCODE_API_MAX,
2841 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2842 .sku = IWL_SKU_G,
e6148917
SO		 2843 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2844 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2845 .ops = &iwl3945_ops,
ef850d7c
MA		 2846 .mod_params = &iwl3945_mod_params,
2847 .use_isr_legacy = true
82b9a121
TW		 2848};
2849
c0f20d91 2850static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2851 .name = "3945ABG",
a0987a8d
RC		 2852 .fw_name_pre = IWL3945_FW_PRE,
2853 .ucode_api_max = IWL3945_UCODE_API_MAX,
2854 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2855 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2856 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2857 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2858 .ops = &iwl3945_ops,
ef850d7c
MA		 2859 .mod_params = &iwl3945_mod_params,
2860 .use_isr_legacy = true
82b9a121
TW		 2861};
2862
bb8c093b 2863struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2864 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2865 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2866 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2867 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2868 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2869 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2870 {0}
2871};
2872
bb8c093b 2873MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux kernel - Deliverables
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