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iwlwifi: cleanup namespace
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <net/mac80211.h>
39
40#include <linux/etherdevice.h>
b481de9c 41
b481de9c 42#include "iwl-3945.h"
5d08cd1d 43#include "iwl-helpers.h"
b481de9c
ZY		 44#include "iwl-3945-rs.h"
45
46#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_##r##M_IEEE, \
49 IWL_RATE_##ip##M_INDEX, \
50 IWL_RATE_##in##M_INDEX, \
51 IWL_RATE_##rp##M_INDEX, \
52 IWL_RATE_##rn##M_INDEX, \
53 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 54 IWL_RATE_##np##M_INDEX, \
55 IWL_RATE_##r##M_INDEX_TABLE, \
56 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 57
58/*
59 * Parameter order:
60 * rate, prev rate, next rate, prev tgg rate, next tgg rate
61 *
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
64 *
65 */
bb8c093b 66const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
14577f23
MA		 67 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 71 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 79};
80
bb8c093b 81/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 82#define IWL_EVT_DISABLE (0)
83#define IWL_EVT_DISABLE_SIZE (1532/32)
84
85/**
bb8c093b 86 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 87 *
88 * Disable an event by writing "1"s into "disable"
89 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
90 * Default values of 0 enable uCode events to be logged.
91 * Use for only special debugging. This function is just a placeholder as-is,
92 * you'll need to provide the special bits! ...
93 * ... and set IWL_EVT_DISABLE to 1. */
bb8c093b 94void iwl3945_disable_events(struct iwl3945_priv *priv)
b481de9c 95{
af7cca2a 96 int ret;
b481de9c
ZY		 97 int i;
98 u32 base; /* SRAM address of event log header */
99 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
100 u32 array_size; /* # of u32 entries in array */
101 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
102 0x00000000, /* 31 - 0 Event id numbers */
103 0x00000000, /* 63 - 32 */
104 0x00000000, /* 95 - 64 */
105 0x00000000, /* 127 - 96 */
106 0x00000000, /* 159 - 128 */
107 0x00000000, /* 191 - 160 */
108 0x00000000, /* 223 - 192 */
109 0x00000000, /* 255 - 224 */
110 0x00000000, /* 287 - 256 */
111 0x00000000, /* 319 - 288 */
112 0x00000000, /* 351 - 320 */
113 0x00000000, /* 383 - 352 */
114 0x00000000, /* 415 - 384 */
115 0x00000000, /* 447 - 416 */
116 0x00000000, /* 479 - 448 */
117 0x00000000, /* 511 - 480 */
118 0x00000000, /* 543 - 512 */
119 0x00000000, /* 575 - 544 */
120 0x00000000, /* 607 - 576 */
121 0x00000000, /* 639 - 608 */
122 0x00000000, /* 671 - 640 */
123 0x00000000, /* 703 - 672 */
124 0x00000000, /* 735 - 704 */
125 0x00000000, /* 767 - 736 */
126 0x00000000, /* 799 - 768 */
127 0x00000000, /* 831 - 800 */
128 0x00000000, /* 863 - 832 */
129 0x00000000, /* 895 - 864 */
130 0x00000000, /* 927 - 896 */
131 0x00000000, /* 959 - 928 */
132 0x00000000, /* 991 - 960 */
133 0x00000000, /* 1023 - 992 */
134 0x00000000, /* 1055 - 1024 */
135 0x00000000, /* 1087 - 1056 */
136 0x00000000, /* 1119 - 1088 */
137 0x00000000, /* 1151 - 1120 */
138 0x00000000, /* 1183 - 1152 */
139 0x00000000, /* 1215 - 1184 */
140 0x00000000, /* 1247 - 1216 */
141 0x00000000, /* 1279 - 1248 */
142 0x00000000, /* 1311 - 1280 */
143 0x00000000, /* 1343 - 1312 */
144 0x00000000, /* 1375 - 1344 */
145 0x00000000, /* 1407 - 1376 */
146 0x00000000, /* 1439 - 1408 */
147 0x00000000, /* 1471 - 1440 */
148 0x00000000, /* 1503 - 1472 */
149 };
150
151 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 152 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 153 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
154 return;
155 }
156
bb8c093b 157 ret = iwl3945_grab_nic_access(priv);
af7cca2a 158 if (ret) {
b481de9c
ZY		 159 IWL_WARNING("Can not read from adapter at this time.\n");
160 return;
161 }
162
bb8c093b
CH		 163 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
165 iwl3945_release_nic_access(priv);
b481de9c
ZY		 166
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
168 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
169 disable_ptr);
bb8c093b 170 ret = iwl3945_grab_nic_access(priv);
b481de9c 171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
bb8c093b 172 iwl3945_write_targ_mem(priv,
af7cca2a
TW		 173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
b481de9c 175
bb8c093b 176 iwl3945_release_nic_access(priv);
b481de9c
ZY		 177 } else {
178 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
179 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
180 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
181 disable_ptr, array_size);
182 }
183
184}
185
186/**
187 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
188 * @priv: eeprom and antenna fields are used to determine antenna flags
189 *
190 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
191 * priv->antenna specifies the antenna diversity mode:
192 *
193 * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
194 * IWL_ANTENNA_MAIN - Force MAIN antenna
195 * IWL_ANTENNA_AUX - Force AUX antenna
196 */
bb8c093b 197__le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
b481de9c
ZY		 198{
199 switch (priv->antenna) {
200 case IWL_ANTENNA_DIVERSITY:
201 return 0;
202
203 case IWL_ANTENNA_MAIN:
204 if (priv->eeprom.antenna_switch_type)
205 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
206 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
207
208 case IWL_ANTENNA_AUX:
209 if (priv->eeprom.antenna_switch_type)
210 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
211 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
212 }
213
214 /* bad antenna selector value */
215 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
216 return 0; /* "diversity" is default if error */
217}
218
219/*****************************************************************************
220 *
221 * Intel PRO/Wireless 3945ABG/BG Network Connection
222 *
223 * RX handler implementations
224 *
225 * Used by iwl-base.c
226 *
227 *****************************************************************************/
228
bb8c093b 229void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 230{
bb8c093b 231 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 232 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 233 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 234 le32_to_cpu(pkt->len));
235
236 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
237
238 priv->last_statistics_time = jiffies;
239}
240
bb8c093b
CH		 241static void iwl3945_handle_data_packet(struct iwl3945_priv *priv, int is_data,
242 struct iwl3945_rx_mem_buffer *rxb,
b481de9c
ZY		 243 struct ieee80211_rx_status *stats,
244 u16 phy_flags)
245{
246 struct ieee80211_hdr *hdr;
bb8c093b
CH		 247 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
248 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
249 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 250 short len = le16_to_cpu(rx_hdr->len);
251
252 /* We received data from the HW, so stop the watchdog */
253 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
254 IWL_DEBUG_DROP("Corruption detected!\n");
255 return;
256 }
257
258 /* We only process data packets if the interface is open */
259 if (unlikely(!priv->is_open)) {
260 IWL_DEBUG_DROP_LIMIT
261 ("Dropping packet while interface is not open.\n");
262 return;
263 }
264 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
bb8c093b
CH		 265 if (iwl3945_param_hwcrypto)
266 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 267 le32_to_cpu(rx_end->status),
268 stats);
bb8c093b 269 iwl3945_handle_data_packet_monitor(priv, rxb, IWL_RX_DATA(pkt),
b481de9c
ZY		 270 len, stats, phy_flags);
271 return;
272 }
273
274 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
275 /* Set the size of the skb to the size of the frame */
276 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
277
278 hdr = (void *)rxb->skb->data;
279
bb8c093b
CH		 280 if (iwl3945_param_hwcrypto)
281 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 282 le32_to_cpu(rx_end->status), stats);
283
284 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
285 rxb->skb = NULL;
286}
287
bb8c093b
CH		 288static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
289 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 290{
bb8c093b
CH		 291 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
292 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
293 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
294 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 295 struct ieee80211_hdr *header;
296 u16 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
297 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
298 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
299 struct ieee80211_rx_status stats = {
300 .mactime = le64_to_cpu(rx_end->timestamp),
301 .freq = ieee80211chan2mhz(le16_to_cpu(rx_hdr->channel)),
302 .channel = le16_to_cpu(rx_hdr->channel),
303 .phymode = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
304 MODE_IEEE80211G : MODE_IEEE80211A,
305 .antenna = 0,
306 .rate = rx_hdr->rate,
307 .flag = 0,
308 };
309 u8 network_packet;
310 int snr;
311
312 if ((unlikely(rx_stats->phy_count > 20))) {
313 IWL_DEBUG_DROP
314 ("dsp size out of range [0,20]: "
315 "%d/n", rx_stats->phy_count);
316 return;
317 }
318
319 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
320 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
321 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
322 return;
323 }
324
325 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
326 iwl3945_handle_data_packet(priv, 1, rxb, &stats, phy_flags);
327 return;
328 }
329
330 /* Convert 3945's rssi indicator to dBm */
331 stats.ssi = rx_stats->rssi - IWL_RSSI_OFFSET;
332
333 /* Set default noise value to -127 */
334 if (priv->last_rx_noise == 0)
335 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
336
337 /* 3945 provides noise info for OFDM frames only.
338 * sig_avg and noise_diff are measured by the 3945's digital signal
339 * processor (DSP), and indicate linear levels of signal level and
340 * distortion/noise within the packet preamble after
341 * automatic gain control (AGC). sig_avg should stay fairly
342 * constant if the radio's AGC is working well.
343 * Since these values are linear (not dB or dBm), linear
344 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
345 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
346 * to obtain noise level in dBm.
347 * Calculate stats.signal (quality indicator in %) based on SNR. */
348 if (rx_stats_noise_diff) {
349 snr = rx_stats_sig_avg / rx_stats_noise_diff;
bb8c093b
CH		 350 stats.noise = stats.ssi - iwl3945_calc_db_from_ratio(snr);
351 stats.signal = iwl3945_calc_sig_qual(stats.ssi, stats.noise);
b481de9c
ZY		 352
353 /* If noise info not available, calculate signal quality indicator (%)
354 * using just the dBm signal level. */
355 } else {
356 stats.noise = priv->last_rx_noise;
bb8c093b 357 stats.signal = iwl3945_calc_sig_qual(stats.ssi, 0);
b481de9c
ZY		 358 }
359
360
361 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
362 stats.ssi, stats.noise, stats.signal,
363 rx_stats_sig_avg, rx_stats_noise_diff);
364
365 stats.freq = ieee80211chan2mhz(stats.channel);
366
bb8c093b 367 /* can be covered by iwl3945_report_frame() in most cases */
b481de9c
ZY		 368/* IWL_DEBUG_RX("RX status: 0x%08X\n", rx_end->status); */
369
370 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
371
bb8c093b 372 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 373
c8b0e6e1 374#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 375 if (iwl3945_debug_level & IWL_DL_STATS && net_ratelimit())
b481de9c
ZY		 376 IWL_DEBUG_STATS
377 ("[%c] %d RSSI: %d Signal: %u, Noise: %u, Rate: %u\n",
378 network_packet ? '*' : ' ',
379 stats.channel, stats.ssi, stats.ssi,
380 stats.ssi, stats.rate);
381
bb8c093b 382 if (iwl3945_debug_level & (IWL_DL_RX))
b481de9c 383 /* Set "1" to report good data frames in groups of 100 */
bb8c093b 384 iwl3945_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 385#endif
386
387 if (network_packet) {
388 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
389 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
390 priv->last_rx_rssi = stats.ssi;
391 priv->last_rx_noise = stats.noise;
392 }
393
394 switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) {
395 case IEEE80211_FTYPE_MGMT:
396 switch (le16_to_cpu(header->frame_control) &
397 IEEE80211_FCTL_STYPE) {
398 case IEEE80211_STYPE_PROBE_RESP:
399 case IEEE80211_STYPE_BEACON:{
400 /* If this is a beacon or probe response for
401 * our network then cache the beacon
402 * timestamp */
403 if ((((priv->iw_mode == IEEE80211_IF_TYPE_STA)
404 && !compare_ether_addr(header->addr2,
405 priv->bssid)) ||
406 ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
407 && !compare_ether_addr(header->addr3,
408 priv->bssid)))) {
409 struct ieee80211_mgmt *mgmt =
410 (struct ieee80211_mgmt *)header;
411 __le32 *pos;
412 pos =
413 (__le32 *) & mgmt->u.beacon.
414 timestamp;
415 priv->timestamp0 = le32_to_cpu(pos[0]);
416 priv->timestamp1 = le32_to_cpu(pos[1]);
417 priv->beacon_int = le16_to_cpu(
418 mgmt->u.beacon.beacon_int);
419 if (priv->call_post_assoc_from_beacon &&
420 (priv->iw_mode ==
421 IEEE80211_IF_TYPE_STA))
422 queue_work(priv->workqueue,
423 &priv->post_associate.work);
424
425 priv->call_post_assoc_from_beacon = 0;
426 }
427
428 break;
429 }
430
431 case IEEE80211_STYPE_ACTION:
432 /* TODO: Parse 802.11h frames for CSA... */
433 break;
434
435 /*
436 * TODO: There is no callback function from upper
437 * stack to inform us when associated status. this
438 * work around to sniff assoc_resp management frame
439 * and finish the association process.
440 */
441 case IEEE80211_STYPE_ASSOC_RESP:
442 case IEEE80211_STYPE_REASSOC_RESP:{
443 struct ieee80211_mgmt *mgnt =
444 (struct ieee80211_mgmt *)header;
445 priv->assoc_id = (~((1 << 15) | (1 << 14)) &
446 le16_to_cpu(mgnt->u.
447 assoc_resp.aid));
448 priv->assoc_capability =
449 le16_to_cpu(mgnt->u.assoc_resp.capab_info);
450 if (priv->beacon_int)
451 queue_work(priv->workqueue,
452 &priv->post_associate.work);
453 else
454 priv->call_post_assoc_from_beacon = 1;
455 break;
456 }
457
458 case IEEE80211_STYPE_PROBE_REQ:{
0795af57
JP		 459 DECLARE_MAC_BUF(mac1);
460 DECLARE_MAC_BUF(mac2);
461 DECLARE_MAC_BUF(mac3);
b481de9c
ZY		 462 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
463 IWL_DEBUG_DROP
0795af57
JP		 464 ("Dropping (non network): %s"
465 ", %s, %s\n",
466 print_mac(mac1, header->addr1),
467 print_mac(mac2, header->addr2),
468 print_mac(mac3, header->addr3));
b481de9c
ZY		 469 return;
470 }
471 }
472
473 iwl3945_handle_data_packet(priv, 0, rxb, &stats, phy_flags);
474 break;
475
476 case IEEE80211_FTYPE_CTL:
477 break;
478
0795af57
JP		 479 case IEEE80211_FTYPE_DATA: {
480 DECLARE_MAC_BUF(mac1);
481 DECLARE_MAC_BUF(mac2);
482 DECLARE_MAC_BUF(mac3);
483
bb8c093b 484 if (unlikely(iwl3945_is_duplicate_packet(priv, header)))
0795af57
JP		 485 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
486 print_mac(mac1, header->addr1),
487 print_mac(mac2, header->addr2),
488 print_mac(mac3, header->addr3));
b481de9c
ZY		 489 else
490 iwl3945_handle_data_packet(priv, 1, rxb, &stats,
491 phy_flags);
492 break;
493 }
0795af57 494 }
b481de9c
ZY		 495}
496
bb8c093b 497int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
b481de9c
ZY		 498 dma_addr_t addr, u16 len)
499{
500 int count;
501 u32 pad;
bb8c093b 502 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 503
504 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
505 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
506
507 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
508 IWL_ERROR("Error can not send more than %d chunks\n",
509 NUM_TFD_CHUNKS);
510 return -EINVAL;
511 }
512
513 tfd->pa[count].addr = cpu_to_le32(addr);
514 tfd->pa[count].len = cpu_to_le32(len);
515
516 count++;
517
518 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
519 TFD_CTL_PAD_SET(pad));
520
521 return 0;
522}
523
524/**
bb8c093b 525 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 526 *
527 * Does NOT advance any indexes
528 */
bb8c093b 529int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 530{
bb8c093b
CH		 531 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
532 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 533 struct pci_dev *dev = priv->pci_dev;
534 int i;
535 int counter;
536
537 /* classify bd */
538 if (txq->q.id == IWL_CMD_QUEUE_NUM)
539 /* nothing to cleanup after for host commands */
540 return 0;
541
542 /* sanity check */
543 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
544 if (counter > NUM_TFD_CHUNKS) {
545 IWL_ERROR("Too many chunks: %i\n", counter);
546 /* @todo issue fatal error, it is quite serious situation */
547 return 0;
548 }
549
550 /* unmap chunks if any */
551
552 for (i = 1; i < counter; i++) {
553 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
554 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 555 if (txq->txb[txq->q.read_ptr].skb[0]) {
556 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
557 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 558 /* Can be called from interrupt context */
559 dev_kfree_skb_any(skb);
fc4b6853 560 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 561 }
562 }
563 }
564 return 0;
565}
566
bb8c093b 567u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
b481de9c
ZY		 568{
569 int i;
570 int ret = IWL_INVALID_STATION;
571 unsigned long flags;
0795af57 572 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 573
574 spin_lock_irqsave(&priv->sta_lock, flags);
575 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
576 if ((priv->stations[i].used) &&
577 (!compare_ether_addr
578 (priv->stations[i].sta.sta.addr, addr))) {
579 ret = i;
580 goto out;
581 }
582
0795af57
JP		 583 IWL_DEBUG_INFO("can not find STA %s (total %d)\n",
584 print_mac(mac, addr), priv->num_stations);
b481de9c
ZY		 585 out:
586 spin_unlock_irqrestore(&priv->sta_lock, flags);
587 return ret;
588}
589
590/**
bb8c093b 591 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 592 *
593*/
bb8c093b
CH		 594void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
595 struct iwl3945_cmd *cmd,
b481de9c
ZY		 596 struct ieee80211_tx_control *ctrl,
597 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
598{
599 unsigned long flags;
600 u16 rate_index = min(ctrl->tx_rate & 0xffff, IWL_RATE_COUNT - 1);
601 u16 rate_mask;
602 int rate;
603 u8 rts_retry_limit;
604 u8 data_retry_limit;
605 __le32 tx_flags;
606 u16 fc = le16_to_cpu(hdr->frame_control);
607
bb8c093b 608 rate = iwl3945_rates[rate_index].plcp;
b481de9c
ZY		 609 tx_flags = cmd->cmd.tx.tx_flags;
610
611 /* We need to figure out how to get the sta->supp_rates while
612 * in this running context; perhaps encoding into ctrl->tx_rate? */
613 rate_mask = IWL_RATES_MASK;
614
615 spin_lock_irqsave(&priv->sta_lock, flags);
616
617 priv->stations[sta_id].current_rate.rate_n_flags = rate;
618
619 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
620 (sta_id != IWL3945_BROADCAST_ID) &&
621 (sta_id != IWL_MULTICAST_ID))
622 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
623
624 spin_unlock_irqrestore(&priv->sta_lock, flags);
625
626 if (tx_id >= IWL_CMD_QUEUE_NUM)
627 rts_retry_limit = 3;
628 else
629 rts_retry_limit = 7;
630
631 if (ieee80211_is_probe_response(fc)) {
632 data_retry_limit = 3;
633 if (data_retry_limit < rts_retry_limit)
634 rts_retry_limit = data_retry_limit;
635 } else
636 data_retry_limit = IWL_DEFAULT_TX_RETRY;
637
638 if (priv->data_retry_limit != -1)
639 data_retry_limit = priv->data_retry_limit;
640
641 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
642 switch (fc & IEEE80211_FCTL_STYPE) {
643 case IEEE80211_STYPE_AUTH:
644 case IEEE80211_STYPE_DEAUTH:
645 case IEEE80211_STYPE_ASSOC_REQ:
646 case IEEE80211_STYPE_REASSOC_REQ:
647 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
648 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
649 tx_flags |= TX_CMD_FLG_CTS_MSK;
650 }
651 break;
652 default:
653 break;
654 }
655 }
656
657 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
658 cmd->cmd.tx.data_retry_limit = data_retry_limit;
659 cmd->cmd.tx.rate = rate;
660 cmd->cmd.tx.tx_flags = tx_flags;
661
662 /* OFDM */
14577f23
MA		 663 cmd->cmd.tx.supp_rates[0] =
664 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 665
666 /* CCK */
14577f23 667 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 668
669 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
670 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
671 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
672 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
673}
674
bb8c093b 675u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 676{
677 unsigned long flags_spin;
bb8c093b 678 struct iwl3945_station_entry *station;
b481de9c
ZY		 679
680 if (sta_id == IWL_INVALID_STATION)
681 return IWL_INVALID_STATION;
682
683 spin_lock_irqsave(&priv->sta_lock, flags_spin);
684 station = &priv->stations[sta_id];
685
686 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
687 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
688 station->current_rate.rate_n_flags = tx_rate;
689 station->sta.mode = STA_CONTROL_MODIFY_MSK;
690
691 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
692
bb8c093b 693 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 694 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
695 sta_id, tx_rate);
696 return sta_id;
697}
698
bb8c093b 699static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
b481de9c
ZY		 700{
701 int rc;
702 unsigned long flags;
703
704 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 705 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 706 if (rc) {
707 spin_unlock_irqrestore(&priv->lock, flags);
708 return rc;
709 }
710
711 if (!pwr_max) {
712 u32 val;
713
714 rc = pci_read_config_dword(priv->pci_dev,
715 PCI_POWER_SOURCE, &val);
716 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
bb8c093b 717 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 718 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
719 ~APMG_PS_CTRL_MSK_PWR_SRC);
bb8c093b 720 iwl3945_release_nic_access(priv);
b481de9c 721
bb8c093b 722 iwl3945_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 723 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
724 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
725 } else
bb8c093b 726 iwl3945_release_nic_access(priv);
b481de9c 727 } else {
bb8c093b 728 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 729 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
730 ~APMG_PS_CTRL_MSK_PWR_SRC);
731
bb8c093b
CH		 732 iwl3945_release_nic_access(priv);
733 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 734 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
735 }
736 spin_unlock_irqrestore(&priv->lock, flags);
737
738 return rc;
739}
740
bb8c093b 741static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 742{
743 int rc;
744 unsigned long flags;
745
746 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 747 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 748 if (rc) {
749 spin_unlock_irqrestore(&priv->lock, flags);
750 return rc;
751 }
752
bb8c093b
CH		 753 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
754 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
b481de9c 755 priv->hw_setting.shared_phys +
bb8c093b
CH		 756 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
757 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
758 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
b481de9c
ZY		 759 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
760 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
761 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
762 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
763 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
764 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
765 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
766 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
767
768 /* fake read to flush all prev I/O */
bb8c093b 769 iwl3945_read_direct32(priv, FH_RSSR_CTRL);
b481de9c 770
bb8c093b 771 iwl3945_release_nic_access(priv);
b481de9c
ZY		 772 spin_unlock_irqrestore(&priv->lock, flags);
773
774 return 0;
775}
776
bb8c093b 777static int iwl3945_tx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 778{
779 int rc;
780 unsigned long flags;
781
782 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 783 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 784 if (rc) {
785 spin_unlock_irqrestore(&priv->lock, flags);
786 return rc;
787 }
788
789 /* bypass mode */
bb8c093b 790 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 791
792 /* RA 0 is active */
bb8c093b 793 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 794
795 /* all 6 fifo are active */
bb8c093b 796 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 797
bb8c093b
CH		 798 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
799 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
800 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
801 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 802
bb8c093b 803 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
b481de9c
ZY		 804 priv->hw_setting.shared_phys);
805
bb8c093b 806 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
b481de9c
ZY		 807 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
808 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
809 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
810 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
811 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
812 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
813 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
814
bb8c093b 815 iwl3945_release_nic_access(priv);
b481de9c
ZY		 816 spin_unlock_irqrestore(&priv->lock, flags);
817
818 return 0;
819}
820
821/**
822 * iwl3945_txq_ctx_reset - Reset TX queue context
823 *
824 * Destroys all DMA structures and initialize them again
825 */
bb8c093b 826static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 827{
828 int rc;
829 int txq_id, slots_num;
830
bb8c093b 831 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 832
833 /* Tx CMD queue */
834 rc = iwl3945_tx_reset(priv);
835 if (rc)
836 goto error;
837
838 /* Tx queue(s) */
839 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
840 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
841 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 842 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 843 txq_id);
844 if (rc) {
845 IWL_ERROR("Tx %d queue init failed\n", txq_id);
846 goto error;
847 }
848 }
849
850 return rc;
851
852 error:
bb8c093b 853 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 854 return rc;
855}
856
bb8c093b 857int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
b481de9c
ZY		 858{
859 u8 rev_id;
860 int rc;
861 unsigned long flags;
bb8c093b 862 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 863
bb8c093b 864 iwl3945_power_init_handle(priv);
b481de9c
ZY		 865
866 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 867 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24));
868 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 869 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
870
bb8c093b
CH		 871 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
872 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 873 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
874 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
875 if (rc < 0) {
876 spin_unlock_irqrestore(&priv->lock, flags);
877 IWL_DEBUG_INFO("Failed to init the card\n");
878 return rc;
879 }
880
bb8c093b 881 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 882 if (rc) {
883 spin_unlock_irqrestore(&priv->lock, flags);
884 return rc;
885 }
bb8c093b 886 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 887 APMG_CLK_VAL_DMA_CLK_RQT |
888 APMG_CLK_VAL_BSM_CLK_RQT);
889 udelay(20);
bb8c093b 890 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c 891 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
bb8c093b 892 iwl3945_release_nic_access(priv);
b481de9c
ZY		 893 spin_unlock_irqrestore(&priv->lock, flags);
894
895 /* Determine HW type */
896 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
897 if (rc)
898 return rc;
899 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
900
901 iwl3945_nic_set_pwr_src(priv, 1);
902 spin_lock_irqsave(&priv->lock, flags);
903
904 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
905 IWL_DEBUG_INFO("RTP type \n");
906 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
907 IWL_DEBUG_INFO("ALM-MB type\n");
bb8c093b 908 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 909 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB);
910 } else {
911 IWL_DEBUG_INFO("ALM-MM type\n");
bb8c093b 912 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 913 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM);
914 }
915
916 spin_unlock_irqrestore(&priv->lock, flags);
917
918 /* Initialize the EEPROM */
bb8c093b 919 rc = iwl3945_eeprom_init(priv);
b481de9c
ZY		 920 if (rc)
921 return rc;
922
923 spin_lock_irqsave(&priv->lock, flags);
924 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
925 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
bb8c093b 926 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 927 CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC);
928 } else
929 IWL_DEBUG_INFO("SKU OP mode is basic\n");
930
931 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
932 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
933 priv->eeprom.board_revision);
bb8c093b 934 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 935 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
936 } else {
937 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
938 priv->eeprom.board_revision);
bb8c093b 939 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 940 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
941 }
942
943 if (priv->eeprom.almgor_m_version <= 1) {
bb8c093b 944 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 945 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
946 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
947 priv->eeprom.almgor_m_version);
948 } else {
949 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
950 priv->eeprom.almgor_m_version);
bb8c093b 951 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 952 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
953 }
954 spin_unlock_irqrestore(&priv->lock, flags);
955
956 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
957 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
958
959 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
960 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
961
962 /* Allocate the RX queue, or reset if it is already allocated */
963 if (!rxq->bd) {
bb8c093b 964 rc = iwl3945_rx_queue_alloc(priv);
b481de9c
ZY		 965 if (rc) {
966 IWL_ERROR("Unable to initialize Rx queue\n");
967 return -ENOMEM;
968 }
969 } else
bb8c093b 970 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 971
bb8c093b 972 iwl3945_rx_replenish(priv);
b481de9c
ZY		 973
974 iwl3945_rx_init(priv, rxq);
975
976 spin_lock_irqsave(&priv->lock, flags);
977
978 /* Look at using this instead:
979 rxq->need_update = 1;
bb8c093b 980 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 981 */
982
bb8c093b 983 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 984 if (rc) {
985 spin_unlock_irqrestore(&priv->lock, flags);
986 return rc;
987 }
bb8c093b
CH		 988 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
989 iwl3945_release_nic_access(priv);
b481de9c
ZY		 990
991 spin_unlock_irqrestore(&priv->lock, flags);
992
993 rc = iwl3945_txq_ctx_reset(priv);
994 if (rc)
995 return rc;
996
997 set_bit(STATUS_INIT, &priv->status);
998
999 return 0;
1000}
1001
1002/**
bb8c093b 1003 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1004 *
1005 * Destroy all TX DMA queues and structures
1006 */
bb8c093b 1007void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
b481de9c
ZY		 1008{
1009 int txq_id;
1010
1011 /* Tx queues */
1012 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
bb8c093b 1013 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c
ZY		 1014}
1015
bb8c093b 1016void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 1017{
1018 int queue;
1019 unsigned long flags;
1020
1021 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1022 if (iwl3945_grab_nic_access(priv)) {
b481de9c 1023 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1024 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1025 return;
1026 }
1027
1028 /* stop SCD */
bb8c093b 1029 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1030
1031 /* reset TFD queues */
1032 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
bb8c093b
CH		 1033 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1034 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
b481de9c
ZY		 1035 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1036 1000);
1037 }
1038
bb8c093b 1039 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1040 spin_unlock_irqrestore(&priv->lock, flags);
1041
bb8c093b 1042 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1043}
1044
bb8c093b 1045int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
b481de9c
ZY		 1046{
1047 int rc = 0;
1048 u32 reg_val;
1049 unsigned long flags;
1050
1051 spin_lock_irqsave(&priv->lock, flags);
1052
1053 /* set stop master bit */
bb8c093b 1054 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1055
bb8c093b 1056 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 1057
1058 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1059 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1060 IWL_DEBUG_INFO("Card in power save, master is already "
1061 "stopped\n");
1062 else {
bb8c093b 1063 rc = iwl3945_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 1064 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1065 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1066 if (rc < 0) {
1067 spin_unlock_irqrestore(&priv->lock, flags);
1068 return rc;
1069 }
1070 }
1071
1072 spin_unlock_irqrestore(&priv->lock, flags);
1073 IWL_DEBUG_INFO("stop master\n");
1074
1075 return rc;
1076}
1077
bb8c093b 1078int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1079{
1080 int rc;
1081 unsigned long flags;
1082
bb8c093b 1083 iwl3945_hw_nic_stop_master(priv);
b481de9c
ZY		 1084
1085 spin_lock_irqsave(&priv->lock, flags);
1086
bb8c093b 1087 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1088
bb8c093b 1089 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1090 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1091 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1092
bb8c093b 1093 rc = iwl3945_grab_nic_access(priv);
b481de9c 1094 if (!rc) {
bb8c093b 1095 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1096 APMG_CLK_VAL_BSM_CLK_RQT);
1097
1098 udelay(10);
1099
bb8c093b 1100 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1101 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1102
bb8c093b
CH		 1103 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1104 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1105 0xFFFFFFFF);
1106
1107 /* enable DMA */
bb8c093b 1108 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1109 APMG_CLK_VAL_DMA_CLK_RQT |
1110 APMG_CLK_VAL_BSM_CLK_RQT);
1111 udelay(10);
1112
bb8c093b 1113 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1114 APMG_PS_CTRL_VAL_RESET_REQ);
1115 udelay(5);
bb8c093b 1116 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1117 APMG_PS_CTRL_VAL_RESET_REQ);
bb8c093b 1118 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1119 }
1120
1121 /* Clear the 'host command active' bit... */
1122 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1123
1124 wake_up_interruptible(&priv->wait_command_queue);
1125 spin_unlock_irqrestore(&priv->lock, flags);
1126
1127 return rc;
1128}
1129
1130/**
bb8c093b 1131 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1132 * return index delta into power gain settings table
1133*/
bb8c093b 1134static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1135{
1136 return (new_reading - old_reading) * (-11) / 100;
1137}
1138
1139/**
bb8c093b 1140 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1141 */
bb8c093b 1142static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c
ZY		 1143{
1144 return (((temperature < -260) || (temperature > 25)) ? 1 : 0);
1145}
1146
bb8c093b 1147int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
b481de9c 1148{
bb8c093b 1149 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1150}
1151
1152/**
bb8c093b 1153 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1154 * get the current temperature by reading from NIC
1155*/
bb8c093b 1156static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
b481de9c
ZY		 1157{
1158 int temperature;
1159
bb8c093b 1160 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1161
1162 /* driver's okay range is -260 to +25.
1163 * human readable okay range is 0 to +285 */
1164 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1165
1166 /* handle insane temp reading */
bb8c093b 1167 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
b481de9c
ZY		 1168 IWL_ERROR("Error bad temperature value %d\n", temperature);
1169
1170 /* if really really hot(?),
1171 * substitute the 3rd band/group's temp measured at factory */
1172 if (priv->last_temperature > 100)
1173 temperature = priv->eeprom.groups[2].temperature;
1174 else /* else use most recent "sane" value from driver */
1175 temperature = priv->last_temperature;
1176 }
1177
1178 return temperature; /* raw, not "human readable" */
1179}
1180
1181/* Adjust Txpower only if temperature variance is greater than threshold.
1182 *
1183 * Both are lower than older versions' 9 degrees */
1184#define IWL_TEMPERATURE_LIMIT_TIMER 6
1185
1186/**
1187 * is_temp_calib_needed - determines if new calibration is needed
1188 *
1189 * records new temperature in tx_mgr->temperature.
1190 * replaces tx_mgr->last_temperature *only* if calib needed
1191 * (assumes caller will actually do the calibration!). */
bb8c093b 1192static int is_temp_calib_needed(struct iwl3945_priv *priv)
b481de9c
ZY		 1193{
1194 int temp_diff;
1195
bb8c093b 1196 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1197 temp_diff = priv->temperature - priv->last_temperature;
1198
1199 /* get absolute value */
1200 if (temp_diff < 0) {
1201 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1202 temp_diff = -temp_diff;
1203 } else if (temp_diff == 0)
1204 IWL_DEBUG_POWER("Same temp,\n");
1205 else
1206 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1207
1208 /* if we don't need calibration, *don't* update last_temperature */
1209 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1210 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1211 return 0;
1212 }
1213
1214 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1215
1216 /* assume that caller will actually do calib ...
1217 * update the "last temperature" value */
1218 priv->last_temperature = priv->temperature;
1219 return 1;
1220}
1221
1222#define IWL_MAX_GAIN_ENTRIES 78
1223#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1224#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1225
1226/* radio and DSP power table, each step is 1/2 dB.
1227 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1228static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1229 {
1230 {251, 127}, /* 2.4 GHz, highest power */
1231 {251, 127},
1232 {251, 127},
1233 {251, 127},
1234 {251, 125},
1235 {251, 110},
1236 {251, 105},
1237 {251, 98},
1238 {187, 125},
1239 {187, 115},
1240 {187, 108},
1241 {187, 99},
1242 {243, 119},
1243 {243, 111},
1244 {243, 105},
1245 {243, 97},
1246 {243, 92},
1247 {211, 106},
1248 {211, 100},
1249 {179, 120},
1250 {179, 113},
1251 {179, 107},
1252 {147, 125},
1253 {147, 119},
1254 {147, 112},
1255 {147, 106},
1256 {147, 101},
1257 {147, 97},
1258 {147, 91},
1259 {115, 107},
1260 {235, 121},
1261 {235, 115},
1262 {235, 109},
1263 {203, 127},
1264 {203, 121},
1265 {203, 115},
1266 {203, 108},
1267 {203, 102},
1268 {203, 96},
1269 {203, 92},
1270 {171, 110},
1271 {171, 104},
1272 {171, 98},
1273 {139, 116},
1274 {227, 125},
1275 {227, 119},
1276 {227, 113},
1277 {227, 107},
1278 {227, 101},
1279 {227, 96},
1280 {195, 113},
1281 {195, 106},
1282 {195, 102},
1283 {195, 95},
1284 {163, 113},
1285 {163, 106},
1286 {163, 102},
1287 {163, 95},
1288 {131, 113},
1289 {131, 106},
1290 {131, 102},
1291 {131, 95},
1292 {99, 113},
1293 {99, 106},
1294 {99, 102},
1295 {99, 95},
1296 {67, 113},
1297 {67, 106},
1298 {67, 102},
1299 {67, 95},
1300 {35, 113},
1301 {35, 106},
1302 {35, 102},
1303 {35, 95},
1304 {3, 113},
1305 {3, 106},
1306 {3, 102},
1307 {3, 95} }, /* 2.4 GHz, lowest power */
1308 {
1309 {251, 127}, /* 5.x GHz, highest power */
1310 {251, 120},
1311 {251, 114},
1312 {219, 119},
1313 {219, 101},
1314 {187, 113},
1315 {187, 102},
1316 {155, 114},
1317 {155, 103},
1318 {123, 117},
1319 {123, 107},
1320 {123, 99},
1321 {123, 92},
1322 {91, 108},
1323 {59, 125},
1324 {59, 118},
1325 {59, 109},
1326 {59, 102},
1327 {59, 96},
1328 {59, 90},
1329 {27, 104},
1330 {27, 98},
1331 {27, 92},
1332 {115, 118},
1333 {115, 111},
1334 {115, 104},
1335 {83, 126},
1336 {83, 121},
1337 {83, 113},
1338 {83, 105},
1339 {83, 99},
1340 {51, 118},
1341 {51, 111},
1342 {51, 104},
1343 {51, 98},
1344 {19, 116},
1345 {19, 109},
1346 {19, 102},
1347 {19, 98},
1348 {19, 93},
1349 {171, 113},
1350 {171, 107},
1351 {171, 99},
1352 {139, 120},
1353 {139, 113},
1354 {139, 107},
1355 {139, 99},
1356 {107, 120},
1357 {107, 113},
1358 {107, 107},
1359 {107, 99},
1360 {75, 120},
1361 {75, 113},
1362 {75, 107},
1363 {75, 99},
1364 {43, 120},
1365 {43, 113},
1366 {43, 107},
1367 {43, 99},
1368 {11, 120},
1369 {11, 113},
1370 {11, 107},
1371 {11, 99},
1372 {131, 107},
1373 {131, 99},
1374 {99, 120},
1375 {99, 113},
1376 {99, 107},
1377 {99, 99},
1378 {67, 120},
1379 {67, 113},
1380 {67, 107},
1381 {67, 99},
1382 {35, 120},
1383 {35, 113},
1384 {35, 107},
1385 {35, 99},
1386 {3, 120} } /* 5.x GHz, lowest power */
1387};
1388
bb8c093b 1389static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1390{
1391 if (index < 0)
1392 return 0;
1393 if (index >= IWL_MAX_GAIN_ENTRIES)
1394 return IWL_MAX_GAIN_ENTRIES - 1;
1395 return (u8) index;
1396}
1397
1398/* Kick off thermal recalibration check every 60 seconds */
1399#define REG_RECALIB_PERIOD (60)
1400
1401/**
bb8c093b 1402 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1403 *
1404 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1405 * or 6 Mbit (OFDM) rates.
1406 */
bb8c093b 1407static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
b481de9c 1408 s32 rate_index, const s8 *clip_pwrs,
bb8c093b 1409 struct iwl3945_channel_info *ch_info,
b481de9c
ZY		 1410 int band_index)
1411{
bb8c093b 1412 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1413 s8 power;
1414 u8 power_index;
1415
1416 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1417
1418 /* use this channel group's 6Mbit clipping/saturation pwr,
1419 * but cap at regulatory scan power restriction (set during init
1420 * based on eeprom channel data) for this channel. */
14577f23 1421 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1422
1423 /* further limit to user's max power preference.
1424 * FIXME: Other spectrum management power limitations do not
1425 * seem to apply?? */
1426 power = min(power, priv->user_txpower_limit);
1427 scan_power_info->requested_power = power;
1428
1429 /* find difference between new scan *power* and current "normal"
1430 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1431 * current "normal" temperature-compensated Tx power *index* for
1432 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1433 * *index*. */
1434 power_index = ch_info->power_info[rate_index].power_table_index
1435 - (power - ch_info->power_info
14577f23 1436 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1437
1438 /* store reference index that we use when adjusting *all* scan
1439 * powers. So we can accommodate user (all channel) or spectrum
1440 * management (single channel) power changes "between" temperature
1441 * feedback compensation procedures.
1442 * don't force fit this reference index into gain table; it may be a
1443 * negative number. This will help avoid errors when we're at
1444 * the lower bounds (highest gains, for warmest temperatures)
1445 * of the table. */
1446
1447 /* don't exceed table bounds for "real" setting */
bb8c093b 1448 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1449
1450 scan_power_info->power_table_index = power_index;
1451 scan_power_info->tpc.tx_gain =
1452 power_gain_table[band_index][power_index].tx_gain;
1453 scan_power_info->tpc.dsp_atten =
1454 power_gain_table[band_index][power_index].dsp_atten;
1455}
1456
1457/**
bb8c093b 1458 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1459 *
1460 * Configures power settings for all rates for the current channel,
1461 * using values from channel info struct, and send to NIC
1462 */
bb8c093b 1463int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
b481de9c 1464{
14577f23 1465 int rate_idx, i;
bb8c093b
CH		 1466 const struct iwl3945_channel_info *ch_info = NULL;
1467 struct iwl3945_txpowertable_cmd txpower = {
b481de9c
ZY		 1468 .channel = priv->active_rxon.channel,
1469 };
1470
1471 txpower.band = (priv->phymode == MODE_IEEE80211A) ? 0 : 1;
bb8c093b 1472 ch_info = iwl3945_get_channel_info(priv,
b481de9c
ZY		 1473 priv->phymode,
1474 le16_to_cpu(priv->active_rxon.channel));
1475 if (!ch_info) {
1476 IWL_ERROR
1477 ("Failed to get channel info for channel %d [%d]\n",
1478 le16_to_cpu(priv->active_rxon.channel), priv->phymode);
1479 return -EINVAL;
1480 }
1481
1482 if (!is_channel_valid(ch_info)) {
1483 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1484 "non-Tx channel.\n");
1485 return 0;
1486 }
1487
1488 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1489 /* Fill OFDM rate */
1490 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1491 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1492
1493 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1494 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1495
1496 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1497 le16_to_cpu(txpower.channel),
1498 txpower.band,
14577f23
MA		 1499 txpower.power[i].tpc.tx_gain,
1500 txpower.power[i].tpc.dsp_atten,
1501 txpower.power[i].rate);
1502 }
1503 /* Fill CCK rates */
1504 for (rate_idx = IWL_FIRST_CCK_RATE;
1505 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1506 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1507 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1508
1509 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1510 le16_to_cpu(txpower.channel),
1511 txpower.band,
1512 txpower.power[i].tpc.tx_gain,
1513 txpower.power[i].tpc.dsp_atten,
1514 txpower.power[i].rate);
b481de9c
ZY		 1515 }
1516
bb8c093b
CH		 1517 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1518 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1519
1520}
1521
1522/**
bb8c093b 1523 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1524 * @ch_info: Channel to update. Uses power_info.requested_power.
1525 *
1526 * Replace requested_power and base_power_index ch_info fields for
1527 * one channel.
1528 *
1529 * Called if user or spectrum management changes power preferences.
1530 * Takes into account h/w and modulation limitations (clip power).
1531 *
1532 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1533 *
1534 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1535 * properly fill out the scan powers, and actual h/w gain settings,
1536 * and send changes to NIC
1537 */
bb8c093b
CH		 1538static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1539 struct iwl3945_channel_info *ch_info)
b481de9c 1540{
bb8c093b 1541 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1542 int power_changed = 0;
1543 int i;
1544 const s8 *clip_pwrs;
1545 int power;
1546
1547 /* Get this chnlgrp's rate-to-max/clip-powers table */
1548 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1549
1550 /* Get this channel's rate-to-current-power settings table */
1551 power_info = ch_info->power_info;
1552
1553 /* update OFDM Txpower settings */
14577f23 1554 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1555 i++, ++power_info) {
1556 int delta_idx;
1557
1558 /* limit new power to be no more than h/w capability */
1559 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1560 if (power == power_info->requested_power)
1561 continue;
1562
1563 /* find difference between old and new requested powers,
1564 * update base (non-temp-compensated) power index */
1565 delta_idx = (power - power_info->requested_power) * 2;
1566 power_info->base_power_index -= delta_idx;
1567
1568 /* save new requested power value */
1569 power_info->requested_power = power;
1570
1571 power_changed = 1;
1572 }
1573
1574 /* update CCK Txpower settings, based on OFDM 12M setting ...
1575 * ... all CCK power settings for a given channel are the *same*. */
1576 if (power_changed) {
1577 power =
14577f23 1578 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1579 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1580
bb8c093b 1581 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1582 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1583 power_info->requested_power = power;
1584 power_info->base_power_index =
14577f23 1585 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1586 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1587 ++power_info;
1588 }
1589 }
1590
1591 return 0;
1592}
1593
1594/**
bb8c093b 1595 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1596 *
1597 * NOTE: Returned power limit may be less (but not more) than requested,
1598 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1599 * (no consideration for h/w clipping limitations).
1600 */
bb8c093b 1601static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
b481de9c
ZY		 1602{
1603 s8 max_power;
1604
1605#if 0
1606 /* if we're using TGd limits, use lower of TGd or EEPROM */
1607 if (ch_info->tgd_data.max_power != 0)
1608 max_power = min(ch_info->tgd_data.max_power,
1609 ch_info->eeprom.max_power_avg);
1610
1611 /* else just use EEPROM limits */
1612 else
1613#endif
1614 max_power = ch_info->eeprom.max_power_avg;
1615
1616 return min(max_power, ch_info->max_power_avg);
1617}
1618
1619/**
bb8c093b 1620 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1621 *
1622 * Compensate txpower settings of *all* channels for temperature.
1623 * This only accounts for the difference between current temperature
1624 * and the factory calibration temperatures, and bases the new settings
1625 * on the channel's base_power_index.
1626 *
1627 * If RxOn is "associated", this sends the new Txpower to NIC!
1628 */
bb8c093b 1629static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
b481de9c 1630{
bb8c093b 1631 struct iwl3945_channel_info *ch_info = NULL;
b481de9c
ZY		 1632 int delta_index;
1633 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1634 u8 a_band;
1635 u8 rate_index;
1636 u8 scan_tbl_index;
1637 u8 i;
1638 int ref_temp;
1639 int temperature = priv->temperature;
1640
1641 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1642 for (i = 0; i < priv->channel_count; i++) {
1643 ch_info = &priv->channel_info[i];
1644 a_band = is_channel_a_band(ch_info);
1645
1646 /* Get this chnlgrp's factory calibration temperature */
1647 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1648 temperature;
1649
1650 /* get power index adjustment based on curr and factory
1651 * temps */
bb8c093b 1652 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1653 ref_temp);
1654
1655 /* set tx power value for all rates, OFDM and CCK */
1656 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1657 rate_index++) {
1658 int power_idx =
1659 ch_info->power_info[rate_index].base_power_index;
1660
1661 /* temperature compensate */
1662 power_idx += delta_index;
1663
1664 /* stay within table range */
bb8c093b 1665 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1666 ch_info->power_info[rate_index].
1667 power_table_index = (u8) power_idx;
1668 ch_info->power_info[rate_index].tpc =
1669 power_gain_table[a_band][power_idx];
1670 }
1671
1672 /* Get this chnlgrp's rate-to-max/clip-powers table */
1673 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1674
1675 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1676 for (scan_tbl_index = 0;
1677 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1678 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1679 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1680 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1681 actual_index, clip_pwrs,
1682 ch_info, a_band);
1683 }
1684 }
1685
1686 /* send Txpower command for current channel to ucode */
bb8c093b 1687 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1688}
1689
bb8c093b 1690int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
b481de9c 1691{
bb8c093b 1692 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 1693 s8 max_power;
1694 u8 a_band;
1695 u8 i;
1696
1697 if (priv->user_txpower_limit == power) {
1698 IWL_DEBUG_POWER("Requested Tx power same as current "
1699 "limit: %ddBm.\n", power);
1700 return 0;
1701 }
1702
1703 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1704 priv->user_txpower_limit = power;
1705
1706 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1707
1708 for (i = 0; i < priv->channel_count; i++) {
1709 ch_info = &priv->channel_info[i];
1710 a_band = is_channel_a_band(ch_info);
1711
1712 /* find minimum power of all user and regulatory constraints
1713 * (does not consider h/w clipping limitations) */
bb8c093b 1714 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1715 max_power = min(power, max_power);
1716 if (max_power != ch_info->curr_txpow) {
1717 ch_info->curr_txpow = max_power;
1718
1719 /* this considers the h/w clipping limitations */
bb8c093b 1720 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1721 }
1722 }
1723
1724 /* update txpower settings for all channels,
1725 * send to NIC if associated. */
1726 is_temp_calib_needed(priv);
bb8c093b 1727 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1728
1729 return 0;
1730}
1731
1732/* will add 3945 channel switch cmd handling later */
bb8c093b 1733int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
b481de9c
ZY		 1734{
1735 return 0;
1736}
1737
1738/**
1739 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1740 *
1741 * -- reset periodic timer
1742 * -- see if temp has changed enough to warrant re-calibration ... if so:
1743 * -- correct coeffs for temp (can reset temp timer)
1744 * -- save this temp as "last",
1745 * -- send new set of gain settings to NIC
1746 * NOTE: This should continue working, even when we're not associated,
1747 * so we can keep our internal table of scan powers current. */
bb8c093b 1748void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
b481de9c
ZY		 1749{
1750 /* This will kick in the "brute force"
bb8c093b 1751 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1752 if (!is_temp_calib_needed(priv))
1753 goto reschedule;
1754
1755 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1756 * This is based *only* on current temperature,
1757 * ignoring any previous power measurements */
bb8c093b 1758 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1759
1760 reschedule:
1761 queue_delayed_work(priv->workqueue,
1762 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1763}
1764
416e1438 1765static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1766{
bb8c093b 1767 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
b481de9c
ZY		 1768 thermal_periodic.work);
1769
1770 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1771 return;
1772
1773 mutex_lock(&priv->mutex);
1774 iwl3945_reg_txpower_periodic(priv);
1775 mutex_unlock(&priv->mutex);
1776}
1777
1778/**
bb8c093b 1779 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 1780 * for the channel.
1781 *
1782 * This function is used when initializing channel-info structs.
1783 *
1784 * NOTE: These channel groups do *NOT* match the bands above!
1785 * These channel groups are based on factory-tested channels;
1786 * on A-band, EEPROM's "group frequency" entries represent the top
1787 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1788 */
bb8c093b
CH		 1789static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
1790 const struct iwl3945_channel_info *ch_info)
b481de9c 1791{
bb8c093b 1792 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
b481de9c
ZY		 1793 u8 group;
1794 u16 group_index = 0; /* based on factory calib frequencies */
1795 u8 grp_channel;
1796
1797 /* Find the group index for the channel ... don't use index 1(?) */
1798 if (is_channel_a_band(ch_info)) {
1799 for (group = 1; group < 5; group++) {
1800 grp_channel = ch_grp[group].group_channel;
1801 if (ch_info->channel <= grp_channel) {
1802 group_index = group;
1803 break;
1804 }
1805 }
1806 /* group 4 has a few channels *above* its factory cal freq */
1807 if (group == 5)
1808 group_index = 4;
1809 } else
1810 group_index = 0; /* 2.4 GHz, group 0 */
1811
1812 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
1813 group_index);
1814 return group_index;
1815}
1816
1817/**
bb8c093b 1818 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 1819 *
1820 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1821 * into radio/DSP gain settings table for requested power.
1822 */
bb8c093b 1823static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
b481de9c
ZY		 1824 s8 requested_power,
1825 s32 setting_index, s32 *new_index)
1826{
bb8c093b 1827 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 1828 s32 index0, index1;
1829 s32 power = 2 * requested_power;
1830 s32 i;
bb8c093b 1831 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 1832 s32 gains0, gains1;
1833 s32 res;
1834 s32 denominator;
1835
1836 chnl_grp = &priv->eeprom.groups[setting_index];
1837 samples = chnl_grp->samples;
1838 for (i = 0; i < 5; i++) {
1839 if (power == samples[i].power) {
1840 *new_index = samples[i].gain_index;
1841 return 0;
1842 }
1843 }
1844
1845 if (power > samples[1].power) {
1846 index0 = 0;
1847 index1 = 1;
1848 } else if (power > samples[2].power) {
1849 index0 = 1;
1850 index1 = 2;
1851 } else if (power > samples[3].power) {
1852 index0 = 2;
1853 index1 = 3;
1854 } else {
1855 index0 = 3;
1856 index1 = 4;
1857 }
1858
1859 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
1860 if (denominator == 0)
1861 return -EINVAL;
1862 gains0 = (s32) samples[index0].gain_index * (1 << 19);
1863 gains1 = (s32) samples[index1].gain_index * (1 << 19);
1864 res = gains0 + (gains1 - gains0) *
1865 ((s32) power - (s32) samples[index0].power) / denominator +
1866 (1 << 18);
1867 *new_index = res >> 19;
1868 return 0;
1869}
1870
bb8c093b 1871static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
b481de9c
ZY		 1872{
1873 u32 i;
1874 s32 rate_index;
bb8c093b 1875 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 1876
1877 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
1878
1879 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
1880 s8 *clip_pwrs; /* table of power levels for each rate */
1881 s8 satur_pwr; /* saturation power for each chnl group */
1882 group = &priv->eeprom.groups[i];
1883
1884 /* sanity check on factory saturation power value */
1885 if (group->saturation_power < 40) {
1886 IWL_WARNING("Error: saturation power is %d, "
1887 "less than minimum expected 40\n",
1888 group->saturation_power);
1889 return;
1890 }
1891
1892 /*
1893 * Derive requested power levels for each rate, based on
1894 * hardware capabilities (saturation power for band).
1895 * Basic value is 3dB down from saturation, with further
1896 * power reductions for highest 3 data rates. These
1897 * backoffs provide headroom for high rate modulation
1898 * power peaks, without too much distortion (clipping).
1899 */
1900 /* we'll fill in this array with h/w max power levels */
1901 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
1902
1903 /* divide factory saturation power by 2 to find -3dB level */
1904 satur_pwr = (s8) (group->saturation_power >> 1);
1905
1906 /* fill in channel group's nominal powers for each rate */
1907 for (rate_index = 0;
1908 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
1909 switch (rate_index) {
14577f23 1910 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 1911 if (i == 0) /* B/G */
1912 *clip_pwrs = satur_pwr;
1913 else /* A */
1914 *clip_pwrs = satur_pwr - 5;
1915 break;
14577f23 1916 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 1917 if (i == 0)
1918 *clip_pwrs = satur_pwr - 7;
1919 else
1920 *clip_pwrs = satur_pwr - 10;
1921 break;
14577f23 1922 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 1923 if (i == 0)
1924 *clip_pwrs = satur_pwr - 9;
1925 else
1926 *clip_pwrs = satur_pwr - 12;
1927 break;
1928 default:
1929 *clip_pwrs = satur_pwr;
1930 break;
1931 }
1932 }
1933 }
1934}
1935
1936/**
1937 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
1938 *
1939 * Second pass (during init) to set up priv->channel_info
1940 *
1941 * Set up Tx-power settings in our channel info database for each VALID
1942 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
1943 * and current temperature.
1944 *
1945 * Since this is based on current temperature (at init time), these values may
1946 * not be valid for very long, but it gives us a starting/default point,
1947 * and allows us to active (i.e. using Tx) scan.
1948 *
1949 * This does *not* write values to NIC, just sets up our internal table.
1950 */
bb8c093b 1951int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
b481de9c 1952{
bb8c093b
CH		 1953 struct iwl3945_channel_info *ch_info = NULL;
1954 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 1955 int delta_index;
1956 u8 rate_index;
1957 u8 scan_tbl_index;
1958 const s8 *clip_pwrs; /* array of power levels for each rate */
1959 u8 gain, dsp_atten;
1960 s8 power;
1961 u8 pwr_index, base_pwr_index, a_band;
1962 u8 i;
1963 int temperature;
1964
1965 /* save temperature reference,
1966 * so we can determine next time to calibrate */
bb8c093b 1967 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1968 priv->last_temperature = temperature;
1969
bb8c093b 1970 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 1971
1972 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
1973 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
1974 i++, ch_info++) {
1975 a_band = is_channel_a_band(ch_info);
1976 if (!is_channel_valid(ch_info))
1977 continue;
1978
1979 /* find this channel's channel group (*not* "band") index */
1980 ch_info->group_index =
bb8c093b 1981 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 1982
1983 /* Get this chnlgrp's rate->max/clip-powers table */
1984 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1985
1986 /* calculate power index *adjustment* value according to
1987 * diff between current temperature and factory temperature */
bb8c093b 1988 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1989 priv->eeprom.groups[ch_info->group_index].
1990 temperature);
1991
1992 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
1993 ch_info->channel, delta_index, temperature +
1994 IWL_TEMP_CONVERT);
1995
1996 /* set tx power value for all OFDM rates */
1997 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
1998 rate_index++) {
1999 s32 power_idx;
2000 int rc;
2001
2002 /* use channel group's clip-power table,
2003 * but don't exceed channel's max power */
2004 s8 pwr = min(ch_info->max_power_avg,
2005 clip_pwrs[rate_index]);
2006
2007 pwr_info = &ch_info->power_info[rate_index];
2008
2009 /* get base (i.e. at factory-measured temperature)
2010 * power table index for this rate's power */
bb8c093b 2011 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2012 ch_info->group_index,
2013 &power_idx);
2014 if (rc) {
2015 IWL_ERROR("Invalid power index\n");
2016 return rc;
2017 }
2018 pwr_info->base_power_index = (u8) power_idx;
2019
2020 /* temperature compensate */
2021 power_idx += delta_index;
2022
2023 /* stay within range of gain table */
bb8c093b 2024 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2025
bb8c093b 2026 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2027 pwr_info->requested_power = pwr;
2028 pwr_info->power_table_index = (u8) power_idx;
2029 pwr_info->tpc.tx_gain =
2030 power_gain_table[a_band][power_idx].tx_gain;
2031 pwr_info->tpc.dsp_atten =
2032 power_gain_table[a_band][power_idx].dsp_atten;
2033 }
2034
2035 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2036 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2037 power = pwr_info->requested_power +
2038 IWL_CCK_FROM_OFDM_POWER_DIFF;
2039 pwr_index = pwr_info->power_table_index +
2040 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2041 base_pwr_index = pwr_info->base_power_index +
2042 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2043
2044 /* stay within table range */
bb8c093b 2045 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2046 gain = power_gain_table[a_band][pwr_index].tx_gain;
2047 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2048
bb8c093b 2049 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2050 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2051 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2052 for (rate_index = 0;
2053 rate_index < IWL_CCK_RATES; rate_index++) {
2054 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2055 pwr_info->requested_power = power;
2056 pwr_info->power_table_index = pwr_index;
2057 pwr_info->base_power_index = base_pwr_index;
2058 pwr_info->tpc.tx_gain = gain;
2059 pwr_info->tpc.dsp_atten = dsp_atten;
2060 }
2061
2062 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2063 for (scan_tbl_index = 0;
2064 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2065 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2066 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2067 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2068 actual_index, clip_pwrs, ch_info, a_band);
2069 }
2070 }
2071
2072 return 0;
2073}
2074
bb8c093b 2075int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 2076{
2077 int rc;
2078 unsigned long flags;
2079
2080 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2081 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2082 if (rc) {
2083 spin_unlock_irqrestore(&priv->lock, flags);
2084 return rc;
2085 }
2086
bb8c093b
CH		 2087 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2088 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
b481de9c
ZY		 2089 if (rc < 0)
2090 IWL_ERROR("Can't stop Rx DMA.\n");
2091
bb8c093b 2092 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2093 spin_unlock_irqrestore(&priv->lock, flags);
2094
2095 return 0;
2096}
2097
bb8c093b 2098int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2099{
2100 int rc;
2101 unsigned long flags;
2102 int txq_id = txq->q.id;
2103
bb8c093b 2104 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2105
2106 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2107
2108 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2109 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2110 if (rc) {
2111 spin_unlock_irqrestore(&priv->lock, flags);
2112 return rc;
2113 }
bb8c093b
CH		 2114 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2115 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
b481de9c 2116
bb8c093b 2117 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
b481de9c
ZY		 2118 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2119 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2120 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2121 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2122 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
bb8c093b 2123 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2124
2125 /* fake read to flush all prev. writes */
bb8c093b 2126 iwl3945_read32(priv, FH_TSSR_CBB_BASE);
b481de9c
ZY		 2127 spin_unlock_irqrestore(&priv->lock, flags);
2128
2129 return 0;
2130}
2131
bb8c093b 2132int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
b481de9c 2133{
bb8c093b 2134 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2135
2136 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2137}
2138
2139/**
2140 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2141 */
bb8c093b 2142int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
b481de9c 2143{
14577f23 2144 int rc, i, index, prev_index;
bb8c093b 2145 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2146 .reserved = {0, 0, 0},
2147 };
bb8c093b 2148 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2149
bb8c093b
CH		 2150 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2151 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2152
2153 table[index].rate_n_flags =
bb8c093b 2154 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2155 table[index].try_cnt = priv->retry_rate;
bb8c093b
CH		 2156 prev_index = iwl3945_get_prev_ieee_rate(i);
2157 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2158 }
2159
2160 switch (priv->phymode) {
2161 case MODE_IEEE80211A:
2162 IWL_DEBUG_RATE("Select A mode rate scale\n");
2163 /* If one of the following CCK rates is used,
2164 * have it fall back to the 6M OFDM rate */
14577f23 2165 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
bb8c093b 2166 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2167
2168 /* Don't fall back to CCK rates */
14577f23 2169 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2170
2171 /* Don't drop out of OFDM rates */
14577f23 2172 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2173 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2174 break;
2175
2176 case MODE_IEEE80211B:
2177 IWL_DEBUG_RATE("Select B mode rate scale\n");
2178 /* If an OFDM rate is used, have it fall back to the
2179 * 1M CCK rates */
14577f23 2180 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
bb8c093b 2181 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
b481de9c
ZY		 2182
2183 /* CCK shouldn't fall back to OFDM... */
14577f23 2184 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
b481de9c
ZY		 2185 break;
2186
2187 default:
2188 IWL_DEBUG_RATE("Select G mode rate scale\n");
2189 break;
2190 }
2191
2192 /* Update the rate scaling for control frame Tx */
2193 rate_cmd.table_id = 0;
bb8c093b 2194 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2195 &rate_cmd);
2196 if (rc)
2197 return rc;
2198
2199 /* Update the rate scaling for data frame Tx */
2200 rate_cmd.table_id = 1;
bb8c093b 2201 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2202 &rate_cmd);
2203}
2204
bb8c093b 2205int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 2206{
2207 memset((void *)&priv->hw_setting, 0,
bb8c093b 2208 sizeof(struct iwl3945_driver_hw_info));
b481de9c
ZY		 2209
2210 priv->hw_setting.shared_virt =
2211 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2212 sizeof(struct iwl3945_shared),
b481de9c
ZY		 2213 &priv->hw_setting.shared_phys);
2214
2215 if (!priv->hw_setting.shared_virt) {
2216 IWL_ERROR("failed to allocate pci memory\n");
2217 mutex_unlock(&priv->mutex);
2218 return -ENOMEM;
2219 }
2220
2221 priv->hw_setting.ac_queue_count = AC_NUM;
2222 priv->hw_setting.rx_buffer_size = IWL_RX_BUF_SIZE;
bb8c093b 2223 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
b481de9c
ZY		 2224 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2225 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
b481de9c
ZY		 2226 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2227 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
2228 return 0;
2229}
2230
bb8c093b
CH		 2231unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2232 struct iwl3945_frame *frame, u8 rate)
b481de9c 2233{
bb8c093b 2234 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2235 unsigned int frame_size;
2236
bb8c093b 2237 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2238 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2239
2240 tx_beacon_cmd->tx.sta_id = IWL3945_BROADCAST_ID;
2241 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2242
bb8c093b 2243 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2244 tx_beacon_cmd->frame,
bb8c093b 2245 iwl3945_broadcast_addr,
b481de9c
ZY		 2246 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2247
2248 BUG_ON(frame_size > MAX_MPDU_SIZE);
2249 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2250
2251 tx_beacon_cmd->tx.rate = rate;
2252 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2253 TX_CMD_FLG_TSF_MSK);
2254
14577f23
MA		 2255 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2256 tx_beacon_cmd->tx.supp_rates[0] =
2257 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2258
b481de9c 2259 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2260 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2261
bb8c093b 2262 return (sizeof(struct iwl3945_tx_beacon_cmd) + frame_size);
b481de9c
ZY		 2263}
2264
bb8c093b 2265void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
b481de9c
ZY		 2266{
2267 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2268}
2269
bb8c093b 2270void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2271{
2272 INIT_DELAYED_WORK(&priv->thermal_periodic,
2273 iwl3945_bg_reg_txpower_periodic);
2274}
2275
bb8c093b 2276void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2277{
2278 cancel_delayed_work(&priv->thermal_periodic);
2279}
2280
bb8c093b 2281struct pci_device_id iwl3945_hw_card_ids[] = {
3567c11d
ZY		 2282 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4222)},
2283 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4227)},
b481de9c
ZY		 2284 {0}
2285};
2286
bb8c093b 2287inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
b481de9c 2288{
bb8c093b 2289 _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
b481de9c
ZY		 2290 return 0;
2291}
2292
bb8c093b 2293MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux kernel - Deliverables
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