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iwl3945: use iwl_get_hw_mode
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
bddadf86 41#include "iwl-3945-fh.h"
600c0e11 42#include "iwl-commands.h"
b481de9c 43#include "iwl-3945.h"
5d08cd1d 44#include "iwl-helpers.h"
5747d47f 45#include "iwl-core.h"
d9829a67 46#include "iwl-agn-rs.h"
b481de9c
ZY		 47
48#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_##r##M_IEEE, \
51 IWL_RATE_##ip##M_INDEX, \
52 IWL_RATE_##in##M_INDEX, \
53 IWL_RATE_##rp##M_INDEX, \
54 IWL_RATE_##rn##M_INDEX, \
55 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 56 IWL_RATE_##np##M_INDEX, \
57 IWL_RATE_##r##M_INDEX_TABLE, \
58 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 59
60/*
61 * Parameter order:
62 * rate, prev rate, next rate, prev tgg rate, next tgg rate
63 *
64 * If there isn't a valid next or previous rate then INV is used which
65 * maps to IWL_RATE_INVALID
66 *
67 */
d9829a67 68const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 69 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
70 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
71 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
72 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 73 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
74 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
75 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
76 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
77 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
78 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
79 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
80 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 81};
82
bb8c093b 83/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 84#define IWL_EVT_DISABLE (0)
85#define IWL_EVT_DISABLE_SIZE (1532/32)
86
87/**
bb8c093b 88 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 89 *
90 * Disable an event by writing "1"s into "disable"
91 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
92 * Default values of 0 enable uCode events to be logged.
93 * Use for only special debugging. This function is just a placeholder as-is,
94 * you'll need to provide the special bits! ...
95 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 96void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 97{
af7cca2a 98 int ret;
b481de9c
ZY		 99 int i;
100 u32 base; /* SRAM address of event log header */
101 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
102 u32 array_size; /* # of u32 entries in array */
103 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
104 0x00000000, /* 31 - 0 Event id numbers */
105 0x00000000, /* 63 - 32 */
106 0x00000000, /* 95 - 64 */
107 0x00000000, /* 127 - 96 */
108 0x00000000, /* 159 - 128 */
109 0x00000000, /* 191 - 160 */
110 0x00000000, /* 223 - 192 */
111 0x00000000, /* 255 - 224 */
112 0x00000000, /* 287 - 256 */
113 0x00000000, /* 319 - 288 */
114 0x00000000, /* 351 - 320 */
115 0x00000000, /* 383 - 352 */
116 0x00000000, /* 415 - 384 */
117 0x00000000, /* 447 - 416 */
118 0x00000000, /* 479 - 448 */
119 0x00000000, /* 511 - 480 */
120 0x00000000, /* 543 - 512 */
121 0x00000000, /* 575 - 544 */
122 0x00000000, /* 607 - 576 */
123 0x00000000, /* 639 - 608 */
124 0x00000000, /* 671 - 640 */
125 0x00000000, /* 703 - 672 */
126 0x00000000, /* 735 - 704 */
127 0x00000000, /* 767 - 736 */
128 0x00000000, /* 799 - 768 */
129 0x00000000, /* 831 - 800 */
130 0x00000000, /* 863 - 832 */
131 0x00000000, /* 895 - 864 */
132 0x00000000, /* 927 - 896 */
133 0x00000000, /* 959 - 928 */
134 0x00000000, /* 991 - 960 */
135 0x00000000, /* 1023 - 992 */
136 0x00000000, /* 1055 - 1024 */
137 0x00000000, /* 1087 - 1056 */
138 0x00000000, /* 1119 - 1088 */
139 0x00000000, /* 1151 - 1120 */
140 0x00000000, /* 1183 - 1152 */
141 0x00000000, /* 1215 - 1184 */
142 0x00000000, /* 1247 - 1216 */
143 0x00000000, /* 1279 - 1248 */
144 0x00000000, /* 1311 - 1280 */
145 0x00000000, /* 1343 - 1312 */
146 0x00000000, /* 1375 - 1344 */
147 0x00000000, /* 1407 - 1376 */
148 0x00000000, /* 1439 - 1408 */
149 0x00000000, /* 1471 - 1440 */
150 0x00000000, /* 1503 - 1472 */
151 };
152
153 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 154 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 155 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 156 return;
157 }
158
5d49f498 159 ret = iwl_grab_nic_access(priv);
af7cca2a 160 if (ret) {
39aadf8c 161 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY		 162 return;
163 }
164
5d49f498
AK		 165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
167 iwl_release_nic_access(priv);
b481de9c
ZY		 168
169 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
170 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
171 disable_ptr);
5d49f498 172 ret = iwl_grab_nic_access(priv);
b481de9c 173 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 174 iwl_write_targ_mem(priv,
af7cca2a
TW		 175 disable_ptr + (i * sizeof(u32)),
176 evt_disable[i]);
b481de9c 177
5d49f498 178 iwl_release_nic_access(priv);
b481de9c
ZY		 179 } else {
180 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
181 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
182 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
183 disable_ptr, array_size);
184 }
185
186}
187
17744ff6
TW		 188static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
189{
190 int idx;
191
192 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
193 if (iwl3945_rates[idx].plcp == plcp)
194 return idx;
195 return -1;
196}
197
b481de9c
ZY		 198/**
199 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
200 * @priv: eeprom and antenna fields are used to determine antenna flags
201 *
f2c7e521 202 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
b481de9c
ZY		 203 * priv->antenna specifies the antenna diversity mode:
204 *
a96a27f9 205 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
b481de9c
ZY		 206 * IWL_ANTENNA_MAIN - Force MAIN antenna
207 * IWL_ANTENNA_AUX - Force AUX antenna
208 */
4a8a4322 209__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
b481de9c
ZY		 210{
211 switch (priv->antenna) {
212 case IWL_ANTENNA_DIVERSITY:
213 return 0;
214
215 case IWL_ANTENNA_MAIN:
f2c7e521 216 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 217 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
218 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
219
220 case IWL_ANTENNA_AUX:
f2c7e521 221 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 222 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
223 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
224 }
225
226 /* bad antenna selector value */
15b1687c 227 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna);
b481de9c
ZY		 228 return 0; /* "diversity" is default if error */
229}
230
91c066f2
TW		 231#ifdef CONFIG_IWL3945_DEBUG
232#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
233
234static const char *iwl3945_get_tx_fail_reason(u32 status)
235{
236 switch (status & TX_STATUS_MSK) {
237 case TX_STATUS_SUCCESS:
238 return "SUCCESS";
239 TX_STATUS_ENTRY(SHORT_LIMIT);
240 TX_STATUS_ENTRY(LONG_LIMIT);
241 TX_STATUS_ENTRY(FIFO_UNDERRUN);
242 TX_STATUS_ENTRY(MGMNT_ABORT);
243 TX_STATUS_ENTRY(NEXT_FRAG);
244 TX_STATUS_ENTRY(LIFE_EXPIRE);
245 TX_STATUS_ENTRY(DEST_PS);
246 TX_STATUS_ENTRY(ABORTED);
247 TX_STATUS_ENTRY(BT_RETRY);
248 TX_STATUS_ENTRY(STA_INVALID);
249 TX_STATUS_ENTRY(FRAG_DROPPED);
250 TX_STATUS_ENTRY(TID_DISABLE);
251 TX_STATUS_ENTRY(FRAME_FLUSHED);
252 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
253 TX_STATUS_ENTRY(TX_LOCKED);
254 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
255 }
256
257 return "UNKNOWN";
258}
259#else
260static inline const char *iwl3945_get_tx_fail_reason(u32 status)
261{
262 return "";
263}
264#endif
265
e6a9854b
JB		 266/*
267 * get ieee prev rate from rate scale table.
268 * for A and B mode we need to overright prev
269 * value
270 */
4a8a4322 271int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 272{
273 int next_rate = iwl3945_get_prev_ieee_rate(rate);
274
275 switch (priv->band) {
276 case IEEE80211_BAND_5GHZ:
277 if (rate == IWL_RATE_12M_INDEX)
278 next_rate = IWL_RATE_9M_INDEX;
279 else if (rate == IWL_RATE_6M_INDEX)
280 next_rate = IWL_RATE_6M_INDEX;
281 break;
7262796a
AM		 282 case IEEE80211_BAND_2GHZ:
283 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
284 iwl3945_is_associated(priv)) {
285 if (rate == IWL_RATE_11M_INDEX)
286 next_rate = IWL_RATE_5M_INDEX;
287 }
e6a9854b 288 break;
7262796a 289
e6a9854b
JB		 290 default:
291 break;
292 }
293
294 return next_rate;
295}
296
91c066f2
TW		 297
298/**
299 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
300 *
301 * When FW advances 'R' index, all entries between old and new 'R' index
302 * need to be reclaimed. As result, some free space forms. If there is
303 * enough free space (> low mark), wake the stack that feeds us.
304 */
4a8a4322 305static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 306 int txq_id, int index)
307{
f2c7e521 308 struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
d20b3c65 309 struct iwl_queue *q = &txq->q;
91c066f2
TW		 310 struct iwl3945_tx_info *tx_info;
311
312 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
313
314 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
315 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
316
317 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 318 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2
TW		 319 tx_info->skb[0] = NULL;
320 iwl3945_hw_txq_free_tfd(priv, txq);
321 }
322
d20b3c65 323 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 324 (txq_id != IWL_CMD_QUEUE_NUM) &&
325 priv->mac80211_registered)
326 ieee80211_wake_queue(priv->hw, txq_id);
327}
328
329/**
330 * iwl3945_rx_reply_tx - Handle Tx response
331 */
4a8a4322 332static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 333 struct iwl_rx_mem_buffer *rxb)
91c066f2 334{
3d24a9f7 335 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 336 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
337 int txq_id = SEQ_TO_QUEUE(sequence);
338 int index = SEQ_TO_INDEX(sequence);
f2c7e521 339 struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
e039fa4a 340 struct ieee80211_tx_info *info;
91c066f2
TW		 341 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
342 u32 status = le32_to_cpu(tx_resp->status);
343 int rate_idx;
74221d07 344 int fail;
91c066f2
TW		 345
346 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
15b1687c 347 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 348 "is out of range [0-%d] %d %d\n", txq_id,
349 index, txq->q.n_bd, txq->q.write_ptr,
350 txq->q.read_ptr);
351 return;
352 }
353
e039fa4a 354 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 355 ieee80211_tx_info_clear_status(info);
356
357 /* Fill the MRR chain with some info about on-chip retransmissions */
358 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
359 if (info->band == IEEE80211_BAND_5GHZ)
360 rate_idx -= IWL_FIRST_OFDM_RATE;
361
362 fail = tx_resp->failure_frame;
74221d07
AM		 363
364 info->status.rates[0].idx = rate_idx;
365 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 366
91c066f2 367 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 368 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
369 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 370
371 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
372 txq_id, iwl3945_get_tx_fail_reason(status), status,
373 tx_resp->rate, tx_resp->failure_frame);
374
91c066f2
TW		 375 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
376 iwl3945_tx_queue_reclaim(priv, txq_id, index);
377
378 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 379 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 380}
381
382
383
b481de9c
ZY		 384/*****************************************************************************
385 *
386 * Intel PRO/Wireless 3945ABG/BG Network Connection
387 *
388 * RX handler implementations
389 *
b481de9c
ZY		 390 *****************************************************************************/
391
4a8a4322 392void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 393{
3d24a9f7 394 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 395 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 396 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 397 le32_to_cpu(pkt->len));
398
f2c7e521 399 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 400
ab53d8af
MA		 401 iwl3945_led_background(priv);
402
b481de9c
ZY		 403 priv->last_statistics_time = jiffies;
404}
405
17744ff6
TW		 406/******************************************************************************
407 *
408 * Misc. internal state and helper functions
409 *
410 ******************************************************************************/
411#ifdef CONFIG_IWL3945_DEBUG
412
413/**
414 * iwl3945_report_frame - dump frame to syslog during debug sessions
415 *
416 * You may hack this function to show different aspects of received frames,
417 * including selective frame dumps.
418 * group100 parameter selects whether to show 1 out of 100 good frames.
419 */
4a8a4322 420static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 421 struct iwl_rx_packet *pkt,
17744ff6
TW		 422 struct ieee80211_hdr *header, int group100)
423{
424 u32 to_us;
425 u32 print_summary = 0;
426 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
427 u32 hundred = 0;
428 u32 dataframe = 0;
fd7c8a40 429 __le16 fc;
17744ff6
TW		 430 u16 seq_ctl;
431 u16 channel;
432 u16 phy_flags;
433 u16 length;
434 u16 status;
435 u16 bcn_tmr;
436 u32 tsf_low;
437 u64 tsf;
438 u8 rssi;
439 u8 agc;
440 u16 sig_avg;
441 u16 noise_diff;
442 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
443 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
444 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
445 u8 *data = IWL_RX_DATA(pkt);
446
447 /* MAC header */
fd7c8a40 448 fc = header->frame_control;
17744ff6
TW		 449 seq_ctl = le16_to_cpu(header->seq_ctrl);
450
451 /* metadata */
452 channel = le16_to_cpu(rx_hdr->channel);
453 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
454 length = le16_to_cpu(rx_hdr->len);
455
456 /* end-of-frame status and timestamp */
457 status = le32_to_cpu(rx_end->status);
458 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
459 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
460 tsf = le64_to_cpu(rx_end->timestamp);
461
462 /* signal statistics */
463 rssi = rx_stats->rssi;
464 agc = rx_stats->agc;
465 sig_avg = le16_to_cpu(rx_stats->sig_avg);
466 noise_diff = le16_to_cpu(rx_stats->noise_diff);
467
468 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
469
470 /* if data frame is to us and all is good,
471 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 472 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
473 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 474 dataframe = 1;
475 if (!group100)
476 print_summary = 1; /* print each frame */
477 else if (priv->framecnt_to_us < 100) {
478 priv->framecnt_to_us++;
479 print_summary = 0;
480 } else {
481 priv->framecnt_to_us = 0;
482 print_summary = 1;
483 hundred = 1;
484 }
485 } else {
486 /* print summary for all other frames */
487 print_summary = 1;
488 }
489
490 if (print_summary) {
491 char *title;
0ff1cca0 492 int rate;
17744ff6
TW		 493
494 if (hundred)
495 title = "100Frames";
fd7c8a40 496 else if (ieee80211_has_retry(fc))
17744ff6 497 title = "Retry";
fd7c8a40 498 else if (ieee80211_is_assoc_resp(fc))
17744ff6 499 title = "AscRsp";
fd7c8a40 500 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 501 title = "RasRsp";
fd7c8a40 502 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 503 title = "PrbRsp";
504 print_dump = 1; /* dump frame contents */
505 } else if (ieee80211_is_beacon(fc)) {
506 title = "Beacon";
507 print_dump = 1; /* dump frame contents */
508 } else if (ieee80211_is_atim(fc))
509 title = "ATIM";
510 else if (ieee80211_is_auth(fc))
511 title = "Auth";
512 else if (ieee80211_is_deauth(fc))
513 title = "DeAuth";
514 else if (ieee80211_is_disassoc(fc))
515 title = "DisAssoc";
516 else
517 title = "Frame";
518
519 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
520 if (rate == -1)
521 rate = 0;
522 else
523 rate = iwl3945_rates[rate].ieee / 2;
524
525 /* print frame summary.
526 * MAC addresses show just the last byte (for brevity),
527 * but you can hack it to show more, if you'd like to. */
528 if (dataframe)
529 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 530 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 531 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 532 length, rssi, channel, rate);
533 else {
534 /* src/dst addresses assume managed mode */
535 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
536 "src=0x%02x, rssi=%u, tim=%lu usec, "
537 "phy=0x%02x, chnl=%d\n",
fd7c8a40 538 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 539 header->addr3[5], rssi,
540 tsf_low - priv->scan_start_tsf,
541 phy_flags, channel);
542 }
543 }
544 if (print_dump)
40b8ec0b 545 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6
TW		 546}
547#else
4a8a4322 548static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 549 struct iwl_rx_packet *pkt,
17744ff6
TW		 550 struct ieee80211_hdr *header, int group100)
551{
552}
553#endif
554
4bd9b4f3 555/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 556static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 557 struct ieee80211_hdr *header)
558{
559 /* Filter incoming packets to determine if they are targeted toward
560 * this network, discarding packets coming from ourselves */
561 switch (priv->iw_mode) {
05c914fe 562 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 563 /* packets to our IBSS update information */
564 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 565 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 566 /* packets to our IBSS update information */
567 return !compare_ether_addr(header->addr2, priv->bssid);
568 default:
569 return 1;
570 }
571}
17744ff6 572
4a8a4322 573static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 574 struct iwl_rx_mem_buffer *rxb,
12342c47 575 struct ieee80211_rx_status *stats)
b481de9c 576{
3d24a9f7 577 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
699669f3 578#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 579 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 580#endif
bb8c093b
CH		 581 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
582 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 583 short len = le16_to_cpu(rx_hdr->len);
584
585 /* We received data from the HW, so stop the watchdog */
3d24a9f7 586 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
b481de9c
ZY		 587 IWL_DEBUG_DROP("Corruption detected!\n");
588 return;
589 }
590
591 /* We only process data packets if the interface is open */
592 if (unlikely(!priv->is_open)) {
593 IWL_DEBUG_DROP_LIMIT
594 ("Dropping packet while interface is not open.\n");
595 return;
596 }
b481de9c
ZY		 597
598 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
599 /* Set the size of the skb to the size of the frame */
600 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
601
df878d8f 602 if (iwl3945_mod_params.sw_crypto)
bb8c093b 603 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 604 le32_to_cpu(rx_end->status), stats);
605
ab53d8af 606#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 607 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 608 priv->rxtxpackets += len;
609#endif
b481de9c
ZY		 610 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
611 rxb->skb = NULL;
612}
613
7878a5a4
MA		 614#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
615
4a8a4322 616static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 617 struct iwl_rx_mem_buffer *rxb)
b481de9c 618{
17744ff6
TW		 619 struct ieee80211_hdr *header;
620 struct ieee80211_rx_status rx_status;
3d24a9f7 621 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 622 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
623 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
624 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 625 int snr;
b481de9c
ZY		 626 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
627 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 628 u8 network_packet;
17744ff6 629
17744ff6
TW		 630 rx_status.flag = 0;
631 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 632 rx_status.freq =
c0186078 633 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 634 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
635 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
636
637 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 638 if (rx_status.band == IEEE80211_BAND_5GHZ)
639 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 640
6f0a2c4d
BR		 641 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
642 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
643
644 /* set the preamble flag if appropriate */
645 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
646 rx_status.flag |= RX_FLAG_SHORTPRE;
647
b481de9c
ZY		 648 if ((unlikely(rx_stats->phy_count > 20))) {
649 IWL_DEBUG_DROP
650 ("dsp size out of range [0,20]: "
651 "%d/n", rx_stats->phy_count);
652 return;
653 }
654
655 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
656 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
657 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
658 return;
659 }
660
56decd3c 661
b481de9c
ZY		 662
663 /* Convert 3945's rssi indicator to dBm */
250bdd21 664 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 665
666 /* Set default noise value to -127 */
667 if (priv->last_rx_noise == 0)
668 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
669
670 /* 3945 provides noise info for OFDM frames only.
671 * sig_avg and noise_diff are measured by the 3945's digital signal
672 * processor (DSP), and indicate linear levels of signal level and
673 * distortion/noise within the packet preamble after
674 * automatic gain control (AGC). sig_avg should stay fairly
675 * constant if the radio's AGC is working well.
676 * Since these values are linear (not dB or dBm), linear
677 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
678 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
679 * to obtain noise level in dBm.
17744ff6 680 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 681 if (rx_stats_noise_diff) {
682 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 683 rx_status.noise = rx_status.signal -
17744ff6 684 iwl3945_calc_db_from_ratio(snr);
566bfe5a 685 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 686 rx_status.noise);
b481de9c
ZY		 687
688 /* If noise info not available, calculate signal quality indicator (%)
689 * using just the dBm signal level. */
690 } else {
17744ff6 691 rx_status.noise = priv->last_rx_noise;
566bfe5a 692 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 693 }
694
695
696 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 697 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 698 rx_stats_sig_avg, rx_stats_noise_diff);
699
b481de9c
ZY		 700 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
701
bb8c093b 702 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 703
17744ff6
TW		 704 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
705 network_packet ? '*' : ' ',
706 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 707 rx_status.signal, rx_status.signal,
708 rx_status.noise, rx_status.rate_idx);
b481de9c 709
17744ff6 710#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 711 if (priv->debug_level & (IWL_DL_RX))
b481de9c 712 /* Set "1" to report good data frames in groups of 100 */
17744ff6 713 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 714#endif
715
716 if (network_packet) {
717 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
718 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 719 priv->last_rx_rssi = rx_status.signal;
17744ff6 720 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 721 }
722
12e5e22d 723 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 724}
725
4a8a4322 726int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 727 dma_addr_t addr, u16 len)
728{
729 int count;
730 u32 pad;
bb8c093b 731 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 732
733 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
734 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
735
736 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 737 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 738 NUM_TFD_CHUNKS);
739 return -EINVAL;
740 }
741
742 tfd->pa[count].addr = cpu_to_le32(addr);
743 tfd->pa[count].len = cpu_to_le32(len);
744
745 count++;
746
747 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
748 TFD_CTL_PAD_SET(pad));
749
750 return 0;
751}
752
753/**
bb8c093b 754 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 755 *
756 * Does NOT advance any indexes
757 */
4a8a4322 758int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 759{
bb8c093b
CH		 760 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
761 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 762 struct pci_dev *dev = priv->pci_dev;
763 int i;
764 int counter;
765
766 /* classify bd */
767 if (txq->q.id == IWL_CMD_QUEUE_NUM)
768 /* nothing to cleanup after for host commands */
769 return 0;
770
771 /* sanity check */
772 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
773 if (counter > NUM_TFD_CHUNKS) {
15b1687c 774 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c
ZY		 775 /* @todo issue fatal error, it is quite serious situation */
776 return 0;
777 }
778
779 /* unmap chunks if any */
780
781 for (i = 1; i < counter; i++) {
782 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
783 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 784 if (txq->txb[txq->q.read_ptr].skb[0]) {
785 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
786 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 787 /* Can be called from interrupt context */
788 dev_kfree_skb_any(skb);
fc4b6853 789 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 790 }
791 }
792 }
793 return 0;
794}
795
4a8a4322 796u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c 797{
c93007ef 798 int i, start = IWL_AP_ID;
b481de9c
ZY		 799 int ret = IWL_INVALID_STATION;
800 unsigned long flags;
801
c93007ef
SO		 802 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
803 (priv->iw_mode == NL80211_IFTYPE_AP))
804 start = IWL_STA_ID;
805
806 if (is_broadcast_ether_addr(addr))
3832ec9d 807 return priv->hw_params.bcast_sta_id;
c93007ef 808
b481de9c 809 spin_lock_irqsave(&priv->sta_lock, flags);
3832ec9d 810 for (i = start; i < priv->hw_params.max_stations; i++)
f2c7e521 811 if ((priv->stations_39[i].used) &&
b481de9c 812 (!compare_ether_addr
f2c7e521 813 (priv->stations_39[i].sta.sta.addr, addr))) {
b481de9c
ZY		 814 ret = i;
815 goto out;
816 }
817
e174961c
JB		 818 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
819 addr, priv->num_stations);
b481de9c
ZY		 820 out:
821 spin_unlock_irqrestore(&priv->sta_lock, flags);
822 return ret;
823}
824
825/**
bb8c093b 826 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 827 *
828*/
c2d79b48 829void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
e039fa4a 830 struct ieee80211_tx_info *info,
b481de9c
ZY		 831 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
832{
e039fa4a 833 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 834 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 835 u16 rate_mask;
836 int rate;
837 u8 rts_retry_limit;
838 u8 data_retry_limit;
839 __le32 tx_flags;
fd7c8a40 840 __le16 fc = hdr->frame_control;
c2d79b48 841 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 842
bb8c093b 843 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 844 tx_flags = tx->tx_flags;
b481de9c
ZY		 845
846 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 847 * in this running context */
b481de9c
ZY		 848 rate_mask = IWL_RATES_MASK;
849
b481de9c
ZY		 850 if (tx_id >= IWL_CMD_QUEUE_NUM)
851 rts_retry_limit = 3;
852 else
853 rts_retry_limit = 7;
854
fd7c8a40 855 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 856 data_retry_limit = 3;
857 if (data_retry_limit < rts_retry_limit)
858 rts_retry_limit = data_retry_limit;
859 } else
860 data_retry_limit = IWL_DEFAULT_TX_RETRY;
861
862 if (priv->data_retry_limit != -1)
863 data_retry_limit = priv->data_retry_limit;
864
fd7c8a40
HH		 865 if (ieee80211_is_mgmt(fc)) {
866 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
867 case cpu_to_le16(IEEE80211_STYPE_AUTH):
868 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
869 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
870 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 871 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
872 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
873 tx_flags |= TX_CMD_FLG_CTS_MSK;
874 }
875 break;
876 default:
877 break;
878 }
879 }
880
c2d79b48
WT		 881 tx->rts_retry_limit = rts_retry_limit;
882 tx->data_retry_limit = data_retry_limit;
883 tx->rate = rate;
884 tx->tx_flags = tx_flags;
b481de9c
ZY		 885
886 /* OFDM */
c2d79b48 887 tx->supp_rates[0] =
14577f23 888 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 889
890 /* CCK */
c2d79b48 891 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 892
893 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
894 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 895 tx->rate, le32_to_cpu(tx->tx_flags),
896 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 897}
898
4a8a4322 899u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 900{
901 unsigned long flags_spin;
bb8c093b 902 struct iwl3945_station_entry *station;
b481de9c
ZY		 903
904 if (sta_id == IWL_INVALID_STATION)
905 return IWL_INVALID_STATION;
906
907 spin_lock_irqsave(&priv->sta_lock, flags_spin);
f2c7e521 908 station = &priv->stations_39[sta_id];
b481de9c
ZY		 909
910 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
911 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 912 station->sta.mode = STA_CONTROL_MODIFY_MSK;
913
914 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
915
bb8c093b 916 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 917 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
918 sta_id, tx_rate);
919 return sta_id;
920}
921
854682ed 922static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c
ZY		 923{
924 int rc;
925 unsigned long flags;
926
927 spin_lock_irqsave(&priv->lock, flags);
5d49f498 928 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 929 if (rc) {
930 spin_unlock_irqrestore(&priv->lock, flags);
931 return rc;
932 }
933
854682ed 934 if (src == IWL_PWR_SRC_VAUX) {
b481de9c
ZY		 935 u32 val;
936
937 rc = pci_read_config_dword(priv->pci_dev,
938 PCI_POWER_SOURCE, &val);
939 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
5d49f498 940 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 941 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
942 ~APMG_PS_CTRL_MSK_PWR_SRC);
5d49f498 943 iwl_release_nic_access(priv);
b481de9c 944
5d49f498 945 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 946 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
947 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
948 } else
5d49f498 949 iwl_release_nic_access(priv);
b481de9c 950 } else {
5d49f498 951 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 952 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
953 ~APMG_PS_CTRL_MSK_PWR_SRC);
954
5d49f498
AK		 955 iwl_release_nic_access(priv);
956 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 957 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
958 }
959 spin_unlock_irqrestore(&priv->lock, flags);
960
961 return rc;
962}
963
4a8a4322 964static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY		 965{
966 int rc;
967 unsigned long flags;
968
969 spin_lock_irqsave(&priv->lock, flags);
5d49f498 970 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 971 if (rc) {
972 spin_unlock_irqrestore(&priv->lock, flags);
973 return rc;
974 }
975
5d49f498
AK		 976 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
977 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
3832ec9d 978 priv->shared_phys +
bb8c093b 979 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
5d49f498
AK		 980 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
981 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 982 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
983 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
984 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
985 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
986 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
987 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
988 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
989 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 990
991 /* fake read to flush all prev I/O */
5d49f498 992 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 993
5d49f498 994 iwl_release_nic_access(priv);
b481de9c
ZY		 995 spin_unlock_irqrestore(&priv->lock, flags);
996
997 return 0;
998}
999
4a8a4322 1000static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1001{
1002 int rc;
1003 unsigned long flags;
1004
1005 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1006 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1007 if (rc) {
1008 spin_unlock_irqrestore(&priv->lock, flags);
1009 return rc;
1010 }
1011
1012 /* bypass mode */
5d49f498 1013 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1014
1015 /* RA 0 is active */
5d49f498 1016 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1017
1018 /* all 6 fifo are active */
5d49f498 1019 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1020
5d49f498
AK		 1021 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1022 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1023 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1024 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1025
5d49f498 1026 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 1027 priv->shared_phys);
b481de9c 1028
5d49f498 1029 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 1030 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1031 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1032 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1033 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1034 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1035 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1036 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 1037
5d49f498 1038 iwl_release_nic_access(priv);
b481de9c
ZY		 1039 spin_unlock_irqrestore(&priv->lock, flags);
1040
1041 return 0;
1042}
1043
1044/**
1045 * iwl3945_txq_ctx_reset - Reset TX queue context
1046 *
1047 * Destroys all DMA structures and initialize them again
1048 */
4a8a4322 1049static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1050{
1051 int rc;
1052 int txq_id, slots_num;
1053
bb8c093b 1054 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1055
1056 /* Tx CMD queue */
1057 rc = iwl3945_tx_reset(priv);
1058 if (rc)
1059 goto error;
1060
1061 /* Tx queue(s) */
1062 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1063 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1064 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
f2c7e521 1065 rc = iwl3945_tx_queue_init(priv, &priv->txq39[txq_id], slots_num,
b481de9c
ZY		 1066 txq_id);
1067 if (rc) {
15b1687c 1068 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1069 goto error;
1070 }
1071 }
1072
1073 return rc;
1074
1075 error:
bb8c093b 1076 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1077 return rc;
1078}
1079
01ec616d 1080static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1081{
01ec616d 1082 int ret = 0;
b481de9c 1083
bb8c093b 1084 iwl3945_power_init_handle(priv);
b481de9c 1085
5d49f498 1086 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1087 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1088
1089 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1090 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1091 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1092
01ec616d
KA		 1093 /* set "initialization complete" bit to move adapter
1094 * D0U* --> D0A* state */
5d49f498 1095 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d
KA		 1096
1097 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1098 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1099 if (ret < 0) {
b481de9c 1100 IWL_DEBUG_INFO("Failed to init the card\n");
01ec616d 1101 goto out;
b481de9c
ZY		 1102 }
1103
01ec616d
KA		 1104 ret = iwl_grab_nic_access(priv);
1105 if (ret)
1106 goto out;
1107
1108 /* enable DMA */
1109 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1110 APMG_CLK_VAL_BSM_CLK_RQT);
1111
b481de9c 1112 udelay(20);
01ec616d
KA		 1113
1114 /* disable L1-Active */
5d49f498 1115 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1116 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1117
5d49f498 1118 iwl_release_nic_access(priv);
01ec616d
KA		 1119out:
1120 return ret;
1121}
b481de9c 1122
01ec616d
KA		 1123static void iwl3945_nic_config(struct iwl_priv *priv)
1124{
1125 unsigned long flags;
1126 u8 rev_id = 0;
b481de9c 1127
b481de9c
ZY		 1128 spin_lock_irqsave(&priv->lock, flags);
1129
1130 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1131 IWL_DEBUG_INFO("RTP type \n");
1132 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1133 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
5d49f498 1134 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1135 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1136 } else {
6f83eaa1 1137 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
5d49f498 1138 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1139 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1140 }
1141
f2c7e521 1142 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
b481de9c 1143 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
5d49f498 1144 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1145 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1146 } else
1147 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1148
f2c7e521 1149 if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
b481de9c 1150 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1151 priv->eeprom39.board_revision);
5d49f498 1152 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1153 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1154 } else {
1155 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1156 priv->eeprom39.board_revision);
5d49f498 1157 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1158 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1159 }
1160
f2c7e521 1161 if (priv->eeprom39.almgor_m_version <= 1) {
5d49f498 1162 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1163 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c 1164 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
f2c7e521 1165 priv->eeprom39.almgor_m_version);
b481de9c
ZY		 1166 } else {
1167 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
f2c7e521 1168 priv->eeprom39.almgor_m_version);
5d49f498 1169 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1170 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1171 }
1172 spin_unlock_irqrestore(&priv->lock, flags);
1173
f2c7e521 1174 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 1175 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1176
f2c7e521 1177 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c 1178 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1179}
1180
1181int iwl3945_hw_nic_init(struct iwl_priv *priv)
1182{
1183 u8 rev_id;
1184 int rc;
1185 unsigned long flags;
1186 struct iwl_rx_queue *rxq = &priv->rxq;
1187
1188 spin_lock_irqsave(&priv->lock, flags);
1189 priv->cfg->ops->lib->apm_ops.init(priv);
1190 spin_unlock_irqrestore(&priv->lock, flags);
1191
1192 /* Determine HW type */
1193 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1194 if (rc)
1195 return rc;
1196 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1197
854682ed
KA		 1198 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1199 if(rc)
1200 return rc;
1201
01ec616d 1202 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1203
1204 /* Allocate the RX queue, or reset if it is already allocated */
1205 if (!rxq->bd) {
bb8c093b 1206 rc = iwl3945_rx_queue_alloc(priv);
b481de9c 1207 if (rc) {
15b1687c 1208 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1209 return -ENOMEM;
1210 }
1211 } else
bb8c093b 1212 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1213
bb8c093b 1214 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1215
1216 iwl3945_rx_init(priv, rxq);
1217
1218 spin_lock_irqsave(&priv->lock, flags);
1219
1220 /* Look at using this instead:
1221 rxq->need_update = 1;
bb8c093b 1222 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1223 */
1224
5d49f498 1225 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1226 if (rc) {
1227 spin_unlock_irqrestore(&priv->lock, flags);
1228 return rc;
1229 }
5d49f498
AK		 1230 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1231 iwl_release_nic_access(priv);
b481de9c
ZY		 1232
1233 spin_unlock_irqrestore(&priv->lock, flags);
1234
1235 rc = iwl3945_txq_ctx_reset(priv);
1236 if (rc)
1237 return rc;
1238
1239 set_bit(STATUS_INIT, &priv->status);
1240
1241 return 0;
1242}
1243
1244/**
bb8c093b 1245 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1246 *
1247 * Destroy all TX DMA queues and structures
1248 */
4a8a4322 1249void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1250{
1251 int txq_id;
1252
1253 /* Tx queues */
1254 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
f2c7e521 1255 iwl3945_tx_queue_free(priv, &priv->txq39[txq_id]);
b481de9c
ZY		 1256}
1257
4a8a4322 1258void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1259{
bddadf86 1260 int txq_id;
b481de9c
ZY		 1261 unsigned long flags;
1262
1263 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1264 if (iwl_grab_nic_access(priv)) {
b481de9c 1265 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1266 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1267 return;
1268 }
1269
1270 /* stop SCD */
5d49f498 1271 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1272
1273 /* reset TFD queues */
bddadf86 1274 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
5d49f498
AK		 1275 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1276 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1277 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1278 1000);
1279 }
1280
5d49f498 1281 iwl_release_nic_access(priv);
b481de9c
ZY		 1282 spin_unlock_irqrestore(&priv->lock, flags);
1283
bb8c093b 1284 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1285}
1286
01ec616d 1287static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1288{
01ec616d 1289 int ret = 0;
b481de9c
ZY		 1290 unsigned long flags;
1291
1292 spin_lock_irqsave(&priv->lock, flags);
1293
1294 /* set stop master bit */
5d49f498 1295 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1296
01ec616d
KA		 1297 iwl_poll_direct_bit(priv, CSR_RESET,
1298 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1299
01ec616d
KA		 1300 if (ret < 0)
1301 goto out;
b481de9c 1302
01ec616d 1303out:
b481de9c
ZY		 1304 spin_unlock_irqrestore(&priv->lock, flags);
1305 IWL_DEBUG_INFO("stop master\n");
1306
01ec616d
KA		 1307 return ret;
1308}
1309
1310static void iwl3945_apm_stop(struct iwl_priv *priv)
1311{
1312 unsigned long flags;
1313
1314 iwl3945_apm_stop_master(priv);
1315
1316 spin_lock_irqsave(&priv->lock, flags);
1317
1318 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1319
1320 udelay(10);
1321 /* clear "init complete" move adapter D0A* --> D0U state */
1322 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1323 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1324}
1325
01ec616d 1326int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c
ZY		 1327{
1328 int rc;
1329 unsigned long flags;
1330
01ec616d 1331 iwl3945_apm_stop_master(priv);
b481de9c
ZY		 1332
1333 spin_lock_irqsave(&priv->lock, flags);
1334
5d49f498 1335 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1336
5d49f498 1337 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1338 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1339
5d49f498 1340 rc = iwl_grab_nic_access(priv);
b481de9c 1341 if (!rc) {
5d49f498 1342 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1343 APMG_CLK_VAL_BSM_CLK_RQT);
1344
1345 udelay(10);
1346
5d49f498 1347 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1348 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1349
5d49f498
AK		 1350 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1351 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1352 0xFFFFFFFF);
1353
1354 /* enable DMA */
5d49f498 1355 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1356 APMG_CLK_VAL_DMA_CLK_RQT |
1357 APMG_CLK_VAL_BSM_CLK_RQT);
1358 udelay(10);
1359
5d49f498 1360 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1361 APMG_PS_CTRL_VAL_RESET_REQ);
1362 udelay(5);
5d49f498 1363 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1364 APMG_PS_CTRL_VAL_RESET_REQ);
5d49f498 1365 iwl_release_nic_access(priv);
b481de9c
ZY		 1366 }
1367
1368 /* Clear the 'host command active' bit... */
1369 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1370
1371 wake_up_interruptible(&priv->wait_command_queue);
1372 spin_unlock_irqrestore(&priv->lock, flags);
1373
1374 return rc;
1375}
1376
1377/**
bb8c093b 1378 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1379 * return index delta into power gain settings table
1380*/
bb8c093b 1381static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1382{
1383 return (new_reading - old_reading) * (-11) / 100;
1384}
1385
1386/**
bb8c093b 1387 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1388 */
bb8c093b 1389static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1390{
3ac7f146 1391 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1392}
1393
4a8a4322 1394int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1395{
5d49f498 1396 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1397}
1398
1399/**
bb8c093b 1400 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1401 * get the current temperature by reading from NIC
1402*/
4a8a4322 1403static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 1404{
1405 int temperature;
1406
bb8c093b 1407 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1408
1409 /* driver's okay range is -260 to +25.
1410 * human readable okay range is 0 to +285 */
1411 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1412
1413 /* handle insane temp reading */
bb8c093b 1414 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1415 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1416
1417 /* if really really hot(?),
1418 * substitute the 3rd band/group's temp measured at factory */
1419 if (priv->last_temperature > 100)
f2c7e521 1420 temperature = priv->eeprom39.groups[2].temperature;
b481de9c
ZY		 1421 else /* else use most recent "sane" value from driver */
1422 temperature = priv->last_temperature;
1423 }
1424
1425 return temperature; /* raw, not "human readable" */
1426}
1427
1428/* Adjust Txpower only if temperature variance is greater than threshold.
1429 *
1430 * Both are lower than older versions' 9 degrees */
1431#define IWL_TEMPERATURE_LIMIT_TIMER 6
1432
1433/**
1434 * is_temp_calib_needed - determines if new calibration is needed
1435 *
1436 * records new temperature in tx_mgr->temperature.
1437 * replaces tx_mgr->last_temperature *only* if calib needed
1438 * (assumes caller will actually do the calibration!). */
4a8a4322 1439static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1440{
1441 int temp_diff;
1442
bb8c093b 1443 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1444 temp_diff = priv->temperature - priv->last_temperature;
1445
1446 /* get absolute value */
1447 if (temp_diff < 0) {
1448 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1449 temp_diff = -temp_diff;
1450 } else if (temp_diff == 0)
1451 IWL_DEBUG_POWER("Same temp,\n");
1452 else
1453 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1454
1455 /* if we don't need calibration, *don't* update last_temperature */
1456 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1457 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1458 return 0;
1459 }
1460
1461 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1462
1463 /* assume that caller will actually do calib ...
1464 * update the "last temperature" value */
1465 priv->last_temperature = priv->temperature;
1466 return 1;
1467}
1468
1469#define IWL_MAX_GAIN_ENTRIES 78
1470#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1471#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1472
1473/* radio and DSP power table, each step is 1/2 dB.
1474 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1475static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1476 {
1477 {251, 127}, /* 2.4 GHz, highest power */
1478 {251, 127},
1479 {251, 127},
1480 {251, 127},
1481 {251, 125},
1482 {251, 110},
1483 {251, 105},
1484 {251, 98},
1485 {187, 125},
1486 {187, 115},
1487 {187, 108},
1488 {187, 99},
1489 {243, 119},
1490 {243, 111},
1491 {243, 105},
1492 {243, 97},
1493 {243, 92},
1494 {211, 106},
1495 {211, 100},
1496 {179, 120},
1497 {179, 113},
1498 {179, 107},
1499 {147, 125},
1500 {147, 119},
1501 {147, 112},
1502 {147, 106},
1503 {147, 101},
1504 {147, 97},
1505 {147, 91},
1506 {115, 107},
1507 {235, 121},
1508 {235, 115},
1509 {235, 109},
1510 {203, 127},
1511 {203, 121},
1512 {203, 115},
1513 {203, 108},
1514 {203, 102},
1515 {203, 96},
1516 {203, 92},
1517 {171, 110},
1518 {171, 104},
1519 {171, 98},
1520 {139, 116},
1521 {227, 125},
1522 {227, 119},
1523 {227, 113},
1524 {227, 107},
1525 {227, 101},
1526 {227, 96},
1527 {195, 113},
1528 {195, 106},
1529 {195, 102},
1530 {195, 95},
1531 {163, 113},
1532 {163, 106},
1533 {163, 102},
1534 {163, 95},
1535 {131, 113},
1536 {131, 106},
1537 {131, 102},
1538 {131, 95},
1539 {99, 113},
1540 {99, 106},
1541 {99, 102},
1542 {99, 95},
1543 {67, 113},
1544 {67, 106},
1545 {67, 102},
1546 {67, 95},
1547 {35, 113},
1548 {35, 106},
1549 {35, 102},
1550 {35, 95},
1551 {3, 113},
1552 {3, 106},
1553 {3, 102},
1554 {3, 95} }, /* 2.4 GHz, lowest power */
1555 {
1556 {251, 127}, /* 5.x GHz, highest power */
1557 {251, 120},
1558 {251, 114},
1559 {219, 119},
1560 {219, 101},
1561 {187, 113},
1562 {187, 102},
1563 {155, 114},
1564 {155, 103},
1565 {123, 117},
1566 {123, 107},
1567 {123, 99},
1568 {123, 92},
1569 {91, 108},
1570 {59, 125},
1571 {59, 118},
1572 {59, 109},
1573 {59, 102},
1574 {59, 96},
1575 {59, 90},
1576 {27, 104},
1577 {27, 98},
1578 {27, 92},
1579 {115, 118},
1580 {115, 111},
1581 {115, 104},
1582 {83, 126},
1583 {83, 121},
1584 {83, 113},
1585 {83, 105},
1586 {83, 99},
1587 {51, 118},
1588 {51, 111},
1589 {51, 104},
1590 {51, 98},
1591 {19, 116},
1592 {19, 109},
1593 {19, 102},
1594 {19, 98},
1595 {19, 93},
1596 {171, 113},
1597 {171, 107},
1598 {171, 99},
1599 {139, 120},
1600 {139, 113},
1601 {139, 107},
1602 {139, 99},
1603 {107, 120},
1604 {107, 113},
1605 {107, 107},
1606 {107, 99},
1607 {75, 120},
1608 {75, 113},
1609 {75, 107},
1610 {75, 99},
1611 {43, 120},
1612 {43, 113},
1613 {43, 107},
1614 {43, 99},
1615 {11, 120},
1616 {11, 113},
1617 {11, 107},
1618 {11, 99},
1619 {131, 107},
1620 {131, 99},
1621 {99, 120},
1622 {99, 113},
1623 {99, 107},
1624 {99, 99},
1625 {67, 120},
1626 {67, 113},
1627 {67, 107},
1628 {67, 99},
1629 {35, 120},
1630 {35, 113},
1631 {35, 107},
1632 {35, 99},
1633 {3, 120} } /* 5.x GHz, lowest power */
1634};
1635
bb8c093b 1636static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1637{
1638 if (index < 0)
1639 return 0;
1640 if (index >= IWL_MAX_GAIN_ENTRIES)
1641 return IWL_MAX_GAIN_ENTRIES - 1;
1642 return (u8) index;
1643}
1644
1645/* Kick off thermal recalibration check every 60 seconds */
1646#define REG_RECALIB_PERIOD (60)
1647
1648/**
bb8c093b 1649 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1650 *
1651 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1652 * or 6 Mbit (OFDM) rates.
1653 */
4a8a4322 1654static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1655 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1656 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1657 int band_index)
1658{
bb8c093b 1659 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1660 s8 power;
1661 u8 power_index;
1662
1663 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1664
1665 /* use this channel group's 6Mbit clipping/saturation pwr,
1666 * but cap at regulatory scan power restriction (set during init
1667 * based on eeprom channel data) for this channel. */
14577f23 1668 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1669
1670 /* further limit to user's max power preference.
1671 * FIXME: Other spectrum management power limitations do not
1672 * seem to apply?? */
1673 power = min(power, priv->user_txpower_limit);
1674 scan_power_info->requested_power = power;
1675
1676 /* find difference between new scan *power* and current "normal"
1677 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1678 * current "normal" temperature-compensated Tx power *index* for
1679 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1680 * *index*. */
1681 power_index = ch_info->power_info[rate_index].power_table_index
1682 - (power - ch_info->power_info
14577f23 1683 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1684
1685 /* store reference index that we use when adjusting *all* scan
1686 * powers. So we can accommodate user (all channel) or spectrum
1687 * management (single channel) power changes "between" temperature
1688 * feedback compensation procedures.
1689 * don't force fit this reference index into gain table; it may be a
1690 * negative number. This will help avoid errors when we're at
1691 * the lower bounds (highest gains, for warmest temperatures)
1692 * of the table. */
1693
1694 /* don't exceed table bounds for "real" setting */
bb8c093b 1695 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1696
1697 scan_power_info->power_table_index = power_index;
1698 scan_power_info->tpc.tx_gain =
1699 power_gain_table[band_index][power_index].tx_gain;
1700 scan_power_info->tpc.dsp_atten =
1701 power_gain_table[band_index][power_index].dsp_atten;
1702}
1703
1704/**
bb8c093b 1705 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1706 *
1707 * Configures power settings for all rates for the current channel,
1708 * using values from channel info struct, and send to NIC
1709 */
4a8a4322 1710int iwl3945_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 1711{
14577f23 1712 int rate_idx, i;
d20b3c65 1713 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1714 struct iwl3945_txpowertable_cmd txpower = {
f2c7e521 1715 .channel = priv->active39_rxon.channel,
b481de9c
ZY		 1716 };
1717
8318d78a 1718 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1719 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1720 priv->band,
f2c7e521 1721 le16_to_cpu(priv->active39_rxon.channel));
b481de9c 1722 if (!ch_info) {
15b1687c
WT		 1723 IWL_ERR(priv,
1724 "Failed to get channel info for channel %d [%d]\n",
1725 le16_to_cpu(priv->active39_rxon.channel), priv->band);
b481de9c
ZY		 1726 return -EINVAL;
1727 }
1728
1729 if (!is_channel_valid(ch_info)) {
1730 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1731 "non-Tx channel.\n");
1732 return 0;
1733 }
1734
1735 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1736 /* Fill OFDM rate */
1737 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1738 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1739
1740 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1741 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1742
1743 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1744 le16_to_cpu(txpower.channel),
1745 txpower.band,
14577f23
MA		 1746 txpower.power[i].tpc.tx_gain,
1747 txpower.power[i].tpc.dsp_atten,
1748 txpower.power[i].rate);
1749 }
1750 /* Fill CCK rates */
1751 for (rate_idx = IWL_FIRST_CCK_RATE;
1752 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1753 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1754 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1755
1756 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1757 le16_to_cpu(txpower.channel),
1758 txpower.band,
1759 txpower.power[i].tpc.tx_gain,
1760 txpower.power[i].tpc.dsp_atten,
1761 txpower.power[i].rate);
b481de9c
ZY		 1762 }
1763
bb8c093b
CH		 1764 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1765 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1766
1767}
1768
1769/**
bb8c093b 1770 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1771 * @ch_info: Channel to update. Uses power_info.requested_power.
1772 *
1773 * Replace requested_power and base_power_index ch_info fields for
1774 * one channel.
1775 *
1776 * Called if user or spectrum management changes power preferences.
1777 * Takes into account h/w and modulation limitations (clip power).
1778 *
1779 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1780 *
1781 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1782 * properly fill out the scan powers, and actual h/w gain settings,
1783 * and send changes to NIC
1784 */
4a8a4322 1785static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1786 struct iwl_channel_info *ch_info)
b481de9c 1787{
bb8c093b 1788 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1789 int power_changed = 0;
1790 int i;
1791 const s8 *clip_pwrs;
1792 int power;
1793
1794 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1795 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1796
1797 /* Get this channel's rate-to-current-power settings table */
1798 power_info = ch_info->power_info;
1799
1800 /* update OFDM Txpower settings */
14577f23 1801 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1802 i++, ++power_info) {
1803 int delta_idx;
1804
1805 /* limit new power to be no more than h/w capability */
1806 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1807 if (power == power_info->requested_power)
1808 continue;
1809
1810 /* find difference between old and new requested powers,
1811 * update base (non-temp-compensated) power index */
1812 delta_idx = (power - power_info->requested_power) * 2;
1813 power_info->base_power_index -= delta_idx;
1814
1815 /* save new requested power value */
1816 power_info->requested_power = power;
1817
1818 power_changed = 1;
1819 }
1820
1821 /* update CCK Txpower settings, based on OFDM 12M setting ...
1822 * ... all CCK power settings for a given channel are the *same*. */
1823 if (power_changed) {
1824 power =
14577f23 1825 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1826 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1827
bb8c093b 1828 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1829 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1830 power_info->requested_power = power;
1831 power_info->base_power_index =
14577f23 1832 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1833 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1834 ++power_info;
1835 }
1836 }
1837
1838 return 0;
1839}
1840
1841/**
bb8c093b 1842 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1843 *
1844 * NOTE: Returned power limit may be less (but not more) than requested,
1845 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1846 * (no consideration for h/w clipping limitations).
1847 */
d20b3c65 1848static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1849{
1850 s8 max_power;
1851
1852#if 0
1853 /* if we're using TGd limits, use lower of TGd or EEPROM */
1854 if (ch_info->tgd_data.max_power != 0)
1855 max_power = min(ch_info->tgd_data.max_power,
1856 ch_info->eeprom.max_power_avg);
1857
1858 /* else just use EEPROM limits */
1859 else
1860#endif
1861 max_power = ch_info->eeprom.max_power_avg;
1862
1863 return min(max_power, ch_info->max_power_avg);
1864}
1865
1866/**
bb8c093b 1867 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1868 *
1869 * Compensate txpower settings of *all* channels for temperature.
1870 * This only accounts for the difference between current temperature
1871 * and the factory calibration temperatures, and bases the new settings
1872 * on the channel's base_power_index.
1873 *
1874 * If RxOn is "associated", this sends the new Txpower to NIC!
1875 */
4a8a4322 1876static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1877{
d20b3c65 1878 struct iwl_channel_info *ch_info = NULL;
b481de9c
ZY		 1879 int delta_index;
1880 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1881 u8 a_band;
1882 u8 rate_index;
1883 u8 scan_tbl_index;
1884 u8 i;
1885 int ref_temp;
1886 int temperature = priv->temperature;
1887
1888 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1889 for (i = 0; i < priv->channel_count; i++) {
1890 ch_info = &priv->channel_info[i];
1891 a_band = is_channel_a_band(ch_info);
1892
1893 /* Get this chnlgrp's factory calibration temperature */
f2c7e521 1894 ref_temp = (s16)priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 1895 temperature;
1896
a96a27f9 1897 /* get power index adjustment based on current and factory
b481de9c 1898 * temps */
bb8c093b 1899 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1900 ref_temp);
1901
1902 /* set tx power value for all rates, OFDM and CCK */
1903 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1904 rate_index++) {
1905 int power_idx =
1906 ch_info->power_info[rate_index].base_power_index;
1907
1908 /* temperature compensate */
1909 power_idx += delta_index;
1910
1911 /* stay within table range */
bb8c093b 1912 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1913 ch_info->power_info[rate_index].
1914 power_table_index = (u8) power_idx;
1915 ch_info->power_info[rate_index].tpc =
1916 power_gain_table[a_band][power_idx];
1917 }
1918
1919 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1920 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1921
1922 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1923 for (scan_tbl_index = 0;
1924 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1925 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1926 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1927 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1928 actual_index, clip_pwrs,
1929 ch_info, a_band);
1930 }
1931 }
1932
1933 /* send Txpower command for current channel to ucode */
bb8c093b 1934 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1935}
1936
4a8a4322 1937int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1938{
d20b3c65 1939 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1940 s8 max_power;
1941 u8 a_band;
1942 u8 i;
1943
1944 if (priv->user_txpower_limit == power) {
1945 IWL_DEBUG_POWER("Requested Tx power same as current "
1946 "limit: %ddBm.\n", power);
1947 return 0;
1948 }
1949
1950 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1951 priv->user_txpower_limit = power;
1952
1953 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1954
1955 for (i = 0; i < priv->channel_count; i++) {
1956 ch_info = &priv->channel_info[i];
1957 a_band = is_channel_a_band(ch_info);
1958
1959 /* find minimum power of all user and regulatory constraints
1960 * (does not consider h/w clipping limitations) */
bb8c093b 1961 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1962 max_power = min(power, max_power);
1963 if (max_power != ch_info->curr_txpow) {
1964 ch_info->curr_txpow = max_power;
1965
1966 /* this considers the h/w clipping limitations */
bb8c093b 1967 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1968 }
1969 }
1970
1971 /* update txpower settings for all channels,
1972 * send to NIC if associated. */
1973 is_temp_calib_needed(priv);
bb8c093b 1974 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1975
1976 return 0;
1977}
1978
1979/* will add 3945 channel switch cmd handling later */
4a8a4322 1980int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1981{
1982 return 0;
1983}
1984
1985/**
1986 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1987 *
1988 * -- reset periodic timer
1989 * -- see if temp has changed enough to warrant re-calibration ... if so:
1990 * -- correct coeffs for temp (can reset temp timer)
1991 * -- save this temp as "last",
1992 * -- send new set of gain settings to NIC
1993 * NOTE: This should continue working, even when we're not associated,
1994 * so we can keep our internal table of scan powers current. */
4a8a4322 1995void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1996{
1997 /* This will kick in the "brute force"
bb8c093b 1998 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1999 if (!is_temp_calib_needed(priv))
2000 goto reschedule;
2001
2002 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2003 * This is based *only* on current temperature,
2004 * ignoring any previous power measurements */
bb8c093b 2005 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2006
2007 reschedule:
2008 queue_delayed_work(priv->workqueue,
2009 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2010}
2011
416e1438 2012static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2013{
4a8a4322 2014 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2015 thermal_periodic.work);
2016
2017 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2018 return;
2019
2020 mutex_lock(&priv->mutex);
2021 iwl3945_reg_txpower_periodic(priv);
2022 mutex_unlock(&priv->mutex);
2023}
2024
2025/**
bb8c093b 2026 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2027 * for the channel.
2028 *
2029 * This function is used when initializing channel-info structs.
2030 *
2031 * NOTE: These channel groups do *NOT* match the bands above!
2032 * These channel groups are based on factory-tested channels;
2033 * on A-band, EEPROM's "group frequency" entries represent the top
2034 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2035 */
4a8a4322 2036static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2037 const struct iwl_channel_info *ch_info)
b481de9c 2038{
f2c7e521 2039 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom39.groups[0];
b481de9c
ZY		 2040 u8 group;
2041 u16 group_index = 0; /* based on factory calib frequencies */
2042 u8 grp_channel;
2043
2044 /* Find the group index for the channel ... don't use index 1(?) */
2045 if (is_channel_a_band(ch_info)) {
2046 for (group = 1; group < 5; group++) {
2047 grp_channel = ch_grp[group].group_channel;
2048 if (ch_info->channel <= grp_channel) {
2049 group_index = group;
2050 break;
2051 }
2052 }
2053 /* group 4 has a few channels *above* its factory cal freq */
2054 if (group == 5)
2055 group_index = 4;
2056 } else
2057 group_index = 0; /* 2.4 GHz, group 0 */
2058
2059 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2060 group_index);
2061 return group_index;
2062}
2063
2064/**
bb8c093b 2065 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2066 *
2067 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2068 * into radio/DSP gain settings table for requested power.
2069 */
4a8a4322 2070static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2071 s8 requested_power,
2072 s32 setting_index, s32 *new_index)
2073{
bb8c093b 2074 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 2075 s32 index0, index1;
2076 s32 power = 2 * requested_power;
2077 s32 i;
bb8c093b 2078 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2079 s32 gains0, gains1;
2080 s32 res;
2081 s32 denominator;
2082
f2c7e521 2083 chnl_grp = &priv->eeprom39.groups[setting_index];
b481de9c
ZY		 2084 samples = chnl_grp->samples;
2085 for (i = 0; i < 5; i++) {
2086 if (power == samples[i].power) {
2087 *new_index = samples[i].gain_index;
2088 return 0;
2089 }
2090 }
2091
2092 if (power > samples[1].power) {
2093 index0 = 0;
2094 index1 = 1;
2095 } else if (power > samples[2].power) {
2096 index0 = 1;
2097 index1 = 2;
2098 } else if (power > samples[3].power) {
2099 index0 = 2;
2100 index1 = 3;
2101 } else {
2102 index0 = 3;
2103 index1 = 4;
2104 }
2105
2106 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2107 if (denominator == 0)
2108 return -EINVAL;
2109 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2110 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2111 res = gains0 + (gains1 - gains0) *
2112 ((s32) power - (s32) samples[index0].power) / denominator +
2113 (1 << 18);
2114 *new_index = res >> 19;
2115 return 0;
2116}
2117
4a8a4322 2118static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2119{
2120 u32 i;
2121 s32 rate_index;
bb8c093b 2122 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2123
2124 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2125
2126 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2127 s8 *clip_pwrs; /* table of power levels for each rate */
2128 s8 satur_pwr; /* saturation power for each chnl group */
f2c7e521 2129 group = &priv->eeprom39.groups[i];
b481de9c
ZY		 2130
2131 /* sanity check on factory saturation power value */
2132 if (group->saturation_power < 40) {
39aadf8c 2133 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2134 "less than minimum expected 40\n",
2135 group->saturation_power);
2136 return;
2137 }
2138
2139 /*
2140 * Derive requested power levels for each rate, based on
2141 * hardware capabilities (saturation power for band).
2142 * Basic value is 3dB down from saturation, with further
2143 * power reductions for highest 3 data rates. These
2144 * backoffs provide headroom for high rate modulation
2145 * power peaks, without too much distortion (clipping).
2146 */
2147 /* we'll fill in this array with h/w max power levels */
f2c7e521 2148 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2149
2150 /* divide factory saturation power by 2 to find -3dB level */
2151 satur_pwr = (s8) (group->saturation_power >> 1);
2152
2153 /* fill in channel group's nominal powers for each rate */
2154 for (rate_index = 0;
2155 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2156 switch (rate_index) {
14577f23 2157 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2158 if (i == 0) /* B/G */
2159 *clip_pwrs = satur_pwr;
2160 else /* A */
2161 *clip_pwrs = satur_pwr - 5;
2162 break;
14577f23 2163 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2164 if (i == 0)
2165 *clip_pwrs = satur_pwr - 7;
2166 else
2167 *clip_pwrs = satur_pwr - 10;
2168 break;
14577f23 2169 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2170 if (i == 0)
2171 *clip_pwrs = satur_pwr - 9;
2172 else
2173 *clip_pwrs = satur_pwr - 12;
2174 break;
2175 default:
2176 *clip_pwrs = satur_pwr;
2177 break;
2178 }
2179 }
2180 }
2181}
2182
2183/**
2184 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2185 *
2186 * Second pass (during init) to set up priv->channel_info
2187 *
2188 * Set up Tx-power settings in our channel info database for each VALID
2189 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2190 * and current temperature.
2191 *
2192 * Since this is based on current temperature (at init time), these values may
2193 * not be valid for very long, but it gives us a starting/default point,
2194 * and allows us to active (i.e. using Tx) scan.
2195 *
2196 * This does *not* write values to NIC, just sets up our internal table.
2197 */
4a8a4322 2198int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2199{
d20b3c65 2200 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2201 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2202 int delta_index;
2203 u8 rate_index;
2204 u8 scan_tbl_index;
2205 const s8 *clip_pwrs; /* array of power levels for each rate */
2206 u8 gain, dsp_atten;
2207 s8 power;
2208 u8 pwr_index, base_pwr_index, a_band;
2209 u8 i;
2210 int temperature;
2211
2212 /* save temperature reference,
2213 * so we can determine next time to calibrate */
bb8c093b 2214 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2215 priv->last_temperature = temperature;
2216
bb8c093b 2217 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2218
2219 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2220 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2221 i++, ch_info++) {
2222 a_band = is_channel_a_band(ch_info);
2223 if (!is_channel_valid(ch_info))
2224 continue;
2225
2226 /* find this channel's channel group (*not* "band") index */
2227 ch_info->group_index =
bb8c093b 2228 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2229
2230 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2231 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2232
2233 /* calculate power index *adjustment* value according to
2234 * diff between current temperature and factory temperature */
bb8c093b 2235 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
f2c7e521 2236 priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 2237 temperature);
2238
2239 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2240 ch_info->channel, delta_index, temperature +
2241 IWL_TEMP_CONVERT);
2242
2243 /* set tx power value for all OFDM rates */
2244 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2245 rate_index++) {
25a4ccea 2246 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2247 int rc;
2248
2249 /* use channel group's clip-power table,
2250 * but don't exceed channel's max power */
2251 s8 pwr = min(ch_info->max_power_avg,
2252 clip_pwrs[rate_index]);
2253
2254 pwr_info = &ch_info->power_info[rate_index];
2255
2256 /* get base (i.e. at factory-measured temperature)
2257 * power table index for this rate's power */
bb8c093b 2258 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2259 ch_info->group_index,
2260 &power_idx);
2261 if (rc) {
15b1687c 2262 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2263 return rc;
2264 }
2265 pwr_info->base_power_index = (u8) power_idx;
2266
2267 /* temperature compensate */
2268 power_idx += delta_index;
2269
2270 /* stay within range of gain table */
bb8c093b 2271 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2272
bb8c093b 2273 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2274 pwr_info->requested_power = pwr;
2275 pwr_info->power_table_index = (u8) power_idx;
2276 pwr_info->tpc.tx_gain =
2277 power_gain_table[a_band][power_idx].tx_gain;
2278 pwr_info->tpc.dsp_atten =
2279 power_gain_table[a_band][power_idx].dsp_atten;
2280 }
2281
2282 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2283 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2284 power = pwr_info->requested_power +
2285 IWL_CCK_FROM_OFDM_POWER_DIFF;
2286 pwr_index = pwr_info->power_table_index +
2287 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2288 base_pwr_index = pwr_info->base_power_index +
2289 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2290
2291 /* stay within table range */
bb8c093b 2292 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2293 gain = power_gain_table[a_band][pwr_index].tx_gain;
2294 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2295
bb8c093b 2296 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2297 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2298 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2299 for (rate_index = 0;
2300 rate_index < IWL_CCK_RATES; rate_index++) {
2301 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2302 pwr_info->requested_power = power;
2303 pwr_info->power_table_index = pwr_index;
2304 pwr_info->base_power_index = base_pwr_index;
2305 pwr_info->tpc.tx_gain = gain;
2306 pwr_info->tpc.dsp_atten = dsp_atten;
2307 }
2308
2309 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2310 for (scan_tbl_index = 0;
2311 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2312 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2313 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2314 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2315 actual_index, clip_pwrs, ch_info, a_band);
2316 }
2317 }
2318
2319 return 0;
2320}
2321
4a8a4322 2322int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2323{
2324 int rc;
2325 unsigned long flags;
2326
2327 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2328 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2329 if (rc) {
2330 spin_unlock_irqrestore(&priv->lock, flags);
2331 return rc;
2332 }
2333
5d49f498
AK		 2334 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2335 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2336 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2337 if (rc < 0)
15b1687c 2338 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2339
5d49f498 2340 iwl_release_nic_access(priv);
b481de9c
ZY		 2341 spin_unlock_irqrestore(&priv->lock, flags);
2342
2343 return 0;
2344}
2345
4a8a4322 2346int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2347{
2348 int rc;
2349 unsigned long flags;
2350 int txq_id = txq->q.id;
2351
3832ec9d 2352 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2353
2354 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2355
2356 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2357 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2358 if (rc) {
2359 spin_unlock_irqrestore(&priv->lock, flags);
2360 return rc;
2361 }
5d49f498
AK		 2362 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2363 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2364
5d49f498 2365 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2366 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2367 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2368 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2369 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2370 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
5d49f498 2371 iwl_release_nic_access(priv);
b481de9c
ZY		 2372
2373 /* fake read to flush all prev. writes */
5d49f498 2374 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2375 spin_unlock_irqrestore(&priv->lock, flags);
2376
2377 return 0;
2378}
2379
4a8a4322 2380int iwl3945_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2381{
3832ec9d 2382 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2383
2384 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2385}
2386
2387/**
2388 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2389 */
4a8a4322 2390int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2391{
14577f23 2392 int rc, i, index, prev_index;
bb8c093b 2393 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2394 .reserved = {0, 0, 0},
2395 };
bb8c093b 2396 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2397
bb8c093b
CH		 2398 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2399 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2400
2401 table[index].rate_n_flags =
bb8c093b 2402 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2403 table[index].try_cnt = priv->retry_rate;
bb8c093b 2404 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2405 table[index].next_rate_index =
2406 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2407 }
2408
8318d78a
JB		 2409 switch (priv->band) {
2410 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2411 IWL_DEBUG_RATE("Select A mode rate scale\n");
2412 /* If one of the following CCK rates is used,
2413 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2414 for (i = IWL_RATE_1M_INDEX_TABLE;
2415 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2416 table[i].next_rate_index =
2417 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2418
2419 /* Don't fall back to CCK rates */
7262796a
AM		 2420 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2421 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2422
2423 /* Don't drop out of OFDM rates */
14577f23 2424 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2425 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2426 break;
2427
8318d78a
JB		 2428 case IEEE80211_BAND_2GHZ:
2429 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2430 /* If an OFDM rate is used, have it fall back to the
2431 * 1M CCK rates */
b481de9c 2432
7262796a
AM		 2433 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2434 iwl3945_is_associated(priv)) {
2435
2436 index = IWL_FIRST_CCK_RATE;
2437 for (i = IWL_RATE_6M_INDEX_TABLE;
2438 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2439 table[i].next_rate_index =
2440 iwl3945_rates[index].table_rs_index;
2441
2442 index = IWL_RATE_11M_INDEX_TABLE;
2443 /* CCK shouldn't fall back to OFDM... */
2444 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2445 }
b481de9c
ZY		 2446 break;
2447
2448 default:
8318d78a 2449 WARN_ON(1);
b481de9c
ZY		 2450 break;
2451 }
2452
2453 /* Update the rate scaling for control frame Tx */
2454 rate_cmd.table_id = 0;
bb8c093b 2455 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2456 &rate_cmd);
2457 if (rc)
2458 return rc;
2459
2460 /* Update the rate scaling for data frame Tx */
2461 rate_cmd.table_id = 1;
bb8c093b 2462 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2463 &rate_cmd);
2464}
2465
796083cb 2466/* Called when initializing driver */
4a8a4322 2467int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2468{
3832ec9d
AK		 2469 memset((void *)&priv->hw_params, 0,
2470 sizeof(struct iwl_hw_params));
b481de9c 2471
3832ec9d 2472 priv->shared_virt =
b481de9c 2473 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2474 sizeof(struct iwl3945_shared),
3832ec9d 2475 &priv->shared_phys);
b481de9c 2476
3832ec9d 2477 if (!priv->shared_virt) {
15b1687c 2478 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2479 mutex_unlock(&priv->mutex);
2480 return -ENOMEM;
2481 }
2482
3832ec9d
AK		 2483 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE;
2484 priv->hw_params.max_pkt_size = 2342;
2485 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2486 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2487 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2488 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2489
3832ec9d 2490 priv->hw_params.tx_ant_num = 2;
b481de9c
ZY		 2491 return 0;
2492}
2493
4a8a4322 2494unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2495 struct iwl3945_frame *frame, u8 rate)
b481de9c 2496{
bb8c093b 2497 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2498 unsigned int frame_size;
2499
bb8c093b 2500 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2501 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2502
3832ec9d 2503 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2504 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2505
bb8c093b 2506 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2507 tx_beacon_cmd->frame,
b481de9c
ZY		 2508 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2509
2510 BUG_ON(frame_size > MAX_MPDU_SIZE);
2511 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2512
2513 tx_beacon_cmd->tx.rate = rate;
2514 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2515 TX_CMD_FLG_TSF_MSK);
2516
14577f23
MA		 2517 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2518 tx_beacon_cmd->tx.supp_rates[0] =
2519 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2520
b481de9c 2521 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2522 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2523
3ac7f146 2524 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2525}
2526
4a8a4322 2527void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2528{
91c066f2 2529 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2530 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2531}
2532
4a8a4322 2533void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2534{
2535 INIT_DELAYED_WORK(&priv->thermal_periodic,
2536 iwl3945_bg_reg_txpower_periodic);
2537}
2538
4a8a4322 2539void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2540{
2541 cancel_delayed_work(&priv->thermal_periodic);
2542}
2543
0164b9b4
KA		 2544/* check contents of special bootstrap uCode SRAM */
2545static int iwl3945_verify_bsm(struct iwl_priv *priv)
2546 {
2547 __le32 *image = priv->ucode_boot.v_addr;
2548 u32 len = priv->ucode_boot.len;
2549 u32 reg;
2550 u32 val;
2551
2552 IWL_DEBUG_INFO("Begin verify bsm\n");
2553
2554 /* verify BSM SRAM contents */
2555 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2556 for (reg = BSM_SRAM_LOWER_BOUND;
2557 reg < BSM_SRAM_LOWER_BOUND + len;
2558 reg += sizeof(u32), image++) {
2559 val = iwl_read_prph(priv, reg);
2560 if (val != le32_to_cpu(*image)) {
2561 IWL_ERR(priv, "BSM uCode verification failed at "
2562 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2563 BSM_SRAM_LOWER_BOUND,
2564 reg - BSM_SRAM_LOWER_BOUND, len,
2565 val, le32_to_cpu(*image));
2566 return -EIO;
2567 }
2568 }
2569
2570 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2571
2572 return 0;
2573}
2574
2575 /**
2576 * iwl3945_load_bsm - Load bootstrap instructions
2577 *
2578 * BSM operation:
2579 *
2580 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2581 * in special SRAM that does not power down during RFKILL. When powering back
2582 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2583 * the bootstrap program into the on-board processor, and starts it.
2584 *
2585 * The bootstrap program loads (via DMA) instructions and data for a new
2586 * program from host DRAM locations indicated by the host driver in the
2587 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2588 * automatically.
2589 *
2590 * When initializing the NIC, the host driver points the BSM to the
2591 * "initialize" uCode image. This uCode sets up some internal data, then
2592 * notifies host via "initialize alive" that it is complete.
2593 *
2594 * The host then replaces the BSM_DRAM_* pointer values to point to the
2595 * normal runtime uCode instructions and a backup uCode data cache buffer
2596 * (filled initially with starting data values for the on-board processor),
2597 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2598 * which begins normal operation.
2599 *
2600 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2601 * the backup data cache in DRAM before SRAM is powered down.
2602 *
2603 * When powering back up, the BSM loads the bootstrap program. This reloads
2604 * the runtime uCode instructions and the backup data cache into SRAM,
2605 * and re-launches the runtime uCode from where it left off.
2606 */
2607static int iwl3945_load_bsm(struct iwl_priv *priv)
2608{
2609 __le32 *image = priv->ucode_boot.v_addr;
2610 u32 len = priv->ucode_boot.len;
2611 dma_addr_t pinst;
2612 dma_addr_t pdata;
2613 u32 inst_len;
2614 u32 data_len;
2615 int rc;
2616 int i;
2617 u32 done;
2618 u32 reg_offset;
2619
2620 IWL_DEBUG_INFO("Begin load bsm\n");
2621
2622 /* make sure bootstrap program is no larger than BSM's SRAM size */
2623 if (len > IWL39_MAX_BSM_SIZE)
2624 return -EINVAL;
2625
2626 /* Tell bootstrap uCode where to find the "Initialize" uCode
2627 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2628 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2629 * after the "initialize" uCode has run, to point to
2630 * runtime/protocol instructions and backup data cache. */
2631 pinst = priv->ucode_init.p_addr;
2632 pdata = priv->ucode_init_data.p_addr;
2633 inst_len = priv->ucode_init.len;
2634 data_len = priv->ucode_init_data.len;
2635
2636 rc = iwl_grab_nic_access(priv);
2637 if (rc)
2638 return rc;
2639
2640 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2641 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2642 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2643 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2644
2645 /* Fill BSM memory with bootstrap instructions */
2646 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2647 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2648 reg_offset += sizeof(u32), image++)
2649 _iwl_write_prph(priv, reg_offset,
2650 le32_to_cpu(*image));
2651
2652 rc = iwl3945_verify_bsm(priv);
2653 if (rc) {
2654 iwl_release_nic_access(priv);
2655 return rc;
2656 }
2657
2658 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2659 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2660 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2661 IWL39_RTC_INST_LOWER_BOUND);
2662 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2663
2664 /* Load bootstrap code into instruction SRAM now,
2665 * to prepare to load "initialize" uCode */
2666 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2667 BSM_WR_CTRL_REG_BIT_START);
2668
2669 /* Wait for load of bootstrap uCode to finish */
2670 for (i = 0; i < 100; i++) {
2671 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2672 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2673 break;
2674 udelay(10);
2675 }
2676 if (i < 100)
2677 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2678 else {
2679 IWL_ERR(priv, "BSM write did not complete!\n");
2680 return -EIO;
2681 }
2682
2683 /* Enable future boot loads whenever power management unit triggers it
2684 * (e.g. when powering back up after power-save shutdown) */
2685 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2686 BSM_WR_CTRL_REG_BIT_START_EN);
2687
2688 iwl_release_nic_access(priv);
2689
2690 return 0;
2691}
2692
2693static struct iwl_lib_ops iwl3945_lib = {
2694 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2695 .apm_ops = {
2696 .init = iwl3945_apm_init,
2697 .reset = iwl3945_apm_reset,
2698 .stop = iwl3945_apm_stop,
2699 .config = iwl3945_nic_config,
854682ed 2700 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2701 },
0164b9b4
KA		 2702};
2703
2704static struct iwl_ops iwl3945_ops = {
2705 .lib = &iwl3945_lib,
2706};
2707
c0f20d91 2708static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2709 .name = "3945BG",
a0987a8d
RC		 2710 .fw_name_pre = IWL3945_FW_PRE,
2711 .ucode_api_max = IWL3945_UCODE_API_MAX,
2712 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2713 .sku = IWL_SKU_G,
0164b9b4 2714 .ops = &iwl3945_ops,
df878d8f 2715 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2716};
2717
c0f20d91 2718static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2719 .name = "3945ABG",
a0987a8d
RC		 2720 .fw_name_pre = IWL3945_FW_PRE,
2721 .ucode_api_max = IWL3945_UCODE_API_MAX,
2722 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2723 .sku = IWL_SKU_A|IWL_SKU_G,
0164b9b4 2724 .ops = &iwl3945_ops,
df878d8f 2725 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2726};
2727
bb8c093b 2728struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2729 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2730 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2731 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2732 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2733 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2734 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2735 {0}
2736};
2737
bb8c093b 2738MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux kernel - Deliverables
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