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iwlwifi: define structures and functions externally for customization
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47 38#include <asm/unaligned.h>
b481de9c 39
6bc913bd 40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
fee1247a 42#include "iwl-core.h"
3395f6e9 43#include "iwl-io.h"
b481de9c 44#include "iwl-helpers.h"
f0832f13 45#include "iwl-calib.h"
5083e563 46#include "iwl-sta.h"
b481de9c 47
630fe9b6 48static int iwl4965_send_tx_power(struct iwl_priv *priv);
91dbc5bd 49static int iwl4965_hw_get_temperature(const struct iwl_priv *priv);
630fe9b6 50
a0987a8d
RC		 51/* Highest firmware API version supported */
52#define IWL4965_UCODE_API_MAX 2
53
54/* Lowest firmware API version supported */
55#define IWL4965_UCODE_API_MIN 2
56
57#define IWL4965_FW_PRE "iwlwifi-4965-"
58#define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
59#define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
d16dc48a
TW		 60
61
1ea87396
AK		 62/* module parameters */
63static struct iwl_mod_params iwl4965_mod_params = {
038669e4 64 .num_of_queues = IWL49_NUM_QUEUES,
9f17b318 65 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
1ea87396 66 .amsdu_size_8K = 1,
3a1081e8 67 .restart_fw = 1,
1ea87396
AK		 68 /* the rest are 0 by default */
69};
70
57aab75a
TW		 71/* check contents of special bootstrap uCode SRAM */
72static int iwl4965_verify_bsm(struct iwl_priv *priv)
73{
74 __le32 *image = priv->ucode_boot.v_addr;
75 u32 len = priv->ucode_boot.len;
76 u32 reg;
77 u32 val;
78
e1623446 79 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
57aab75a
TW		 80
81 /* verify BSM SRAM contents */
82 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
83 for (reg = BSM_SRAM_LOWER_BOUND;
84 reg < BSM_SRAM_LOWER_BOUND + len;
85 reg += sizeof(u32), image++) {
86 val = iwl_read_prph(priv, reg);
87 if (val != le32_to_cpu(*image)) {
15b1687c 88 IWL_ERR(priv, "BSM uCode verification failed at "
57aab75a
TW		 89 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
90 BSM_SRAM_LOWER_BOUND,
91 reg - BSM_SRAM_LOWER_BOUND, len,
92 val, le32_to_cpu(*image));
93 return -EIO;
94 }
95 }
96
e1623446 97 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
57aab75a
TW		 98
99 return 0;
100}
101
102/**
103 * iwl4965_load_bsm - Load bootstrap instructions
104 *
105 * BSM operation:
106 *
107 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
108 * in special SRAM that does not power down during RFKILL. When powering back
109 * up after power-saving sleeps (or during initial uCode load), the BSM loads
110 * the bootstrap program into the on-board processor, and starts it.
111 *
112 * The bootstrap program loads (via DMA) instructions and data for a new
113 * program from host DRAM locations indicated by the host driver in the
114 * BSM_DRAM_* registers. Once the new program is loaded, it starts
115 * automatically.
116 *
117 * When initializing the NIC, the host driver points the BSM to the
118 * "initialize" uCode image. This uCode sets up some internal data, then
119 * notifies host via "initialize alive" that it is complete.
120 *
121 * The host then replaces the BSM_DRAM_* pointer values to point to the
122 * normal runtime uCode instructions and a backup uCode data cache buffer
123 * (filled initially with starting data values for the on-board processor),
124 * then triggers the "initialize" uCode to load and launch the runtime uCode,
125 * which begins normal operation.
126 *
127 * When doing a power-save shutdown, runtime uCode saves data SRAM into
128 * the backup data cache in DRAM before SRAM is powered down.
129 *
130 * When powering back up, the BSM loads the bootstrap program. This reloads
131 * the runtime uCode instructions and the backup data cache into SRAM,
132 * and re-launches the runtime uCode from where it left off.
133 */
134static int iwl4965_load_bsm(struct iwl_priv *priv)
135{
136 __le32 *image = priv->ucode_boot.v_addr;
137 u32 len = priv->ucode_boot.len;
138 dma_addr_t pinst;
139 dma_addr_t pdata;
140 u32 inst_len;
141 u32 data_len;
142 int i;
143 u32 done;
144 u32 reg_offset;
145 int ret;
146
e1623446 147 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
57aab75a 148
fe9b6b72
RR		 149 priv->ucode_type = UCODE_RT;
150
57aab75a 151 /* make sure bootstrap program is no larger than BSM's SRAM size */
250bdd21 152 if (len > IWL49_MAX_BSM_SIZE)
57aab75a
TW		 153 return -EINVAL;
154
155 /* Tell bootstrap uCode where to find the "Initialize" uCode
156 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
2d87889f 157 * NOTE: iwl_init_alive_start() will replace these values,
57aab75a 158 * after the "initialize" uCode has run, to point to
2d87889f
TW		 159 * runtime/protocol instructions and backup data cache.
160 */
57aab75a
TW		 161 pinst = priv->ucode_init.p_addr >> 4;
162 pdata = priv->ucode_init_data.p_addr >> 4;
163 inst_len = priv->ucode_init.len;
164 data_len = priv->ucode_init_data.len;
165
166 ret = iwl_grab_nic_access(priv);
167 if (ret)
168 return ret;
169
170 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
171 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
172 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
173 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
174
175 /* Fill BSM memory with bootstrap instructions */
176 for (reg_offset = BSM_SRAM_LOWER_BOUND;
177 reg_offset < BSM_SRAM_LOWER_BOUND + len;
178 reg_offset += sizeof(u32), image++)
179 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
180
181 ret = iwl4965_verify_bsm(priv);
182 if (ret) {
183 iwl_release_nic_access(priv);
184 return ret;
185 }
186
187 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
188 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
250bdd21 189 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
57aab75a
TW		 190 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
191
192 /* Load bootstrap code into instruction SRAM now,
193 * to prepare to load "initialize" uCode */
194 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
195
196 /* Wait for load of bootstrap uCode to finish */
197 for (i = 0; i < 100; i++) {
198 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
199 if (!(done & BSM_WR_CTRL_REG_BIT_START))
200 break;
201 udelay(10);
202 }
203 if (i < 100)
e1623446 204 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
57aab75a 205 else {
15b1687c 206 IWL_ERR(priv, "BSM write did not complete!\n");
57aab75a
TW		 207 return -EIO;
208 }
209
210 /* Enable future boot loads whenever power management unit triggers it
211 * (e.g. when powering back up after power-save shutdown) */
212 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
213
214 iwl_release_nic_access(priv);
215
216 return 0;
217}
218
f3ccc08c
EG		 219/**
220 * iwl4965_set_ucode_ptrs - Set uCode address location
221 *
222 * Tell initialization uCode where to find runtime uCode.
223 *
224 * BSM registers initially contain pointers to initialization uCode.
225 * We need to replace them to load runtime uCode inst and data,
226 * and to save runtime data when powering down.
227 */
228static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
229{
230 dma_addr_t pinst;
231 dma_addr_t pdata;
232 unsigned long flags;
233 int ret = 0;
234
235 /* bits 35:4 for 4965 */
236 pinst = priv->ucode_code.p_addr >> 4;
237 pdata = priv->ucode_data_backup.p_addr >> 4;
238
239 spin_lock_irqsave(&priv->lock, flags);
240 ret = iwl_grab_nic_access(priv);
241 if (ret) {
242 spin_unlock_irqrestore(&priv->lock, flags);
243 return ret;
244 }
245
246 /* Tell bootstrap uCode where to find image to load */
247 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
248 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
249 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
250 priv->ucode_data.len);
251
a96a27f9 252 /* Inst byte count must be last to set up, bit 31 signals uCode
f3ccc08c
EG		 253 * that all new ptr/size info is in place */
254 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
255 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
256 iwl_release_nic_access(priv);
257
258 spin_unlock_irqrestore(&priv->lock, flags);
259
e1623446 260 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
f3ccc08c
EG		 261
262 return ret;
263}
264
265/**
266 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
267 *
268 * Called after REPLY_ALIVE notification received from "initialize" uCode.
269 *
270 * The 4965 "initialize" ALIVE reply contains calibration data for:
271 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
272 * (3945 does not contain this data).
273 *
274 * Tell "initialize" uCode to go ahead and load the runtime uCode.
275*/
276static void iwl4965_init_alive_start(struct iwl_priv *priv)
277{
278 /* Check alive response for "valid" sign from uCode */
279 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
280 /* We had an error bringing up the hardware, so take it
281 * all the way back down so we can try again */
e1623446 282 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
f3ccc08c
EG		 283 goto restart;
284 }
285
286 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
287 * This is a paranoid check, because we would not have gotten the
288 * "initialize" alive if code weren't properly loaded. */
289 if (iwl_verify_ucode(priv)) {
290 /* Runtime instruction load was bad;
291 * take it all the way back down so we can try again */
e1623446 292 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
f3ccc08c
EG		 293 goto restart;
294 }
295
296 /* Calculate temperature */
91dbc5bd 297 priv->temperature = iwl4965_hw_get_temperature(priv);
f3ccc08c
EG		 298
299 /* Send pointers to protocol/runtime uCode image ... init code will
300 * load and launch runtime uCode, which will send us another "Alive"
301 * notification. */
e1623446 302 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
f3ccc08c
EG		 303 if (iwl4965_set_ucode_ptrs(priv)) {
304 /* Runtime instruction load won't happen;
305 * take it all the way back down so we can try again */
e1623446 306 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
f3ccc08c
EG		 307 goto restart;
308 }
309 return;
310
311restart:
312 queue_work(priv->workqueue, &priv->restart);
313}
314
b481de9c
ZY		 315static int is_fat_channel(__le32 rxon_flags)
316{
317 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
318 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
319}
320
8614f360
TW		 321/*
322 * EEPROM handlers
323 */
0ef2ca67 324static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
8614f360 325{
0ef2ca67 326 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
8614f360 327}
b481de9c 328
da1bc453 329/*
a96a27f9 330 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 331 * must be called under priv->lock and mac access
332 */
333static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
b481de9c 334{
da1bc453 335 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
b481de9c
ZY		 336}
337
91238714 338static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 339{
91238714 340 int ret = 0;
b481de9c 341
3395f6e9 342 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 343 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 344
8f061891
TW		 345 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
346 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
347 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
348
91238714
TW		 349 /* set "initialization complete" bit to move adapter
350 * D0U* --> D0A* state */
3395f6e9 351 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 352
91238714 353 /* wait for clock stabilization */
73d7b5ac
ZY		 354 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
355 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
91238714 356 if (ret < 0) {
e1623446 357 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
91238714 358 goto out;
b481de9c
ZY		 359 }
360
91238714
TW		 361 ret = iwl_grab_nic_access(priv);
362 if (ret)
363 goto out;
b481de9c 364
91238714 365 /* enable DMA */
8f061891
TW		 366 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
367 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 368
369 udelay(20);
370
8f061891 371 /* disable L1-Active */
3395f6e9 372 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 373 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 374
3395f6e9 375 iwl_release_nic_access(priv);
91238714 376out:
91238714
TW		 377 return ret;
378}
379
694cc56d
TW		 380
381static void iwl4965_nic_config(struct iwl_priv *priv)
91238714
TW		 382{
383 unsigned long flags;
91238714 384 u32 val;
694cc56d 385 u16 radio_cfg;
e7b63581 386 u16 link;
6f4083aa 387
b481de9c
ZY		 388 spin_lock_irqsave(&priv->lock, flags);
389
b661c819 390 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
b481de9c
ZY		 391 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
392 /* Enable No Snoop field */
393 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
394 val & ~(1 << 11));
395 }
396
e7b63581 397 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
b481de9c 398
8f061891 399 /* L1 is enabled by BIOS */
e7b63581 400 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
a96a27f9 401 /* disable L0S disabled L1A enabled */
8f061891
TW		 402 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
403 else
404 /* L0S enabled L1A disabled */
405 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
b481de9c 406
694cc56d 407 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
b481de9c 408
694cc56d
TW		 409 /* write radio config values to register */
410 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
411 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
412 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
413 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
414 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
b481de9c 415
694cc56d 416 /* set CSR_HW_CONFIG_REG for uCode use */
3395f6e9 417 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
a395b920
TW		 418 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
419 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 420
694cc56d
TW		 421 priv->calib_info = (struct iwl_eeprom_calib_info *)
422 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
423
424 spin_unlock_irqrestore(&priv->lock, flags);
425}
426
46315e01
TW		 427static int iwl4965_apm_stop_master(struct iwl_priv *priv)
428{
46315e01
TW		 429 unsigned long flags;
430
431 spin_lock_irqsave(&priv->lock, flags);
432
433 /* set stop master bit */
434 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
435
febf3370 436 iwl_poll_direct_bit(priv, CSR_RESET,
73d7b5ac 437 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
46315e01 438
46315e01 439 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 440 IWL_DEBUG_INFO(priv, "stop master\n");
46315e01 441
febf3370 442 return 0;
46315e01
TW		 443}
444
f118a91d
TW		 445static void iwl4965_apm_stop(struct iwl_priv *priv)
446{
447 unsigned long flags;
448
46315e01 449 iwl4965_apm_stop_master(priv);
f118a91d
TW		 450
451 spin_lock_irqsave(&priv->lock, flags);
452
453 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
454
455 udelay(10);
1d3e6c61
MA		 456 /* clear "init complete" move adapter D0A* --> D0U state */
457 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d
TW		 458 spin_unlock_irqrestore(&priv->lock, flags);
459}
460
7f066108 461static int iwl4965_apm_reset(struct iwl_priv *priv)
b481de9c 462{
7f066108 463 int ret = 0;
b481de9c
ZY		 464 unsigned long flags;
465
46315e01 466 iwl4965_apm_stop_master(priv);
b481de9c
ZY		 467
468 spin_lock_irqsave(&priv->lock, flags);
469
3395f6e9 470 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 471
472 udelay(10);
473
7f066108
TW		 474 /* FIXME: put here L1A -L0S w/a */
475
3395f6e9 476 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d 477
73d7b5ac
ZY		 478 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
479 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
42802d71 480 if (ret < 0)
7f066108
TW		 481 goto out;
482
b481de9c
ZY		 483 udelay(10);
484
7f066108
TW		 485 ret = iwl_grab_nic_access(priv);
486 if (ret)
487 goto out;
488 /* Enable DMA and BSM Clock */
489 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
490 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 491
7f066108 492 udelay(10);
b481de9c 493
7f066108
TW		 494 /* disable L1A */
495 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
496 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 497
7f066108 498 iwl_release_nic_access(priv);
b481de9c
ZY		 499
500 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
501 wake_up_interruptible(&priv->wait_command_queue);
502
7f066108 503out:
b481de9c
ZY		 504 spin_unlock_irqrestore(&priv->lock, flags);
505
7f066108 506 return ret;
b481de9c
ZY		 507}
508
b481de9c
ZY		 509/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
510 * Called after every association, but this runs only once!
511 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 512static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 513{
f0832f13 514 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 515
3109ece1 516 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 517 struct iwl_calib_diff_gain_cmd cmd;
b481de9c
ZY		 518
519 memset(&cmd, 0, sizeof(cmd));
0d950d84 520 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
b481de9c
ZY		 521 cmd.diff_gain_a = 0;
522 cmd.diff_gain_b = 0;
523 cmd.diff_gain_c = 0;
f0832f13
EG		 524 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
525 sizeof(cmd), &cmd))
15b1687c
WT		 526 IWL_ERR(priv,
527 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c 528 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
e1623446 529 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
b481de9c 530 }
b481de9c
ZY		 531}
532
f0832f13
EG		 533static void iwl4965_gain_computation(struct iwl_priv *priv,
534 u32 *average_noise,
535 u16 min_average_noise_antenna_i,
536 u32 min_average_noise)
b481de9c 537{
f0832f13
EG		 538 int i, ret;
539 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 540
f0832f13 541 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 542
f0832f13
EG		 543 for (i = 0; i < NUM_RX_CHAINS; i++) {
544 s32 delta_g = 0;
b481de9c 545
f0832f13
EG		 546 if (!(data->disconn_array[i]) &&
547 (data->delta_gain_code[i] ==
b481de9c 548 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 549 delta_g = average_noise[i] - min_average_noise;
550 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
551 data->delta_gain_code[i] =
552 min(data->delta_gain_code[i],
553 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
554
555 data->delta_gain_code[i] =
556 (data->delta_gain_code[i] | (1 << 2));
557 } else {
558 data->delta_gain_code[i] = 0;
b481de9c 559 }
b481de9c 560 }
e1623446 561 IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
f0832f13
EG		 562 data->delta_gain_code[0],
563 data->delta_gain_code[1],
564 data->delta_gain_code[2]);
b481de9c 565
f0832f13
EG		 566 /* Differential gain gets sent to uCode only once */
567 if (!data->radio_write) {
f69f42a6 568 struct iwl_calib_diff_gain_cmd cmd;
f0832f13 569 data->radio_write = 1;
b481de9c 570
f0832f13 571 memset(&cmd, 0, sizeof(cmd));
0d950d84 572 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
f0832f13
EG		 573 cmd.diff_gain_a = data->delta_gain_code[0];
574 cmd.diff_gain_b = data->delta_gain_code[1];
575 cmd.diff_gain_c = data->delta_gain_code[2];
576 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
577 sizeof(cmd), &cmd);
578 if (ret)
e1623446 579 IWL_DEBUG_CALIB(priv, "fail sending cmd "
f0832f13
EG		 580 "REPLY_PHY_CALIBRATION_CMD \n");
581
582 /* TODO we might want recalculate
583 * rx_chain in rxon cmd */
584
585 /* Mark so we run this algo only once! */
586 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 587 }
f0832f13
EG		 588 data->chain_noise_a = 0;
589 data->chain_noise_b = 0;
590 data->chain_noise_c = 0;
591 data->chain_signal_a = 0;
592 data->chain_signal_b = 0;
593 data->chain_signal_c = 0;
594 data->beacon_count = 0;
b481de9c
ZY		 595}
596
a326a5d0
EG		 597static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
598 __le32 *tx_flags)
599{
e6a9854b 600 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
a326a5d0
EG		 601 *tx_flags |= TX_CMD_FLG_RTS_MSK;
602 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 603 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
a326a5d0
EG		 604 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
605 *tx_flags |= TX_CMD_FLG_CTS_MSK;
606 }
607}
608
b481de9c
ZY		 609static void iwl4965_bg_txpower_work(struct work_struct *work)
610{
c79dd5b5 611 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 612 txpower_work);
613
614 /* If a scan happened to start before we got here
615 * then just return; the statistics notification will
616 * kick off another scheduled work to compensate for
617 * any temperature delta we missed here. */
618 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
619 test_bit(STATUS_SCANNING, &priv->status))
620 return;
621
622 mutex_lock(&priv->mutex);
623
a96a27f9 624 /* Regardless of if we are associated, we must reconfigure the
b481de9c
ZY		 625 * TX power since frames can be sent on non-radar channels while
626 * not associated */
630fe9b6 627 iwl4965_send_tx_power(priv);
b481de9c
ZY		 628
629 /* Update last_temperature to keep is_calib_needed from running
630 * when it isn't needed... */
631 priv->last_temperature = priv->temperature;
632
633 mutex_unlock(&priv->mutex);
634}
635
636/*
637 * Acquire priv->lock before calling this function !
638 */
c79dd5b5 639static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 640{
3395f6e9 641 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 642 (index & 0xff) | (txq_id << 8));
12a81f60 643 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 644}
645
8b6eaea8
CB		 646/**
647 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
648 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
649 * @scd_retry: (1) Indicates queue will be used in aggregation mode
650 *
651 * NOTE: Acquire priv->lock before calling this function !
b481de9c 652 */
c79dd5b5 653static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
16466903 654 struct iwl_tx_queue *txq,
b481de9c
ZY		 655 int tx_fifo_id, int scd_retry)
656{
657 int txq_id = txq->q.id;
8b6eaea8
CB		 658
659 /* Find out whether to activate Tx queue */
c3056065 660 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
b481de9c 661
8b6eaea8 662 /* Set up and activate */
12a81f60 663 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 664 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
665 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
666 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
667 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
668 IWL49_SCD_QUEUE_STTS_REG_MSK);
b481de9c
ZY		 669
670 txq->sched_retry = scd_retry;
671
e1623446 672 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
8b6eaea8 673 active ? "Activate" : "Deactivate",
b481de9c
ZY		 674 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
675}
676
677static const u16 default_queue_to_tx_fifo[] = {
678 IWL_TX_FIFO_AC3,
679 IWL_TX_FIFO_AC2,
680 IWL_TX_FIFO_AC1,
681 IWL_TX_FIFO_AC0,
038669e4 682 IWL49_CMD_FIFO_NUM,
b481de9c
ZY		 683 IWL_TX_FIFO_HCCA_1,
684 IWL_TX_FIFO_HCCA_2
685};
686
be1f3ab6 687static int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 688{
689 u32 a;
b481de9c 690 unsigned long flags;
857485c0 691 int ret;
31a73fe4 692 int i, chan;
40fc95d5 693 u32 reg_val;
b481de9c
ZY		 694
695 spin_lock_irqsave(&priv->lock, flags);
696
3395f6e9 697 ret = iwl_grab_nic_access(priv);
857485c0 698 if (ret) {
b481de9c 699 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 700 return ret;
b481de9c
ZY		 701 }
702
8b6eaea8 703 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 704 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
038669e4
EG		 705 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
706 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 707 iwl_write_targ_mem(priv, a, 0);
038669e4 708 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 709 iwl_write_targ_mem(priv, a, 0);
5425e490 710 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 711 iwl_write_targ_mem(priv, a, 0);
b481de9c 712
8b6eaea8 713 /* Tel 4965 where to find Tx byte count tables */
12a81f60 714 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
4ddbb7d0 715 priv->scd_bc_tbls.dma >> 10);
8b6eaea8 716
31a73fe4
WT		 717 /* Enable DMA channel */
718 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
719 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
720 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
721 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
722
40fc95d5
WT		 723 /* Update FH chicken bits */
724 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
725 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
726 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
727
8b6eaea8 728 /* Disable chain mode for all queues */
12a81f60 729 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 730
8b6eaea8 731 /* Initialize each Tx queue (including the command queue) */
5425e490 732 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 733
734 /* TFD circular buffer read/write indexes */
12a81f60 735 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 736 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 737
738 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 739 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 740 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
741 (SCD_WIN_SIZE <<
742 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
743 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 744
745 /* Frame limit */
3395f6e9 746 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 747 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
748 sizeof(u32),
749 (SCD_FRAME_LIMIT <<
750 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
751 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c
ZY		 752
753 }
12a81f60 754 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 755 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 756
8b6eaea8 757 /* Activate all Tx DMA/FIFO channels */
31a73fe4 758 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
b481de9c
ZY		 759
760 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 761
762 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 763 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
764 int ac = default_queue_to_tx_fifo[i];
36470749 765 iwl_txq_ctx_activate(priv, i);
b481de9c
ZY		 766 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
767 }
768
3395f6e9 769 iwl_release_nic_access(priv);
b481de9c
ZY		 770 spin_unlock_irqrestore(&priv->lock, flags);
771
857485c0 772 return ret;
b481de9c
ZY		 773}
774
f0832f13
EG		 775static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
776 .min_nrg_cck = 97,
777 .max_nrg_cck = 0,
778
779 .auto_corr_min_ofdm = 85,
780 .auto_corr_min_ofdm_mrc = 170,
781 .auto_corr_min_ofdm_x1 = 105,
782 .auto_corr_min_ofdm_mrc_x1 = 220,
783
784 .auto_corr_max_ofdm = 120,
785 .auto_corr_max_ofdm_mrc = 210,
786 .auto_corr_max_ofdm_x1 = 140,
787 .auto_corr_max_ofdm_mrc_x1 = 270,
788
789 .auto_corr_min_cck = 125,
790 .auto_corr_max_cck = 200,
791 .auto_corr_min_cck_mrc = 200,
792 .auto_corr_max_cck_mrc = 400,
793
794 .nrg_th_cck = 100,
795 .nrg_th_ofdm = 100,
796};
f0832f13 797
8b6eaea8 798/**
5425e490 799 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 800 *
801 * Called when initializing driver
802 */
be1f3ab6 803static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 804{
316c30d9 805
038669e4 806 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1ea87396 807 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
15b1687c
WT		 808 IWL_ERR(priv,
809 "invalid queues_num, should be between %d and %d\n",
810 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
059ff826 811 return -EINVAL;
316c30d9 812 }
b481de9c 813
5425e490 814 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
f3f911d1 815 priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
4ddbb7d0
TW		 816 priv->hw_params.scd_bc_tbls_size =
817 IWL49_NUM_QUEUES * sizeof(struct iwl4965_scd_bc_tbl);
a8e74e27 818 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
5425e490
TW		 819 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
820 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
099b40b7
RR		 821 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
822 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
823 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
824 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
825
141c43a3
WT		 826 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
827
ec35cf2a
TW		 828 priv->hw_params.tx_chains_num = 2;
829 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 830 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
831 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 832 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
833
f0832f13 834 priv->hw_params.sens = &iwl4965_sensitivity;
3e82a822 835
059ff826 836 return 0;
b481de9c
ZY		 837}
838
b481de9c
ZY		 839static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
840{
841 s32 sign = 1;
842
843 if (num < 0) {
844 sign = -sign;
845 num = -num;
846 }
847 if (denom < 0) {
848 sign = -sign;
849 denom = -denom;
850 }
851 *res = 1;
852 *res = ((num * 2 + denom) / (denom * 2)) * sign;
853
854 return 1;
855}
856
8b6eaea8
CB		 857/**
858 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
859 *
860 * Determines power supply voltage compensation for txpower calculations.
861 * Returns number of 1/2-dB steps to subtract from gain table index,
862 * to compensate for difference between power supply voltage during
863 * factory measurements, vs. current power supply voltage.
864 *
865 * Voltage indication is higher for lower voltage.
866 * Lower voltage requires more gain (lower gain table index).
867 */
b481de9c
ZY		 868static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
869 s32 current_voltage)
870{
871 s32 comp = 0;
872
873 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
874 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
875 return 0;
876
877 iwl4965_math_div_round(current_voltage - eeprom_voltage,
878 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
879
880 if (current_voltage > eeprom_voltage)
881 comp *= 2;
882 if ((comp < -2) || (comp > 2))
883 comp = 0;
884
885 return comp;
886}
887
b481de9c
ZY		 888static s32 iwl4965_get_tx_atten_grp(u16 channel)
889{
890 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
891 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
892 return CALIB_CH_GROUP_5;
893
894 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
895 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
896 return CALIB_CH_GROUP_1;
897
898 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
899 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
900 return CALIB_CH_GROUP_2;
901
902 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
903 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
904 return CALIB_CH_GROUP_3;
905
906 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
907 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
908 return CALIB_CH_GROUP_4;
909
b481de9c
ZY		 910 return -1;
911}
912
c79dd5b5 913static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 914{
915 s32 b = -1;
916
917 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 918 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 919 continue;
920
073d3f5f
TW		 921 if ((channel >= priv->calib_info->band_info[b].ch_from)
922 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 923 break;
924 }
925
926 return b;
927}
928
929static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
930{
931 s32 val;
932
933 if (x2 == x1)
934 return y1;
935 else {
936 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
937 return val + y2;
938 }
939}
940
8b6eaea8
CB		 941/**
942 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
943 *
944 * Interpolates factory measurements from the two sample channels within a
945 * sub-band, to apply to channel of interest. Interpolation is proportional to
946 * differences in channel frequencies, which is proportional to differences
947 * in channel number.
948 */
c79dd5b5 949static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 950 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 951{
952 s32 s = -1;
953 u32 c;
954 u32 m;
073d3f5f
TW		 955 const struct iwl_eeprom_calib_measure *m1;
956 const struct iwl_eeprom_calib_measure *m2;
957 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 958 u32 ch_i1;
959 u32 ch_i2;
960
961 s = iwl4965_get_sub_band(priv, channel);
962 if (s >= EEPROM_TX_POWER_BANDS) {
15b1687c 963 IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
b481de9c
ZY		 964 return -1;
965 }
966
073d3f5f
TW		 967 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
968 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 969 chan_info->ch_num = (u8) channel;
970
e1623446 971 IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
b481de9c
ZY		 972 channel, s, ch_i1, ch_i2);
973
974 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
975 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 976 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 977 measurements[c][m]);
073d3f5f 978 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 979 measurements[c][m]);
980 omeas = &(chan_info->measurements[c][m]);
981
982 omeas->actual_pow =
983 (u8) iwl4965_interpolate_value(channel, ch_i1,
984 m1->actual_pow,
985 ch_i2,
986 m2->actual_pow);
987 omeas->gain_idx =
988 (u8) iwl4965_interpolate_value(channel, ch_i1,
989 m1->gain_idx, ch_i2,
990 m2->gain_idx);
991 omeas->temperature =
992 (u8) iwl4965_interpolate_value(channel, ch_i1,
993 m1->temperature,
994 ch_i2,
995 m2->temperature);
996 omeas->pa_det =
997 (s8) iwl4965_interpolate_value(channel, ch_i1,
998 m1->pa_det, ch_i2,
999 m2->pa_det);
1000
e1623446
TW		 1001 IWL_DEBUG_TXPOWER(priv,
1002 "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1003 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1004 IWL_DEBUG_TXPOWER(priv,
1005 "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1006 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1007 IWL_DEBUG_TXPOWER(priv,
1008 "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1009 m1->pa_det, m2->pa_det, omeas->pa_det);
1010 IWL_DEBUG_TXPOWER(priv,
1011 "chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1012 m1->temperature, m2->temperature,
1013 omeas->temperature);
b481de9c
ZY		 1014 }
1015 }
1016
1017 return 0;
1018}
1019
1020/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1021 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1022static s32 back_off_table[] = {
1023 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1024 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1025 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1026 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1027 10 /* CCK */
1028};
1029
1030/* Thermal compensation values for txpower for various frequency ranges ...
1031 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1032static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1033 s32 degrees_per_05db_a;
1034 s32 degrees_per_05db_a_denom;
1035} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1036 {9, 2}, /* group 0 5.2, ch 34-43 */
1037 {4, 1}, /* group 1 5.2, ch 44-70 */
1038 {4, 1}, /* group 2 5.2, ch 71-124 */
1039 {4, 1}, /* group 3 5.2, ch 125-200 */
1040 {3, 1} /* group 4 2.4, ch all */
1041};
1042
1043static s32 get_min_power_index(s32 rate_power_index, u32 band)
1044{
1045 if (!band) {
1046 if ((rate_power_index & 7) <= 4)
1047 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1048 }
1049 return MIN_TX_GAIN_INDEX;
1050}
1051
1052struct gain_entry {
1053 u8 dsp;
1054 u8 radio;
1055};
1056
1057static const struct gain_entry gain_table[2][108] = {
1058 /* 5.2GHz power gain index table */
1059 {
1060 {123, 0x3F}, /* highest txpower */
1061 {117, 0x3F},
1062 {110, 0x3F},
1063 {104, 0x3F},
1064 {98, 0x3F},
1065 {110, 0x3E},
1066 {104, 0x3E},
1067 {98, 0x3E},
1068 {110, 0x3D},
1069 {104, 0x3D},
1070 {98, 0x3D},
1071 {110, 0x3C},
1072 {104, 0x3C},
1073 {98, 0x3C},
1074 {110, 0x3B},
1075 {104, 0x3B},
1076 {98, 0x3B},
1077 {110, 0x3A},
1078 {104, 0x3A},
1079 {98, 0x3A},
1080 {110, 0x39},
1081 {104, 0x39},
1082 {98, 0x39},
1083 {110, 0x38},
1084 {104, 0x38},
1085 {98, 0x38},
1086 {110, 0x37},
1087 {104, 0x37},
1088 {98, 0x37},
1089 {110, 0x36},
1090 {104, 0x36},
1091 {98, 0x36},
1092 {110, 0x35},
1093 {104, 0x35},
1094 {98, 0x35},
1095 {110, 0x34},
1096 {104, 0x34},
1097 {98, 0x34},
1098 {110, 0x33},
1099 {104, 0x33},
1100 {98, 0x33},
1101 {110, 0x32},
1102 {104, 0x32},
1103 {98, 0x32},
1104 {110, 0x31},
1105 {104, 0x31},
1106 {98, 0x31},
1107 {110, 0x30},
1108 {104, 0x30},
1109 {98, 0x30},
1110 {110, 0x25},
1111 {104, 0x25},
1112 {98, 0x25},
1113 {110, 0x24},
1114 {104, 0x24},
1115 {98, 0x24},
1116 {110, 0x23},
1117 {104, 0x23},
1118 {98, 0x23},
1119 {110, 0x22},
1120 {104, 0x18},
1121 {98, 0x18},
1122 {110, 0x17},
1123 {104, 0x17},
1124 {98, 0x17},
1125 {110, 0x16},
1126 {104, 0x16},
1127 {98, 0x16},
1128 {110, 0x15},
1129 {104, 0x15},
1130 {98, 0x15},
1131 {110, 0x14},
1132 {104, 0x14},
1133 {98, 0x14},
1134 {110, 0x13},
1135 {104, 0x13},
1136 {98, 0x13},
1137 {110, 0x12},
1138 {104, 0x08},
1139 {98, 0x08},
1140 {110, 0x07},
1141 {104, 0x07},
1142 {98, 0x07},
1143 {110, 0x06},
1144 {104, 0x06},
1145 {98, 0x06},
1146 {110, 0x05},
1147 {104, 0x05},
1148 {98, 0x05},
1149 {110, 0x04},
1150 {104, 0x04},
1151 {98, 0x04},
1152 {110, 0x03},
1153 {104, 0x03},
1154 {98, 0x03},
1155 {110, 0x02},
1156 {104, 0x02},
1157 {98, 0x02},
1158 {110, 0x01},
1159 {104, 0x01},
1160 {98, 0x01},
1161 {110, 0x00},
1162 {104, 0x00},
1163 {98, 0x00},
1164 {93, 0x00},
1165 {88, 0x00},
1166 {83, 0x00},
1167 {78, 0x00},
1168 },
1169 /* 2.4GHz power gain index table */
1170 {
1171 {110, 0x3f}, /* highest txpower */
1172 {104, 0x3f},
1173 {98, 0x3f},
1174 {110, 0x3e},
1175 {104, 0x3e},
1176 {98, 0x3e},
1177 {110, 0x3d},
1178 {104, 0x3d},
1179 {98, 0x3d},
1180 {110, 0x3c},
1181 {104, 0x3c},
1182 {98, 0x3c},
1183 {110, 0x3b},
1184 {104, 0x3b},
1185 {98, 0x3b},
1186 {110, 0x3a},
1187 {104, 0x3a},
1188 {98, 0x3a},
1189 {110, 0x39},
1190 {104, 0x39},
1191 {98, 0x39},
1192 {110, 0x38},
1193 {104, 0x38},
1194 {98, 0x38},
1195 {110, 0x37},
1196 {104, 0x37},
1197 {98, 0x37},
1198 {110, 0x36},
1199 {104, 0x36},
1200 {98, 0x36},
1201 {110, 0x35},
1202 {104, 0x35},
1203 {98, 0x35},
1204 {110, 0x34},
1205 {104, 0x34},
1206 {98, 0x34},
1207 {110, 0x33},
1208 {104, 0x33},
1209 {98, 0x33},
1210 {110, 0x32},
1211 {104, 0x32},
1212 {98, 0x32},
1213 {110, 0x31},
1214 {104, 0x31},
1215 {98, 0x31},
1216 {110, 0x30},
1217 {104, 0x30},
1218 {98, 0x30},
1219 {110, 0x6},
1220 {104, 0x6},
1221 {98, 0x6},
1222 {110, 0x5},
1223 {104, 0x5},
1224 {98, 0x5},
1225 {110, 0x4},
1226 {104, 0x4},
1227 {98, 0x4},
1228 {110, 0x3},
1229 {104, 0x3},
1230 {98, 0x3},
1231 {110, 0x2},
1232 {104, 0x2},
1233 {98, 0x2},
1234 {110, 0x1},
1235 {104, 0x1},
1236 {98, 0x1},
1237 {110, 0x0},
1238 {104, 0x0},
1239 {98, 0x0},
1240 {97, 0},
1241 {96, 0},
1242 {95, 0},
1243 {94, 0},
1244 {93, 0},
1245 {92, 0},
1246 {91, 0},
1247 {90, 0},
1248 {89, 0},
1249 {88, 0},
1250 {87, 0},
1251 {86, 0},
1252 {85, 0},
1253 {84, 0},
1254 {83, 0},
1255 {82, 0},
1256 {81, 0},
1257 {80, 0},
1258 {79, 0},
1259 {78, 0},
1260 {77, 0},
1261 {76, 0},
1262 {75, 0},
1263 {74, 0},
1264 {73, 0},
1265 {72, 0},
1266 {71, 0},
1267 {70, 0},
1268 {69, 0},
1269 {68, 0},
1270 {67, 0},
1271 {66, 0},
1272 {65, 0},
1273 {64, 0},
1274 {63, 0},
1275 {62, 0},
1276 {61, 0},
1277 {60, 0},
1278 {59, 0},
1279 }
1280};
1281
c79dd5b5 1282static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1283 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1284 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1285{
1286 u8 saturation_power;
1287 s32 target_power;
1288 s32 user_target_power;
1289 s32 power_limit;
1290 s32 current_temp;
1291 s32 reg_limit;
1292 s32 current_regulatory;
1293 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1294 int i;
1295 int c;
bf85ea4f 1296 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1297 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1298 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1299 s16 voltage;
1300 s32 init_voltage;
1301 s32 voltage_compensation;
1302 s32 degrees_per_05db_num;
1303 s32 degrees_per_05db_denom;
1304 s32 factory_temp;
1305 s32 temperature_comp[2];
1306 s32 factory_gain_index[2];
1307 s32 factory_actual_pwr[2];
1308 s32 power_index;
1309
62ea9c5b 1310 /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
b481de9c 1311 * are used for indexing into txpower table) */
630fe9b6 1312 user_target_power = 2 * priv->tx_power_user_lmt;
b481de9c
ZY		 1313
1314 /* Get current (RXON) channel, band, width */
e1623446 1315 IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_fat %d\n", channel, band,
b481de9c
ZY		 1316 is_fat);
1317
630fe9b6
TW		 1318 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1319
1320 if (!is_channel_valid(ch_info))
b481de9c
ZY		 1321 return -EINVAL;
1322
1323 /* get txatten group, used to select 1) thermal txpower adjustment
1324 * and 2) mimo txpower balance between Tx chains. */
1325 txatten_grp = iwl4965_get_tx_atten_grp(channel);
a3139c59 1326 if (txatten_grp < 0) {
15b1687c 1327 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
a3139c59 1328 channel);
b481de9c 1329 return -EINVAL;
a3139c59 1330 }
b481de9c 1331
e1623446 1332 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
b481de9c
ZY		 1333 channel, txatten_grp);
1334
1335 if (is_fat) {
1336 if (ctrl_chan_high)
1337 channel -= 2;
1338 else
1339 channel += 2;
1340 }
1341
1342 /* hardware txpower limits ...
1343 * saturation (clipping distortion) txpowers are in half-dBm */
1344 if (band)
073d3f5f 1345 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1346 else
073d3f5f 1347 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1348
1349 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1350 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1351 if (band)
1352 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1353 else
1354 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1355 }
1356
1357 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1358 * max_power_avg values are in dBm, convert * 2 */
1359 if (is_fat)
1360 reg_limit = ch_info->fat_max_power_avg * 2;
1361 else
1362 reg_limit = ch_info->max_power_avg * 2;
1363
1364 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1365 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1366 if (band)
1367 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1368 else
1369 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1370 }
1371
1372 /* Interpolate txpower calibration values for this channel,
1373 * based on factory calibration tests on spaced channels. */
1374 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1375
1376 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 1377 voltage = priv->calib_info->voltage;
b481de9c
ZY		 1378 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1379 voltage_compensation =
1380 iwl4965_get_voltage_compensation(voltage, init_voltage);
1381
e1623446 1382 IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
b481de9c
ZY		 1383 init_voltage,
1384 voltage, voltage_compensation);
1385
1386 /* get current temperature (Celsius) */
1387 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1388 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1389 current_temp = KELVIN_TO_CELSIUS(current_temp);
1390
1391 /* select thermal txpower adjustment params, based on channel group
1392 * (same frequency group used for mimo txatten adjustment) */
1393 degrees_per_05db_num =
1394 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1395 degrees_per_05db_denom =
1396 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1397
1398 /* get per-chain txpower values from factory measurements */
1399 for (c = 0; c < 2; c++) {
1400 measurement = &ch_eeprom_info.measurements[c][1];
1401
1402 /* txgain adjustment (in half-dB steps) based on difference
1403 * between factory and current temperature */
1404 factory_temp = measurement->temperature;
1405 iwl4965_math_div_round((current_temp - factory_temp) *
1406 degrees_per_05db_denom,
1407 degrees_per_05db_num,
1408 &temperature_comp[c]);
1409
1410 factory_gain_index[c] = measurement->gain_idx;
1411 factory_actual_pwr[c] = measurement->actual_pow;
1412
e1623446
TW		 1413 IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
1414 IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
b481de9c
ZY		 1415 "curr tmp %d, comp %d steps\n",
1416 factory_temp, current_temp,
1417 temperature_comp[c]);
1418
e1623446 1419 IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
b481de9c
ZY		 1420 factory_gain_index[c],
1421 factory_actual_pwr[c]);
1422 }
1423
1424 /* for each of 33 bit-rates (including 1 for CCK) */
1425 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1426 u8 is_mimo_rate;
bb8c093b 1427 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 1428
1429 /* for mimo, reduce each chain's txpower by half
1430 * (3dB, 6 steps), so total output power is regulatory
1431 * compliant. */
1432 if (i & 0x8) {
1433 current_regulatory = reg_limit -
1434 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1435 is_mimo_rate = 1;
1436 } else {
1437 current_regulatory = reg_limit;
1438 is_mimo_rate = 0;
1439 }
1440
1441 /* find txpower limit, either hardware or regulatory */
1442 power_limit = saturation_power - back_off_table[i];
1443 if (power_limit > current_regulatory)
1444 power_limit = current_regulatory;
1445
1446 /* reduce user's txpower request if necessary
1447 * for this rate on this channel */
1448 target_power = user_target_power;
1449 if (target_power > power_limit)
1450 target_power = power_limit;
1451
e1623446 1452 IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
b481de9c
ZY		 1453 i, saturation_power - back_off_table[i],
1454 current_regulatory, user_target_power,
1455 target_power);
1456
1457 /* for each of 2 Tx chains (radio transmitters) */
1458 for (c = 0; c < 2; c++) {
1459 s32 atten_value;
1460
1461 if (is_mimo_rate)
1462 atten_value =
1463 (s32)le32_to_cpu(priv->card_alive_init.
1464 tx_atten[txatten_grp][c]);
1465 else
1466 atten_value = 0;
1467
1468 /* calculate index; higher index means lower txpower */
1469 power_index = (u8) (factory_gain_index[c] -
1470 (target_power -
1471 factory_actual_pwr[c]) -
1472 temperature_comp[c] -
1473 voltage_compensation +
1474 atten_value);
1475
e1623446 1476/* IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
b481de9c
ZY		 1477 power_index); */
1478
1479 if (power_index < get_min_power_index(i, band))
1480 power_index = get_min_power_index(i, band);
1481
1482 /* adjust 5 GHz index to support negative indexes */
1483 if (!band)
1484 power_index += 9;
1485
1486 /* CCK, rate 32, reduce txpower for CCK */
1487 if (i == POWER_TABLE_CCK_ENTRY)
1488 power_index +=
1489 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1490
1491 /* stay within the table! */
1492 if (power_index > 107) {
39aadf8c 1493 IWL_WARN(priv, "txpower index %d > 107\n",
b481de9c
ZY		 1494 power_index);
1495 power_index = 107;
1496 }
1497 if (power_index < 0) {
39aadf8c 1498 IWL_WARN(priv, "txpower index %d < 0\n",
b481de9c
ZY		 1499 power_index);
1500 power_index = 0;
1501 }
1502
1503 /* fill txpower command for this rate/chain */
1504 tx_power.s.radio_tx_gain[c] =
1505 gain_table[band][power_index].radio;
1506 tx_power.s.dsp_predis_atten[c] =
1507 gain_table[band][power_index].dsp;
1508
e1623446 1509 IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
b481de9c
ZY		 1510 "gain 0x%02x dsp %d\n",
1511 c, atten_value, power_index,
1512 tx_power.s.radio_tx_gain[c],
1513 tx_power.s.dsp_predis_atten[c]);
3ac7f146 1514 } /* for each chain */
b481de9c
ZY		 1515
1516 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1517
3ac7f146 1518 } /* for each rate */
b481de9c
ZY		 1519
1520 return 0;
1521}
1522
1523/**
630fe9b6 1524 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
b481de9c
ZY		 1525 *
1526 * Uses the active RXON for channel, band, and characteristics (fat, high)
630fe9b6 1527 * The power limit is taken from priv->tx_power_user_lmt.
b481de9c 1528 */
630fe9b6 1529static int iwl4965_send_tx_power(struct iwl_priv *priv)
b481de9c 1530{
bb8c093b 1531 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 1532 int ret;
b481de9c
ZY		 1533 u8 band = 0;
1534 u8 is_fat = 0;
1535 u8 ctrl_chan_high = 0;
1536
1537 if (test_bit(STATUS_SCANNING, &priv->status)) {
1538 /* If this gets hit a lot, switch it to a BUG() and catch
1539 * the stack trace to find out who is calling this during
1540 * a scan. */
39aadf8c 1541 IWL_WARN(priv, "TX Power requested while scanning!\n");
b481de9c
ZY		 1542 return -EAGAIN;
1543 }
1544
8318d78a 1545 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 1546
1547 is_fat = is_fat_channel(priv->active_rxon.flags);
1548
1549 if (is_fat &&
1550 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1551 ctrl_chan_high = 1;
1552
1553 cmd.band = band;
1554 cmd.channel = priv->active_rxon.channel;
1555
857485c0 1556 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 1557 le16_to_cpu(priv->active_rxon.channel),
1558 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 1559 if (ret)
1560 goto out;
b481de9c 1561
857485c0
TW		 1562 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1563
1564out:
1565 return ret;
b481de9c
ZY		 1566}
1567
7e8c519e
TW		 1568static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1569{
1570 int ret = 0;
1571 struct iwl4965_rxon_assoc_cmd rxon_assoc;
c1adf9fb
GG		 1572 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1573 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
7e8c519e
TW		 1574
1575 if ((rxon1->flags == rxon2->flags) &&
1576 (rxon1->filter_flags == rxon2->filter_flags) &&
1577 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1578 (rxon1->ofdm_ht_single_stream_basic_rates ==
1579 rxon2->ofdm_ht_single_stream_basic_rates) &&
1580 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1581 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1582 (rxon1->rx_chain == rxon2->rx_chain) &&
1583 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
e1623446 1584 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
7e8c519e
TW		 1585 return 0;
1586 }
1587
1588 rxon_assoc.flags = priv->staging_rxon.flags;
1589 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1590 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1591 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1592 rxon_assoc.reserved = 0;
1593 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1594 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1595 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1596 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1597 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1598
1599 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1600 sizeof(rxon_assoc), &rxon_assoc, NULL);
1601 if (ret)
1602 return ret;
1603
1604 return ret;
1605}
1606
3c935522 1607#ifdef IEEE80211_CONF_CHANNEL_SWITCH
a33c2f47 1608static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1609{
1610 int rc;
1611 u8 band = 0;
1612 u8 is_fat = 0;
1613 u8 ctrl_chan_high = 0;
bb8c093b 1614 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 1615 const struct iwl_channel_info *ch_info;
b481de9c 1616
8318d78a 1617 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 1618
8622e705 1619 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 1620
1621 is_fat = is_fat_channel(priv->staging_rxon.flags);
1622
1623 if (is_fat &&
1624 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1625 ctrl_chan_high = 1;
1626
1627 cmd.band = band;
1628 cmd.expect_beacon = 0;
1629 cmd.channel = cpu_to_le16(channel);
1630 cmd.rxon_flags = priv->active_rxon.flags;
1631 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1632 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1633 if (ch_info)
1634 cmd.expect_beacon = is_channel_radar(ch_info);
1635 else
1636 cmd.expect_beacon = 1;
1637
1638 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
1639 ctrl_chan_high, &cmd.tx_power);
1640 if (rc) {
e1623446 1641 IWL_DEBUG_11H(priv, "error:%d fill txpower_tbl\n", rc);
b481de9c
ZY		 1642 return rc;
1643 }
1644
857485c0 1645 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 1646 return rc;
1647}
3c935522 1648#endif
b481de9c 1649
8b6eaea8 1650/**
e2a722eb 1651 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 1652 */
e2a722eb 1653static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 1654 struct iwl_tx_queue *txq,
e2a722eb 1655 u16 byte_cnt)
b481de9c 1656{
4ddbb7d0 1657 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 1658 int txq_id = txq->q.id;
1659 int write_ptr = txq->q.write_ptr;
1660 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1661 __le16 bc_ent;
b481de9c 1662
127901ab 1663 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
b481de9c 1664
127901ab 1665 bc_ent = cpu_to_le16(len & 0xFFF);
8b6eaea8 1666 /* Set up byte count within first 256 entries */
4ddbb7d0 1667 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
b481de9c 1668
8b6eaea8 1669 /* If within first 64 entries, duplicate at end */
127901ab 1670 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 1671 scd_bc_tbl[txq_id].
127901ab 1672 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
b481de9c
ZY		 1673}
1674
b481de9c
ZY		 1675/**
1676 * sign_extend - Sign extend a value using specified bit as sign-bit
1677 *
1678 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1679 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1680 *
1681 * @param oper value to sign extend
1682 * @param index 0 based bit index (0<=index<32) to sign bit
1683 */
1684static s32 sign_extend(u32 oper, int index)
1685{
1686 u8 shift = 31 - index;
1687
1688 return (s32)(oper << shift) >> shift;
1689}
1690
1691/**
91dbc5bd 1692 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
b481de9c
ZY		 1693 * @statistics: Provides the temperature reading from the uCode
1694 *
1695 * A return of <0 indicates bogus data in the statistics
1696 */
91dbc5bd 1697static int iwl4965_hw_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 1698{
1699 s32 temperature;
1700 s32 vt;
1701 s32 R1, R2, R3;
1702 u32 R4;
1703
1704 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1705 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
e1623446 1706 IWL_DEBUG_TEMP(priv, "Running FAT temperature calibration\n");
b481de9c
ZY		 1707 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1708 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1709 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1710 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1711 } else {
e1623446 1712 IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
b481de9c
ZY		 1713 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1714 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1715 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1716 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1717 }
1718
1719 /*
8b6eaea8 1720 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 1721 *
1722 * NOTE If we haven't received a statistics notification yet
1723 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 1724 * "initialize" ALIVE response.
1725 */
b481de9c
ZY		 1726 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1727 vt = sign_extend(R4, 23);
1728 else
1729 vt = sign_extend(
1730 le32_to_cpu(priv->statistics.general.temperature), 23);
1731
e1623446 1732 IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
b481de9c
ZY		 1733
1734 if (R3 == R1) {
15b1687c 1735 IWL_ERR(priv, "Calibration conflict R1 == R3\n");
b481de9c
ZY		 1736 return -1;
1737 }
1738
1739 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1740 * Add offset to center the adjustment around 0 degrees Centigrade. */
1741 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1742 temperature /= (R3 - R1);
91dbc5bd 1743 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
b481de9c 1744
e1623446 1745 IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
91dbc5bd 1746 temperature, KELVIN_TO_CELSIUS(temperature));
b481de9c
ZY		 1747
1748 return temperature;
1749}
1750
1751/* Adjust Txpower only if temperature variance is greater than threshold. */
1752#define IWL_TEMPERATURE_THRESHOLD 3
1753
1754/**
1755 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1756 *
1757 * If the temperature changed has changed sufficiently, then a recalibration
1758 * is needed.
1759 *
1760 * Assumes caller will replace priv->last_temperature once calibration
1761 * executed.
1762 */
c79dd5b5 1763static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1764{
1765 int temp_diff;
1766
1767 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
e1623446 1768 IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
b481de9c
ZY		 1769 return 0;
1770 }
1771
1772 temp_diff = priv->temperature - priv->last_temperature;
1773
1774 /* get absolute value */
1775 if (temp_diff < 0) {
e1623446 1776 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d, \n", temp_diff);
b481de9c
ZY		 1777 temp_diff = -temp_diff;
1778 } else if (temp_diff == 0)
e1623446 1779 IWL_DEBUG_POWER(priv, "Same temp, \n");
b481de9c 1780 else
e1623446 1781 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d, \n", temp_diff);
b481de9c
ZY		 1782
1783 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
e1623446 1784 IWL_DEBUG_POWER(priv, "Thermal txpower calib not needed\n");
b481de9c
ZY		 1785 return 0;
1786 }
1787
e1623446 1788 IWL_DEBUG_POWER(priv, "Thermal txpower calib needed\n");
b481de9c
ZY		 1789
1790 return 1;
1791}
1792
5225640b 1793static void iwl4965_temperature_calib(struct iwl_priv *priv)
b481de9c 1794{
b481de9c 1795 s32 temp;
b481de9c 1796
91dbc5bd 1797 temp = iwl4965_hw_get_temperature(priv);
b481de9c
ZY		 1798 if (temp < 0)
1799 return;
1800
1801 if (priv->temperature != temp) {
1802 if (priv->temperature)
e1623446 1803 IWL_DEBUG_TEMP(priv, "Temperature changed "
b481de9c
ZY		 1804 "from %dC to %dC\n",
1805 KELVIN_TO_CELSIUS(priv->temperature),
1806 KELVIN_TO_CELSIUS(temp));
1807 else
e1623446 1808 IWL_DEBUG_TEMP(priv, "Temperature "
b481de9c
ZY		 1809 "initialized to %dC\n",
1810 KELVIN_TO_CELSIUS(temp));
1811 }
1812
1813 priv->temperature = temp;
1814 set_bit(STATUS_TEMPERATURE, &priv->status);
1815
203566f3
EG		 1816 if (!priv->disable_tx_power_cal &&
1817 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1818 iwl4965_is_temp_calib_needed(priv))
b481de9c
ZY		 1819 queue_work(priv->workqueue, &priv->txpower_work);
1820}
1821
fe01b477
RR		 1822/**
1823 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1824 */
c79dd5b5 1825static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 1826 u16 txq_id)
1827{
1828 /* Simply stop the queue, but don't change any configuration;
1829 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 1830 iwl_write_prph(priv,
12a81f60 1831 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 1832 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1833 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
fe01b477 1834}
b481de9c 1835
fe01b477 1836/**
7f3e4bb6 1837 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
b095d03a 1838 * priv->lock must be held by the caller
fe01b477 1839 */
30e553e3
TW		 1840static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1841 u16 ssn_idx, u8 tx_fifo)
fe01b477 1842{
b095d03a
RR		 1843 int ret = 0;
1844
9f17b318
TW		 1845 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1846 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
39aadf8c
WT		 1847 IWL_WARN(priv,
1848 "queue number out of range: %d, must be %d to %d\n",
9f17b318
TW		 1849 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1850 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
fe01b477 1851 return -EINVAL;
b481de9c
ZY		 1852 }
1853
3395f6e9 1854 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 1855 if (ret)
1856 return ret;
1857
fe01b477
RR		 1858 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1859
12a81f60 1860 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 1861
1862 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1863 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1864 /* supposes that ssn_idx is valid (!= 0xFFF) */
1865 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1866
12a81f60 1867 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
36470749 1868 iwl_txq_ctx_deactivate(priv, txq_id);
fe01b477
RR		 1869 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1870
3395f6e9 1871 iwl_release_nic_access(priv);
b095d03a 1872
fe01b477
RR		 1873 return 0;
1874}
b481de9c 1875
8b6eaea8
CB		 1876/**
1877 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1878 */
c79dd5b5 1879static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 1880 u16 txq_id)
1881{
1882 u32 tbl_dw_addr;
1883 u32 tbl_dw;
1884 u16 scd_q2ratid;
1885
30e553e3 1886 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
b481de9c
ZY		 1887
1888 tbl_dw_addr = priv->scd_base_addr +
038669e4 1889 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
b481de9c 1890
3395f6e9 1891 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 1892
1893 if (txq_id & 0x1)
1894 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1895 else
1896 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1897
3395f6e9 1898 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 1899
1900 return 0;
1901}
1902
fe01b477 1903
b481de9c 1904/**
8b6eaea8
CB		 1905 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1906 *
7f3e4bb6 1907 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
8b6eaea8 1908 * i.e. it must be one of the higher queues used for aggregation
b481de9c 1909 */
30e553e3
TW		 1910static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1911 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
b481de9c
ZY		 1912{
1913 unsigned long flags;
30e553e3 1914 int ret;
b481de9c
ZY		 1915 u16 ra_tid;
1916
9f17b318
TW		 1917 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1918 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
39aadf8c
WT		 1919 IWL_WARN(priv,
1920 "queue number out of range: %d, must be %d to %d\n",
9f17b318
TW		 1921 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1922 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
1923 return -EINVAL;
1924 }
b481de9c
ZY		 1925
1926 ra_tid = BUILD_RAxTID(sta_id, tid);
1927
8b6eaea8 1928 /* Modify device's station table to Tx this TID */
9f58671e 1929 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
b481de9c
ZY		 1930
1931 spin_lock_irqsave(&priv->lock, flags);
30e553e3
TW		 1932 ret = iwl_grab_nic_access(priv);
1933 if (ret) {
b481de9c 1934 spin_unlock_irqrestore(&priv->lock, flags);
30e553e3 1935 return ret;
b481de9c
ZY		 1936 }
1937
8b6eaea8 1938 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 1939 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1940
8b6eaea8 1941 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 1942 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1943
8b6eaea8 1944 /* Set this queue as a chain-building queue */
12a81f60 1945 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 1946
8b6eaea8
CB		 1947 /* Place first TFD at index corresponding to start sequence number.
1948 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 1949 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1950 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 1951 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1952
8b6eaea8 1953 /* Set up Tx window size and frame limit for this queue */
3395f6e9 1954 iwl_write_targ_mem(priv,
038669e4
EG		 1955 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1956 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1957 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
b481de9c 1958
3395f6e9 1959 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 1960 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1961 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1962 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c 1963
12a81f60 1964 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 1965
8b6eaea8 1966 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 1967 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1968
3395f6e9 1969 iwl_release_nic_access(priv);
b481de9c
ZY		 1970 spin_unlock_irqrestore(&priv->lock, flags);
1971
1972 return 0;
1973}
1974
133636de 1975
c1adf9fb
GG		 1976static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1977{
1978 switch (cmd_id) {
1979 case REPLY_RXON:
1980 return (u16) sizeof(struct iwl4965_rxon_cmd);
1981 default:
1982 return len;
1983 }
1984}
1985
133636de
TW		 1986static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1987{
1988 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1989 addsta->mode = cmd->mode;
1990 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1991 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1992 addsta->station_flags = cmd->station_flags;
1993 addsta->station_flags_msk = cmd->station_flags_msk;
1994 addsta->tid_disable_tx = cmd->tid_disable_tx;
1995 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1996 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1997 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1998 addsta->reserved1 = __constant_cpu_to_le16(0);
1999 addsta->reserved2 = __constant_cpu_to_le32(0);
2000
2001 return (u16)sizeof(struct iwl4965_addsta_cmd);
2002}
f20217d9 2003
f20217d9
TW		 2004static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
2005{
25a6572c 2006 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
f20217d9
TW		 2007}
2008
2009/**
a96a27f9 2010 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
f20217d9
TW		 2011 */
2012static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
2013 struct iwl_ht_agg *agg,
25a6572c
TW		 2014 struct iwl4965_tx_resp *tx_resp,
2015 int txq_id, u16 start_idx)
f20217d9
TW		 2016{
2017 u16 status;
25a6572c 2018 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
f20217d9
TW		 2019 struct ieee80211_tx_info *info = NULL;
2020 struct ieee80211_hdr *hdr = NULL;
e7d326ac 2021 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 2022 int i, sh, idx;
f20217d9 2023 u16 seq;
f20217d9 2024 if (agg->wait_for_ba)
e1623446 2025 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
f20217d9
TW		 2026
2027 agg->frame_count = tx_resp->frame_count;
2028 agg->start_idx = start_idx;
e7d326ac 2029 agg->rate_n_flags = rate_n_flags;
f20217d9
TW		 2030 agg->bitmap = 0;
2031
3fd07a1e 2032 /* num frames attempted by Tx command */
f20217d9
TW		 2033 if (agg->frame_count == 1) {
2034 /* Only one frame was attempted; no block-ack will arrive */
2035 status = le16_to_cpu(frame_status[0].status);
25a6572c 2036 idx = start_idx;
f20217d9
TW		 2037
2038 /* FIXME: code repetition */
e1623446 2039 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
f20217d9
TW		 2040 agg->frame_count, agg->start_idx, idx);
2041
2042 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 2043 info->status.rates[0].count = tx_resp->failure_frame + 1;
f20217d9 2044 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c3056065 2045 info->flags |= iwl_is_tx_success(status) ?
f20217d9 2046 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2047 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
f20217d9
TW		 2048 /* FIXME: code repetition end */
2049
e1623446 2050 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
f20217d9 2051 status & 0xff, tx_resp->failure_frame);
e1623446 2052 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
f20217d9
TW		 2053
2054 agg->wait_for_ba = 0;
2055 } else {
2056 /* Two or more frames were attempted; expect block-ack */
2057 u64 bitmap = 0;
2058 int start = agg->start_idx;
2059
2060 /* Construct bit-map of pending frames within Tx window */
2061 for (i = 0; i < agg->frame_count; i++) {
2062 u16 sc;
2063 status = le16_to_cpu(frame_status[i].status);
2064 seq = le16_to_cpu(frame_status[i].sequence);
2065 idx = SEQ_TO_INDEX(seq);
2066 txq_id = SEQ_TO_QUEUE(seq);
2067
2068 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
2069 AGG_TX_STATE_ABORT_MSK))
2070 continue;
2071
e1623446 2072 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
f20217d9
TW		 2073 agg->frame_count, txq_id, idx);
2074
2075 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
2076
2077 sc = le16_to_cpu(hdr->seq_ctrl);
2078 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
15b1687c
WT		 2079 IWL_ERR(priv,
2080 "BUG_ON idx doesn't match seq control"
2081 " idx=%d, seq_idx=%d, seq=%d\n",
2082 idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
f20217d9
TW		 2083 return -1;
2084 }
2085
e1623446 2086 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
f20217d9
TW		 2087 i, idx, SEQ_TO_SN(sc));
2088
2089 sh = idx - start;
2090 if (sh > 64) {
2091 sh = (start - idx) + 0xff;
2092 bitmap = bitmap << sh;
2093 sh = 0;
2094 start = idx;
2095 } else if (sh < -64)
2096 sh = 0xff - (start - idx);
2097 else if (sh < 0) {
2098 sh = start - idx;
2099 start = idx;
2100 bitmap = bitmap << sh;
2101 sh = 0;
2102 }
4aa41f12 2103 bitmap |= 1ULL << sh;
e1623446 2104 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
4aa41f12 2105 start, (unsigned long long)bitmap);
f20217d9
TW		 2106 }
2107
2108 agg->bitmap = bitmap;
2109 agg->start_idx = start;
e1623446 2110 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
f20217d9
TW		 2111 agg->frame_count, agg->start_idx,
2112 (unsigned long long)agg->bitmap);
2113
2114 if (bitmap)
2115 agg->wait_for_ba = 1;
2116 }
2117 return 0;
2118}
f20217d9
TW		 2119
2120/**
2121 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2122 */
2123static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2124 struct iwl_rx_mem_buffer *rxb)
2125{
2126 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2127 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2128 int txq_id = SEQ_TO_QUEUE(sequence);
2129 int index = SEQ_TO_INDEX(sequence);
2130 struct iwl_tx_queue *txq = &priv->txq[txq_id];
3fd07a1e 2131 struct ieee80211_hdr *hdr;
f20217d9
TW		 2132 struct ieee80211_tx_info *info;
2133 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
25a6572c 2134 u32 status = le32_to_cpu(tx_resp->u.status);
3fd07a1e
TW		 2135 int tid = MAX_TID_COUNT;
2136 int sta_id;
2137 int freed;
f20217d9 2138 u8 *qc = NULL;
f20217d9
TW		 2139
2140 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 2141 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
f20217d9
TW		 2142 "is out of range [0-%d] %d %d\n", txq_id,
2143 index, txq->q.n_bd, txq->q.write_ptr,
2144 txq->q.read_ptr);
2145 return;
2146 }
2147
2148 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2149 memset(&info->status, 0, sizeof(info->status));
2150
f20217d9 2151 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
3fd07a1e 2152 if (ieee80211_is_data_qos(hdr->frame_control)) {
fd7c8a40 2153 qc = ieee80211_get_qos_ctl(hdr);
f20217d9
TW		 2154 tid = qc[0] & 0xf;
2155 }
2156
2157 sta_id = iwl_get_ra_sta_id(priv, hdr);
2158 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
15b1687c 2159 IWL_ERR(priv, "Station not known\n");
f20217d9
TW		 2160 return;
2161 }
2162
2163 if (txq->sched_retry) {
2164 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2165 struct iwl_ht_agg *agg = NULL;
2166
3fd07a1e 2167 WARN_ON(!qc);
f20217d9
TW		 2168
2169 agg = &priv->stations[sta_id].tid[tid].agg;
2170
25a6572c 2171 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
f20217d9 2172
3235427e
RR		 2173 /* check if BAR is needed */
2174 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2175 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
f20217d9
TW		 2176
2177 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
f20217d9 2178 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
e1623446 2179 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
f20217d9 2180 "%d index %d\n", scd_ssn , index);
17b88929 2181 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
f20217d9
TW		 2182 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2183
3fd07a1e
TW		 2184 if (priv->mac80211_registered &&
2185 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2186 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
f20217d9
TW		 2187 if (agg->state == IWL_AGG_OFF)
2188 ieee80211_wake_queue(priv->hw, txq_id);
2189 else
3fd07a1e
TW		 2190 ieee80211_wake_queue(priv->hw,
2191 txq->swq_id);
f20217d9 2192 }
f20217d9
TW		 2193 }
2194 } else {
e6a9854b 2195 info->status.rates[0].count = tx_resp->failure_frame + 1;
3fd07a1e
TW		 2196 info->flags |= iwl_is_tx_success(status) ?
2197 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2198 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 2199 le32_to_cpu(tx_resp->rate_n_flags),
2200 info);
2201
e1623446 2202 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
3fd07a1e
TW		 2203 "rate_n_flags 0x%x retries %d\n",
2204 txq_id,
2205 iwl_get_tx_fail_reason(status), status,
2206 le32_to_cpu(tx_resp->rate_n_flags),
2207 tx_resp->failure_frame);
e7d326ac 2208
3fd07a1e 2209 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
ed7fafec 2210 if (qc && likely(sta_id != IWL_INVALID_STATION))
f20217d9 2211 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 2212
2213 if (priv->mac80211_registered &&
2214 (iwl_queue_space(&txq->q) > txq->q.low_mark))
f20217d9 2215 ieee80211_wake_queue(priv->hw, txq_id);
f20217d9 2216 }
f20217d9 2217
ed7fafec 2218 if (qc && likely(sta_id != IWL_INVALID_STATION))
3fd07a1e
TW		 2219 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
2220
f20217d9 2221 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 2222 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
f20217d9
TW		 2223}
2224
caab8f1a
TW		 2225static int iwl4965_calc_rssi(struct iwl_priv *priv,
2226 struct iwl_rx_phy_res *rx_resp)
2227{
2228 /* data from PHY/DSP regarding signal strength, etc.,
2229 * contents are always there, not configurable by host. */
2230 struct iwl4965_rx_non_cfg_phy *ncphy =
2231 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2232 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2233 >> IWL49_AGC_DB_POS;
2234
2235 u32 valid_antennae =
2236 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2237 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2238 u8 max_rssi = 0;
2239 u32 i;
2240
2241 /* Find max rssi among 3 possible receivers.
2242 * These values are measured by the digital signal processor (DSP).
2243 * They should stay fairly constant even as the signal strength varies,
2244 * if the radio's automatic gain control (AGC) is working right.
2245 * AGC value (see below) will provide the "interesting" info. */
2246 for (i = 0; i < 3; i++)
2247 if (valid_antennae & (1 << i))
2248 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2249
e1623446 2250 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
caab8f1a
TW		 2251 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2252 max_rssi, agc);
2253
2254 /* dBm = max_rssi dB - agc dB - constant.
2255 * Higher AGC (higher radio gain) means lower signal. */
250bdd21 2256 return max_rssi - agc - IWL49_RSSI_OFFSET;
caab8f1a
TW		 2257}
2258
f20217d9 2259
b481de9c 2260/* Set up 4965-specific Rx frame reply handlers */
d4789efe 2261static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 2262{
2263 /* Legacy Rx frames */
1781a07f 2264 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
37a44211 2265 /* Tx response */
f20217d9 2266 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
b481de9c
ZY		 2267}
2268
4e39317d 2269static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2270{
2271 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
b481de9c
ZY		 2272}
2273
4e39317d 2274static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2275{
4e39317d 2276 cancel_work_sync(&priv->txpower_work);
b481de9c
ZY		 2277}
2278
3c424c28
TW		 2279
2280static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 2281 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 2282};
2283
857485c0 2284static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
c1adf9fb 2285 .get_hcmd_size = iwl4965_get_hcmd_size,
133636de 2286 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
f0832f13
EG		 2287 .chain_noise_reset = iwl4965_chain_noise_reset,
2288 .gain_computation = iwl4965_gain_computation,
a326a5d0 2289 .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag,
caab8f1a 2290 .calc_rssi = iwl4965_calc_rssi,
857485c0
TW		 2291};
2292
6bc913bd 2293static struct iwl_lib_ops iwl4965_lib = {
5425e490 2294 .set_hw_params = iwl4965_hw_set_hw_params,
e2a722eb 2295 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
da1bc453 2296 .txq_set_sched = iwl4965_txq_set_sched,
30e553e3
TW		 2297 .txq_agg_enable = iwl4965_txq_agg_enable,
2298 .txq_agg_disable = iwl4965_txq_agg_disable,
7aaa1d79
SO		 2299 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
2300 .txq_free_tfd = iwl_hw_txq_free_tfd,
a8e74e27 2301 .txq_init = iwl_hw_tx_queue_init,
d4789efe 2302 .rx_handler_setup = iwl4965_rx_handler_setup,
4e39317d
EG		 2303 .setup_deferred_work = iwl4965_setup_deferred_work,
2304 .cancel_deferred_work = iwl4965_cancel_deferred_work,
57aab75a
TW		 2305 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2306 .alive_notify = iwl4965_alive_notify,
f3ccc08c 2307 .init_alive_start = iwl4965_init_alive_start,
57aab75a 2308 .load_ucode = iwl4965_load_bsm,
6f4083aa 2309 .apm_ops = {
91238714 2310 .init = iwl4965_apm_init,
7f066108 2311 .reset = iwl4965_apm_reset,
f118a91d 2312 .stop = iwl4965_apm_stop,
694cc56d 2313 .config = iwl4965_nic_config,
5b9f8cd3 2314 .set_pwr_src = iwl_set_pwr_src,
6f4083aa 2315 },
6bc913bd 2316 .eeprom_ops = {
073d3f5f
TW		 2317 .regulatory_bands = {
2318 EEPROM_REGULATORY_BAND_1_CHANNELS,
2319 EEPROM_REGULATORY_BAND_2_CHANNELS,
2320 EEPROM_REGULATORY_BAND_3_CHANNELS,
2321 EEPROM_REGULATORY_BAND_4_CHANNELS,
2322 EEPROM_REGULATORY_BAND_5_CHANNELS,
2323 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
2324 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
2325 },
6bc913bd
AK		 2326 .verify_signature = iwlcore_eeprom_verify_signature,
2327 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2328 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 2329 .calib_version = iwl4965_eeprom_calib_version,
073d3f5f 2330 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 2331 },
630fe9b6 2332 .send_tx_power = iwl4965_send_tx_power,
5b9f8cd3 2333 .update_chain_flags = iwl_update_chain_flags,
8f91aecb 2334 .temperature = iwl4965_temperature_calib,
6bc913bd
AK		 2335};
2336
2337static struct iwl_ops iwl4965_ops = {
2338 .lib = &iwl4965_lib,
3c424c28 2339 .hcmd = &iwl4965_hcmd,
857485c0 2340 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 2341};
2342
fed9017e 2343struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 2344 .name = "4965AGN",
a0987a8d
RC		 2345 .fw_name_pre = IWL4965_FW_PRE,
2346 .ucode_api_max = IWL4965_UCODE_API_MAX,
2347 .ucode_api_min = IWL4965_UCODE_API_MIN,
82b9a121 2348 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 2349 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
0ef2ca67
TW		 2350 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2351 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
6bc913bd 2352 .ops = &iwl4965_ops,
1ea87396 2353 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 2354};
2355
d16dc48a 2356/* Module firmware */
a0987a8d 2357MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
d16dc48a 2358
1ea87396
AK		 2359module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
2360MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2361module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
2362MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b 2363module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
61a2d07d 2364MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
95aa194a 2365module_param_named(debug, iwl4965_mod_params.debug, uint, 0444);
1ea87396
AK		 2366MODULE_PARM_DESC(debug, "debug output mask");
2367module_param_named(
2368 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
2369MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2370
2371module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
2372MODULE_PARM_DESC(queues_num, "number of hw queues.");
49779293
RR		 2373/* 11n */
2374module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, 0444);
2375MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
1ea87396
AK		 2376module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
2377MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
49779293 2378
3a1081e8
EK		 2379module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
2380MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
Linux kernel - Deliverables
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