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iwlwifi: 4965 define firmware file name once
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47 38#include <asm/unaligned.h>
b481de9c 39
6bc913bd 40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
fee1247a 42#include "iwl-core.h"
3395f6e9 43#include "iwl-io.h"
b481de9c 44#include "iwl-helpers.h"
f0832f13 45#include "iwl-calib.h"
5083e563 46#include "iwl-sta.h"
b481de9c 47
630fe9b6 48static int iwl4965_send_tx_power(struct iwl_priv *priv);
91dbc5bd 49static int iwl4965_hw_get_temperature(const struct iwl_priv *priv);
630fe9b6 50
d16dc48a
TW		 51/* Change firmware file name, using "-" and incrementing number,
52 * *only* when uCode interface or architecture changes so that it
53 * is not compatible with earlier drivers.
54 * This number will also appear in << 8 position of 1st dword of uCode file */
55#define IWL4965_UCODE_API "-2"
25e35a56 56#define IWL4965_MODULE_FIRMWARE "iwlwifi-4965" IWL4965_UCODE_API ".ucode"
d16dc48a
TW		 57
58
1ea87396
AK		 59/* module parameters */
60static struct iwl_mod_params iwl4965_mod_params = {
038669e4 61 .num_of_queues = IWL49_NUM_QUEUES,
9f17b318 62 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
1ea87396
AK		 63 .enable_qos = 1,
64 .amsdu_size_8K = 1,
3a1081e8 65 .restart_fw = 1,
1ea87396
AK		 66 /* the rest are 0 by default */
67};
68
57aab75a
TW		 69/* check contents of special bootstrap uCode SRAM */
70static int iwl4965_verify_bsm(struct iwl_priv *priv)
71{
72 __le32 *image = priv->ucode_boot.v_addr;
73 u32 len = priv->ucode_boot.len;
74 u32 reg;
75 u32 val;
76
77 IWL_DEBUG_INFO("Begin verify bsm\n");
78
79 /* verify BSM SRAM contents */
80 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
81 for (reg = BSM_SRAM_LOWER_BOUND;
82 reg < BSM_SRAM_LOWER_BOUND + len;
83 reg += sizeof(u32), image++) {
84 val = iwl_read_prph(priv, reg);
85 if (val != le32_to_cpu(*image)) {
86 IWL_ERROR("BSM uCode verification failed at "
87 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
88 BSM_SRAM_LOWER_BOUND,
89 reg - BSM_SRAM_LOWER_BOUND, len,
90 val, le32_to_cpu(*image));
91 return -EIO;
92 }
93 }
94
95 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
96
97 return 0;
98}
99
100/**
101 * iwl4965_load_bsm - Load bootstrap instructions
102 *
103 * BSM operation:
104 *
105 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
106 * in special SRAM that does not power down during RFKILL. When powering back
107 * up after power-saving sleeps (or during initial uCode load), the BSM loads
108 * the bootstrap program into the on-board processor, and starts it.
109 *
110 * The bootstrap program loads (via DMA) instructions and data for a new
111 * program from host DRAM locations indicated by the host driver in the
112 * BSM_DRAM_* registers. Once the new program is loaded, it starts
113 * automatically.
114 *
115 * When initializing the NIC, the host driver points the BSM to the
116 * "initialize" uCode image. This uCode sets up some internal data, then
117 * notifies host via "initialize alive" that it is complete.
118 *
119 * The host then replaces the BSM_DRAM_* pointer values to point to the
120 * normal runtime uCode instructions and a backup uCode data cache buffer
121 * (filled initially with starting data values for the on-board processor),
122 * then triggers the "initialize" uCode to load and launch the runtime uCode,
123 * which begins normal operation.
124 *
125 * When doing a power-save shutdown, runtime uCode saves data SRAM into
126 * the backup data cache in DRAM before SRAM is powered down.
127 *
128 * When powering back up, the BSM loads the bootstrap program. This reloads
129 * the runtime uCode instructions and the backup data cache into SRAM,
130 * and re-launches the runtime uCode from where it left off.
131 */
132static int iwl4965_load_bsm(struct iwl_priv *priv)
133{
134 __le32 *image = priv->ucode_boot.v_addr;
135 u32 len = priv->ucode_boot.len;
136 dma_addr_t pinst;
137 dma_addr_t pdata;
138 u32 inst_len;
139 u32 data_len;
140 int i;
141 u32 done;
142 u32 reg_offset;
143 int ret;
144
145 IWL_DEBUG_INFO("Begin load bsm\n");
146
fe9b6b72
RR		 147 priv->ucode_type = UCODE_RT;
148
57aab75a
TW		 149 /* make sure bootstrap program is no larger than BSM's SRAM size */
150 if (len > IWL_MAX_BSM_SIZE)
151 return -EINVAL;
152
153 /* Tell bootstrap uCode where to find the "Initialize" uCode
154 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
2d87889f 155 * NOTE: iwl_init_alive_start() will replace these values,
57aab75a 156 * after the "initialize" uCode has run, to point to
2d87889f
TW		 157 * runtime/protocol instructions and backup data cache.
158 */
57aab75a
TW		 159 pinst = priv->ucode_init.p_addr >> 4;
160 pdata = priv->ucode_init_data.p_addr >> 4;
161 inst_len = priv->ucode_init.len;
162 data_len = priv->ucode_init_data.len;
163
164 ret = iwl_grab_nic_access(priv);
165 if (ret)
166 return ret;
167
168 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
169 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
170 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
171 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
172
173 /* Fill BSM memory with bootstrap instructions */
174 for (reg_offset = BSM_SRAM_LOWER_BOUND;
175 reg_offset < BSM_SRAM_LOWER_BOUND + len;
176 reg_offset += sizeof(u32), image++)
177 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
178
179 ret = iwl4965_verify_bsm(priv);
180 if (ret) {
181 iwl_release_nic_access(priv);
182 return ret;
183 }
184
185 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
186 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
187 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
188 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
189
190 /* Load bootstrap code into instruction SRAM now,
191 * to prepare to load "initialize" uCode */
192 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
193
194 /* Wait for load of bootstrap uCode to finish */
195 for (i = 0; i < 100; i++) {
196 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
197 if (!(done & BSM_WR_CTRL_REG_BIT_START))
198 break;
199 udelay(10);
200 }
201 if (i < 100)
202 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
203 else {
204 IWL_ERROR("BSM write did not complete!\n");
205 return -EIO;
206 }
207
208 /* Enable future boot loads whenever power management unit triggers it
209 * (e.g. when powering back up after power-save shutdown) */
210 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
211
212 iwl_release_nic_access(priv);
213
214 return 0;
215}
216
f3ccc08c
EG		 217/**
218 * iwl4965_set_ucode_ptrs - Set uCode address location
219 *
220 * Tell initialization uCode where to find runtime uCode.
221 *
222 * BSM registers initially contain pointers to initialization uCode.
223 * We need to replace them to load runtime uCode inst and data,
224 * and to save runtime data when powering down.
225 */
226static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
227{
228 dma_addr_t pinst;
229 dma_addr_t pdata;
230 unsigned long flags;
231 int ret = 0;
232
233 /* bits 35:4 for 4965 */
234 pinst = priv->ucode_code.p_addr >> 4;
235 pdata = priv->ucode_data_backup.p_addr >> 4;
236
237 spin_lock_irqsave(&priv->lock, flags);
238 ret = iwl_grab_nic_access(priv);
239 if (ret) {
240 spin_unlock_irqrestore(&priv->lock, flags);
241 return ret;
242 }
243
244 /* Tell bootstrap uCode where to find image to load */
245 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
246 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
247 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
248 priv->ucode_data.len);
249
a96a27f9 250 /* Inst byte count must be last to set up, bit 31 signals uCode
f3ccc08c
EG		 251 * that all new ptr/size info is in place */
252 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
253 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
254 iwl_release_nic_access(priv);
255
256 spin_unlock_irqrestore(&priv->lock, flags);
257
258 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
259
260 return ret;
261}
262
263/**
264 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
265 *
266 * Called after REPLY_ALIVE notification received from "initialize" uCode.
267 *
268 * The 4965 "initialize" ALIVE reply contains calibration data for:
269 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
270 * (3945 does not contain this data).
271 *
272 * Tell "initialize" uCode to go ahead and load the runtime uCode.
273*/
274static void iwl4965_init_alive_start(struct iwl_priv *priv)
275{
276 /* Check alive response for "valid" sign from uCode */
277 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
278 /* We had an error bringing up the hardware, so take it
279 * all the way back down so we can try again */
280 IWL_DEBUG_INFO("Initialize Alive failed.\n");
281 goto restart;
282 }
283
284 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
285 * This is a paranoid check, because we would not have gotten the
286 * "initialize" alive if code weren't properly loaded. */
287 if (iwl_verify_ucode(priv)) {
288 /* Runtime instruction load was bad;
289 * take it all the way back down so we can try again */
290 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
291 goto restart;
292 }
293
294 /* Calculate temperature */
91dbc5bd 295 priv->temperature = iwl4965_hw_get_temperature(priv);
f3ccc08c
EG		 296
297 /* Send pointers to protocol/runtime uCode image ... init code will
298 * load and launch runtime uCode, which will send us another "Alive"
299 * notification. */
300 IWL_DEBUG_INFO("Initialization Alive received.\n");
301 if (iwl4965_set_ucode_ptrs(priv)) {
302 /* Runtime instruction load won't happen;
303 * take it all the way back down so we can try again */
304 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
305 goto restart;
306 }
307 return;
308
309restart:
310 queue_work(priv->workqueue, &priv->restart);
311}
312
b481de9c
ZY		 313static int is_fat_channel(__le32 rxon_flags)
314{
315 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
316 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
317}
318
8614f360
TW		 319/*
320 * EEPROM handlers
321 */
0ef2ca67 322static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
8614f360 323{
0ef2ca67 324 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
8614f360 325}
b481de9c 326
da1bc453 327/*
a96a27f9 328 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 329 * must be called under priv->lock and mac access
330 */
331static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
b481de9c 332{
da1bc453 333 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
b481de9c
ZY		 334}
335
91238714 336static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 337{
91238714 338 int ret = 0;
b481de9c 339
3395f6e9 340 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 341 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 342
8f061891
TW		 343 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
344 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
345 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
346
91238714
TW		 347 /* set "initialization complete" bit to move adapter
348 * D0U* --> D0A* state */
3395f6e9 349 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 350
91238714
TW		 351 /* wait for clock stabilization */
352 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
353 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
354 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
355 if (ret < 0) {
356 IWL_DEBUG_INFO("Failed to init the card\n");
357 goto out;
b481de9c
ZY		 358 }
359
91238714
TW		 360 ret = iwl_grab_nic_access(priv);
361 if (ret)
362 goto out;
b481de9c 363
91238714 364 /* enable DMA */
8f061891
TW		 365 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
366 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 367
368 udelay(20);
369
8f061891 370 /* disable L1-Active */
3395f6e9 371 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 372 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 373
3395f6e9 374 iwl_release_nic_access(priv);
91238714 375out:
91238714
TW		 376 return ret;
377}
378
694cc56d
TW		 379
380static void iwl4965_nic_config(struct iwl_priv *priv)
91238714
TW		 381{
382 unsigned long flags;
91238714 383 u32 val;
694cc56d 384 u16 radio_cfg;
e7b63581 385 u16 link;
6f4083aa 386
b481de9c
ZY		 387 spin_lock_irqsave(&priv->lock, flags);
388
b661c819 389 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
b481de9c
ZY		 390 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
391 /* Enable No Snoop field */
392 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
393 val & ~(1 << 11));
394 }
395
e7b63581 396 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
b481de9c 397
8f061891 398 /* L1 is enabled by BIOS */
e7b63581 399 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
a96a27f9 400 /* disable L0S disabled L1A enabled */
8f061891
TW		 401 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
402 else
403 /* L0S enabled L1A disabled */
404 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
b481de9c 405
694cc56d 406 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
b481de9c 407
694cc56d
TW		 408 /* write radio config values to register */
409 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
410 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
411 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
412 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
413 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
b481de9c 414
694cc56d 415 /* set CSR_HW_CONFIG_REG for uCode use */
3395f6e9 416 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
a395b920
TW		 417 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
418 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 419
694cc56d
TW		 420 priv->calib_info = (struct iwl_eeprom_calib_info *)
421 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
422
423 spin_unlock_irqrestore(&priv->lock, flags);
424}
425
46315e01
TW		 426static int iwl4965_apm_stop_master(struct iwl_priv *priv)
427{
428 int ret = 0;
429 unsigned long flags;
430
431 spin_lock_irqsave(&priv->lock, flags);
432
433 /* set stop master bit */
434 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
435
436 ret = iwl_poll_bit(priv, CSR_RESET,
437 CSR_RESET_REG_FLAG_MASTER_DISABLED,
438 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
439 if (ret < 0)
440 goto out;
441
442out:
443 spin_unlock_irqrestore(&priv->lock, flags);
444 IWL_DEBUG_INFO("stop master\n");
445
446 return ret;
447}
448
f118a91d
TW		 449static void iwl4965_apm_stop(struct iwl_priv *priv)
450{
451 unsigned long flags;
452
46315e01 453 iwl4965_apm_stop_master(priv);
f118a91d
TW		 454
455 spin_lock_irqsave(&priv->lock, flags);
456
457 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
458
459 udelay(10);
1d3e6c61
MA		 460 /* clear "init complete" move adapter D0A* --> D0U state */
461 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d
TW		 462 spin_unlock_irqrestore(&priv->lock, flags);
463}
464
7f066108 465static int iwl4965_apm_reset(struct iwl_priv *priv)
b481de9c 466{
7f066108 467 int ret = 0;
b481de9c
ZY		 468 unsigned long flags;
469
46315e01 470 iwl4965_apm_stop_master(priv);
b481de9c
ZY		 471
472 spin_lock_irqsave(&priv->lock, flags);
473
3395f6e9 474 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 475
476 udelay(10);
477
7f066108
TW		 478 /* FIXME: put here L1A -L0S w/a */
479
3395f6e9 480 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d 481
7f066108 482 ret = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 483 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
484 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
485
7f066108
TW		 486 if (ret)
487 goto out;
488
b481de9c
ZY		 489 udelay(10);
490
7f066108
TW		 491 ret = iwl_grab_nic_access(priv);
492 if (ret)
493 goto out;
494 /* Enable DMA and BSM Clock */
495 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
496 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 497
7f066108 498 udelay(10);
b481de9c 499
7f066108
TW		 500 /* disable L1A */
501 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
502 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 503
7f066108 504 iwl_release_nic_access(priv);
b481de9c
ZY		 505
506 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
507 wake_up_interruptible(&priv->wait_command_queue);
508
7f066108 509out:
b481de9c
ZY		 510 spin_unlock_irqrestore(&priv->lock, flags);
511
7f066108 512 return ret;
b481de9c
ZY		 513}
514
b481de9c
ZY		 515/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
516 * Called after every association, but this runs only once!
517 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 518static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 519{
f0832f13 520 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 521
3109ece1 522 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 523 struct iwl_calib_diff_gain_cmd cmd;
b481de9c
ZY		 524
525 memset(&cmd, 0, sizeof(cmd));
f69f42a6 526 cmd.opCode = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
b481de9c
ZY		 527 cmd.diff_gain_a = 0;
528 cmd.diff_gain_b = 0;
529 cmd.diff_gain_c = 0;
f0832f13
EG		 530 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
531 sizeof(cmd), &cmd))
532 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 533 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
534 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
535 }
b481de9c
ZY		 536}
537
f0832f13
EG		 538static void iwl4965_gain_computation(struct iwl_priv *priv,
539 u32 *average_noise,
540 u16 min_average_noise_antenna_i,
541 u32 min_average_noise)
b481de9c 542{
f0832f13
EG		 543 int i, ret;
544 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 545
f0832f13 546 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 547
f0832f13
EG		 548 for (i = 0; i < NUM_RX_CHAINS; i++) {
549 s32 delta_g = 0;
b481de9c 550
f0832f13
EG		 551 if (!(data->disconn_array[i]) &&
552 (data->delta_gain_code[i] ==
b481de9c 553 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 554 delta_g = average_noise[i] - min_average_noise;
555 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
556 data->delta_gain_code[i] =
557 min(data->delta_gain_code[i],
558 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
559
560 data->delta_gain_code[i] =
561 (data->delta_gain_code[i] | (1 << 2));
562 } else {
563 data->delta_gain_code[i] = 0;
b481de9c 564 }
b481de9c 565 }
f0832f13
EG		 566 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
567 data->delta_gain_code[0],
568 data->delta_gain_code[1],
569 data->delta_gain_code[2]);
b481de9c 570
f0832f13
EG		 571 /* Differential gain gets sent to uCode only once */
572 if (!data->radio_write) {
f69f42a6 573 struct iwl_calib_diff_gain_cmd cmd;
f0832f13 574 data->radio_write = 1;
b481de9c 575
f0832f13 576 memset(&cmd, 0, sizeof(cmd));
f69f42a6 577 cmd.opCode = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
f0832f13
EG		 578 cmd.diff_gain_a = data->delta_gain_code[0];
579 cmd.diff_gain_b = data->delta_gain_code[1];
580 cmd.diff_gain_c = data->delta_gain_code[2];
581 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
582 sizeof(cmd), &cmd);
583 if (ret)
584 IWL_DEBUG_CALIB("fail sending cmd "
585 "REPLY_PHY_CALIBRATION_CMD \n");
586
587 /* TODO we might want recalculate
588 * rx_chain in rxon cmd */
589
590 /* Mark so we run this algo only once! */
591 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 592 }
f0832f13
EG		 593 data->chain_noise_a = 0;
594 data->chain_noise_b = 0;
595 data->chain_noise_c = 0;
596 data->chain_signal_a = 0;
597 data->chain_signal_b = 0;
598 data->chain_signal_c = 0;
599 data->beacon_count = 0;
b481de9c
ZY		 600}
601
a326a5d0
EG		 602static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
603 __le32 *tx_flags)
604{
e6a9854b 605 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
a326a5d0
EG		 606 *tx_flags |= TX_CMD_FLG_RTS_MSK;
607 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
e6a9854b 608 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
a326a5d0
EG		 609 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
610 *tx_flags |= TX_CMD_FLG_CTS_MSK;
611 }
612}
613
b481de9c
ZY		 614static void iwl4965_bg_txpower_work(struct work_struct *work)
615{
c79dd5b5 616 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 617 txpower_work);
618
619 /* If a scan happened to start before we got here
620 * then just return; the statistics notification will
621 * kick off another scheduled work to compensate for
622 * any temperature delta we missed here. */
623 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
624 test_bit(STATUS_SCANNING, &priv->status))
625 return;
626
627 mutex_lock(&priv->mutex);
628
a96a27f9 629 /* Regardless of if we are associated, we must reconfigure the
b481de9c
ZY		 630 * TX power since frames can be sent on non-radar channels while
631 * not associated */
630fe9b6 632 iwl4965_send_tx_power(priv);
b481de9c
ZY		 633
634 /* Update last_temperature to keep is_calib_needed from running
635 * when it isn't needed... */
636 priv->last_temperature = priv->temperature;
637
638 mutex_unlock(&priv->mutex);
639}
640
641/*
642 * Acquire priv->lock before calling this function !
643 */
c79dd5b5 644static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 645{
3395f6e9 646 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 647 (index & 0xff) | (txq_id << 8));
12a81f60 648 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 649}
650
8b6eaea8
CB		 651/**
652 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
653 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
654 * @scd_retry: (1) Indicates queue will be used in aggregation mode
655 *
656 * NOTE: Acquire priv->lock before calling this function !
b481de9c 657 */
c79dd5b5 658static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
16466903 659 struct iwl_tx_queue *txq,
b481de9c
ZY		 660 int tx_fifo_id, int scd_retry)
661{
662 int txq_id = txq->q.id;
8b6eaea8
CB		 663
664 /* Find out whether to activate Tx queue */
c3056065 665 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
b481de9c 666
8b6eaea8 667 /* Set up and activate */
12a81f60 668 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 669 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
670 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
671 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
672 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
673 IWL49_SCD_QUEUE_STTS_REG_MSK);
b481de9c
ZY		 674
675 txq->sched_retry = scd_retry;
676
677 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 678 active ? "Activate" : "Deactivate",
b481de9c
ZY		 679 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
680}
681
682static const u16 default_queue_to_tx_fifo[] = {
683 IWL_TX_FIFO_AC3,
684 IWL_TX_FIFO_AC2,
685 IWL_TX_FIFO_AC1,
686 IWL_TX_FIFO_AC0,
038669e4 687 IWL49_CMD_FIFO_NUM,
b481de9c
ZY		 688 IWL_TX_FIFO_HCCA_1,
689 IWL_TX_FIFO_HCCA_2
690};
691
be1f3ab6 692static int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 693{
694 u32 a;
695 int i = 0;
696 unsigned long flags;
857485c0 697 int ret;
b481de9c
ZY		 698
699 spin_lock_irqsave(&priv->lock, flags);
700
3395f6e9 701 ret = iwl_grab_nic_access(priv);
857485c0 702 if (ret) {
b481de9c 703 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 704 return ret;
b481de9c
ZY		 705 }
706
8b6eaea8 707 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 708 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
038669e4
EG		 709 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
710 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 711 iwl_write_targ_mem(priv, a, 0);
038669e4 712 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 713 iwl_write_targ_mem(priv, a, 0);
5425e490 714 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 715 iwl_write_targ_mem(priv, a, 0);
b481de9c 716
8b6eaea8 717 /* Tel 4965 where to find Tx byte count tables */
12a81f60 718 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
4ddbb7d0 719 priv->scd_bc_tbls.dma >> 10);
8b6eaea8
CB		 720
721 /* Disable chain mode for all queues */
12a81f60 722 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 723
8b6eaea8 724 /* Initialize each Tx queue (including the command queue) */
5425e490 725 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 726
727 /* TFD circular buffer read/write indexes */
12a81f60 728 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 729 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 730
731 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 732 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 733 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
734 (SCD_WIN_SIZE <<
735 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
736 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 737
738 /* Frame limit */
3395f6e9 739 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 740 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
741 sizeof(u32),
742 (SCD_FRAME_LIMIT <<
743 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
744 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c
ZY		 745
746 }
12a81f60 747 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 748 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 749
8b6eaea8 750 /* Activate all Tx DMA/FIFO channels */
da1bc453 751 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
b481de9c
ZY		 752
753 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 754
755 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 756 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
757 int ac = default_queue_to_tx_fifo[i];
36470749 758 iwl_txq_ctx_activate(priv, i);
b481de9c
ZY		 759 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
760 }
761
3395f6e9 762 iwl_release_nic_access(priv);
b481de9c
ZY		 763 spin_unlock_irqrestore(&priv->lock, flags);
764
857485c0 765 return ret;
b481de9c
ZY		 766}
767
f0832f13
EG		 768static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
769 .min_nrg_cck = 97,
770 .max_nrg_cck = 0,
771
772 .auto_corr_min_ofdm = 85,
773 .auto_corr_min_ofdm_mrc = 170,
774 .auto_corr_min_ofdm_x1 = 105,
775 .auto_corr_min_ofdm_mrc_x1 = 220,
776
777 .auto_corr_max_ofdm = 120,
778 .auto_corr_max_ofdm_mrc = 210,
779 .auto_corr_max_ofdm_x1 = 140,
780 .auto_corr_max_ofdm_mrc_x1 = 270,
781
782 .auto_corr_min_cck = 125,
783 .auto_corr_max_cck = 200,
784 .auto_corr_min_cck_mrc = 200,
785 .auto_corr_max_cck_mrc = 400,
786
787 .nrg_th_cck = 100,
788 .nrg_th_ofdm = 100,
789};
f0832f13 790
8b6eaea8 791/**
5425e490 792 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 793 *
794 * Called when initializing driver
795 */
be1f3ab6 796static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 797{
316c30d9 798
038669e4 799 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1ea87396 800 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 801 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
038669e4 802 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
059ff826 803 return -EINVAL;
316c30d9 804 }
b481de9c 805
5425e490 806 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
4ddbb7d0
TW		 807 priv->hw_params.scd_bc_tbls_size =
808 IWL49_NUM_QUEUES * sizeof(struct iwl4965_scd_bc_tbl);
5425e490
TW		 809 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
810 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
099b40b7
RR		 811 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
812 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
813 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
814 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
815
ec35cf2a
TW		 816 priv->hw_params.tx_chains_num = 2;
817 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 818 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
819 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 820 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
821
f0832f13 822 priv->hw_params.sens = &iwl4965_sensitivity;
3e82a822 823
059ff826 824 return 0;
b481de9c
ZY		 825}
826
b481de9c
ZY		 827static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
828{
829 s32 sign = 1;
830
831 if (num < 0) {
832 sign = -sign;
833 num = -num;
834 }
835 if (denom < 0) {
836 sign = -sign;
837 denom = -denom;
838 }
839 *res = 1;
840 *res = ((num * 2 + denom) / (denom * 2)) * sign;
841
842 return 1;
843}
844
8b6eaea8
CB		 845/**
846 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
847 *
848 * Determines power supply voltage compensation for txpower calculations.
849 * Returns number of 1/2-dB steps to subtract from gain table index,
850 * to compensate for difference between power supply voltage during
851 * factory measurements, vs. current power supply voltage.
852 *
853 * Voltage indication is higher for lower voltage.
854 * Lower voltage requires more gain (lower gain table index).
855 */
b481de9c
ZY		 856static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
857 s32 current_voltage)
858{
859 s32 comp = 0;
860
861 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
862 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
863 return 0;
864
865 iwl4965_math_div_round(current_voltage - eeprom_voltage,
866 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
867
868 if (current_voltage > eeprom_voltage)
869 comp *= 2;
870 if ((comp < -2) || (comp > 2))
871 comp = 0;
872
873 return comp;
874}
875
b481de9c
ZY		 876static s32 iwl4965_get_tx_atten_grp(u16 channel)
877{
878 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
879 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
880 return CALIB_CH_GROUP_5;
881
882 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
883 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
884 return CALIB_CH_GROUP_1;
885
886 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
887 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
888 return CALIB_CH_GROUP_2;
889
890 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
891 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
892 return CALIB_CH_GROUP_3;
893
894 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
895 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
896 return CALIB_CH_GROUP_4;
897
898 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
899 return -1;
900}
901
c79dd5b5 902static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 903{
904 s32 b = -1;
905
906 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 907 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 908 continue;
909
073d3f5f
TW		 910 if ((channel >= priv->calib_info->band_info[b].ch_from)
911 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 912 break;
913 }
914
915 return b;
916}
917
918static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
919{
920 s32 val;
921
922 if (x2 == x1)
923 return y1;
924 else {
925 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
926 return val + y2;
927 }
928}
929
8b6eaea8
CB		 930/**
931 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
932 *
933 * Interpolates factory measurements from the two sample channels within a
934 * sub-band, to apply to channel of interest. Interpolation is proportional to
935 * differences in channel frequencies, which is proportional to differences
936 * in channel number.
937 */
c79dd5b5 938static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 939 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 940{
941 s32 s = -1;
942 u32 c;
943 u32 m;
073d3f5f
TW		 944 const struct iwl_eeprom_calib_measure *m1;
945 const struct iwl_eeprom_calib_measure *m2;
946 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 947 u32 ch_i1;
948 u32 ch_i2;
949
950 s = iwl4965_get_sub_band(priv, channel);
951 if (s >= EEPROM_TX_POWER_BANDS) {
6f147926 952 IWL_ERROR("Tx Power can not find channel %d\n", channel);
b481de9c
ZY		 953 return -1;
954 }
955
073d3f5f
TW		 956 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
957 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 958 chan_info->ch_num = (u8) channel;
959
960 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
961 channel, s, ch_i1, ch_i2);
962
963 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
964 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 965 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 966 measurements[c][m]);
073d3f5f 967 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 968 measurements[c][m]);
969 omeas = &(chan_info->measurements[c][m]);
970
971 omeas->actual_pow =
972 (u8) iwl4965_interpolate_value(channel, ch_i1,
973 m1->actual_pow,
974 ch_i2,
975 m2->actual_pow);
976 omeas->gain_idx =
977 (u8) iwl4965_interpolate_value(channel, ch_i1,
978 m1->gain_idx, ch_i2,
979 m2->gain_idx);
980 omeas->temperature =
981 (u8) iwl4965_interpolate_value(channel, ch_i1,
982 m1->temperature,
983 ch_i2,
984 m2->temperature);
985 omeas->pa_det =
986 (s8) iwl4965_interpolate_value(channel, ch_i1,
987 m1->pa_det, ch_i2,
988 m2->pa_det);
989
990 IWL_DEBUG_TXPOWER
991 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
992 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
993 IWL_DEBUG_TXPOWER
994 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
995 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
996 IWL_DEBUG_TXPOWER
997 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
998 m1->pa_det, m2->pa_det, omeas->pa_det);
999 IWL_DEBUG_TXPOWER
1000 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1001 m1->temperature, m2->temperature,
1002 omeas->temperature);
1003 }
1004 }
1005
1006 return 0;
1007}
1008
1009/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1010 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1011static s32 back_off_table[] = {
1012 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1013 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1014 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1015 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1016 10 /* CCK */
1017};
1018
1019/* Thermal compensation values for txpower for various frequency ranges ...
1020 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1021static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1022 s32 degrees_per_05db_a;
1023 s32 degrees_per_05db_a_denom;
1024} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1025 {9, 2}, /* group 0 5.2, ch 34-43 */
1026 {4, 1}, /* group 1 5.2, ch 44-70 */
1027 {4, 1}, /* group 2 5.2, ch 71-124 */
1028 {4, 1}, /* group 3 5.2, ch 125-200 */
1029 {3, 1} /* group 4 2.4, ch all */
1030};
1031
1032static s32 get_min_power_index(s32 rate_power_index, u32 band)
1033{
1034 if (!band) {
1035 if ((rate_power_index & 7) <= 4)
1036 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1037 }
1038 return MIN_TX_GAIN_INDEX;
1039}
1040
1041struct gain_entry {
1042 u8 dsp;
1043 u8 radio;
1044};
1045
1046static const struct gain_entry gain_table[2][108] = {
1047 /* 5.2GHz power gain index table */
1048 {
1049 {123, 0x3F}, /* highest txpower */
1050 {117, 0x3F},
1051 {110, 0x3F},
1052 {104, 0x3F},
1053 {98, 0x3F},
1054 {110, 0x3E},
1055 {104, 0x3E},
1056 {98, 0x3E},
1057 {110, 0x3D},
1058 {104, 0x3D},
1059 {98, 0x3D},
1060 {110, 0x3C},
1061 {104, 0x3C},
1062 {98, 0x3C},
1063 {110, 0x3B},
1064 {104, 0x3B},
1065 {98, 0x3B},
1066 {110, 0x3A},
1067 {104, 0x3A},
1068 {98, 0x3A},
1069 {110, 0x39},
1070 {104, 0x39},
1071 {98, 0x39},
1072 {110, 0x38},
1073 {104, 0x38},
1074 {98, 0x38},
1075 {110, 0x37},
1076 {104, 0x37},
1077 {98, 0x37},
1078 {110, 0x36},
1079 {104, 0x36},
1080 {98, 0x36},
1081 {110, 0x35},
1082 {104, 0x35},
1083 {98, 0x35},
1084 {110, 0x34},
1085 {104, 0x34},
1086 {98, 0x34},
1087 {110, 0x33},
1088 {104, 0x33},
1089 {98, 0x33},
1090 {110, 0x32},
1091 {104, 0x32},
1092 {98, 0x32},
1093 {110, 0x31},
1094 {104, 0x31},
1095 {98, 0x31},
1096 {110, 0x30},
1097 {104, 0x30},
1098 {98, 0x30},
1099 {110, 0x25},
1100 {104, 0x25},
1101 {98, 0x25},
1102 {110, 0x24},
1103 {104, 0x24},
1104 {98, 0x24},
1105 {110, 0x23},
1106 {104, 0x23},
1107 {98, 0x23},
1108 {110, 0x22},
1109 {104, 0x18},
1110 {98, 0x18},
1111 {110, 0x17},
1112 {104, 0x17},
1113 {98, 0x17},
1114 {110, 0x16},
1115 {104, 0x16},
1116 {98, 0x16},
1117 {110, 0x15},
1118 {104, 0x15},
1119 {98, 0x15},
1120 {110, 0x14},
1121 {104, 0x14},
1122 {98, 0x14},
1123 {110, 0x13},
1124 {104, 0x13},
1125 {98, 0x13},
1126 {110, 0x12},
1127 {104, 0x08},
1128 {98, 0x08},
1129 {110, 0x07},
1130 {104, 0x07},
1131 {98, 0x07},
1132 {110, 0x06},
1133 {104, 0x06},
1134 {98, 0x06},
1135 {110, 0x05},
1136 {104, 0x05},
1137 {98, 0x05},
1138 {110, 0x04},
1139 {104, 0x04},
1140 {98, 0x04},
1141 {110, 0x03},
1142 {104, 0x03},
1143 {98, 0x03},
1144 {110, 0x02},
1145 {104, 0x02},
1146 {98, 0x02},
1147 {110, 0x01},
1148 {104, 0x01},
1149 {98, 0x01},
1150 {110, 0x00},
1151 {104, 0x00},
1152 {98, 0x00},
1153 {93, 0x00},
1154 {88, 0x00},
1155 {83, 0x00},
1156 {78, 0x00},
1157 },
1158 /* 2.4GHz power gain index table */
1159 {
1160 {110, 0x3f}, /* highest txpower */
1161 {104, 0x3f},
1162 {98, 0x3f},
1163 {110, 0x3e},
1164 {104, 0x3e},
1165 {98, 0x3e},
1166 {110, 0x3d},
1167 {104, 0x3d},
1168 {98, 0x3d},
1169 {110, 0x3c},
1170 {104, 0x3c},
1171 {98, 0x3c},
1172 {110, 0x3b},
1173 {104, 0x3b},
1174 {98, 0x3b},
1175 {110, 0x3a},
1176 {104, 0x3a},
1177 {98, 0x3a},
1178 {110, 0x39},
1179 {104, 0x39},
1180 {98, 0x39},
1181 {110, 0x38},
1182 {104, 0x38},
1183 {98, 0x38},
1184 {110, 0x37},
1185 {104, 0x37},
1186 {98, 0x37},
1187 {110, 0x36},
1188 {104, 0x36},
1189 {98, 0x36},
1190 {110, 0x35},
1191 {104, 0x35},
1192 {98, 0x35},
1193 {110, 0x34},
1194 {104, 0x34},
1195 {98, 0x34},
1196 {110, 0x33},
1197 {104, 0x33},
1198 {98, 0x33},
1199 {110, 0x32},
1200 {104, 0x32},
1201 {98, 0x32},
1202 {110, 0x31},
1203 {104, 0x31},
1204 {98, 0x31},
1205 {110, 0x30},
1206 {104, 0x30},
1207 {98, 0x30},
1208 {110, 0x6},
1209 {104, 0x6},
1210 {98, 0x6},
1211 {110, 0x5},
1212 {104, 0x5},
1213 {98, 0x5},
1214 {110, 0x4},
1215 {104, 0x4},
1216 {98, 0x4},
1217 {110, 0x3},
1218 {104, 0x3},
1219 {98, 0x3},
1220 {110, 0x2},
1221 {104, 0x2},
1222 {98, 0x2},
1223 {110, 0x1},
1224 {104, 0x1},
1225 {98, 0x1},
1226 {110, 0x0},
1227 {104, 0x0},
1228 {98, 0x0},
1229 {97, 0},
1230 {96, 0},
1231 {95, 0},
1232 {94, 0},
1233 {93, 0},
1234 {92, 0},
1235 {91, 0},
1236 {90, 0},
1237 {89, 0},
1238 {88, 0},
1239 {87, 0},
1240 {86, 0},
1241 {85, 0},
1242 {84, 0},
1243 {83, 0},
1244 {82, 0},
1245 {81, 0},
1246 {80, 0},
1247 {79, 0},
1248 {78, 0},
1249 {77, 0},
1250 {76, 0},
1251 {75, 0},
1252 {74, 0},
1253 {73, 0},
1254 {72, 0},
1255 {71, 0},
1256 {70, 0},
1257 {69, 0},
1258 {68, 0},
1259 {67, 0},
1260 {66, 0},
1261 {65, 0},
1262 {64, 0},
1263 {63, 0},
1264 {62, 0},
1265 {61, 0},
1266 {60, 0},
1267 {59, 0},
1268 }
1269};
1270
c79dd5b5 1271static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1272 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1273 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1274{
1275 u8 saturation_power;
1276 s32 target_power;
1277 s32 user_target_power;
1278 s32 power_limit;
1279 s32 current_temp;
1280 s32 reg_limit;
1281 s32 current_regulatory;
1282 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1283 int i;
1284 int c;
bf85ea4f 1285 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1286 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1287 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1288 s16 voltage;
1289 s32 init_voltage;
1290 s32 voltage_compensation;
1291 s32 degrees_per_05db_num;
1292 s32 degrees_per_05db_denom;
1293 s32 factory_temp;
1294 s32 temperature_comp[2];
1295 s32 factory_gain_index[2];
1296 s32 factory_actual_pwr[2];
1297 s32 power_index;
1298
b481de9c
ZY		 1299 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1300 * are used for indexing into txpower table) */
630fe9b6 1301 user_target_power = 2 * priv->tx_power_user_lmt;
b481de9c
ZY		 1302
1303 /* Get current (RXON) channel, band, width */
b481de9c
ZY		 1304 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1305 is_fat);
1306
630fe9b6
TW		 1307 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1308
1309 if (!is_channel_valid(ch_info))
b481de9c
ZY		 1310 return -EINVAL;
1311
1312 /* get txatten group, used to select 1) thermal txpower adjustment
1313 * and 2) mimo txpower balance between Tx chains. */
1314 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1315 if (txatten_grp < 0)
1316 return -EINVAL;
1317
1318 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1319 channel, txatten_grp);
1320
1321 if (is_fat) {
1322 if (ctrl_chan_high)
1323 channel -= 2;
1324 else
1325 channel += 2;
1326 }
1327
1328 /* hardware txpower limits ...
1329 * saturation (clipping distortion) txpowers are in half-dBm */
1330 if (band)
073d3f5f 1331 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1332 else
073d3f5f 1333 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1334
1335 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1336 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1337 if (band)
1338 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1339 else
1340 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1341 }
1342
1343 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1344 * max_power_avg values are in dBm, convert * 2 */
1345 if (is_fat)
1346 reg_limit = ch_info->fat_max_power_avg * 2;
1347 else
1348 reg_limit = ch_info->max_power_avg * 2;
1349
1350 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1351 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1352 if (band)
1353 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1354 else
1355 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1356 }
1357
1358 /* Interpolate txpower calibration values for this channel,
1359 * based on factory calibration tests on spaced channels. */
1360 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1361
1362 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 1363 voltage = priv->calib_info->voltage;
b481de9c
ZY		 1364 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1365 voltage_compensation =
1366 iwl4965_get_voltage_compensation(voltage, init_voltage);
1367
1368 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1369 init_voltage,
1370 voltage, voltage_compensation);
1371
1372 /* get current temperature (Celsius) */
1373 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1374 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1375 current_temp = KELVIN_TO_CELSIUS(current_temp);
1376
1377 /* select thermal txpower adjustment params, based on channel group
1378 * (same frequency group used for mimo txatten adjustment) */
1379 degrees_per_05db_num =
1380 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1381 degrees_per_05db_denom =
1382 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1383
1384 /* get per-chain txpower values from factory measurements */
1385 for (c = 0; c < 2; c++) {
1386 measurement = &ch_eeprom_info.measurements[c][1];
1387
1388 /* txgain adjustment (in half-dB steps) based on difference
1389 * between factory and current temperature */
1390 factory_temp = measurement->temperature;
1391 iwl4965_math_div_round((current_temp - factory_temp) *
1392 degrees_per_05db_denom,
1393 degrees_per_05db_num,
1394 &temperature_comp[c]);
1395
1396 factory_gain_index[c] = measurement->gain_idx;
1397 factory_actual_pwr[c] = measurement->actual_pow;
1398
1399 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1400 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1401 "curr tmp %d, comp %d steps\n",
1402 factory_temp, current_temp,
1403 temperature_comp[c]);
1404
1405 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1406 factory_gain_index[c],
1407 factory_actual_pwr[c]);
1408 }
1409
1410 /* for each of 33 bit-rates (including 1 for CCK) */
1411 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1412 u8 is_mimo_rate;
bb8c093b 1413 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 1414
1415 /* for mimo, reduce each chain's txpower by half
1416 * (3dB, 6 steps), so total output power is regulatory
1417 * compliant. */
1418 if (i & 0x8) {
1419 current_regulatory = reg_limit -
1420 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1421 is_mimo_rate = 1;
1422 } else {
1423 current_regulatory = reg_limit;
1424 is_mimo_rate = 0;
1425 }
1426
1427 /* find txpower limit, either hardware or regulatory */
1428 power_limit = saturation_power - back_off_table[i];
1429 if (power_limit > current_regulatory)
1430 power_limit = current_regulatory;
1431
1432 /* reduce user's txpower request if necessary
1433 * for this rate on this channel */
1434 target_power = user_target_power;
1435 if (target_power > power_limit)
1436 target_power = power_limit;
1437
1438 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1439 i, saturation_power - back_off_table[i],
1440 current_regulatory, user_target_power,
1441 target_power);
1442
1443 /* for each of 2 Tx chains (radio transmitters) */
1444 for (c = 0; c < 2; c++) {
1445 s32 atten_value;
1446
1447 if (is_mimo_rate)
1448 atten_value =
1449 (s32)le32_to_cpu(priv->card_alive_init.
1450 tx_atten[txatten_grp][c]);
1451 else
1452 atten_value = 0;
1453
1454 /* calculate index; higher index means lower txpower */
1455 power_index = (u8) (factory_gain_index[c] -
1456 (target_power -
1457 factory_actual_pwr[c]) -
1458 temperature_comp[c] -
1459 voltage_compensation +
1460 atten_value);
1461
1462/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1463 power_index); */
1464
1465 if (power_index < get_min_power_index(i, band))
1466 power_index = get_min_power_index(i, band);
1467
1468 /* adjust 5 GHz index to support negative indexes */
1469 if (!band)
1470 power_index += 9;
1471
1472 /* CCK, rate 32, reduce txpower for CCK */
1473 if (i == POWER_TABLE_CCK_ENTRY)
1474 power_index +=
1475 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1476
1477 /* stay within the table! */
1478 if (power_index > 107) {
1479 IWL_WARNING("txpower index %d > 107\n",
1480 power_index);
1481 power_index = 107;
1482 }
1483 if (power_index < 0) {
1484 IWL_WARNING("txpower index %d < 0\n",
1485 power_index);
1486 power_index = 0;
1487 }
1488
1489 /* fill txpower command for this rate/chain */
1490 tx_power.s.radio_tx_gain[c] =
1491 gain_table[band][power_index].radio;
1492 tx_power.s.dsp_predis_atten[c] =
1493 gain_table[band][power_index].dsp;
1494
1495 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1496 "gain 0x%02x dsp %d\n",
1497 c, atten_value, power_index,
1498 tx_power.s.radio_tx_gain[c],
1499 tx_power.s.dsp_predis_atten[c]);
3ac7f146 1500 } /* for each chain */
b481de9c
ZY		 1501
1502 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1503
3ac7f146 1504 } /* for each rate */
b481de9c
ZY		 1505
1506 return 0;
1507}
1508
1509/**
630fe9b6 1510 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
b481de9c
ZY		 1511 *
1512 * Uses the active RXON for channel, band, and characteristics (fat, high)
630fe9b6 1513 * The power limit is taken from priv->tx_power_user_lmt.
b481de9c 1514 */
630fe9b6 1515static int iwl4965_send_tx_power(struct iwl_priv *priv)
b481de9c 1516{
bb8c093b 1517 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 1518 int ret;
b481de9c
ZY		 1519 u8 band = 0;
1520 u8 is_fat = 0;
1521 u8 ctrl_chan_high = 0;
1522
1523 if (test_bit(STATUS_SCANNING, &priv->status)) {
1524 /* If this gets hit a lot, switch it to a BUG() and catch
1525 * the stack trace to find out who is calling this during
1526 * a scan. */
1527 IWL_WARNING("TX Power requested while scanning!\n");
1528 return -EAGAIN;
1529 }
1530
8318d78a 1531 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 1532
1533 is_fat = is_fat_channel(priv->active_rxon.flags);
1534
1535 if (is_fat &&
1536 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1537 ctrl_chan_high = 1;
1538
1539 cmd.band = band;
1540 cmd.channel = priv->active_rxon.channel;
1541
857485c0 1542 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 1543 le16_to_cpu(priv->active_rxon.channel),
1544 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 1545 if (ret)
1546 goto out;
b481de9c 1547
857485c0
TW		 1548 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1549
1550out:
1551 return ret;
b481de9c
ZY		 1552}
1553
7e8c519e
TW		 1554static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1555{
1556 int ret = 0;
1557 struct iwl4965_rxon_assoc_cmd rxon_assoc;
c1adf9fb
GG		 1558 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1559 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
7e8c519e
TW		 1560
1561 if ((rxon1->flags == rxon2->flags) &&
1562 (rxon1->filter_flags == rxon2->filter_flags) &&
1563 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1564 (rxon1->ofdm_ht_single_stream_basic_rates ==
1565 rxon2->ofdm_ht_single_stream_basic_rates) &&
1566 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1567 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1568 (rxon1->rx_chain == rxon2->rx_chain) &&
1569 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1570 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1571 return 0;
1572 }
1573
1574 rxon_assoc.flags = priv->staging_rxon.flags;
1575 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1576 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1577 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1578 rxon_assoc.reserved = 0;
1579 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1580 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1581 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1582 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1583 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1584
1585 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1586 sizeof(rxon_assoc), &rxon_assoc, NULL);
1587 if (ret)
1588 return ret;
1589
1590 return ret;
1591}
1592
3c935522 1593#ifdef IEEE80211_CONF_CHANNEL_SWITCH
a33c2f47 1594static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1595{
1596 int rc;
1597 u8 band = 0;
1598 u8 is_fat = 0;
1599 u8 ctrl_chan_high = 0;
bb8c093b 1600 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 1601 const struct iwl_channel_info *ch_info;
b481de9c 1602
8318d78a 1603 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 1604
8622e705 1605 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 1606
1607 is_fat = is_fat_channel(priv->staging_rxon.flags);
1608
1609 if (is_fat &&
1610 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1611 ctrl_chan_high = 1;
1612
1613 cmd.band = band;
1614 cmd.expect_beacon = 0;
1615 cmd.channel = cpu_to_le16(channel);
1616 cmd.rxon_flags = priv->active_rxon.flags;
1617 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1618 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1619 if (ch_info)
1620 cmd.expect_beacon = is_channel_radar(ch_info);
1621 else
1622 cmd.expect_beacon = 1;
1623
1624 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
1625 ctrl_chan_high, &cmd.tx_power);
1626 if (rc) {
1627 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
1628 return rc;
1629 }
1630
857485c0 1631 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 1632 return rc;
1633}
3c935522 1634#endif
b481de9c 1635
8b6eaea8 1636/**
e2a722eb 1637 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 1638 */
e2a722eb 1639static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 1640 struct iwl_tx_queue *txq,
e2a722eb 1641 u16 byte_cnt)
b481de9c 1642{
4ddbb7d0 1643 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 1644 int txq_id = txq->q.id;
1645 int write_ptr = txq->q.write_ptr;
1646 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1647 __le16 bc_ent;
b481de9c 1648
127901ab 1649 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
b481de9c 1650
127901ab 1651 bc_ent = cpu_to_le16(len & 0xFFF);
8b6eaea8 1652 /* Set up byte count within first 256 entries */
4ddbb7d0 1653 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
b481de9c 1654
8b6eaea8 1655 /* If within first 64 entries, duplicate at end */
127901ab 1656 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 1657 scd_bc_tbl[txq_id].
127901ab 1658 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
b481de9c
ZY		 1659}
1660
b481de9c
ZY		 1661/**
1662 * sign_extend - Sign extend a value using specified bit as sign-bit
1663 *
1664 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1665 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1666 *
1667 * @param oper value to sign extend
1668 * @param index 0 based bit index (0<=index<32) to sign bit
1669 */
1670static s32 sign_extend(u32 oper, int index)
1671{
1672 u8 shift = 31 - index;
1673
1674 return (s32)(oper << shift) >> shift;
1675}
1676
1677/**
91dbc5bd 1678 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
b481de9c
ZY		 1679 * @statistics: Provides the temperature reading from the uCode
1680 *
1681 * A return of <0 indicates bogus data in the statistics
1682 */
91dbc5bd 1683static int iwl4965_hw_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 1684{
1685 s32 temperature;
1686 s32 vt;
1687 s32 R1, R2, R3;
1688 u32 R4;
1689
1690 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1691 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
1692 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
1693 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1694 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1695 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1696 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1697 } else {
1698 IWL_DEBUG_TEMP("Running temperature calibration\n");
1699 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1700 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1701 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1702 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1703 }
1704
1705 /*
8b6eaea8 1706 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 1707 *
1708 * NOTE If we haven't received a statistics notification yet
1709 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 1710 * "initialize" ALIVE response.
1711 */
b481de9c
ZY		 1712 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1713 vt = sign_extend(R4, 23);
1714 else
1715 vt = sign_extend(
1716 le32_to_cpu(priv->statistics.general.temperature), 23);
1717
91dbc5bd 1718 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
b481de9c
ZY		 1719
1720 if (R3 == R1) {
1721 IWL_ERROR("Calibration conflict R1 == R3\n");
1722 return -1;
1723 }
1724
1725 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1726 * Add offset to center the adjustment around 0 degrees Centigrade. */
1727 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1728 temperature /= (R3 - R1);
91dbc5bd 1729 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
b481de9c 1730
91dbc5bd
EG		 1731 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n",
1732 temperature, KELVIN_TO_CELSIUS(temperature));
b481de9c
ZY		 1733
1734 return temperature;
1735}
1736
1737/* Adjust Txpower only if temperature variance is greater than threshold. */
1738#define IWL_TEMPERATURE_THRESHOLD 3
1739
1740/**
1741 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1742 *
1743 * If the temperature changed has changed sufficiently, then a recalibration
1744 * is needed.
1745 *
1746 * Assumes caller will replace priv->last_temperature once calibration
1747 * executed.
1748 */
c79dd5b5 1749static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1750{
1751 int temp_diff;
1752
1753 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1754 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
1755 return 0;
1756 }
1757
1758 temp_diff = priv->temperature - priv->last_temperature;
1759
1760 /* get absolute value */
1761 if (temp_diff < 0) {
1762 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
1763 temp_diff = -temp_diff;
1764 } else if (temp_diff == 0)
1765 IWL_DEBUG_POWER("Same temp, \n");
1766 else
1767 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
1768
1769 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1770 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
1771 return 0;
1772 }
1773
1774 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
1775
1776 return 1;
1777}
1778
5225640b 1779static void iwl4965_temperature_calib(struct iwl_priv *priv)
b481de9c 1780{
b481de9c 1781 s32 temp;
b481de9c 1782
91dbc5bd 1783 temp = iwl4965_hw_get_temperature(priv);
b481de9c
ZY		 1784 if (temp < 0)
1785 return;
1786
1787 if (priv->temperature != temp) {
1788 if (priv->temperature)
1789 IWL_DEBUG_TEMP("Temperature changed "
1790 "from %dC to %dC\n",
1791 KELVIN_TO_CELSIUS(priv->temperature),
1792 KELVIN_TO_CELSIUS(temp));
1793 else
1794 IWL_DEBUG_TEMP("Temperature "
1795 "initialized to %dC\n",
1796 KELVIN_TO_CELSIUS(temp));
1797 }
1798
1799 priv->temperature = temp;
1800 set_bit(STATUS_TEMPERATURE, &priv->status);
1801
203566f3
EG		 1802 if (!priv->disable_tx_power_cal &&
1803 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1804 iwl4965_is_temp_calib_needed(priv))
b481de9c
ZY		 1805 queue_work(priv->workqueue, &priv->txpower_work);
1806}
1807
fe01b477
RR		 1808/**
1809 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1810 */
c79dd5b5 1811static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 1812 u16 txq_id)
1813{
1814 /* Simply stop the queue, but don't change any configuration;
1815 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 1816 iwl_write_prph(priv,
12a81f60 1817 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 1818 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1819 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
fe01b477 1820}
b481de9c 1821
fe01b477 1822/**
7f3e4bb6 1823 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
b095d03a 1824 * priv->lock must be held by the caller
fe01b477 1825 */
30e553e3
TW		 1826static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1827 u16 ssn_idx, u8 tx_fifo)
fe01b477 1828{
b095d03a
RR		 1829 int ret = 0;
1830
9f17b318
TW		 1831 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1832 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1833 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1834 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1835 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
fe01b477 1836 return -EINVAL;
b481de9c
ZY		 1837 }
1838
3395f6e9 1839 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 1840 if (ret)
1841 return ret;
1842
fe01b477
RR		 1843 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1844
12a81f60 1845 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 1846
1847 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1848 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1849 /* supposes that ssn_idx is valid (!= 0xFFF) */
1850 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1851
12a81f60 1852 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
36470749 1853 iwl_txq_ctx_deactivate(priv, txq_id);
fe01b477
RR		 1854 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1855
3395f6e9 1856 iwl_release_nic_access(priv);
b095d03a 1857
fe01b477
RR		 1858 return 0;
1859}
b481de9c 1860
8b6eaea8
CB		 1861/**
1862 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1863 */
c79dd5b5 1864static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 1865 u16 txq_id)
1866{
1867 u32 tbl_dw_addr;
1868 u32 tbl_dw;
1869 u16 scd_q2ratid;
1870
30e553e3 1871 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
b481de9c
ZY		 1872
1873 tbl_dw_addr = priv->scd_base_addr +
038669e4 1874 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
b481de9c 1875
3395f6e9 1876 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 1877
1878 if (txq_id & 0x1)
1879 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1880 else
1881 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1882
3395f6e9 1883 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 1884
1885 return 0;
1886}
1887
fe01b477 1888
b481de9c 1889/**
8b6eaea8
CB		 1890 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1891 *
7f3e4bb6 1892 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
8b6eaea8 1893 * i.e. it must be one of the higher queues used for aggregation
b481de9c 1894 */
30e553e3
TW		 1895static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1896 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
b481de9c
ZY		 1897{
1898 unsigned long flags;
30e553e3 1899 int ret;
b481de9c
ZY		 1900 u16 ra_tid;
1901
9f17b318
TW		 1902 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1903 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1904 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1905 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1906 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
1907 return -EINVAL;
1908 }
b481de9c
ZY		 1909
1910 ra_tid = BUILD_RAxTID(sta_id, tid);
1911
8b6eaea8 1912 /* Modify device's station table to Tx this TID */
9f58671e 1913 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
b481de9c
ZY		 1914
1915 spin_lock_irqsave(&priv->lock, flags);
30e553e3
TW		 1916 ret = iwl_grab_nic_access(priv);
1917 if (ret) {
b481de9c 1918 spin_unlock_irqrestore(&priv->lock, flags);
30e553e3 1919 return ret;
b481de9c
ZY		 1920 }
1921
8b6eaea8 1922 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 1923 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1924
8b6eaea8 1925 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 1926 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1927
8b6eaea8 1928 /* Set this queue as a chain-building queue */
12a81f60 1929 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 1930
8b6eaea8
CB		 1931 /* Place first TFD at index corresponding to start sequence number.
1932 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 1933 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1934 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 1935 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1936
8b6eaea8 1937 /* Set up Tx window size and frame limit for this queue */
3395f6e9 1938 iwl_write_targ_mem(priv,
038669e4
EG		 1939 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1940 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1941 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
b481de9c 1942
3395f6e9 1943 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 1944 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1945 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1946 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c 1947
12a81f60 1948 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 1949
8b6eaea8 1950 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 1951 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1952
3395f6e9 1953 iwl_release_nic_access(priv);
b481de9c
ZY		 1954 spin_unlock_irqrestore(&priv->lock, flags);
1955
1956 return 0;
1957}
1958
133636de 1959
c1adf9fb
GG		 1960static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1961{
1962 switch (cmd_id) {
1963 case REPLY_RXON:
1964 return (u16) sizeof(struct iwl4965_rxon_cmd);
1965 default:
1966 return len;
1967 }
1968}
1969
133636de
TW		 1970static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1971{
1972 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1973 addsta->mode = cmd->mode;
1974 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1975 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1976 addsta->station_flags = cmd->station_flags;
1977 addsta->station_flags_msk = cmd->station_flags_msk;
1978 addsta->tid_disable_tx = cmd->tid_disable_tx;
1979 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1980 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1981 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1982 addsta->reserved1 = __constant_cpu_to_le16(0);
1983 addsta->reserved2 = __constant_cpu_to_le32(0);
1984
1985 return (u16)sizeof(struct iwl4965_addsta_cmd);
1986}
f20217d9 1987
f20217d9
TW		 1988static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
1989{
25a6572c 1990 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
f20217d9
TW		 1991}
1992
1993/**
a96a27f9 1994 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
f20217d9
TW		 1995 */
1996static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
1997 struct iwl_ht_agg *agg,
25a6572c
TW		 1998 struct iwl4965_tx_resp *tx_resp,
1999 int txq_id, u16 start_idx)
f20217d9
TW		 2000{
2001 u16 status;
25a6572c 2002 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
f20217d9
TW		 2003 struct ieee80211_tx_info *info = NULL;
2004 struct ieee80211_hdr *hdr = NULL;
e7d326ac 2005 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 2006 int i, sh, idx;
f20217d9 2007 u16 seq;
f20217d9
TW		 2008 if (agg->wait_for_ba)
2009 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
2010
2011 agg->frame_count = tx_resp->frame_count;
2012 agg->start_idx = start_idx;
e7d326ac 2013 agg->rate_n_flags = rate_n_flags;
f20217d9
TW		 2014 agg->bitmap = 0;
2015
3fd07a1e 2016 /* num frames attempted by Tx command */
f20217d9
TW		 2017 if (agg->frame_count == 1) {
2018 /* Only one frame was attempted; no block-ack will arrive */
2019 status = le16_to_cpu(frame_status[0].status);
25a6572c 2020 idx = start_idx;
f20217d9
TW		 2021
2022 /* FIXME: code repetition */
2023 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2024 agg->frame_count, agg->start_idx, idx);
2025
2026 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 2027 info->status.rates[0].count = tx_resp->failure_frame + 1;
f20217d9 2028 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c3056065 2029 info->flags |= iwl_is_tx_success(status) ?
f20217d9 2030 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2031 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
f20217d9
TW		 2032 /* FIXME: code repetition end */
2033
2034 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
2035 status & 0xff, tx_resp->failure_frame);
e7d326ac 2036 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
f20217d9
TW		 2037
2038 agg->wait_for_ba = 0;
2039 } else {
2040 /* Two or more frames were attempted; expect block-ack */
2041 u64 bitmap = 0;
2042 int start = agg->start_idx;
2043
2044 /* Construct bit-map of pending frames within Tx window */
2045 for (i = 0; i < agg->frame_count; i++) {
2046 u16 sc;
2047 status = le16_to_cpu(frame_status[i].status);
2048 seq = le16_to_cpu(frame_status[i].sequence);
2049 idx = SEQ_TO_INDEX(seq);
2050 txq_id = SEQ_TO_QUEUE(seq);
2051
2052 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
2053 AGG_TX_STATE_ABORT_MSK))
2054 continue;
2055
2056 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2057 agg->frame_count, txq_id, idx);
2058
2059 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
2060
2061 sc = le16_to_cpu(hdr->seq_ctrl);
2062 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2063 IWL_ERROR("BUG_ON idx doesn't match seq control"
2064 " idx=%d, seq_idx=%d, seq=%d\n",
2065 idx, SEQ_TO_SN(sc),
2066 hdr->seq_ctrl);
2067 return -1;
2068 }
2069
2070 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
2071 i, idx, SEQ_TO_SN(sc));
2072
2073 sh = idx - start;
2074 if (sh > 64) {
2075 sh = (start - idx) + 0xff;
2076 bitmap = bitmap << sh;
2077 sh = 0;
2078 start = idx;
2079 } else if (sh < -64)
2080 sh = 0xff - (start - idx);
2081 else if (sh < 0) {
2082 sh = start - idx;
2083 start = idx;
2084 bitmap = bitmap << sh;
2085 sh = 0;
2086 }
4aa41f12
EG		 2087 bitmap |= 1ULL << sh;
2088 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
2089 start, (unsigned long long)bitmap);
f20217d9
TW		 2090 }
2091
2092 agg->bitmap = bitmap;
2093 agg->start_idx = start;
f20217d9
TW		 2094 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2095 agg->frame_count, agg->start_idx,
2096 (unsigned long long)agg->bitmap);
2097
2098 if (bitmap)
2099 agg->wait_for_ba = 1;
2100 }
2101 return 0;
2102}
f20217d9
TW		 2103
2104/**
2105 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2106 */
2107static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2108 struct iwl_rx_mem_buffer *rxb)
2109{
2110 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2111 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2112 int txq_id = SEQ_TO_QUEUE(sequence);
2113 int index = SEQ_TO_INDEX(sequence);
2114 struct iwl_tx_queue *txq = &priv->txq[txq_id];
3fd07a1e 2115 struct ieee80211_hdr *hdr;
f20217d9
TW		 2116 struct ieee80211_tx_info *info;
2117 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
25a6572c 2118 u32 status = le32_to_cpu(tx_resp->u.status);
3fd07a1e
TW		 2119 int tid = MAX_TID_COUNT;
2120 int sta_id;
2121 int freed;
f20217d9 2122 u8 *qc = NULL;
f20217d9
TW		 2123
2124 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2125 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
2126 "is out of range [0-%d] %d %d\n", txq_id,
2127 index, txq->q.n_bd, txq->q.write_ptr,
2128 txq->q.read_ptr);
2129 return;
2130 }
2131
2132 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2133 memset(&info->status, 0, sizeof(info->status));
2134
f20217d9 2135 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
3fd07a1e 2136 if (ieee80211_is_data_qos(hdr->frame_control)) {
fd7c8a40 2137 qc = ieee80211_get_qos_ctl(hdr);
f20217d9
TW		 2138 tid = qc[0] & 0xf;
2139 }
2140
2141 sta_id = iwl_get_ra_sta_id(priv, hdr);
2142 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2143 IWL_ERROR("Station not known\n");
2144 return;
2145 }
2146
2147 if (txq->sched_retry) {
2148 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2149 struct iwl_ht_agg *agg = NULL;
2150
3fd07a1e 2151 WARN_ON(!qc);
f20217d9
TW		 2152
2153 agg = &priv->stations[sta_id].tid[tid].agg;
2154
25a6572c 2155 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
f20217d9 2156
3235427e
RR		 2157 /* check if BAR is needed */
2158 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2159 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
f20217d9
TW		 2160
2161 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
f20217d9
TW		 2162 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2163 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
2164 "%d index %d\n", scd_ssn , index);
17b88929 2165 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
f20217d9
TW		 2166 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2167
3fd07a1e
TW		 2168 if (priv->mac80211_registered &&
2169 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2170 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
f20217d9
TW		 2171 if (agg->state == IWL_AGG_OFF)
2172 ieee80211_wake_queue(priv->hw, txq_id);
2173 else
3fd07a1e
TW		 2174 ieee80211_wake_queue(priv->hw,
2175 txq->swq_id);
f20217d9 2176 }
f20217d9
TW		 2177 }
2178 } else {
e6a9854b 2179 info->status.rates[0].count = tx_resp->failure_frame + 1;
3fd07a1e
TW		 2180 info->flags |= iwl_is_tx_success(status) ?
2181 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2182 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 2183 le32_to_cpu(tx_resp->rate_n_flags),
2184 info);
2185
3fd07a1e
TW		 2186 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) "
2187 "rate_n_flags 0x%x retries %d\n",
2188 txq_id,
2189 iwl_get_tx_fail_reason(status), status,
2190 le32_to_cpu(tx_resp->rate_n_flags),
2191 tx_resp->failure_frame);
e7d326ac 2192
3fd07a1e 2193 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
ed7fafec 2194 if (qc && likely(sta_id != IWL_INVALID_STATION))
f20217d9 2195 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 2196
2197 if (priv->mac80211_registered &&
2198 (iwl_queue_space(&txq->q) > txq->q.low_mark))
f20217d9 2199 ieee80211_wake_queue(priv->hw, txq_id);
f20217d9 2200 }
f20217d9 2201
ed7fafec 2202 if (qc && likely(sta_id != IWL_INVALID_STATION))
3fd07a1e
TW		 2203 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
2204
f20217d9
TW		 2205 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2206 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
2207}
2208
caab8f1a
TW		 2209static int iwl4965_calc_rssi(struct iwl_priv *priv,
2210 struct iwl_rx_phy_res *rx_resp)
2211{
2212 /* data from PHY/DSP regarding signal strength, etc.,
2213 * contents are always there, not configurable by host. */
2214 struct iwl4965_rx_non_cfg_phy *ncphy =
2215 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2216 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2217 >> IWL49_AGC_DB_POS;
2218
2219 u32 valid_antennae =
2220 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2221 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2222 u8 max_rssi = 0;
2223 u32 i;
2224
2225 /* Find max rssi among 3 possible receivers.
2226 * These values are measured by the digital signal processor (DSP).
2227 * They should stay fairly constant even as the signal strength varies,
2228 * if the radio's automatic gain control (AGC) is working right.
2229 * AGC value (see below) will provide the "interesting" info. */
2230 for (i = 0; i < 3; i++)
2231 if (valid_antennae & (1 << i))
2232 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2233
2234 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2235 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2236 max_rssi, agc);
2237
2238 /* dBm = max_rssi dB - agc dB - constant.
2239 * Higher AGC (higher radio gain) means lower signal. */
2240 return max_rssi - agc - IWL_RSSI_OFFSET;
2241}
2242
f20217d9 2243
b481de9c 2244/* Set up 4965-specific Rx frame reply handlers */
d4789efe 2245static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 2246{
2247 /* Legacy Rx frames */
1781a07f 2248 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
37a44211 2249 /* Tx response */
f20217d9 2250 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
b481de9c
ZY		 2251}
2252
4e39317d 2253static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2254{
2255 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
b481de9c
ZY		 2256}
2257
4e39317d 2258static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2259{
4e39317d 2260 cancel_work_sync(&priv->txpower_work);
b481de9c
ZY		 2261}
2262
3c424c28
TW		 2263
2264static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 2265 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 2266};
2267
857485c0 2268static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
c1adf9fb 2269 .get_hcmd_size = iwl4965_get_hcmd_size,
133636de 2270 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
f0832f13
EG		 2271 .chain_noise_reset = iwl4965_chain_noise_reset,
2272 .gain_computation = iwl4965_gain_computation,
a326a5d0 2273 .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag,
caab8f1a 2274 .calc_rssi = iwl4965_calc_rssi,
857485c0
TW		 2275};
2276
6bc913bd 2277static struct iwl_lib_ops iwl4965_lib = {
5425e490 2278 .set_hw_params = iwl4965_hw_set_hw_params,
e2a722eb 2279 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
da1bc453 2280 .txq_set_sched = iwl4965_txq_set_sched,
30e553e3
TW		 2281 .txq_agg_enable = iwl4965_txq_agg_enable,
2282 .txq_agg_disable = iwl4965_txq_agg_disable,
d4789efe 2283 .rx_handler_setup = iwl4965_rx_handler_setup,
4e39317d
EG		 2284 .setup_deferred_work = iwl4965_setup_deferred_work,
2285 .cancel_deferred_work = iwl4965_cancel_deferred_work,
57aab75a
TW		 2286 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2287 .alive_notify = iwl4965_alive_notify,
f3ccc08c 2288 .init_alive_start = iwl4965_init_alive_start,
57aab75a 2289 .load_ucode = iwl4965_load_bsm,
6f4083aa 2290 .apm_ops = {
91238714 2291 .init = iwl4965_apm_init,
7f066108 2292 .reset = iwl4965_apm_reset,
f118a91d 2293 .stop = iwl4965_apm_stop,
694cc56d 2294 .config = iwl4965_nic_config,
5b9f8cd3 2295 .set_pwr_src = iwl_set_pwr_src,
6f4083aa 2296 },
6bc913bd 2297 .eeprom_ops = {
073d3f5f
TW		 2298 .regulatory_bands = {
2299 EEPROM_REGULATORY_BAND_1_CHANNELS,
2300 EEPROM_REGULATORY_BAND_2_CHANNELS,
2301 EEPROM_REGULATORY_BAND_3_CHANNELS,
2302 EEPROM_REGULATORY_BAND_4_CHANNELS,
2303 EEPROM_REGULATORY_BAND_5_CHANNELS,
2304 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
2305 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
2306 },
6bc913bd
AK		 2307 .verify_signature = iwlcore_eeprom_verify_signature,
2308 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2309 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 2310 .calib_version = iwl4965_eeprom_calib_version,
073d3f5f 2311 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 2312 },
630fe9b6 2313 .send_tx_power = iwl4965_send_tx_power,
5b9f8cd3 2314 .update_chain_flags = iwl_update_chain_flags,
8f91aecb 2315 .temperature = iwl4965_temperature_calib,
6bc913bd
AK		 2316};
2317
2318static struct iwl_ops iwl4965_ops = {
2319 .lib = &iwl4965_lib,
3c424c28 2320 .hcmd = &iwl4965_hcmd,
857485c0 2321 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 2322};
2323
fed9017e 2324struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 2325 .name = "4965AGN",
25e35a56 2326 .fw_name = IWL4965_MODULE_FIRMWARE,
82b9a121 2327 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 2328 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
0ef2ca67
TW		 2329 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2330 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
6bc913bd 2331 .ops = &iwl4965_ops,
1ea87396 2332 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 2333};
2334
d16dc48a 2335/* Module firmware */
25e35a56 2336MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE);
d16dc48a 2337
1ea87396
AK		 2338module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
2339MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2340module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
2341MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b 2342module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
61a2d07d 2343MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
1ea87396
AK		 2344module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
2345MODULE_PARM_DESC(debug, "debug output mask");
2346module_param_named(
2347 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
2348MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2349
2350module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
2351MODULE_PARM_DESC(queues_num, "number of hw queues.");
1ea87396
AK		 2352/* QoS */
2353module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
2354MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
49779293
RR		 2355/* 11n */
2356module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, 0444);
2357MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
1ea87396
AK		 2358module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
2359MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
49779293 2360
3a1081e8
EK		 2361module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
2362MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
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