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iwlwifi: move scan to iwl-scan.c iwlcore
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
3e0d4cb1 42#include "iwl-dev.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c 45#include "iwl-helpers.h"
f0832f13 46#include "iwl-calib.h"
5083e563 47#include "iwl-sta.h"
b481de9c 48
630fe9b6
TW		 49static int iwl4965_send_tx_power(struct iwl_priv *priv);
50
1ea87396
AK		 51/* module parameters */
52static struct iwl_mod_params iwl4965_mod_params = {
038669e4 53 .num_of_queues = IWL49_NUM_QUEUES,
1ea87396
AK		 54 .enable_qos = 1,
55 .amsdu_size_8K = 1,
3a1081e8 56 .restart_fw = 1,
1ea87396
AK		 57 /* the rest are 0 by default */
58};
59
57aab75a
TW		 60/* check contents of special bootstrap uCode SRAM */
61static int iwl4965_verify_bsm(struct iwl_priv *priv)
62{
63 __le32 *image = priv->ucode_boot.v_addr;
64 u32 len = priv->ucode_boot.len;
65 u32 reg;
66 u32 val;
67
68 IWL_DEBUG_INFO("Begin verify bsm\n");
69
70 /* verify BSM SRAM contents */
71 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
72 for (reg = BSM_SRAM_LOWER_BOUND;
73 reg < BSM_SRAM_LOWER_BOUND + len;
74 reg += sizeof(u32), image++) {
75 val = iwl_read_prph(priv, reg);
76 if (val != le32_to_cpu(*image)) {
77 IWL_ERROR("BSM uCode verification failed at "
78 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
79 BSM_SRAM_LOWER_BOUND,
80 reg - BSM_SRAM_LOWER_BOUND, len,
81 val, le32_to_cpu(*image));
82 return -EIO;
83 }
84 }
85
86 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
87
88 return 0;
89}
90
91/**
92 * iwl4965_load_bsm - Load bootstrap instructions
93 *
94 * BSM operation:
95 *
96 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
97 * in special SRAM that does not power down during RFKILL. When powering back
98 * up after power-saving sleeps (or during initial uCode load), the BSM loads
99 * the bootstrap program into the on-board processor, and starts it.
100 *
101 * The bootstrap program loads (via DMA) instructions and data for a new
102 * program from host DRAM locations indicated by the host driver in the
103 * BSM_DRAM_* registers. Once the new program is loaded, it starts
104 * automatically.
105 *
106 * When initializing the NIC, the host driver points the BSM to the
107 * "initialize" uCode image. This uCode sets up some internal data, then
108 * notifies host via "initialize alive" that it is complete.
109 *
110 * The host then replaces the BSM_DRAM_* pointer values to point to the
111 * normal runtime uCode instructions and a backup uCode data cache buffer
112 * (filled initially with starting data values for the on-board processor),
113 * then triggers the "initialize" uCode to load and launch the runtime uCode,
114 * which begins normal operation.
115 *
116 * When doing a power-save shutdown, runtime uCode saves data SRAM into
117 * the backup data cache in DRAM before SRAM is powered down.
118 *
119 * When powering back up, the BSM loads the bootstrap program. This reloads
120 * the runtime uCode instructions and the backup data cache into SRAM,
121 * and re-launches the runtime uCode from where it left off.
122 */
123static int iwl4965_load_bsm(struct iwl_priv *priv)
124{
125 __le32 *image = priv->ucode_boot.v_addr;
126 u32 len = priv->ucode_boot.len;
127 dma_addr_t pinst;
128 dma_addr_t pdata;
129 u32 inst_len;
130 u32 data_len;
131 int i;
132 u32 done;
133 u32 reg_offset;
134 int ret;
135
136 IWL_DEBUG_INFO("Begin load bsm\n");
137
fe9b6b72
RR		 138 priv->ucode_type = UCODE_RT;
139
57aab75a
TW		 140 /* make sure bootstrap program is no larger than BSM's SRAM size */
141 if (len > IWL_MAX_BSM_SIZE)
142 return -EINVAL;
143
144 /* Tell bootstrap uCode where to find the "Initialize" uCode
145 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
2d87889f 146 * NOTE: iwl_init_alive_start() will replace these values,
57aab75a 147 * after the "initialize" uCode has run, to point to
2d87889f
TW		 148 * runtime/protocol instructions and backup data cache.
149 */
57aab75a
TW		 150 pinst = priv->ucode_init.p_addr >> 4;
151 pdata = priv->ucode_init_data.p_addr >> 4;
152 inst_len = priv->ucode_init.len;
153 data_len = priv->ucode_init_data.len;
154
155 ret = iwl_grab_nic_access(priv);
156 if (ret)
157 return ret;
158
159 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
160 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
161 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
162 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
163
164 /* Fill BSM memory with bootstrap instructions */
165 for (reg_offset = BSM_SRAM_LOWER_BOUND;
166 reg_offset < BSM_SRAM_LOWER_BOUND + len;
167 reg_offset += sizeof(u32), image++)
168 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
169
170 ret = iwl4965_verify_bsm(priv);
171 if (ret) {
172 iwl_release_nic_access(priv);
173 return ret;
174 }
175
176 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
177 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
178 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
179 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
180
181 /* Load bootstrap code into instruction SRAM now,
182 * to prepare to load "initialize" uCode */
183 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
184
185 /* Wait for load of bootstrap uCode to finish */
186 for (i = 0; i < 100; i++) {
187 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
188 if (!(done & BSM_WR_CTRL_REG_BIT_START))
189 break;
190 udelay(10);
191 }
192 if (i < 100)
193 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
194 else {
195 IWL_ERROR("BSM write did not complete!\n");
196 return -EIO;
197 }
198
199 /* Enable future boot loads whenever power management unit triggers it
200 * (e.g. when powering back up after power-save shutdown) */
201 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
202
203 iwl_release_nic_access(priv);
204
205 return 0;
206}
207
f3ccc08c
EG		 208/**
209 * iwl4965_set_ucode_ptrs - Set uCode address location
210 *
211 * Tell initialization uCode where to find runtime uCode.
212 *
213 * BSM registers initially contain pointers to initialization uCode.
214 * We need to replace them to load runtime uCode inst and data,
215 * and to save runtime data when powering down.
216 */
217static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
218{
219 dma_addr_t pinst;
220 dma_addr_t pdata;
221 unsigned long flags;
222 int ret = 0;
223
224 /* bits 35:4 for 4965 */
225 pinst = priv->ucode_code.p_addr >> 4;
226 pdata = priv->ucode_data_backup.p_addr >> 4;
227
228 spin_lock_irqsave(&priv->lock, flags);
229 ret = iwl_grab_nic_access(priv);
230 if (ret) {
231 spin_unlock_irqrestore(&priv->lock, flags);
232 return ret;
233 }
234
235 /* Tell bootstrap uCode where to find image to load */
236 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
237 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
238 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
239 priv->ucode_data.len);
240
241 /* Inst bytecount must be last to set up, bit 31 signals uCode
242 * that all new ptr/size info is in place */
243 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
244 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
245 iwl_release_nic_access(priv);
246
247 spin_unlock_irqrestore(&priv->lock, flags);
248
249 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
250
251 return ret;
252}
253
254/**
255 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
256 *
257 * Called after REPLY_ALIVE notification received from "initialize" uCode.
258 *
259 * The 4965 "initialize" ALIVE reply contains calibration data for:
260 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
261 * (3945 does not contain this data).
262 *
263 * Tell "initialize" uCode to go ahead and load the runtime uCode.
264*/
265static void iwl4965_init_alive_start(struct iwl_priv *priv)
266{
267 /* Check alive response for "valid" sign from uCode */
268 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
269 /* We had an error bringing up the hardware, so take it
270 * all the way back down so we can try again */
271 IWL_DEBUG_INFO("Initialize Alive failed.\n");
272 goto restart;
273 }
274
275 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
276 * This is a paranoid check, because we would not have gotten the
277 * "initialize" alive if code weren't properly loaded. */
278 if (iwl_verify_ucode(priv)) {
279 /* Runtime instruction load was bad;
280 * take it all the way back down so we can try again */
281 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
282 goto restart;
283 }
284
285 /* Calculate temperature */
286 priv->temperature = iwl4965_get_temperature(priv);
287
288 /* Send pointers to protocol/runtime uCode image ... init code will
289 * load and launch runtime uCode, which will send us another "Alive"
290 * notification. */
291 IWL_DEBUG_INFO("Initialization Alive received.\n");
292 if (iwl4965_set_ucode_ptrs(priv)) {
293 /* Runtime instruction load won't happen;
294 * take it all the way back down so we can try again */
295 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
296 goto restart;
297 }
298 return;
299
300restart:
301 queue_work(priv->workqueue, &priv->restart);
302}
303
b481de9c
ZY		 304static int is_fat_channel(__le32 rxon_flags)
305{
306 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
307 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
308}
309
17744ff6
TW		 310int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
311{
312 int idx = 0;
313
314 /* 4965 HT rate format */
315 if (rate_n_flags & RATE_MCS_HT_MSK) {
316 idx = (rate_n_flags & 0xff);
317
fde0db31
GC		 318 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
319 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
17744ff6
TW		 320
321 idx += IWL_FIRST_OFDM_RATE;
322 /* skip 9M not supported in ht*/
323 if (idx >= IWL_RATE_9M_INDEX)
324 idx += 1;
325 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
326 return idx;
327
328 /* 4965 legacy rate format, search for match in table */
329 } else {
1826dcc0
TW		 330 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
331 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
17744ff6
TW		 332 return idx;
333 }
334
335 return -1;
336}
337
4c424e4c
RR		 338/**
339 * translate ucode response to mac80211 tx status control values
340 */
c79dd5b5 341void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
e039fa4a 342 struct ieee80211_tx_info *control)
4c424e4c
RR		 343{
344 int rate_index;
345
346 control->antenna_sel_tx =
fde0db31 347 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
4c424e4c 348 if (rate_n_flags & RATE_MCS_HT_MSK)
e039fa4a 349 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
4c424e4c 350 if (rate_n_flags & RATE_MCS_GF_MSK)
e039fa4a 351 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
4c424e4c 352 if (rate_n_flags & RATE_MCS_FAT_MSK)
e039fa4a 353 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
4c424e4c 354 if (rate_n_flags & RATE_MCS_DUP_MSK)
e039fa4a 355 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
4c424e4c 356 if (rate_n_flags & RATE_MCS_SGI_MSK)
e039fa4a 357 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
4c424e4c 358 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
2e92e6f2
JB		 359 if (control->band == IEEE80211_BAND_5GHZ)
360 rate_index -= IWL_FIRST_OFDM_RATE;
361 control->tx_rate_idx = rate_index;
4c424e4c 362}
17744ff6 363
8614f360
TW		 364/*
365 * EEPROM handlers
366 */
367
368static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
369{
370 u16 eeprom_ver;
371 u16 calib_ver;
372
373 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
374
375 calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
376
377 if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
378 calib_ver < EEPROM_4965_TX_POWER_VERSION)
379 goto err;
380
381 return 0;
382err:
383 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
384 eeprom_ver, EEPROM_4965_EEPROM_VERSION,
385 calib_ver, EEPROM_4965_TX_POWER_VERSION);
386 return -EINVAL;
387
388}
079a2533 389int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 390{
d8609652 391 int ret;
b481de9c
ZY		 392 unsigned long flags;
393
394 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 395 ret = iwl_grab_nic_access(priv);
d8609652 396 if (ret) {
b481de9c 397 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 398 return ret;
b481de9c
ZY		 399 }
400
6f4083aa 401 if (src == IWL_PWR_SRC_VAUX) {
b481de9c 402 u32 val;
d8609652 403 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
6f4083aa 404 &val);
b481de9c 405
6f4083aa 406 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
3395f6e9 407 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 408 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
409 ~APMG_PS_CTRL_MSK_PWR_SRC);
410 }
411 } else {
3395f6e9 412 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 413 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
414 ~APMG_PS_CTRL_MSK_PWR_SRC);
415 }
b481de9c 416
3395f6e9 417 iwl_release_nic_access(priv);
b481de9c
ZY		 418 spin_unlock_irqrestore(&priv->lock, flags);
419
d8609652 420 return ret;
b481de9c
ZY		 421}
422
da1bc453
TW		 423/*
424 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
425 * must be called under priv->lock and mac access
426 */
427static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
b481de9c 428{
da1bc453 429 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
b481de9c
ZY		 430}
431
91238714 432static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 433{
91238714 434 int ret = 0;
b481de9c 435
3395f6e9 436 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 437 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 438
8f061891
TW		 439 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
440 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
441 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
442
91238714
TW		 443 /* set "initialization complete" bit to move adapter
444 * D0U* --> D0A* state */
3395f6e9 445 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 446
91238714
TW		 447 /* wait for clock stabilization */
448 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
449 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
450 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
451 if (ret < 0) {
452 IWL_DEBUG_INFO("Failed to init the card\n");
453 goto out;
b481de9c
ZY		 454 }
455
91238714
TW		 456 ret = iwl_grab_nic_access(priv);
457 if (ret)
458 goto out;
b481de9c 459
91238714 460 /* enable DMA */
8f061891
TW		 461 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
462 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 463
464 udelay(20);
465
8f061891 466 /* disable L1-Active */
3395f6e9 467 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 468 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 469
3395f6e9 470 iwl_release_nic_access(priv);
91238714 471out:
91238714
TW		 472 return ret;
473}
474
694cc56d
TW		 475
476static void iwl4965_nic_config(struct iwl_priv *priv)
91238714
TW		 477{
478 unsigned long flags;
91238714 479 u32 val;
694cc56d
TW		 480 u16 radio_cfg;
481 u8 val_link;
6f4083aa 482
b481de9c
ZY		 483 spin_lock_irqsave(&priv->lock, flags);
484
b661c819 485 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
b481de9c
ZY		 486 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
487 /* Enable No Snoop field */
488 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
489 val & ~(1 << 11));
490 }
491
b481de9c
ZY		 492 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
493
8f061891
TW		 494 /* L1 is enabled by BIOS */
495 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
496 /* diable L0S disabled L1A enabled */
497 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
498 else
499 /* L0S enabled L1A disabled */
500 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
b481de9c 501
694cc56d 502 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
b481de9c 503
694cc56d
TW		 504 /* write radio config values to register */
505 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
506 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
507 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
508 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
509 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
b481de9c 510
694cc56d 511 /* set CSR_HW_CONFIG_REG for uCode use */
3395f6e9 512 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
a395b920
TW		 513 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
514 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 515
694cc56d
TW		 516 priv->calib_info = (struct iwl_eeprom_calib_info *)
517 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
518
519 spin_unlock_irqrestore(&priv->lock, flags);
520}
521
46315e01
TW		 522static int iwl4965_apm_stop_master(struct iwl_priv *priv)
523{
524 int ret = 0;
525 unsigned long flags;
526
527 spin_lock_irqsave(&priv->lock, flags);
528
529 /* set stop master bit */
530 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
531
532 ret = iwl_poll_bit(priv, CSR_RESET,
533 CSR_RESET_REG_FLAG_MASTER_DISABLED,
534 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
535 if (ret < 0)
536 goto out;
537
538out:
539 spin_unlock_irqrestore(&priv->lock, flags);
540 IWL_DEBUG_INFO("stop master\n");
541
542 return ret;
543}
544
f118a91d
TW		 545static void iwl4965_apm_stop(struct iwl_priv *priv)
546{
547 unsigned long flags;
548
46315e01 549 iwl4965_apm_stop_master(priv);
f118a91d
TW		 550
551 spin_lock_irqsave(&priv->lock, flags);
552
553 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
554
555 udelay(10);
556
557 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
558 spin_unlock_irqrestore(&priv->lock, flags);
559}
560
7f066108 561static int iwl4965_apm_reset(struct iwl_priv *priv)
b481de9c 562{
7f066108 563 int ret = 0;
b481de9c
ZY		 564 unsigned long flags;
565
46315e01 566 iwl4965_apm_stop_master(priv);
b481de9c
ZY		 567
568 spin_lock_irqsave(&priv->lock, flags);
569
3395f6e9 570 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 571
572 udelay(10);
573
7f066108
TW		 574 /* FIXME: put here L1A -L0S w/a */
575
3395f6e9 576 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d 577
7f066108 578 ret = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 579 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
580 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
581
7f066108
TW		 582 if (ret)
583 goto out;
584
b481de9c
ZY		 585 udelay(10);
586
7f066108
TW		 587 ret = iwl_grab_nic_access(priv);
588 if (ret)
589 goto out;
590 /* Enable DMA and BSM Clock */
591 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
592 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 593
7f066108 594 udelay(10);
b481de9c 595
7f066108
TW		 596 /* disable L1A */
597 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
598 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 599
7f066108 600 iwl_release_nic_access(priv);
b481de9c
ZY		 601
602 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
603 wake_up_interruptible(&priv->wait_command_queue);
604
7f066108 605out:
b481de9c
ZY		 606 spin_unlock_irqrestore(&priv->lock, flags);
607
7f066108 608 return ret;
b481de9c
ZY		 609}
610
611#define REG_RECALIB_PERIOD (60)
612
c79dd5b5 613void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 614{
bb8c093b 615 struct iwl4965_ct_kill_config cmd;
b481de9c 616 unsigned long flags;
857485c0 617 int ret = 0;
b481de9c
ZY		 618
619 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 620 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 621 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
622 spin_unlock_irqrestore(&priv->lock, flags);
623
099b40b7 624 cmd.critical_temperature_R =
b73cdf27
EG		 625 cpu_to_le32(priv->hw_params.ct_kill_threshold);
626
857485c0
TW		 627 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
628 sizeof(cmd), &cmd);
629 if (ret)
b481de9c
ZY		 630 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
631 else
b73cdf27
EG		 632 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
633 "critical temperature is %d\n",
634 cmd.critical_temperature_R);
b481de9c
ZY		 635}
636
b481de9c
ZY		 637/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
638 * Called after every association, but this runs only once!
639 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 640static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 641{
f0832f13 642 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 643
3109ece1 644 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 645 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 646
647 memset(&cmd, 0, sizeof(cmd));
648 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
649 cmd.diff_gain_a = 0;
650 cmd.diff_gain_b = 0;
651 cmd.diff_gain_c = 0;
f0832f13
EG		 652 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
653 sizeof(cmd), &cmd))
654 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 655 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
656 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
657 }
b481de9c
ZY		 658}
659
f0832f13
EG		 660static void iwl4965_gain_computation(struct iwl_priv *priv,
661 u32 *average_noise,
662 u16 min_average_noise_antenna_i,
663 u32 min_average_noise)
b481de9c 664{
f0832f13
EG		 665 int i, ret;
666 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 667
f0832f13 668 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 669
f0832f13
EG		 670 for (i = 0; i < NUM_RX_CHAINS; i++) {
671 s32 delta_g = 0;
b481de9c 672
f0832f13
EG		 673 if (!(data->disconn_array[i]) &&
674 (data->delta_gain_code[i] ==
b481de9c 675 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 676 delta_g = average_noise[i] - min_average_noise;
677 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
678 data->delta_gain_code[i] =
679 min(data->delta_gain_code[i],
680 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
681
682 data->delta_gain_code[i] =
683 (data->delta_gain_code[i] | (1 << 2));
684 } else {
685 data->delta_gain_code[i] = 0;
b481de9c 686 }
b481de9c 687 }
f0832f13
EG		 688 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
689 data->delta_gain_code[0],
690 data->delta_gain_code[1],
691 data->delta_gain_code[2]);
b481de9c 692
f0832f13
EG		 693 /* Differential gain gets sent to uCode only once */
694 if (!data->radio_write) {
695 struct iwl4965_calibration_cmd cmd;
696 data->radio_write = 1;
b481de9c 697
f0832f13
EG		 698 memset(&cmd, 0, sizeof(cmd));
699 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
700 cmd.diff_gain_a = data->delta_gain_code[0];
701 cmd.diff_gain_b = data->delta_gain_code[1];
702 cmd.diff_gain_c = data->delta_gain_code[2];
703 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
704 sizeof(cmd), &cmd);
705 if (ret)
706 IWL_DEBUG_CALIB("fail sending cmd "
707 "REPLY_PHY_CALIBRATION_CMD \n");
708
709 /* TODO we might want recalculate
710 * rx_chain in rxon cmd */
711
712 /* Mark so we run this algo only once! */
713 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 714 }
f0832f13
EG		 715 data->chain_noise_a = 0;
716 data->chain_noise_b = 0;
717 data->chain_noise_c = 0;
718 data->chain_signal_a = 0;
719 data->chain_signal_b = 0;
720 data->chain_signal_c = 0;
721 data->beacon_count = 0;
b481de9c
ZY		 722}
723
b481de9c
ZY		 724static void iwl4965_bg_txpower_work(struct work_struct *work)
725{
c79dd5b5 726 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 727 txpower_work);
728
729 /* If a scan happened to start before we got here
730 * then just return; the statistics notification will
731 * kick off another scheduled work to compensate for
732 * any temperature delta we missed here. */
733 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
734 test_bit(STATUS_SCANNING, &priv->status))
735 return;
736
737 mutex_lock(&priv->mutex);
738
739 /* Regardless of if we are assocaited, we must reconfigure the
740 * TX power since frames can be sent on non-radar channels while
741 * not associated */
630fe9b6 742 iwl4965_send_tx_power(priv);
b481de9c
ZY		 743
744 /* Update last_temperature to keep is_calib_needed from running
745 * when it isn't needed... */
746 priv->last_temperature = priv->temperature;
747
748 mutex_unlock(&priv->mutex);
749}
750
751/*
752 * Acquire priv->lock before calling this function !
753 */
c79dd5b5 754static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 755{
3395f6e9 756 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 757 (index & 0xff) | (txq_id << 8));
12a81f60 758 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 759}
760
8b6eaea8
CB		 761/**
762 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
763 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
764 * @scd_retry: (1) Indicates queue will be used in aggregation mode
765 *
766 * NOTE: Acquire priv->lock before calling this function !
b481de9c 767 */
c79dd5b5 768static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
16466903 769 struct iwl_tx_queue *txq,
b481de9c
ZY		 770 int tx_fifo_id, int scd_retry)
771{
772 int txq_id = txq->q.id;
8b6eaea8
CB		 773
774 /* Find out whether to activate Tx queue */
b481de9c
ZY		 775 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
776
8b6eaea8 777 /* Set up and activate */
12a81f60 778 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 779 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
780 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
781 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
782 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
783 IWL49_SCD_QUEUE_STTS_REG_MSK);
b481de9c
ZY		 784
785 txq->sched_retry = scd_retry;
786
787 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 788 active ? "Activate" : "Deactivate",
b481de9c
ZY		 789 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
790}
791
792static const u16 default_queue_to_tx_fifo[] = {
793 IWL_TX_FIFO_AC3,
794 IWL_TX_FIFO_AC2,
795 IWL_TX_FIFO_AC1,
796 IWL_TX_FIFO_AC0,
038669e4 797 IWL49_CMD_FIFO_NUM,
b481de9c
ZY		 798 IWL_TX_FIFO_HCCA_1,
799 IWL_TX_FIFO_HCCA_2
800};
801
c79dd5b5 802int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 803{
804 u32 a;
805 int i = 0;
806 unsigned long flags;
857485c0 807 int ret;
b481de9c
ZY		 808
809 spin_lock_irqsave(&priv->lock, flags);
810
3395f6e9 811 ret = iwl_grab_nic_access(priv);
857485c0 812 if (ret) {
b481de9c 813 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 814 return ret;
b481de9c
ZY		 815 }
816
8b6eaea8 817 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 818 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
038669e4
EG		 819 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
820 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 821 iwl_write_targ_mem(priv, a, 0);
038669e4 822 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 823 iwl_write_targ_mem(priv, a, 0);
5425e490 824 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 825 iwl_write_targ_mem(priv, a, 0);
b481de9c 826
8b6eaea8 827 /* Tel 4965 where to find Tx byte count tables */
12a81f60 828 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 829 (priv->shared_phys +
bb8c093b 830 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 831
832 /* Disable chain mode for all queues */
12a81f60 833 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 834
8b6eaea8 835 /* Initialize each Tx queue (including the command queue) */
5425e490 836 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 837
838 /* TFD circular buffer read/write indexes */
12a81f60 839 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 840 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 841
842 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 843 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 844 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
845 (SCD_WIN_SIZE <<
846 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
847 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 848
849 /* Frame limit */
3395f6e9 850 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 851 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
852 sizeof(u32),
853 (SCD_FRAME_LIMIT <<
854 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
855 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c
ZY		 856
857 }
12a81f60 858 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 859 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 860
8b6eaea8 861 /* Activate all Tx DMA/FIFO channels */
da1bc453 862 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
b481de9c
ZY		 863
864 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 865
866 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 867 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
868 int ac = default_queue_to_tx_fifo[i];
36470749 869 iwl_txq_ctx_activate(priv, i);
b481de9c
ZY		 870 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
871 }
872
3395f6e9 873 iwl_release_nic_access(priv);
b481de9c
ZY		 874 spin_unlock_irqrestore(&priv->lock, flags);
875
857485c0 876 return ret;
b481de9c
ZY		 877}
878
f0832f13
EG		 879static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
880 .min_nrg_cck = 97,
881 .max_nrg_cck = 0,
882
883 .auto_corr_min_ofdm = 85,
884 .auto_corr_min_ofdm_mrc = 170,
885 .auto_corr_min_ofdm_x1 = 105,
886 .auto_corr_min_ofdm_mrc_x1 = 220,
887
888 .auto_corr_max_ofdm = 120,
889 .auto_corr_max_ofdm_mrc = 210,
890 .auto_corr_max_ofdm_x1 = 140,
891 .auto_corr_max_ofdm_mrc_x1 = 270,
892
893 .auto_corr_min_cck = 125,
894 .auto_corr_max_cck = 200,
895 .auto_corr_min_cck_mrc = 200,
896 .auto_corr_max_cck_mrc = 400,
897
898 .nrg_th_cck = 100,
899 .nrg_th_ofdm = 100,
900};
f0832f13 901
8b6eaea8 902/**
5425e490 903 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 904 *
905 * Called when initializing driver
906 */
5425e490 907int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 908{
316c30d9 909
038669e4 910 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1ea87396 911 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 912 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
038669e4 913 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
059ff826 914 return -EINVAL;
316c30d9 915 }
b481de9c 916
5425e490 917 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
7f3e4bb6 918 priv->hw_params.first_ampdu_q = IWL49_FIRST_AMPDU_QUEUE;
099b40b7 919 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
5425e490
TW		 920 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
921 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 922 if (priv->cfg->mod_params->amsdu_size_8K)
5425e490 923 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
9ee1ba47 924 else
5425e490
TW		 925 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
926 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
927 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
928 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822 929
099b40b7
RR		 930 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
931 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
932 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
933 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
934
ec35cf2a
TW		 935 priv->hw_params.tx_chains_num = 2;
936 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 937 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
938 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 939 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
940
f0832f13 941 priv->hw_params.sens = &iwl4965_sensitivity;
3e82a822 942
059ff826 943 return 0;
b481de9c
ZY		 944}
945
5da4b55f
MA		 946/* set card power command */
947static int iwl4965_set_power(struct iwl_priv *priv,
948 void *cmd)
949{
950 int ret = 0;
951
952 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
953 sizeof(struct iwl4965_powertable_cmd),
954 cmd, NULL);
955 return ret;
956}
b481de9c
ZY		 957
958static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
959{
960 s32 sign = 1;
961
962 if (num < 0) {
963 sign = -sign;
964 num = -num;
965 }
966 if (denom < 0) {
967 sign = -sign;
968 denom = -denom;
969 }
970 *res = 1;
971 *res = ((num * 2 + denom) / (denom * 2)) * sign;
972
973 return 1;
974}
975
8b6eaea8
CB		 976/**
977 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
978 *
979 * Determines power supply voltage compensation for txpower calculations.
980 * Returns number of 1/2-dB steps to subtract from gain table index,
981 * to compensate for difference between power supply voltage during
982 * factory measurements, vs. current power supply voltage.
983 *
984 * Voltage indication is higher for lower voltage.
985 * Lower voltage requires more gain (lower gain table index).
986 */
b481de9c
ZY		 987static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
988 s32 current_voltage)
989{
990 s32 comp = 0;
991
992 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
993 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
994 return 0;
995
996 iwl4965_math_div_round(current_voltage - eeprom_voltage,
997 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
998
999 if (current_voltage > eeprom_voltage)
1000 comp *= 2;
1001 if ((comp < -2) || (comp > 2))
1002 comp = 0;
1003
1004 return comp;
1005}
1006
b481de9c
ZY		 1007static s32 iwl4965_get_tx_atten_grp(u16 channel)
1008{
1009 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1010 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1011 return CALIB_CH_GROUP_5;
1012
1013 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1014 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1015 return CALIB_CH_GROUP_1;
1016
1017 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1018 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1019 return CALIB_CH_GROUP_2;
1020
1021 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1022 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1023 return CALIB_CH_GROUP_3;
1024
1025 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1026 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1027 return CALIB_CH_GROUP_4;
1028
1029 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1030 return -1;
1031}
1032
c79dd5b5 1033static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 1034{
1035 s32 b = -1;
1036
1037 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 1038 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 1039 continue;
1040
073d3f5f
TW		 1041 if ((channel >= priv->calib_info->band_info[b].ch_from)
1042 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 1043 break;
1044 }
1045
1046 return b;
1047}
1048
1049static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1050{
1051 s32 val;
1052
1053 if (x2 == x1)
1054 return y1;
1055 else {
1056 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1057 return val + y2;
1058 }
1059}
1060
8b6eaea8
CB		 1061/**
1062 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1063 *
1064 * Interpolates factory measurements from the two sample channels within a
1065 * sub-band, to apply to channel of interest. Interpolation is proportional to
1066 * differences in channel frequencies, which is proportional to differences
1067 * in channel number.
1068 */
c79dd5b5 1069static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 1070 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 1071{
1072 s32 s = -1;
1073 u32 c;
1074 u32 m;
073d3f5f
TW		 1075 const struct iwl_eeprom_calib_measure *m1;
1076 const struct iwl_eeprom_calib_measure *m2;
1077 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 1078 u32 ch_i1;
1079 u32 ch_i2;
1080
1081 s = iwl4965_get_sub_band(priv, channel);
1082 if (s >= EEPROM_TX_POWER_BANDS) {
1083 IWL_ERROR("Tx Power can not find channel %d ", channel);
1084 return -1;
1085 }
1086
073d3f5f
TW		 1087 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1088 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 1089 chan_info->ch_num = (u8) channel;
1090
1091 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1092 channel, s, ch_i1, ch_i2);
1093
1094 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1095 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 1096 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 1097 measurements[c][m]);
073d3f5f 1098 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 1099 measurements[c][m]);
1100 omeas = &(chan_info->measurements[c][m]);
1101
1102 omeas->actual_pow =
1103 (u8) iwl4965_interpolate_value(channel, ch_i1,
1104 m1->actual_pow,
1105 ch_i2,
1106 m2->actual_pow);
1107 omeas->gain_idx =
1108 (u8) iwl4965_interpolate_value(channel, ch_i1,
1109 m1->gain_idx, ch_i2,
1110 m2->gain_idx);
1111 omeas->temperature =
1112 (u8) iwl4965_interpolate_value(channel, ch_i1,
1113 m1->temperature,
1114 ch_i2,
1115 m2->temperature);
1116 omeas->pa_det =
1117 (s8) iwl4965_interpolate_value(channel, ch_i1,
1118 m1->pa_det, ch_i2,
1119 m2->pa_det);
1120
1121 IWL_DEBUG_TXPOWER
1122 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1123 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1124 IWL_DEBUG_TXPOWER
1125 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1126 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1127 IWL_DEBUG_TXPOWER
1128 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1129 m1->pa_det, m2->pa_det, omeas->pa_det);
1130 IWL_DEBUG_TXPOWER
1131 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1132 m1->temperature, m2->temperature,
1133 omeas->temperature);
1134 }
1135 }
1136
1137 return 0;
1138}
1139
1140/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1141 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1142static s32 back_off_table[] = {
1143 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1144 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1145 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1146 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1147 10 /* CCK */
1148};
1149
1150/* Thermal compensation values for txpower for various frequency ranges ...
1151 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1152static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1153 s32 degrees_per_05db_a;
1154 s32 degrees_per_05db_a_denom;
1155} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1156 {9, 2}, /* group 0 5.2, ch 34-43 */
1157 {4, 1}, /* group 1 5.2, ch 44-70 */
1158 {4, 1}, /* group 2 5.2, ch 71-124 */
1159 {4, 1}, /* group 3 5.2, ch 125-200 */
1160 {3, 1} /* group 4 2.4, ch all */
1161};
1162
1163static s32 get_min_power_index(s32 rate_power_index, u32 band)
1164{
1165 if (!band) {
1166 if ((rate_power_index & 7) <= 4)
1167 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1168 }
1169 return MIN_TX_GAIN_INDEX;
1170}
1171
1172struct gain_entry {
1173 u8 dsp;
1174 u8 radio;
1175};
1176
1177static const struct gain_entry gain_table[2][108] = {
1178 /* 5.2GHz power gain index table */
1179 {
1180 {123, 0x3F}, /* highest txpower */
1181 {117, 0x3F},
1182 {110, 0x3F},
1183 {104, 0x3F},
1184 {98, 0x3F},
1185 {110, 0x3E},
1186 {104, 0x3E},
1187 {98, 0x3E},
1188 {110, 0x3D},
1189 {104, 0x3D},
1190 {98, 0x3D},
1191 {110, 0x3C},
1192 {104, 0x3C},
1193 {98, 0x3C},
1194 {110, 0x3B},
1195 {104, 0x3B},
1196 {98, 0x3B},
1197 {110, 0x3A},
1198 {104, 0x3A},
1199 {98, 0x3A},
1200 {110, 0x39},
1201 {104, 0x39},
1202 {98, 0x39},
1203 {110, 0x38},
1204 {104, 0x38},
1205 {98, 0x38},
1206 {110, 0x37},
1207 {104, 0x37},
1208 {98, 0x37},
1209 {110, 0x36},
1210 {104, 0x36},
1211 {98, 0x36},
1212 {110, 0x35},
1213 {104, 0x35},
1214 {98, 0x35},
1215 {110, 0x34},
1216 {104, 0x34},
1217 {98, 0x34},
1218 {110, 0x33},
1219 {104, 0x33},
1220 {98, 0x33},
1221 {110, 0x32},
1222 {104, 0x32},
1223 {98, 0x32},
1224 {110, 0x31},
1225 {104, 0x31},
1226 {98, 0x31},
1227 {110, 0x30},
1228 {104, 0x30},
1229 {98, 0x30},
1230 {110, 0x25},
1231 {104, 0x25},
1232 {98, 0x25},
1233 {110, 0x24},
1234 {104, 0x24},
1235 {98, 0x24},
1236 {110, 0x23},
1237 {104, 0x23},
1238 {98, 0x23},
1239 {110, 0x22},
1240 {104, 0x18},
1241 {98, 0x18},
1242 {110, 0x17},
1243 {104, 0x17},
1244 {98, 0x17},
1245 {110, 0x16},
1246 {104, 0x16},
1247 {98, 0x16},
1248 {110, 0x15},
1249 {104, 0x15},
1250 {98, 0x15},
1251 {110, 0x14},
1252 {104, 0x14},
1253 {98, 0x14},
1254 {110, 0x13},
1255 {104, 0x13},
1256 {98, 0x13},
1257 {110, 0x12},
1258 {104, 0x08},
1259 {98, 0x08},
1260 {110, 0x07},
1261 {104, 0x07},
1262 {98, 0x07},
1263 {110, 0x06},
1264 {104, 0x06},
1265 {98, 0x06},
1266 {110, 0x05},
1267 {104, 0x05},
1268 {98, 0x05},
1269 {110, 0x04},
1270 {104, 0x04},
1271 {98, 0x04},
1272 {110, 0x03},
1273 {104, 0x03},
1274 {98, 0x03},
1275 {110, 0x02},
1276 {104, 0x02},
1277 {98, 0x02},
1278 {110, 0x01},
1279 {104, 0x01},
1280 {98, 0x01},
1281 {110, 0x00},
1282 {104, 0x00},
1283 {98, 0x00},
1284 {93, 0x00},
1285 {88, 0x00},
1286 {83, 0x00},
1287 {78, 0x00},
1288 },
1289 /* 2.4GHz power gain index table */
1290 {
1291 {110, 0x3f}, /* highest txpower */
1292 {104, 0x3f},
1293 {98, 0x3f},
1294 {110, 0x3e},
1295 {104, 0x3e},
1296 {98, 0x3e},
1297 {110, 0x3d},
1298 {104, 0x3d},
1299 {98, 0x3d},
1300 {110, 0x3c},
1301 {104, 0x3c},
1302 {98, 0x3c},
1303 {110, 0x3b},
1304 {104, 0x3b},
1305 {98, 0x3b},
1306 {110, 0x3a},
1307 {104, 0x3a},
1308 {98, 0x3a},
1309 {110, 0x39},
1310 {104, 0x39},
1311 {98, 0x39},
1312 {110, 0x38},
1313 {104, 0x38},
1314 {98, 0x38},
1315 {110, 0x37},
1316 {104, 0x37},
1317 {98, 0x37},
1318 {110, 0x36},
1319 {104, 0x36},
1320 {98, 0x36},
1321 {110, 0x35},
1322 {104, 0x35},
1323 {98, 0x35},
1324 {110, 0x34},
1325 {104, 0x34},
1326 {98, 0x34},
1327 {110, 0x33},
1328 {104, 0x33},
1329 {98, 0x33},
1330 {110, 0x32},
1331 {104, 0x32},
1332 {98, 0x32},
1333 {110, 0x31},
1334 {104, 0x31},
1335 {98, 0x31},
1336 {110, 0x30},
1337 {104, 0x30},
1338 {98, 0x30},
1339 {110, 0x6},
1340 {104, 0x6},
1341 {98, 0x6},
1342 {110, 0x5},
1343 {104, 0x5},
1344 {98, 0x5},
1345 {110, 0x4},
1346 {104, 0x4},
1347 {98, 0x4},
1348 {110, 0x3},
1349 {104, 0x3},
1350 {98, 0x3},
1351 {110, 0x2},
1352 {104, 0x2},
1353 {98, 0x2},
1354 {110, 0x1},
1355 {104, 0x1},
1356 {98, 0x1},
1357 {110, 0x0},
1358 {104, 0x0},
1359 {98, 0x0},
1360 {97, 0},
1361 {96, 0},
1362 {95, 0},
1363 {94, 0},
1364 {93, 0},
1365 {92, 0},
1366 {91, 0},
1367 {90, 0},
1368 {89, 0},
1369 {88, 0},
1370 {87, 0},
1371 {86, 0},
1372 {85, 0},
1373 {84, 0},
1374 {83, 0},
1375 {82, 0},
1376 {81, 0},
1377 {80, 0},
1378 {79, 0},
1379 {78, 0},
1380 {77, 0},
1381 {76, 0},
1382 {75, 0},
1383 {74, 0},
1384 {73, 0},
1385 {72, 0},
1386 {71, 0},
1387 {70, 0},
1388 {69, 0},
1389 {68, 0},
1390 {67, 0},
1391 {66, 0},
1392 {65, 0},
1393 {64, 0},
1394 {63, 0},
1395 {62, 0},
1396 {61, 0},
1397 {60, 0},
1398 {59, 0},
1399 }
1400};
1401
c79dd5b5 1402static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1403 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1404 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1405{
1406 u8 saturation_power;
1407 s32 target_power;
1408 s32 user_target_power;
1409 s32 power_limit;
1410 s32 current_temp;
1411 s32 reg_limit;
1412 s32 current_regulatory;
1413 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1414 int i;
1415 int c;
bf85ea4f 1416 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1417 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1418 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1419 s16 voltage;
1420 s32 init_voltage;
1421 s32 voltage_compensation;
1422 s32 degrees_per_05db_num;
1423 s32 degrees_per_05db_denom;
1424 s32 factory_temp;
1425 s32 temperature_comp[2];
1426 s32 factory_gain_index[2];
1427 s32 factory_actual_pwr[2];
1428 s32 power_index;
1429
b481de9c
ZY		 1430 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1431 * are used for indexing into txpower table) */
630fe9b6 1432 user_target_power = 2 * priv->tx_power_user_lmt;
b481de9c
ZY		 1433
1434 /* Get current (RXON) channel, band, width */
b481de9c
ZY		 1435 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1436 is_fat);
1437
630fe9b6
TW		 1438 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1439
1440 if (!is_channel_valid(ch_info))
b481de9c
ZY		 1441 return -EINVAL;
1442
1443 /* get txatten group, used to select 1) thermal txpower adjustment
1444 * and 2) mimo txpower balance between Tx chains. */
1445 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1446 if (txatten_grp < 0)
1447 return -EINVAL;
1448
1449 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1450 channel, txatten_grp);
1451
1452 if (is_fat) {
1453 if (ctrl_chan_high)
1454 channel -= 2;
1455 else
1456 channel += 2;
1457 }
1458
1459 /* hardware txpower limits ...
1460 * saturation (clipping distortion) txpowers are in half-dBm */
1461 if (band)
073d3f5f 1462 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1463 else
073d3f5f 1464 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1465
1466 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1467 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1468 if (band)
1469 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1470 else
1471 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1472 }
1473
1474 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1475 * max_power_avg values are in dBm, convert * 2 */
1476 if (is_fat)
1477 reg_limit = ch_info->fat_max_power_avg * 2;
1478 else
1479 reg_limit = ch_info->max_power_avg * 2;
1480
1481 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1482 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1483 if (band)
1484 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1485 else
1486 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1487 }
1488
1489 /* Interpolate txpower calibration values for this channel,
1490 * based on factory calibration tests on spaced channels. */
1491 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1492
1493 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 1494 voltage = priv->calib_info->voltage;
b481de9c
ZY		 1495 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1496 voltage_compensation =
1497 iwl4965_get_voltage_compensation(voltage, init_voltage);
1498
1499 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1500 init_voltage,
1501 voltage, voltage_compensation);
1502
1503 /* get current temperature (Celsius) */
1504 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1505 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1506 current_temp = KELVIN_TO_CELSIUS(current_temp);
1507
1508 /* select thermal txpower adjustment params, based on channel group
1509 * (same frequency group used for mimo txatten adjustment) */
1510 degrees_per_05db_num =
1511 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1512 degrees_per_05db_denom =
1513 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1514
1515 /* get per-chain txpower values from factory measurements */
1516 for (c = 0; c < 2; c++) {
1517 measurement = &ch_eeprom_info.measurements[c][1];
1518
1519 /* txgain adjustment (in half-dB steps) based on difference
1520 * between factory and current temperature */
1521 factory_temp = measurement->temperature;
1522 iwl4965_math_div_round((current_temp - factory_temp) *
1523 degrees_per_05db_denom,
1524 degrees_per_05db_num,
1525 &temperature_comp[c]);
1526
1527 factory_gain_index[c] = measurement->gain_idx;
1528 factory_actual_pwr[c] = measurement->actual_pow;
1529
1530 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1531 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1532 "curr tmp %d, comp %d steps\n",
1533 factory_temp, current_temp,
1534 temperature_comp[c]);
1535
1536 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1537 factory_gain_index[c],
1538 factory_actual_pwr[c]);
1539 }
1540
1541 /* for each of 33 bit-rates (including 1 for CCK) */
1542 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1543 u8 is_mimo_rate;
bb8c093b 1544 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 1545
1546 /* for mimo, reduce each chain's txpower by half
1547 * (3dB, 6 steps), so total output power is regulatory
1548 * compliant. */
1549 if (i & 0x8) {
1550 current_regulatory = reg_limit -
1551 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1552 is_mimo_rate = 1;
1553 } else {
1554 current_regulatory = reg_limit;
1555 is_mimo_rate = 0;
1556 }
1557
1558 /* find txpower limit, either hardware or regulatory */
1559 power_limit = saturation_power - back_off_table[i];
1560 if (power_limit > current_regulatory)
1561 power_limit = current_regulatory;
1562
1563 /* reduce user's txpower request if necessary
1564 * for this rate on this channel */
1565 target_power = user_target_power;
1566 if (target_power > power_limit)
1567 target_power = power_limit;
1568
1569 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1570 i, saturation_power - back_off_table[i],
1571 current_regulatory, user_target_power,
1572 target_power);
1573
1574 /* for each of 2 Tx chains (radio transmitters) */
1575 for (c = 0; c < 2; c++) {
1576 s32 atten_value;
1577
1578 if (is_mimo_rate)
1579 atten_value =
1580 (s32)le32_to_cpu(priv->card_alive_init.
1581 tx_atten[txatten_grp][c]);
1582 else
1583 atten_value = 0;
1584
1585 /* calculate index; higher index means lower txpower */
1586 power_index = (u8) (factory_gain_index[c] -
1587 (target_power -
1588 factory_actual_pwr[c]) -
1589 temperature_comp[c] -
1590 voltage_compensation +
1591 atten_value);
1592
1593/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1594 power_index); */
1595
1596 if (power_index < get_min_power_index(i, band))
1597 power_index = get_min_power_index(i, band);
1598
1599 /* adjust 5 GHz index to support negative indexes */
1600 if (!band)
1601 power_index += 9;
1602
1603 /* CCK, rate 32, reduce txpower for CCK */
1604 if (i == POWER_TABLE_CCK_ENTRY)
1605 power_index +=
1606 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1607
1608 /* stay within the table! */
1609 if (power_index > 107) {
1610 IWL_WARNING("txpower index %d > 107\n",
1611 power_index);
1612 power_index = 107;
1613 }
1614 if (power_index < 0) {
1615 IWL_WARNING("txpower index %d < 0\n",
1616 power_index);
1617 power_index = 0;
1618 }
1619
1620 /* fill txpower command for this rate/chain */
1621 tx_power.s.radio_tx_gain[c] =
1622 gain_table[band][power_index].radio;
1623 tx_power.s.dsp_predis_atten[c] =
1624 gain_table[band][power_index].dsp;
1625
1626 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1627 "gain 0x%02x dsp %d\n",
1628 c, atten_value, power_index,
1629 tx_power.s.radio_tx_gain[c],
1630 tx_power.s.dsp_predis_atten[c]);
1631 }/* for each chain */
1632
1633 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1634
1635 }/* for each rate */
1636
1637 return 0;
1638}
1639
1640/**
630fe9b6 1641 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
b481de9c
ZY		 1642 *
1643 * Uses the active RXON for channel, band, and characteristics (fat, high)
630fe9b6 1644 * The power limit is taken from priv->tx_power_user_lmt.
b481de9c 1645 */
630fe9b6 1646static int iwl4965_send_tx_power(struct iwl_priv *priv)
b481de9c 1647{
bb8c093b 1648 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 1649 int ret;
b481de9c
ZY		 1650 u8 band = 0;
1651 u8 is_fat = 0;
1652 u8 ctrl_chan_high = 0;
1653
1654 if (test_bit(STATUS_SCANNING, &priv->status)) {
1655 /* If this gets hit a lot, switch it to a BUG() and catch
1656 * the stack trace to find out who is calling this during
1657 * a scan. */
1658 IWL_WARNING("TX Power requested while scanning!\n");
1659 return -EAGAIN;
1660 }
1661
8318d78a 1662 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 1663
1664 is_fat = is_fat_channel(priv->active_rxon.flags);
1665
1666 if (is_fat &&
1667 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1668 ctrl_chan_high = 1;
1669
1670 cmd.band = band;
1671 cmd.channel = priv->active_rxon.channel;
1672
857485c0 1673 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 1674 le16_to_cpu(priv->active_rxon.channel),
1675 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 1676 if (ret)
1677 goto out;
b481de9c 1678
857485c0
TW		 1679 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1680
1681out:
1682 return ret;
b481de9c
ZY		 1683}
1684
7e8c519e
TW		 1685static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1686{
1687 int ret = 0;
1688 struct iwl4965_rxon_assoc_cmd rxon_assoc;
c1adf9fb
GG		 1689 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1690 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
7e8c519e
TW		 1691
1692 if ((rxon1->flags == rxon2->flags) &&
1693 (rxon1->filter_flags == rxon2->filter_flags) &&
1694 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1695 (rxon1->ofdm_ht_single_stream_basic_rates ==
1696 rxon2->ofdm_ht_single_stream_basic_rates) &&
1697 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1698 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1699 (rxon1->rx_chain == rxon2->rx_chain) &&
1700 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1701 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1702 return 0;
1703 }
1704
1705 rxon_assoc.flags = priv->staging_rxon.flags;
1706 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1707 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1708 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1709 rxon_assoc.reserved = 0;
1710 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1711 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1712 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1713 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1714 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1715
1716 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1717 sizeof(rxon_assoc), &rxon_assoc, NULL);
1718 if (ret)
1719 return ret;
1720
1721 return ret;
1722}
1723
1724
c79dd5b5 1725int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1726{
1727 int rc;
1728 u8 band = 0;
1729 u8 is_fat = 0;
1730 u8 ctrl_chan_high = 0;
bb8c093b 1731 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 1732 const struct iwl_channel_info *ch_info;
b481de9c 1733
8318d78a 1734 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 1735
8622e705 1736 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 1737
1738 is_fat = is_fat_channel(priv->staging_rxon.flags);
1739
1740 if (is_fat &&
1741 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1742 ctrl_chan_high = 1;
1743
1744 cmd.band = band;
1745 cmd.expect_beacon = 0;
1746 cmd.channel = cpu_to_le16(channel);
1747 cmd.rxon_flags = priv->active_rxon.flags;
1748 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1749 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1750 if (ch_info)
1751 cmd.expect_beacon = is_channel_radar(ch_info);
1752 else
1753 cmd.expect_beacon = 1;
1754
1755 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
1756 ctrl_chan_high, &cmd.tx_power);
1757 if (rc) {
1758 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
1759 return rc;
1760 }
1761
857485c0 1762 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 1763 return rc;
1764}
1765
d67f5489 1766static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
b481de9c 1767{
059ff826
TW		 1768 struct iwl4965_shared *s = priv->shared_virt;
1769 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 1770}
1771
c79dd5b5 1772int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 1773{
1774 return priv->temperature;
1775}
1776
c79dd5b5 1777unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
fcab423d 1778 struct iwl_frame *frame, u8 rate)
b481de9c 1779{
bb8c093b 1780 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 1781 unsigned int frame_size;
1782
1783 tx_beacon_cmd = &frame->u.beacon;
1784 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
1785
5425e490 1786 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 1787 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1788
bb8c093b 1789 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 1790 tx_beacon_cmd->frame,
57bd1bea 1791 iwl_bcast_addr,
b481de9c
ZY		 1792 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
1793
1794 BUG_ON(frame_size > MAX_MPDU_SIZE);
1795 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
1796
1797 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
1798 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 1799 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 1800 else
1801 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 1802 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 1803
1804 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
1805 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
1806 return (sizeof(*tx_beacon_cmd) + frame_size);
1807}
1808
399f4900
RR		 1809static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
1810{
1811 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
1812 sizeof(struct iwl4965_shared),
1813 &priv->shared_phys);
1814 if (!priv->shared_virt)
1815 return -ENOMEM;
1816
1817 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
1818
d67f5489
RR		 1819 priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
1820
399f4900
RR		 1821 return 0;
1822}
1823
1824static void iwl4965_free_shared_mem(struct iwl_priv *priv)
1825{
1826 if (priv->shared_virt)
1827 pci_free_consistent(priv->pci_dev,
1828 sizeof(struct iwl4965_shared),
1829 priv->shared_virt,
1830 priv->shared_phys);
1831}
1832
8b6eaea8 1833/**
e2a722eb 1834 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 1835 */
e2a722eb 1836static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 1837 struct iwl_tx_queue *txq,
e2a722eb 1838 u16 byte_cnt)
b481de9c
ZY		 1839{
1840 int len;
1841 int txq_id = txq->q.id;
059ff826 1842 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 1843
b481de9c
ZY		 1844 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1845
8b6eaea8 1846 /* Set up byte count within first 256 entries */
b481de9c 1847 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 1848 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 1849
8b6eaea8 1850 /* If within first 64 entries, duplicate at end */
038669e4 1851 if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
b481de9c 1852 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
038669e4 1853 tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 1854 byte_cnt, len);
b481de9c
ZY		 1855}
1856
b481de9c
ZY		 1857/**
1858 * sign_extend - Sign extend a value using specified bit as sign-bit
1859 *
1860 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1861 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1862 *
1863 * @param oper value to sign extend
1864 * @param index 0 based bit index (0<=index<32) to sign bit
1865 */
1866static s32 sign_extend(u32 oper, int index)
1867{
1868 u8 shift = 31 - index;
1869
1870 return (s32)(oper << shift) >> shift;
1871}
1872
1873/**
1874 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
1875 * @statistics: Provides the temperature reading from the uCode
1876 *
1877 * A return of <0 indicates bogus data in the statistics
1878 */
c79dd5b5 1879int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 1880{
1881 s32 temperature;
1882 s32 vt;
1883 s32 R1, R2, R3;
1884 u32 R4;
1885
1886 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1887 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
1888 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
1889 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1890 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1891 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1892 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1893 } else {
1894 IWL_DEBUG_TEMP("Running temperature calibration\n");
1895 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1896 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1897 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1898 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1899 }
1900
1901 /*
8b6eaea8 1902 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 1903 *
1904 * NOTE If we haven't received a statistics notification yet
1905 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 1906 * "initialize" ALIVE response.
1907 */
b481de9c
ZY		 1908 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1909 vt = sign_extend(R4, 23);
1910 else
1911 vt = sign_extend(
1912 le32_to_cpu(priv->statistics.general.temperature), 23);
1913
1914 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
1915 R1, R2, R3, vt);
1916
1917 if (R3 == R1) {
1918 IWL_ERROR("Calibration conflict R1 == R3\n");
1919 return -1;
1920 }
1921
1922 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1923 * Add offset to center the adjustment around 0 degrees Centigrade. */
1924 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1925 temperature /= (R3 - R1);
1926 temperature = (temperature * 97) / 100 +
1927 TEMPERATURE_CALIB_KELVIN_OFFSET;
1928
1929 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
1930 KELVIN_TO_CELSIUS(temperature));
1931
1932 return temperature;
1933}
1934
1935/* Adjust Txpower only if temperature variance is greater than threshold. */
1936#define IWL_TEMPERATURE_THRESHOLD 3
1937
1938/**
1939 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1940 *
1941 * If the temperature changed has changed sufficiently, then a recalibration
1942 * is needed.
1943 *
1944 * Assumes caller will replace priv->last_temperature once calibration
1945 * executed.
1946 */
c79dd5b5 1947static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1948{
1949 int temp_diff;
1950
1951 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1952 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
1953 return 0;
1954 }
1955
1956 temp_diff = priv->temperature - priv->last_temperature;
1957
1958 /* get absolute value */
1959 if (temp_diff < 0) {
1960 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
1961 temp_diff = -temp_diff;
1962 } else if (temp_diff == 0)
1963 IWL_DEBUG_POWER("Same temp, \n");
1964 else
1965 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
1966
1967 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1968 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
1969 return 0;
1970 }
1971
1972 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
1973
1974 return 1;
1975}
1976
1977/* Calculate noise level, based on measurements during network silence just
1978 * before arriving beacon. This measurement can be done only if we know
1979 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 1980static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 1981{
1982 struct statistics_rx_non_phy *rx_info
1983 = &(priv->statistics.rx.general);
1984 int num_active_rx = 0;
1985 int total_silence = 0;
1986 int bcn_silence_a =
1987 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
1988 int bcn_silence_b =
1989 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
1990 int bcn_silence_c =
1991 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
1992
1993 if (bcn_silence_a) {
1994 total_silence += bcn_silence_a;
1995 num_active_rx++;
1996 }
1997 if (bcn_silence_b) {
1998 total_silence += bcn_silence_b;
1999 num_active_rx++;
2000 }
2001 if (bcn_silence_c) {
2002 total_silence += bcn_silence_c;
2003 num_active_rx++;
2004 }
2005
2006 /* Average among active antennas */
2007 if (num_active_rx)
2008 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2009 else
2010 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2011
2012 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2013 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2014 priv->last_rx_noise);
2015}
2016
a55360e4
TW		 2017void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
2018 struct iwl_rx_mem_buffer *rxb)
b481de9c 2019{
db11d634 2020 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 2021 int change;
2022 s32 temp;
2023
2024 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2025 (int)sizeof(priv->statistics), pkt->len);
2026
2027 change = ((priv->statistics.general.temperature !=
2028 pkt->u.stats.general.temperature) ||
2029 ((priv->statistics.flag &
2030 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2031 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2032
2033 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2034
2035 set_bit(STATUS_STATISTICS, &priv->status);
2036
2037 /* Reschedule the statistics timer to occur in
2038 * REG_RECALIB_PERIOD seconds to ensure we get a
2039 * thermal update even if the uCode doesn't give
2040 * us one */
2041 mod_timer(&priv->statistics_periodic, jiffies +
2042 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2043
2044 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2045 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2046 iwl4965_rx_calc_noise(priv);
16e727e8 2047 queue_work(priv->workqueue, &priv->run_time_calib_work);
b481de9c
ZY		 2048 }
2049
ab53d8af
MA		 2050 iwl_leds_background(priv);
2051
b481de9c
ZY		 2052 /* If the hardware hasn't reported a change in
2053 * temperature then don't bother computing a
2054 * calibrated temperature value */
2055 if (!change)
2056 return;
2057
2058 temp = iwl4965_get_temperature(priv);
2059 if (temp < 0)
2060 return;
2061
2062 if (priv->temperature != temp) {
2063 if (priv->temperature)
2064 IWL_DEBUG_TEMP("Temperature changed "
2065 "from %dC to %dC\n",
2066 KELVIN_TO_CELSIUS(priv->temperature),
2067 KELVIN_TO_CELSIUS(temp));
2068 else
2069 IWL_DEBUG_TEMP("Temperature "
2070 "initialized to %dC\n",
2071 KELVIN_TO_CELSIUS(temp));
2072 }
2073
2074 priv->temperature = temp;
2075 set_bit(STATUS_TEMPERATURE, &priv->status);
2076
203566f3
EG		 2077 if (!priv->disable_tx_power_cal &&
2078 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2079 iwl4965_is_temp_calib_needed(priv))
b481de9c
ZY		 2080 queue_work(priv->workqueue, &priv->txpower_work);
2081}
2082
c79dd5b5 2083static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 2084 struct sk_buff *skb,
2085 struct iwl4965_rx_phy_res *rx_start,
2086 struct ieee80211_rx_status *stats,
2087 u32 ampdu_status)
2088{
566bfe5a 2089 s8 signal = stats->signal;
12342c47 2090 s8 noise = 0;
8318d78a 2091 int rate = stats->rate_idx;
12342c47 2092 u64 tsf = stats->mactime;
a0b484fe 2093 __le16 antenna;
12342c47
ZY		 2094 __le16 phy_flags_hw = rx_start->phy_flags;
2095 struct iwl4965_rt_rx_hdr {
2096 struct ieee80211_radiotap_header rt_hdr;
2097 __le64 rt_tsf; /* TSF */
2098 u8 rt_flags; /* radiotap packet flags */
2099 u8 rt_rate; /* rate in 500kb/s */
2100 __le16 rt_channelMHz; /* channel in MHz */
2101 __le16 rt_chbitmask; /* channel bitfield */
2102 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2103 s8 rt_dbmnoise;
2104 u8 rt_antenna; /* antenna number */
2105 } __attribute__ ((packed)) *iwl4965_rt;
2106
2107 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2108 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2109 if (net_ratelimit())
2110 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 2111 "radiotap head [%zd]\n",
12342c47
ZY		 2112 skb_headroom(skb), sizeof(*iwl4965_rt));
2113 return;
2114 }
2115
2116 /* put radiotap header in front of 802.11 header and data */
2117 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2118
2119 /* initialise radiotap header */
2120 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2121 iwl4965_rt->rt_hdr.it_pad = 0;
2122
2123 /* total header + data */
2124 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2125 &iwl4965_rt->rt_hdr.it_len);
2126
2127 /* Indicate all the fields we add to the radiotap header */
2128 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2129 (1 << IEEE80211_RADIOTAP_FLAGS) |
2130 (1 << IEEE80211_RADIOTAP_RATE) |
2131 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2132 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2133 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2134 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2135 &iwl4965_rt->rt_hdr.it_present);
2136
2137 /* Zero the flags, we'll add to them as we go */
2138 iwl4965_rt->rt_flags = 0;
2139
2140 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2141
2142 iwl4965_rt->rt_dbmsignal = signal;
2143 iwl4965_rt->rt_dbmnoise = noise;
2144
2145 /* Convert the channel frequency and set the flags */
2146 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2147 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2148 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2149 IEEE80211_CHAN_5GHZ),
2150 &iwl4965_rt->rt_chbitmask);
2151 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2152 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2153 IEEE80211_CHAN_2GHZ),
2154 &iwl4965_rt->rt_chbitmask);
2155 else /* 802.11g */
2156 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2157 IEEE80211_CHAN_2GHZ),
2158 &iwl4965_rt->rt_chbitmask);
2159
12342c47
ZY		 2160 if (rate == -1)
2161 iwl4965_rt->rt_rate = 0;
2162 else
1826dcc0 2163 iwl4965_rt->rt_rate = iwl_rates[rate].ieee;
12342c47
ZY		 2164
2165 /*
2166 * "antenna number"
2167 *
2168 * It seems that the antenna field in the phy flags value
2169 * is actually a bitfield. This is undefined by radiotap,
2170 * it wants an actual antenna number but I always get "7"
2171 * for most legacy frames I receive indicating that the
2172 * same frame was received on all three RX chains.
2173 *
2174 * I think this field should be removed in favour of a
2175 * new 802.11n radiotap field "RX chains" that is defined
2176 * as a bitmask.
2177 */
a0b484fe
JB		 2178 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2179 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 2180
2181 /* set the preamble flag if appropriate */
2182 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2183 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2184
2185 stats->flag |= RX_FLAG_RADIOTAP;
2186}
2187
19758bef
TW		 2188static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2189{
2190 /* 0 - mgmt, 1 - cnt, 2 - data */
2191 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2192 priv->rx_stats[idx].cnt++;
2193 priv->rx_stats[idx].bytes += len;
2194}
2195
3ec47732
EG		 2196/*
2197 * returns non-zero if packet should be dropped
2198 */
2199static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2200 struct ieee80211_hdr *hdr,
2201 u32 decrypt_res,
2202 struct ieee80211_rx_status *stats)
2203{
2204 u16 fc = le16_to_cpu(hdr->frame_control);
2205
2206 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2207 return 0;
2208
2209 if (!(fc & IEEE80211_FCTL_PROTECTED))
2210 return 0;
2211
2212 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2213 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2214 case RX_RES_STATUS_SEC_TYPE_TKIP:
2215 /* The uCode has got a bad phase 1 Key, pushes the packet.
2216 * Decryption will be done in SW. */
2217 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2218 RX_RES_STATUS_BAD_KEY_TTAK)
2219 break;
2220
ccc038ab 2221 case RX_RES_STATUS_SEC_TYPE_WEP:
3ec47732
EG		 2222 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2223 RX_RES_STATUS_BAD_ICV_MIC) {
2224 /* bad ICV, the packet is destroyed since the
2225 * decryption is inplace, drop it */
2226 IWL_DEBUG_RX("Packet destroyed\n");
2227 return -1;
2228 }
3ec47732
EG		 2229 case RX_RES_STATUS_SEC_TYPE_CCMP:
2230 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2231 RX_RES_STATUS_DECRYPT_OK) {
2232 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2233 stats->flag |= RX_FLAG_DECRYPTED;
2234 }
2235 break;
2236
2237 default:
2238 break;
2239 }
2240 return 0;
2241}
2242
bf403db8 2243static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
17e476b8
EG		 2244{
2245 u32 decrypt_out = 0;
2246
2247 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2248 RX_RES_STATUS_STATION_FOUND)
2249 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2250 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2251
2252 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2253
2254 /* packet was not encrypted */
2255 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2256 RX_RES_STATUS_SEC_TYPE_NONE)
2257 return decrypt_out;
2258
2259 /* packet was encrypted with unknown alg */
2260 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2261 RX_RES_STATUS_SEC_TYPE_ERR)
2262 return decrypt_out;
2263
2264 /* decryption was not done in HW */
2265 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2266 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2267 return decrypt_out;
2268
2269 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2270
2271 case RX_RES_STATUS_SEC_TYPE_CCMP:
2272 /* alg is CCM: check MIC only */
2273 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2274 /* Bad MIC */
2275 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2276 else
2277 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2278
2279 break;
2280
2281 case RX_RES_STATUS_SEC_TYPE_TKIP:
2282 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2283 /* Bad TTAK */
2284 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2285 break;
2286 }
2287 /* fall through if TTAK OK */
2288 default:
2289 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2290 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2291 else
2292 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2293 break;
2294 };
2295
2296 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2297 decrypt_in, decrypt_out);
2298
2299 return decrypt_out;
2300}
2301
c79dd5b5 2302static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 2303 int include_phy,
a55360e4 2304 struct iwl_rx_mem_buffer *rxb,
b481de9c
ZY		 2305 struct ieee80211_rx_status *stats)
2306{
db11d634 2307 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 2308 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2309 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2310 struct ieee80211_hdr *hdr;
2311 u16 len;
2312 __le32 *rx_end;
2313 unsigned int skblen;
2314 u32 ampdu_status;
17e476b8 2315 u32 ampdu_status_legacy;
b481de9c
ZY		 2316
2317 if (!include_phy && priv->last_phy_res[0])
2318 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2319
2320 if (!rx_start) {
2321 IWL_ERROR("MPDU frame without a PHY data\n");
2322 return;
2323 }
2324 if (include_phy) {
2325 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
2326 rx_start->cfg_phy_cnt);
2327
2328 len = le16_to_cpu(rx_start->byte_count);
2329
2330 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
2331 sizeof(struct iwl4965_rx_phy_res) +
2332 rx_start->cfg_phy_cnt + len);
2333
2334 } else {
2335 struct iwl4965_rx_mpdu_res_start *amsdu =
2336 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2337
2338 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
2339 sizeof(struct iwl4965_rx_mpdu_res_start));
2340 len = le16_to_cpu(amsdu->byte_count);
2341 rx_start->byte_count = amsdu->byte_count;
2342 rx_end = (__le32 *) (((u8 *) hdr) + len);
2343 }
4419e39b
AK		 2344 /* In monitor mode allow 802.11 ACk frames (10 bytes) */
2345 if (len > priv->hw_params.max_pkt_size ||
2346 len < ((priv->iw_mode == IEEE80211_IF_TYPE_MNTR) ? 10 : 16)) {
12342c47 2347 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 2348 return;
2349 }
2350
2351 ampdu_status = le32_to_cpu(*rx_end);
2352 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
2353
17e476b8
EG		 2354 if (!include_phy) {
2355 /* New status scheme, need to translate */
2356 ampdu_status_legacy = ampdu_status;
bf403db8 2357 ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
17e476b8
EG		 2358 }
2359
b481de9c
ZY		 2360 /* start from MAC */
2361 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
2362 skb_put(rxb->skb, len); /* end where data ends */
2363
2364 /* We only process data packets if the interface is open */
2365 if (unlikely(!priv->is_open)) {
2366 IWL_DEBUG_DROP_LIMIT
2367 ("Dropping packet while interface is not open.\n");
2368 return;
2369 }
2370
b481de9c
ZY		 2371 stats->flag = 0;
2372 hdr = (struct ieee80211_hdr *)rxb->skb->data;
2373
3ec47732 2374 /* in case of HW accelerated crypto and bad decryption, drop */
099b40b7 2375 if (!priv->hw_params.sw_crypto &&
3ec47732
EG		 2376 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
2377 return;
b481de9c 2378
12342c47
ZY		 2379 if (priv->add_radiotap)
2380 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
2381
19758bef 2382 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 2383 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
2384 priv->alloc_rxb_skb--;
2385 rxb->skb = NULL;
b481de9c
ZY		 2386}
2387
2388/* Calc max signal level (dBm) among 3 possible receivers */
bf403db8
EK		 2389static int iwl4965_calc_rssi(struct iwl_priv *priv,
2390 struct iwl4965_rx_phy_res *rx_resp)
b481de9c
ZY		 2391{
2392 /* data from PHY/DSP regarding signal strength, etc.,
2393 * contents are always there, not configurable by host. */
2394 struct iwl4965_rx_non_cfg_phy *ncphy =
2395 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
2396 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
2397 >> IWL_AGC_DB_POS;
2398
2399 u32 valid_antennae =
2400 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
2401 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
2402 u8 max_rssi = 0;
2403 u32 i;
2404
2405 /* Find max rssi among 3 possible receivers.
2406 * These values are measured by the digital signal processor (DSP).
2407 * They should stay fairly constant even as the signal strength varies,
2408 * if the radio's automatic gain control (AGC) is working right.
2409 * AGC value (see below) will provide the "interesting" info. */
2410 for (i = 0; i < 3; i++)
2411 if (valid_antennae & (1 << i))
2412 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2413
2414 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2415 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2416 max_rssi, agc);
2417
2418 /* dBm = max_rssi dB - agc dB - constant.
2419 * Higher AGC (higher radio gain) means lower signal. */
2420 return (max_rssi - agc - IWL_RSSI_OFFSET);
2421}
2422
c79dd5b5 2423static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 2424{
2425 unsigned long flags;
2426
2427 spin_lock_irqsave(&priv->sta_lock, flags);
2428 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
2429 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
2430 priv->stations[sta_id].sta.sta.modify_mask = 0;
2431 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2432 spin_unlock_irqrestore(&priv->sta_lock, flags);
2433
133636de 2434 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 2435}
2436
c79dd5b5 2437static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 2438{
2439 /* FIXME: need locking over ps_status ??? */
947b13a7 2440 u8 sta_id = iwl_find_station(priv, addr);
b481de9c
ZY		 2441
2442 if (sta_id != IWL_INVALID_STATION) {
2443 u8 sta_awake = priv->stations[sta_id].
2444 ps_status == STA_PS_STATUS_WAKE;
2445
2446 if (sta_awake && ps_bit)
2447 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
2448 else if (!sta_awake && !ps_bit) {
2449 iwl4965_sta_modify_ps_wake(priv, sta_id);
2450 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
2451 }
2452 }
2453}
0a6857e7 2454#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 2455
2456/**
2457 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
2458 *
2459 * You may hack this function to show different aspects of received frames,
2460 * including selective frame dumps.
2461 * group100 parameter selects whether to show 1 out of 100 good frames.
2462 *
2463 * TODO: This was originally written for 3945, need to audit for
2464 * proper operation with 4965.
2465 */
c79dd5b5 2466static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
db11d634 2467 struct iwl_rx_packet *pkt,
17744ff6
TW		 2468 struct ieee80211_hdr *header, int group100)
2469{
2470 u32 to_us;
2471 u32 print_summary = 0;
2472 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
2473 u32 hundred = 0;
2474 u32 dataframe = 0;
2475 u16 fc;
2476 u16 seq_ctl;
2477 u16 channel;
2478 u16 phy_flags;
2479 int rate_sym;
2480 u16 length;
2481 u16 status;
2482 u16 bcn_tmr;
2483 u32 tsf_low;
2484 u64 tsf;
2485 u8 rssi;
2486 u8 agc;
2487 u16 sig_avg;
2488 u16 noise_diff;
2489 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
2490 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
2491 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
2492 u8 *data = IWL_RX_DATA(pkt);
2493
bf403db8 2494 if (likely(!(priv->debug_level & IWL_DL_RX)))
17744ff6
TW		 2495 return;
2496
2497 /* MAC header */
2498 fc = le16_to_cpu(header->frame_control);
2499 seq_ctl = le16_to_cpu(header->seq_ctrl);
2500
2501 /* metadata */
2502 channel = le16_to_cpu(rx_hdr->channel);
2503 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
2504 rate_sym = rx_hdr->rate;
2505 length = le16_to_cpu(rx_hdr->len);
2506
2507 /* end-of-frame status and timestamp */
2508 status = le32_to_cpu(rx_end->status);
2509 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
2510 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
2511 tsf = le64_to_cpu(rx_end->timestamp);
2512
2513 /* signal statistics */
2514 rssi = rx_stats->rssi;
2515 agc = rx_stats->agc;
2516 sig_avg = le16_to_cpu(rx_stats->sig_avg);
2517 noise_diff = le16_to_cpu(rx_stats->noise_diff);
2518
2519 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
2520
2521 /* if data frame is to us and all is good,
2522 * (optionally) print summary for only 1 out of every 100 */
2523 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
2524 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
2525 dataframe = 1;
2526 if (!group100)
2527 print_summary = 1; /* print each frame */
2528 else if (priv->framecnt_to_us < 100) {
2529 priv->framecnt_to_us++;
2530 print_summary = 0;
2531 } else {
2532 priv->framecnt_to_us = 0;
2533 print_summary = 1;
2534 hundred = 1;
2535 }
2536 } else {
2537 /* print summary for all other frames */
2538 print_summary = 1;
2539 }
2540
2541 if (print_summary) {
2542 char *title;
2543 int rate_idx;
2544 u32 bitrate;
2545
2546 if (hundred)
2547 title = "100Frames";
2548 else if (fc & IEEE80211_FCTL_RETRY)
2549 title = "Retry";
2550 else if (ieee80211_is_assoc_response(fc))
2551 title = "AscRsp";
2552 else if (ieee80211_is_reassoc_response(fc))
2553 title = "RasRsp";
2554 else if (ieee80211_is_probe_response(fc)) {
2555 title = "PrbRsp";
2556 print_dump = 1; /* dump frame contents */
2557 } else if (ieee80211_is_beacon(fc)) {
2558 title = "Beacon";
2559 print_dump = 1; /* dump frame contents */
2560 } else if (ieee80211_is_atim(fc))
2561 title = "ATIM";
2562 else if (ieee80211_is_auth(fc))
2563 title = "Auth";
2564 else if (ieee80211_is_deauth(fc))
2565 title = "DeAuth";
2566 else if (ieee80211_is_disassoc(fc))
2567 title = "DisAssoc";
2568 else
2569 title = "Frame";
2570
2571 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
2572 if (unlikely(rate_idx == -1))
2573 bitrate = 0;
2574 else
1826dcc0 2575 bitrate = iwl_rates[rate_idx].ieee / 2;
17744ff6
TW		 2576
2577 /* print frame summary.
2578 * MAC addresses show just the last byte (for brevity),
2579 * but you can hack it to show more, if you'd like to. */
2580 if (dataframe)
2581 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
2582 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
2583 title, fc, header->addr1[5],
2584 length, rssi, channel, bitrate);
2585 else {
2586 /* src/dst addresses assume managed mode */
2587 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
2588 "src=0x%02x, rssi=%u, tim=%lu usec, "
2589 "phy=0x%02x, chnl=%d\n",
2590 title, fc, header->addr1[5],
2591 header->addr3[5], rssi,
2592 tsf_low - priv->scan_start_tsf,
2593 phy_flags, channel);
2594 }
2595 }
2596 if (print_dump)
bf403db8 2597 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6
TW		 2598}
2599#else
c79dd5b5 2600static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
db11d634 2601 struct iwl_rx_packet *pkt,
17744ff6
TW		 2602 struct ieee80211_hdr *header,
2603 int group100)
2604{
2605}
2606#endif
2607
b481de9c 2608
7878a5a4 2609
857485c0 2610/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 2611 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
37a44211 2612void iwl4965_rx_reply_rx(struct iwl_priv *priv,
a55360e4 2613 struct iwl_rx_mem_buffer *rxb)
b481de9c 2614{
17744ff6
TW		 2615 struct ieee80211_hdr *header;
2616 struct ieee80211_rx_status rx_status;
db11d634 2617 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 2618 /* Use phy data (Rx signal strength, etc.) contained within
2619 * this rx packet for legacy frames,
2620 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 2621 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 2622 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2623 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
2624 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2625 __le32 *rx_end;
2626 unsigned int len = 0;
b481de9c 2627 u16 fc;
b481de9c
ZY		 2628 u8 network_packet;
2629
17744ff6 2630 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
dc92e497 2631 rx_status.freq =
c0186078 2632 ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
17744ff6
TW		 2633 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
2634 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
dc92e497
TW		 2635 rx_status.rate_idx =
2636 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
17744ff6
TW		 2637 if (rx_status.band == IEEE80211_BAND_5GHZ)
2638 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
2639
2640 rx_status.antenna = 0;
2641 rx_status.flag = 0;
2642
b481de9c 2643 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
dc92e497
TW		 2644 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
2645 rx_start->cfg_phy_cnt);
b481de9c
ZY		 2646 return;
2647 }
17744ff6 2648
b481de9c
ZY		 2649 if (!include_phy) {
2650 if (priv->last_phy_res[0])
2651 rx_start = (struct iwl4965_rx_phy_res *)
2652 &priv->last_phy_res[1];
2653 else
2654 rx_start = NULL;
2655 }
2656
2657 if (!rx_start) {
2658 IWL_ERROR("MPDU frame without a PHY data\n");
2659 return;
2660 }
2661
2662 if (include_phy) {
2663 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
2664 + rx_start->cfg_phy_cnt);
2665
2666 len = le16_to_cpu(rx_start->byte_count);
17744ff6 2667 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 2668 sizeof(struct iwl4965_rx_phy_res) + len);
2669 } else {
2670 struct iwl4965_rx_mpdu_res_start *amsdu =
2671 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2672
2673 header = (void *)(pkt->u.raw +
2674 sizeof(struct iwl4965_rx_mpdu_res_start));
2675 len = le16_to_cpu(amsdu->byte_count);
2676 rx_end = (__le32 *) (pkt->u.raw +
2677 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
2678 }
2679
2680 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
2681 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
2682 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
2683 le32_to_cpu(*rx_end));
2684 return;
2685 }
2686
2687 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
2688
b481de9c 2689 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
566bfe5a 2690 rx_status.signal = iwl4965_calc_rssi(priv, rx_start);
b481de9c
ZY		 2691
2692 /* Meaningful noise values are available only from beacon statistics,
2693 * which are gathered only when associated, and indicate noise
2694 * only for the associated network channel ...
2695 * Ignore these noise values while scanning (other channels) */
3109ece1 2696 if (iwl_is_associated(priv) &&
b481de9c 2697 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6 2698 rx_status.noise = priv->last_rx_noise;
566bfe5a 2699 rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal,
17744ff6 2700 rx_status.noise);
b481de9c 2701 } else {
17744ff6 2702 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
566bfe5a 2703 rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 2704 }
2705
2706 /* Reset beacon noise level if not associated. */
3109ece1 2707 if (!iwl_is_associated(priv))
b481de9c
ZY		 2708 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2709
17744ff6
TW		 2710 /* Set "1" to report good data frames in groups of 100 */
2711 /* FIXME: need to optimze the call: */
2712 iwl4965_dbg_report_frame(priv, pkt, header, 1);
2713
2714 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
566bfe5a 2715 rx_status.signal, rx_status.noise, rx_status.signal,
06501d29 2716 (unsigned long long)rx_status.mactime);
b481de9c 2717
4419e39b
AK		 2718
2719 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
2720 iwl4965_handle_data_packet(priv, 1, include_phy,
2721 rxb, &rx_status);
2722 return;
2723 }
2724
bb8c093b 2725 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 2726 if (network_packet) {
566bfe5a 2727 priv->last_rx_rssi = rx_status.signal;
b481de9c
ZY		 2728 priv->last_beacon_time = priv->ucode_beacon_time;
2729 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
2730 }
2731
2732 fc = le16_to_cpu(header->frame_control);
2733 switch (fc & IEEE80211_FCTL_FTYPE) {
2734 case IEEE80211_FTYPE_MGMT:
b481de9c
ZY		 2735 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
2736 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
2737 header->addr2);
17744ff6 2738 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 2739 break;
2740
2741 case IEEE80211_FTYPE_CTL:
b481de9c
ZY		 2742 switch (fc & IEEE80211_FCTL_STYPE) {
2743 case IEEE80211_STYPE_BACK_REQ:
2744 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
2745 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 2746 rxb, &rx_status);
b481de9c
ZY		 2747 break;
2748 default:
2749 break;
2750 }
b481de9c
ZY		 2751 break;
2752
0795af57
JP		 2753 case IEEE80211_FTYPE_DATA: {
2754 DECLARE_MAC_BUF(mac1);
2755 DECLARE_MAC_BUF(mac2);
2756 DECLARE_MAC_BUF(mac3);
2757
b481de9c
ZY		 2758 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
2759 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
2760 header->addr2);
2761
2762 if (unlikely(!network_packet))
2763 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 2764 "%s, %s, %s\n",
2765 print_mac(mac1, header->addr1),
2766 print_mac(mac2, header->addr2),
2767 print_mac(mac3, header->addr3));
bb8c093b 2768 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 2769 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
2770 print_mac(mac1, header->addr1),
2771 print_mac(mac2, header->addr2),
2772 print_mac(mac3, header->addr3));
b481de9c
ZY		 2773 else
2774 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 2775 &rx_status);
b481de9c 2776 break;
0795af57 2777 }
b481de9c
ZY		 2778 default:
2779 break;
2780
2781 }
2782}
2783
8b6eaea8
CB		 2784/**
2785 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2786 *
2787 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2788 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2789 */
c79dd5b5 2790static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
6def9761 2791 struct iwl_ht_agg *agg,
bb8c093b 2792 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 2793 ba_resp)
2794
2795{
2796 int i, sh, ack;
fe01b477
RR		 2797 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2798 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2799 u64 bitmap;
2800 int successes = 0;
e039fa4a 2801 struct ieee80211_tx_info *info;
b481de9c
ZY		 2802
2803 if (unlikely(!agg->wait_for_ba)) {
2804 IWL_ERROR("Received BA when not expected\n");
2805 return -EINVAL;
2806 }
8b6eaea8
CB		 2807
2808 /* Mark that the expected block-ack response arrived */
b481de9c 2809 agg->wait_for_ba = 0;
fe01b477 2810 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 2811
2812 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 2813 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 2814 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 2815 sh += 0x100;
2816
8b6eaea8 2817 /* don't use 64-bit values for now */
fe01b477 2818 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 2819
2820 if (agg->frame_count > (64 - sh)) {
2821 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
2822 return -1;
2823 }
2824
2825 /* check for success or failure according to the
8b6eaea8 2826 * transmitted bitmap and block-ack bitmap */
fe01b477 2827 bitmap &= agg->bitmap;
b481de9c 2828
8b6eaea8
CB		 2829 /* For each frame attempted in aggregation,
2830 * update driver's record of tx frame's status. */
b481de9c 2831 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 2832 ack = bitmap & (1 << i);
2833 successes += !!ack;
b481de9c 2834 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 2835 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
2836 agg->start_idx + i);
2837 }
2838
e039fa4a
JB		 2839 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
2840 memset(&info->status, 0, sizeof(info->status));
2841 info->flags = IEEE80211_TX_STAT_ACK;
2842 info->flags |= IEEE80211_TX_STAT_AMPDU;
2843 info->status.ampdu_ack_map = successes;
2844 info->status.ampdu_ack_len = agg->frame_count;
2845 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
fe01b477 2846
f868f4e1 2847 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 2848
2849 return 0;
2850}
2851
2852/**
2853 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2854 */
c79dd5b5 2855static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 2856 u16 txq_id)
2857{
2858 /* Simply stop the queue, but don't change any configuration;
2859 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 2860 iwl_write_prph(priv,
12a81f60 2861 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 2862 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
2863 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
fe01b477 2864}
b481de9c 2865
fe01b477 2866/**
7f3e4bb6 2867 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
b095d03a 2868 * priv->lock must be held by the caller
fe01b477 2869 */
30e553e3
TW		 2870static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
2871 u16 ssn_idx, u8 tx_fifo)
fe01b477 2872{
b095d03a
RR		 2873 int ret = 0;
2874
7f3e4bb6 2875 if (IWL49_FIRST_AMPDU_QUEUE > txq_id) {
fe01b477 2876 IWL_WARNING("queue number too small: %d, must be > %d\n",
7f3e4bb6 2877 txq_id, IWL49_FIRST_AMPDU_QUEUE);
fe01b477 2878 return -EINVAL;
b481de9c
ZY		 2879 }
2880
3395f6e9 2881 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 2882 if (ret)
2883 return ret;
2884
fe01b477
RR		 2885 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
2886
12a81f60 2887 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 2888
2889 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2890 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2891 /* supposes that ssn_idx is valid (!= 0xFFF) */
2892 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
2893
12a81f60 2894 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
36470749 2895 iwl_txq_ctx_deactivate(priv, txq_id);
fe01b477
RR		 2896 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
2897
3395f6e9 2898 iwl_release_nic_access(priv);
b095d03a 2899
fe01b477
RR		 2900 return 0;
2901}
b481de9c 2902
b481de9c 2903
8b6eaea8
CB		 2904/**
2905 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
2906 *
2907 * Handles block-acknowledge notification from device, which reports success
2908 * of frames sent via aggregation.
2909 */
c79dd5b5 2910static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
a55360e4 2911 struct iwl_rx_mem_buffer *rxb)
b481de9c 2912{
db11d634 2913 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
bb8c093b 2914 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 2915 int index;
16466903 2916 struct iwl_tx_queue *txq = NULL;
6def9761 2917 struct iwl_ht_agg *agg;
fe01b477 2918 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 2919
2920 /* "flow" corresponds to Tx queue */
fe01b477 2921 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 2922
2923 /* "ssn" is start of block-ack Tx window, corresponds to index
2924 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 2925 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2926
dfe7d458 2927 if (scd_flow >= priv->hw_params.max_txq_num) {
b481de9c
ZY		 2928 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
2929 return;
2930 }
2931
fe01b477 2932 txq = &priv->txq[scd_flow];
b481de9c 2933 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 2934
2935 /* Find index just before block-ack window */
443cfd45 2936 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 2937
01ebd063 2938 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 2939
0795af57
JP		 2940 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
2941 "sta_id = %d\n",
b481de9c 2942 agg->wait_for_ba,
0795af57 2943 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 2944 ba_resp->sta_id);
fe01b477 2945 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 2946 "%d, scd_ssn = %d\n",
2947 ba_resp->tid,
fe01b477 2948 ba_resp->seq_ctl,
0310ae72 2949 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 2950 ba_resp->scd_flow,
2951 ba_resp->scd_ssn);
fe01b477 2952 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 2953 agg->start_idx,
f868f4e1 2954 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 2955
2956 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 2957 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 2958
2959 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2960 * block-ack window (we assume that they've been successfully
2961 * transmitted ... if not, it's too late anyway). */
fe01b477 2962 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
0d0b2c1c
RR		 2963 /* calculate mac80211 ampdu sw queue to wake */
2964 int ampdu_q =
7f3e4bb6 2965 scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
17b88929 2966 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
fe01b477
RR		 2967 priv->stations[ba_resp->sta_id].
2968 tid[ba_resp->tid].tfds_in_queue -= freed;
443cfd45 2969 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
fe01b477
RR		 2970 priv->mac80211_registered &&
2971 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
0d0b2c1c 2972 ieee80211_wake_queue(priv->hw, ampdu_q);
30e553e3
TW		 2973
2974 iwl_txq_check_empty(priv, ba_resp->sta_id,
2975 ba_resp->tid, scd_flow);
fe01b477 2976 }
b481de9c
ZY		 2977}
2978
8b6eaea8
CB		 2979/**
2980 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2981 */
c79dd5b5 2982static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 2983 u16 txq_id)
2984{
2985 u32 tbl_dw_addr;
2986 u32 tbl_dw;
2987 u16 scd_q2ratid;
2988
30e553e3 2989 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
b481de9c
ZY		 2990
2991 tbl_dw_addr = priv->scd_base_addr +
038669e4 2992 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
b481de9c 2993
3395f6e9 2994 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 2995
2996 if (txq_id & 0x1)
2997 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2998 else
2999 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3000
3395f6e9 3001 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 3002
3003 return 0;
3004}
3005
fe01b477 3006
b481de9c 3007/**
8b6eaea8
CB		 3008 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3009 *
7f3e4bb6 3010 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
8b6eaea8 3011 * i.e. it must be one of the higher queues used for aggregation
b481de9c 3012 */
30e553e3
TW		 3013static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
3014 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
b481de9c
ZY		 3015{
3016 unsigned long flags;
30e553e3 3017 int ret;
b481de9c
ZY		 3018 u16 ra_tid;
3019
7f3e4bb6 3020 if (IWL49_FIRST_AMPDU_QUEUE > txq_id)
b481de9c 3021 IWL_WARNING("queue number too small: %d, must be > %d\n",
7f3e4bb6 3022 txq_id, IWL49_FIRST_AMPDU_QUEUE);
b481de9c
ZY		 3023
3024 ra_tid = BUILD_RAxTID(sta_id, tid);
3025
8b6eaea8 3026 /* Modify device's station table to Tx this TID */
5083e563 3027 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 3028
3029 spin_lock_irqsave(&priv->lock, flags);
30e553e3
TW		 3030 ret = iwl_grab_nic_access(priv);
3031 if (ret) {
b481de9c 3032 spin_unlock_irqrestore(&priv->lock, flags);
30e553e3 3033 return ret;
b481de9c
ZY		 3034 }
3035
8b6eaea8 3036 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 3037 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3038
8b6eaea8 3039 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 3040 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3041
8b6eaea8 3042 /* Set this queue as a chain-building queue */
12a81f60 3043 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 3044
8b6eaea8
CB		 3045 /* Place first TFD at index corresponding to start sequence number.
3046 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 3047 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3048 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 3049 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3050
8b6eaea8 3051 /* Set up Tx window size and frame limit for this queue */
3395f6e9 3052 iwl_write_targ_mem(priv,
038669e4
EG		 3053 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3054 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3055 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
b481de9c 3056
3395f6e9 3057 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 3058 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3059 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3060 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c 3061
12a81f60 3062 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 3063
8b6eaea8 3064 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 3065 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3066
3395f6e9 3067 iwl_release_nic_access(priv);
b481de9c
ZY		 3068 spin_unlock_irqrestore(&priv->lock, flags);
3069
3070 return 0;
3071}
3072
fe07aa7a
RR		 3073static int iwl4965_rx_agg_start(struct iwl_priv *priv,
3074 const u8 *addr, int tid, u16 ssn)
b481de9c
ZY		 3075{
3076 unsigned long flags;
fe07aa7a
RR		 3077 int sta_id;
3078
3079 sta_id = iwl_find_station(priv, addr);
3080 if (sta_id == IWL_INVALID_STATION)
3081 return -ENXIO;
b481de9c
ZY		 3082
3083 spin_lock_irqsave(&priv->sta_lock, flags);
3084 priv->stations[sta_id].sta.station_flags_msk = 0;
3085 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3086 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
3087 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3088 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3089 spin_unlock_irqrestore(&priv->sta_lock, flags);
3090
133636de 3091 return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
fe07aa7a 3092 CMD_ASYNC);
b481de9c
ZY		 3093}
3094
fe07aa7a
RR		 3095static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
3096 const u8 *addr, int tid)
b481de9c
ZY		 3097{
3098 unsigned long flags;
fe07aa7a
RR		 3099 int sta_id;
3100
3101 sta_id = iwl_find_station(priv, addr);
3102 if (sta_id == IWL_INVALID_STATION)
3103 return -ENXIO;
b481de9c
ZY		 3104
3105 spin_lock_irqsave(&priv->sta_lock, flags);
3106 priv->stations[sta_id].sta.station_flags_msk = 0;
3107 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3108 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
3109 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3110 spin_unlock_irqrestore(&priv->sta_lock, flags);
3111
133636de 3112 return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
fe07aa7a 3113 CMD_ASYNC);
b481de9c
ZY		 3114}
3115
8114fcf1
RR		 3116int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
3117 enum ieee80211_ampdu_mlme_action action,
3118 const u8 *addr, u16 tid, u16 *ssn)
3119{
c79dd5b5 3120 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 3121 DECLARE_MAC_BUF(mac);
3122
fe07aa7a
RR		 3123 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
3124 print_mac(mac, addr), tid);
3125
8114fcf1
RR		 3126 switch (action) {
3127 case IEEE80211_AMPDU_RX_START:
3128 IWL_DEBUG_HT("start Rx\n");
fe07aa7a 3129 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
8114fcf1
RR		 3130 case IEEE80211_AMPDU_RX_STOP:
3131 IWL_DEBUG_HT("stop Rx\n");
fe07aa7a 3132 return iwl4965_rx_agg_stop(priv, addr, tid);
8114fcf1
RR		 3133 case IEEE80211_AMPDU_TX_START:
3134 IWL_DEBUG_HT("start Tx\n");
30e553e3 3135 return iwl_tx_agg_start(priv, addr, tid, ssn);
8114fcf1
RR		 3136 case IEEE80211_AMPDU_TX_STOP:
3137 IWL_DEBUG_HT("stop Tx\n");
30e553e3 3138 return iwl_tx_agg_stop(priv, addr, tid);
8114fcf1
RR		 3139 default:
3140 IWL_DEBUG_HT("unknown\n");
3141 return -EINVAL;
3142 break;
3143 }
3144 return 0;
3145}
133636de 3146
c1adf9fb
GG		 3147static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
3148{
3149 switch (cmd_id) {
3150 case REPLY_RXON:
3151 return (u16) sizeof(struct iwl4965_rxon_cmd);
3152 default:
3153 return len;
3154 }
3155}
3156
133636de
TW		 3157static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
3158{
3159 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
3160 addsta->mode = cmd->mode;
3161 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
3162 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
3163 addsta->station_flags = cmd->station_flags;
3164 addsta->station_flags_msk = cmd->station_flags_msk;
3165 addsta->tid_disable_tx = cmd->tid_disable_tx;
3166 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
3167 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
3168 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
3169 addsta->reserved1 = __constant_cpu_to_le16(0);
3170 addsta->reserved2 = __constant_cpu_to_le32(0);
3171
3172 return (u16)sizeof(struct iwl4965_addsta_cmd);
3173}
f20217d9 3174
f20217d9
TW		 3175static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
3176{
25a6572c 3177 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
f20217d9
TW		 3178}
3179
3180/**
3181 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
3182 */
3183static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
3184 struct iwl_ht_agg *agg,
25a6572c
TW		 3185 struct iwl4965_tx_resp *tx_resp,
3186 int txq_id, u16 start_idx)
f20217d9
TW		 3187{
3188 u16 status;
25a6572c 3189 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
f20217d9
TW		 3190 struct ieee80211_tx_info *info = NULL;
3191 struct ieee80211_hdr *hdr = NULL;
25a6572c 3192 int i, sh, idx;
f20217d9
TW		 3193 u16 seq;
3194
3195 if (agg->wait_for_ba)
3196 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
3197
3198 agg->frame_count = tx_resp->frame_count;
3199 agg->start_idx = start_idx;
3200 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
3201 agg->bitmap = 0;
3202
3203 /* # frames attempted by Tx command */
3204 if (agg->frame_count == 1) {
3205 /* Only one frame was attempted; no block-ack will arrive */
3206 status = le16_to_cpu(frame_status[0].status);
25a6572c 3207 idx = start_idx;
f20217d9
TW		 3208
3209 /* FIXME: code repetition */
3210 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
3211 agg->frame_count, agg->start_idx, idx);
3212
3213 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
3214 info->status.retry_count = tx_resp->failure_frame;
3215 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
3216 info->flags |= iwl_is_tx_success(status)?
3217 IEEE80211_TX_STAT_ACK : 0;
3218 iwl4965_hwrate_to_tx_control(priv,
3219 le32_to_cpu(tx_resp->rate_n_flags),
3220 info);
3221 /* FIXME: code repetition end */
3222
3223 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
3224 status & 0xff, tx_resp->failure_frame);
3225 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n",
3226 iwl4965_hw_get_rate_n_flags(tx_resp->rate_n_flags));
3227
3228 agg->wait_for_ba = 0;
3229 } else {
3230 /* Two or more frames were attempted; expect block-ack */
3231 u64 bitmap = 0;
3232 int start = agg->start_idx;
3233
3234 /* Construct bit-map of pending frames within Tx window */
3235 for (i = 0; i < agg->frame_count; i++) {
3236 u16 sc;
3237 status = le16_to_cpu(frame_status[i].status);
3238 seq = le16_to_cpu(frame_status[i].sequence);
3239 idx = SEQ_TO_INDEX(seq);
3240 txq_id = SEQ_TO_QUEUE(seq);
3241
3242 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
3243 AGG_TX_STATE_ABORT_MSK))
3244 continue;
3245
3246 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
3247 agg->frame_count, txq_id, idx);
3248
3249 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
3250
3251 sc = le16_to_cpu(hdr->seq_ctrl);
3252 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
3253 IWL_ERROR("BUG_ON idx doesn't match seq control"
3254 " idx=%d, seq_idx=%d, seq=%d\n",
3255 idx, SEQ_TO_SN(sc),
3256 hdr->seq_ctrl);
3257 return -1;
3258 }
3259
3260 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
3261 i, idx, SEQ_TO_SN(sc));
3262
3263 sh = idx - start;
3264 if (sh > 64) {
3265 sh = (start - idx) + 0xff;
3266 bitmap = bitmap << sh;
3267 sh = 0;
3268 start = idx;
3269 } else if (sh < -64)
3270 sh = 0xff - (start - idx);
3271 else if (sh < 0) {
3272 sh = start - idx;
3273 start = idx;
3274 bitmap = bitmap << sh;
3275 sh = 0;
3276 }
3277 bitmap |= (1 << sh);
3278 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
3279 start, (u32)(bitmap & 0xFFFFFFFF));
3280 }
3281
3282 agg->bitmap = bitmap;
3283 agg->start_idx = start;
3284 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
3285 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
3286 agg->frame_count, agg->start_idx,
3287 (unsigned long long)agg->bitmap);
3288
3289 if (bitmap)
3290 agg->wait_for_ba = 1;
3291 }
3292 return 0;
3293}
f20217d9
TW		 3294
3295/**
3296 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
3297 */
3298static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
3299 struct iwl_rx_mem_buffer *rxb)
3300{
3301 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3302 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3303 int txq_id = SEQ_TO_QUEUE(sequence);
3304 int index = SEQ_TO_INDEX(sequence);
3305 struct iwl_tx_queue *txq = &priv->txq[txq_id];
3306 struct ieee80211_tx_info *info;
3307 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
25a6572c 3308 u32 status = le32_to_cpu(tx_resp->u.status);
f20217d9
TW		 3309 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
3310 u16 fc;
3311 struct ieee80211_hdr *hdr;
3312 u8 *qc = NULL;
f20217d9
TW		 3313
3314 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
3315 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3316 "is out of range [0-%d] %d %d\n", txq_id,
3317 index, txq->q.n_bd, txq->q.write_ptr,
3318 txq->q.read_ptr);
3319 return;
3320 }
3321
3322 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
3323 memset(&info->status, 0, sizeof(info->status));
3324
f20217d9
TW		 3325 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
3326 fc = le16_to_cpu(hdr->frame_control);
3327 if (ieee80211_is_qos_data(fc)) {
3328 qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
3329 tid = qc[0] & 0xf;
3330 }
3331
3332 sta_id = iwl_get_ra_sta_id(priv, hdr);
3333 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
3334 IWL_ERROR("Station not known\n");
3335 return;
3336 }
3337
3338 if (txq->sched_retry) {
3339 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
3340 struct iwl_ht_agg *agg = NULL;
3341
3342 if (!qc)
3343 return;
3344
3345 agg = &priv->stations[sta_id].tid[tid].agg;
3346
25a6572c 3347 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
f20217d9
TW		 3348
3349 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) {
3350 /* TODO: send BAR */
3351 }
3352
3353 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
3354 int freed, ampdu_q;
3355 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
3356 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
3357 "%d index %d\n", scd_ssn , index);
17b88929 3358 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
f20217d9
TW		 3359 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3360
3361 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
3362 txq_id >= 0 && priv->mac80211_registered &&
3363 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
3364 /* calculate mac80211 ampdu sw queue to wake */
7f3e4bb6 3365 ampdu_q = txq_id - IWL49_FIRST_AMPDU_QUEUE +
f20217d9
TW		 3366 priv->hw->queues;
3367 if (agg->state == IWL_AGG_OFF)
3368 ieee80211_wake_queue(priv->hw, txq_id);
3369 else
3370 ieee80211_wake_queue(priv->hw, ampdu_q);
3371 }
30e553e3 3372 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
f20217d9
TW		 3373 }
3374 } else {
4f85f5b3
RR		 3375 info->status.retry_count = tx_resp->failure_frame;
3376 info->flags |=
3377 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
3378 iwl4965_hwrate_to_tx_control(priv,
3379 le32_to_cpu(tx_resp->rate_n_flags),
3380 info);
3381
3382 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
3383 "0x%x retries %d\n", txq_id,
3384 iwl_get_tx_fail_reason(status),
3385 status, le32_to_cpu(tx_resp->rate_n_flags),
3386 tx_resp->failure_frame);
3387
3388 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
3389 if (index != -1) {
3390 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
3391 if (tid != MAX_TID_COUNT)
f20217d9 3392 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
4f85f5b3 3393 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
f20217d9
TW		 3394 (txq_id >= 0) && priv->mac80211_registered)
3395 ieee80211_wake_queue(priv->hw, txq_id);
4f85f5b3 3396 if (tid != MAX_TID_COUNT)
30e553e3 3397 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
4f85f5b3 3398 }
f20217d9 3399 }
f20217d9
TW		 3400
3401 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3402 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3403}
3404
3405
b481de9c 3406/* Set up 4965-specific Rx frame reply handlers */
d4789efe 3407static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 3408{
3409 /* Legacy Rx frames */
857485c0 3410 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
37a44211 3411 /* Tx response */
f20217d9 3412 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
4f85f5b3 3413 /* block ack */
b481de9c 3414 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
b481de9c
ZY		 3415}
3416
4e39317d 3417static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 3418{
3419 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
b481de9c
ZY		 3420}
3421
4e39317d 3422static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3423{
4e39317d 3424 cancel_work_sync(&priv->txpower_work);
b481de9c
ZY		 3425}
3426
3c424c28
TW		 3427
3428static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 3429 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 3430};
3431
857485c0 3432static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
c1adf9fb 3433 .get_hcmd_size = iwl4965_get_hcmd_size,
133636de 3434 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
f0832f13
EG		 3435 .chain_noise_reset = iwl4965_chain_noise_reset,
3436 .gain_computation = iwl4965_gain_computation,
857485c0
TW		 3437};
3438
6bc913bd 3439static struct iwl_lib_ops iwl4965_lib = {
5425e490 3440 .set_hw_params = iwl4965_hw_set_hw_params,
399f4900
RR		 3441 .alloc_shared_mem = iwl4965_alloc_shared_mem,
3442 .free_shared_mem = iwl4965_free_shared_mem,
d67f5489 3443 .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
e2a722eb 3444 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
da1bc453 3445 .txq_set_sched = iwl4965_txq_set_sched,
30e553e3
TW		 3446 .txq_agg_enable = iwl4965_txq_agg_enable,
3447 .txq_agg_disable = iwl4965_txq_agg_disable,
d4789efe 3448 .rx_handler_setup = iwl4965_rx_handler_setup,
4e39317d
EG		 3449 .setup_deferred_work = iwl4965_setup_deferred_work,
3450 .cancel_deferred_work = iwl4965_cancel_deferred_work,
57aab75a
TW		 3451 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
3452 .alive_notify = iwl4965_alive_notify,
f3ccc08c 3453 .init_alive_start = iwl4965_init_alive_start,
57aab75a 3454 .load_ucode = iwl4965_load_bsm,
6f4083aa 3455 .apm_ops = {
91238714 3456 .init = iwl4965_apm_init,
7f066108 3457 .reset = iwl4965_apm_reset,
f118a91d 3458 .stop = iwl4965_apm_stop,
694cc56d 3459 .config = iwl4965_nic_config,
6f4083aa
TW		 3460 .set_pwr_src = iwl4965_set_pwr_src,
3461 },
6bc913bd 3462 .eeprom_ops = {
073d3f5f
TW		 3463 .regulatory_bands = {
3464 EEPROM_REGULATORY_BAND_1_CHANNELS,
3465 EEPROM_REGULATORY_BAND_2_CHANNELS,
3466 EEPROM_REGULATORY_BAND_3_CHANNELS,
3467 EEPROM_REGULATORY_BAND_4_CHANNELS,
3468 EEPROM_REGULATORY_BAND_5_CHANNELS,
3469 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
3470 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
3471 },
6bc913bd
AK		 3472 .verify_signature = iwlcore_eeprom_verify_signature,
3473 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
3474 .release_semaphore = iwlcore_eeprom_release_semaphore,
8614f360 3475 .check_version = iwl4965_eeprom_check_version,
073d3f5f 3476 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 3477 },
ad97edd2 3478 .radio_kill_sw = iwl4965_radio_kill_sw,
5da4b55f 3479 .set_power = iwl4965_set_power,
630fe9b6 3480 .send_tx_power = iwl4965_send_tx_power,
5da4b55f 3481 .update_chain_flags = iwl4965_update_chain_flags,
6bc913bd
AK		 3482};
3483
3484static struct iwl_ops iwl4965_ops = {
3485 .lib = &iwl4965_lib,
3c424c28 3486 .hcmd = &iwl4965_hcmd,
857485c0 3487 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 3488};
3489
fed9017e 3490struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 3491 .name = "4965AGN",
4bf775cd 3492 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 3493 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 3494 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
6bc913bd 3495 .ops = &iwl4965_ops,
1ea87396 3496 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 3497};
3498
1ea87396
AK		 3499module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
3500MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
3501module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
3502MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b
EG		 3503module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
3504MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
1ea87396
AK		 3505module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
3506MODULE_PARM_DESC(debug, "debug output mask");
3507module_param_named(
3508 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
3509MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
3510
3511module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
3512MODULE_PARM_DESC(queues_num, "number of hw queues.");
3513
3514/* QoS */
3515module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
3516MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
3517module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
3518MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
3a1081e8
EK		 3519module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
3520MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
Linux kernel - Deliverables
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