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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
eb7ae89c | 3 | * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
759ef89f | 22 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
24 | * | |
25 | *****************************************************************************/ | |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
b481de9c ZY |
29 | #include <linux/init.h> |
30 | #include <linux/pci.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/wireless.h> | |
36 | #include <net/mac80211.h> | |
b481de9c | 37 | #include <linux/etherdevice.h> |
12342c47 | 38 | #include <asm/unaligned.h> |
b481de9c | 39 | |
6bc913bd | 40 | #include "iwl-eeprom.h" |
3e0d4cb1 | 41 | #include "iwl-dev.h" |
fee1247a | 42 | #include "iwl-core.h" |
3395f6e9 | 43 | #include "iwl-io.h" |
b481de9c | 44 | #include "iwl-helpers.h" |
f0832f13 | 45 | #include "iwl-calib.h" |
5083e563 | 46 | #include "iwl-sta.h" |
b481de9c | 47 | |
630fe9b6 | 48 | static int iwl4965_send_tx_power(struct iwl_priv *priv); |
91dbc5bd | 49 | static int iwl4965_hw_get_temperature(const struct iwl_priv *priv); |
630fe9b6 | 50 | |
a0987a8d RC |
51 | /* Highest firmware API version supported */ |
52 | #define IWL4965_UCODE_API_MAX 2 | |
53 | ||
54 | /* Lowest firmware API version supported */ | |
55 | #define IWL4965_UCODE_API_MIN 2 | |
56 | ||
57 | #define IWL4965_FW_PRE "iwlwifi-4965-" | |
58 | #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode" | |
59 | #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api) | |
d16dc48a TW |
60 | |
61 | ||
1ea87396 AK |
62 | /* module parameters */ |
63 | static struct iwl_mod_params iwl4965_mod_params = { | |
038669e4 | 64 | .num_of_queues = IWL49_NUM_QUEUES, |
9f17b318 | 65 | .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES, |
1ea87396 | 66 | .amsdu_size_8K = 1, |
3a1081e8 | 67 | .restart_fw = 1, |
1ea87396 AK |
68 | /* the rest are 0 by default */ |
69 | }; | |
70 | ||
57aab75a TW |
71 | /* check contents of special bootstrap uCode SRAM */ |
72 | static int iwl4965_verify_bsm(struct iwl_priv *priv) | |
73 | { | |
74 | __le32 *image = priv->ucode_boot.v_addr; | |
75 | u32 len = priv->ucode_boot.len; | |
76 | u32 reg; | |
77 | u32 val; | |
78 | ||
79 | IWL_DEBUG_INFO("Begin verify bsm\n"); | |
80 | ||
81 | /* verify BSM SRAM contents */ | |
82 | val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG); | |
83 | for (reg = BSM_SRAM_LOWER_BOUND; | |
84 | reg < BSM_SRAM_LOWER_BOUND + len; | |
85 | reg += sizeof(u32), image++) { | |
86 | val = iwl_read_prph(priv, reg); | |
87 | if (val != le32_to_cpu(*image)) { | |
88 | IWL_ERROR("BSM uCode verification failed at " | |
89 | "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", | |
90 | BSM_SRAM_LOWER_BOUND, | |
91 | reg - BSM_SRAM_LOWER_BOUND, len, | |
92 | val, le32_to_cpu(*image)); | |
93 | return -EIO; | |
94 | } | |
95 | } | |
96 | ||
97 | IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n"); | |
98 | ||
99 | return 0; | |
100 | } | |
101 | ||
102 | /** | |
103 | * iwl4965_load_bsm - Load bootstrap instructions | |
104 | * | |
105 | * BSM operation: | |
106 | * | |
107 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
108 | * in special SRAM that does not power down during RFKILL. When powering back | |
109 | * up after power-saving sleeps (or during initial uCode load), the BSM loads | |
110 | * the bootstrap program into the on-board processor, and starts it. | |
111 | * | |
112 | * The bootstrap program loads (via DMA) instructions and data for a new | |
113 | * program from host DRAM locations indicated by the host driver in the | |
114 | * BSM_DRAM_* registers. Once the new program is loaded, it starts | |
115 | * automatically. | |
116 | * | |
117 | * When initializing the NIC, the host driver points the BSM to the | |
118 | * "initialize" uCode image. This uCode sets up some internal data, then | |
119 | * notifies host via "initialize alive" that it is complete. | |
120 | * | |
121 | * The host then replaces the BSM_DRAM_* pointer values to point to the | |
122 | * normal runtime uCode instructions and a backup uCode data cache buffer | |
123 | * (filled initially with starting data values for the on-board processor), | |
124 | * then triggers the "initialize" uCode to load and launch the runtime uCode, | |
125 | * which begins normal operation. | |
126 | * | |
127 | * When doing a power-save shutdown, runtime uCode saves data SRAM into | |
128 | * the backup data cache in DRAM before SRAM is powered down. | |
129 | * | |
130 | * When powering back up, the BSM loads the bootstrap program. This reloads | |
131 | * the runtime uCode instructions and the backup data cache into SRAM, | |
132 | * and re-launches the runtime uCode from where it left off. | |
133 | */ | |
134 | static int iwl4965_load_bsm(struct iwl_priv *priv) | |
135 | { | |
136 | __le32 *image = priv->ucode_boot.v_addr; | |
137 | u32 len = priv->ucode_boot.len; | |
138 | dma_addr_t pinst; | |
139 | dma_addr_t pdata; | |
140 | u32 inst_len; | |
141 | u32 data_len; | |
142 | int i; | |
143 | u32 done; | |
144 | u32 reg_offset; | |
145 | int ret; | |
146 | ||
147 | IWL_DEBUG_INFO("Begin load bsm\n"); | |
148 | ||
fe9b6b72 RR |
149 | priv->ucode_type = UCODE_RT; |
150 | ||
57aab75a TW |
151 | /* make sure bootstrap program is no larger than BSM's SRAM size */ |
152 | if (len > IWL_MAX_BSM_SIZE) | |
153 | return -EINVAL; | |
154 | ||
155 | /* Tell bootstrap uCode where to find the "Initialize" uCode | |
156 | * in host DRAM ... host DRAM physical address bits 35:4 for 4965. | |
2d87889f | 157 | * NOTE: iwl_init_alive_start() will replace these values, |
57aab75a | 158 | * after the "initialize" uCode has run, to point to |
2d87889f TW |
159 | * runtime/protocol instructions and backup data cache. |
160 | */ | |
57aab75a TW |
161 | pinst = priv->ucode_init.p_addr >> 4; |
162 | pdata = priv->ucode_init_data.p_addr >> 4; | |
163 | inst_len = priv->ucode_init.len; | |
164 | data_len = priv->ucode_init_data.len; | |
165 | ||
166 | ret = iwl_grab_nic_access(priv); | |
167 | if (ret) | |
168 | return ret; | |
169 | ||
170 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); | |
171 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
172 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | |
173 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); | |
174 | ||
175 | /* Fill BSM memory with bootstrap instructions */ | |
176 | for (reg_offset = BSM_SRAM_LOWER_BOUND; | |
177 | reg_offset < BSM_SRAM_LOWER_BOUND + len; | |
178 | reg_offset += sizeof(u32), image++) | |
179 | _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image)); | |
180 | ||
181 | ret = iwl4965_verify_bsm(priv); | |
182 | if (ret) { | |
183 | iwl_release_nic_access(priv); | |
184 | return ret; | |
185 | } | |
186 | ||
187 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | |
188 | iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); | |
189 | iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND); | |
190 | iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); | |
191 | ||
192 | /* Load bootstrap code into instruction SRAM now, | |
193 | * to prepare to load "initialize" uCode */ | |
194 | iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START); | |
195 | ||
196 | /* Wait for load of bootstrap uCode to finish */ | |
197 | for (i = 0; i < 100; i++) { | |
198 | done = iwl_read_prph(priv, BSM_WR_CTRL_REG); | |
199 | if (!(done & BSM_WR_CTRL_REG_BIT_START)) | |
200 | break; | |
201 | udelay(10); | |
202 | } | |
203 | if (i < 100) | |
204 | IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i); | |
205 | else { | |
206 | IWL_ERROR("BSM write did not complete!\n"); | |
207 | return -EIO; | |
208 | } | |
209 | ||
210 | /* Enable future boot loads whenever power management unit triggers it | |
211 | * (e.g. when powering back up after power-save shutdown) */ | |
212 | iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN); | |
213 | ||
214 | iwl_release_nic_access(priv); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
f3ccc08c EG |
219 | /** |
220 | * iwl4965_set_ucode_ptrs - Set uCode address location | |
221 | * | |
222 | * Tell initialization uCode where to find runtime uCode. | |
223 | * | |
224 | * BSM registers initially contain pointers to initialization uCode. | |
225 | * We need to replace them to load runtime uCode inst and data, | |
226 | * and to save runtime data when powering down. | |
227 | */ | |
228 | static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv) | |
229 | { | |
230 | dma_addr_t pinst; | |
231 | dma_addr_t pdata; | |
232 | unsigned long flags; | |
233 | int ret = 0; | |
234 | ||
235 | /* bits 35:4 for 4965 */ | |
236 | pinst = priv->ucode_code.p_addr >> 4; | |
237 | pdata = priv->ucode_data_backup.p_addr >> 4; | |
238 | ||
239 | spin_lock_irqsave(&priv->lock, flags); | |
240 | ret = iwl_grab_nic_access(priv); | |
241 | if (ret) { | |
242 | spin_unlock_irqrestore(&priv->lock, flags); | |
243 | return ret; | |
244 | } | |
245 | ||
246 | /* Tell bootstrap uCode where to find image to load */ | |
247 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); | |
248 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
249 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, | |
250 | priv->ucode_data.len); | |
251 | ||
a96a27f9 | 252 | /* Inst byte count must be last to set up, bit 31 signals uCode |
f3ccc08c EG |
253 | * that all new ptr/size info is in place */ |
254 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, | |
255 | priv->ucode_code.len | BSM_DRAM_INST_LOAD); | |
256 | iwl_release_nic_access(priv); | |
257 | ||
258 | spin_unlock_irqrestore(&priv->lock, flags); | |
259 | ||
260 | IWL_DEBUG_INFO("Runtime uCode pointers are set.\n"); | |
261 | ||
262 | return ret; | |
263 | } | |
264 | ||
265 | /** | |
266 | * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received | |
267 | * | |
268 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
269 | * | |
270 | * The 4965 "initialize" ALIVE reply contains calibration data for: | |
271 | * Voltage, temperature, and MIMO tx gain correction, now stored in priv | |
272 | * (3945 does not contain this data). | |
273 | * | |
274 | * Tell "initialize" uCode to go ahead and load the runtime uCode. | |
275 | */ | |
276 | static void iwl4965_init_alive_start(struct iwl_priv *priv) | |
277 | { | |
278 | /* Check alive response for "valid" sign from uCode */ | |
279 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
280 | /* We had an error bringing up the hardware, so take it | |
281 | * all the way back down so we can try again */ | |
282 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
283 | goto restart; | |
284 | } | |
285 | ||
286 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
287 | * This is a paranoid check, because we would not have gotten the | |
288 | * "initialize" alive if code weren't properly loaded. */ | |
289 | if (iwl_verify_ucode(priv)) { | |
290 | /* Runtime instruction load was bad; | |
291 | * take it all the way back down so we can try again */ | |
292 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
293 | goto restart; | |
294 | } | |
295 | ||
296 | /* Calculate temperature */ | |
91dbc5bd | 297 | priv->temperature = iwl4965_hw_get_temperature(priv); |
f3ccc08c EG |
298 | |
299 | /* Send pointers to protocol/runtime uCode image ... init code will | |
300 | * load and launch runtime uCode, which will send us another "Alive" | |
301 | * notification. */ | |
302 | IWL_DEBUG_INFO("Initialization Alive received.\n"); | |
303 | if (iwl4965_set_ucode_ptrs(priv)) { | |
304 | /* Runtime instruction load won't happen; | |
305 | * take it all the way back down so we can try again */ | |
306 | IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n"); | |
307 | goto restart; | |
308 | } | |
309 | return; | |
310 | ||
311 | restart: | |
312 | queue_work(priv->workqueue, &priv->restart); | |
313 | } | |
314 | ||
b481de9c ZY |
315 | static int is_fat_channel(__le32 rxon_flags) |
316 | { | |
317 | return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) || | |
318 | (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK); | |
319 | } | |
320 | ||
8614f360 TW |
321 | /* |
322 | * EEPROM handlers | |
323 | */ | |
0ef2ca67 | 324 | static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv) |
8614f360 | 325 | { |
0ef2ca67 | 326 | return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET); |
8614f360 | 327 | } |
b481de9c | 328 | |
da1bc453 | 329 | /* |
a96a27f9 | 330 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask |
da1bc453 TW |
331 | * must be called under priv->lock and mac access |
332 | */ | |
333 | static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask) | |
b481de9c | 334 | { |
da1bc453 | 335 | iwl_write_prph(priv, IWL49_SCD_TXFACT, mask); |
b481de9c ZY |
336 | } |
337 | ||
91238714 | 338 | static int iwl4965_apm_init(struct iwl_priv *priv) |
b481de9c | 339 | { |
91238714 | 340 | int ret = 0; |
b481de9c | 341 | |
3395f6e9 | 342 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
91238714 | 343 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
b481de9c | 344 | |
8f061891 TW |
345 | /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ |
346 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
347 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
348 | ||
91238714 TW |
349 | /* set "initialization complete" bit to move adapter |
350 | * D0U* --> D0A* state */ | |
3395f6e9 | 351 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
b481de9c | 352 | |
91238714 | 353 | /* wait for clock stabilization */ |
73d7b5ac ZY |
354 | ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, |
355 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
91238714 TW |
356 | if (ret < 0) { |
357 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
358 | goto out; | |
b481de9c ZY |
359 | } |
360 | ||
91238714 TW |
361 | ret = iwl_grab_nic_access(priv); |
362 | if (ret) | |
363 | goto out; | |
b481de9c | 364 | |
91238714 | 365 | /* enable DMA */ |
8f061891 TW |
366 | iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT | |
367 | APMG_CLK_VAL_BSM_CLK_RQT); | |
b481de9c ZY |
368 | |
369 | udelay(20); | |
370 | ||
8f061891 | 371 | /* disable L1-Active */ |
3395f6e9 | 372 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
91238714 | 373 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
b481de9c | 374 | |
3395f6e9 | 375 | iwl_release_nic_access(priv); |
91238714 | 376 | out: |
91238714 TW |
377 | return ret; |
378 | } | |
379 | ||
694cc56d TW |
380 | |
381 | static void iwl4965_nic_config(struct iwl_priv *priv) | |
91238714 TW |
382 | { |
383 | unsigned long flags; | |
91238714 | 384 | u32 val; |
694cc56d | 385 | u16 radio_cfg; |
e7b63581 | 386 | u16 link; |
6f4083aa | 387 | |
b481de9c ZY |
388 | spin_lock_irqsave(&priv->lock, flags); |
389 | ||
b661c819 | 390 | if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) { |
b481de9c ZY |
391 | pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val); |
392 | /* Enable No Snoop field */ | |
393 | pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8, | |
394 | val & ~(1 << 11)); | |
395 | } | |
396 | ||
e7b63581 | 397 | pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link); |
b481de9c | 398 | |
8f061891 | 399 | /* L1 is enabled by BIOS */ |
e7b63581 | 400 | if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) |
a96a27f9 | 401 | /* disable L0S disabled L1A enabled */ |
8f061891 TW |
402 | iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
403 | else | |
404 | /* L0S enabled L1A disabled */ | |
405 | iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
b481de9c | 406 | |
694cc56d | 407 | radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); |
b481de9c | 408 | |
694cc56d TW |
409 | /* write radio config values to register */ |
410 | if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX) | |
411 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
412 | EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | | |
413 | EEPROM_RF_CFG_STEP_MSK(radio_cfg) | | |
414 | EEPROM_RF_CFG_DASH_MSK(radio_cfg)); | |
b481de9c | 415 | |
694cc56d | 416 | /* set CSR_HW_CONFIG_REG for uCode use */ |
3395f6e9 | 417 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
a395b920 TW |
418 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | |
419 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
b481de9c | 420 | |
694cc56d TW |
421 | priv->calib_info = (struct iwl_eeprom_calib_info *) |
422 | iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET); | |
423 | ||
424 | spin_unlock_irqrestore(&priv->lock, flags); | |
425 | } | |
426 | ||
46315e01 TW |
427 | static int iwl4965_apm_stop_master(struct iwl_priv *priv) |
428 | { | |
46315e01 TW |
429 | unsigned long flags; |
430 | ||
431 | spin_lock_irqsave(&priv->lock, flags); | |
432 | ||
433 | /* set stop master bit */ | |
434 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
435 | ||
febf3370 | 436 | iwl_poll_direct_bit(priv, CSR_RESET, |
73d7b5ac | 437 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); |
46315e01 | 438 | |
46315e01 TW |
439 | spin_unlock_irqrestore(&priv->lock, flags); |
440 | IWL_DEBUG_INFO("stop master\n"); | |
441 | ||
febf3370 | 442 | return 0; |
46315e01 TW |
443 | } |
444 | ||
f118a91d TW |
445 | static void iwl4965_apm_stop(struct iwl_priv *priv) |
446 | { | |
447 | unsigned long flags; | |
448 | ||
46315e01 | 449 | iwl4965_apm_stop_master(priv); |
f118a91d TW |
450 | |
451 | spin_lock_irqsave(&priv->lock, flags); | |
452 | ||
453 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
454 | ||
455 | udelay(10); | |
1d3e6c61 MA |
456 | /* clear "init complete" move adapter D0A* --> D0U state */ |
457 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
f118a91d TW |
458 | spin_unlock_irqrestore(&priv->lock, flags); |
459 | } | |
460 | ||
7f066108 | 461 | static int iwl4965_apm_reset(struct iwl_priv *priv) |
b481de9c | 462 | { |
7f066108 | 463 | int ret = 0; |
b481de9c ZY |
464 | unsigned long flags; |
465 | ||
46315e01 | 466 | iwl4965_apm_stop_master(priv); |
b481de9c ZY |
467 | |
468 | spin_lock_irqsave(&priv->lock, flags); | |
469 | ||
3395f6e9 | 470 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
b481de9c ZY |
471 | |
472 | udelay(10); | |
473 | ||
7f066108 TW |
474 | /* FIXME: put here L1A -L0S w/a */ |
475 | ||
3395f6e9 | 476 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
f118a91d | 477 | |
73d7b5ac ZY |
478 | ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, |
479 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
42802d71 | 480 | if (ret < 0) |
7f066108 TW |
481 | goto out; |
482 | ||
b481de9c ZY |
483 | udelay(10); |
484 | ||
7f066108 TW |
485 | ret = iwl_grab_nic_access(priv); |
486 | if (ret) | |
487 | goto out; | |
488 | /* Enable DMA and BSM Clock */ | |
489 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT | | |
490 | APMG_CLK_VAL_BSM_CLK_RQT); | |
b481de9c | 491 | |
7f066108 | 492 | udelay(10); |
b481de9c | 493 | |
7f066108 TW |
494 | /* disable L1A */ |
495 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | |
496 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
b481de9c | 497 | |
7f066108 | 498 | iwl_release_nic_access(priv); |
b481de9c ZY |
499 | |
500 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
501 | wake_up_interruptible(&priv->wait_command_queue); | |
502 | ||
7f066108 | 503 | out: |
b481de9c ZY |
504 | spin_unlock_irqrestore(&priv->lock, flags); |
505 | ||
7f066108 | 506 | return ret; |
b481de9c ZY |
507 | } |
508 | ||
b481de9c ZY |
509 | /* Reset differential Rx gains in NIC to prepare for chain noise calibration. |
510 | * Called after every association, but this runs only once! | |
511 | * ... once chain noise is calibrated the first time, it's good forever. */ | |
f0832f13 | 512 | static void iwl4965_chain_noise_reset(struct iwl_priv *priv) |
b481de9c | 513 | { |
f0832f13 | 514 | struct iwl_chain_noise_data *data = &(priv->chain_noise_data); |
b481de9c | 515 | |
3109ece1 | 516 | if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { |
f69f42a6 | 517 | struct iwl_calib_diff_gain_cmd cmd; |
b481de9c ZY |
518 | |
519 | memset(&cmd, 0, sizeof(cmd)); | |
0d950d84 | 520 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD; |
b481de9c ZY |
521 | cmd.diff_gain_a = 0; |
522 | cmd.diff_gain_b = 0; | |
523 | cmd.diff_gain_c = 0; | |
f0832f13 EG |
524 | if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, |
525 | sizeof(cmd), &cmd)) | |
526 | IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); | |
b481de9c ZY |
527 | data->state = IWL_CHAIN_NOISE_ACCUMULATE; |
528 | IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); | |
529 | } | |
b481de9c ZY |
530 | } |
531 | ||
f0832f13 EG |
532 | static void iwl4965_gain_computation(struct iwl_priv *priv, |
533 | u32 *average_noise, | |
534 | u16 min_average_noise_antenna_i, | |
535 | u32 min_average_noise) | |
b481de9c | 536 | { |
f0832f13 EG |
537 | int i, ret; |
538 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
b481de9c | 539 | |
f0832f13 | 540 | data->delta_gain_code[min_average_noise_antenna_i] = 0; |
b481de9c | 541 | |
f0832f13 EG |
542 | for (i = 0; i < NUM_RX_CHAINS; i++) { |
543 | s32 delta_g = 0; | |
b481de9c | 544 | |
f0832f13 EG |
545 | if (!(data->disconn_array[i]) && |
546 | (data->delta_gain_code[i] == | |
b481de9c | 547 | CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) { |
f0832f13 EG |
548 | delta_g = average_noise[i] - min_average_noise; |
549 | data->delta_gain_code[i] = (u8)((delta_g * 10) / 15); | |
550 | data->delta_gain_code[i] = | |
551 | min(data->delta_gain_code[i], | |
552 | (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE); | |
553 | ||
554 | data->delta_gain_code[i] = | |
555 | (data->delta_gain_code[i] | (1 << 2)); | |
556 | } else { | |
557 | data->delta_gain_code[i] = 0; | |
b481de9c | 558 | } |
b481de9c | 559 | } |
f0832f13 EG |
560 | IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n", |
561 | data->delta_gain_code[0], | |
562 | data->delta_gain_code[1], | |
563 | data->delta_gain_code[2]); | |
b481de9c | 564 | |
f0832f13 EG |
565 | /* Differential gain gets sent to uCode only once */ |
566 | if (!data->radio_write) { | |
f69f42a6 | 567 | struct iwl_calib_diff_gain_cmd cmd; |
f0832f13 | 568 | data->radio_write = 1; |
b481de9c | 569 | |
f0832f13 | 570 | memset(&cmd, 0, sizeof(cmd)); |
0d950d84 | 571 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD; |
f0832f13 EG |
572 | cmd.diff_gain_a = data->delta_gain_code[0]; |
573 | cmd.diff_gain_b = data->delta_gain_code[1]; | |
574 | cmd.diff_gain_c = data->delta_gain_code[2]; | |
575 | ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, | |
576 | sizeof(cmd), &cmd); | |
577 | if (ret) | |
578 | IWL_DEBUG_CALIB("fail sending cmd " | |
579 | "REPLY_PHY_CALIBRATION_CMD \n"); | |
580 | ||
581 | /* TODO we might want recalculate | |
582 | * rx_chain in rxon cmd */ | |
583 | ||
584 | /* Mark so we run this algo only once! */ | |
585 | data->state = IWL_CHAIN_NOISE_CALIBRATED; | |
b481de9c | 586 | } |
f0832f13 EG |
587 | data->chain_noise_a = 0; |
588 | data->chain_noise_b = 0; | |
589 | data->chain_noise_c = 0; | |
590 | data->chain_signal_a = 0; | |
591 | data->chain_signal_b = 0; | |
592 | data->chain_signal_c = 0; | |
593 | data->beacon_count = 0; | |
b481de9c ZY |
594 | } |
595 | ||
a326a5d0 EG |
596 | static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info, |
597 | __le32 *tx_flags) | |
598 | { | |
e6a9854b | 599 | if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) { |
a326a5d0 EG |
600 | *tx_flags |= TX_CMD_FLG_RTS_MSK; |
601 | *tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
e6a9854b | 602 | } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { |
a326a5d0 EG |
603 | *tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
604 | *tx_flags |= TX_CMD_FLG_CTS_MSK; | |
605 | } | |
606 | } | |
607 | ||
b481de9c ZY |
608 | static void iwl4965_bg_txpower_work(struct work_struct *work) |
609 | { | |
c79dd5b5 | 610 | struct iwl_priv *priv = container_of(work, struct iwl_priv, |
b481de9c ZY |
611 | txpower_work); |
612 | ||
613 | /* If a scan happened to start before we got here | |
614 | * then just return; the statistics notification will | |
615 | * kick off another scheduled work to compensate for | |
616 | * any temperature delta we missed here. */ | |
617 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
618 | test_bit(STATUS_SCANNING, &priv->status)) | |
619 | return; | |
620 | ||
621 | mutex_lock(&priv->mutex); | |
622 | ||
a96a27f9 | 623 | /* Regardless of if we are associated, we must reconfigure the |
b481de9c ZY |
624 | * TX power since frames can be sent on non-radar channels while |
625 | * not associated */ | |
630fe9b6 | 626 | iwl4965_send_tx_power(priv); |
b481de9c ZY |
627 | |
628 | /* Update last_temperature to keep is_calib_needed from running | |
629 | * when it isn't needed... */ | |
630 | priv->last_temperature = priv->temperature; | |
631 | ||
632 | mutex_unlock(&priv->mutex); | |
633 | } | |
634 | ||
635 | /* | |
636 | * Acquire priv->lock before calling this function ! | |
637 | */ | |
c79dd5b5 | 638 | static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index) |
b481de9c | 639 | { |
3395f6e9 | 640 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, |
b481de9c | 641 | (index & 0xff) | (txq_id << 8)); |
12a81f60 | 642 | iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index); |
b481de9c ZY |
643 | } |
644 | ||
8b6eaea8 CB |
645 | /** |
646 | * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue | |
647 | * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed | |
648 | * @scd_retry: (1) Indicates queue will be used in aggregation mode | |
649 | * | |
650 | * NOTE: Acquire priv->lock before calling this function ! | |
b481de9c | 651 | */ |
c79dd5b5 | 652 | static void iwl4965_tx_queue_set_status(struct iwl_priv *priv, |
16466903 | 653 | struct iwl_tx_queue *txq, |
b481de9c ZY |
654 | int tx_fifo_id, int scd_retry) |
655 | { | |
656 | int txq_id = txq->q.id; | |
8b6eaea8 CB |
657 | |
658 | /* Find out whether to activate Tx queue */ | |
c3056065 | 659 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; |
b481de9c | 660 | |
8b6eaea8 | 661 | /* Set up and activate */ |
12a81f60 | 662 | iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id), |
038669e4 EG |
663 | (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
664 | (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) | | |
665 | (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) | | |
666 | (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) | | |
667 | IWL49_SCD_QUEUE_STTS_REG_MSK); | |
b481de9c ZY |
668 | |
669 | txq->sched_retry = scd_retry; | |
670 | ||
671 | IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", | |
8b6eaea8 | 672 | active ? "Activate" : "Deactivate", |
b481de9c ZY |
673 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); |
674 | } | |
675 | ||
676 | static const u16 default_queue_to_tx_fifo[] = { | |
677 | IWL_TX_FIFO_AC3, | |
678 | IWL_TX_FIFO_AC2, | |
679 | IWL_TX_FIFO_AC1, | |
680 | IWL_TX_FIFO_AC0, | |
038669e4 | 681 | IWL49_CMD_FIFO_NUM, |
b481de9c ZY |
682 | IWL_TX_FIFO_HCCA_1, |
683 | IWL_TX_FIFO_HCCA_2 | |
684 | }; | |
685 | ||
be1f3ab6 | 686 | static int iwl4965_alive_notify(struct iwl_priv *priv) |
b481de9c ZY |
687 | { |
688 | u32 a; | |
b481de9c | 689 | unsigned long flags; |
857485c0 | 690 | int ret; |
31a73fe4 | 691 | int i, chan; |
40fc95d5 | 692 | u32 reg_val; |
b481de9c ZY |
693 | |
694 | spin_lock_irqsave(&priv->lock, flags); | |
695 | ||
3395f6e9 | 696 | ret = iwl_grab_nic_access(priv); |
857485c0 | 697 | if (ret) { |
b481de9c | 698 | spin_unlock_irqrestore(&priv->lock, flags); |
857485c0 | 699 | return ret; |
b481de9c ZY |
700 | } |
701 | ||
8b6eaea8 | 702 | /* Clear 4965's internal Tx Scheduler data base */ |
12a81f60 | 703 | priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR); |
038669e4 EG |
704 | a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET; |
705 | for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4) | |
3395f6e9 | 706 | iwl_write_targ_mem(priv, a, 0); |
038669e4 | 707 | for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4) |
3395f6e9 | 708 | iwl_write_targ_mem(priv, a, 0); |
5425e490 | 709 | for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) |
3395f6e9 | 710 | iwl_write_targ_mem(priv, a, 0); |
b481de9c | 711 | |
8b6eaea8 | 712 | /* Tel 4965 where to find Tx byte count tables */ |
12a81f60 | 713 | iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR, |
4ddbb7d0 | 714 | priv->scd_bc_tbls.dma >> 10); |
8b6eaea8 | 715 | |
31a73fe4 WT |
716 | /* Enable DMA channel */ |
717 | for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++) | |
718 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
719 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
720 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
721 | ||
40fc95d5 WT |
722 | /* Update FH chicken bits */ |
723 | reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); | |
724 | iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, | |
725 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
726 | ||
8b6eaea8 | 727 | /* Disable chain mode for all queues */ |
12a81f60 | 728 | iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0); |
b481de9c | 729 | |
8b6eaea8 | 730 | /* Initialize each Tx queue (including the command queue) */ |
5425e490 | 731 | for (i = 0; i < priv->hw_params.max_txq_num; i++) { |
8b6eaea8 CB |
732 | |
733 | /* TFD circular buffer read/write indexes */ | |
12a81f60 | 734 | iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0); |
3395f6e9 | 735 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); |
8b6eaea8 CB |
736 | |
737 | /* Max Tx Window size for Scheduler-ACK mode */ | |
3395f6e9 | 738 | iwl_write_targ_mem(priv, priv->scd_base_addr + |
038669e4 EG |
739 | IWL49_SCD_CONTEXT_QUEUE_OFFSET(i), |
740 | (SCD_WIN_SIZE << | |
741 | IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & | |
742 | IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); | |
8b6eaea8 CB |
743 | |
744 | /* Frame limit */ | |
3395f6e9 | 745 | iwl_write_targ_mem(priv, priv->scd_base_addr + |
038669e4 EG |
746 | IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) + |
747 | sizeof(u32), | |
748 | (SCD_FRAME_LIMIT << | |
749 | IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
750 | IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); | |
b481de9c ZY |
751 | |
752 | } | |
12a81f60 | 753 | iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK, |
5425e490 | 754 | (1 << priv->hw_params.max_txq_num) - 1); |
b481de9c | 755 | |
8b6eaea8 | 756 | /* Activate all Tx DMA/FIFO channels */ |
31a73fe4 | 757 | priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6)); |
b481de9c ZY |
758 | |
759 | iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); | |
8b6eaea8 CB |
760 | |
761 | /* Map each Tx/cmd queue to its corresponding fifo */ | |
b481de9c ZY |
762 | for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) { |
763 | int ac = default_queue_to_tx_fifo[i]; | |
36470749 | 764 | iwl_txq_ctx_activate(priv, i); |
b481de9c ZY |
765 | iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); |
766 | } | |
767 | ||
3395f6e9 | 768 | iwl_release_nic_access(priv); |
b481de9c ZY |
769 | spin_unlock_irqrestore(&priv->lock, flags); |
770 | ||
857485c0 | 771 | return ret; |
b481de9c ZY |
772 | } |
773 | ||
f0832f13 EG |
774 | static struct iwl_sensitivity_ranges iwl4965_sensitivity = { |
775 | .min_nrg_cck = 97, | |
776 | .max_nrg_cck = 0, | |
777 | ||
778 | .auto_corr_min_ofdm = 85, | |
779 | .auto_corr_min_ofdm_mrc = 170, | |
780 | .auto_corr_min_ofdm_x1 = 105, | |
781 | .auto_corr_min_ofdm_mrc_x1 = 220, | |
782 | ||
783 | .auto_corr_max_ofdm = 120, | |
784 | .auto_corr_max_ofdm_mrc = 210, | |
785 | .auto_corr_max_ofdm_x1 = 140, | |
786 | .auto_corr_max_ofdm_mrc_x1 = 270, | |
787 | ||
788 | .auto_corr_min_cck = 125, | |
789 | .auto_corr_max_cck = 200, | |
790 | .auto_corr_min_cck_mrc = 200, | |
791 | .auto_corr_max_cck_mrc = 400, | |
792 | ||
793 | .nrg_th_cck = 100, | |
794 | .nrg_th_ofdm = 100, | |
795 | }; | |
f0832f13 | 796 | |
8b6eaea8 | 797 | /** |
5425e490 | 798 | * iwl4965_hw_set_hw_params |
8b6eaea8 CB |
799 | * |
800 | * Called when initializing driver | |
801 | */ | |
be1f3ab6 | 802 | static int iwl4965_hw_set_hw_params(struct iwl_priv *priv) |
b481de9c | 803 | { |
316c30d9 | 804 | |
038669e4 | 805 | if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) || |
1ea87396 | 806 | (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { |
316c30d9 | 807 | IWL_ERROR("invalid queues_num, should be between %d and %d\n", |
038669e4 | 808 | IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES); |
059ff826 | 809 | return -EINVAL; |
316c30d9 | 810 | } |
b481de9c | 811 | |
5425e490 | 812 | priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; |
f3f911d1 | 813 | priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM; |
4ddbb7d0 TW |
814 | priv->hw_params.scd_bc_tbls_size = |
815 | IWL49_NUM_QUEUES * sizeof(struct iwl4965_scd_bc_tbl); | |
5425e490 TW |
816 | priv->hw_params.max_stations = IWL4965_STATION_COUNT; |
817 | priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID; | |
099b40b7 RR |
818 | priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE; |
819 | priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE; | |
820 | priv->hw_params.max_bsm_size = BSM_SRAM_SIZE; | |
821 | priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ); | |
822 | ||
ec35cf2a TW |
823 | priv->hw_params.tx_chains_num = 2; |
824 | priv->hw_params.rx_chains_num = 2; | |
fde0db31 GC |
825 | priv->hw_params.valid_tx_ant = ANT_A | ANT_B; |
826 | priv->hw_params.valid_rx_ant = ANT_A | ANT_B; | |
099b40b7 RR |
827 | priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD); |
828 | ||
f0832f13 | 829 | priv->hw_params.sens = &iwl4965_sensitivity; |
3e82a822 | 830 | |
059ff826 | 831 | return 0; |
b481de9c ZY |
832 | } |
833 | ||
b481de9c ZY |
834 | static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res) |
835 | { | |
836 | s32 sign = 1; | |
837 | ||
838 | if (num < 0) { | |
839 | sign = -sign; | |
840 | num = -num; | |
841 | } | |
842 | if (denom < 0) { | |
843 | sign = -sign; | |
844 | denom = -denom; | |
845 | } | |
846 | *res = 1; | |
847 | *res = ((num * 2 + denom) / (denom * 2)) * sign; | |
848 | ||
849 | return 1; | |
850 | } | |
851 | ||
8b6eaea8 CB |
852 | /** |
853 | * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower | |
854 | * | |
855 | * Determines power supply voltage compensation for txpower calculations. | |
856 | * Returns number of 1/2-dB steps to subtract from gain table index, | |
857 | * to compensate for difference between power supply voltage during | |
858 | * factory measurements, vs. current power supply voltage. | |
859 | * | |
860 | * Voltage indication is higher for lower voltage. | |
861 | * Lower voltage requires more gain (lower gain table index). | |
862 | */ | |
b481de9c ZY |
863 | static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage, |
864 | s32 current_voltage) | |
865 | { | |
866 | s32 comp = 0; | |
867 | ||
868 | if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) || | |
869 | (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage)) | |
870 | return 0; | |
871 | ||
872 | iwl4965_math_div_round(current_voltage - eeprom_voltage, | |
873 | TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp); | |
874 | ||
875 | if (current_voltage > eeprom_voltage) | |
876 | comp *= 2; | |
877 | if ((comp < -2) || (comp > 2)) | |
878 | comp = 0; | |
879 | ||
880 | return comp; | |
881 | } | |
882 | ||
b481de9c ZY |
883 | static s32 iwl4965_get_tx_atten_grp(u16 channel) |
884 | { | |
885 | if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH && | |
886 | channel <= CALIB_IWL_TX_ATTEN_GR5_LCH) | |
887 | return CALIB_CH_GROUP_5; | |
888 | ||
889 | if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH && | |
890 | channel <= CALIB_IWL_TX_ATTEN_GR1_LCH) | |
891 | return CALIB_CH_GROUP_1; | |
892 | ||
893 | if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH && | |
894 | channel <= CALIB_IWL_TX_ATTEN_GR2_LCH) | |
895 | return CALIB_CH_GROUP_2; | |
896 | ||
897 | if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH && | |
898 | channel <= CALIB_IWL_TX_ATTEN_GR3_LCH) | |
899 | return CALIB_CH_GROUP_3; | |
900 | ||
901 | if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH && | |
902 | channel <= CALIB_IWL_TX_ATTEN_GR4_LCH) | |
903 | return CALIB_CH_GROUP_4; | |
904 | ||
905 | IWL_ERROR("Can't find txatten group for channel %d.\n", channel); | |
906 | return -1; | |
907 | } | |
908 | ||
c79dd5b5 | 909 | static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel) |
b481de9c ZY |
910 | { |
911 | s32 b = -1; | |
912 | ||
913 | for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) { | |
073d3f5f | 914 | if (priv->calib_info->band_info[b].ch_from == 0) |
b481de9c ZY |
915 | continue; |
916 | ||
073d3f5f TW |
917 | if ((channel >= priv->calib_info->band_info[b].ch_from) |
918 | && (channel <= priv->calib_info->band_info[b].ch_to)) | |
b481de9c ZY |
919 | break; |
920 | } | |
921 | ||
922 | return b; | |
923 | } | |
924 | ||
925 | static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2) | |
926 | { | |
927 | s32 val; | |
928 | ||
929 | if (x2 == x1) | |
930 | return y1; | |
931 | else { | |
932 | iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val); | |
933 | return val + y2; | |
934 | } | |
935 | } | |
936 | ||
8b6eaea8 CB |
937 | /** |
938 | * iwl4965_interpolate_chan - Interpolate factory measurements for one channel | |
939 | * | |
940 | * Interpolates factory measurements from the two sample channels within a | |
941 | * sub-band, to apply to channel of interest. Interpolation is proportional to | |
942 | * differences in channel frequencies, which is proportional to differences | |
943 | * in channel number. | |
944 | */ | |
c79dd5b5 | 945 | static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel, |
073d3f5f | 946 | struct iwl_eeprom_calib_ch_info *chan_info) |
b481de9c ZY |
947 | { |
948 | s32 s = -1; | |
949 | u32 c; | |
950 | u32 m; | |
073d3f5f TW |
951 | const struct iwl_eeprom_calib_measure *m1; |
952 | const struct iwl_eeprom_calib_measure *m2; | |
953 | struct iwl_eeprom_calib_measure *omeas; | |
b481de9c ZY |
954 | u32 ch_i1; |
955 | u32 ch_i2; | |
956 | ||
957 | s = iwl4965_get_sub_band(priv, channel); | |
958 | if (s >= EEPROM_TX_POWER_BANDS) { | |
6f147926 | 959 | IWL_ERROR("Tx Power can not find channel %d\n", channel); |
b481de9c ZY |
960 | return -1; |
961 | } | |
962 | ||
073d3f5f TW |
963 | ch_i1 = priv->calib_info->band_info[s].ch1.ch_num; |
964 | ch_i2 = priv->calib_info->band_info[s].ch2.ch_num; | |
b481de9c ZY |
965 | chan_info->ch_num = (u8) channel; |
966 | ||
967 | IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n", | |
968 | channel, s, ch_i1, ch_i2); | |
969 | ||
970 | for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) { | |
971 | for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) { | |
073d3f5f | 972 | m1 = &(priv->calib_info->band_info[s].ch1. |
b481de9c | 973 | measurements[c][m]); |
073d3f5f | 974 | m2 = &(priv->calib_info->band_info[s].ch2. |
b481de9c ZY |
975 | measurements[c][m]); |
976 | omeas = &(chan_info->measurements[c][m]); | |
977 | ||
978 | omeas->actual_pow = | |
979 | (u8) iwl4965_interpolate_value(channel, ch_i1, | |
980 | m1->actual_pow, | |
981 | ch_i2, | |
982 | m2->actual_pow); | |
983 | omeas->gain_idx = | |
984 | (u8) iwl4965_interpolate_value(channel, ch_i1, | |
985 | m1->gain_idx, ch_i2, | |
986 | m2->gain_idx); | |
987 | omeas->temperature = | |
988 | (u8) iwl4965_interpolate_value(channel, ch_i1, | |
989 | m1->temperature, | |
990 | ch_i2, | |
991 | m2->temperature); | |
992 | omeas->pa_det = | |
993 | (s8) iwl4965_interpolate_value(channel, ch_i1, | |
994 | m1->pa_det, ch_i2, | |
995 | m2->pa_det); | |
996 | ||
997 | IWL_DEBUG_TXPOWER | |
998 | ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m, | |
999 | m1->actual_pow, m2->actual_pow, omeas->actual_pow); | |
1000 | IWL_DEBUG_TXPOWER | |
1001 | ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m, | |
1002 | m1->gain_idx, m2->gain_idx, omeas->gain_idx); | |
1003 | IWL_DEBUG_TXPOWER | |
1004 | ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m, | |
1005 | m1->pa_det, m2->pa_det, omeas->pa_det); | |
1006 | IWL_DEBUG_TXPOWER | |
1007 | ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m, | |
1008 | m1->temperature, m2->temperature, | |
1009 | omeas->temperature); | |
1010 | } | |
1011 | } | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | /* bit-rate-dependent table to prevent Tx distortion, in half-dB units, | |
1017 | * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */ | |
1018 | static s32 back_off_table[] = { | |
1019 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */ | |
1020 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */ | |
1021 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */ | |
1022 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */ | |
1023 | 10 /* CCK */ | |
1024 | }; | |
1025 | ||
1026 | /* Thermal compensation values for txpower for various frequency ranges ... | |
1027 | * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */ | |
bb8c093b | 1028 | static struct iwl4965_txpower_comp_entry { |
b481de9c ZY |
1029 | s32 degrees_per_05db_a; |
1030 | s32 degrees_per_05db_a_denom; | |
1031 | } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = { | |
1032 | {9, 2}, /* group 0 5.2, ch 34-43 */ | |
1033 | {4, 1}, /* group 1 5.2, ch 44-70 */ | |
1034 | {4, 1}, /* group 2 5.2, ch 71-124 */ | |
1035 | {4, 1}, /* group 3 5.2, ch 125-200 */ | |
1036 | {3, 1} /* group 4 2.4, ch all */ | |
1037 | }; | |
1038 | ||
1039 | static s32 get_min_power_index(s32 rate_power_index, u32 band) | |
1040 | { | |
1041 | if (!band) { | |
1042 | if ((rate_power_index & 7) <= 4) | |
1043 | return MIN_TX_GAIN_INDEX_52GHZ_EXT; | |
1044 | } | |
1045 | return MIN_TX_GAIN_INDEX; | |
1046 | } | |
1047 | ||
1048 | struct gain_entry { | |
1049 | u8 dsp; | |
1050 | u8 radio; | |
1051 | }; | |
1052 | ||
1053 | static const struct gain_entry gain_table[2][108] = { | |
1054 | /* 5.2GHz power gain index table */ | |
1055 | { | |
1056 | {123, 0x3F}, /* highest txpower */ | |
1057 | {117, 0x3F}, | |
1058 | {110, 0x3F}, | |
1059 | {104, 0x3F}, | |
1060 | {98, 0x3F}, | |
1061 | {110, 0x3E}, | |
1062 | {104, 0x3E}, | |
1063 | {98, 0x3E}, | |
1064 | {110, 0x3D}, | |
1065 | {104, 0x3D}, | |
1066 | {98, 0x3D}, | |
1067 | {110, 0x3C}, | |
1068 | {104, 0x3C}, | |
1069 | {98, 0x3C}, | |
1070 | {110, 0x3B}, | |
1071 | {104, 0x3B}, | |
1072 | {98, 0x3B}, | |
1073 | {110, 0x3A}, | |
1074 | {104, 0x3A}, | |
1075 | {98, 0x3A}, | |
1076 | {110, 0x39}, | |
1077 | {104, 0x39}, | |
1078 | {98, 0x39}, | |
1079 | {110, 0x38}, | |
1080 | {104, 0x38}, | |
1081 | {98, 0x38}, | |
1082 | {110, 0x37}, | |
1083 | {104, 0x37}, | |
1084 | {98, 0x37}, | |
1085 | {110, 0x36}, | |
1086 | {104, 0x36}, | |
1087 | {98, 0x36}, | |
1088 | {110, 0x35}, | |
1089 | {104, 0x35}, | |
1090 | {98, 0x35}, | |
1091 | {110, 0x34}, | |
1092 | {104, 0x34}, | |
1093 | {98, 0x34}, | |
1094 | {110, 0x33}, | |
1095 | {104, 0x33}, | |
1096 | {98, 0x33}, | |
1097 | {110, 0x32}, | |
1098 | {104, 0x32}, | |
1099 | {98, 0x32}, | |
1100 | {110, 0x31}, | |
1101 | {104, 0x31}, | |
1102 | {98, 0x31}, | |
1103 | {110, 0x30}, | |
1104 | {104, 0x30}, | |
1105 | {98, 0x30}, | |
1106 | {110, 0x25}, | |
1107 | {104, 0x25}, | |
1108 | {98, 0x25}, | |
1109 | {110, 0x24}, | |
1110 | {104, 0x24}, | |
1111 | {98, 0x24}, | |
1112 | {110, 0x23}, | |
1113 | {104, 0x23}, | |
1114 | {98, 0x23}, | |
1115 | {110, 0x22}, | |
1116 | {104, 0x18}, | |
1117 | {98, 0x18}, | |
1118 | {110, 0x17}, | |
1119 | {104, 0x17}, | |
1120 | {98, 0x17}, | |
1121 | {110, 0x16}, | |
1122 | {104, 0x16}, | |
1123 | {98, 0x16}, | |
1124 | {110, 0x15}, | |
1125 | {104, 0x15}, | |
1126 | {98, 0x15}, | |
1127 | {110, 0x14}, | |
1128 | {104, 0x14}, | |
1129 | {98, 0x14}, | |
1130 | {110, 0x13}, | |
1131 | {104, 0x13}, | |
1132 | {98, 0x13}, | |
1133 | {110, 0x12}, | |
1134 | {104, 0x08}, | |
1135 | {98, 0x08}, | |
1136 | {110, 0x07}, | |
1137 | {104, 0x07}, | |
1138 | {98, 0x07}, | |
1139 | {110, 0x06}, | |
1140 | {104, 0x06}, | |
1141 | {98, 0x06}, | |
1142 | {110, 0x05}, | |
1143 | {104, 0x05}, | |
1144 | {98, 0x05}, | |
1145 | {110, 0x04}, | |
1146 | {104, 0x04}, | |
1147 | {98, 0x04}, | |
1148 | {110, 0x03}, | |
1149 | {104, 0x03}, | |
1150 | {98, 0x03}, | |
1151 | {110, 0x02}, | |
1152 | {104, 0x02}, | |
1153 | {98, 0x02}, | |
1154 | {110, 0x01}, | |
1155 | {104, 0x01}, | |
1156 | {98, 0x01}, | |
1157 | {110, 0x00}, | |
1158 | {104, 0x00}, | |
1159 | {98, 0x00}, | |
1160 | {93, 0x00}, | |
1161 | {88, 0x00}, | |
1162 | {83, 0x00}, | |
1163 | {78, 0x00}, | |
1164 | }, | |
1165 | /* 2.4GHz power gain index table */ | |
1166 | { | |
1167 | {110, 0x3f}, /* highest txpower */ | |
1168 | {104, 0x3f}, | |
1169 | {98, 0x3f}, | |
1170 | {110, 0x3e}, | |
1171 | {104, 0x3e}, | |
1172 | {98, 0x3e}, | |
1173 | {110, 0x3d}, | |
1174 | {104, 0x3d}, | |
1175 | {98, 0x3d}, | |
1176 | {110, 0x3c}, | |
1177 | {104, 0x3c}, | |
1178 | {98, 0x3c}, | |
1179 | {110, 0x3b}, | |
1180 | {104, 0x3b}, | |
1181 | {98, 0x3b}, | |
1182 | {110, 0x3a}, | |
1183 | {104, 0x3a}, | |
1184 | {98, 0x3a}, | |
1185 | {110, 0x39}, | |
1186 | {104, 0x39}, | |
1187 | {98, 0x39}, | |
1188 | {110, 0x38}, | |
1189 | {104, 0x38}, | |
1190 | {98, 0x38}, | |
1191 | {110, 0x37}, | |
1192 | {104, 0x37}, | |
1193 | {98, 0x37}, | |
1194 | {110, 0x36}, | |
1195 | {104, 0x36}, | |
1196 | {98, 0x36}, | |
1197 | {110, 0x35}, | |
1198 | {104, 0x35}, | |
1199 | {98, 0x35}, | |
1200 | {110, 0x34}, | |
1201 | {104, 0x34}, | |
1202 | {98, 0x34}, | |
1203 | {110, 0x33}, | |
1204 | {104, 0x33}, | |
1205 | {98, 0x33}, | |
1206 | {110, 0x32}, | |
1207 | {104, 0x32}, | |
1208 | {98, 0x32}, | |
1209 | {110, 0x31}, | |
1210 | {104, 0x31}, | |
1211 | {98, 0x31}, | |
1212 | {110, 0x30}, | |
1213 | {104, 0x30}, | |
1214 | {98, 0x30}, | |
1215 | {110, 0x6}, | |
1216 | {104, 0x6}, | |
1217 | {98, 0x6}, | |
1218 | {110, 0x5}, | |
1219 | {104, 0x5}, | |
1220 | {98, 0x5}, | |
1221 | {110, 0x4}, | |
1222 | {104, 0x4}, | |
1223 | {98, 0x4}, | |
1224 | {110, 0x3}, | |
1225 | {104, 0x3}, | |
1226 | {98, 0x3}, | |
1227 | {110, 0x2}, | |
1228 | {104, 0x2}, | |
1229 | {98, 0x2}, | |
1230 | {110, 0x1}, | |
1231 | {104, 0x1}, | |
1232 | {98, 0x1}, | |
1233 | {110, 0x0}, | |
1234 | {104, 0x0}, | |
1235 | {98, 0x0}, | |
1236 | {97, 0}, | |
1237 | {96, 0}, | |
1238 | {95, 0}, | |
1239 | {94, 0}, | |
1240 | {93, 0}, | |
1241 | {92, 0}, | |
1242 | {91, 0}, | |
1243 | {90, 0}, | |
1244 | {89, 0}, | |
1245 | {88, 0}, | |
1246 | {87, 0}, | |
1247 | {86, 0}, | |
1248 | {85, 0}, | |
1249 | {84, 0}, | |
1250 | {83, 0}, | |
1251 | {82, 0}, | |
1252 | {81, 0}, | |
1253 | {80, 0}, | |
1254 | {79, 0}, | |
1255 | {78, 0}, | |
1256 | {77, 0}, | |
1257 | {76, 0}, | |
1258 | {75, 0}, | |
1259 | {74, 0}, | |
1260 | {73, 0}, | |
1261 | {72, 0}, | |
1262 | {71, 0}, | |
1263 | {70, 0}, | |
1264 | {69, 0}, | |
1265 | {68, 0}, | |
1266 | {67, 0}, | |
1267 | {66, 0}, | |
1268 | {65, 0}, | |
1269 | {64, 0}, | |
1270 | {63, 0}, | |
1271 | {62, 0}, | |
1272 | {61, 0}, | |
1273 | {60, 0}, | |
1274 | {59, 0}, | |
1275 | } | |
1276 | }; | |
1277 | ||
c79dd5b5 | 1278 | static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel, |
b481de9c | 1279 | u8 is_fat, u8 ctrl_chan_high, |
bb8c093b | 1280 | struct iwl4965_tx_power_db *tx_power_tbl) |
b481de9c ZY |
1281 | { |
1282 | u8 saturation_power; | |
1283 | s32 target_power; | |
1284 | s32 user_target_power; | |
1285 | s32 power_limit; | |
1286 | s32 current_temp; | |
1287 | s32 reg_limit; | |
1288 | s32 current_regulatory; | |
1289 | s32 txatten_grp = CALIB_CH_GROUP_MAX; | |
1290 | int i; | |
1291 | int c; | |
bf85ea4f | 1292 | const struct iwl_channel_info *ch_info = NULL; |
073d3f5f TW |
1293 | struct iwl_eeprom_calib_ch_info ch_eeprom_info; |
1294 | const struct iwl_eeprom_calib_measure *measurement; | |
b481de9c ZY |
1295 | s16 voltage; |
1296 | s32 init_voltage; | |
1297 | s32 voltage_compensation; | |
1298 | s32 degrees_per_05db_num; | |
1299 | s32 degrees_per_05db_denom; | |
1300 | s32 factory_temp; | |
1301 | s32 temperature_comp[2]; | |
1302 | s32 factory_gain_index[2]; | |
1303 | s32 factory_actual_pwr[2]; | |
1304 | s32 power_index; | |
1305 | ||
b481de9c ZY |
1306 | /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units |
1307 | * are used for indexing into txpower table) */ | |
630fe9b6 | 1308 | user_target_power = 2 * priv->tx_power_user_lmt; |
b481de9c ZY |
1309 | |
1310 | /* Get current (RXON) channel, band, width */ | |
b481de9c ZY |
1311 | IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band, |
1312 | is_fat); | |
1313 | ||
630fe9b6 TW |
1314 | ch_info = iwl_get_channel_info(priv, priv->band, channel); |
1315 | ||
1316 | if (!is_channel_valid(ch_info)) | |
b481de9c ZY |
1317 | return -EINVAL; |
1318 | ||
1319 | /* get txatten group, used to select 1) thermal txpower adjustment | |
1320 | * and 2) mimo txpower balance between Tx chains. */ | |
1321 | txatten_grp = iwl4965_get_tx_atten_grp(channel); | |
1322 | if (txatten_grp < 0) | |
1323 | return -EINVAL; | |
1324 | ||
1325 | IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n", | |
1326 | channel, txatten_grp); | |
1327 | ||
1328 | if (is_fat) { | |
1329 | if (ctrl_chan_high) | |
1330 | channel -= 2; | |
1331 | else | |
1332 | channel += 2; | |
1333 | } | |
1334 | ||
1335 | /* hardware txpower limits ... | |
1336 | * saturation (clipping distortion) txpowers are in half-dBm */ | |
1337 | if (band) | |
073d3f5f | 1338 | saturation_power = priv->calib_info->saturation_power24; |
b481de9c | 1339 | else |
073d3f5f | 1340 | saturation_power = priv->calib_info->saturation_power52; |
b481de9c ZY |
1341 | |
1342 | if (saturation_power < IWL_TX_POWER_SATURATION_MIN || | |
1343 | saturation_power > IWL_TX_POWER_SATURATION_MAX) { | |
1344 | if (band) | |
1345 | saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24; | |
1346 | else | |
1347 | saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52; | |
1348 | } | |
1349 | ||
1350 | /* regulatory txpower limits ... reg_limit values are in half-dBm, | |
1351 | * max_power_avg values are in dBm, convert * 2 */ | |
1352 | if (is_fat) | |
1353 | reg_limit = ch_info->fat_max_power_avg * 2; | |
1354 | else | |
1355 | reg_limit = ch_info->max_power_avg * 2; | |
1356 | ||
1357 | if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) || | |
1358 | (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) { | |
1359 | if (band) | |
1360 | reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24; | |
1361 | else | |
1362 | reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52; | |
1363 | } | |
1364 | ||
1365 | /* Interpolate txpower calibration values for this channel, | |
1366 | * based on factory calibration tests on spaced channels. */ | |
1367 | iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info); | |
1368 | ||
1369 | /* calculate tx gain adjustment based on power supply voltage */ | |
073d3f5f | 1370 | voltage = priv->calib_info->voltage; |
b481de9c ZY |
1371 | init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage); |
1372 | voltage_compensation = | |
1373 | iwl4965_get_voltage_compensation(voltage, init_voltage); | |
1374 | ||
1375 | IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n", | |
1376 | init_voltage, | |
1377 | voltage, voltage_compensation); | |
1378 | ||
1379 | /* get current temperature (Celsius) */ | |
1380 | current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN); | |
1381 | current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX); | |
1382 | current_temp = KELVIN_TO_CELSIUS(current_temp); | |
1383 | ||
1384 | /* select thermal txpower adjustment params, based on channel group | |
1385 | * (same frequency group used for mimo txatten adjustment) */ | |
1386 | degrees_per_05db_num = | |
1387 | tx_power_cmp_tble[txatten_grp].degrees_per_05db_a; | |
1388 | degrees_per_05db_denom = | |
1389 | tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom; | |
1390 | ||
1391 | /* get per-chain txpower values from factory measurements */ | |
1392 | for (c = 0; c < 2; c++) { | |
1393 | measurement = &ch_eeprom_info.measurements[c][1]; | |
1394 | ||
1395 | /* txgain adjustment (in half-dB steps) based on difference | |
1396 | * between factory and current temperature */ | |
1397 | factory_temp = measurement->temperature; | |
1398 | iwl4965_math_div_round((current_temp - factory_temp) * | |
1399 | degrees_per_05db_denom, | |
1400 | degrees_per_05db_num, | |
1401 | &temperature_comp[c]); | |
1402 | ||
1403 | factory_gain_index[c] = measurement->gain_idx; | |
1404 | factory_actual_pwr[c] = measurement->actual_pow; | |
1405 | ||
1406 | IWL_DEBUG_TXPOWER("chain = %d\n", c); | |
1407 | IWL_DEBUG_TXPOWER("fctry tmp %d, " | |
1408 | "curr tmp %d, comp %d steps\n", | |
1409 | factory_temp, current_temp, | |
1410 | temperature_comp[c]); | |
1411 | ||
1412 | IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n", | |
1413 | factory_gain_index[c], | |
1414 | factory_actual_pwr[c]); | |
1415 | } | |
1416 | ||
1417 | /* for each of 33 bit-rates (including 1 for CCK) */ | |
1418 | for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) { | |
1419 | u8 is_mimo_rate; | |
bb8c093b | 1420 | union iwl4965_tx_power_dual_stream tx_power; |
b481de9c ZY |
1421 | |
1422 | /* for mimo, reduce each chain's txpower by half | |
1423 | * (3dB, 6 steps), so total output power is regulatory | |
1424 | * compliant. */ | |
1425 | if (i & 0x8) { | |
1426 | current_regulatory = reg_limit - | |
1427 | IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION; | |
1428 | is_mimo_rate = 1; | |
1429 | } else { | |
1430 | current_regulatory = reg_limit; | |
1431 | is_mimo_rate = 0; | |
1432 | } | |
1433 | ||
1434 | /* find txpower limit, either hardware or regulatory */ | |
1435 | power_limit = saturation_power - back_off_table[i]; | |
1436 | if (power_limit > current_regulatory) | |
1437 | power_limit = current_regulatory; | |
1438 | ||
1439 | /* reduce user's txpower request if necessary | |
1440 | * for this rate on this channel */ | |
1441 | target_power = user_target_power; | |
1442 | if (target_power > power_limit) | |
1443 | target_power = power_limit; | |
1444 | ||
1445 | IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n", | |
1446 | i, saturation_power - back_off_table[i], | |
1447 | current_regulatory, user_target_power, | |
1448 | target_power); | |
1449 | ||
1450 | /* for each of 2 Tx chains (radio transmitters) */ | |
1451 | for (c = 0; c < 2; c++) { | |
1452 | s32 atten_value; | |
1453 | ||
1454 | if (is_mimo_rate) | |
1455 | atten_value = | |
1456 | (s32)le32_to_cpu(priv->card_alive_init. | |
1457 | tx_atten[txatten_grp][c]); | |
1458 | else | |
1459 | atten_value = 0; | |
1460 | ||
1461 | /* calculate index; higher index means lower txpower */ | |
1462 | power_index = (u8) (factory_gain_index[c] - | |
1463 | (target_power - | |
1464 | factory_actual_pwr[c]) - | |
1465 | temperature_comp[c] - | |
1466 | voltage_compensation + | |
1467 | atten_value); | |
1468 | ||
1469 | /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n", | |
1470 | power_index); */ | |
1471 | ||
1472 | if (power_index < get_min_power_index(i, band)) | |
1473 | power_index = get_min_power_index(i, band); | |
1474 | ||
1475 | /* adjust 5 GHz index to support negative indexes */ | |
1476 | if (!band) | |
1477 | power_index += 9; | |
1478 | ||
1479 | /* CCK, rate 32, reduce txpower for CCK */ | |
1480 | if (i == POWER_TABLE_CCK_ENTRY) | |
1481 | power_index += | |
1482 | IWL_TX_POWER_CCK_COMPENSATION_C_STEP; | |
1483 | ||
1484 | /* stay within the table! */ | |
1485 | if (power_index > 107) { | |
1486 | IWL_WARNING("txpower index %d > 107\n", | |
1487 | power_index); | |
1488 | power_index = 107; | |
1489 | } | |
1490 | if (power_index < 0) { | |
1491 | IWL_WARNING("txpower index %d < 0\n", | |
1492 | power_index); | |
1493 | power_index = 0; | |
1494 | } | |
1495 | ||
1496 | /* fill txpower command for this rate/chain */ | |
1497 | tx_power.s.radio_tx_gain[c] = | |
1498 | gain_table[band][power_index].radio; | |
1499 | tx_power.s.dsp_predis_atten[c] = | |
1500 | gain_table[band][power_index].dsp; | |
1501 | ||
1502 | IWL_DEBUG_TXPOWER("chain %d mimo %d index %d " | |
1503 | "gain 0x%02x dsp %d\n", | |
1504 | c, atten_value, power_index, | |
1505 | tx_power.s.radio_tx_gain[c], | |
1506 | tx_power.s.dsp_predis_atten[c]); | |
3ac7f146 | 1507 | } /* for each chain */ |
b481de9c ZY |
1508 | |
1509 | tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw); | |
1510 | ||
3ac7f146 | 1511 | } /* for each rate */ |
b481de9c ZY |
1512 | |
1513 | return 0; | |
1514 | } | |
1515 | ||
1516 | /** | |
630fe9b6 | 1517 | * iwl4965_send_tx_power - Configure the TXPOWER level user limit |
b481de9c ZY |
1518 | * |
1519 | * Uses the active RXON for channel, band, and characteristics (fat, high) | |
630fe9b6 | 1520 | * The power limit is taken from priv->tx_power_user_lmt. |
b481de9c | 1521 | */ |
630fe9b6 | 1522 | static int iwl4965_send_tx_power(struct iwl_priv *priv) |
b481de9c | 1523 | { |
bb8c093b | 1524 | struct iwl4965_txpowertable_cmd cmd = { 0 }; |
857485c0 | 1525 | int ret; |
b481de9c ZY |
1526 | u8 band = 0; |
1527 | u8 is_fat = 0; | |
1528 | u8 ctrl_chan_high = 0; | |
1529 | ||
1530 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
1531 | /* If this gets hit a lot, switch it to a BUG() and catch | |
1532 | * the stack trace to find out who is calling this during | |
1533 | * a scan. */ | |
1534 | IWL_WARNING("TX Power requested while scanning!\n"); | |
1535 | return -EAGAIN; | |
1536 | } | |
1537 | ||
8318d78a | 1538 | band = priv->band == IEEE80211_BAND_2GHZ; |
b481de9c ZY |
1539 | |
1540 | is_fat = is_fat_channel(priv->active_rxon.flags); | |
1541 | ||
1542 | if (is_fat && | |
1543 | (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK)) | |
1544 | ctrl_chan_high = 1; | |
1545 | ||
1546 | cmd.band = band; | |
1547 | cmd.channel = priv->active_rxon.channel; | |
1548 | ||
857485c0 | 1549 | ret = iwl4965_fill_txpower_tbl(priv, band, |
b481de9c ZY |
1550 | le16_to_cpu(priv->active_rxon.channel), |
1551 | is_fat, ctrl_chan_high, &cmd.tx_power); | |
857485c0 TW |
1552 | if (ret) |
1553 | goto out; | |
b481de9c | 1554 | |
857485c0 TW |
1555 | ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd); |
1556 | ||
1557 | out: | |
1558 | return ret; | |
b481de9c ZY |
1559 | } |
1560 | ||
7e8c519e TW |
1561 | static int iwl4965_send_rxon_assoc(struct iwl_priv *priv) |
1562 | { | |
1563 | int ret = 0; | |
1564 | struct iwl4965_rxon_assoc_cmd rxon_assoc; | |
c1adf9fb GG |
1565 | const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; |
1566 | const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; | |
7e8c519e TW |
1567 | |
1568 | if ((rxon1->flags == rxon2->flags) && | |
1569 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1570 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1571 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
1572 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
1573 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
1574 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
1575 | (rxon1->rx_chain == rxon2->rx_chain) && | |
1576 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
1577 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
1578 | return 0; | |
1579 | } | |
1580 | ||
1581 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1582 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1583 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1584 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1585 | rxon_assoc.reserved = 0; | |
1586 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
1587 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
1588 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
1589 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
1590 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
1591 | ||
1592 | ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, | |
1593 | sizeof(rxon_assoc), &rxon_assoc, NULL); | |
1594 | if (ret) | |
1595 | return ret; | |
1596 | ||
1597 | return ret; | |
1598 | } | |
1599 | ||
3c935522 | 1600 | #ifdef IEEE80211_CONF_CHANNEL_SWITCH |
a33c2f47 | 1601 | static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel) |
b481de9c ZY |
1602 | { |
1603 | int rc; | |
1604 | u8 band = 0; | |
1605 | u8 is_fat = 0; | |
1606 | u8 ctrl_chan_high = 0; | |
bb8c093b | 1607 | struct iwl4965_channel_switch_cmd cmd = { 0 }; |
bf85ea4f | 1608 | const struct iwl_channel_info *ch_info; |
b481de9c | 1609 | |
8318d78a | 1610 | band = priv->band == IEEE80211_BAND_2GHZ; |
b481de9c | 1611 | |
8622e705 | 1612 | ch_info = iwl_get_channel_info(priv, priv->band, channel); |
b481de9c ZY |
1613 | |
1614 | is_fat = is_fat_channel(priv->staging_rxon.flags); | |
1615 | ||
1616 | if (is_fat && | |
1617 | (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK)) | |
1618 | ctrl_chan_high = 1; | |
1619 | ||
1620 | cmd.band = band; | |
1621 | cmd.expect_beacon = 0; | |
1622 | cmd.channel = cpu_to_le16(channel); | |
1623 | cmd.rxon_flags = priv->active_rxon.flags; | |
1624 | cmd.rxon_filter_flags = priv->active_rxon.filter_flags; | |
1625 | cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time); | |
1626 | if (ch_info) | |
1627 | cmd.expect_beacon = is_channel_radar(ch_info); | |
1628 | else | |
1629 | cmd.expect_beacon = 1; | |
1630 | ||
1631 | rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat, | |
1632 | ctrl_chan_high, &cmd.tx_power); | |
1633 | if (rc) { | |
1634 | IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc); | |
1635 | return rc; | |
1636 | } | |
1637 | ||
857485c0 | 1638 | rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd); |
b481de9c ZY |
1639 | return rc; |
1640 | } | |
3c935522 | 1641 | #endif |
b481de9c | 1642 | |
8b6eaea8 | 1643 | /** |
e2a722eb | 1644 | * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array |
8b6eaea8 | 1645 | */ |
e2a722eb | 1646 | static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv, |
16466903 | 1647 | struct iwl_tx_queue *txq, |
e2a722eb | 1648 | u16 byte_cnt) |
b481de9c | 1649 | { |
4ddbb7d0 | 1650 | struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab TW |
1651 | int txq_id = txq->q.id; |
1652 | int write_ptr = txq->q.write_ptr; | |
1653 | int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
1654 | __le16 bc_ent; | |
b481de9c | 1655 | |
127901ab | 1656 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
b481de9c | 1657 | |
127901ab | 1658 | bc_ent = cpu_to_le16(len & 0xFFF); |
8b6eaea8 | 1659 | /* Set up byte count within first 256 entries */ |
4ddbb7d0 | 1660 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; |
b481de9c | 1661 | |
8b6eaea8 | 1662 | /* If within first 64 entries, duplicate at end */ |
127901ab | 1663 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 1664 | scd_bc_tbl[txq_id]. |
127901ab | 1665 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; |
b481de9c ZY |
1666 | } |
1667 | ||
b481de9c ZY |
1668 | /** |
1669 | * sign_extend - Sign extend a value using specified bit as sign-bit | |
1670 | * | |
1671 | * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1 | |
1672 | * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7. | |
1673 | * | |
1674 | * @param oper value to sign extend | |
1675 | * @param index 0 based bit index (0<=index<32) to sign bit | |
1676 | */ | |
1677 | static s32 sign_extend(u32 oper, int index) | |
1678 | { | |
1679 | u8 shift = 31 - index; | |
1680 | ||
1681 | return (s32)(oper << shift) >> shift; | |
1682 | } | |
1683 | ||
1684 | /** | |
91dbc5bd | 1685 | * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin) |
b481de9c ZY |
1686 | * @statistics: Provides the temperature reading from the uCode |
1687 | * | |
1688 | * A return of <0 indicates bogus data in the statistics | |
1689 | */ | |
91dbc5bd | 1690 | static int iwl4965_hw_get_temperature(const struct iwl_priv *priv) |
b481de9c ZY |
1691 | { |
1692 | s32 temperature; | |
1693 | s32 vt; | |
1694 | s32 R1, R2, R3; | |
1695 | u32 R4; | |
1696 | ||
1697 | if (test_bit(STATUS_TEMPERATURE, &priv->status) && | |
1698 | (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) { | |
1699 | IWL_DEBUG_TEMP("Running FAT temperature calibration\n"); | |
1700 | R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]); | |
1701 | R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]); | |
1702 | R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]); | |
1703 | R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]); | |
1704 | } else { | |
1705 | IWL_DEBUG_TEMP("Running temperature calibration\n"); | |
1706 | R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]); | |
1707 | R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]); | |
1708 | R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]); | |
1709 | R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]); | |
1710 | } | |
1711 | ||
1712 | /* | |
8b6eaea8 | 1713 | * Temperature is only 23 bits, so sign extend out to 32. |
b481de9c ZY |
1714 | * |
1715 | * NOTE If we haven't received a statistics notification yet | |
1716 | * with an updated temperature, use R4 provided to us in the | |
8b6eaea8 CB |
1717 | * "initialize" ALIVE response. |
1718 | */ | |
b481de9c ZY |
1719 | if (!test_bit(STATUS_TEMPERATURE, &priv->status)) |
1720 | vt = sign_extend(R4, 23); | |
1721 | else | |
1722 | vt = sign_extend( | |
1723 | le32_to_cpu(priv->statistics.general.temperature), 23); | |
1724 | ||
91dbc5bd | 1725 | IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt); |
b481de9c ZY |
1726 | |
1727 | if (R3 == R1) { | |
1728 | IWL_ERROR("Calibration conflict R1 == R3\n"); | |
1729 | return -1; | |
1730 | } | |
1731 | ||
1732 | /* Calculate temperature in degrees Kelvin, adjust by 97%. | |
1733 | * Add offset to center the adjustment around 0 degrees Centigrade. */ | |
1734 | temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2); | |
1735 | temperature /= (R3 - R1); | |
91dbc5bd | 1736 | temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET; |
b481de9c | 1737 | |
91dbc5bd EG |
1738 | IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", |
1739 | temperature, KELVIN_TO_CELSIUS(temperature)); | |
b481de9c ZY |
1740 | |
1741 | return temperature; | |
1742 | } | |
1743 | ||
1744 | /* Adjust Txpower only if temperature variance is greater than threshold. */ | |
1745 | #define IWL_TEMPERATURE_THRESHOLD 3 | |
1746 | ||
1747 | /** | |
1748 | * iwl4965_is_temp_calib_needed - determines if new calibration is needed | |
1749 | * | |
1750 | * If the temperature changed has changed sufficiently, then a recalibration | |
1751 | * is needed. | |
1752 | * | |
1753 | * Assumes caller will replace priv->last_temperature once calibration | |
1754 | * executed. | |
1755 | */ | |
c79dd5b5 | 1756 | static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv) |
b481de9c ZY |
1757 | { |
1758 | int temp_diff; | |
1759 | ||
1760 | if (!test_bit(STATUS_STATISTICS, &priv->status)) { | |
1761 | IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n"); | |
1762 | return 0; | |
1763 | } | |
1764 | ||
1765 | temp_diff = priv->temperature - priv->last_temperature; | |
1766 | ||
1767 | /* get absolute value */ | |
1768 | if (temp_diff < 0) { | |
1769 | IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff); | |
1770 | temp_diff = -temp_diff; | |
1771 | } else if (temp_diff == 0) | |
1772 | IWL_DEBUG_POWER("Same temp, \n"); | |
1773 | else | |
1774 | IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff); | |
1775 | ||
1776 | if (temp_diff < IWL_TEMPERATURE_THRESHOLD) { | |
1777 | IWL_DEBUG_POWER("Thermal txpower calib not needed\n"); | |
1778 | return 0; | |
1779 | } | |
1780 | ||
1781 | IWL_DEBUG_POWER("Thermal txpower calib needed\n"); | |
1782 | ||
1783 | return 1; | |
1784 | } | |
1785 | ||
5225640b | 1786 | static void iwl4965_temperature_calib(struct iwl_priv *priv) |
b481de9c | 1787 | { |
b481de9c | 1788 | s32 temp; |
b481de9c | 1789 | |
91dbc5bd | 1790 | temp = iwl4965_hw_get_temperature(priv); |
b481de9c ZY |
1791 | if (temp < 0) |
1792 | return; | |
1793 | ||
1794 | if (priv->temperature != temp) { | |
1795 | if (priv->temperature) | |
1796 | IWL_DEBUG_TEMP("Temperature changed " | |
1797 | "from %dC to %dC\n", | |
1798 | KELVIN_TO_CELSIUS(priv->temperature), | |
1799 | KELVIN_TO_CELSIUS(temp)); | |
1800 | else | |
1801 | IWL_DEBUG_TEMP("Temperature " | |
1802 | "initialized to %dC\n", | |
1803 | KELVIN_TO_CELSIUS(temp)); | |
1804 | } | |
1805 | ||
1806 | priv->temperature = temp; | |
1807 | set_bit(STATUS_TEMPERATURE, &priv->status); | |
1808 | ||
203566f3 EG |
1809 | if (!priv->disable_tx_power_cal && |
1810 | unlikely(!test_bit(STATUS_SCANNING, &priv->status)) && | |
1811 | iwl4965_is_temp_calib_needed(priv)) | |
b481de9c ZY |
1812 | queue_work(priv->workqueue, &priv->txpower_work); |
1813 | } | |
1814 | ||
fe01b477 RR |
1815 | /** |
1816 | * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration | |
1817 | */ | |
c79dd5b5 | 1818 | static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, |
fe01b477 RR |
1819 | u16 txq_id) |
1820 | { | |
1821 | /* Simply stop the queue, but don't change any configuration; | |
1822 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
3395f6e9 | 1823 | iwl_write_prph(priv, |
12a81f60 | 1824 | IWL49_SCD_QUEUE_STATUS_BITS(txq_id), |
038669e4 EG |
1825 | (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)| |
1826 | (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
fe01b477 | 1827 | } |
b481de9c | 1828 | |
fe01b477 | 1829 | /** |
7f3e4bb6 | 1830 | * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE |
b095d03a | 1831 | * priv->lock must be held by the caller |
fe01b477 | 1832 | */ |
30e553e3 TW |
1833 | static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, |
1834 | u16 ssn_idx, u8 tx_fifo) | |
fe01b477 | 1835 | { |
b095d03a RR |
1836 | int ret = 0; |
1837 | ||
9f17b318 TW |
1838 | if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || |
1839 | (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) { | |
1840 | IWL_WARNING("queue number out of range: %d, must be %d to %d\n", | |
1841 | txq_id, IWL49_FIRST_AMPDU_QUEUE, | |
1842 | IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1); | |
fe01b477 | 1843 | return -EINVAL; |
b481de9c ZY |
1844 | } |
1845 | ||
3395f6e9 | 1846 | ret = iwl_grab_nic_access(priv); |
b095d03a RR |
1847 | if (ret) |
1848 | return ret; | |
1849 | ||
fe01b477 RR |
1850 | iwl4965_tx_queue_stop_scheduler(priv, txq_id); |
1851 | ||
12a81f60 | 1852 | iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); |
fe01b477 RR |
1853 | |
1854 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
1855 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
1856 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
1857 | iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); | |
1858 | ||
12a81f60 | 1859 | iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id)); |
36470749 | 1860 | iwl_txq_ctx_deactivate(priv, txq_id); |
fe01b477 RR |
1861 | iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); |
1862 | ||
3395f6e9 | 1863 | iwl_release_nic_access(priv); |
b095d03a | 1864 | |
fe01b477 RR |
1865 | return 0; |
1866 | } | |
b481de9c | 1867 | |
8b6eaea8 CB |
1868 | /** |
1869 | * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue | |
1870 | */ | |
c79dd5b5 | 1871 | static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, |
b481de9c ZY |
1872 | u16 txq_id) |
1873 | { | |
1874 | u32 tbl_dw_addr; | |
1875 | u32 tbl_dw; | |
1876 | u16 scd_q2ratid; | |
1877 | ||
30e553e3 | 1878 | scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; |
b481de9c ZY |
1879 | |
1880 | tbl_dw_addr = priv->scd_base_addr + | |
038669e4 | 1881 | IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); |
b481de9c | 1882 | |
3395f6e9 | 1883 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); |
b481de9c ZY |
1884 | |
1885 | if (txq_id & 0x1) | |
1886 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1887 | else | |
1888 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1889 | ||
3395f6e9 | 1890 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); |
b481de9c ZY |
1891 | |
1892 | return 0; | |
1893 | } | |
1894 | ||
fe01b477 | 1895 | |
b481de9c | 1896 | /** |
8b6eaea8 CB |
1897 | * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue |
1898 | * | |
7f3e4bb6 | 1899 | * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE, |
8b6eaea8 | 1900 | * i.e. it must be one of the higher queues used for aggregation |
b481de9c | 1901 | */ |
30e553e3 TW |
1902 | static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id, |
1903 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) | |
b481de9c ZY |
1904 | { |
1905 | unsigned long flags; | |
30e553e3 | 1906 | int ret; |
b481de9c ZY |
1907 | u16 ra_tid; |
1908 | ||
9f17b318 TW |
1909 | if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) || |
1910 | (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) { | |
1911 | IWL_WARNING("queue number out of range: %d, must be %d to %d\n", | |
1912 | txq_id, IWL49_FIRST_AMPDU_QUEUE, | |
1913 | IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1); | |
1914 | return -EINVAL; | |
1915 | } | |
b481de9c ZY |
1916 | |
1917 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
1918 | ||
8b6eaea8 | 1919 | /* Modify device's station table to Tx this TID */ |
9f58671e | 1920 | iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); |
b481de9c ZY |
1921 | |
1922 | spin_lock_irqsave(&priv->lock, flags); | |
30e553e3 TW |
1923 | ret = iwl_grab_nic_access(priv); |
1924 | if (ret) { | |
b481de9c | 1925 | spin_unlock_irqrestore(&priv->lock, flags); |
30e553e3 | 1926 | return ret; |
b481de9c ZY |
1927 | } |
1928 | ||
8b6eaea8 | 1929 | /* Stop this Tx queue before configuring it */ |
b481de9c ZY |
1930 | iwl4965_tx_queue_stop_scheduler(priv, txq_id); |
1931 | ||
8b6eaea8 | 1932 | /* Map receiver-address / traffic-ID to this queue */ |
b481de9c ZY |
1933 | iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id); |
1934 | ||
8b6eaea8 | 1935 | /* Set this queue as a chain-building queue */ |
12a81f60 | 1936 | iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); |
b481de9c | 1937 | |
8b6eaea8 CB |
1938 | /* Place first TFD at index corresponding to start sequence number. |
1939 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
fc4b6853 TW |
1940 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); |
1941 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
b481de9c ZY |
1942 | iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); |
1943 | ||
8b6eaea8 | 1944 | /* Set up Tx window size and frame limit for this queue */ |
3395f6e9 | 1945 | iwl_write_targ_mem(priv, |
038669e4 EG |
1946 | priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id), |
1947 | (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & | |
1948 | IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); | |
b481de9c | 1949 | |
3395f6e9 | 1950 | iwl_write_targ_mem(priv, priv->scd_base_addr + |
038669e4 EG |
1951 | IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1952 | (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) | |
1953 | & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); | |
b481de9c | 1954 | |
12a81f60 | 1955 | iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id)); |
b481de9c | 1956 | |
8b6eaea8 | 1957 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
b481de9c ZY |
1958 | iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); |
1959 | ||
3395f6e9 | 1960 | iwl_release_nic_access(priv); |
b481de9c ZY |
1961 | spin_unlock_irqrestore(&priv->lock, flags); |
1962 | ||
1963 | return 0; | |
1964 | } | |
1965 | ||
133636de | 1966 | |
c1adf9fb GG |
1967 | static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len) |
1968 | { | |
1969 | switch (cmd_id) { | |
1970 | case REPLY_RXON: | |
1971 | return (u16) sizeof(struct iwl4965_rxon_cmd); | |
1972 | default: | |
1973 | return len; | |
1974 | } | |
1975 | } | |
1976 | ||
133636de TW |
1977 | static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) |
1978 | { | |
1979 | struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data; | |
1980 | addsta->mode = cmd->mode; | |
1981 | memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify)); | |
1982 | memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo)); | |
1983 | addsta->station_flags = cmd->station_flags; | |
1984 | addsta->station_flags_msk = cmd->station_flags_msk; | |
1985 | addsta->tid_disable_tx = cmd->tid_disable_tx; | |
1986 | addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid; | |
1987 | addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid; | |
1988 | addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn; | |
1989 | addsta->reserved1 = __constant_cpu_to_le16(0); | |
1990 | addsta->reserved2 = __constant_cpu_to_le32(0); | |
1991 | ||
1992 | return (u16)sizeof(struct iwl4965_addsta_cmd); | |
1993 | } | |
f20217d9 | 1994 | |
f20217d9 TW |
1995 | static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp) |
1996 | { | |
25a6572c | 1997 | return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN; |
f20217d9 TW |
1998 | } |
1999 | ||
2000 | /** | |
a96a27f9 | 2001 | * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue |
f20217d9 TW |
2002 | */ |
2003 | static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv, | |
2004 | struct iwl_ht_agg *agg, | |
25a6572c TW |
2005 | struct iwl4965_tx_resp *tx_resp, |
2006 | int txq_id, u16 start_idx) | |
f20217d9 TW |
2007 | { |
2008 | u16 status; | |
25a6572c | 2009 | struct agg_tx_status *frame_status = tx_resp->u.agg_status; |
f20217d9 TW |
2010 | struct ieee80211_tx_info *info = NULL; |
2011 | struct ieee80211_hdr *hdr = NULL; | |
e7d326ac | 2012 | u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); |
25a6572c | 2013 | int i, sh, idx; |
f20217d9 | 2014 | u16 seq; |
f20217d9 TW |
2015 | if (agg->wait_for_ba) |
2016 | IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); | |
2017 | ||
2018 | agg->frame_count = tx_resp->frame_count; | |
2019 | agg->start_idx = start_idx; | |
e7d326ac | 2020 | agg->rate_n_flags = rate_n_flags; |
f20217d9 TW |
2021 | agg->bitmap = 0; |
2022 | ||
3fd07a1e | 2023 | /* num frames attempted by Tx command */ |
f20217d9 TW |
2024 | if (agg->frame_count == 1) { |
2025 | /* Only one frame was attempted; no block-ack will arrive */ | |
2026 | status = le16_to_cpu(frame_status[0].status); | |
25a6572c | 2027 | idx = start_idx; |
f20217d9 TW |
2028 | |
2029 | /* FIXME: code repetition */ | |
2030 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", | |
2031 | agg->frame_count, agg->start_idx, idx); | |
2032 | ||
2033 | info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); | |
e6a9854b | 2034 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
f20217d9 | 2035 | info->flags &= ~IEEE80211_TX_CTL_AMPDU; |
c3056065 | 2036 | info->flags |= iwl_is_tx_success(status) ? |
f20217d9 | 2037 | IEEE80211_TX_STAT_ACK : 0; |
e7d326ac | 2038 | iwl_hwrate_to_tx_control(priv, rate_n_flags, info); |
f20217d9 TW |
2039 | /* FIXME: code repetition end */ |
2040 | ||
2041 | IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", | |
2042 | status & 0xff, tx_resp->failure_frame); | |
e7d326ac | 2043 | IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); |
f20217d9 TW |
2044 | |
2045 | agg->wait_for_ba = 0; | |
2046 | } else { | |
2047 | /* Two or more frames were attempted; expect block-ack */ | |
2048 | u64 bitmap = 0; | |
2049 | int start = agg->start_idx; | |
2050 | ||
2051 | /* Construct bit-map of pending frames within Tx window */ | |
2052 | for (i = 0; i < agg->frame_count; i++) { | |
2053 | u16 sc; | |
2054 | status = le16_to_cpu(frame_status[i].status); | |
2055 | seq = le16_to_cpu(frame_status[i].sequence); | |
2056 | idx = SEQ_TO_INDEX(seq); | |
2057 | txq_id = SEQ_TO_QUEUE(seq); | |
2058 | ||
2059 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
2060 | AGG_TX_STATE_ABORT_MSK)) | |
2061 | continue; | |
2062 | ||
2063 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", | |
2064 | agg->frame_count, txq_id, idx); | |
2065 | ||
2066 | hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); | |
2067 | ||
2068 | sc = le16_to_cpu(hdr->seq_ctrl); | |
2069 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
2070 | IWL_ERROR("BUG_ON idx doesn't match seq control" | |
2071 | " idx=%d, seq_idx=%d, seq=%d\n", | |
2072 | idx, SEQ_TO_SN(sc), | |
2073 | hdr->seq_ctrl); | |
2074 | return -1; | |
2075 | } | |
2076 | ||
2077 | IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", | |
2078 | i, idx, SEQ_TO_SN(sc)); | |
2079 | ||
2080 | sh = idx - start; | |
2081 | if (sh > 64) { | |
2082 | sh = (start - idx) + 0xff; | |
2083 | bitmap = bitmap << sh; | |
2084 | sh = 0; | |
2085 | start = idx; | |
2086 | } else if (sh < -64) | |
2087 | sh = 0xff - (start - idx); | |
2088 | else if (sh < 0) { | |
2089 | sh = start - idx; | |
2090 | start = idx; | |
2091 | bitmap = bitmap << sh; | |
2092 | sh = 0; | |
2093 | } | |
4aa41f12 EG |
2094 | bitmap |= 1ULL << sh; |
2095 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", | |
2096 | start, (unsigned long long)bitmap); | |
f20217d9 TW |
2097 | } |
2098 | ||
2099 | agg->bitmap = bitmap; | |
2100 | agg->start_idx = start; | |
f20217d9 TW |
2101 | IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", |
2102 | agg->frame_count, agg->start_idx, | |
2103 | (unsigned long long)agg->bitmap); | |
2104 | ||
2105 | if (bitmap) | |
2106 | agg->wait_for_ba = 1; | |
2107 | } | |
2108 | return 0; | |
2109 | } | |
f20217d9 TW |
2110 | |
2111 | /** | |
2112 | * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response | |
2113 | */ | |
2114 | static void iwl4965_rx_reply_tx(struct iwl_priv *priv, | |
2115 | struct iwl_rx_mem_buffer *rxb) | |
2116 | { | |
2117 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
2118 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
2119 | int txq_id = SEQ_TO_QUEUE(sequence); | |
2120 | int index = SEQ_TO_INDEX(sequence); | |
2121 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
3fd07a1e | 2122 | struct ieee80211_hdr *hdr; |
f20217d9 TW |
2123 | struct ieee80211_tx_info *info; |
2124 | struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; | |
25a6572c | 2125 | u32 status = le32_to_cpu(tx_resp->u.status); |
3fd07a1e TW |
2126 | int tid = MAX_TID_COUNT; |
2127 | int sta_id; | |
2128 | int freed; | |
f20217d9 | 2129 | u8 *qc = NULL; |
f20217d9 TW |
2130 | |
2131 | if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { | |
2132 | IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " | |
2133 | "is out of range [0-%d] %d %d\n", txq_id, | |
2134 | index, txq->q.n_bd, txq->q.write_ptr, | |
2135 | txq->q.read_ptr); | |
2136 | return; | |
2137 | } | |
2138 | ||
2139 | info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); | |
2140 | memset(&info->status, 0, sizeof(info->status)); | |
2141 | ||
f20217d9 | 2142 | hdr = iwl_tx_queue_get_hdr(priv, txq_id, index); |
3fd07a1e | 2143 | if (ieee80211_is_data_qos(hdr->frame_control)) { |
fd7c8a40 | 2144 | qc = ieee80211_get_qos_ctl(hdr); |
f20217d9 TW |
2145 | tid = qc[0] & 0xf; |
2146 | } | |
2147 | ||
2148 | sta_id = iwl_get_ra_sta_id(priv, hdr); | |
2149 | if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) { | |
2150 | IWL_ERROR("Station not known\n"); | |
2151 | return; | |
2152 | } | |
2153 | ||
2154 | if (txq->sched_retry) { | |
2155 | const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp); | |
2156 | struct iwl_ht_agg *agg = NULL; | |
2157 | ||
3fd07a1e | 2158 | WARN_ON(!qc); |
f20217d9 TW |
2159 | |
2160 | agg = &priv->stations[sta_id].tid[tid].agg; | |
2161 | ||
25a6572c | 2162 | iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); |
f20217d9 | 2163 | |
3235427e RR |
2164 | /* check if BAR is needed */ |
2165 | if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) | |
2166 | info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
f20217d9 TW |
2167 | |
2168 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { | |
f20217d9 TW |
2169 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); |
2170 | IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn " | |
2171 | "%d index %d\n", scd_ssn , index); | |
17b88929 | 2172 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
f20217d9 TW |
2173 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
2174 | ||
3fd07a1e TW |
2175 | if (priv->mac80211_registered && |
2176 | (iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
2177 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { | |
f20217d9 TW |
2178 | if (agg->state == IWL_AGG_OFF) |
2179 | ieee80211_wake_queue(priv->hw, txq_id); | |
2180 | else | |
3fd07a1e TW |
2181 | ieee80211_wake_queue(priv->hw, |
2182 | txq->swq_id); | |
f20217d9 | 2183 | } |
f20217d9 TW |
2184 | } |
2185 | } else { | |
e6a9854b | 2186 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
3fd07a1e TW |
2187 | info->flags |= iwl_is_tx_success(status) ? |
2188 | IEEE80211_TX_STAT_ACK : 0; | |
e7d326ac | 2189 | iwl_hwrate_to_tx_control(priv, |
4f85f5b3 RR |
2190 | le32_to_cpu(tx_resp->rate_n_flags), |
2191 | info); | |
2192 | ||
3fd07a1e TW |
2193 | IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) " |
2194 | "rate_n_flags 0x%x retries %d\n", | |
2195 | txq_id, | |
2196 | iwl_get_tx_fail_reason(status), status, | |
2197 | le32_to_cpu(tx_resp->rate_n_flags), | |
2198 | tx_resp->failure_frame); | |
e7d326ac | 2199 | |
3fd07a1e | 2200 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
ed7fafec | 2201 | if (qc && likely(sta_id != IWL_INVALID_STATION)) |
f20217d9 | 2202 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
3fd07a1e TW |
2203 | |
2204 | if (priv->mac80211_registered && | |
2205 | (iwl_queue_space(&txq->q) > txq->q.low_mark)) | |
f20217d9 | 2206 | ieee80211_wake_queue(priv->hw, txq_id); |
f20217d9 | 2207 | } |
f20217d9 | 2208 | |
ed7fafec | 2209 | if (qc && likely(sta_id != IWL_INVALID_STATION)) |
3fd07a1e TW |
2210 | iwl_txq_check_empty(priv, sta_id, tid, txq_id); |
2211 | ||
f20217d9 TW |
2212 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) |
2213 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); | |
2214 | } | |
2215 | ||
caab8f1a TW |
2216 | static int iwl4965_calc_rssi(struct iwl_priv *priv, |
2217 | struct iwl_rx_phy_res *rx_resp) | |
2218 | { | |
2219 | /* data from PHY/DSP regarding signal strength, etc., | |
2220 | * contents are always there, not configurable by host. */ | |
2221 | struct iwl4965_rx_non_cfg_phy *ncphy = | |
2222 | (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | |
2223 | u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK) | |
2224 | >> IWL49_AGC_DB_POS; | |
2225 | ||
2226 | u32 valid_antennae = | |
2227 | (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK) | |
2228 | >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET; | |
2229 | u8 max_rssi = 0; | |
2230 | u32 i; | |
2231 | ||
2232 | /* Find max rssi among 3 possible receivers. | |
2233 | * These values are measured by the digital signal processor (DSP). | |
2234 | * They should stay fairly constant even as the signal strength varies, | |
2235 | * if the radio's automatic gain control (AGC) is working right. | |
2236 | * AGC value (see below) will provide the "interesting" info. */ | |
2237 | for (i = 0; i < 3; i++) | |
2238 | if (valid_antennae & (1 << i)) | |
2239 | max_rssi = max(ncphy->rssi_info[i << 1], max_rssi); | |
2240 | ||
2241 | IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", | |
2242 | ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4], | |
2243 | max_rssi, agc); | |
2244 | ||
2245 | /* dBm = max_rssi dB - agc dB - constant. | |
2246 | * Higher AGC (higher radio gain) means lower signal. */ | |
2247 | return max_rssi - agc - IWL_RSSI_OFFSET; | |
2248 | } | |
2249 | ||
f20217d9 | 2250 | |
b481de9c | 2251 | /* Set up 4965-specific Rx frame reply handlers */ |
d4789efe | 2252 | static void iwl4965_rx_handler_setup(struct iwl_priv *priv) |
b481de9c ZY |
2253 | { |
2254 | /* Legacy Rx frames */ | |
1781a07f | 2255 | priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx; |
37a44211 | 2256 | /* Tx response */ |
f20217d9 | 2257 | priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx; |
b481de9c ZY |
2258 | } |
2259 | ||
4e39317d | 2260 | static void iwl4965_setup_deferred_work(struct iwl_priv *priv) |
b481de9c ZY |
2261 | { |
2262 | INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work); | |
b481de9c ZY |
2263 | } |
2264 | ||
4e39317d | 2265 | static void iwl4965_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 2266 | { |
4e39317d | 2267 | cancel_work_sync(&priv->txpower_work); |
b481de9c ZY |
2268 | } |
2269 | ||
3c424c28 TW |
2270 | |
2271 | static struct iwl_hcmd_ops iwl4965_hcmd = { | |
7e8c519e | 2272 | .rxon_assoc = iwl4965_send_rxon_assoc, |
3c424c28 TW |
2273 | }; |
2274 | ||
857485c0 | 2275 | static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = { |
c1adf9fb | 2276 | .get_hcmd_size = iwl4965_get_hcmd_size, |
133636de | 2277 | .build_addsta_hcmd = iwl4965_build_addsta_hcmd, |
f0832f13 EG |
2278 | .chain_noise_reset = iwl4965_chain_noise_reset, |
2279 | .gain_computation = iwl4965_gain_computation, | |
a326a5d0 | 2280 | .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag, |
caab8f1a | 2281 | .calc_rssi = iwl4965_calc_rssi, |
857485c0 TW |
2282 | }; |
2283 | ||
6bc913bd | 2284 | static struct iwl_lib_ops iwl4965_lib = { |
5425e490 | 2285 | .set_hw_params = iwl4965_hw_set_hw_params, |
e2a722eb | 2286 | .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl, |
da1bc453 | 2287 | .txq_set_sched = iwl4965_txq_set_sched, |
30e553e3 TW |
2288 | .txq_agg_enable = iwl4965_txq_agg_enable, |
2289 | .txq_agg_disable = iwl4965_txq_agg_disable, | |
d4789efe | 2290 | .rx_handler_setup = iwl4965_rx_handler_setup, |
4e39317d EG |
2291 | .setup_deferred_work = iwl4965_setup_deferred_work, |
2292 | .cancel_deferred_work = iwl4965_cancel_deferred_work, | |
57aab75a TW |
2293 | .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr, |
2294 | .alive_notify = iwl4965_alive_notify, | |
f3ccc08c | 2295 | .init_alive_start = iwl4965_init_alive_start, |
57aab75a | 2296 | .load_ucode = iwl4965_load_bsm, |
6f4083aa | 2297 | .apm_ops = { |
91238714 | 2298 | .init = iwl4965_apm_init, |
7f066108 | 2299 | .reset = iwl4965_apm_reset, |
f118a91d | 2300 | .stop = iwl4965_apm_stop, |
694cc56d | 2301 | .config = iwl4965_nic_config, |
5b9f8cd3 | 2302 | .set_pwr_src = iwl_set_pwr_src, |
6f4083aa | 2303 | }, |
6bc913bd | 2304 | .eeprom_ops = { |
073d3f5f TW |
2305 | .regulatory_bands = { |
2306 | EEPROM_REGULATORY_BAND_1_CHANNELS, | |
2307 | EEPROM_REGULATORY_BAND_2_CHANNELS, | |
2308 | EEPROM_REGULATORY_BAND_3_CHANNELS, | |
2309 | EEPROM_REGULATORY_BAND_4_CHANNELS, | |
2310 | EEPROM_REGULATORY_BAND_5_CHANNELS, | |
2311 | EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS, | |
2312 | EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS | |
2313 | }, | |
6bc913bd AK |
2314 | .verify_signature = iwlcore_eeprom_verify_signature, |
2315 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
2316 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
0ef2ca67 | 2317 | .calib_version = iwl4965_eeprom_calib_version, |
073d3f5f | 2318 | .query_addr = iwlcore_eeprom_query_addr, |
6bc913bd | 2319 | }, |
630fe9b6 | 2320 | .send_tx_power = iwl4965_send_tx_power, |
5b9f8cd3 | 2321 | .update_chain_flags = iwl_update_chain_flags, |
8f91aecb | 2322 | .temperature = iwl4965_temperature_calib, |
6bc913bd AK |
2323 | }; |
2324 | ||
2325 | static struct iwl_ops iwl4965_ops = { | |
2326 | .lib = &iwl4965_lib, | |
3c424c28 | 2327 | .hcmd = &iwl4965_hcmd, |
857485c0 | 2328 | .utils = &iwl4965_hcmd_utils, |
6bc913bd AK |
2329 | }; |
2330 | ||
fed9017e | 2331 | struct iwl_cfg iwl4965_agn_cfg = { |
82b9a121 | 2332 | .name = "4965AGN", |
a0987a8d RC |
2333 | .fw_name_pre = IWL4965_FW_PRE, |
2334 | .ucode_api_max = IWL4965_UCODE_API_MAX, | |
2335 | .ucode_api_min = IWL4965_UCODE_API_MIN, | |
82b9a121 | 2336 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
073d3f5f | 2337 | .eeprom_size = IWL4965_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
2338 | .eeprom_ver = EEPROM_4965_EEPROM_VERSION, |
2339 | .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION, | |
6bc913bd | 2340 | .ops = &iwl4965_ops, |
1ea87396 | 2341 | .mod_params = &iwl4965_mod_params, |
82b9a121 TW |
2342 | }; |
2343 | ||
d16dc48a | 2344 | /* Module firmware */ |
a0987a8d | 2345 | MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX)); |
d16dc48a | 2346 | |
1ea87396 AK |
2347 | module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444); |
2348 | MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])"); | |
2349 | module_param_named(disable, iwl4965_mod_params.disable, int, 0444); | |
2350 | MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])"); | |
fcc76c6b | 2351 | module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444); |
61a2d07d | 2352 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); |
95aa194a | 2353 | module_param_named(debug, iwl4965_mod_params.debug, uint, 0444); |
1ea87396 AK |
2354 | MODULE_PARM_DESC(debug, "debug output mask"); |
2355 | module_param_named( | |
2356 | disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444); | |
2357 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); | |
2358 | ||
2359 | module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444); | |
2360 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | |
49779293 RR |
2361 | /* 11n */ |
2362 | module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, 0444); | |
2363 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | |
1ea87396 AK |
2364 | module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444); |
2365 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
49779293 | 2366 | |
3a1081e8 EK |
2367 | module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444); |
2368 | MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error"); |