projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: iwl3945 remove 4965 commands
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
82b9a121 42#include "iwl-core.h"
b481de9c
ZY		 43#include "iwl-4965.h"
44#include "iwl-helpers.h"
45
c79dd5b5 46static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
416e1438 47
b481de9c
ZY		 48#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_SISO_##s##M_PLCP, \
51 IWL_RATE_MIMO_##s##M_PLCP, \
52 IWL_RATE_##r##M_IEEE, \
53 IWL_RATE_##ip##M_INDEX, \
54 IWL_RATE_##in##M_INDEX, \
55 IWL_RATE_##rp##M_INDEX, \
56 IWL_RATE_##rn##M_INDEX, \
57 IWL_RATE_##pp##M_INDEX, \
58 IWL_RATE_##np##M_INDEX }
59
60/*
61 * Parameter order:
62 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
63 *
64 * If there isn't a valid next or previous rate then INV is used which
65 * maps to IWL_RATE_INVALID
66 *
67 */
bb8c093b 68const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
b481de9c
ZY		 69 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
70 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
71 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
72 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
73 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
74 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
75 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
76 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
77 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
78 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
79 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
80 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
81 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
82};
83
fe01b477
RR		 84#ifdef CONFIG_IWL4965_HT
85
86static const u16 default_tid_to_tx_fifo[] = {
87 IWL_TX_FIFO_AC1,
88 IWL_TX_FIFO_AC0,
89 IWL_TX_FIFO_AC0,
90 IWL_TX_FIFO_AC1,
91 IWL_TX_FIFO_AC2,
92 IWL_TX_FIFO_AC2,
93 IWL_TX_FIFO_AC3,
94 IWL_TX_FIFO_AC3,
95 IWL_TX_FIFO_NONE,
96 IWL_TX_FIFO_NONE,
97 IWL_TX_FIFO_NONE,
98 IWL_TX_FIFO_NONE,
99 IWL_TX_FIFO_NONE,
100 IWL_TX_FIFO_NONE,
101 IWL_TX_FIFO_NONE,
102 IWL_TX_FIFO_NONE,
103 IWL_TX_FIFO_AC3
104};
105
106#endif /*CONFIG_IWL4965_HT */
107
bf85ea4f
AK		 108static int iwl4965_init_drv(struct iwl_priv *priv)
109{
110 int ret;
111 int i;
112
113 priv->antenna = (enum iwl4965_antenna)iwl4965_mod_params.antenna;
114 priv->retry_rate = 1;
115 priv->ibss_beacon = NULL;
116
117 spin_lock_init(&priv->lock);
118 spin_lock_init(&priv->power_data.lock);
119 spin_lock_init(&priv->sta_lock);
120 spin_lock_init(&priv->hcmd_lock);
121 spin_lock_init(&priv->lq_mngr.lock);
122
123 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
124 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
125
126 INIT_LIST_HEAD(&priv->free_frames);
127
128 mutex_init(&priv->mutex);
129
130 /* Clear the driver's (not device's) station table */
131 iwlcore_clear_stations_table(priv);
132
133 priv->data_retry_limit = -1;
134 priv->ieee_channels = NULL;
135 priv->ieee_rates = NULL;
136 priv->band = IEEE80211_BAND_2GHZ;
137
138 priv->iw_mode = IEEE80211_IF_TYPE_STA;
139
140 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
141 priv->valid_antenna = 0x7; /* assume all 3 connected */
142 priv->ps_mode = IWL_MIMO_PS_NONE;
143
144 /* Choose which receivers/antennas to use */
145 iwl4965_set_rxon_chain(priv);
146
147 iwlcore_reset_qos(priv);
148
149 priv->qos_data.qos_active = 0;
150 priv->qos_data.qos_cap.val = 0;
151
152 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
153
154 priv->rates_mask = IWL_RATES_MASK;
155 /* If power management is turned on, default to AC mode */
156 priv->power_mode = IWL_POWER_AC;
157 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
158
159 ret = iwl_init_channel_map(priv);
160 if (ret) {
161 IWL_ERROR("initializing regulatory failed: %d\n", ret);
162 goto err;
163 }
164
165 ret = iwl4965_init_geos(priv);
166 if (ret) {
167 IWL_ERROR("initializing geos failed: %d\n", ret);
168 goto err_free_channel_map;
169 }
170
171 iwl4965_rate_control_register(priv->hw);
172 ret = ieee80211_register_hw(priv->hw);
173 if (ret) {
174 IWL_ERROR("Failed to register network device (error %d)\n",
175 ret);
176 goto err_free_geos;
177 }
178
179 priv->hw->conf.beacon_int = 100;
180 priv->mac80211_registered = 1;
181
182 return 0;
183
184err_free_geos:
185 iwl4965_free_geos(priv);
186err_free_channel_map:
187 iwl_free_channel_map(priv);
188err:
189 return ret;
190}
191
b481de9c
ZY		 192static int is_fat_channel(__le32 rxon_flags)
193{
194 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
195 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
196}
197
c79dd5b5 198static u8 is_single_stream(struct iwl_priv *priv)
b481de9c 199{
c8b0e6e1 200#ifdef CONFIG_IWL4965_HT
fd105e79
RR		 201 if (!priv->current_ht_config.is_ht ||
202 (priv->current_ht_config.supp_mcs_set[1] == 0) ||
b481de9c
ZY		 203 (priv->ps_mode == IWL_MIMO_PS_STATIC))
204 return 1;
205#else
206 return 1;
c8b0e6e1 207#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 208 return 0;
209}
210
17744ff6
TW		 211int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
212{
213 int idx = 0;
214
215 /* 4965 HT rate format */
216 if (rate_n_flags & RATE_MCS_HT_MSK) {
217 idx = (rate_n_flags & 0xff);
218
219 if (idx >= IWL_RATE_MIMO_6M_PLCP)
220 idx = idx - IWL_RATE_MIMO_6M_PLCP;
221
222 idx += IWL_FIRST_OFDM_RATE;
223 /* skip 9M not supported in ht*/
224 if (idx >= IWL_RATE_9M_INDEX)
225 idx += 1;
226 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
227 return idx;
228
229 /* 4965 legacy rate format, search for match in table */
230 } else {
231 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
232 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
233 return idx;
234 }
235
236 return -1;
237}
238
4c424e4c
RR		 239/**
240 * translate ucode response to mac80211 tx status control values
241 */
c79dd5b5 242void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
4c424e4c
RR		 243 struct ieee80211_tx_control *control)
244{
245 int rate_index;
246
247 control->antenna_sel_tx =
248 ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_A_POS);
249 if (rate_n_flags & RATE_MCS_HT_MSK)
250 control->flags |= IEEE80211_TXCTL_OFDM_HT;
251 if (rate_n_flags & RATE_MCS_GF_MSK)
252 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
253 if (rate_n_flags & RATE_MCS_FAT_MSK)
254 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
255 if (rate_n_flags & RATE_MCS_DUP_MSK)
256 control->flags |= IEEE80211_TXCTL_DUP_DATA;
257 if (rate_n_flags & RATE_MCS_SGI_MSK)
258 control->flags |= IEEE80211_TXCTL_SHORT_GI;
259 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
260 * IEEE80211_BAND_2GHZ band as it contains all the rates */
261 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
262 if (rate_index == -1)
263 control->tx_rate = NULL;
264 else
265 control->tx_rate =
266 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
267}
17744ff6 268
b481de9c
ZY		 269/*
270 * Determine how many receiver/antenna chains to use.
271 * More provides better reception via diversity. Fewer saves power.
272 * MIMO (dual stream) requires at least 2, but works better with 3.
273 * This does not determine *which* chains to use, just how many.
274 */
c79dd5b5 275static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
b481de9c
ZY		 276 u8 *idle_state, u8 *rx_state)
277{
278 u8 is_single = is_single_stream(priv);
279 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
280
281 /* # of Rx chains to use when expecting MIMO. */
282 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
283 *rx_state = 2;
284 else
285 *rx_state = 3;
286
287 /* # Rx chains when idling and maybe trying to save power */
288 switch (priv->ps_mode) {
289 case IWL_MIMO_PS_STATIC:
290 case IWL_MIMO_PS_DYNAMIC:
291 *idle_state = (is_cam) ? 2 : 1;
292 break;
293 case IWL_MIMO_PS_NONE:
294 *idle_state = (is_cam) ? *rx_state : 1;
295 break;
296 default:
297 *idle_state = 1;
298 break;
299 }
300
301 return 0;
302}
303
c79dd5b5 304int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 305{
306 int rc;
307 unsigned long flags;
308
309 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 310 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 311 if (rc) {
312 spin_unlock_irqrestore(&priv->lock, flags);
313 return rc;
314 }
315
8b6eaea8 316 /* stop Rx DMA */
bb8c093b
CH		 317 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
318 rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
b481de9c
ZY		 319 (1 << 24), 1000);
320 if (rc < 0)
321 IWL_ERROR("Can't stop Rx DMA.\n");
322
bb8c093b 323 iwl4965_release_nic_access(priv);
b481de9c
ZY		 324 spin_unlock_irqrestore(&priv->lock, flags);
325
326 return 0;
327}
328
c79dd5b5 329u8 iwl4965_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c
ZY		 330{
331 int i;
332 int start = 0;
333 int ret = IWL_INVALID_STATION;
334 unsigned long flags;
0795af57 335 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 336
337 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
338 (priv->iw_mode == IEEE80211_IF_TYPE_AP))
339 start = IWL_STA_ID;
340
341 if (is_broadcast_ether_addr(addr))
a4062b8f 342 return priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 343
344 spin_lock_irqsave(&priv->sta_lock, flags);
345 for (i = start; i < priv->hw_setting.max_stations; i++)
346 if ((priv->stations[i].used) &&
347 (!compare_ether_addr
348 (priv->stations[i].sta.sta.addr, addr))) {
349 ret = i;
350 goto out;
351 }
352
a50e2e3f 353 IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
0795af57 354 print_mac(mac, addr), priv->num_stations);
b481de9c
ZY		 355
356 out:
357 spin_unlock_irqrestore(&priv->sta_lock, flags);
358 return ret;
359}
360
c79dd5b5 361static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
b481de9c 362{
d8609652 363 int ret;
b481de9c
ZY		 364 unsigned long flags;
365
366 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 367 ret = iwl4965_grab_nic_access(priv);
d8609652 368 if (ret) {
b481de9c 369 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 370 return ret;
b481de9c
ZY		 371 }
372
373 if (!pwr_max) {
374 u32 val;
375
d8609652 376 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
b481de9c
ZY		 377 &val);
378
379 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
bb8c093b 380 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 381 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
382 ~APMG_PS_CTRL_MSK_PWR_SRC);
383 } else
bb8c093b 384 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 385 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
386 ~APMG_PS_CTRL_MSK_PWR_SRC);
387
bb8c093b 388 iwl4965_release_nic_access(priv);
b481de9c
ZY		 389 spin_unlock_irqrestore(&priv->lock, flags);
390
d8609652 391 return ret;
b481de9c
ZY		 392}
393
c79dd5b5 394static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c
ZY		 395{
396 int rc;
397 unsigned long flags;
9ee1ba47 398 unsigned int rb_size;
b481de9c
ZY		 399
400 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 401 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 402 if (rc) {
403 spin_unlock_irqrestore(&priv->lock, flags);
404 return rc;
405 }
406
00acbc91 407 if (iwl4965_mod_params.amsdu_size_8K)
9ee1ba47
RR		 408 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
409 else
410 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
411
8b6eaea8 412 /* Stop Rx DMA */
bb8c093b 413 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
b481de9c 414
8b6eaea8 415 /* Reset driver's Rx queue write index */
bb8c093b 416 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
8b6eaea8
CB		 417
418 /* Tell device where to find RBD circular buffer in DRAM */
bb8c093b 419 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
b481de9c
ZY		 420 rxq->dma_addr >> 8);
421
8b6eaea8 422 /* Tell device where in DRAM to update its Rx status */
bb8c093b 423 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
b481de9c 424 (priv->hw_setting.shared_phys +
bb8c093b 425 offsetof(struct iwl4965_shared, val0)) >> 4);
b481de9c 426
8b6eaea8 427 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
bb8c093b 428 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
b481de9c
ZY		 429 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
430 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
9ee1ba47 431 rb_size |
b481de9c
ZY		 432 /*0x10 << 4 | */
433 (RX_QUEUE_SIZE_LOG <<
434 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
435
436 /*
bb8c093b 437 * iwl4965_write32(priv,CSR_INT_COAL_REG,0);
b481de9c
ZY		 438 */
439
bb8c093b 440 iwl4965_release_nic_access(priv);
b481de9c
ZY		 441 spin_unlock_irqrestore(&priv->lock, flags);
442
443 return 0;
444}
445
8b6eaea8 446/* Tell 4965 where to find the "keep warm" buffer */
c79dd5b5 447static int iwl4965_kw_init(struct iwl_priv *priv)
b481de9c
ZY		 448{
449 unsigned long flags;
450 int rc;
451
452 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 453 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 454 if (rc)
455 goto out;
456
bb8c093b 457 iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
b481de9c 458 priv->kw.dma_addr >> 4);
bb8c093b 459 iwl4965_release_nic_access(priv);
b481de9c
ZY		 460out:
461 spin_unlock_irqrestore(&priv->lock, flags);
462 return rc;
463}
464
c79dd5b5 465static int iwl4965_kw_alloc(struct iwl_priv *priv)
b481de9c
ZY		 466{
467 struct pci_dev *dev = priv->pci_dev;
bb8c093b 468 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 469
470 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
471 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
472 if (!kw->v_addr)
473 return -ENOMEM;
474
475 return 0;
476}
477
8b6eaea8
CB		 478/**
479 * iwl4965_kw_free - Free the "keep warm" buffer
480 */
c79dd5b5 481static void iwl4965_kw_free(struct iwl_priv *priv)
b481de9c
ZY		 482{
483 struct pci_dev *dev = priv->pci_dev;
bb8c093b 484 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 485
486 if (kw->v_addr) {
487 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
488 memset(kw, 0, sizeof(*kw));
489 }
490}
491
492/**
493 * iwl4965_txq_ctx_reset - Reset TX queue context
494 * Destroys all DMA structures and initialise them again
495 *
496 * @param priv
497 * @return error code
498 */
c79dd5b5 499static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 500{
501 int rc = 0;
502 int txq_id, slots_num;
503 unsigned long flags;
504
505 iwl4965_kw_free(priv);
506
8b6eaea8 507 /* Free all tx/cmd queues and keep-warm buffer */
bb8c093b 508 iwl4965_hw_txq_ctx_free(priv);
b481de9c 509
8b6eaea8 510 /* Alloc keep-warm buffer */
b481de9c
ZY		 511 rc = iwl4965_kw_alloc(priv);
512 if (rc) {
513 IWL_ERROR("Keep Warm allocation failed");
514 goto error_kw;
515 }
516
517 spin_lock_irqsave(&priv->lock, flags);
518
bb8c093b 519 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 520 if (unlikely(rc)) {
521 IWL_ERROR("TX reset failed");
522 spin_unlock_irqrestore(&priv->lock, flags);
523 goto error_reset;
524 }
525
8b6eaea8 526 /* Turn off all Tx DMA channels */
bb8c093b
CH		 527 iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0);
528 iwl4965_release_nic_access(priv);
b481de9c
ZY		 529 spin_unlock_irqrestore(&priv->lock, flags);
530
8b6eaea8 531 /* Tell 4965 where to find the keep-warm buffer */
b481de9c
ZY		 532 rc = iwl4965_kw_init(priv);
533 if (rc) {
534 IWL_ERROR("kw_init failed\n");
535 goto error_reset;
536 }
537
8b6eaea8
CB		 538 /* Alloc and init all (default 16) Tx queues,
539 * including the command queue (#4) */
b481de9c
ZY		 540 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
541 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
542 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 543 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 544 txq_id);
545 if (rc) {
546 IWL_ERROR("Tx %d queue init failed\n", txq_id);
547 goto error;
548 }
549 }
550
551 return rc;
552
553 error:
bb8c093b 554 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 555 error_reset:
556 iwl4965_kw_free(priv);
557 error_kw:
558 return rc;
559}
560
c79dd5b5 561int iwl4965_hw_nic_init(struct iwl_priv *priv)
b481de9c
ZY		 562{
563 int rc;
564 unsigned long flags;
bb8c093b 565 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 566 u8 rev_id;
567 u32 val;
568 u8 val_link;
569
bb8c093b 570 iwl4965_power_init_handle(priv);
b481de9c
ZY		 571
572 /* nic_init */
573 spin_lock_irqsave(&priv->lock, flags);
574
bb8c093b 575 iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 576 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
577
bb8c093b
CH		 578 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
579 rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 580 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
581 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
582 if (rc < 0) {
583 spin_unlock_irqrestore(&priv->lock, flags);
584 IWL_DEBUG_INFO("Failed to init the card\n");
585 return rc;
586 }
587
bb8c093b 588 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 589 if (rc) {
590 spin_unlock_irqrestore(&priv->lock, flags);
591 return rc;
592 }
593
bb8c093b 594 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c 595
bb8c093b 596 iwl4965_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 597 APMG_CLK_VAL_DMA_CLK_RQT |
598 APMG_CLK_VAL_BSM_CLK_RQT);
bb8c093b 599 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c
ZY		 600
601 udelay(20);
602
bb8c093b 603 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c
ZY		 604 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
605
bb8c093b
CH		 606 iwl4965_release_nic_access(priv);
607 iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32);
b481de9c
ZY		 608 spin_unlock_irqrestore(&priv->lock, flags);
609
610 /* Determine HW type */
611 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
612 if (rc)
613 return rc;
614
615 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
616
617 iwl4965_nic_set_pwr_src(priv, 1);
618 spin_lock_irqsave(&priv->lock, flags);
619
620 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
621 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
622 /* Enable No Snoop field */
623 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
624 val & ~(1 << 11));
625 }
626
627 spin_unlock_irqrestore(&priv->lock, flags);
628
b481de9c
ZY		 629 if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
630 IWL_ERROR("Older EEPROM detected! Aborting.\n");
631 return -EINVAL;
632 }
633
634 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
635
636 /* disable L1 entry -- workaround for pre-B1 */
637 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
638
639 spin_lock_irqsave(&priv->lock, flags);
640
641 /* set CSR_HW_CONFIG_REG for uCode use */
642
9f6adf23 643 iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1
TW		 644 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
645 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
646 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 647
bb8c093b 648 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 649 if (rc < 0) {
650 spin_unlock_irqrestore(&priv->lock, flags);
651 IWL_DEBUG_INFO("Failed to init the card\n");
652 return rc;
653 }
654
bb8c093b
CH		 655 iwl4965_read_prph(priv, APMG_PS_CTRL_REG);
656 iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 657 APMG_PS_CTRL_VAL_RESET_REQ);
658 udelay(5);
bb8c093b 659 iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 660 APMG_PS_CTRL_VAL_RESET_REQ);
661
bb8c093b 662 iwl4965_release_nic_access(priv);
b481de9c
ZY		 663 spin_unlock_irqrestore(&priv->lock, flags);
664
bb8c093b 665 iwl4965_hw_card_show_info(priv);
b481de9c
ZY		 666
667 /* end nic_init */
668
669 /* Allocate the RX queue, or reset if it is already allocated */
670 if (!rxq->bd) {
bb8c093b 671 rc = iwl4965_rx_queue_alloc(priv);
b481de9c
ZY		 672 if (rc) {
673 IWL_ERROR("Unable to initialize Rx queue\n");
674 return -ENOMEM;
675 }
676 } else
bb8c093b 677 iwl4965_rx_queue_reset(priv, rxq);
b481de9c 678
bb8c093b 679 iwl4965_rx_replenish(priv);
b481de9c
ZY		 680
681 iwl4965_rx_init(priv, rxq);
682
683 spin_lock_irqsave(&priv->lock, flags);
684
685 rxq->need_update = 1;
bb8c093b 686 iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 687
688 spin_unlock_irqrestore(&priv->lock, flags);
8b6eaea8
CB		 689
690 /* Allocate and init all Tx and Command queues */
b481de9c
ZY		 691 rc = iwl4965_txq_ctx_reset(priv);
692 if (rc)
693 return rc;
694
695 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
696 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
697
698 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
699 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
700
701 set_bit(STATUS_INIT, &priv->status);
702
703 return 0;
704}
705
c79dd5b5 706int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 707{
708 int rc = 0;
709 u32 reg_val;
710 unsigned long flags;
711
712 spin_lock_irqsave(&priv->lock, flags);
713
714 /* set stop master bit */
bb8c093b 715 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 716
bb8c093b 717 reg_val = iwl4965_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 718
719 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
720 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
721 IWL_DEBUG_INFO("Card in power save, master is already "
722 "stopped\n");
723 else {
bb8c093b 724 rc = iwl4965_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 725 CSR_RESET_REG_FLAG_MASTER_DISABLED,
726 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
727 if (rc < 0) {
728 spin_unlock_irqrestore(&priv->lock, flags);
729 return rc;
730 }
731 }
732
733 spin_unlock_irqrestore(&priv->lock, flags);
734 IWL_DEBUG_INFO("stop master\n");
735
736 return rc;
737}
738
8b6eaea8
CB		 739/**
740 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
741 */
c79dd5b5 742void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c
ZY		 743{
744
745 int txq_id;
746 unsigned long flags;
747
8b6eaea8 748 /* Stop each Tx DMA channel, and wait for it to be idle */
b481de9c
ZY		 749 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
750 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 751 if (iwl4965_grab_nic_access(priv)) {
b481de9c
ZY		 752 spin_unlock_irqrestore(&priv->lock, flags);
753 continue;
754 }
755
bb8c093b 756 iwl4965_write_direct32(priv,
b481de9c
ZY		 757 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
758 0x0);
bb8c093b 759 iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
b481de9c
ZY		 760 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
761 (txq_id), 200);
bb8c093b 762 iwl4965_release_nic_access(priv);
b481de9c
ZY		 763 spin_unlock_irqrestore(&priv->lock, flags);
764 }
765
8b6eaea8 766 /* Deallocate memory for all Tx queues */
bb8c093b 767 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 768}
769
c79dd5b5 770int iwl4965_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 771{
772 int rc = 0;
773 unsigned long flags;
774
bb8c093b 775 iwl4965_hw_nic_stop_master(priv);
b481de9c
ZY		 776
777 spin_lock_irqsave(&priv->lock, flags);
778
bb8c093b 779 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 780
781 udelay(10);
782
bb8c093b
CH		 783 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
784 rc = iwl4965_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 785 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
786 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
787
788 udelay(10);
789
bb8c093b 790 rc = iwl4965_grab_nic_access(priv);
b481de9c 791 if (!rc) {
bb8c093b 792 iwl4965_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 793 APMG_CLK_VAL_DMA_CLK_RQT |
794 APMG_CLK_VAL_BSM_CLK_RQT);
795
796 udelay(10);
797
bb8c093b 798 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c
ZY		 799 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
800
bb8c093b 801 iwl4965_release_nic_access(priv);
b481de9c
ZY		 802 }
803
804 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
805 wake_up_interruptible(&priv->wait_command_queue);
806
807 spin_unlock_irqrestore(&priv->lock, flags);
808
809 return rc;
810
811}
812
813#define REG_RECALIB_PERIOD (60)
814
815/**
816 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
817 *
818 * This callback is provided in order to queue the statistics_work
819 * in work_queue context (v. softirq)
820 *
821 * This timer function is continually reset to execute within
822 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
823 * was received. We need to ensure we receive the statistics in order
824 * to update the temperature used for calibrating the TXPOWER. However,
825 * we can't send the statistics command from softirq context (which
826 * is the context which timers run at) so we have to queue off the
827 * statistics_work to actually send the command to the hardware.
828 */
829static void iwl4965_bg_statistics_periodic(unsigned long data)
830{
c79dd5b5 831 struct iwl_priv *priv = (struct iwl_priv *)data;
b481de9c
ZY		 832
833 queue_work(priv->workqueue, &priv->statistics_work);
834}
835
836/**
837 * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
838 *
bb8c093b 839 * This is queued by iwl4965_bg_statistics_periodic.
b481de9c
ZY		 840 */
841static void iwl4965_bg_statistics_work(struct work_struct *work)
842{
c79dd5b5 843 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 844 statistics_work);
845
846 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
847 return;
848
849 mutex_lock(&priv->mutex);
bb8c093b 850 iwl4965_send_statistics_request(priv);
b481de9c
ZY		 851 mutex_unlock(&priv->mutex);
852}
853
854#define CT_LIMIT_CONST 259
855#define TM_CT_KILL_THRESHOLD 110
856
c79dd5b5 857void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 858{
bb8c093b 859 struct iwl4965_ct_kill_config cmd;
b481de9c
ZY		 860 u32 R1, R2, R3;
861 u32 temp_th;
862 u32 crit_temperature;
863 unsigned long flags;
864 int rc = 0;
865
866 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 867 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 868 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
869 spin_unlock_irqrestore(&priv->lock, flags);
870
871 if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
872 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
873 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
874 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
875 } else {
876 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
877 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
878 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
879 }
880
881 temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
882
883 crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
884 cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
bb8c093b 885 rc = iwl4965_send_cmd_pdu(priv,
b481de9c
ZY		 886 REPLY_CT_KILL_CONFIG_CMD, sizeof(cmd), &cmd);
887 if (rc)
888 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
889 else
890 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
891}
892
c8b0e6e1 893#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 894
895/* "false alarms" are signals that our DSP tries to lock onto,
896 * but then determines that they are either noise, or transmissions
897 * from a distant wireless network (also "noise", really) that get
898 * "stepped on" by stronger transmissions within our own network.
899 * This algorithm attempts to set a sensitivity level that is high
900 * enough to receive all of our own network traffic, but not so
901 * high that our DSP gets too busy trying to lock onto non-network
902 * activity/noise. */
c79dd5b5 903static int iwl4965_sens_energy_cck(struct iwl_priv *priv,
b481de9c
ZY		 904 u32 norm_fa,
905 u32 rx_enable_time,
906 struct statistics_general_data *rx_info)
907{
908 u32 max_nrg_cck = 0;
909 int i = 0;
910 u8 max_silence_rssi = 0;
911 u32 silence_ref = 0;
912 u8 silence_rssi_a = 0;
913 u8 silence_rssi_b = 0;
914 u8 silence_rssi_c = 0;
915 u32 val;
916
917 /* "false_alarms" values below are cross-multiplications to assess the
918 * numbers of false alarms within the measured period of actual Rx
919 * (Rx is off when we're txing), vs the min/max expected false alarms
920 * (some should be expected if rx is sensitive enough) in a
921 * hypothetical listening period of 200 time units (TU), 204.8 msec:
922 *
923 * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
924 *
925 * */
926 u32 false_alarms = norm_fa * 200 * 1024;
927 u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
928 u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
bb8c093b 929 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 930
931 data = &(priv->sensitivity_data);
932
933 data->nrg_auto_corr_silence_diff = 0;
934
935 /* Find max silence rssi among all 3 receivers.
936 * This is background noise, which may include transmissions from other
937 * networks, measured during silence before our network's beacon */
938 silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
8a1b0245 939 ALL_BAND_FILTER) >> 8);
b481de9c 940 silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
8a1b0245 941 ALL_BAND_FILTER) >> 8);
b481de9c 942 silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
8a1b0245 943 ALL_BAND_FILTER) >> 8);
b481de9c
ZY		 944
945 val = max(silence_rssi_b, silence_rssi_c);
946 max_silence_rssi = max(silence_rssi_a, (u8) val);
947
948 /* Store silence rssi in 20-beacon history table */
949 data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
950 data->nrg_silence_idx++;
951 if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
952 data->nrg_silence_idx = 0;
953
954 /* Find max silence rssi across 20 beacon history */
955 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
956 val = data->nrg_silence_rssi[i];
957 silence_ref = max(silence_ref, val);
958 }
959 IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
960 silence_rssi_a, silence_rssi_b, silence_rssi_c,
961 silence_ref);
962
963 /* Find max rx energy (min value!) among all 3 receivers,
964 * measured during beacon frame.
965 * Save it in 10-beacon history table. */
966 i = data->nrg_energy_idx;
967 val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
968 data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
969
970 data->nrg_energy_idx++;
971 if (data->nrg_energy_idx >= 10)
972 data->nrg_energy_idx = 0;
973
974 /* Find min rx energy (max value) across 10 beacon history.
975 * This is the minimum signal level that we want to receive well.
976 * Add backoff (margin so we don't miss slightly lower energy frames).
977 * This establishes an upper bound (min value) for energy threshold. */
978 max_nrg_cck = data->nrg_value[0];
979 for (i = 1; i < 10; i++)
980 max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
981 max_nrg_cck += 6;
982
983 IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
984 rx_info->beacon_energy_a, rx_info->beacon_energy_b,
985 rx_info->beacon_energy_c, max_nrg_cck - 6);
986
987 /* Count number of consecutive beacons with fewer-than-desired
988 * false alarms. */
989 if (false_alarms < min_false_alarms)
990 data->num_in_cck_no_fa++;
991 else
992 data->num_in_cck_no_fa = 0;
993 IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
994 data->num_in_cck_no_fa);
995
996 /* If we got too many false alarms this time, reduce sensitivity */
997 if (false_alarms > max_false_alarms) {
998 IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
999 false_alarms, max_false_alarms);
1000 IWL_DEBUG_CALIB("... reducing sensitivity\n");
1001 data->nrg_curr_state = IWL_FA_TOO_MANY;
1002
1003 if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
1004 /* Store for "fewer than desired" on later beacon */
1005 data->nrg_silence_ref = silence_ref;
1006
1007 /* increase energy threshold (reduce nrg value)
1008 * to decrease sensitivity */
1009 if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
1010 data->nrg_th_cck = data->nrg_th_cck
1011 - NRG_STEP_CCK;
1012 }
1013
1014 /* increase auto_corr values to decrease sensitivity */
1015 if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
1016 data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
1017 else {
1018 val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
1019 data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
1020 }
1021 val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
1022 data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
1023
1024 /* Else if we got fewer than desired, increase sensitivity */
1025 } else if (false_alarms < min_false_alarms) {
1026 data->nrg_curr_state = IWL_FA_TOO_FEW;
1027
1028 /* Compare silence level with silence level for most recent
1029 * healthy number or too many false alarms */
1030 data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
1031 (s32)silence_ref;
1032
1033 IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
1034 false_alarms, min_false_alarms,
1035 data->nrg_auto_corr_silence_diff);
1036
1037 /* Increase value to increase sensitivity, but only if:
1038 * 1a) previous beacon did *not* have *too many* false alarms
1039 * 1b) AND there's a significant difference in Rx levels
1040 * from a previous beacon with too many, or healthy # FAs
1041 * OR 2) We've seen a lot of beacons (100) with too few
1042 * false alarms */
1043 if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
1044 ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
1045 (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
1046
1047 IWL_DEBUG_CALIB("... increasing sensitivity\n");
1048 /* Increase nrg value to increase sensitivity */
1049 val = data->nrg_th_cck + NRG_STEP_CCK;
1050 data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
1051
1052 /* Decrease auto_corr values to increase sensitivity */
1053 val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
1054 data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
1055
1056 val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
1057 data->auto_corr_cck_mrc =
1058 max((u32)AUTO_CORR_MIN_CCK_MRC, val);
1059
1060 } else
1061 IWL_DEBUG_CALIB("... but not changing sensitivity\n");
1062
1063 /* Else we got a healthy number of false alarms, keep status quo */
1064 } else {
1065 IWL_DEBUG_CALIB(" FA in safe zone\n");
1066 data->nrg_curr_state = IWL_FA_GOOD_RANGE;
1067
1068 /* Store for use in "fewer than desired" with later beacon */
1069 data->nrg_silence_ref = silence_ref;
1070
1071 /* If previous beacon had too many false alarms,
1072 * give it some extra margin by reducing sensitivity again
1073 * (but don't go below measured energy of desired Rx) */
1074 if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
1075 IWL_DEBUG_CALIB("... increasing margin\n");
1076 data->nrg_th_cck -= NRG_MARGIN;
1077 }
1078 }
1079
1080 /* Make sure the energy threshold does not go above the measured
1081 * energy of the desired Rx signals (reduced by backoff margin),
1082 * or else we might start missing Rx frames.
1083 * Lower value is higher energy, so we use max()!
1084 */
1085 data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
1086 IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
1087
1088 data->nrg_prev_state = data->nrg_curr_state;
1089
1090 return 0;
1091}
1092
1093
c79dd5b5 1094static int iwl4965_sens_auto_corr_ofdm(struct iwl_priv *priv,
b481de9c
ZY		 1095 u32 norm_fa,
1096 u32 rx_enable_time)
1097{
1098 u32 val;
1099 u32 false_alarms = norm_fa * 200 * 1024;
1100 u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
1101 u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
bb8c093b 1102 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1103
1104 data = &(priv->sensitivity_data);
1105
1106 /* If we got too many false alarms this time, reduce sensitivity */
1107 if (false_alarms > max_false_alarms) {
1108
1109 IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
1110 false_alarms, max_false_alarms);
1111
1112 val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
1113 data->auto_corr_ofdm =
1114 min((u32)AUTO_CORR_MAX_OFDM, val);
1115
1116 val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
1117 data->auto_corr_ofdm_mrc =
1118 min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
1119
1120 val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
1121 data->auto_corr_ofdm_x1 =
1122 min((u32)AUTO_CORR_MAX_OFDM_X1, val);
1123
1124 val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
1125 data->auto_corr_ofdm_mrc_x1 =
1126 min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
1127 }
1128
1129 /* Else if we got fewer than desired, increase sensitivity */
1130 else if (false_alarms < min_false_alarms) {
1131
1132 IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
1133 false_alarms, min_false_alarms);
1134
1135 val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
1136 data->auto_corr_ofdm =
1137 max((u32)AUTO_CORR_MIN_OFDM, val);
1138
1139 val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
1140 data->auto_corr_ofdm_mrc =
1141 max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
1142
1143 val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
1144 data->auto_corr_ofdm_x1 =
1145 max((u32)AUTO_CORR_MIN_OFDM_X1, val);
1146
1147 val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
1148 data->auto_corr_ofdm_mrc_x1 =
1149 max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
1150 }
1151
1152 else
1153 IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
1154 min_false_alarms, false_alarms, max_false_alarms);
1155
1156 return 0;
1157}
1158
c79dd5b5 1159static int iwl4965_sensitivity_callback(struct iwl_priv *priv,
bb8c093b 1160 struct iwl4965_cmd *cmd, struct sk_buff *skb)
b481de9c
ZY		 1161{
1162 /* We didn't cache the SKB; let the caller free it */
1163 return 1;
1164}
1165
1166/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
c79dd5b5 1167static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
b481de9c
ZY		 1168{
1169 int rc = 0;
bb8c093b
CH		 1170 struct iwl4965_sensitivity_cmd cmd ;
1171 struct iwl4965_sensitivity_data *data = NULL;
1172 struct iwl4965_host_cmd cmd_out = {
b481de9c 1173 .id = SENSITIVITY_CMD,
bb8c093b 1174 .len = sizeof(struct iwl4965_sensitivity_cmd),
b481de9c
ZY		 1175 .meta.flags = flags,
1176 .data = &cmd,
1177 };
1178
1179 data = &(priv->sensitivity_data);
1180
1181 memset(&cmd, 0, sizeof(cmd));
1182
1183 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
1184 cpu_to_le16((u16)data->auto_corr_ofdm);
1185 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
1186 cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
1187 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
1188 cpu_to_le16((u16)data->auto_corr_ofdm_x1);
1189 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
1190 cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
1191
1192 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
1193 cpu_to_le16((u16)data->auto_corr_cck);
1194 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
1195 cpu_to_le16((u16)data->auto_corr_cck_mrc);
1196
1197 cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
1198 cpu_to_le16((u16)data->nrg_th_cck);
1199 cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
1200 cpu_to_le16((u16)data->nrg_th_ofdm);
1201
1202 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
1203 __constant_cpu_to_le16(190);
1204 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
1205 __constant_cpu_to_le16(390);
1206 cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
1207 __constant_cpu_to_le16(62);
1208
1209 IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
1210 data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
1211 data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
1212 data->nrg_th_ofdm);
1213
1214 IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
1215 data->auto_corr_cck, data->auto_corr_cck_mrc,
1216 data->nrg_th_cck);
1217
f7d09d7c 1218 /* Update uCode's "work" table, and copy it to DSP */
b481de9c
ZY		 1219 cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
1220
1221 if (flags & CMD_ASYNC)
bb8c093b 1222 cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
b481de9c
ZY		 1223
1224 /* Don't send command to uCode if nothing has changed */
1225 if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
1226 sizeof(u16)*HD_TABLE_SIZE)) {
1227 IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
1228 return 0;
1229 }
1230
1231 /* Copy table for comparison next time */
1232 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
1233 sizeof(u16)*HD_TABLE_SIZE);
1234
bb8c093b 1235 rc = iwl4965_send_cmd(priv, &cmd_out);
b481de9c
ZY		 1236 if (!rc) {
1237 IWL_DEBUG_CALIB("SENSITIVITY_CMD succeeded\n");
1238 return rc;
1239 }
1240
1241 return 0;
1242}
1243
c79dd5b5 1244void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
b481de9c
ZY		 1245{
1246 int rc = 0;
1247 int i;
bb8c093b 1248 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1249
1250 IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
1251
1252 if (force)
1253 memset(&(priv->sensitivity_tbl[0]), 0,
1254 sizeof(u16)*HD_TABLE_SIZE);
1255
1256 /* Clear driver's sensitivity algo data */
1257 data = &(priv->sensitivity_data);
bb8c093b 1258 memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
b481de9c
ZY		 1259
1260 data->num_in_cck_no_fa = 0;
1261 data->nrg_curr_state = IWL_FA_TOO_MANY;
1262 data->nrg_prev_state = IWL_FA_TOO_MANY;
1263 data->nrg_silence_ref = 0;
1264 data->nrg_silence_idx = 0;
1265 data->nrg_energy_idx = 0;
1266
1267 for (i = 0; i < 10; i++)
1268 data->nrg_value[i] = 0;
1269
1270 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
1271 data->nrg_silence_rssi[i] = 0;
1272
1273 data->auto_corr_ofdm = 90;
1274 data->auto_corr_ofdm_mrc = 170;
1275 data->auto_corr_ofdm_x1 = 105;
1276 data->auto_corr_ofdm_mrc_x1 = 220;
1277 data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
1278 data->auto_corr_cck_mrc = 200;
1279 data->nrg_th_cck = 100;
1280 data->nrg_th_ofdm = 100;
1281
1282 data->last_bad_plcp_cnt_ofdm = 0;
1283 data->last_fa_cnt_ofdm = 0;
1284 data->last_bad_plcp_cnt_cck = 0;
1285 data->last_fa_cnt_cck = 0;
1286
1287 /* Clear prior Sensitivity command data to force send to uCode */
1288 if (force)
1289 memset(&(priv->sensitivity_tbl[0]), 0,
1290 sizeof(u16)*HD_TABLE_SIZE);
1291
1292 rc |= iwl4965_sensitivity_write(priv, flags);
1293 IWL_DEBUG_CALIB("<<return 0x%X\n", rc);
1294
1295 return;
1296}
1297
1298
1299/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1300 * Called after every association, but this runs only once!
1301 * ... once chain noise is calibrated the first time, it's good forever. */
c79dd5b5 1302void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 1303{
bb8c093b 1304 struct iwl4965_chain_noise_data *data = NULL;
b481de9c
ZY		 1305 int rc = 0;
1306
1307 data = &(priv->chain_noise_data);
bb8c093b
CH		 1308 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl4965_is_associated(priv)) {
1309 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1310
1311 memset(&cmd, 0, sizeof(cmd));
1312 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1313 cmd.diff_gain_a = 0;
1314 cmd.diff_gain_b = 0;
1315 cmd.diff_gain_c = 0;
bb8c093b 1316 rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
b481de9c
ZY		 1317 sizeof(cmd), &cmd);
1318 msleep(4);
1319 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1320 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1321 }
1322 return;
1323}
1324
1325/*
1326 * Accumulate 20 beacons of signal and noise statistics for each of
1327 * 3 receivers/antennas/rx-chains, then figure out:
1328 * 1) Which antennas are connected.
1329 * 2) Differential rx gain settings to balance the 3 receivers.
1330 */
c79dd5b5 1331static void iwl4965_noise_calibration(struct iwl_priv *priv,
bb8c093b 1332 struct iwl4965_notif_statistics *stat_resp)
b481de9c 1333{
bb8c093b 1334 struct iwl4965_chain_noise_data *data = NULL;
b481de9c
ZY		 1335 int rc = 0;
1336
1337 u32 chain_noise_a;
1338 u32 chain_noise_b;
1339 u32 chain_noise_c;
1340 u32 chain_sig_a;
1341 u32 chain_sig_b;
1342 u32 chain_sig_c;
1343 u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1344 u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1345 u32 max_average_sig;
1346 u16 max_average_sig_antenna_i;
1347 u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
1348 u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
1349 u16 i = 0;
1350 u16 chan_num = INITIALIZATION_VALUE;
1351 u32 band = INITIALIZATION_VALUE;
1352 u32 active_chains = 0;
1353 unsigned long flags;
1354 struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
1355
1356 data = &(priv->chain_noise_data);
1357
1358 /* Accumulate just the first 20 beacons after the first association,
1359 * then we're done forever. */
1360 if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
1361 if (data->state == IWL_CHAIN_NOISE_ALIVE)
1362 IWL_DEBUG_CALIB("Wait for noise calib reset\n");
1363 return;
1364 }
1365
1366 spin_lock_irqsave(&priv->lock, flags);
1367 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1368 IWL_DEBUG_CALIB(" << Interference data unavailable\n");
1369 spin_unlock_irqrestore(&priv->lock, flags);
1370 return;
1371 }
1372
1373 band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
1374 chan_num = le16_to_cpu(priv->staging_rxon.channel);
1375
1376 /* Make sure we accumulate data for just the associated channel
1377 * (even if scanning). */
1378 if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
1379 ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
1380 (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
1381 IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
1382 chan_num, band);
1383 spin_unlock_irqrestore(&priv->lock, flags);
1384 return;
1385 }
1386
1387 /* Accumulate beacon statistics values across 20 beacons */
1388 chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
1389 IN_BAND_FILTER;
1390 chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
1391 IN_BAND_FILTER;
1392 chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
1393 IN_BAND_FILTER;
1394
1395 chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
1396 chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
1397 chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
1398
1399 spin_unlock_irqrestore(&priv->lock, flags);
1400
1401 data->beacon_count++;
1402
1403 data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
1404 data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
1405 data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
1406
1407 data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
1408 data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
1409 data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
1410
1411 IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
1412 data->beacon_count);
1413 IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
1414 chain_sig_a, chain_sig_b, chain_sig_c);
1415 IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
1416 chain_noise_a, chain_noise_b, chain_noise_c);
1417
1418 /* If this is the 20th beacon, determine:
1419 * 1) Disconnected antennas (using signal strengths)
1420 * 2) Differential gain (using silence noise) to balance receivers */
1421 if (data->beacon_count == CAL_NUM_OF_BEACONS) {
1422
1423 /* Analyze signal for disconnected antenna */
1424 average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
1425 average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
1426 average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
1427
1428 if (average_sig[0] >= average_sig[1]) {
1429 max_average_sig = average_sig[0];
1430 max_average_sig_antenna_i = 0;
1431 active_chains = (1 << max_average_sig_antenna_i);
1432 } else {
1433 max_average_sig = average_sig[1];
1434 max_average_sig_antenna_i = 1;
1435 active_chains = (1 << max_average_sig_antenna_i);
1436 }
1437
1438 if (average_sig[2] >= max_average_sig) {
1439 max_average_sig = average_sig[2];
1440 max_average_sig_antenna_i = 2;
1441 active_chains = (1 << max_average_sig_antenna_i);
1442 }
1443
1444 IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
1445 average_sig[0], average_sig[1], average_sig[2]);
1446 IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
1447 max_average_sig, max_average_sig_antenna_i);
1448
1449 /* Compare signal strengths for all 3 receivers. */
1450 for (i = 0; i < NUM_RX_CHAINS; i++) {
1451 if (i != max_average_sig_antenna_i) {
1452 s32 rssi_delta = (max_average_sig -
1453 average_sig[i]);
1454
1455 /* If signal is very weak, compared with
1456 * strongest, mark it as disconnected. */
1457 if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
1458 data->disconn_array[i] = 1;
1459 else
1460 active_chains |= (1 << i);
1461 IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
1462 "disconn_array[i] = %d\n",
1463 i, rssi_delta, data->disconn_array[i]);
1464 }
1465 }
1466
1467 /*If both chains A & B are disconnected -
1468 * connect B and leave A as is */
1469 if (data->disconn_array[CHAIN_A] &&
1470 data->disconn_array[CHAIN_B]) {
1471 data->disconn_array[CHAIN_B] = 0;
1472 active_chains |= (1 << CHAIN_B);
1473 IWL_DEBUG_CALIB("both A & B chains are disconnected! "
1474 "W/A - declare B as connected\n");
1475 }
1476
1477 IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
1478 active_chains);
1479
1480 /* Save for use within RXON, TX, SCAN commands, etc. */
1481 priv->valid_antenna = active_chains;
1482
1483 /* Analyze noise for rx balance */
1484 average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
1485 average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
1486 average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
1487
1488 for (i = 0; i < NUM_RX_CHAINS; i++) {
1489 if (!(data->disconn_array[i]) &&
1490 (average_noise[i] <= min_average_noise)) {
1491 /* This means that chain i is active and has
1492 * lower noise values so far: */
1493 min_average_noise = average_noise[i];
1494 min_average_noise_antenna_i = i;
1495 }
1496 }
1497
1498 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1499
1500 IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
1501 average_noise[0], average_noise[1],
1502 average_noise[2]);
1503
1504 IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
1505 min_average_noise, min_average_noise_antenna_i);
1506
1507 for (i = 0; i < NUM_RX_CHAINS; i++) {
1508 s32 delta_g = 0;
1509
1510 if (!(data->disconn_array[i]) &&
1511 (data->delta_gain_code[i] ==
1512 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1513 delta_g = average_noise[i] - min_average_noise;
1514 data->delta_gain_code[i] = (u8)((delta_g *
1515 10) / 15);
1516 if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
1517 data->delta_gain_code[i])
1518 data->delta_gain_code[i] =
1519 CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
1520
1521 data->delta_gain_code[i] =
1522 (data->delta_gain_code[i] | (1 << 2));
1523 } else
1524 data->delta_gain_code[i] = 0;
1525 }
1526 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1527 data->delta_gain_code[0],
1528 data->delta_gain_code[1],
1529 data->delta_gain_code[2]);
1530
1531 /* Differential gain gets sent to uCode only once */
1532 if (!data->radio_write) {
bb8c093b 1533 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1534 data->radio_write = 1;
1535
1536 memset(&cmd, 0, sizeof(cmd));
1537 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1538 cmd.diff_gain_a = data->delta_gain_code[0];
1539 cmd.diff_gain_b = data->delta_gain_code[1];
1540 cmd.diff_gain_c = data->delta_gain_code[2];
bb8c093b 1541 rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
b481de9c
ZY		 1542 sizeof(cmd), &cmd);
1543 if (rc)
1544 IWL_DEBUG_CALIB("fail sending cmd "
1545 "REPLY_PHY_CALIBRATION_CMD \n");
1546
1547 /* TODO we might want recalculate
1548 * rx_chain in rxon cmd */
1549
1550 /* Mark so we run this algo only once! */
1551 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1552 }
1553 data->chain_noise_a = 0;
1554 data->chain_noise_b = 0;
1555 data->chain_noise_c = 0;
1556 data->chain_signal_a = 0;
1557 data->chain_signal_b = 0;
1558 data->chain_signal_c = 0;
1559 data->beacon_count = 0;
1560 }
1561 return;
1562}
1563
c79dd5b5 1564static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
bb8c093b 1565 struct iwl4965_notif_statistics *resp)
b481de9c
ZY		 1566{
1567 int rc = 0;
1568 u32 rx_enable_time;
1569 u32 fa_cck;
1570 u32 fa_ofdm;
1571 u32 bad_plcp_cck;
1572 u32 bad_plcp_ofdm;
1573 u32 norm_fa_ofdm;
1574 u32 norm_fa_cck;
bb8c093b 1575 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1576 struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
1577 struct statistics_rx *statistics = &(resp->rx);
1578 unsigned long flags;
1579 struct statistics_general_data statis;
1580
1581 data = &(priv->sensitivity_data);
1582
bb8c093b 1583 if (!iwl4965_is_associated(priv)) {
b481de9c
ZY		 1584 IWL_DEBUG_CALIB("<< - not associated\n");
1585 return;
1586 }
1587
1588 spin_lock_irqsave(&priv->lock, flags);
1589 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1590 IWL_DEBUG_CALIB("<< invalid data.\n");
1591 spin_unlock_irqrestore(&priv->lock, flags);
1592 return;
1593 }
1594
1595 /* Extract Statistics: */
1596 rx_enable_time = le32_to_cpu(rx_info->channel_load);
1597 fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
1598 fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
1599 bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
1600 bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
1601
1602 statis.beacon_silence_rssi_a =
1603 le32_to_cpu(statistics->general.beacon_silence_rssi_a);
1604 statis.beacon_silence_rssi_b =
1605 le32_to_cpu(statistics->general.beacon_silence_rssi_b);
1606 statis.beacon_silence_rssi_c =
1607 le32_to_cpu(statistics->general.beacon_silence_rssi_c);
1608 statis.beacon_energy_a =
1609 le32_to_cpu(statistics->general.beacon_energy_a);
1610 statis.beacon_energy_b =
1611 le32_to_cpu(statistics->general.beacon_energy_b);
1612 statis.beacon_energy_c =
1613 le32_to_cpu(statistics->general.beacon_energy_c);
1614
1615 spin_unlock_irqrestore(&priv->lock, flags);
1616
1617 IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
1618
1619 if (!rx_enable_time) {
1620 IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
1621 return;
1622 }
1623
1624 /* These statistics increase monotonically, and do not reset
1625 * at each beacon. Calculate difference from last value, or just
1626 * use the new statistics value if it has reset or wrapped around. */
1627 if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
1628 data->last_bad_plcp_cnt_cck = bad_plcp_cck;
1629 else {
1630 bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
1631 data->last_bad_plcp_cnt_cck += bad_plcp_cck;
1632 }
1633
1634 if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
1635 data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
1636 else {
1637 bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
1638 data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
1639 }
1640
1641 if (data->last_fa_cnt_ofdm > fa_ofdm)
1642 data->last_fa_cnt_ofdm = fa_ofdm;
1643 else {
1644 fa_ofdm -= data->last_fa_cnt_ofdm;
1645 data->last_fa_cnt_ofdm += fa_ofdm;
1646 }
1647
1648 if (data->last_fa_cnt_cck > fa_cck)
1649 data->last_fa_cnt_cck = fa_cck;
1650 else {
1651 fa_cck -= data->last_fa_cnt_cck;
1652 data->last_fa_cnt_cck += fa_cck;
1653 }
1654
1655 /* Total aborted signal locks */
1656 norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
1657 norm_fa_cck = fa_cck + bad_plcp_cck;
1658
1659 IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
1660 bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
1661
1662 iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
1663 iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
1664 rc |= iwl4965_sensitivity_write(priv, CMD_ASYNC);
1665
1666 return;
1667}
1668
1669static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1670{
c79dd5b5 1671 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1672 sensitivity_work);
1673
1674 mutex_lock(&priv->mutex);
1675
1676 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1677 test_bit(STATUS_SCANNING, &priv->status)) {
1678 mutex_unlock(&priv->mutex);
1679 return;
1680 }
1681
1682 if (priv->start_calib) {
1683 iwl4965_noise_calibration(priv, &priv->statistics);
1684
1685 if (priv->sensitivity_data.state ==
1686 IWL_SENS_CALIB_NEED_REINIT) {
1687 iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
1688 priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
1689 } else
1690 iwl4965_sensitivity_calibration(priv,
1691 &priv->statistics);
1692 }
1693
1694 mutex_unlock(&priv->mutex);
1695 return;
1696}
c8b0e6e1 1697#endif /*CONFIG_IWL4965_SENSITIVITY*/
b481de9c
ZY		 1698
1699static void iwl4965_bg_txpower_work(struct work_struct *work)
1700{
c79dd5b5 1701 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1702 txpower_work);
1703
1704 /* If a scan happened to start before we got here
1705 * then just return; the statistics notification will
1706 * kick off another scheduled work to compensate for
1707 * any temperature delta we missed here. */
1708 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1709 test_bit(STATUS_SCANNING, &priv->status))
1710 return;
1711
1712 mutex_lock(&priv->mutex);
1713
1714 /* Regardless of if we are assocaited, we must reconfigure the
1715 * TX power since frames can be sent on non-radar channels while
1716 * not associated */
bb8c093b 1717 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 1718
1719 /* Update last_temperature to keep is_calib_needed from running
1720 * when it isn't needed... */
1721 priv->last_temperature = priv->temperature;
1722
1723 mutex_unlock(&priv->mutex);
1724}
1725
1726/*
1727 * Acquire priv->lock before calling this function !
1728 */
c79dd5b5 1729static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 1730{
bb8c093b 1731 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 1732 (index & 0xff) | (txq_id << 8));
bb8c093b 1733 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 1734}
1735
8b6eaea8
CB		 1736/**
1737 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1738 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1739 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1740 *
1741 * NOTE: Acquire priv->lock before calling this function !
b481de9c 1742 */
c79dd5b5 1743static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
bb8c093b 1744 struct iwl4965_tx_queue *txq,
b481de9c
ZY		 1745 int tx_fifo_id, int scd_retry)
1746{
1747 int txq_id = txq->q.id;
8b6eaea8
CB		 1748
1749 /* Find out whether to activate Tx queue */
b481de9c
ZY		 1750 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1751
8b6eaea8 1752 /* Set up and activate */
bb8c093b 1753 iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
b481de9c
ZY		 1754 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1755 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1756 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1757 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1758 SCD_QUEUE_STTS_REG_MSK);
1759
1760 txq->sched_retry = scd_retry;
1761
1762 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 1763 active ? "Activate" : "Deactivate",
b481de9c
ZY		 1764 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1765}
1766
1767static const u16 default_queue_to_tx_fifo[] = {
1768 IWL_TX_FIFO_AC3,
1769 IWL_TX_FIFO_AC2,
1770 IWL_TX_FIFO_AC1,
1771 IWL_TX_FIFO_AC0,
1772 IWL_CMD_FIFO_NUM,
1773 IWL_TX_FIFO_HCCA_1,
1774 IWL_TX_FIFO_HCCA_2
1775};
1776
c79dd5b5 1777static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1778{
1779 set_bit(txq_id, &priv->txq_ctx_active_msk);
1780}
1781
c79dd5b5 1782static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1783{
1784 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1785}
1786
c79dd5b5 1787int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 1788{
1789 u32 a;
1790 int i = 0;
1791 unsigned long flags;
1792 int rc;
1793
1794 spin_lock_irqsave(&priv->lock, flags);
1795
c8b0e6e1 1796#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c 1797 memset(&(priv->sensitivity_data), 0,
bb8c093b 1798 sizeof(struct iwl4965_sensitivity_data));
b481de9c 1799 memset(&(priv->chain_noise_data), 0,
bb8c093b 1800 sizeof(struct iwl4965_chain_noise_data));
b481de9c
ZY		 1801 for (i = 0; i < NUM_RX_CHAINS; i++)
1802 priv->chain_noise_data.delta_gain_code[i] =
1803 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
c8b0e6e1 1804#endif /* CONFIG_IWL4965_SENSITIVITY*/
bb8c093b 1805 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 1806 if (rc) {
1807 spin_unlock_irqrestore(&priv->lock, flags);
1808 return rc;
1809 }
1810
8b6eaea8 1811 /* Clear 4965's internal Tx Scheduler data base */
bb8c093b 1812 priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
b481de9c
ZY		 1813 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1814 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
bb8c093b 1815 iwl4965_write_targ_mem(priv, a, 0);
b481de9c 1816 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
bb8c093b 1817 iwl4965_write_targ_mem(priv, a, 0);
b481de9c 1818 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
bb8c093b 1819 iwl4965_write_targ_mem(priv, a, 0);
b481de9c 1820
8b6eaea8 1821 /* Tel 4965 where to find Tx byte count tables */
bb8c093b 1822 iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
b481de9c 1823 (priv->hw_setting.shared_phys +
bb8c093b 1824 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 1825
1826 /* Disable chain mode for all queues */
bb8c093b 1827 iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
b481de9c 1828
8b6eaea8 1829 /* Initialize each Tx queue (including the command queue) */
b481de9c 1830 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
8b6eaea8
CB		 1831
1832 /* TFD circular buffer read/write indexes */
bb8c093b
CH		 1833 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
1834 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 1835
1836 /* Max Tx Window size for Scheduler-ACK mode */
bb8c093b 1837 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1838 SCD_CONTEXT_QUEUE_OFFSET(i),
1839 (SCD_WIN_SIZE <<
1840 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1841 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 1842
1843 /* Frame limit */
bb8c093b 1844 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1845 SCD_CONTEXT_QUEUE_OFFSET(i) +
1846 sizeof(u32),
1847 (SCD_FRAME_LIMIT <<
1848 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1849 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1850
1851 }
bb8c093b 1852 iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
b481de9c
ZY		 1853 (1 << priv->hw_setting.max_txq_num) - 1);
1854
8b6eaea8 1855 /* Activate all Tx DMA/FIFO channels */
bb8c093b 1856 iwl4965_write_prph(priv, KDR_SCD_TXFACT,
b481de9c
ZY		 1857 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1858
1859 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 1860
1861 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 1862 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1863 int ac = default_queue_to_tx_fifo[i];
1864 iwl4965_txq_ctx_activate(priv, i);
1865 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1866 }
1867
bb8c093b 1868 iwl4965_release_nic_access(priv);
b481de9c
ZY		 1869 spin_unlock_irqrestore(&priv->lock, flags);
1870
1871 return 0;
1872}
1873
8b6eaea8
CB		 1874/**
1875 * iwl4965_hw_set_hw_setting
1876 *
1877 * Called when initializing driver
1878 */
c79dd5b5 1879int iwl4965_hw_set_hw_setting(struct iwl_priv *priv)
b481de9c 1880{
316c30d9
AK		 1881 int ret = 0;
1882
00acbc91
AK		 1883 if ((iwl4965_mod_params.num_of_queues > IWL_MAX_NUM_QUEUES) ||
1884 (iwl4965_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9
AK		 1885 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
1886 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
1887 ret = -EINVAL;
1888 goto out;
1889 }
1890
8b6eaea8 1891 /* Allocate area for Tx byte count tables and Rx queue status */
b481de9c
ZY		 1892 priv->hw_setting.shared_virt =
1893 pci_alloc_consistent(priv->pci_dev,
bb8c093b 1894 sizeof(struct iwl4965_shared),
b481de9c
ZY		 1895 &priv->hw_setting.shared_phys);
1896
316c30d9
AK		 1897 if (!priv->hw_setting.shared_virt) {
1898 ret = -ENOMEM;
1899 goto out;
1900 }
b481de9c 1901
bb8c093b 1902 memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
b481de9c 1903
00acbc91 1904 priv->hw_setting.max_txq_num = iwl4965_mod_params.num_of_queues;
bb8c093b 1905 priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
b481de9c
ZY		 1906 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
1907 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
00acbc91 1908 if (iwl4965_mod_params.amsdu_size_8K)
9ee1ba47
RR		 1909 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1910 else
1911 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1912 priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
b481de9c
ZY		 1913 priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
1914 priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822
TW		 1915
1916 priv->hw_setting.tx_ant_num = 2;
1917
316c30d9
AK		 1918out:
1919 return ret;
b481de9c
ZY		 1920}
1921
1922/**
bb8c093b 1923 * iwl4965_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1924 *
1925 * Destroy all TX DMA queues and structures
1926 */
c79dd5b5 1927void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1928{
1929 int txq_id;
1930
1931 /* Tx queues */
1932 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
bb8c093b 1933 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c 1934
8b6eaea8 1935 /* Keep-warm buffer */
b481de9c
ZY		 1936 iwl4965_kw_free(priv);
1937}
1938
1939/**
8b6eaea8 1940 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
b481de9c 1941 *
8b6eaea8
CB		 1942 * Does NOT advance any TFD circular buffer read/write indexes
1943 * Does NOT free the TFD itself (which is within circular buffer)
b481de9c 1944 */
c79dd5b5 1945int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 1946{
bb8c093b
CH		 1947 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1948 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 1949 struct pci_dev *dev = priv->pci_dev;
1950 int i;
1951 int counter = 0;
1952 int index, is_odd;
1953
8b6eaea8 1954 /* Host command buffers stay mapped in memory, nothing to clean */
b481de9c 1955 if (txq->q.id == IWL_CMD_QUEUE_NUM)
b481de9c
ZY		 1956 return 0;
1957
8b6eaea8 1958 /* Sanity check on number of chunks */
b481de9c
ZY		 1959 counter = IWL_GET_BITS(*bd, num_tbs);
1960 if (counter > MAX_NUM_OF_TBS) {
1961 IWL_ERROR("Too many chunks: %i\n", counter);
1962 /* @todo issue fatal error, it is quite serious situation */
1963 return 0;
1964 }
1965
8b6eaea8
CB		 1966 /* Unmap chunks, if any.
1967 * TFD info for odd chunks is different format than for even chunks. */
b481de9c
ZY		 1968 for (i = 0; i < counter; i++) {
1969 index = i / 2;
1970 is_odd = i & 0x1;
1971
1972 if (is_odd)
1973 pci_unmap_single(
1974 dev,
1975 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1976 (IWL_GET_BITS(bd->pa[index],
1977 tb2_addr_hi20) << 16),
1978 IWL_GET_BITS(bd->pa[index], tb2_len),
1979 PCI_DMA_TODEVICE);
1980
1981 else if (i > 0)
1982 pci_unmap_single(dev,
1983 le32_to_cpu(bd->pa[index].tb1_addr),
1984 IWL_GET_BITS(bd->pa[index], tb1_len),
1985 PCI_DMA_TODEVICE);
1986
8b6eaea8 1987 /* Free SKB, if any, for this chunk */
fc4b6853
TW		 1988 if (txq->txb[txq->q.read_ptr].skb[i]) {
1989 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
b481de9c
ZY		 1990
1991 dev_kfree_skb(skb);
fc4b6853 1992 txq->txb[txq->q.read_ptr].skb[i] = NULL;
b481de9c
ZY		 1993 }
1994 }
1995 return 0;
1996}
1997
c79dd5b5 1998int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1999{
bb8c093b 2000 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
b481de9c
ZY		 2001 return -EINVAL;
2002}
2003
2004static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
2005{
2006 s32 sign = 1;
2007
2008 if (num < 0) {
2009 sign = -sign;
2010 num = -num;
2011 }
2012 if (denom < 0) {
2013 sign = -sign;
2014 denom = -denom;
2015 }
2016 *res = 1;
2017 *res = ((num * 2 + denom) / (denom * 2)) * sign;
2018
2019 return 1;
2020}
2021
8b6eaea8
CB		 2022/**
2023 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
2024 *
2025 * Determines power supply voltage compensation for txpower calculations.
2026 * Returns number of 1/2-dB steps to subtract from gain table index,
2027 * to compensate for difference between power supply voltage during
2028 * factory measurements, vs. current power supply voltage.
2029 *
2030 * Voltage indication is higher for lower voltage.
2031 * Lower voltage requires more gain (lower gain table index).
2032 */
b481de9c
ZY		 2033static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
2034 s32 current_voltage)
2035{
2036 s32 comp = 0;
2037
2038 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
2039 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
2040 return 0;
2041
2042 iwl4965_math_div_round(current_voltage - eeprom_voltage,
2043 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
2044
2045 if (current_voltage > eeprom_voltage)
2046 comp *= 2;
2047 if ((comp < -2) || (comp > 2))
2048 comp = 0;
2049
2050 return comp;
2051}
2052
bf85ea4f 2053static const struct iwl_channel_info *
c79dd5b5 2054iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
8318d78a 2055 enum ieee80211_band band, u16 channel)
b481de9c 2056{
bf85ea4f 2057 const struct iwl_channel_info *ch_info;
b481de9c 2058
8318d78a 2059 ch_info = iwl4965_get_channel_info(priv, band, channel);
b481de9c
ZY		 2060
2061 if (!is_channel_valid(ch_info))
2062 return NULL;
2063
2064 return ch_info;
2065}
2066
2067static s32 iwl4965_get_tx_atten_grp(u16 channel)
2068{
2069 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
2070 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
2071 return CALIB_CH_GROUP_5;
2072
2073 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
2074 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
2075 return CALIB_CH_GROUP_1;
2076
2077 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
2078 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
2079 return CALIB_CH_GROUP_2;
2080
2081 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
2082 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
2083 return CALIB_CH_GROUP_3;
2084
2085 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
2086 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
2087 return CALIB_CH_GROUP_4;
2088
2089 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
2090 return -1;
2091}
2092
c79dd5b5 2093static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 2094{
2095 s32 b = -1;
2096
2097 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
2098 if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
2099 continue;
2100
2101 if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
2102 && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
2103 break;
2104 }
2105
2106 return b;
2107}
2108
2109static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
2110{
2111 s32 val;
2112
2113 if (x2 == x1)
2114 return y1;
2115 else {
2116 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
2117 return val + y2;
2118 }
2119}
2120
8b6eaea8
CB		 2121/**
2122 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
2123 *
2124 * Interpolates factory measurements from the two sample channels within a
2125 * sub-band, to apply to channel of interest. Interpolation is proportional to
2126 * differences in channel frequencies, which is proportional to differences
2127 * in channel number.
2128 */
c79dd5b5 2129static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
bb8c093b 2130 struct iwl4965_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 2131{
2132 s32 s = -1;
2133 u32 c;
2134 u32 m;
bb8c093b
CH		 2135 const struct iwl4965_eeprom_calib_measure *m1;
2136 const struct iwl4965_eeprom_calib_measure *m2;
2137 struct iwl4965_eeprom_calib_measure *omeas;
b481de9c
ZY		 2138 u32 ch_i1;
2139 u32 ch_i2;
2140
2141 s = iwl4965_get_sub_band(priv, channel);
2142 if (s >= EEPROM_TX_POWER_BANDS) {
2143 IWL_ERROR("Tx Power can not find channel %d ", channel);
2144 return -1;
2145 }
2146
2147 ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
2148 ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
2149 chan_info->ch_num = (u8) channel;
2150
2151 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
2152 channel, s, ch_i1, ch_i2);
2153
2154 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
2155 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
2156 m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
2157 measurements[c][m]);
2158 m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
2159 measurements[c][m]);
2160 omeas = &(chan_info->measurements[c][m]);
2161
2162 omeas->actual_pow =
2163 (u8) iwl4965_interpolate_value(channel, ch_i1,
2164 m1->actual_pow,
2165 ch_i2,
2166 m2->actual_pow);
2167 omeas->gain_idx =
2168 (u8) iwl4965_interpolate_value(channel, ch_i1,
2169 m1->gain_idx, ch_i2,
2170 m2->gain_idx);
2171 omeas->temperature =
2172 (u8) iwl4965_interpolate_value(channel, ch_i1,
2173 m1->temperature,
2174 ch_i2,
2175 m2->temperature);
2176 omeas->pa_det =
2177 (s8) iwl4965_interpolate_value(channel, ch_i1,
2178 m1->pa_det, ch_i2,
2179 m2->pa_det);
2180
2181 IWL_DEBUG_TXPOWER
2182 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
2183 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
2184 IWL_DEBUG_TXPOWER
2185 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
2186 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
2187 IWL_DEBUG_TXPOWER
2188 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
2189 m1->pa_det, m2->pa_det, omeas->pa_det);
2190 IWL_DEBUG_TXPOWER
2191 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
2192 m1->temperature, m2->temperature,
2193 omeas->temperature);
2194 }
2195 }
2196
2197 return 0;
2198}
2199
2200/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
2201 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
2202static s32 back_off_table[] = {
2203 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
2204 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
2205 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
2206 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
2207 10 /* CCK */
2208};
2209
2210/* Thermal compensation values for txpower for various frequency ranges ...
2211 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 2212static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 2213 s32 degrees_per_05db_a;
2214 s32 degrees_per_05db_a_denom;
2215} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
2216 {9, 2}, /* group 0 5.2, ch 34-43 */
2217 {4, 1}, /* group 1 5.2, ch 44-70 */
2218 {4, 1}, /* group 2 5.2, ch 71-124 */
2219 {4, 1}, /* group 3 5.2, ch 125-200 */
2220 {3, 1} /* group 4 2.4, ch all */
2221};
2222
2223static s32 get_min_power_index(s32 rate_power_index, u32 band)
2224{
2225 if (!band) {
2226 if ((rate_power_index & 7) <= 4)
2227 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
2228 }
2229 return MIN_TX_GAIN_INDEX;
2230}
2231
2232struct gain_entry {
2233 u8 dsp;
2234 u8 radio;
2235};
2236
2237static const struct gain_entry gain_table[2][108] = {
2238 /* 5.2GHz power gain index table */
2239 {
2240 {123, 0x3F}, /* highest txpower */
2241 {117, 0x3F},
2242 {110, 0x3F},
2243 {104, 0x3F},
2244 {98, 0x3F},
2245 {110, 0x3E},
2246 {104, 0x3E},
2247 {98, 0x3E},
2248 {110, 0x3D},
2249 {104, 0x3D},
2250 {98, 0x3D},
2251 {110, 0x3C},
2252 {104, 0x3C},
2253 {98, 0x3C},
2254 {110, 0x3B},
2255 {104, 0x3B},
2256 {98, 0x3B},
2257 {110, 0x3A},
2258 {104, 0x3A},
2259 {98, 0x3A},
2260 {110, 0x39},
2261 {104, 0x39},
2262 {98, 0x39},
2263 {110, 0x38},
2264 {104, 0x38},
2265 {98, 0x38},
2266 {110, 0x37},
2267 {104, 0x37},
2268 {98, 0x37},
2269 {110, 0x36},
2270 {104, 0x36},
2271 {98, 0x36},
2272 {110, 0x35},
2273 {104, 0x35},
2274 {98, 0x35},
2275 {110, 0x34},
2276 {104, 0x34},
2277 {98, 0x34},
2278 {110, 0x33},
2279 {104, 0x33},
2280 {98, 0x33},
2281 {110, 0x32},
2282 {104, 0x32},
2283 {98, 0x32},
2284 {110, 0x31},
2285 {104, 0x31},
2286 {98, 0x31},
2287 {110, 0x30},
2288 {104, 0x30},
2289 {98, 0x30},
2290 {110, 0x25},
2291 {104, 0x25},
2292 {98, 0x25},
2293 {110, 0x24},
2294 {104, 0x24},
2295 {98, 0x24},
2296 {110, 0x23},
2297 {104, 0x23},
2298 {98, 0x23},
2299 {110, 0x22},
2300 {104, 0x18},
2301 {98, 0x18},
2302 {110, 0x17},
2303 {104, 0x17},
2304 {98, 0x17},
2305 {110, 0x16},
2306 {104, 0x16},
2307 {98, 0x16},
2308 {110, 0x15},
2309 {104, 0x15},
2310 {98, 0x15},
2311 {110, 0x14},
2312 {104, 0x14},
2313 {98, 0x14},
2314 {110, 0x13},
2315 {104, 0x13},
2316 {98, 0x13},
2317 {110, 0x12},
2318 {104, 0x08},
2319 {98, 0x08},
2320 {110, 0x07},
2321 {104, 0x07},
2322 {98, 0x07},
2323 {110, 0x06},
2324 {104, 0x06},
2325 {98, 0x06},
2326 {110, 0x05},
2327 {104, 0x05},
2328 {98, 0x05},
2329 {110, 0x04},
2330 {104, 0x04},
2331 {98, 0x04},
2332 {110, 0x03},
2333 {104, 0x03},
2334 {98, 0x03},
2335 {110, 0x02},
2336 {104, 0x02},
2337 {98, 0x02},
2338 {110, 0x01},
2339 {104, 0x01},
2340 {98, 0x01},
2341 {110, 0x00},
2342 {104, 0x00},
2343 {98, 0x00},
2344 {93, 0x00},
2345 {88, 0x00},
2346 {83, 0x00},
2347 {78, 0x00},
2348 },
2349 /* 2.4GHz power gain index table */
2350 {
2351 {110, 0x3f}, /* highest txpower */
2352 {104, 0x3f},
2353 {98, 0x3f},
2354 {110, 0x3e},
2355 {104, 0x3e},
2356 {98, 0x3e},
2357 {110, 0x3d},
2358 {104, 0x3d},
2359 {98, 0x3d},
2360 {110, 0x3c},
2361 {104, 0x3c},
2362 {98, 0x3c},
2363 {110, 0x3b},
2364 {104, 0x3b},
2365 {98, 0x3b},
2366 {110, 0x3a},
2367 {104, 0x3a},
2368 {98, 0x3a},
2369 {110, 0x39},
2370 {104, 0x39},
2371 {98, 0x39},
2372 {110, 0x38},
2373 {104, 0x38},
2374 {98, 0x38},
2375 {110, 0x37},
2376 {104, 0x37},
2377 {98, 0x37},
2378 {110, 0x36},
2379 {104, 0x36},
2380 {98, 0x36},
2381 {110, 0x35},
2382 {104, 0x35},
2383 {98, 0x35},
2384 {110, 0x34},
2385 {104, 0x34},
2386 {98, 0x34},
2387 {110, 0x33},
2388 {104, 0x33},
2389 {98, 0x33},
2390 {110, 0x32},
2391 {104, 0x32},
2392 {98, 0x32},
2393 {110, 0x31},
2394 {104, 0x31},
2395 {98, 0x31},
2396 {110, 0x30},
2397 {104, 0x30},
2398 {98, 0x30},
2399 {110, 0x6},
2400 {104, 0x6},
2401 {98, 0x6},
2402 {110, 0x5},
2403 {104, 0x5},
2404 {98, 0x5},
2405 {110, 0x4},
2406 {104, 0x4},
2407 {98, 0x4},
2408 {110, 0x3},
2409 {104, 0x3},
2410 {98, 0x3},
2411 {110, 0x2},
2412 {104, 0x2},
2413 {98, 0x2},
2414 {110, 0x1},
2415 {104, 0x1},
2416 {98, 0x1},
2417 {110, 0x0},
2418 {104, 0x0},
2419 {98, 0x0},
2420 {97, 0},
2421 {96, 0},
2422 {95, 0},
2423 {94, 0},
2424 {93, 0},
2425 {92, 0},
2426 {91, 0},
2427 {90, 0},
2428 {89, 0},
2429 {88, 0},
2430 {87, 0},
2431 {86, 0},
2432 {85, 0},
2433 {84, 0},
2434 {83, 0},
2435 {82, 0},
2436 {81, 0},
2437 {80, 0},
2438 {79, 0},
2439 {78, 0},
2440 {77, 0},
2441 {76, 0},
2442 {75, 0},
2443 {74, 0},
2444 {73, 0},
2445 {72, 0},
2446 {71, 0},
2447 {70, 0},
2448 {69, 0},
2449 {68, 0},
2450 {67, 0},
2451 {66, 0},
2452 {65, 0},
2453 {64, 0},
2454 {63, 0},
2455 {62, 0},
2456 {61, 0},
2457 {60, 0},
2458 {59, 0},
2459 }
2460};
2461
c79dd5b5 2462static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 2463 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 2464 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 2465{
2466 u8 saturation_power;
2467 s32 target_power;
2468 s32 user_target_power;
2469 s32 power_limit;
2470 s32 current_temp;
2471 s32 reg_limit;
2472 s32 current_regulatory;
2473 s32 txatten_grp = CALIB_CH_GROUP_MAX;
2474 int i;
2475 int c;
bf85ea4f 2476 const struct iwl_channel_info *ch_info = NULL;
bb8c093b
CH		 2477 struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
2478 const struct iwl4965_eeprom_calib_measure *measurement;
b481de9c
ZY		 2479 s16 voltage;
2480 s32 init_voltage;
2481 s32 voltage_compensation;
2482 s32 degrees_per_05db_num;
2483 s32 degrees_per_05db_denom;
2484 s32 factory_temp;
2485 s32 temperature_comp[2];
2486 s32 factory_gain_index[2];
2487 s32 factory_actual_pwr[2];
2488 s32 power_index;
2489
2490 /* Sanity check requested level (dBm) */
2491 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
2492 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
2493 priv->user_txpower_limit);
2494 return -EINVAL;
2495 }
2496 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
2497 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
2498 priv->user_txpower_limit);
2499 return -EINVAL;
2500 }
2501
2502 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
2503 * are used for indexing into txpower table) */
2504 user_target_power = 2 * priv->user_txpower_limit;
2505
2506 /* Get current (RXON) channel, band, width */
2507 ch_info =
8318d78a 2508 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
b481de9c
ZY		 2509
2510 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
2511 is_fat);
2512
2513 if (!ch_info)
2514 return -EINVAL;
2515
2516 /* get txatten group, used to select 1) thermal txpower adjustment
2517 * and 2) mimo txpower balance between Tx chains. */
2518 txatten_grp = iwl4965_get_tx_atten_grp(channel);
2519 if (txatten_grp < 0)
2520 return -EINVAL;
2521
2522 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
2523 channel, txatten_grp);
2524
2525 if (is_fat) {
2526 if (ctrl_chan_high)
2527 channel -= 2;
2528 else
2529 channel += 2;
2530 }
2531
2532 /* hardware txpower limits ...
2533 * saturation (clipping distortion) txpowers are in half-dBm */
2534 if (band)
2535 saturation_power = priv->eeprom.calib_info.saturation_power24;
2536 else
2537 saturation_power = priv->eeprom.calib_info.saturation_power52;
2538
2539 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
2540 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
2541 if (band)
2542 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
2543 else
2544 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
2545 }
2546
2547 /* regulatory txpower limits ... reg_limit values are in half-dBm,
2548 * max_power_avg values are in dBm, convert * 2 */
2549 if (is_fat)
2550 reg_limit = ch_info->fat_max_power_avg * 2;
2551 else
2552 reg_limit = ch_info->max_power_avg * 2;
2553
2554 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2555 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2556 if (band)
2557 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2558 else
2559 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2560 }
2561
2562 /* Interpolate txpower calibration values for this channel,
2563 * based on factory calibration tests on spaced channels. */
2564 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2565
2566 /* calculate tx gain adjustment based on power supply voltage */
2567 voltage = priv->eeprom.calib_info.voltage;
2568 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2569 voltage_compensation =
2570 iwl4965_get_voltage_compensation(voltage, init_voltage);
2571
2572 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2573 init_voltage,
2574 voltage, voltage_compensation);
2575
2576 /* get current temperature (Celsius) */
2577 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2578 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2579 current_temp = KELVIN_TO_CELSIUS(current_temp);
2580
2581 /* select thermal txpower adjustment params, based on channel group
2582 * (same frequency group used for mimo txatten adjustment) */
2583 degrees_per_05db_num =
2584 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2585 degrees_per_05db_denom =
2586 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2587
2588 /* get per-chain txpower values from factory measurements */
2589 for (c = 0; c < 2; c++) {
2590 measurement = &ch_eeprom_info.measurements[c][1];
2591
2592 /* txgain adjustment (in half-dB steps) based on difference
2593 * between factory and current temperature */
2594 factory_temp = measurement->temperature;
2595 iwl4965_math_div_round((current_temp - factory_temp) *
2596 degrees_per_05db_denom,
2597 degrees_per_05db_num,
2598 &temperature_comp[c]);
2599
2600 factory_gain_index[c] = measurement->gain_idx;
2601 factory_actual_pwr[c] = measurement->actual_pow;
2602
2603 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2604 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2605 "curr tmp %d, comp %d steps\n",
2606 factory_temp, current_temp,
2607 temperature_comp[c]);
2608
2609 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2610 factory_gain_index[c],
2611 factory_actual_pwr[c]);
2612 }
2613
2614 /* for each of 33 bit-rates (including 1 for CCK) */
2615 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2616 u8 is_mimo_rate;
bb8c093b 2617 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 2618
2619 /* for mimo, reduce each chain's txpower by half
2620 * (3dB, 6 steps), so total output power is regulatory
2621 * compliant. */
2622 if (i & 0x8) {
2623 current_regulatory = reg_limit -
2624 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2625 is_mimo_rate = 1;
2626 } else {
2627 current_regulatory = reg_limit;
2628 is_mimo_rate = 0;
2629 }
2630
2631 /* find txpower limit, either hardware or regulatory */
2632 power_limit = saturation_power - back_off_table[i];
2633 if (power_limit > current_regulatory)
2634 power_limit = current_regulatory;
2635
2636 /* reduce user's txpower request if necessary
2637 * for this rate on this channel */
2638 target_power = user_target_power;
2639 if (target_power > power_limit)
2640 target_power = power_limit;
2641
2642 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2643 i, saturation_power - back_off_table[i],
2644 current_regulatory, user_target_power,
2645 target_power);
2646
2647 /* for each of 2 Tx chains (radio transmitters) */
2648 for (c = 0; c < 2; c++) {
2649 s32 atten_value;
2650
2651 if (is_mimo_rate)
2652 atten_value =
2653 (s32)le32_to_cpu(priv->card_alive_init.
2654 tx_atten[txatten_grp][c]);
2655 else
2656 atten_value = 0;
2657
2658 /* calculate index; higher index means lower txpower */
2659 power_index = (u8) (factory_gain_index[c] -
2660 (target_power -
2661 factory_actual_pwr[c]) -
2662 temperature_comp[c] -
2663 voltage_compensation +
2664 atten_value);
2665
2666/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2667 power_index); */
2668
2669 if (power_index < get_min_power_index(i, band))
2670 power_index = get_min_power_index(i, band);
2671
2672 /* adjust 5 GHz index to support negative indexes */
2673 if (!band)
2674 power_index += 9;
2675
2676 /* CCK, rate 32, reduce txpower for CCK */
2677 if (i == POWER_TABLE_CCK_ENTRY)
2678 power_index +=
2679 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2680
2681 /* stay within the table! */
2682 if (power_index > 107) {
2683 IWL_WARNING("txpower index %d > 107\n",
2684 power_index);
2685 power_index = 107;
2686 }
2687 if (power_index < 0) {
2688 IWL_WARNING("txpower index %d < 0\n",
2689 power_index);
2690 power_index = 0;
2691 }
2692
2693 /* fill txpower command for this rate/chain */
2694 tx_power.s.radio_tx_gain[c] =
2695 gain_table[band][power_index].radio;
2696 tx_power.s.dsp_predis_atten[c] =
2697 gain_table[band][power_index].dsp;
2698
2699 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2700 "gain 0x%02x dsp %d\n",
2701 c, atten_value, power_index,
2702 tx_power.s.radio_tx_gain[c],
2703 tx_power.s.dsp_predis_atten[c]);
2704 }/* for each chain */
2705
2706 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2707
2708 }/* for each rate */
2709
2710 return 0;
2711}
2712
2713/**
bb8c093b 2714 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
b481de9c
ZY		 2715 *
2716 * Uses the active RXON for channel, band, and characteristics (fat, high)
2717 * The power limit is taken from priv->user_txpower_limit.
2718 */
c79dd5b5 2719int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 2720{
bb8c093b 2721 struct iwl4965_txpowertable_cmd cmd = { 0 };
b481de9c
ZY		 2722 int rc = 0;
2723 u8 band = 0;
2724 u8 is_fat = 0;
2725 u8 ctrl_chan_high = 0;
2726
2727 if (test_bit(STATUS_SCANNING, &priv->status)) {
2728 /* If this gets hit a lot, switch it to a BUG() and catch
2729 * the stack trace to find out who is calling this during
2730 * a scan. */
2731 IWL_WARNING("TX Power requested while scanning!\n");
2732 return -EAGAIN;
2733 }
2734
8318d78a 2735 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 2736
2737 is_fat = is_fat_channel(priv->active_rxon.flags);
2738
2739 if (is_fat &&
2740 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2741 ctrl_chan_high = 1;
2742
2743 cmd.band = band;
2744 cmd.channel = priv->active_rxon.channel;
2745
2746 rc = iwl4965_fill_txpower_tbl(priv, band,
2747 le16_to_cpu(priv->active_rxon.channel),
2748 is_fat, ctrl_chan_high, &cmd.tx_power);
2749 if (rc)
2750 return rc;
2751
bb8c093b 2752 rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
b481de9c
ZY		 2753 return rc;
2754}
2755
c79dd5b5 2756int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2757{
2758 int rc;
2759 u8 band = 0;
2760 u8 is_fat = 0;
2761 u8 ctrl_chan_high = 0;
bb8c093b 2762 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 2763 const struct iwl_channel_info *ch_info;
b481de9c 2764
8318d78a 2765 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 2766
8318d78a 2767 ch_info = iwl4965_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 2768
2769 is_fat = is_fat_channel(priv->staging_rxon.flags);
2770
2771 if (is_fat &&
2772 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2773 ctrl_chan_high = 1;
2774
2775 cmd.band = band;
2776 cmd.expect_beacon = 0;
2777 cmd.channel = cpu_to_le16(channel);
2778 cmd.rxon_flags = priv->active_rxon.flags;
2779 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2780 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2781 if (ch_info)
2782 cmd.expect_beacon = is_channel_radar(ch_info);
2783 else
2784 cmd.expect_beacon = 1;
2785
2786 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2787 ctrl_chan_high, &cmd.tx_power);
2788 if (rc) {
2789 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2790 return rc;
2791 }
2792
bb8c093b 2793 rc = iwl4965_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 2794 return rc;
2795}
2796
2797#define RTS_HCCA_RETRY_LIMIT 3
2798#define RTS_DFAULT_RETRY_LIMIT 60
2799
c79dd5b5 2800void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
bb8c093b 2801 struct iwl4965_cmd *cmd,
b481de9c
ZY		 2802 struct ieee80211_tx_control *ctrl,
2803 struct ieee80211_hdr *hdr, int sta_id,
2804 int is_hcca)
2805{
87e4f7df 2806 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
b481de9c
ZY		 2807 u8 rts_retry_limit = 0;
2808 u8 data_retry_limit = 0;
b481de9c 2809 u16 fc = le16_to_cpu(hdr->frame_control);
87e4f7df
TW		 2810 u8 rate_plcp;
2811 u16 rate_flags = 0;
8318d78a 2812 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c 2813
87e4f7df 2814 rate_plcp = iwl4965_rates[rate_idx].plcp;
b481de9c
ZY		 2815
2816 rts_retry_limit = (is_hcca) ?
2817 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2818
87e4f7df
TW		 2819 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2820 rate_flags |= RATE_MCS_CCK_MSK;
2821
2822
b481de9c
ZY		 2823 if (ieee80211_is_probe_response(fc)) {
2824 data_retry_limit = 3;
2825 if (data_retry_limit < rts_retry_limit)
2826 rts_retry_limit = data_retry_limit;
2827 } else
2828 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2829
2830 if (priv->data_retry_limit != -1)
2831 data_retry_limit = priv->data_retry_limit;
2832
87e4f7df
TW		 2833
2834 if (ieee80211_is_data(fc)) {
2835 tx->initial_rate_index = 0;
2836 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2837 } else {
b481de9c
ZY		 2838 switch (fc & IEEE80211_FCTL_STYPE) {
2839 case IEEE80211_STYPE_AUTH:
2840 case IEEE80211_STYPE_DEAUTH:
2841 case IEEE80211_STYPE_ASSOC_REQ:
2842 case IEEE80211_STYPE_REASSOC_REQ:
87e4f7df
TW		 2843 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2844 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2845 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
b481de9c
ZY		 2846 }
2847 break;
2848 default:
2849 break;
2850 }
87e4f7df
TW		 2851
2852 /* Alternate between antenna A and B for successive frames */
2853 if (priv->use_ant_b_for_management_frame) {
2854 priv->use_ant_b_for_management_frame = 0;
2855 rate_flags |= RATE_MCS_ANT_B_MSK;
2856 } else {
2857 priv->use_ant_b_for_management_frame = 1;
2858 rate_flags |= RATE_MCS_ANT_A_MSK;
2859 }
b481de9c
ZY		 2860 }
2861
87e4f7df
TW		 2862 tx->rts_retry_limit = rts_retry_limit;
2863 tx->data_retry_limit = data_retry_limit;
2864 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
b481de9c
ZY		 2865}
2866
c79dd5b5 2867int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2868{
bb8c093b 2869 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2870
2871 return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
2872}
2873
c79dd5b5 2874int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 2875{
2876 return priv->temperature;
2877}
2878
c79dd5b5 2879unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2880 struct iwl4965_frame *frame, u8 rate)
b481de9c 2881{
bb8c093b 2882 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2883 unsigned int frame_size;
2884
2885 tx_beacon_cmd = &frame->u.beacon;
2886 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2887
a4062b8f 2888 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 2889 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2890
bb8c093b 2891 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 2892 tx_beacon_cmd->frame,
bb8c093b 2893 iwl4965_broadcast_addr,
b481de9c
ZY		 2894 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2895
2896 BUG_ON(frame_size > MAX_MPDU_SIZE);
2897 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2898
2899 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2900 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2901 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 2902 else
2903 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2904 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 2905
2906 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2907 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2908 return (sizeof(*tx_beacon_cmd) + frame_size);
2909}
2910
8b6eaea8
CB		 2911/*
2912 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2913 * given Tx queue, and enable the DMA channel used for that queue.
2914 *
2915 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2916 * channels supported in hardware.
2917 */
c79dd5b5 2918int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c
ZY		 2919{
2920 int rc;
2921 unsigned long flags;
2922 int txq_id = txq->q.id;
2923
2924 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2925 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 2926 if (rc) {
2927 spin_unlock_irqrestore(&priv->lock, flags);
2928 return rc;
2929 }
2930
8b6eaea8 2931 /* Circular buffer (TFD queue in DRAM) physical base address */
bb8c093b 2932 iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
b481de9c 2933 txq->q.dma_addr >> 8);
8b6eaea8
CB		 2934
2935 /* Enable DMA channel, using same id as for TFD queue */
bb8c093b 2936 iwl4965_write_direct32(
b481de9c
ZY		 2937 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2938 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2939 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
bb8c093b 2940 iwl4965_release_nic_access(priv);
b481de9c
ZY		 2941 spin_unlock_irqrestore(&priv->lock, flags);
2942
2943 return 0;
2944}
2945
c79dd5b5 2946int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 2947 dma_addr_t addr, u16 len)
2948{
2949 int index, is_odd;
bb8c093b 2950 struct iwl4965_tfd_frame *tfd = ptr;
b481de9c
ZY		 2951 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2952
8b6eaea8 2953 /* Each TFD can point to a maximum 20 Tx buffers */
b481de9c
ZY		 2954 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2955 IWL_ERROR("Error can not send more than %d chunks\n",
2956 MAX_NUM_OF_TBS);
2957 return -EINVAL;
2958 }
2959
2960 index = num_tbs / 2;
2961 is_odd = num_tbs & 0x1;
2962
2963 if (!is_odd) {
2964 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2965 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
6a218f6f 2966 iwl_get_dma_hi_address(addr));
b481de9c
ZY		 2967 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2968 } else {
2969 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2970 (u32) (addr & 0xffff));
2971 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2972 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2973 }
2974
2975 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2976
2977 return 0;
2978}
2979
c79dd5b5 2980static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
b481de9c
ZY		 2981{
2982 u16 hw_version = priv->eeprom.board_revision_4965;
2983
2984 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2985 ((hw_version >> 8) & 0x0F),
2986 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2987
2988 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2989 priv->eeprom.board_pba_number_4965);
2990}
2991
2992#define IWL_TX_CRC_SIZE 4
2993#define IWL_TX_DELIMITER_SIZE 4
2994
8b6eaea8
CB		 2995/**
2996 * iwl4965_tx_queue_update_wr_ptr - Set up entry in Tx byte-count array
2997 */
c79dd5b5 2998int iwl4965_tx_queue_update_wr_ptr(struct iwl_priv *priv,
bb8c093b 2999 struct iwl4965_tx_queue *txq, u16 byte_cnt)
b481de9c
ZY		 3000{
3001 int len;
3002 int txq_id = txq->q.id;
bb8c093b 3003 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 3004
3005 if (txq->need_update == 0)
3006 return 0;
3007
3008 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
3009
8b6eaea8 3010 /* Set up byte count within first 256 entries */
b481de9c 3011 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 3012 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 3013
8b6eaea8 3014 /* If within first 64 entries, duplicate at end */
fc4b6853 3015 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
b481de9c 3016 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 3017 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
b481de9c
ZY		 3018 byte_cnt, len);
3019
3020 return 0;
3021}
3022
8b6eaea8
CB		 3023/**
3024 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
3025 *
3026 * Selects how many and which Rx receivers/antennas/chains to use.
3027 * This should not be used for scan command ... it puts data in wrong place.
3028 */
c79dd5b5 3029void iwl4965_set_rxon_chain(struct iwl_priv *priv)
b481de9c
ZY		 3030{
3031 u8 is_single = is_single_stream(priv);
3032 u8 idle_state, rx_state;
3033
3034 priv->staging_rxon.rx_chain = 0;
3035 rx_state = idle_state = 3;
3036
3037 /* Tell uCode which antennas are actually connected.
3038 * Before first association, we assume all antennas are connected.
3039 * Just after first association, iwl4965_noise_calibration()
3040 * checks which antennas actually *are* connected. */
3041 priv->staging_rxon.rx_chain |=
3042 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
3043
3044 /* How many receivers should we use? */
3045 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
3046 priv->staging_rxon.rx_chain |=
3047 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
3048 priv->staging_rxon.rx_chain |=
3049 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
3050
3051 if (!is_single && (rx_state >= 2) &&
3052 !test_bit(STATUS_POWER_PMI, &priv->status))
3053 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
3054 else
3055 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
3056
3057 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
3058}
3059
b481de9c
ZY		 3060/**
3061 * sign_extend - Sign extend a value using specified bit as sign-bit
3062 *
3063 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
3064 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
3065 *
3066 * @param oper value to sign extend
3067 * @param index 0 based bit index (0<=index<32) to sign bit
3068 */
3069static s32 sign_extend(u32 oper, int index)
3070{
3071 u8 shift = 31 - index;
3072
3073 return (s32)(oper << shift) >> shift;
3074}
3075
3076/**
3077 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
3078 * @statistics: Provides the temperature reading from the uCode
3079 *
3080 * A return of <0 indicates bogus data in the statistics
3081 */
c79dd5b5 3082int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 3083{
3084 s32 temperature;
3085 s32 vt;
3086 s32 R1, R2, R3;
3087 u32 R4;
3088
3089 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
3090 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
3091 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
3092 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
3093 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
3094 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
3095 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
3096 } else {
3097 IWL_DEBUG_TEMP("Running temperature calibration\n");
3098 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
3099 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
3100 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
3101 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
3102 }
3103
3104 /*
8b6eaea8 3105 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 3106 *
3107 * NOTE If we haven't received a statistics notification yet
3108 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 3109 * "initialize" ALIVE response.
3110 */
b481de9c
ZY		 3111 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
3112 vt = sign_extend(R4, 23);
3113 else
3114 vt = sign_extend(
3115 le32_to_cpu(priv->statistics.general.temperature), 23);
3116
3117 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
3118 R1, R2, R3, vt);
3119
3120 if (R3 == R1) {
3121 IWL_ERROR("Calibration conflict R1 == R3\n");
3122 return -1;
3123 }
3124
3125 /* Calculate temperature in degrees Kelvin, adjust by 97%.
3126 * Add offset to center the adjustment around 0 degrees Centigrade. */
3127 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
3128 temperature /= (R3 - R1);
3129 temperature = (temperature * 97) / 100 +
3130 TEMPERATURE_CALIB_KELVIN_OFFSET;
3131
3132 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
3133 KELVIN_TO_CELSIUS(temperature));
3134
3135 return temperature;
3136}
3137
3138/* Adjust Txpower only if temperature variance is greater than threshold. */
3139#define IWL_TEMPERATURE_THRESHOLD 3
3140
3141/**
3142 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
3143 *
3144 * If the temperature changed has changed sufficiently, then a recalibration
3145 * is needed.
3146 *
3147 * Assumes caller will replace priv->last_temperature once calibration
3148 * executed.
3149 */
c79dd5b5 3150static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 3151{
3152 int temp_diff;
3153
3154 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
3155 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
3156 return 0;
3157 }
3158
3159 temp_diff = priv->temperature - priv->last_temperature;
3160
3161 /* get absolute value */
3162 if (temp_diff < 0) {
3163 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
3164 temp_diff = -temp_diff;
3165 } else if (temp_diff == 0)
3166 IWL_DEBUG_POWER("Same temp, \n");
3167 else
3168 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
3169
3170 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
3171 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
3172 return 0;
3173 }
3174
3175 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
3176
3177 return 1;
3178}
3179
3180/* Calculate noise level, based on measurements during network silence just
3181 * before arriving beacon. This measurement can be done only if we know
3182 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 3183static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 3184{
3185 struct statistics_rx_non_phy *rx_info
3186 = &(priv->statistics.rx.general);
3187 int num_active_rx = 0;
3188 int total_silence = 0;
3189 int bcn_silence_a =
3190 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
3191 int bcn_silence_b =
3192 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
3193 int bcn_silence_c =
3194 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
3195
3196 if (bcn_silence_a) {
3197 total_silence += bcn_silence_a;
3198 num_active_rx++;
3199 }
3200 if (bcn_silence_b) {
3201 total_silence += bcn_silence_b;
3202 num_active_rx++;
3203 }
3204 if (bcn_silence_c) {
3205 total_silence += bcn_silence_c;
3206 num_active_rx++;
3207 }
3208
3209 /* Average among active antennas */
3210 if (num_active_rx)
3211 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
3212 else
3213 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3214
3215 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
3216 bcn_silence_a, bcn_silence_b, bcn_silence_c,
3217 priv->last_rx_noise);
3218}
3219
c79dd5b5 3220void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3221{
bb8c093b 3222 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3223 int change;
3224 s32 temp;
3225
3226 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
3227 (int)sizeof(priv->statistics), pkt->len);
3228
3229 change = ((priv->statistics.general.temperature !=
3230 pkt->u.stats.general.temperature) ||
3231 ((priv->statistics.flag &
3232 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
3233 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
3234
3235 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
3236
3237 set_bit(STATUS_STATISTICS, &priv->status);
3238
3239 /* Reschedule the statistics timer to occur in
3240 * REG_RECALIB_PERIOD seconds to ensure we get a
3241 * thermal update even if the uCode doesn't give
3242 * us one */
3243 mod_timer(&priv->statistics_periodic, jiffies +
3244 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
3245
3246 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3247 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
3248 iwl4965_rx_calc_noise(priv);
c8b0e6e1 3249#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 3250 queue_work(priv->workqueue, &priv->sensitivity_work);
3251#endif
3252 }
3253
3254 /* If the hardware hasn't reported a change in
3255 * temperature then don't bother computing a
3256 * calibrated temperature value */
3257 if (!change)
3258 return;
3259
3260 temp = iwl4965_get_temperature(priv);
3261 if (temp < 0)
3262 return;
3263
3264 if (priv->temperature != temp) {
3265 if (priv->temperature)
3266 IWL_DEBUG_TEMP("Temperature changed "
3267 "from %dC to %dC\n",
3268 KELVIN_TO_CELSIUS(priv->temperature),
3269 KELVIN_TO_CELSIUS(temp));
3270 else
3271 IWL_DEBUG_TEMP("Temperature "
3272 "initialized to %dC\n",
3273 KELVIN_TO_CELSIUS(temp));
3274 }
3275
3276 priv->temperature = temp;
3277 set_bit(STATUS_TEMPERATURE, &priv->status);
3278
3279 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3280 iwl4965_is_temp_calib_needed(priv))
3281 queue_work(priv->workqueue, &priv->txpower_work);
3282}
3283
c79dd5b5 3284static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 3285 struct sk_buff *skb,
3286 struct iwl4965_rx_phy_res *rx_start,
3287 struct ieee80211_rx_status *stats,
3288 u32 ampdu_status)
3289{
3290 s8 signal = stats->ssi;
3291 s8 noise = 0;
8318d78a 3292 int rate = stats->rate_idx;
12342c47
ZY		 3293 u64 tsf = stats->mactime;
3294 __le16 phy_flags_hw = rx_start->phy_flags;
3295 struct iwl4965_rt_rx_hdr {
3296 struct ieee80211_radiotap_header rt_hdr;
3297 __le64 rt_tsf; /* TSF */
3298 u8 rt_flags; /* radiotap packet flags */
3299 u8 rt_rate; /* rate in 500kb/s */
3300 __le16 rt_channelMHz; /* channel in MHz */
3301 __le16 rt_chbitmask; /* channel bitfield */
3302 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
3303 s8 rt_dbmnoise;
3304 u8 rt_antenna; /* antenna number */
3305 } __attribute__ ((packed)) *iwl4965_rt;
3306
3307 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
3308 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
3309 if (net_ratelimit())
3310 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 3311 "radiotap head [%zd]\n",
12342c47
ZY		 3312 skb_headroom(skb), sizeof(*iwl4965_rt));
3313 return;
3314 }
3315
3316 /* put radiotap header in front of 802.11 header and data */
3317 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
3318
3319 /* initialise radiotap header */
3320 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
3321 iwl4965_rt->rt_hdr.it_pad = 0;
3322
3323 /* total header + data */
3324 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
3325 &iwl4965_rt->rt_hdr.it_len);
3326
3327 /* Indicate all the fields we add to the radiotap header */
3328 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
3329 (1 << IEEE80211_RADIOTAP_FLAGS) |
3330 (1 << IEEE80211_RADIOTAP_RATE) |
3331 (1 << IEEE80211_RADIOTAP_CHANNEL) |
3332 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
3333 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
3334 (1 << IEEE80211_RADIOTAP_ANTENNA)),
3335 &iwl4965_rt->rt_hdr.it_present);
3336
3337 /* Zero the flags, we'll add to them as we go */
3338 iwl4965_rt->rt_flags = 0;
3339
3340 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
3341
3342 iwl4965_rt->rt_dbmsignal = signal;
3343 iwl4965_rt->rt_dbmnoise = noise;
3344
3345 /* Convert the channel frequency and set the flags */
3346 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
3347 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
3348 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3349 IEEE80211_CHAN_5GHZ),
3350 &iwl4965_rt->rt_chbitmask);
3351 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
3352 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
3353 IEEE80211_CHAN_2GHZ),
3354 &iwl4965_rt->rt_chbitmask);
3355 else /* 802.11g */
3356 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3357 IEEE80211_CHAN_2GHZ),
3358 &iwl4965_rt->rt_chbitmask);
3359
12342c47
ZY		 3360 if (rate == -1)
3361 iwl4965_rt->rt_rate = 0;
3362 else
3363 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
3364
3365 /*
3366 * "antenna number"
3367 *
3368 * It seems that the antenna field in the phy flags value
3369 * is actually a bitfield. This is undefined by radiotap,
3370 * it wants an actual antenna number but I always get "7"
3371 * for most legacy frames I receive indicating that the
3372 * same frame was received on all three RX chains.
3373 *
3374 * I think this field should be removed in favour of a
3375 * new 802.11n radiotap field "RX chains" that is defined
3376 * as a bitmask.
3377 */
3378 iwl4965_rt->rt_antenna =
3379 le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
3380
3381 /* set the preamble flag if appropriate */
3382 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
3383 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3384
3385 stats->flag |= RX_FLAG_RADIOTAP;
3386}
3387
19758bef
TW		 3388static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
3389{
3390 /* 0 - mgmt, 1 - cnt, 2 - data */
3391 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
3392 priv->rx_stats[idx].cnt++;
3393 priv->rx_stats[idx].bytes += len;
3394}
3395
17e476b8
EG		 3396static u32 iwl4965_translate_rx_status(u32 decrypt_in)
3397{
3398 u32 decrypt_out = 0;
3399
3400 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
3401 RX_RES_STATUS_STATION_FOUND)
3402 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
3403 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
3404
3405 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
3406
3407 /* packet was not encrypted */
3408 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3409 RX_RES_STATUS_SEC_TYPE_NONE)
3410 return decrypt_out;
3411
3412 /* packet was encrypted with unknown alg */
3413 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3414 RX_RES_STATUS_SEC_TYPE_ERR)
3415 return decrypt_out;
3416
3417 /* decryption was not done in HW */
3418 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
3419 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
3420 return decrypt_out;
3421
3422 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
3423
3424 case RX_RES_STATUS_SEC_TYPE_CCMP:
3425 /* alg is CCM: check MIC only */
3426 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
3427 /* Bad MIC */
3428 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3429 else
3430 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3431
3432 break;
3433
3434 case RX_RES_STATUS_SEC_TYPE_TKIP:
3435 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
3436 /* Bad TTAK */
3437 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
3438 break;
3439 }
3440 /* fall through if TTAK OK */
3441 default:
3442 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
3443 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3444 else
3445 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3446 break;
3447 };
3448
3449 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
3450 decrypt_in, decrypt_out);
3451
3452 return decrypt_out;
3453}
3454
c79dd5b5 3455static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 3456 int include_phy,
bb8c093b 3457 struct iwl4965_rx_mem_buffer *rxb,
b481de9c
ZY		 3458 struct ieee80211_rx_status *stats)
3459{
bb8c093b 3460 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3461 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3462 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3463 struct ieee80211_hdr *hdr;
3464 u16 len;
3465 __le32 *rx_end;
3466 unsigned int skblen;
3467 u32 ampdu_status;
17e476b8 3468 u32 ampdu_status_legacy;
b481de9c
ZY		 3469
3470 if (!include_phy && priv->last_phy_res[0])
3471 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3472
3473 if (!rx_start) {
3474 IWL_ERROR("MPDU frame without a PHY data\n");
3475 return;
3476 }
3477 if (include_phy) {
3478 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3479 rx_start->cfg_phy_cnt);
3480
3481 len = le16_to_cpu(rx_start->byte_count);
3482
3483 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3484 sizeof(struct iwl4965_rx_phy_res) +
3485 rx_start->cfg_phy_cnt + len);
3486
3487 } else {
3488 struct iwl4965_rx_mpdu_res_start *amsdu =
3489 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3490
3491 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3492 sizeof(struct iwl4965_rx_mpdu_res_start));
3493 len = le16_to_cpu(amsdu->byte_count);
3494 rx_start->byte_count = amsdu->byte_count;
3495 rx_end = (__le32 *) (((u8 *) hdr) + len);
3496 }
9ee1ba47 3497 if (len > priv->hw_setting.max_pkt_size || len < 16) {
12342c47 3498 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 3499 return;
3500 }
3501
3502 ampdu_status = le32_to_cpu(*rx_end);
3503 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3504
17e476b8
EG		 3505 if (!include_phy) {
3506 /* New status scheme, need to translate */
3507 ampdu_status_legacy = ampdu_status;
3508 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3509 }
3510
b481de9c
ZY		 3511 /* start from MAC */
3512 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3513 skb_put(rxb->skb, len); /* end where data ends */
3514
3515 /* We only process data packets if the interface is open */
3516 if (unlikely(!priv->is_open)) {
3517 IWL_DEBUG_DROP_LIMIT
3518 ("Dropping packet while interface is not open.\n");
3519 return;
3520 }
3521
b481de9c
ZY		 3522 stats->flag = 0;
3523 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3524
00acbc91 3525 if (iwl4965_mod_params.hw_crypto)
bb8c093b 3526 iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
b481de9c 3527
12342c47
ZY		 3528 if (priv->add_radiotap)
3529 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3530
19758bef 3531 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 3532 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3533 priv->alloc_rxb_skb--;
3534 rxb->skb = NULL;
3535#ifdef LED
3536 priv->led_packets += len;
bb8c093b 3537 iwl4965_setup_activity_timer(priv);
b481de9c
ZY		 3538#endif
3539}
3540
3541/* Calc max signal level (dBm) among 3 possible receivers */
3542static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3543{
3544 /* data from PHY/DSP regarding signal strength, etc.,
3545 * contents are always there, not configurable by host. */
3546 struct iwl4965_rx_non_cfg_phy *ncphy =
3547 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3548 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3549 >> IWL_AGC_DB_POS;
3550
3551 u32 valid_antennae =
3552 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3553 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3554 u8 max_rssi = 0;
3555 u32 i;
3556
3557 /* Find max rssi among 3 possible receivers.
3558 * These values are measured by the digital signal processor (DSP).
3559 * They should stay fairly constant even as the signal strength varies,
3560 * if the radio's automatic gain control (AGC) is working right.
3561 * AGC value (see below) will provide the "interesting" info. */
3562 for (i = 0; i < 3; i++)
3563 if (valid_antennae & (1 << i))
3564 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3565
3566 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3567 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3568 max_rssi, agc);
3569
3570 /* dBm = max_rssi dB - agc dB - constant.
3571 * Higher AGC (higher radio gain) means lower signal. */
3572 return (max_rssi - agc - IWL_RSSI_OFFSET);
3573}
3574
c8b0e6e1 3575#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 3576
3577/* Parsed Information Elements */
3578struct ieee802_11_elems {
3579 u8 *ds_params;
3580 u8 ds_params_len;
3581 u8 *tim;
3582 u8 tim_len;
3583 u8 *ibss_params;
3584 u8 ibss_params_len;
3585 u8 *erp_info;
3586 u8 erp_info_len;
3587 u8 *ht_cap_param;
3588 u8 ht_cap_param_len;
3589 u8 *ht_extra_param;
3590 u8 ht_extra_param_len;
3591};
3592
3593static int parse_elems(u8 *start, size_t len, struct ieee802_11_elems *elems)
3594{
3595 size_t left = len;
3596 u8 *pos = start;
3597 int unknown = 0;
3598
3599 memset(elems, 0, sizeof(*elems));
3600
3601 while (left >= 2) {
3602 u8 id, elen;
3603
3604 id = *pos++;
3605 elen = *pos++;
3606 left -= 2;
3607
3608 if (elen > left)
3609 return -1;
3610
3611 switch (id) {
3612 case WLAN_EID_DS_PARAMS:
3613 elems->ds_params = pos;
3614 elems->ds_params_len = elen;
3615 break;
3616 case WLAN_EID_TIM:
3617 elems->tim = pos;
3618 elems->tim_len = elen;
3619 break;
3620 case WLAN_EID_IBSS_PARAMS:
3621 elems->ibss_params = pos;
3622 elems->ibss_params_len = elen;
3623 break;
3624 case WLAN_EID_ERP_INFO:
3625 elems->erp_info = pos;
3626 elems->erp_info_len = elen;
3627 break;
3628 case WLAN_EID_HT_CAPABILITY:
3629 elems->ht_cap_param = pos;
3630 elems->ht_cap_param_len = elen;
3631 break;
3632 case WLAN_EID_HT_EXTRA_INFO:
3633 elems->ht_extra_param = pos;
3634 elems->ht_extra_param_len = elen;
3635 break;
3636 default:
3637 unknown++;
3638 break;
3639 }
3640
3641 left -= elen;
3642 pos += elen;
3643 }
3644
3645 return 0;
3646}
326eeee8 3647
78330fdd
TW		 3648void iwl4965_init_ht_hw_capab(struct ieee80211_ht_info *ht_info,
3649 enum ieee80211_band band)
326eeee8
RR		 3650{
3651 ht_info->cap = 0;
3652 memset(ht_info->supp_mcs_set, 0, 16);
3653
3654 ht_info->ht_supported = 1;
3655
78330fdd 3656 if (band == IEEE80211_BAND_5GHZ) {
326eeee8
RR		 3657 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3658 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3659 ht_info->supp_mcs_set[4] = 0x01;
3660 }
3661 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3662 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3663 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3664 (IWL_MIMO_PS_NONE << 2));
00acbc91 3665 if (iwl4965_mod_params.amsdu_size_8K) {
9ee1ba47
RR		 3666 printk(KERN_DEBUG "iwl4965 in A-MSDU 8K support mode\n");
3667 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
3668 }
326eeee8
RR		 3669
3670 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3671 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3672
3673 ht_info->supp_mcs_set[0] = 0xFF;
3674 ht_info->supp_mcs_set[1] = 0xFF;
3675}
c8b0e6e1 3676#endif /* CONFIG_IWL4965_HT */
b481de9c 3677
c79dd5b5 3678static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 3679{
3680 unsigned long flags;
3681
3682 spin_lock_irqsave(&priv->sta_lock, flags);
3683 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3684 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3685 priv->stations[sta_id].sta.sta.modify_mask = 0;
3686 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3687 spin_unlock_irqrestore(&priv->sta_lock, flags);
3688
bb8c093b 3689 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3690}
3691
c79dd5b5 3692static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 3693{
3694 /* FIXME: need locking over ps_status ??? */
bb8c093b 3695 u8 sta_id = iwl4965_hw_find_station(priv, addr);
b481de9c
ZY		 3696
3697 if (sta_id != IWL_INVALID_STATION) {
3698 u8 sta_awake = priv->stations[sta_id].
3699 ps_status == STA_PS_STATUS_WAKE;
3700
3701 if (sta_awake && ps_bit)
3702 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3703 else if (!sta_awake && !ps_bit) {
3704 iwl4965_sta_modify_ps_wake(priv, sta_id);
3705 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3706 }
3707 }
3708}
0a6857e7 3709#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 3710
3711/**
3712 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3713 *
3714 * You may hack this function to show different aspects of received frames,
3715 * including selective frame dumps.
3716 * group100 parameter selects whether to show 1 out of 100 good frames.
3717 *
3718 * TODO: This was originally written for 3945, need to audit for
3719 * proper operation with 4965.
3720 */
c79dd5b5 3721static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3722 struct iwl4965_rx_packet *pkt,
3723 struct ieee80211_hdr *header, int group100)
3724{
3725 u32 to_us;
3726 u32 print_summary = 0;
3727 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3728 u32 hundred = 0;
3729 u32 dataframe = 0;
3730 u16 fc;
3731 u16 seq_ctl;
3732 u16 channel;
3733 u16 phy_flags;
3734 int rate_sym;
3735 u16 length;
3736 u16 status;
3737 u16 bcn_tmr;
3738 u32 tsf_low;
3739 u64 tsf;
3740 u8 rssi;
3741 u8 agc;
3742 u16 sig_avg;
3743 u16 noise_diff;
3744 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3745 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3746 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3747 u8 *data = IWL_RX_DATA(pkt);
3748
0a6857e7 3749 if (likely(!(iwl_debug_level & IWL_DL_RX)))
17744ff6
TW		 3750 return;
3751
3752 /* MAC header */
3753 fc = le16_to_cpu(header->frame_control);
3754 seq_ctl = le16_to_cpu(header->seq_ctrl);
3755
3756 /* metadata */
3757 channel = le16_to_cpu(rx_hdr->channel);
3758 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3759 rate_sym = rx_hdr->rate;
3760 length = le16_to_cpu(rx_hdr->len);
3761
3762 /* end-of-frame status and timestamp */
3763 status = le32_to_cpu(rx_end->status);
3764 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3765 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3766 tsf = le64_to_cpu(rx_end->timestamp);
3767
3768 /* signal statistics */
3769 rssi = rx_stats->rssi;
3770 agc = rx_stats->agc;
3771 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3772 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3773
3774 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3775
3776 /* if data frame is to us and all is good,
3777 * (optionally) print summary for only 1 out of every 100 */
3778 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3779 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3780 dataframe = 1;
3781 if (!group100)
3782 print_summary = 1; /* print each frame */
3783 else if (priv->framecnt_to_us < 100) {
3784 priv->framecnt_to_us++;
3785 print_summary = 0;
3786 } else {
3787 priv->framecnt_to_us = 0;
3788 print_summary = 1;
3789 hundred = 1;
3790 }
3791 } else {
3792 /* print summary for all other frames */
3793 print_summary = 1;
3794 }
3795
3796 if (print_summary) {
3797 char *title;
3798 int rate_idx;
3799 u32 bitrate;
3800
3801 if (hundred)
3802 title = "100Frames";
3803 else if (fc & IEEE80211_FCTL_RETRY)
3804 title = "Retry";
3805 else if (ieee80211_is_assoc_response(fc))
3806 title = "AscRsp";
3807 else if (ieee80211_is_reassoc_response(fc))
3808 title = "RasRsp";
3809 else if (ieee80211_is_probe_response(fc)) {
3810 title = "PrbRsp";
3811 print_dump = 1; /* dump frame contents */
3812 } else if (ieee80211_is_beacon(fc)) {
3813 title = "Beacon";
3814 print_dump = 1; /* dump frame contents */
3815 } else if (ieee80211_is_atim(fc))
3816 title = "ATIM";
3817 else if (ieee80211_is_auth(fc))
3818 title = "Auth";
3819 else if (ieee80211_is_deauth(fc))
3820 title = "DeAuth";
3821 else if (ieee80211_is_disassoc(fc))
3822 title = "DisAssoc";
3823 else
3824 title = "Frame";
3825
3826 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3827 if (unlikely(rate_idx == -1))
3828 bitrate = 0;
3829 else
3830 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3831
3832 /* print frame summary.
3833 * MAC addresses show just the last byte (for brevity),
3834 * but you can hack it to show more, if you'd like to. */
3835 if (dataframe)
3836 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3837 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3838 title, fc, header->addr1[5],
3839 length, rssi, channel, bitrate);
3840 else {
3841 /* src/dst addresses assume managed mode */
3842 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3843 "src=0x%02x, rssi=%u, tim=%lu usec, "
3844 "phy=0x%02x, chnl=%d\n",
3845 title, fc, header->addr1[5],
3846 header->addr3[5], rssi,
3847 tsf_low - priv->scan_start_tsf,
3848 phy_flags, channel);
3849 }
3850 }
3851 if (print_dump)
0a6857e7 3852 iwl_print_hex_dump(IWL_DL_RX, data, length);
17744ff6
TW		 3853}
3854#else
c79dd5b5 3855static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3856 struct iwl4965_rx_packet *pkt,
3857 struct ieee80211_hdr *header,
3858 int group100)
3859{
3860}
3861#endif
3862
b481de9c 3863
7878a5a4
MA		 3864#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
3865
b481de9c
ZY		 3866/* Called for REPLY_4965_RX (legacy ABG frames), or
3867 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
c79dd5b5 3868static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
bb8c093b 3869 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3870{
17744ff6
TW		 3871 struct ieee80211_hdr *header;
3872 struct ieee80211_rx_status rx_status;
bb8c093b 3873 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3874 /* Use phy data (Rx signal strength, etc.) contained within
3875 * this rx packet for legacy frames,
3876 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3877 int include_phy = (pkt->hdr.cmd == REPLY_4965_RX);
3878 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3879 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3880 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3881 __le32 *rx_end;
3882 unsigned int len = 0;
b481de9c 3883 u16 fc;
b481de9c
ZY		 3884 u8 network_packet;
3885
17744ff6
TW		 3886 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
3887 rx_status.freq = ieee80211chan2mhz(le16_to_cpu(rx_start->channel));
3888 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3889 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
3890 rx_status.rate_idx = iwl4965_hwrate_to_plcp_idx(
3891 le32_to_cpu(rx_start->rate_n_flags));
3892
3893 if (rx_status.band == IEEE80211_BAND_5GHZ)
3894 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3895
3896 rx_status.antenna = 0;
3897 rx_status.flag = 0;
3898
b481de9c
ZY		 3899 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3900 IWL_DEBUG_DROP
3901 ("dsp size out of range [0,20]: "
3902 "%d/n", rx_start->cfg_phy_cnt);
3903 return;
3904 }
17744ff6 3905
b481de9c
ZY		 3906 if (!include_phy) {
3907 if (priv->last_phy_res[0])
3908 rx_start = (struct iwl4965_rx_phy_res *)
3909 &priv->last_phy_res[1];
3910 else
3911 rx_start = NULL;
3912 }
3913
3914 if (!rx_start) {
3915 IWL_ERROR("MPDU frame without a PHY data\n");
3916 return;
3917 }
3918
3919 if (include_phy) {
3920 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3921 + rx_start->cfg_phy_cnt);
3922
3923 len = le16_to_cpu(rx_start->byte_count);
17744ff6 3924 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 3925 sizeof(struct iwl4965_rx_phy_res) + len);
3926 } else {
3927 struct iwl4965_rx_mpdu_res_start *amsdu =
3928 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3929
3930 header = (void *)(pkt->u.raw +
3931 sizeof(struct iwl4965_rx_mpdu_res_start));
3932 len = le16_to_cpu(amsdu->byte_count);
3933 rx_end = (__le32 *) (pkt->u.raw +
3934 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3935 }
3936
3937 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3938 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3939 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3940 le32_to_cpu(*rx_end));
3941 return;
3942 }
3943
3944 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3945
b481de9c 3946 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
17744ff6 3947 rx_status.ssi = iwl4965_calc_rssi(rx_start);
b481de9c
ZY		 3948
3949 /* Meaningful noise values are available only from beacon statistics,
3950 * which are gathered only when associated, and indicate noise
3951 * only for the associated network channel ...
3952 * Ignore these noise values while scanning (other channels) */
bb8c093b 3953 if (iwl4965_is_associated(priv) &&
b481de9c 3954 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6
TW		 3955 rx_status.noise = priv->last_rx_noise;
3956 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3957 rx_status.noise);
b481de9c 3958 } else {
17744ff6
TW		 3959 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3960 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
b481de9c
ZY		 3961 }
3962
3963 /* Reset beacon noise level if not associated. */
bb8c093b 3964 if (!iwl4965_is_associated(priv))
b481de9c
ZY		 3965 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3966
17744ff6
TW		 3967 /* Set "1" to report good data frames in groups of 100 */
3968 /* FIXME: need to optimze the call: */
3969 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3970
3971 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3972 rx_status.ssi, rx_status.noise, rx_status.signal,
3973 rx_status.mactime);
b481de9c 3974
bb8c093b 3975 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 3976 if (network_packet) {
17744ff6 3977 priv->last_rx_rssi = rx_status.ssi;
b481de9c
ZY		 3978 priv->last_beacon_time = priv->ucode_beacon_time;
3979 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3980 }
3981
3982 fc = le16_to_cpu(header->frame_control);
3983 switch (fc & IEEE80211_FCTL_FTYPE) {
3984 case IEEE80211_FTYPE_MGMT:
3985
3986 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3987 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3988 header->addr2);
3989 switch (fc & IEEE80211_FCTL_STYPE) {
3990 case IEEE80211_STYPE_PROBE_RESP:
3991 case IEEE80211_STYPE_BEACON:
3992 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA &&
3993 !compare_ether_addr(header->addr2, priv->bssid)) ||
3994 (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
3995 !compare_ether_addr(header->addr3, priv->bssid))) {
3996 struct ieee80211_mgmt *mgmt =
3997 (struct ieee80211_mgmt *)header;
3998 u64 timestamp =
3999 le64_to_cpu(mgmt->u.beacon.timestamp);
4000
4001 priv->timestamp0 = timestamp & 0xFFFFFFFF;
4002 priv->timestamp1 =
4003 (timestamp >> 32) & 0xFFFFFFFF;
4004 priv->beacon_int = le16_to_cpu(
4005 mgmt->u.beacon.beacon_int);
4006 if (priv->call_post_assoc_from_beacon &&
4007 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
4008 priv->call_post_assoc_from_beacon = 0;
4009 queue_work(priv->workqueue,
4010 &priv->post_associate.work);
4011 }
4012 }
4013 break;
4014
4015 case IEEE80211_STYPE_ACTION:
4016 break;
4017
4018 /*
471b3efd
JB		 4019 * TODO: Use the new callback function from
4020 * mac80211 instead of sniffing these packets.
b481de9c
ZY		 4021 */
4022 case IEEE80211_STYPE_ASSOC_RESP:
4023 case IEEE80211_STYPE_REASSOC_RESP:
052c4b9f 4024 if (network_packet) {
c8b0e6e1 4025#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 4026 u8 *pos = NULL;
4027 struct ieee802_11_elems elems;
c8b0e6e1 4028#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 4029 struct ieee80211_mgmt *mgnt =
4030 (struct ieee80211_mgmt *)header;
4031
7878a5a4
MA		 4032 /* We have just associated, give some
4033 * time for the 4-way handshake if
4034 * any. Don't start scan too early. */
4035 priv->next_scan_jiffies = jiffies +
4036 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
4037
b481de9c
ZY		 4038 priv->assoc_id = (~((1 << 15) | (1 << 14))
4039 & le16_to_cpu(mgnt->u.assoc_resp.aid));
4040 priv->assoc_capability =
4041 le16_to_cpu(
4042 mgnt->u.assoc_resp.capab_info);
c8b0e6e1 4043#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 4044 pos = mgnt->u.assoc_resp.variable;
4045 if (!parse_elems(pos,
4046 len - (pos - (u8 *) mgnt),
4047 &elems)) {
4048 if (elems.ht_extra_param &&
4049 elems.ht_cap_param)
4050 break;
4051 }
c8b0e6e1 4052#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 4053 /* assoc_id is 0 no association */
4054 if (!priv->assoc_id)
4055 break;
4056 if (priv->beacon_int)
4057 queue_work(priv->workqueue,
4058 &priv->post_associate.work);
4059 else
4060 priv->call_post_assoc_from_beacon = 1;
4061 }
4062
4063 break;
4064
4065 case IEEE80211_STYPE_PROBE_REQ:
4066 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
bb8c093b 4067 !iwl4965_is_associated(priv)) {
0795af57
JP		 4068 DECLARE_MAC_BUF(mac1);
4069 DECLARE_MAC_BUF(mac2);
4070 DECLARE_MAC_BUF(mac3);
4071
b481de9c 4072 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 4073 "%s, %s, %s\n",
4074 print_mac(mac1, header->addr1),
4075 print_mac(mac2, header->addr2),
4076 print_mac(mac3, header->addr3));
b481de9c
ZY		 4077 return;
4078 }
4079 }
17744ff6 4080 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 4081 break;
4082
4083 case IEEE80211_FTYPE_CTL:
9ab46173 4084#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 4085 switch (fc & IEEE80211_FCTL_STYPE) {
4086 case IEEE80211_STYPE_BACK_REQ:
4087 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
4088 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 4089 rxb, &rx_status);
b481de9c
ZY		 4090 break;
4091 default:
4092 break;
4093 }
4094#endif
b481de9c
ZY		 4095 break;
4096
0795af57
JP		 4097 case IEEE80211_FTYPE_DATA: {
4098 DECLARE_MAC_BUF(mac1);
4099 DECLARE_MAC_BUF(mac2);
4100 DECLARE_MAC_BUF(mac3);
4101
b481de9c
ZY		 4102 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4103 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4104 header->addr2);
4105
4106 if (unlikely(!network_packet))
4107 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 4108 "%s, %s, %s\n",
4109 print_mac(mac1, header->addr1),
4110 print_mac(mac2, header->addr2),
4111 print_mac(mac3, header->addr3));
bb8c093b 4112 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 4113 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
4114 print_mac(mac1, header->addr1),
4115 print_mac(mac2, header->addr2),
4116 print_mac(mac3, header->addr3));
b481de9c
ZY		 4117 else
4118 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 4119 &rx_status);
b481de9c 4120 break;
0795af57 4121 }
b481de9c
ZY		 4122 default:
4123 break;
4124
4125 }
4126}
4127
4128/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
4129 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
c79dd5b5 4130static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
bb8c093b 4131 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4132{
bb8c093b 4133 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 4134 priv->last_phy_res[0] = 1;
4135 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
4136 sizeof(struct iwl4965_rx_phy_res));
4137}
4138
c79dd5b5 4139static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
bb8c093b 4140 struct iwl4965_rx_mem_buffer *rxb)
b481de9c
ZY		 4141
4142{
c8b0e6e1 4143#ifdef CONFIG_IWL4965_SENSITIVITY
bb8c093b
CH		 4144 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4145 struct iwl4965_missed_beacon_notif *missed_beacon;
b481de9c
ZY		 4146
4147 missed_beacon = &pkt->u.missed_beacon;
4148 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
4149 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
4150 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
4151 le32_to_cpu(missed_beacon->total_missed_becons),
4152 le32_to_cpu(missed_beacon->num_recvd_beacons),
4153 le32_to_cpu(missed_beacon->num_expected_beacons));
4154 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
4155 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
4156 queue_work(priv->workqueue, &priv->sensitivity_work);
4157 }
c8b0e6e1 4158#endif /*CONFIG_IWL4965_SENSITIVITY*/
b481de9c
ZY		 4159}
4160
c8b0e6e1 4161#ifdef CONFIG_IWL4965_HT
b481de9c 4162
8b6eaea8
CB		 4163/**
4164 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
4165 */
c79dd5b5 4166static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
b481de9c
ZY		 4167 int sta_id, int tid)
4168{
4169 unsigned long flags;
4170
8b6eaea8 4171 /* Remove "disable" flag, to enable Tx for this TID */
b481de9c
ZY		 4172 spin_lock_irqsave(&priv->sta_lock, flags);
4173 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
4174 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
4175 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4176 spin_unlock_irqrestore(&priv->sta_lock, flags);
4177
bb8c093b 4178 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4179}
4180
8b6eaea8
CB		 4181/**
4182 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
4183 *
4184 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
4185 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
4186 */
c79dd5b5 4187static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b
CH		 4188 struct iwl4965_ht_agg *agg,
4189 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 4190 ba_resp)
4191
4192{
4193 int i, sh, ack;
fe01b477
RR		 4194 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
4195 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
4196 u64 bitmap;
4197 int successes = 0;
4198 struct ieee80211_tx_status *tx_status;
b481de9c
ZY		 4199
4200 if (unlikely(!agg->wait_for_ba)) {
4201 IWL_ERROR("Received BA when not expected\n");
4202 return -EINVAL;
4203 }
8b6eaea8
CB		 4204
4205 /* Mark that the expected block-ack response arrived */
b481de9c 4206 agg->wait_for_ba = 0;
fe01b477 4207 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 4208
4209 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 4210 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 4211 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 4212 sh += 0x100;
4213
8b6eaea8 4214 /* don't use 64-bit values for now */
fe01b477 4215 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 4216
4217 if (agg->frame_count > (64 - sh)) {
4218 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
4219 return -1;
4220 }
4221
4222 /* check for success or failure according to the
8b6eaea8 4223 * transmitted bitmap and block-ack bitmap */
fe01b477 4224 bitmap &= agg->bitmap;
b481de9c 4225
8b6eaea8
CB		 4226 /* For each frame attempted in aggregation,
4227 * update driver's record of tx frame's status. */
b481de9c 4228 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 4229 ack = bitmap & (1 << i);
4230 successes += !!ack;
b481de9c 4231 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 4232 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
4233 agg->start_idx + i);
4234 }
4235
4236 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
4237 tx_status->flags = IEEE80211_TX_STATUS_ACK;
99556438
RR		 4238 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
4239 tx_status->ampdu_ack_map = successes;
4240 tx_status->ampdu_ack_len = agg->frame_count;
4c424e4c
RR		 4241 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
4242 &tx_status->control);
fe01b477 4243
f868f4e1 4244 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 4245
4246 return 0;
4247}
4248
4249/**
4250 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
4251 */
c79dd5b5 4252static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 4253 u16 txq_id)
4254{
4255 /* Simply stop the queue, but don't change any configuration;
4256 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
4257 iwl4965_write_prph(priv,
4258 KDR_SCD_QUEUE_STATUS_BITS(txq_id),
4259 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
4260 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
4261}
b481de9c 4262
fe01b477
RR		 4263/**
4264 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
b095d03a 4265 * priv->lock must be held by the caller
fe01b477 4266 */
c79dd5b5 4267static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
fe01b477
RR		 4268 u16 ssn_idx, u8 tx_fifo)
4269{
b095d03a
RR		 4270 int ret = 0;
4271
fe01b477
RR		 4272 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
4273 IWL_WARNING("queue number too small: %d, must be > %d\n",
4274 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4275 return -EINVAL;
b481de9c
ZY		 4276 }
4277
b095d03a
RR		 4278 ret = iwl4965_grab_nic_access(priv);
4279 if (ret)
4280 return ret;
4281
fe01b477
RR		 4282 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4283
4284 iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
4285
4286 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4287 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
4288 /* supposes that ssn_idx is valid (!= 0xFFF) */
4289 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4290
4291 iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
4292 iwl4965_txq_ctx_deactivate(priv, txq_id);
4293 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4294
b095d03a
RR		 4295 iwl4965_release_nic_access(priv);
4296
fe01b477
RR		 4297 return 0;
4298}
b481de9c 4299
c79dd5b5 4300int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
fe01b477
RR		 4301 u8 tid, int txq_id)
4302{
4303 struct iwl4965_queue *q = &priv->txq[txq_id].q;
4304 u8 *addr = priv->stations[sta_id].sta.sta.addr;
4305 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
4306
4307 switch (priv->stations[sta_id].tid[tid].agg.state) {
4308 case IWL_EMPTYING_HW_QUEUE_DELBA:
4309 /* We are reclaiming the last packet of the */
4310 /* aggregated HW queue */
4311 if (txq_id == tid_data->agg.txq_id &&
4312 q->read_ptr == q->write_ptr) {
4313 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
4314 int tx_fifo = default_tid_to_tx_fifo[tid];
4315 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
4316 iwl4965_tx_queue_agg_disable(priv, txq_id,
4317 ssn, tx_fifo);
4318 tid_data->agg.state = IWL_AGG_OFF;
4319 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4320 }
4321 break;
4322 case IWL_EMPTYING_HW_QUEUE_ADDBA:
4323 /* We are reclaiming the last packet of the queue */
4324 if (tid_data->tfds_in_queue == 0) {
4325 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
4326 tid_data->agg.state = IWL_AGG_ON;
4327 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4328 }
4329 break;
4330 }
b481de9c
ZY		 4331 return 0;
4332}
4333
8b6eaea8
CB		 4334/**
4335 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
4336 * @index -- current index
4337 * @n_bd -- total number of entries in queue (s/b power of 2)
4338 */
bb8c093b 4339static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 4340{
4341 return (index == 0) ? n_bd - 1 : index - 1;
4342}
4343
8b6eaea8
CB		 4344/**
4345 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
4346 *
4347 * Handles block-acknowledge notification from device, which reports success
4348 * of frames sent via aggregation.
4349 */
c79dd5b5 4350static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b 4351 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4352{
bb8c093b
CH		 4353 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4354 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 4355 int index;
bb8c093b
CH		 4356 struct iwl4965_tx_queue *txq = NULL;
4357 struct iwl4965_ht_agg *agg;
fe01b477 4358 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 4359
4360 /* "flow" corresponds to Tx queue */
fe01b477 4361 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 4362
4363 /* "ssn" is start of block-ack Tx window, corresponds to index
4364 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 4365 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
4366
fe01b477 4367 if (scd_flow >= ARRAY_SIZE(priv->txq)) {
b481de9c
ZY		 4368 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
4369 return;
4370 }
4371
fe01b477 4372 txq = &priv->txq[scd_flow];
b481de9c 4373 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 4374
4375 /* Find index just before block-ack window */
bb8c093b 4376 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 4377
01ebd063 4378 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 4379
0795af57
JP		 4380 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
4381 "sta_id = %d\n",
b481de9c 4382 agg->wait_for_ba,
0795af57 4383 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 4384 ba_resp->sta_id);
fe01b477 4385 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 4386 "%d, scd_ssn = %d\n",
4387 ba_resp->tid,
fe01b477 4388 ba_resp->seq_ctl,
0310ae72 4389 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 4390 ba_resp->scd_flow,
4391 ba_resp->scd_ssn);
fe01b477 4392 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 4393 agg->start_idx,
f868f4e1 4394 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 4395
4396 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 4397 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 4398
4399 /* Release all TFDs before the SSN, i.e. all TFDs in front of
4400 * block-ack window (we assume that they've been successfully
4401 * transmitted ... if not, it's too late anyway). */
fe01b477
RR		 4402 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
4403 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
4404 priv->stations[ba_resp->sta_id].
4405 tid[ba_resp->tid].tfds_in_queue -= freed;
4406 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
4407 priv->mac80211_registered &&
4408 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
4409 ieee80211_wake_queue(priv->hw, scd_flow);
4410 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
4411 ba_resp->tid, scd_flow);
4412 }
b481de9c
ZY		 4413}
4414
8b6eaea8
CB		 4415/**
4416 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
4417 */
c79dd5b5 4418static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 4419 u16 txq_id)
4420{
4421 u32 tbl_dw_addr;
4422 u32 tbl_dw;
4423 u16 scd_q2ratid;
4424
4425 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
4426
4427 tbl_dw_addr = priv->scd_base_addr +
4428 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
4429
bb8c093b 4430 tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 4431
4432 if (txq_id & 0x1)
4433 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
4434 else
4435 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
4436
bb8c093b 4437 iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 4438
4439 return 0;
4440}
4441
fe01b477 4442
b481de9c 4443/**
8b6eaea8
CB		 4444 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
4445 *
4446 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
4447 * i.e. it must be one of the higher queues used for aggregation
b481de9c 4448 */
c79dd5b5 4449static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
b481de9c
ZY		 4450 int tx_fifo, int sta_id, int tid,
4451 u16 ssn_idx)
4452{
4453 unsigned long flags;
4454 int rc;
4455 u16 ra_tid;
4456
4457 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
4458 IWL_WARNING("queue number too small: %d, must be > %d\n",
4459 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4460
4461 ra_tid = BUILD_RAxTID(sta_id, tid);
4462
8b6eaea8 4463 /* Modify device's station table to Tx this TID */
bb8c093b 4464 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 4465
4466 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 4467 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 4468 if (rc) {
4469 spin_unlock_irqrestore(&priv->lock, flags);
4470 return rc;
4471 }
4472
8b6eaea8 4473 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 4474 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4475
8b6eaea8 4476 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 4477 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
4478
8b6eaea8 4479 /* Set this queue as a chain-building queue */
8a1b0245 4480 iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 4481
8b6eaea8
CB		 4482 /* Place first TFD at index corresponding to start sequence number.
4483 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 4484 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4485 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 4486 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4487
8b6eaea8 4488 /* Set up Tx window size and frame limit for this queue */
bb8c093b 4489 iwl4965_write_targ_mem(priv,
b481de9c
ZY		 4490 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
4491 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4492 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4493
bb8c093b 4494 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 4495 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
4496 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4497 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4498
bb8c093b 4499 iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 4500
8b6eaea8 4501 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 4502 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4503
bb8c093b 4504 iwl4965_release_nic_access(priv);
b481de9c
ZY		 4505 spin_unlock_irqrestore(&priv->lock, flags);
4506
4507 return 0;
4508}
4509
c8b0e6e1 4510#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4511
4512/**
4513 * iwl4965_add_station - Initialize a station's hardware rate table
4514 *
8b6eaea8 4515 * The uCode's station table contains a table of fallback rates
b481de9c
ZY		 4516 * for automatic fallback during transmission.
4517 *
8b6eaea8
CB		 4518 * NOTE: This sets up a default set of values. These will be replaced later
4519 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
4520 * rc80211_simple.
b481de9c 4521 *
8b6eaea8
CB		 4522 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
4523 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
4524 * which requires station table entry to exist).
b481de9c 4525 */
c79dd5b5 4526void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 4527{
4528 int i, r;
bb8c093b 4529 struct iwl4965_link_quality_cmd link_cmd = {
b481de9c
ZY		 4530 .reserved1 = 0,
4531 };
4532 u16 rate_flags;
4533
8b6eaea8
CB		 4534 /* Set up the rate scaling to start at selected rate, fall back
4535 * all the way down to 1M in IEEE order, and then spin on 1M */
b481de9c
ZY		 4536 if (is_ap)
4537 r = IWL_RATE_54M_INDEX;
8318d78a 4538 else if (priv->band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4539 r = IWL_RATE_6M_INDEX;
4540 else
4541 r = IWL_RATE_1M_INDEX;
4542
4543 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
4544 rate_flags = 0;
4545 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
4546 rate_flags |= RATE_MCS_CCK_MSK;
4547
8b6eaea8 4548 /* Use Tx antenna B only */
b481de9c
ZY		 4549 rate_flags |= RATE_MCS_ANT_B_MSK;
4550 rate_flags &= ~RATE_MCS_ANT_A_MSK;
8b6eaea8 4551
b481de9c 4552 link_cmd.rs_table[i].rate_n_flags =
bb8c093b
CH		 4553 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
4554 r = iwl4965_get_prev_ieee_rate(r);
b481de9c
ZY		 4555 }
4556
4557 link_cmd.general_params.single_stream_ant_msk = 2;
4558 link_cmd.general_params.dual_stream_ant_msk = 3;
4559 link_cmd.agg_params.agg_dis_start_th = 3;
4560 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
4561
4562 /* Update the rate scaling for control frame Tx to AP */
a4062b8f 4563 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_setting.bcast_sta_id;
b481de9c 4564
bb8c093b 4565 iwl4965_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
b481de9c
ZY		 4566 &link_cmd);
4567}
4568
c8b0e6e1 4569#ifdef CONFIG_IWL4965_HT
b481de9c 4570
c79dd5b5 4571static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
8318d78a 4572 enum ieee80211_band band,
78330fdd 4573 u16 channel, u8 extension_chan_offset)
b481de9c 4574{
bf85ea4f 4575 const struct iwl_channel_info *ch_info;
b481de9c 4576
8318d78a 4577 ch_info = iwl4965_get_channel_info(priv, band, channel);
b481de9c
ZY		 4578 if (!is_channel_valid(ch_info))
4579 return 0;
4580
134eb5d3 4581 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
b481de9c
ZY		 4582 return 0;
4583
4584 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
4585 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
4586 return 1;
4587
4588 return 0;
4589}
4590
c79dd5b5 4591static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
fd105e79 4592 struct ieee80211_ht_info *sta_ht_inf)
b481de9c 4593{
fd105e79 4594 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
b481de9c 4595
fd105e79
RR		 4596 if ((!iwl_ht_conf->is_ht) ||
4597 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
134eb5d3 4598 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
b481de9c
ZY		 4599 return 0;
4600
fd105e79
RR		 4601 if (sta_ht_inf) {
4602 if ((!sta_ht_inf->ht_supported) ||
194c7ca6 4603 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
fd105e79
RR		 4604 return 0;
4605 }
b481de9c 4606
78330fdd 4607 return (iwl4965_is_channel_extension(priv, priv->band,
fd105e79
RR		 4608 iwl_ht_conf->control_channel,
4609 iwl_ht_conf->extension_chan_offset));
b481de9c
ZY		 4610}
4611
c79dd5b5 4612void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
b481de9c 4613{
bb8c093b 4614 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 4615 u32 val;
4616
4617 if (!ht_info->is_ht)
4618 return;
4619
8b6eaea8 4620 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
fd105e79 4621 if (iwl4965_is_fat_tx_allowed(priv, NULL))
b481de9c
ZY		 4622 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4623 else
4624 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4625 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
4626
4627 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
4628 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4629 le16_to_cpu(rxon->channel),
4630 ht_info->control_channel);
4631 rxon->channel = cpu_to_le16(ht_info->control_channel);
4632 return;
4633 }
4634
8b6eaea8 4635 /* Note: control channel is opposite of extension channel */
b481de9c
ZY		 4636 switch (ht_info->extension_chan_offset) {
4637 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4638 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4639 break;
4640 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4641 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4642 break;
134eb5d3 4643 case IWL_EXT_CHANNEL_OFFSET_NONE:
b481de9c
ZY		 4644 default:
4645 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4646 break;
4647 }
4648
fd105e79 4649 val = ht_info->ht_protection;
b481de9c
ZY		 4650
4651 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4652
b481de9c
ZY		 4653 iwl4965_set_rxon_chain(priv);
4654
4655 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
4656 "rxon flags 0x%X operation mode :0x%X "
4657 "extension channel offset 0x%x "
4658 "control chan %d\n",
fd105e79
RR		 4659 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
4660 le32_to_cpu(rxon->flags), ht_info->ht_protection,
b481de9c
ZY		 4661 ht_info->extension_chan_offset,
4662 ht_info->control_channel);
4663 return;
4664}
4665
c79dd5b5 4666void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
67d62035 4667 struct ieee80211_ht_info *sta_ht_inf)
b481de9c
ZY		 4668{
4669 __le32 sta_flags;
e53cfe0e 4670 u8 mimo_ps_mode;
b481de9c 4671
67d62035 4672 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
b481de9c
ZY		 4673 goto done;
4674
e53cfe0e
TW		 4675 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4676
b481de9c
ZY		 4677 sta_flags = priv->stations[index].sta.station_flags;
4678
e53cfe0e
TW		 4679 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4680
4681 switch (mimo_ps_mode) {
4682 case WLAN_HT_CAP_MIMO_PS_STATIC:
4683 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4684 break;
4685 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
b481de9c 4686 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
e53cfe0e
TW		 4687 break;
4688 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4689 break;
4690 default:
4691 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4692 break;
4693 }
b481de9c
ZY		 4694
4695 sta_flags |= cpu_to_le32(
67d62035 4696 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
b481de9c
ZY		 4697
4698 sta_flags |= cpu_to_le32(
67d62035 4699 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
b481de9c 4700
67d62035 4701 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
b481de9c 4702 sta_flags |= STA_FLG_FAT_EN_MSK;
67d62035 4703 else
e53cfe0e 4704 sta_flags &= ~STA_FLG_FAT_EN_MSK;
67d62035 4705
b481de9c
ZY		 4706 priv->stations[index].sta.station_flags = sta_flags;
4707 done:
4708 return;
4709}
4710
c79dd5b5 4711static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
b481de9c
ZY		 4712 int sta_id, int tid, u16 ssn)
4713{
4714 unsigned long flags;
4715
4716 spin_lock_irqsave(&priv->sta_lock, flags);
4717 priv->stations[sta_id].sta.station_flags_msk = 0;
4718 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4719 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4720 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4721 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4722 spin_unlock_irqrestore(&priv->sta_lock, flags);
4723
bb8c093b 4724 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4725}
4726
c79dd5b5 4727static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
b481de9c
ZY		 4728 int sta_id, int tid)
4729{
4730 unsigned long flags;
4731
4732 spin_lock_irqsave(&priv->sta_lock, flags);
4733 priv->stations[sta_id].sta.station_flags_msk = 0;
4734 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4735 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4736 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4737 spin_unlock_irqrestore(&priv->sta_lock, flags);
4738
bb8c093b 4739 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4740}
4741
8b6eaea8
CB		 4742/*
4743 * Find first available (lowest unused) Tx Queue, mark it "active".
4744 * Called only when finding queue for aggregation.
4745 * Should never return anything < 7, because they should already
4746 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4747 */
c79dd5b5 4748static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
b481de9c
ZY		 4749{
4750 int txq_id;
4751
4752 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
4753 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4754 return txq_id;
4755 return -1;
4756}
4757
fe01b477
RR		 4758static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
4759 u16 tid, u16 *start_seq_num)
b481de9c 4760{
c79dd5b5 4761 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 4762 int sta_id;
4763 int tx_fifo;
4764 int txq_id;
4765 int ssn = -1;
b095d03a 4766 int ret = 0;
b481de9c 4767 unsigned long flags;
bb8c093b 4768 struct iwl4965_tid_data *tid_data;
0795af57 4769 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 4770
4771 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4772 tx_fifo = default_tid_to_tx_fifo[tid];
4773 else
4774 return -EINVAL;
4775
fe01b477
RR		 4776 IWL_WARNING("%s on da = %s tid = %d\n",
4777 __func__, print_mac(mac, da), tid);
b481de9c 4778
bb8c093b 4779 sta_id = iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 4780 if (sta_id == IWL_INVALID_STATION)
4781 return -ENXIO;
4782
fe01b477
RR		 4783 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4784 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4785 return -ENXIO;
4786 }
4787
bb8c093b 4788 txq_id = iwl4965_txq_ctx_activate_free(priv);
b481de9c
ZY		 4789 if (txq_id == -1)
4790 return -ENXIO;
4791
4792 spin_lock_irqsave(&priv->sta_lock, flags);
4793 tid_data = &priv->stations[sta_id].tid[tid];
4794 ssn = SEQ_TO_SN(tid_data->seq_number);
4795 tid_data->agg.txq_id = txq_id;
4796 spin_unlock_irqrestore(&priv->sta_lock, flags);
4797
4798 *start_seq_num = ssn;
b095d03a
RR		 4799 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4800 sta_id, tid, ssn);
4801 if (ret)
4802 return ret;
b481de9c 4803
b095d03a 4804 ret = 0;
fe01b477
RR		 4805 if (tid_data->tfds_in_queue == 0) {
4806 printk(KERN_ERR "HW queue is empty\n");
4807 tid_data->agg.state = IWL_AGG_ON;
4808 ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
4809 } else {
4810 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4811 tid_data->tfds_in_queue);
4812 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4813 }
b095d03a 4814 return ret;
fe01b477 4815}
b481de9c 4816
fe01b477
RR		 4817static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
4818 u16 tid)
b481de9c
ZY		 4819{
4820
c79dd5b5 4821 struct iwl_priv *priv = hw->priv;
b481de9c 4822 int tx_fifo_id, txq_id, sta_id, ssn = -1;
bb8c093b 4823 struct iwl4965_tid_data *tid_data;
b095d03a 4824 int ret, write_ptr, read_ptr;
fe01b477 4825 unsigned long flags;
0795af57
JP		 4826 DECLARE_MAC_BUF(mac);
4827
b481de9c 4828 if (!da) {
fe01b477 4829 IWL_ERROR("da = NULL\n");
b481de9c
ZY		 4830 return -EINVAL;
4831 }
4832
4833 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4834 tx_fifo_id = default_tid_to_tx_fifo[tid];
4835 else
4836 return -EINVAL;
4837
bb8c093b 4838 sta_id = iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 4839
4840 if (sta_id == IWL_INVALID_STATION)
4841 return -ENXIO;
4842
fe01b477
RR		 4843 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4844 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4845
b481de9c
ZY		 4846 tid_data = &priv->stations[sta_id].tid[tid];
4847 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4848 txq_id = tid_data->agg.txq_id;
fe01b477
RR		 4849 write_ptr = priv->txq[txq_id].q.write_ptr;
4850 read_ptr = priv->txq[txq_id].q.read_ptr;
4851
4852 /* The queue is not empty */
4853 if (write_ptr != read_ptr) {
4854 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4855 priv->stations[sta_id].tid[tid].agg.state =
4856 IWL_EMPTYING_HW_QUEUE_DELBA;
4857 return 0;
4858 }
4859
4860 IWL_DEBUG_HT("HW queue empty\n");;
4861 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
b481de9c 4862
fe01b477 4863 spin_lock_irqsave(&priv->lock, flags);
b095d03a 4864 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
fe01b477
RR		 4865 spin_unlock_irqrestore(&priv->lock, flags);
4866
b095d03a
RR		 4867 if (ret)
4868 return ret;
b481de9c 4869
fe01b477 4870 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
b481de9c 4871
fe01b477
RR		 4872 IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
4873 print_mac(mac, da), tid);
8114fcf1 4874
8114fcf1
RR		 4875 return 0;
4876}
4877
4878int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4879 enum ieee80211_ampdu_mlme_action action,
4880 const u8 *addr, u16 tid, u16 *ssn)
4881{
c79dd5b5 4882 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 4883 int sta_id;
4884 DECLARE_MAC_BUF(mac);
4885
4886 IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
4887 print_mac(mac, addr), tid);
4888 sta_id = iwl4965_hw_find_station(priv, addr);
4889 switch (action) {
4890 case IEEE80211_AMPDU_RX_START:
4891 IWL_DEBUG_HT("start Rx\n");
4892 iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
4893 break;
4894 case IEEE80211_AMPDU_RX_STOP:
4895 IWL_DEBUG_HT("stop Rx\n");
4896 iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
4897 break;
4898 case IEEE80211_AMPDU_TX_START:
4899 IWL_DEBUG_HT("start Tx\n");
4900 return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
4901 case IEEE80211_AMPDU_TX_STOP:
4902 IWL_DEBUG_HT("stop Tx\n");
4903 return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
4904 default:
4905 IWL_DEBUG_HT("unknown\n");
4906 return -EINVAL;
4907 break;
4908 }
4909 return 0;
4910}
4911
c8b0e6e1 4912#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4913
4914/* Set up 4965-specific Rx frame reply handlers */
c79dd5b5 4915void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 4916{
4917 /* Legacy Rx frames */
4918 priv->rx_handlers[REPLY_4965_RX] = iwl4965_rx_reply_rx;
4919
4920 /* High-throughput (HT) Rx frames */
4921 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4922 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4923
4924 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4925 iwl4965_rx_missed_beacon_notif;
4926
c8b0e6e1 4927#ifdef CONFIG_IWL4965_HT
b481de9c 4928 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
c8b0e6e1 4929#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4930}
4931
c79dd5b5 4932void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4933{
4934 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4935 INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
c8b0e6e1 4936#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 4937 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4938#endif
b481de9c
ZY		 4939 init_timer(&priv->statistics_periodic);
4940 priv->statistics_periodic.data = (unsigned long)priv;
4941 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4942}
4943
c79dd5b5 4944void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4945{
4946 del_timer_sync(&priv->statistics_periodic);
4947
4948 cancel_delayed_work(&priv->init_alive_start);
4949}
4950
6bc913bd 4951static struct iwl_lib_ops iwl4965_lib = {
bf85ea4f 4952 .init_drv = iwl4965_init_drv,
6bc913bd
AK		 4953 .eeprom_ops = {
4954 .verify_signature = iwlcore_eeprom_verify_signature,
4955 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4956 .release_semaphore = iwlcore_eeprom_release_semaphore,
4957 },
4958};
4959
4960static struct iwl_ops iwl4965_ops = {
4961 .lib = &iwl4965_lib,
4962};
4963
82b9a121
TW		 4964static struct iwl_cfg iwl4965_agn_cfg = {
4965 .name = "4965AGN",
4bf775cd 4966 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 4967 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
6bc913bd 4968 .ops = &iwl4965_ops,
82b9a121
TW		 4969};
4970
bb8c093b 4971struct pci_device_id iwl4965_hw_card_ids[] = {
82b9a121
TW		 4972 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4973 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
b481de9c
ZY		 4974 {0}
4975};
4976
bb8c093b 4977MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);
Linux kernel - Deliverables
This page took 0.371459 seconds and 5 git commands to generate.