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iwlwifi: move iwl4965_rf_kill_ct_config to iwl-core.c
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
3e0d4cb1 42#include "iwl-dev.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c 45#include "iwl-helpers.h"
f0832f13 46#include "iwl-calib.h"
5083e563 47#include "iwl-sta.h"
b481de9c 48
630fe9b6
TW		 49static int iwl4965_send_tx_power(struct iwl_priv *priv);
50
1ea87396
AK		 51/* module parameters */
52static struct iwl_mod_params iwl4965_mod_params = {
038669e4 53 .num_of_queues = IWL49_NUM_QUEUES,
1ea87396
AK		 54 .enable_qos = 1,
55 .amsdu_size_8K = 1,
3a1081e8 56 .restart_fw = 1,
1ea87396
AK		 57 /* the rest are 0 by default */
58};
59
57aab75a
TW		 60/* check contents of special bootstrap uCode SRAM */
61static int iwl4965_verify_bsm(struct iwl_priv *priv)
62{
63 __le32 *image = priv->ucode_boot.v_addr;
64 u32 len = priv->ucode_boot.len;
65 u32 reg;
66 u32 val;
67
68 IWL_DEBUG_INFO("Begin verify bsm\n");
69
70 /* verify BSM SRAM contents */
71 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
72 for (reg = BSM_SRAM_LOWER_BOUND;
73 reg < BSM_SRAM_LOWER_BOUND + len;
74 reg += sizeof(u32), image++) {
75 val = iwl_read_prph(priv, reg);
76 if (val != le32_to_cpu(*image)) {
77 IWL_ERROR("BSM uCode verification failed at "
78 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
79 BSM_SRAM_LOWER_BOUND,
80 reg - BSM_SRAM_LOWER_BOUND, len,
81 val, le32_to_cpu(*image));
82 return -EIO;
83 }
84 }
85
86 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
87
88 return 0;
89}
90
91/**
92 * iwl4965_load_bsm - Load bootstrap instructions
93 *
94 * BSM operation:
95 *
96 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
97 * in special SRAM that does not power down during RFKILL. When powering back
98 * up after power-saving sleeps (or during initial uCode load), the BSM loads
99 * the bootstrap program into the on-board processor, and starts it.
100 *
101 * The bootstrap program loads (via DMA) instructions and data for a new
102 * program from host DRAM locations indicated by the host driver in the
103 * BSM_DRAM_* registers. Once the new program is loaded, it starts
104 * automatically.
105 *
106 * When initializing the NIC, the host driver points the BSM to the
107 * "initialize" uCode image. This uCode sets up some internal data, then
108 * notifies host via "initialize alive" that it is complete.
109 *
110 * The host then replaces the BSM_DRAM_* pointer values to point to the
111 * normal runtime uCode instructions and a backup uCode data cache buffer
112 * (filled initially with starting data values for the on-board processor),
113 * then triggers the "initialize" uCode to load and launch the runtime uCode,
114 * which begins normal operation.
115 *
116 * When doing a power-save shutdown, runtime uCode saves data SRAM into
117 * the backup data cache in DRAM before SRAM is powered down.
118 *
119 * When powering back up, the BSM loads the bootstrap program. This reloads
120 * the runtime uCode instructions and the backup data cache into SRAM,
121 * and re-launches the runtime uCode from where it left off.
122 */
123static int iwl4965_load_bsm(struct iwl_priv *priv)
124{
125 __le32 *image = priv->ucode_boot.v_addr;
126 u32 len = priv->ucode_boot.len;
127 dma_addr_t pinst;
128 dma_addr_t pdata;
129 u32 inst_len;
130 u32 data_len;
131 int i;
132 u32 done;
133 u32 reg_offset;
134 int ret;
135
136 IWL_DEBUG_INFO("Begin load bsm\n");
137
fe9b6b72
RR		 138 priv->ucode_type = UCODE_RT;
139
57aab75a
TW		 140 /* make sure bootstrap program is no larger than BSM's SRAM size */
141 if (len > IWL_MAX_BSM_SIZE)
142 return -EINVAL;
143
144 /* Tell bootstrap uCode where to find the "Initialize" uCode
145 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
2d87889f 146 * NOTE: iwl_init_alive_start() will replace these values,
57aab75a 147 * after the "initialize" uCode has run, to point to
2d87889f
TW		 148 * runtime/protocol instructions and backup data cache.
149 */
57aab75a
TW		 150 pinst = priv->ucode_init.p_addr >> 4;
151 pdata = priv->ucode_init_data.p_addr >> 4;
152 inst_len = priv->ucode_init.len;
153 data_len = priv->ucode_init_data.len;
154
155 ret = iwl_grab_nic_access(priv);
156 if (ret)
157 return ret;
158
159 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
160 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
161 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
162 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
163
164 /* Fill BSM memory with bootstrap instructions */
165 for (reg_offset = BSM_SRAM_LOWER_BOUND;
166 reg_offset < BSM_SRAM_LOWER_BOUND + len;
167 reg_offset += sizeof(u32), image++)
168 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
169
170 ret = iwl4965_verify_bsm(priv);
171 if (ret) {
172 iwl_release_nic_access(priv);
173 return ret;
174 }
175
176 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
177 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
178 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
179 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
180
181 /* Load bootstrap code into instruction SRAM now,
182 * to prepare to load "initialize" uCode */
183 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
184
185 /* Wait for load of bootstrap uCode to finish */
186 for (i = 0; i < 100; i++) {
187 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
188 if (!(done & BSM_WR_CTRL_REG_BIT_START))
189 break;
190 udelay(10);
191 }
192 if (i < 100)
193 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
194 else {
195 IWL_ERROR("BSM write did not complete!\n");
196 return -EIO;
197 }
198
199 /* Enable future boot loads whenever power management unit triggers it
200 * (e.g. when powering back up after power-save shutdown) */
201 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
202
203 iwl_release_nic_access(priv);
204
205 return 0;
206}
207
f3ccc08c
EG		 208/**
209 * iwl4965_set_ucode_ptrs - Set uCode address location
210 *
211 * Tell initialization uCode where to find runtime uCode.
212 *
213 * BSM registers initially contain pointers to initialization uCode.
214 * We need to replace them to load runtime uCode inst and data,
215 * and to save runtime data when powering down.
216 */
217static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
218{
219 dma_addr_t pinst;
220 dma_addr_t pdata;
221 unsigned long flags;
222 int ret = 0;
223
224 /* bits 35:4 for 4965 */
225 pinst = priv->ucode_code.p_addr >> 4;
226 pdata = priv->ucode_data_backup.p_addr >> 4;
227
228 spin_lock_irqsave(&priv->lock, flags);
229 ret = iwl_grab_nic_access(priv);
230 if (ret) {
231 spin_unlock_irqrestore(&priv->lock, flags);
232 return ret;
233 }
234
235 /* Tell bootstrap uCode where to find image to load */
236 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
237 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
238 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
239 priv->ucode_data.len);
240
241 /* Inst bytecount must be last to set up, bit 31 signals uCode
242 * that all new ptr/size info is in place */
243 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
244 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
245 iwl_release_nic_access(priv);
246
247 spin_unlock_irqrestore(&priv->lock, flags);
248
249 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
250
251 return ret;
252}
253
254/**
255 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
256 *
257 * Called after REPLY_ALIVE notification received from "initialize" uCode.
258 *
259 * The 4965 "initialize" ALIVE reply contains calibration data for:
260 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
261 * (3945 does not contain this data).
262 *
263 * Tell "initialize" uCode to go ahead and load the runtime uCode.
264*/
265static void iwl4965_init_alive_start(struct iwl_priv *priv)
266{
267 /* Check alive response for "valid" sign from uCode */
268 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
269 /* We had an error bringing up the hardware, so take it
270 * all the way back down so we can try again */
271 IWL_DEBUG_INFO("Initialize Alive failed.\n");
272 goto restart;
273 }
274
275 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
276 * This is a paranoid check, because we would not have gotten the
277 * "initialize" alive if code weren't properly loaded. */
278 if (iwl_verify_ucode(priv)) {
279 /* Runtime instruction load was bad;
280 * take it all the way back down so we can try again */
281 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
282 goto restart;
283 }
284
285 /* Calculate temperature */
286 priv->temperature = iwl4965_get_temperature(priv);
287
288 /* Send pointers to protocol/runtime uCode image ... init code will
289 * load and launch runtime uCode, which will send us another "Alive"
290 * notification. */
291 IWL_DEBUG_INFO("Initialization Alive received.\n");
292 if (iwl4965_set_ucode_ptrs(priv)) {
293 /* Runtime instruction load won't happen;
294 * take it all the way back down so we can try again */
295 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
296 goto restart;
297 }
298 return;
299
300restart:
301 queue_work(priv->workqueue, &priv->restart);
302}
303
b481de9c
ZY		 304static int is_fat_channel(__le32 rxon_flags)
305{
306 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
307 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
308}
309
8614f360
TW		 310/*
311 * EEPROM handlers
312 */
313
314static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
315{
316 u16 eeprom_ver;
317 u16 calib_ver;
318
319 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
320
321 calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
322
323 if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
324 calib_ver < EEPROM_4965_TX_POWER_VERSION)
325 goto err;
326
327 return 0;
328err:
329 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
330 eeprom_ver, EEPROM_4965_EEPROM_VERSION,
331 calib_ver, EEPROM_4965_TX_POWER_VERSION);
332 return -EINVAL;
333
334}
079a2533 335int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 336{
d8609652 337 int ret;
b481de9c
ZY		 338 unsigned long flags;
339
340 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 341 ret = iwl_grab_nic_access(priv);
d8609652 342 if (ret) {
b481de9c 343 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 344 return ret;
b481de9c
ZY		 345 }
346
6f4083aa 347 if (src == IWL_PWR_SRC_VAUX) {
b481de9c 348 u32 val;
d8609652 349 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
6f4083aa 350 &val);
b481de9c 351
6f4083aa 352 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
3395f6e9 353 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 354 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
355 ~APMG_PS_CTRL_MSK_PWR_SRC);
356 }
357 } else {
3395f6e9 358 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 359 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
360 ~APMG_PS_CTRL_MSK_PWR_SRC);
361 }
b481de9c 362
3395f6e9 363 iwl_release_nic_access(priv);
b481de9c
ZY		 364 spin_unlock_irqrestore(&priv->lock, flags);
365
d8609652 366 return ret;
b481de9c
ZY		 367}
368
da1bc453
TW		 369/*
370 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
371 * must be called under priv->lock and mac access
372 */
373static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
b481de9c 374{
da1bc453 375 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
b481de9c
ZY		 376}
377
91238714 378static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 379{
91238714 380 int ret = 0;
b481de9c 381
3395f6e9 382 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 383 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 384
8f061891
TW		 385 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
386 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
387 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
388
91238714
TW		 389 /* set "initialization complete" bit to move adapter
390 * D0U* --> D0A* state */
3395f6e9 391 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 392
91238714
TW		 393 /* wait for clock stabilization */
394 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
395 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
396 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
397 if (ret < 0) {
398 IWL_DEBUG_INFO("Failed to init the card\n");
399 goto out;
b481de9c
ZY		 400 }
401
91238714
TW		 402 ret = iwl_grab_nic_access(priv);
403 if (ret)
404 goto out;
b481de9c 405
91238714 406 /* enable DMA */
8f061891
TW		 407 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
408 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 409
410 udelay(20);
411
8f061891 412 /* disable L1-Active */
3395f6e9 413 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 414 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 415
3395f6e9 416 iwl_release_nic_access(priv);
91238714 417out:
91238714
TW		 418 return ret;
419}
420
694cc56d
TW		 421
422static void iwl4965_nic_config(struct iwl_priv *priv)
91238714
TW		 423{
424 unsigned long flags;
91238714 425 u32 val;
694cc56d
TW		 426 u16 radio_cfg;
427 u8 val_link;
6f4083aa 428
b481de9c
ZY		 429 spin_lock_irqsave(&priv->lock, flags);
430
b661c819 431 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
b481de9c
ZY		 432 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
433 /* Enable No Snoop field */
434 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
435 val & ~(1 << 11));
436 }
437
b481de9c
ZY		 438 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
439
8f061891
TW		 440 /* L1 is enabled by BIOS */
441 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
442 /* diable L0S disabled L1A enabled */
443 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
444 else
445 /* L0S enabled L1A disabled */
446 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
b481de9c 447
694cc56d 448 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
b481de9c 449
694cc56d
TW		 450 /* write radio config values to register */
451 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
452 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
453 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
454 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
455 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
b481de9c 456
694cc56d 457 /* set CSR_HW_CONFIG_REG for uCode use */
3395f6e9 458 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
a395b920
TW		 459 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
460 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 461
694cc56d
TW		 462 priv->calib_info = (struct iwl_eeprom_calib_info *)
463 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
464
465 spin_unlock_irqrestore(&priv->lock, flags);
466}
467
46315e01
TW		 468static int iwl4965_apm_stop_master(struct iwl_priv *priv)
469{
470 int ret = 0;
471 unsigned long flags;
472
473 spin_lock_irqsave(&priv->lock, flags);
474
475 /* set stop master bit */
476 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
477
478 ret = iwl_poll_bit(priv, CSR_RESET,
479 CSR_RESET_REG_FLAG_MASTER_DISABLED,
480 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
481 if (ret < 0)
482 goto out;
483
484out:
485 spin_unlock_irqrestore(&priv->lock, flags);
486 IWL_DEBUG_INFO("stop master\n");
487
488 return ret;
489}
490
f118a91d
TW		 491static void iwl4965_apm_stop(struct iwl_priv *priv)
492{
493 unsigned long flags;
494
46315e01 495 iwl4965_apm_stop_master(priv);
f118a91d
TW		 496
497 spin_lock_irqsave(&priv->lock, flags);
498
499 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
500
501 udelay(10);
502
503 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
504 spin_unlock_irqrestore(&priv->lock, flags);
505}
506
7f066108 507static int iwl4965_apm_reset(struct iwl_priv *priv)
b481de9c 508{
7f066108 509 int ret = 0;
b481de9c
ZY		 510 unsigned long flags;
511
46315e01 512 iwl4965_apm_stop_master(priv);
b481de9c
ZY		 513
514 spin_lock_irqsave(&priv->lock, flags);
515
3395f6e9 516 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 517
518 udelay(10);
519
7f066108
TW		 520 /* FIXME: put here L1A -L0S w/a */
521
3395f6e9 522 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d 523
7f066108 524 ret = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 525 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
526 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
527
7f066108
TW		 528 if (ret)
529 goto out;
530
b481de9c
ZY		 531 udelay(10);
532
7f066108
TW		 533 ret = iwl_grab_nic_access(priv);
534 if (ret)
535 goto out;
536 /* Enable DMA and BSM Clock */
537 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
538 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 539
7f066108 540 udelay(10);
b481de9c 541
7f066108
TW		 542 /* disable L1A */
543 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
544 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 545
7f066108 546 iwl_release_nic_access(priv);
b481de9c
ZY		 547
548 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
549 wake_up_interruptible(&priv->wait_command_queue);
550
7f066108 551out:
b481de9c
ZY		 552 spin_unlock_irqrestore(&priv->lock, flags);
553
7f066108 554 return ret;
b481de9c
ZY		 555}
556
557#define REG_RECALIB_PERIOD (60)
558
b481de9c
ZY		 559/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
560 * Called after every association, but this runs only once!
561 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 562static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 563{
f0832f13 564 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 565
3109ece1 566 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 567 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 568
569 memset(&cmd, 0, sizeof(cmd));
570 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
571 cmd.diff_gain_a = 0;
572 cmd.diff_gain_b = 0;
573 cmd.diff_gain_c = 0;
f0832f13
EG		 574 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
575 sizeof(cmd), &cmd))
576 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 577 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
578 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
579 }
b481de9c
ZY		 580}
581
f0832f13
EG		 582static void iwl4965_gain_computation(struct iwl_priv *priv,
583 u32 *average_noise,
584 u16 min_average_noise_antenna_i,
585 u32 min_average_noise)
b481de9c 586{
f0832f13
EG		 587 int i, ret;
588 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 589
f0832f13 590 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 591
f0832f13
EG		 592 for (i = 0; i < NUM_RX_CHAINS; i++) {
593 s32 delta_g = 0;
b481de9c 594
f0832f13
EG		 595 if (!(data->disconn_array[i]) &&
596 (data->delta_gain_code[i] ==
b481de9c 597 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 598 delta_g = average_noise[i] - min_average_noise;
599 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
600 data->delta_gain_code[i] =
601 min(data->delta_gain_code[i],
602 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
603
604 data->delta_gain_code[i] =
605 (data->delta_gain_code[i] | (1 << 2));
606 } else {
607 data->delta_gain_code[i] = 0;
b481de9c 608 }
b481de9c 609 }
f0832f13
EG		 610 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
611 data->delta_gain_code[0],
612 data->delta_gain_code[1],
613 data->delta_gain_code[2]);
b481de9c 614
f0832f13
EG		 615 /* Differential gain gets sent to uCode only once */
616 if (!data->radio_write) {
617 struct iwl4965_calibration_cmd cmd;
618 data->radio_write = 1;
b481de9c 619
f0832f13
EG		 620 memset(&cmd, 0, sizeof(cmd));
621 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
622 cmd.diff_gain_a = data->delta_gain_code[0];
623 cmd.diff_gain_b = data->delta_gain_code[1];
624 cmd.diff_gain_c = data->delta_gain_code[2];
625 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
626 sizeof(cmd), &cmd);
627 if (ret)
628 IWL_DEBUG_CALIB("fail sending cmd "
629 "REPLY_PHY_CALIBRATION_CMD \n");
630
631 /* TODO we might want recalculate
632 * rx_chain in rxon cmd */
633
634 /* Mark so we run this algo only once! */
635 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 636 }
f0832f13
EG		 637 data->chain_noise_a = 0;
638 data->chain_noise_b = 0;
639 data->chain_noise_c = 0;
640 data->chain_signal_a = 0;
641 data->chain_signal_b = 0;
642 data->chain_signal_c = 0;
643 data->beacon_count = 0;
b481de9c
ZY		 644}
645
b481de9c
ZY		 646static void iwl4965_bg_txpower_work(struct work_struct *work)
647{
c79dd5b5 648 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 649 txpower_work);
650
651 /* If a scan happened to start before we got here
652 * then just return; the statistics notification will
653 * kick off another scheduled work to compensate for
654 * any temperature delta we missed here. */
655 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
656 test_bit(STATUS_SCANNING, &priv->status))
657 return;
658
659 mutex_lock(&priv->mutex);
660
661 /* Regardless of if we are assocaited, we must reconfigure the
662 * TX power since frames can be sent on non-radar channels while
663 * not associated */
630fe9b6 664 iwl4965_send_tx_power(priv);
b481de9c
ZY		 665
666 /* Update last_temperature to keep is_calib_needed from running
667 * when it isn't needed... */
668 priv->last_temperature = priv->temperature;
669
670 mutex_unlock(&priv->mutex);
671}
672
673/*
674 * Acquire priv->lock before calling this function !
675 */
c79dd5b5 676static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 677{
3395f6e9 678 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 679 (index & 0xff) | (txq_id << 8));
12a81f60 680 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 681}
682
8b6eaea8
CB		 683/**
684 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
685 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
686 * @scd_retry: (1) Indicates queue will be used in aggregation mode
687 *
688 * NOTE: Acquire priv->lock before calling this function !
b481de9c 689 */
c79dd5b5 690static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
16466903 691 struct iwl_tx_queue *txq,
b481de9c
ZY		 692 int tx_fifo_id, int scd_retry)
693{
694 int txq_id = txq->q.id;
8b6eaea8
CB		 695
696 /* Find out whether to activate Tx queue */
b481de9c
ZY		 697 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
698
8b6eaea8 699 /* Set up and activate */
12a81f60 700 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 701 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
702 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
703 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
704 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
705 IWL49_SCD_QUEUE_STTS_REG_MSK);
b481de9c
ZY		 706
707 txq->sched_retry = scd_retry;
708
709 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 710 active ? "Activate" : "Deactivate",
b481de9c
ZY		 711 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
712}
713
714static const u16 default_queue_to_tx_fifo[] = {
715 IWL_TX_FIFO_AC3,
716 IWL_TX_FIFO_AC2,
717 IWL_TX_FIFO_AC1,
718 IWL_TX_FIFO_AC0,
038669e4 719 IWL49_CMD_FIFO_NUM,
b481de9c
ZY		 720 IWL_TX_FIFO_HCCA_1,
721 IWL_TX_FIFO_HCCA_2
722};
723
c79dd5b5 724int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 725{
726 u32 a;
727 int i = 0;
728 unsigned long flags;
857485c0 729 int ret;
b481de9c
ZY		 730
731 spin_lock_irqsave(&priv->lock, flags);
732
3395f6e9 733 ret = iwl_grab_nic_access(priv);
857485c0 734 if (ret) {
b481de9c 735 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 736 return ret;
b481de9c
ZY		 737 }
738
8b6eaea8 739 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 740 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
038669e4
EG		 741 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
742 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 743 iwl_write_targ_mem(priv, a, 0);
038669e4 744 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 745 iwl_write_targ_mem(priv, a, 0);
5425e490 746 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 747 iwl_write_targ_mem(priv, a, 0);
b481de9c 748
8b6eaea8 749 /* Tel 4965 where to find Tx byte count tables */
12a81f60 750 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 751 (priv->shared_phys +
bb8c093b 752 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 753
754 /* Disable chain mode for all queues */
12a81f60 755 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 756
8b6eaea8 757 /* Initialize each Tx queue (including the command queue) */
5425e490 758 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 759
760 /* TFD circular buffer read/write indexes */
12a81f60 761 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 762 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 763
764 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 765 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 766 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
767 (SCD_WIN_SIZE <<
768 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
769 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 770
771 /* Frame limit */
3395f6e9 772 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 773 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
774 sizeof(u32),
775 (SCD_FRAME_LIMIT <<
776 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
777 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c
ZY		 778
779 }
12a81f60 780 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 781 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 782
8b6eaea8 783 /* Activate all Tx DMA/FIFO channels */
da1bc453 784 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
b481de9c
ZY		 785
786 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 787
788 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 789 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
790 int ac = default_queue_to_tx_fifo[i];
36470749 791 iwl_txq_ctx_activate(priv, i);
b481de9c
ZY		 792 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
793 }
794
3395f6e9 795 iwl_release_nic_access(priv);
b481de9c
ZY		 796 spin_unlock_irqrestore(&priv->lock, flags);
797
857485c0 798 return ret;
b481de9c
ZY		 799}
800
f0832f13
EG		 801static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
802 .min_nrg_cck = 97,
803 .max_nrg_cck = 0,
804
805 .auto_corr_min_ofdm = 85,
806 .auto_corr_min_ofdm_mrc = 170,
807 .auto_corr_min_ofdm_x1 = 105,
808 .auto_corr_min_ofdm_mrc_x1 = 220,
809
810 .auto_corr_max_ofdm = 120,
811 .auto_corr_max_ofdm_mrc = 210,
812 .auto_corr_max_ofdm_x1 = 140,
813 .auto_corr_max_ofdm_mrc_x1 = 270,
814
815 .auto_corr_min_cck = 125,
816 .auto_corr_max_cck = 200,
817 .auto_corr_min_cck_mrc = 200,
818 .auto_corr_max_cck_mrc = 400,
819
820 .nrg_th_cck = 100,
821 .nrg_th_ofdm = 100,
822};
f0832f13 823
8b6eaea8 824/**
5425e490 825 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 826 *
827 * Called when initializing driver
828 */
5425e490 829int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 830{
316c30d9 831
038669e4 832 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1ea87396 833 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 834 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
038669e4 835 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
059ff826 836 return -EINVAL;
316c30d9 837 }
b481de9c 838
5425e490 839 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
7f3e4bb6 840 priv->hw_params.first_ampdu_q = IWL49_FIRST_AMPDU_QUEUE;
099b40b7 841 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
5425e490
TW		 842 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
843 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 844 if (priv->cfg->mod_params->amsdu_size_8K)
5425e490 845 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
9ee1ba47 846 else
5425e490
TW		 847 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
848 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
849 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
850 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822 851
099b40b7
RR		 852 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
853 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
854 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
855 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
856
ec35cf2a
TW		 857 priv->hw_params.tx_chains_num = 2;
858 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 859 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
860 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 861 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
862
f0832f13 863 priv->hw_params.sens = &iwl4965_sensitivity;
3e82a822 864
059ff826 865 return 0;
b481de9c
ZY		 866}
867
5da4b55f
MA		 868/* set card power command */
869static int iwl4965_set_power(struct iwl_priv *priv,
870 void *cmd)
871{
872 int ret = 0;
873
874 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
875 sizeof(struct iwl4965_powertable_cmd),
876 cmd, NULL);
877 return ret;
878}
b481de9c
ZY		 879
880static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
881{
882 s32 sign = 1;
883
884 if (num < 0) {
885 sign = -sign;
886 num = -num;
887 }
888 if (denom < 0) {
889 sign = -sign;
890 denom = -denom;
891 }
892 *res = 1;
893 *res = ((num * 2 + denom) / (denom * 2)) * sign;
894
895 return 1;
896}
897
8b6eaea8
CB		 898/**
899 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
900 *
901 * Determines power supply voltage compensation for txpower calculations.
902 * Returns number of 1/2-dB steps to subtract from gain table index,
903 * to compensate for difference between power supply voltage during
904 * factory measurements, vs. current power supply voltage.
905 *
906 * Voltage indication is higher for lower voltage.
907 * Lower voltage requires more gain (lower gain table index).
908 */
b481de9c
ZY		 909static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
910 s32 current_voltage)
911{
912 s32 comp = 0;
913
914 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
915 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
916 return 0;
917
918 iwl4965_math_div_round(current_voltage - eeprom_voltage,
919 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
920
921 if (current_voltage > eeprom_voltage)
922 comp *= 2;
923 if ((comp < -2) || (comp > 2))
924 comp = 0;
925
926 return comp;
927}
928
b481de9c
ZY		 929static s32 iwl4965_get_tx_atten_grp(u16 channel)
930{
931 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
932 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
933 return CALIB_CH_GROUP_5;
934
935 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
936 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
937 return CALIB_CH_GROUP_1;
938
939 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
940 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
941 return CALIB_CH_GROUP_2;
942
943 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
944 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
945 return CALIB_CH_GROUP_3;
946
947 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
948 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
949 return CALIB_CH_GROUP_4;
950
951 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
952 return -1;
953}
954
c79dd5b5 955static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 956{
957 s32 b = -1;
958
959 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 960 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 961 continue;
962
073d3f5f
TW		 963 if ((channel >= priv->calib_info->band_info[b].ch_from)
964 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 965 break;
966 }
967
968 return b;
969}
970
971static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
972{
973 s32 val;
974
975 if (x2 == x1)
976 return y1;
977 else {
978 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
979 return val + y2;
980 }
981}
982
8b6eaea8
CB		 983/**
984 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
985 *
986 * Interpolates factory measurements from the two sample channels within a
987 * sub-band, to apply to channel of interest. Interpolation is proportional to
988 * differences in channel frequencies, which is proportional to differences
989 * in channel number.
990 */
c79dd5b5 991static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 992 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 993{
994 s32 s = -1;
995 u32 c;
996 u32 m;
073d3f5f
TW		 997 const struct iwl_eeprom_calib_measure *m1;
998 const struct iwl_eeprom_calib_measure *m2;
999 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 1000 u32 ch_i1;
1001 u32 ch_i2;
1002
1003 s = iwl4965_get_sub_band(priv, channel);
1004 if (s >= EEPROM_TX_POWER_BANDS) {
1005 IWL_ERROR("Tx Power can not find channel %d ", channel);
1006 return -1;
1007 }
1008
073d3f5f
TW		 1009 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1010 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 1011 chan_info->ch_num = (u8) channel;
1012
1013 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1014 channel, s, ch_i1, ch_i2);
1015
1016 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1017 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 1018 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 1019 measurements[c][m]);
073d3f5f 1020 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 1021 measurements[c][m]);
1022 omeas = &(chan_info->measurements[c][m]);
1023
1024 omeas->actual_pow =
1025 (u8) iwl4965_interpolate_value(channel, ch_i1,
1026 m1->actual_pow,
1027 ch_i2,
1028 m2->actual_pow);
1029 omeas->gain_idx =
1030 (u8) iwl4965_interpolate_value(channel, ch_i1,
1031 m1->gain_idx, ch_i2,
1032 m2->gain_idx);
1033 omeas->temperature =
1034 (u8) iwl4965_interpolate_value(channel, ch_i1,
1035 m1->temperature,
1036 ch_i2,
1037 m2->temperature);
1038 omeas->pa_det =
1039 (s8) iwl4965_interpolate_value(channel, ch_i1,
1040 m1->pa_det, ch_i2,
1041 m2->pa_det);
1042
1043 IWL_DEBUG_TXPOWER
1044 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1045 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1046 IWL_DEBUG_TXPOWER
1047 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1048 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1049 IWL_DEBUG_TXPOWER
1050 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1051 m1->pa_det, m2->pa_det, omeas->pa_det);
1052 IWL_DEBUG_TXPOWER
1053 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1054 m1->temperature, m2->temperature,
1055 omeas->temperature);
1056 }
1057 }
1058
1059 return 0;
1060}
1061
1062/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1063 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1064static s32 back_off_table[] = {
1065 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1066 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1067 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1068 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1069 10 /* CCK */
1070};
1071
1072/* Thermal compensation values for txpower for various frequency ranges ...
1073 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1074static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1075 s32 degrees_per_05db_a;
1076 s32 degrees_per_05db_a_denom;
1077} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1078 {9, 2}, /* group 0 5.2, ch 34-43 */
1079 {4, 1}, /* group 1 5.2, ch 44-70 */
1080 {4, 1}, /* group 2 5.2, ch 71-124 */
1081 {4, 1}, /* group 3 5.2, ch 125-200 */
1082 {3, 1} /* group 4 2.4, ch all */
1083};
1084
1085static s32 get_min_power_index(s32 rate_power_index, u32 band)
1086{
1087 if (!band) {
1088 if ((rate_power_index & 7) <= 4)
1089 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1090 }
1091 return MIN_TX_GAIN_INDEX;
1092}
1093
1094struct gain_entry {
1095 u8 dsp;
1096 u8 radio;
1097};
1098
1099static const struct gain_entry gain_table[2][108] = {
1100 /* 5.2GHz power gain index table */
1101 {
1102 {123, 0x3F}, /* highest txpower */
1103 {117, 0x3F},
1104 {110, 0x3F},
1105 {104, 0x3F},
1106 {98, 0x3F},
1107 {110, 0x3E},
1108 {104, 0x3E},
1109 {98, 0x3E},
1110 {110, 0x3D},
1111 {104, 0x3D},
1112 {98, 0x3D},
1113 {110, 0x3C},
1114 {104, 0x3C},
1115 {98, 0x3C},
1116 {110, 0x3B},
1117 {104, 0x3B},
1118 {98, 0x3B},
1119 {110, 0x3A},
1120 {104, 0x3A},
1121 {98, 0x3A},
1122 {110, 0x39},
1123 {104, 0x39},
1124 {98, 0x39},
1125 {110, 0x38},
1126 {104, 0x38},
1127 {98, 0x38},
1128 {110, 0x37},
1129 {104, 0x37},
1130 {98, 0x37},
1131 {110, 0x36},
1132 {104, 0x36},
1133 {98, 0x36},
1134 {110, 0x35},
1135 {104, 0x35},
1136 {98, 0x35},
1137 {110, 0x34},
1138 {104, 0x34},
1139 {98, 0x34},
1140 {110, 0x33},
1141 {104, 0x33},
1142 {98, 0x33},
1143 {110, 0x32},
1144 {104, 0x32},
1145 {98, 0x32},
1146 {110, 0x31},
1147 {104, 0x31},
1148 {98, 0x31},
1149 {110, 0x30},
1150 {104, 0x30},
1151 {98, 0x30},
1152 {110, 0x25},
1153 {104, 0x25},
1154 {98, 0x25},
1155 {110, 0x24},
1156 {104, 0x24},
1157 {98, 0x24},
1158 {110, 0x23},
1159 {104, 0x23},
1160 {98, 0x23},
1161 {110, 0x22},
1162 {104, 0x18},
1163 {98, 0x18},
1164 {110, 0x17},
1165 {104, 0x17},
1166 {98, 0x17},
1167 {110, 0x16},
1168 {104, 0x16},
1169 {98, 0x16},
1170 {110, 0x15},
1171 {104, 0x15},
1172 {98, 0x15},
1173 {110, 0x14},
1174 {104, 0x14},
1175 {98, 0x14},
1176 {110, 0x13},
1177 {104, 0x13},
1178 {98, 0x13},
1179 {110, 0x12},
1180 {104, 0x08},
1181 {98, 0x08},
1182 {110, 0x07},
1183 {104, 0x07},
1184 {98, 0x07},
1185 {110, 0x06},
1186 {104, 0x06},
1187 {98, 0x06},
1188 {110, 0x05},
1189 {104, 0x05},
1190 {98, 0x05},
1191 {110, 0x04},
1192 {104, 0x04},
1193 {98, 0x04},
1194 {110, 0x03},
1195 {104, 0x03},
1196 {98, 0x03},
1197 {110, 0x02},
1198 {104, 0x02},
1199 {98, 0x02},
1200 {110, 0x01},
1201 {104, 0x01},
1202 {98, 0x01},
1203 {110, 0x00},
1204 {104, 0x00},
1205 {98, 0x00},
1206 {93, 0x00},
1207 {88, 0x00},
1208 {83, 0x00},
1209 {78, 0x00},
1210 },
1211 /* 2.4GHz power gain index table */
1212 {
1213 {110, 0x3f}, /* highest txpower */
1214 {104, 0x3f},
1215 {98, 0x3f},
1216 {110, 0x3e},
1217 {104, 0x3e},
1218 {98, 0x3e},
1219 {110, 0x3d},
1220 {104, 0x3d},
1221 {98, 0x3d},
1222 {110, 0x3c},
1223 {104, 0x3c},
1224 {98, 0x3c},
1225 {110, 0x3b},
1226 {104, 0x3b},
1227 {98, 0x3b},
1228 {110, 0x3a},
1229 {104, 0x3a},
1230 {98, 0x3a},
1231 {110, 0x39},
1232 {104, 0x39},
1233 {98, 0x39},
1234 {110, 0x38},
1235 {104, 0x38},
1236 {98, 0x38},
1237 {110, 0x37},
1238 {104, 0x37},
1239 {98, 0x37},
1240 {110, 0x36},
1241 {104, 0x36},
1242 {98, 0x36},
1243 {110, 0x35},
1244 {104, 0x35},
1245 {98, 0x35},
1246 {110, 0x34},
1247 {104, 0x34},
1248 {98, 0x34},
1249 {110, 0x33},
1250 {104, 0x33},
1251 {98, 0x33},
1252 {110, 0x32},
1253 {104, 0x32},
1254 {98, 0x32},
1255 {110, 0x31},
1256 {104, 0x31},
1257 {98, 0x31},
1258 {110, 0x30},
1259 {104, 0x30},
1260 {98, 0x30},
1261 {110, 0x6},
1262 {104, 0x6},
1263 {98, 0x6},
1264 {110, 0x5},
1265 {104, 0x5},
1266 {98, 0x5},
1267 {110, 0x4},
1268 {104, 0x4},
1269 {98, 0x4},
1270 {110, 0x3},
1271 {104, 0x3},
1272 {98, 0x3},
1273 {110, 0x2},
1274 {104, 0x2},
1275 {98, 0x2},
1276 {110, 0x1},
1277 {104, 0x1},
1278 {98, 0x1},
1279 {110, 0x0},
1280 {104, 0x0},
1281 {98, 0x0},
1282 {97, 0},
1283 {96, 0},
1284 {95, 0},
1285 {94, 0},
1286 {93, 0},
1287 {92, 0},
1288 {91, 0},
1289 {90, 0},
1290 {89, 0},
1291 {88, 0},
1292 {87, 0},
1293 {86, 0},
1294 {85, 0},
1295 {84, 0},
1296 {83, 0},
1297 {82, 0},
1298 {81, 0},
1299 {80, 0},
1300 {79, 0},
1301 {78, 0},
1302 {77, 0},
1303 {76, 0},
1304 {75, 0},
1305 {74, 0},
1306 {73, 0},
1307 {72, 0},
1308 {71, 0},
1309 {70, 0},
1310 {69, 0},
1311 {68, 0},
1312 {67, 0},
1313 {66, 0},
1314 {65, 0},
1315 {64, 0},
1316 {63, 0},
1317 {62, 0},
1318 {61, 0},
1319 {60, 0},
1320 {59, 0},
1321 }
1322};
1323
c79dd5b5 1324static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1325 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1326 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1327{
1328 u8 saturation_power;
1329 s32 target_power;
1330 s32 user_target_power;
1331 s32 power_limit;
1332 s32 current_temp;
1333 s32 reg_limit;
1334 s32 current_regulatory;
1335 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1336 int i;
1337 int c;
bf85ea4f 1338 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1339 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1340 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1341 s16 voltage;
1342 s32 init_voltage;
1343 s32 voltage_compensation;
1344 s32 degrees_per_05db_num;
1345 s32 degrees_per_05db_denom;
1346 s32 factory_temp;
1347 s32 temperature_comp[2];
1348 s32 factory_gain_index[2];
1349 s32 factory_actual_pwr[2];
1350 s32 power_index;
1351
b481de9c
ZY		 1352 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1353 * are used for indexing into txpower table) */
630fe9b6 1354 user_target_power = 2 * priv->tx_power_user_lmt;
b481de9c
ZY		 1355
1356 /* Get current (RXON) channel, band, width */
b481de9c
ZY		 1357 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1358 is_fat);
1359
630fe9b6
TW		 1360 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1361
1362 if (!is_channel_valid(ch_info))
b481de9c
ZY		 1363 return -EINVAL;
1364
1365 /* get txatten group, used to select 1) thermal txpower adjustment
1366 * and 2) mimo txpower balance between Tx chains. */
1367 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1368 if (txatten_grp < 0)
1369 return -EINVAL;
1370
1371 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1372 channel, txatten_grp);
1373
1374 if (is_fat) {
1375 if (ctrl_chan_high)
1376 channel -= 2;
1377 else
1378 channel += 2;
1379 }
1380
1381 /* hardware txpower limits ...
1382 * saturation (clipping distortion) txpowers are in half-dBm */
1383 if (band)
073d3f5f 1384 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1385 else
073d3f5f 1386 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1387
1388 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1389 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1390 if (band)
1391 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1392 else
1393 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1394 }
1395
1396 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1397 * max_power_avg values are in dBm, convert * 2 */
1398 if (is_fat)
1399 reg_limit = ch_info->fat_max_power_avg * 2;
1400 else
1401 reg_limit = ch_info->max_power_avg * 2;
1402
1403 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1404 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1405 if (band)
1406 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1407 else
1408 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1409 }
1410
1411 /* Interpolate txpower calibration values for this channel,
1412 * based on factory calibration tests on spaced channels. */
1413 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1414
1415 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 1416 voltage = priv->calib_info->voltage;
b481de9c
ZY		 1417 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1418 voltage_compensation =
1419 iwl4965_get_voltage_compensation(voltage, init_voltage);
1420
1421 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1422 init_voltage,
1423 voltage, voltage_compensation);
1424
1425 /* get current temperature (Celsius) */
1426 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1427 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1428 current_temp = KELVIN_TO_CELSIUS(current_temp);
1429
1430 /* select thermal txpower adjustment params, based on channel group
1431 * (same frequency group used for mimo txatten adjustment) */
1432 degrees_per_05db_num =
1433 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1434 degrees_per_05db_denom =
1435 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1436
1437 /* get per-chain txpower values from factory measurements */
1438 for (c = 0; c < 2; c++) {
1439 measurement = &ch_eeprom_info.measurements[c][1];
1440
1441 /* txgain adjustment (in half-dB steps) based on difference
1442 * between factory and current temperature */
1443 factory_temp = measurement->temperature;
1444 iwl4965_math_div_round((current_temp - factory_temp) *
1445 degrees_per_05db_denom,
1446 degrees_per_05db_num,
1447 &temperature_comp[c]);
1448
1449 factory_gain_index[c] = measurement->gain_idx;
1450 factory_actual_pwr[c] = measurement->actual_pow;
1451
1452 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1453 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1454 "curr tmp %d, comp %d steps\n",
1455 factory_temp, current_temp,
1456 temperature_comp[c]);
1457
1458 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1459 factory_gain_index[c],
1460 factory_actual_pwr[c]);
1461 }
1462
1463 /* for each of 33 bit-rates (including 1 for CCK) */
1464 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1465 u8 is_mimo_rate;
bb8c093b 1466 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 1467
1468 /* for mimo, reduce each chain's txpower by half
1469 * (3dB, 6 steps), so total output power is regulatory
1470 * compliant. */
1471 if (i & 0x8) {
1472 current_regulatory = reg_limit -
1473 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1474 is_mimo_rate = 1;
1475 } else {
1476 current_regulatory = reg_limit;
1477 is_mimo_rate = 0;
1478 }
1479
1480 /* find txpower limit, either hardware or regulatory */
1481 power_limit = saturation_power - back_off_table[i];
1482 if (power_limit > current_regulatory)
1483 power_limit = current_regulatory;
1484
1485 /* reduce user's txpower request if necessary
1486 * for this rate on this channel */
1487 target_power = user_target_power;
1488 if (target_power > power_limit)
1489 target_power = power_limit;
1490
1491 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1492 i, saturation_power - back_off_table[i],
1493 current_regulatory, user_target_power,
1494 target_power);
1495
1496 /* for each of 2 Tx chains (radio transmitters) */
1497 for (c = 0; c < 2; c++) {
1498 s32 atten_value;
1499
1500 if (is_mimo_rate)
1501 atten_value =
1502 (s32)le32_to_cpu(priv->card_alive_init.
1503 tx_atten[txatten_grp][c]);
1504 else
1505 atten_value = 0;
1506
1507 /* calculate index; higher index means lower txpower */
1508 power_index = (u8) (factory_gain_index[c] -
1509 (target_power -
1510 factory_actual_pwr[c]) -
1511 temperature_comp[c] -
1512 voltage_compensation +
1513 atten_value);
1514
1515/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1516 power_index); */
1517
1518 if (power_index < get_min_power_index(i, band))
1519 power_index = get_min_power_index(i, band);
1520
1521 /* adjust 5 GHz index to support negative indexes */
1522 if (!band)
1523 power_index += 9;
1524
1525 /* CCK, rate 32, reduce txpower for CCK */
1526 if (i == POWER_TABLE_CCK_ENTRY)
1527 power_index +=
1528 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1529
1530 /* stay within the table! */
1531 if (power_index > 107) {
1532 IWL_WARNING("txpower index %d > 107\n",
1533 power_index);
1534 power_index = 107;
1535 }
1536 if (power_index < 0) {
1537 IWL_WARNING("txpower index %d < 0\n",
1538 power_index);
1539 power_index = 0;
1540 }
1541
1542 /* fill txpower command for this rate/chain */
1543 tx_power.s.radio_tx_gain[c] =
1544 gain_table[band][power_index].radio;
1545 tx_power.s.dsp_predis_atten[c] =
1546 gain_table[band][power_index].dsp;
1547
1548 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1549 "gain 0x%02x dsp %d\n",
1550 c, atten_value, power_index,
1551 tx_power.s.radio_tx_gain[c],
1552 tx_power.s.dsp_predis_atten[c]);
1553 }/* for each chain */
1554
1555 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1556
1557 }/* for each rate */
1558
1559 return 0;
1560}
1561
1562/**
630fe9b6 1563 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
b481de9c
ZY		 1564 *
1565 * Uses the active RXON for channel, band, and characteristics (fat, high)
630fe9b6 1566 * The power limit is taken from priv->tx_power_user_lmt.
b481de9c 1567 */
630fe9b6 1568static int iwl4965_send_tx_power(struct iwl_priv *priv)
b481de9c 1569{
bb8c093b 1570 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 1571 int ret;
b481de9c
ZY		 1572 u8 band = 0;
1573 u8 is_fat = 0;
1574 u8 ctrl_chan_high = 0;
1575
1576 if (test_bit(STATUS_SCANNING, &priv->status)) {
1577 /* If this gets hit a lot, switch it to a BUG() and catch
1578 * the stack trace to find out who is calling this during
1579 * a scan. */
1580 IWL_WARNING("TX Power requested while scanning!\n");
1581 return -EAGAIN;
1582 }
1583
8318d78a 1584 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 1585
1586 is_fat = is_fat_channel(priv->active_rxon.flags);
1587
1588 if (is_fat &&
1589 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1590 ctrl_chan_high = 1;
1591
1592 cmd.band = band;
1593 cmd.channel = priv->active_rxon.channel;
1594
857485c0 1595 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 1596 le16_to_cpu(priv->active_rxon.channel),
1597 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 1598 if (ret)
1599 goto out;
b481de9c 1600
857485c0
TW		 1601 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1602
1603out:
1604 return ret;
b481de9c
ZY		 1605}
1606
7e8c519e
TW		 1607static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1608{
1609 int ret = 0;
1610 struct iwl4965_rxon_assoc_cmd rxon_assoc;
c1adf9fb
GG		 1611 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1612 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
7e8c519e
TW		 1613
1614 if ((rxon1->flags == rxon2->flags) &&
1615 (rxon1->filter_flags == rxon2->filter_flags) &&
1616 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1617 (rxon1->ofdm_ht_single_stream_basic_rates ==
1618 rxon2->ofdm_ht_single_stream_basic_rates) &&
1619 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1620 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1621 (rxon1->rx_chain == rxon2->rx_chain) &&
1622 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1623 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1624 return 0;
1625 }
1626
1627 rxon_assoc.flags = priv->staging_rxon.flags;
1628 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1629 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1630 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1631 rxon_assoc.reserved = 0;
1632 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1633 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1634 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1635 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1636 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1637
1638 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1639 sizeof(rxon_assoc), &rxon_assoc, NULL);
1640 if (ret)
1641 return ret;
1642
1643 return ret;
1644}
1645
1646
c79dd5b5 1647int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1648{
1649 int rc;
1650 u8 band = 0;
1651 u8 is_fat = 0;
1652 u8 ctrl_chan_high = 0;
bb8c093b 1653 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 1654 const struct iwl_channel_info *ch_info;
b481de9c 1655
8318d78a 1656 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 1657
8622e705 1658 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 1659
1660 is_fat = is_fat_channel(priv->staging_rxon.flags);
1661
1662 if (is_fat &&
1663 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1664 ctrl_chan_high = 1;
1665
1666 cmd.band = band;
1667 cmd.expect_beacon = 0;
1668 cmd.channel = cpu_to_le16(channel);
1669 cmd.rxon_flags = priv->active_rxon.flags;
1670 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1671 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1672 if (ch_info)
1673 cmd.expect_beacon = is_channel_radar(ch_info);
1674 else
1675 cmd.expect_beacon = 1;
1676
1677 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
1678 ctrl_chan_high, &cmd.tx_power);
1679 if (rc) {
1680 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
1681 return rc;
1682 }
1683
857485c0 1684 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 1685 return rc;
1686}
1687
d67f5489 1688static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
b481de9c 1689{
059ff826
TW		 1690 struct iwl4965_shared *s = priv->shared_virt;
1691 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 1692}
1693
c79dd5b5 1694int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 1695{
1696 return priv->temperature;
1697}
1698
c79dd5b5 1699unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
fcab423d 1700 struct iwl_frame *frame, u8 rate)
b481de9c 1701{
bb8c093b 1702 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 1703 unsigned int frame_size;
1704
1705 tx_beacon_cmd = &frame->u.beacon;
1706 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
1707
5425e490 1708 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 1709 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1710
bb8c093b 1711 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 1712 tx_beacon_cmd->frame,
57bd1bea 1713 iwl_bcast_addr,
b481de9c
ZY		 1714 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
1715
1716 BUG_ON(frame_size > MAX_MPDU_SIZE);
1717 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
1718
1719 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
1720 tx_beacon_cmd->tx.rate_n_flags =
e7d326ac 1721 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 1722 else
1723 tx_beacon_cmd->tx.rate_n_flags =
e7d326ac 1724 iwl_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 1725
1726 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
1727 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
1728 return (sizeof(*tx_beacon_cmd) + frame_size);
1729}
1730
399f4900
RR		 1731static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
1732{
1733 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
1734 sizeof(struct iwl4965_shared),
1735 &priv->shared_phys);
1736 if (!priv->shared_virt)
1737 return -ENOMEM;
1738
1739 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
1740
d67f5489
RR		 1741 priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
1742
399f4900
RR		 1743 return 0;
1744}
1745
1746static void iwl4965_free_shared_mem(struct iwl_priv *priv)
1747{
1748 if (priv->shared_virt)
1749 pci_free_consistent(priv->pci_dev,
1750 sizeof(struct iwl4965_shared),
1751 priv->shared_virt,
1752 priv->shared_phys);
1753}
1754
8b6eaea8 1755/**
e2a722eb 1756 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 1757 */
e2a722eb 1758static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 1759 struct iwl_tx_queue *txq,
e2a722eb 1760 u16 byte_cnt)
b481de9c
ZY		 1761{
1762 int len;
1763 int txq_id = txq->q.id;
059ff826 1764 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 1765
b481de9c
ZY		 1766 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1767
8b6eaea8 1768 /* Set up byte count within first 256 entries */
b481de9c 1769 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 1770 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 1771
8b6eaea8 1772 /* If within first 64 entries, duplicate at end */
038669e4 1773 if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
b481de9c 1774 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
038669e4 1775 tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 1776 byte_cnt, len);
b481de9c
ZY		 1777}
1778
b481de9c
ZY		 1779/**
1780 * sign_extend - Sign extend a value using specified bit as sign-bit
1781 *
1782 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1783 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1784 *
1785 * @param oper value to sign extend
1786 * @param index 0 based bit index (0<=index<32) to sign bit
1787 */
1788static s32 sign_extend(u32 oper, int index)
1789{
1790 u8 shift = 31 - index;
1791
1792 return (s32)(oper << shift) >> shift;
1793}
1794
1795/**
1796 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
1797 * @statistics: Provides the temperature reading from the uCode
1798 *
1799 * A return of <0 indicates bogus data in the statistics
1800 */
c79dd5b5 1801int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 1802{
1803 s32 temperature;
1804 s32 vt;
1805 s32 R1, R2, R3;
1806 u32 R4;
1807
1808 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1809 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
1810 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
1811 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1812 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1813 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1814 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1815 } else {
1816 IWL_DEBUG_TEMP("Running temperature calibration\n");
1817 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1818 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1819 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1820 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1821 }
1822
1823 /*
8b6eaea8 1824 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 1825 *
1826 * NOTE If we haven't received a statistics notification yet
1827 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 1828 * "initialize" ALIVE response.
1829 */
b481de9c
ZY		 1830 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1831 vt = sign_extend(R4, 23);
1832 else
1833 vt = sign_extend(
1834 le32_to_cpu(priv->statistics.general.temperature), 23);
1835
1836 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
1837 R1, R2, R3, vt);
1838
1839 if (R3 == R1) {
1840 IWL_ERROR("Calibration conflict R1 == R3\n");
1841 return -1;
1842 }
1843
1844 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1845 * Add offset to center the adjustment around 0 degrees Centigrade. */
1846 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1847 temperature /= (R3 - R1);
1848 temperature = (temperature * 97) / 100 +
1849 TEMPERATURE_CALIB_KELVIN_OFFSET;
1850
1851 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
1852 KELVIN_TO_CELSIUS(temperature));
1853
1854 return temperature;
1855}
1856
1857/* Adjust Txpower only if temperature variance is greater than threshold. */
1858#define IWL_TEMPERATURE_THRESHOLD 3
1859
1860/**
1861 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1862 *
1863 * If the temperature changed has changed sufficiently, then a recalibration
1864 * is needed.
1865 *
1866 * Assumes caller will replace priv->last_temperature once calibration
1867 * executed.
1868 */
c79dd5b5 1869static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1870{
1871 int temp_diff;
1872
1873 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1874 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
1875 return 0;
1876 }
1877
1878 temp_diff = priv->temperature - priv->last_temperature;
1879
1880 /* get absolute value */
1881 if (temp_diff < 0) {
1882 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
1883 temp_diff = -temp_diff;
1884 } else if (temp_diff == 0)
1885 IWL_DEBUG_POWER("Same temp, \n");
1886 else
1887 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
1888
1889 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1890 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
1891 return 0;
1892 }
1893
1894 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
1895
1896 return 1;
1897}
1898
1899/* Calculate noise level, based on measurements during network silence just
1900 * before arriving beacon. This measurement can be done only if we know
1901 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 1902static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 1903{
1904 struct statistics_rx_non_phy *rx_info
1905 = &(priv->statistics.rx.general);
1906 int num_active_rx = 0;
1907 int total_silence = 0;
1908 int bcn_silence_a =
1909 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
1910 int bcn_silence_b =
1911 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
1912 int bcn_silence_c =
1913 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
1914
1915 if (bcn_silence_a) {
1916 total_silence += bcn_silence_a;
1917 num_active_rx++;
1918 }
1919 if (bcn_silence_b) {
1920 total_silence += bcn_silence_b;
1921 num_active_rx++;
1922 }
1923 if (bcn_silence_c) {
1924 total_silence += bcn_silence_c;
1925 num_active_rx++;
1926 }
1927
1928 /* Average among active antennas */
1929 if (num_active_rx)
1930 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
1931 else
1932 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
1933
1934 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
1935 bcn_silence_a, bcn_silence_b, bcn_silence_c,
1936 priv->last_rx_noise);
1937}
1938
a55360e4
TW		 1939void iwl4965_hw_rx_statistics(struct iwl_priv *priv,
1940 struct iwl_rx_mem_buffer *rxb)
b481de9c 1941{
db11d634 1942 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 1943 int change;
1944 s32 temp;
1945
1946 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
1947 (int)sizeof(priv->statistics), pkt->len);
1948
1949 change = ((priv->statistics.general.temperature !=
1950 pkt->u.stats.general.temperature) ||
1951 ((priv->statistics.flag &
1952 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
1953 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
1954
1955 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
1956
1957 set_bit(STATUS_STATISTICS, &priv->status);
1958
1959 /* Reschedule the statistics timer to occur in
1960 * REG_RECALIB_PERIOD seconds to ensure we get a
1961 * thermal update even if the uCode doesn't give
1962 * us one */
1963 mod_timer(&priv->statistics_periodic, jiffies +
1964 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
1965
1966 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1967 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
1968 iwl4965_rx_calc_noise(priv);
16e727e8 1969 queue_work(priv->workqueue, &priv->run_time_calib_work);
b481de9c
ZY		 1970 }
1971
ab53d8af
MA		 1972 iwl_leds_background(priv);
1973
b481de9c
ZY		 1974 /* If the hardware hasn't reported a change in
1975 * temperature then don't bother computing a
1976 * calibrated temperature value */
1977 if (!change)
1978 return;
1979
1980 temp = iwl4965_get_temperature(priv);
1981 if (temp < 0)
1982 return;
1983
1984 if (priv->temperature != temp) {
1985 if (priv->temperature)
1986 IWL_DEBUG_TEMP("Temperature changed "
1987 "from %dC to %dC\n",
1988 KELVIN_TO_CELSIUS(priv->temperature),
1989 KELVIN_TO_CELSIUS(temp));
1990 else
1991 IWL_DEBUG_TEMP("Temperature "
1992 "initialized to %dC\n",
1993 KELVIN_TO_CELSIUS(temp));
1994 }
1995
1996 priv->temperature = temp;
1997 set_bit(STATUS_TEMPERATURE, &priv->status);
1998
203566f3
EG		 1999 if (!priv->disable_tx_power_cal &&
2000 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2001 iwl4965_is_temp_calib_needed(priv))
b481de9c
ZY		 2002 queue_work(priv->workqueue, &priv->txpower_work);
2003}
2004
c79dd5b5 2005static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 2006 struct sk_buff *skb,
2007 struct iwl4965_rx_phy_res *rx_start,
2008 struct ieee80211_rx_status *stats,
2009 u32 ampdu_status)
2010{
566bfe5a 2011 s8 signal = stats->signal;
12342c47 2012 s8 noise = 0;
8318d78a 2013 int rate = stats->rate_idx;
12342c47 2014 u64 tsf = stats->mactime;
a0b484fe 2015 __le16 antenna;
12342c47
ZY		 2016 __le16 phy_flags_hw = rx_start->phy_flags;
2017 struct iwl4965_rt_rx_hdr {
2018 struct ieee80211_radiotap_header rt_hdr;
2019 __le64 rt_tsf; /* TSF */
2020 u8 rt_flags; /* radiotap packet flags */
2021 u8 rt_rate; /* rate in 500kb/s */
2022 __le16 rt_channelMHz; /* channel in MHz */
2023 __le16 rt_chbitmask; /* channel bitfield */
2024 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2025 s8 rt_dbmnoise;
2026 u8 rt_antenna; /* antenna number */
2027 } __attribute__ ((packed)) *iwl4965_rt;
2028
2029 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2030 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2031 if (net_ratelimit())
2032 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 2033 "radiotap head [%zd]\n",
12342c47
ZY		 2034 skb_headroom(skb), sizeof(*iwl4965_rt));
2035 return;
2036 }
2037
2038 /* put radiotap header in front of 802.11 header and data */
2039 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2040
2041 /* initialise radiotap header */
2042 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2043 iwl4965_rt->rt_hdr.it_pad = 0;
2044
2045 /* total header + data */
2046 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2047 &iwl4965_rt->rt_hdr.it_len);
2048
2049 /* Indicate all the fields we add to the radiotap header */
2050 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2051 (1 << IEEE80211_RADIOTAP_FLAGS) |
2052 (1 << IEEE80211_RADIOTAP_RATE) |
2053 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2054 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2055 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2056 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2057 &iwl4965_rt->rt_hdr.it_present);
2058
2059 /* Zero the flags, we'll add to them as we go */
2060 iwl4965_rt->rt_flags = 0;
2061
2062 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2063
2064 iwl4965_rt->rt_dbmsignal = signal;
2065 iwl4965_rt->rt_dbmnoise = noise;
2066
2067 /* Convert the channel frequency and set the flags */
2068 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2069 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2070 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2071 IEEE80211_CHAN_5GHZ),
2072 &iwl4965_rt->rt_chbitmask);
2073 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2074 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2075 IEEE80211_CHAN_2GHZ),
2076 &iwl4965_rt->rt_chbitmask);
2077 else /* 802.11g */
2078 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2079 IEEE80211_CHAN_2GHZ),
2080 &iwl4965_rt->rt_chbitmask);
2081
12342c47
ZY		 2082 if (rate == -1)
2083 iwl4965_rt->rt_rate = 0;
2084 else
1826dcc0 2085 iwl4965_rt->rt_rate = iwl_rates[rate].ieee;
12342c47
ZY		 2086
2087 /*
2088 * "antenna number"
2089 *
2090 * It seems that the antenna field in the phy flags value
2091 * is actually a bitfield. This is undefined by radiotap,
2092 * it wants an actual antenna number but I always get "7"
2093 * for most legacy frames I receive indicating that the
2094 * same frame was received on all three RX chains.
2095 *
2096 * I think this field should be removed in favour of a
2097 * new 802.11n radiotap field "RX chains" that is defined
2098 * as a bitmask.
2099 */
a0b484fe
JB		 2100 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2101 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 2102
2103 /* set the preamble flag if appropriate */
2104 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2105 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2106
2107 stats->flag |= RX_FLAG_RADIOTAP;
2108}
2109
19758bef
TW		 2110static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2111{
2112 /* 0 - mgmt, 1 - cnt, 2 - data */
2113 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2114 priv->rx_stats[idx].cnt++;
2115 priv->rx_stats[idx].bytes += len;
2116}
2117
3ec47732
EG		 2118/*
2119 * returns non-zero if packet should be dropped
2120 */
2121static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2122 struct ieee80211_hdr *hdr,
2123 u32 decrypt_res,
2124 struct ieee80211_rx_status *stats)
2125{
2126 u16 fc = le16_to_cpu(hdr->frame_control);
2127
2128 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2129 return 0;
2130
2131 if (!(fc & IEEE80211_FCTL_PROTECTED))
2132 return 0;
2133
2134 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2135 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2136 case RX_RES_STATUS_SEC_TYPE_TKIP:
2137 /* The uCode has got a bad phase 1 Key, pushes the packet.
2138 * Decryption will be done in SW. */
2139 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2140 RX_RES_STATUS_BAD_KEY_TTAK)
2141 break;
2142
ccc038ab 2143 case RX_RES_STATUS_SEC_TYPE_WEP:
3ec47732
EG		 2144 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2145 RX_RES_STATUS_BAD_ICV_MIC) {
2146 /* bad ICV, the packet is destroyed since the
2147 * decryption is inplace, drop it */
2148 IWL_DEBUG_RX("Packet destroyed\n");
2149 return -1;
2150 }
3ec47732
EG		 2151 case RX_RES_STATUS_SEC_TYPE_CCMP:
2152 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2153 RX_RES_STATUS_DECRYPT_OK) {
2154 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2155 stats->flag |= RX_FLAG_DECRYPTED;
2156 }
2157 break;
2158
2159 default:
2160 break;
2161 }
2162 return 0;
2163}
2164
bf403db8 2165static u32 iwl4965_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
17e476b8
EG		 2166{
2167 u32 decrypt_out = 0;
2168
2169 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2170 RX_RES_STATUS_STATION_FOUND)
2171 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2172 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2173
2174 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2175
2176 /* packet was not encrypted */
2177 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2178 RX_RES_STATUS_SEC_TYPE_NONE)
2179 return decrypt_out;
2180
2181 /* packet was encrypted with unknown alg */
2182 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2183 RX_RES_STATUS_SEC_TYPE_ERR)
2184 return decrypt_out;
2185
2186 /* decryption was not done in HW */
2187 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2188 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2189 return decrypt_out;
2190
2191 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2192
2193 case RX_RES_STATUS_SEC_TYPE_CCMP:
2194 /* alg is CCM: check MIC only */
2195 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2196 /* Bad MIC */
2197 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2198 else
2199 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2200
2201 break;
2202
2203 case RX_RES_STATUS_SEC_TYPE_TKIP:
2204 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2205 /* Bad TTAK */
2206 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2207 break;
2208 }
2209 /* fall through if TTAK OK */
2210 default:
2211 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2212 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2213 else
2214 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2215 break;
2216 };
2217
2218 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2219 decrypt_in, decrypt_out);
2220
2221 return decrypt_out;
2222}
2223
c79dd5b5 2224static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 2225 int include_phy,
a55360e4 2226 struct iwl_rx_mem_buffer *rxb,
b481de9c
ZY		 2227 struct ieee80211_rx_status *stats)
2228{
db11d634 2229 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 2230 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2231 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2232 struct ieee80211_hdr *hdr;
2233 u16 len;
2234 __le32 *rx_end;
2235 unsigned int skblen;
2236 u32 ampdu_status;
17e476b8 2237 u32 ampdu_status_legacy;
b481de9c
ZY		 2238
2239 if (!include_phy && priv->last_phy_res[0])
2240 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2241
2242 if (!rx_start) {
2243 IWL_ERROR("MPDU frame without a PHY data\n");
2244 return;
2245 }
2246 if (include_phy) {
2247 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
2248 rx_start->cfg_phy_cnt);
2249
2250 len = le16_to_cpu(rx_start->byte_count);
2251
2252 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
2253 sizeof(struct iwl4965_rx_phy_res) +
2254 rx_start->cfg_phy_cnt + len);
2255
2256 } else {
2257 struct iwl4965_rx_mpdu_res_start *amsdu =
2258 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2259
2260 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
2261 sizeof(struct iwl4965_rx_mpdu_res_start));
2262 len = le16_to_cpu(amsdu->byte_count);
2263 rx_start->byte_count = amsdu->byte_count;
2264 rx_end = (__le32 *) (((u8 *) hdr) + len);
2265 }
4419e39b
AK		 2266 /* In monitor mode allow 802.11 ACk frames (10 bytes) */
2267 if (len > priv->hw_params.max_pkt_size ||
2268 len < ((priv->iw_mode == IEEE80211_IF_TYPE_MNTR) ? 10 : 16)) {
12342c47 2269 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 2270 return;
2271 }
2272
2273 ampdu_status = le32_to_cpu(*rx_end);
2274 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
2275
17e476b8
EG		 2276 if (!include_phy) {
2277 /* New status scheme, need to translate */
2278 ampdu_status_legacy = ampdu_status;
bf403db8 2279 ampdu_status = iwl4965_translate_rx_status(priv, ampdu_status);
17e476b8
EG		 2280 }
2281
b481de9c
ZY		 2282 /* start from MAC */
2283 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
2284 skb_put(rxb->skb, len); /* end where data ends */
2285
2286 /* We only process data packets if the interface is open */
2287 if (unlikely(!priv->is_open)) {
2288 IWL_DEBUG_DROP_LIMIT
2289 ("Dropping packet while interface is not open.\n");
2290 return;
2291 }
2292
b481de9c
ZY		 2293 stats->flag = 0;
2294 hdr = (struct ieee80211_hdr *)rxb->skb->data;
2295
3ec47732 2296 /* in case of HW accelerated crypto and bad decryption, drop */
099b40b7 2297 if (!priv->hw_params.sw_crypto &&
3ec47732
EG		 2298 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
2299 return;
b481de9c 2300
12342c47
ZY		 2301 if (priv->add_radiotap)
2302 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
2303
19758bef 2304 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 2305 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
2306 priv->alloc_rxb_skb--;
2307 rxb->skb = NULL;
b481de9c
ZY		 2308}
2309
2310/* Calc max signal level (dBm) among 3 possible receivers */
bf403db8
EK		 2311static int iwl4965_calc_rssi(struct iwl_priv *priv,
2312 struct iwl4965_rx_phy_res *rx_resp)
b481de9c
ZY		 2313{
2314 /* data from PHY/DSP regarding signal strength, etc.,
2315 * contents are always there, not configurable by host. */
2316 struct iwl4965_rx_non_cfg_phy *ncphy =
2317 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
2318 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
2319 >> IWL_AGC_DB_POS;
2320
2321 u32 valid_antennae =
2322 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
2323 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
2324 u8 max_rssi = 0;
2325 u32 i;
2326
2327 /* Find max rssi among 3 possible receivers.
2328 * These values are measured by the digital signal processor (DSP).
2329 * They should stay fairly constant even as the signal strength varies,
2330 * if the radio's automatic gain control (AGC) is working right.
2331 * AGC value (see below) will provide the "interesting" info. */
2332 for (i = 0; i < 3; i++)
2333 if (valid_antennae & (1 << i))
2334 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2335
2336 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2337 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2338 max_rssi, agc);
2339
2340 /* dBm = max_rssi dB - agc dB - constant.
2341 * Higher AGC (higher radio gain) means lower signal. */
2342 return (max_rssi - agc - IWL_RSSI_OFFSET);
2343}
2344
c79dd5b5 2345static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 2346{
2347 unsigned long flags;
2348
2349 spin_lock_irqsave(&priv->sta_lock, flags);
2350 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
2351 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
2352 priv->stations[sta_id].sta.sta.modify_mask = 0;
2353 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2354 spin_unlock_irqrestore(&priv->sta_lock, flags);
2355
133636de 2356 iwl_send_add_sta(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 2357}
2358
c79dd5b5 2359static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 2360{
2361 /* FIXME: need locking over ps_status ??? */
947b13a7 2362 u8 sta_id = iwl_find_station(priv, addr);
b481de9c
ZY		 2363
2364 if (sta_id != IWL_INVALID_STATION) {
2365 u8 sta_awake = priv->stations[sta_id].
2366 ps_status == STA_PS_STATUS_WAKE;
2367
2368 if (sta_awake && ps_bit)
2369 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
2370 else if (!sta_awake && !ps_bit) {
2371 iwl4965_sta_modify_ps_wake(priv, sta_id);
2372 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
2373 }
2374 }
2375}
0a6857e7 2376#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 2377
2378/**
2379 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
2380 *
2381 * You may hack this function to show different aspects of received frames,
2382 * including selective frame dumps.
2383 * group100 parameter selects whether to show 1 out of 100 good frames.
2384 *
2385 * TODO: This was originally written for 3945, need to audit for
2386 * proper operation with 4965.
2387 */
c79dd5b5 2388static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
db11d634 2389 struct iwl_rx_packet *pkt,
17744ff6
TW		 2390 struct ieee80211_hdr *header, int group100)
2391{
2392 u32 to_us;
2393 u32 print_summary = 0;
2394 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
2395 u32 hundred = 0;
2396 u32 dataframe = 0;
2397 u16 fc;
2398 u16 seq_ctl;
2399 u16 channel;
2400 u16 phy_flags;
2401 int rate_sym;
2402 u16 length;
2403 u16 status;
2404 u16 bcn_tmr;
2405 u32 tsf_low;
2406 u64 tsf;
2407 u8 rssi;
2408 u8 agc;
2409 u16 sig_avg;
2410 u16 noise_diff;
2411 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
2412 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
2413 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
2414 u8 *data = IWL_RX_DATA(pkt);
2415
bf403db8 2416 if (likely(!(priv->debug_level & IWL_DL_RX)))
17744ff6
TW		 2417 return;
2418
2419 /* MAC header */
2420 fc = le16_to_cpu(header->frame_control);
2421 seq_ctl = le16_to_cpu(header->seq_ctrl);
2422
2423 /* metadata */
2424 channel = le16_to_cpu(rx_hdr->channel);
2425 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
2426 rate_sym = rx_hdr->rate;
2427 length = le16_to_cpu(rx_hdr->len);
2428
2429 /* end-of-frame status and timestamp */
2430 status = le32_to_cpu(rx_end->status);
2431 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
2432 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
2433 tsf = le64_to_cpu(rx_end->timestamp);
2434
2435 /* signal statistics */
2436 rssi = rx_stats->rssi;
2437 agc = rx_stats->agc;
2438 sig_avg = le16_to_cpu(rx_stats->sig_avg);
2439 noise_diff = le16_to_cpu(rx_stats->noise_diff);
2440
2441 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
2442
2443 /* if data frame is to us and all is good,
2444 * (optionally) print summary for only 1 out of every 100 */
2445 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
2446 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
2447 dataframe = 1;
2448 if (!group100)
2449 print_summary = 1; /* print each frame */
2450 else if (priv->framecnt_to_us < 100) {
2451 priv->framecnt_to_us++;
2452 print_summary = 0;
2453 } else {
2454 priv->framecnt_to_us = 0;
2455 print_summary = 1;
2456 hundred = 1;
2457 }
2458 } else {
2459 /* print summary for all other frames */
2460 print_summary = 1;
2461 }
2462
2463 if (print_summary) {
2464 char *title;
2465 int rate_idx;
2466 u32 bitrate;
2467
2468 if (hundred)
2469 title = "100Frames";
2470 else if (fc & IEEE80211_FCTL_RETRY)
2471 title = "Retry";
2472 else if (ieee80211_is_assoc_response(fc))
2473 title = "AscRsp";
2474 else if (ieee80211_is_reassoc_response(fc))
2475 title = "RasRsp";
2476 else if (ieee80211_is_probe_response(fc)) {
2477 title = "PrbRsp";
2478 print_dump = 1; /* dump frame contents */
2479 } else if (ieee80211_is_beacon(fc)) {
2480 title = "Beacon";
2481 print_dump = 1; /* dump frame contents */
2482 } else if (ieee80211_is_atim(fc))
2483 title = "ATIM";
2484 else if (ieee80211_is_auth(fc))
2485 title = "Auth";
2486 else if (ieee80211_is_deauth(fc))
2487 title = "DeAuth";
2488 else if (ieee80211_is_disassoc(fc))
2489 title = "DisAssoc";
2490 else
2491 title = "Frame";
2492
e7d326ac 2493 rate_idx = iwl_hwrate_to_plcp_idx(rate_sym);
17744ff6
TW		 2494 if (unlikely(rate_idx == -1))
2495 bitrate = 0;
2496 else
1826dcc0 2497 bitrate = iwl_rates[rate_idx].ieee / 2;
17744ff6
TW		 2498
2499 /* print frame summary.
2500 * MAC addresses show just the last byte (for brevity),
2501 * but you can hack it to show more, if you'd like to. */
2502 if (dataframe)
2503 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
2504 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
2505 title, fc, header->addr1[5],
2506 length, rssi, channel, bitrate);
2507 else {
2508 /* src/dst addresses assume managed mode */
2509 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
2510 "src=0x%02x, rssi=%u, tim=%lu usec, "
2511 "phy=0x%02x, chnl=%d\n",
2512 title, fc, header->addr1[5],
2513 header->addr3[5], rssi,
2514 tsf_low - priv->scan_start_tsf,
2515 phy_flags, channel);
2516 }
2517 }
2518 if (print_dump)
bf403db8 2519 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6
TW		 2520}
2521#else
c79dd5b5 2522static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
db11d634 2523 struct iwl_rx_packet *pkt,
17744ff6
TW		 2524 struct ieee80211_hdr *header,
2525 int group100)
2526{
2527}
2528#endif
2529
b481de9c 2530
7878a5a4 2531
857485c0 2532/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 2533 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
37a44211 2534void iwl4965_rx_reply_rx(struct iwl_priv *priv,
a55360e4 2535 struct iwl_rx_mem_buffer *rxb)
b481de9c 2536{
17744ff6
TW		 2537 struct ieee80211_hdr *header;
2538 struct ieee80211_rx_status rx_status;
db11d634 2539 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 2540 /* Use phy data (Rx signal strength, etc.) contained within
2541 * this rx packet for legacy frames,
2542 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 2543 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 2544 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2545 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
2546 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2547 __le32 *rx_end;
2548 unsigned int len = 0;
b481de9c 2549 u16 fc;
b481de9c
ZY		 2550 u8 network_packet;
2551
17744ff6 2552 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
dc92e497 2553 rx_status.freq =
c0186078 2554 ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
17744ff6
TW		 2555 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
2556 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
dc92e497 2557 rx_status.rate_idx =
e7d326ac 2558 iwl_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
17744ff6
TW		 2559 if (rx_status.band == IEEE80211_BAND_5GHZ)
2560 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
2561
2562 rx_status.antenna = 0;
2563 rx_status.flag = 0;
2564
b481de9c 2565 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
dc92e497
TW		 2566 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
2567 rx_start->cfg_phy_cnt);
b481de9c
ZY		 2568 return;
2569 }
17744ff6 2570
b481de9c
ZY		 2571 if (!include_phy) {
2572 if (priv->last_phy_res[0])
2573 rx_start = (struct iwl4965_rx_phy_res *)
2574 &priv->last_phy_res[1];
2575 else
2576 rx_start = NULL;
2577 }
2578
2579 if (!rx_start) {
2580 IWL_ERROR("MPDU frame without a PHY data\n");
2581 return;
2582 }
2583
2584 if (include_phy) {
2585 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
2586 + rx_start->cfg_phy_cnt);
2587
2588 len = le16_to_cpu(rx_start->byte_count);
17744ff6 2589 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 2590 sizeof(struct iwl4965_rx_phy_res) + len);
2591 } else {
2592 struct iwl4965_rx_mpdu_res_start *amsdu =
2593 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2594
2595 header = (void *)(pkt->u.raw +
2596 sizeof(struct iwl4965_rx_mpdu_res_start));
2597 len = le16_to_cpu(amsdu->byte_count);
2598 rx_end = (__le32 *) (pkt->u.raw +
2599 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
2600 }
2601
2602 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
2603 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
2604 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
2605 le32_to_cpu(*rx_end));
2606 return;
2607 }
2608
2609 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
2610
b481de9c 2611 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
566bfe5a 2612 rx_status.signal = iwl4965_calc_rssi(priv, rx_start);
b481de9c
ZY		 2613
2614 /* Meaningful noise values are available only from beacon statistics,
2615 * which are gathered only when associated, and indicate noise
2616 * only for the associated network channel ...
2617 * Ignore these noise values while scanning (other channels) */
3109ece1 2618 if (iwl_is_associated(priv) &&
b481de9c 2619 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6 2620 rx_status.noise = priv->last_rx_noise;
566bfe5a 2621 rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal,
17744ff6 2622 rx_status.noise);
b481de9c 2623 } else {
17744ff6 2624 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
566bfe5a 2625 rx_status.qual = iwl4965_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 2626 }
2627
2628 /* Reset beacon noise level if not associated. */
3109ece1 2629 if (!iwl_is_associated(priv))
b481de9c
ZY		 2630 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2631
17744ff6
TW		 2632 /* Set "1" to report good data frames in groups of 100 */
2633 /* FIXME: need to optimze the call: */
2634 iwl4965_dbg_report_frame(priv, pkt, header, 1);
2635
2636 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
566bfe5a 2637 rx_status.signal, rx_status.noise, rx_status.signal,
06501d29 2638 (unsigned long long)rx_status.mactime);
b481de9c 2639
4419e39b
AK		 2640
2641 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
2642 iwl4965_handle_data_packet(priv, 1, include_phy,
2643 rxb, &rx_status);
2644 return;
2645 }
2646
bb8c093b 2647 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 2648 if (network_packet) {
566bfe5a 2649 priv->last_rx_rssi = rx_status.signal;
b481de9c
ZY		 2650 priv->last_beacon_time = priv->ucode_beacon_time;
2651 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
2652 }
2653
2654 fc = le16_to_cpu(header->frame_control);
2655 switch (fc & IEEE80211_FCTL_FTYPE) {
2656 case IEEE80211_FTYPE_MGMT:
b481de9c
ZY		 2657 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
2658 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
2659 header->addr2);
17744ff6 2660 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 2661 break;
2662
2663 case IEEE80211_FTYPE_CTL:
b481de9c
ZY		 2664 switch (fc & IEEE80211_FCTL_STYPE) {
2665 case IEEE80211_STYPE_BACK_REQ:
2666 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
2667 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 2668 rxb, &rx_status);
b481de9c
ZY		 2669 break;
2670 default:
2671 break;
2672 }
b481de9c
ZY		 2673 break;
2674
0795af57
JP		 2675 case IEEE80211_FTYPE_DATA: {
2676 DECLARE_MAC_BUF(mac1);
2677 DECLARE_MAC_BUF(mac2);
2678 DECLARE_MAC_BUF(mac3);
2679
b481de9c
ZY		 2680 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
2681 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
2682 header->addr2);
2683
2684 if (unlikely(!network_packet))
2685 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 2686 "%s, %s, %s\n",
2687 print_mac(mac1, header->addr1),
2688 print_mac(mac2, header->addr2),
2689 print_mac(mac3, header->addr3));
bb8c093b 2690 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 2691 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
2692 print_mac(mac1, header->addr1),
2693 print_mac(mac2, header->addr2),
2694 print_mac(mac3, header->addr3));
b481de9c
ZY		 2695 else
2696 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 2697 &rx_status);
b481de9c 2698 break;
0795af57 2699 }
b481de9c
ZY		 2700 default:
2701 break;
2702
2703 }
2704}
2705
8b6eaea8
CB		 2706/**
2707 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
2708 *
2709 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
2710 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
2711 */
c79dd5b5 2712static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
6def9761 2713 struct iwl_ht_agg *agg,
bb8c093b 2714 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 2715 ba_resp)
2716
2717{
2718 int i, sh, ack;
fe01b477
RR		 2719 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
2720 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
2721 u64 bitmap;
2722 int successes = 0;
e039fa4a 2723 struct ieee80211_tx_info *info;
b481de9c
ZY		 2724
2725 if (unlikely(!agg->wait_for_ba)) {
2726 IWL_ERROR("Received BA when not expected\n");
2727 return -EINVAL;
2728 }
8b6eaea8
CB		 2729
2730 /* Mark that the expected block-ack response arrived */
b481de9c 2731 agg->wait_for_ba = 0;
fe01b477 2732 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 2733
2734 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 2735 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 2736 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 2737 sh += 0x100;
2738
8b6eaea8 2739 /* don't use 64-bit values for now */
fe01b477 2740 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 2741
2742 if (agg->frame_count > (64 - sh)) {
2743 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
2744 return -1;
2745 }
2746
2747 /* check for success or failure according to the
8b6eaea8 2748 * transmitted bitmap and block-ack bitmap */
fe01b477 2749 bitmap &= agg->bitmap;
b481de9c 2750
8b6eaea8
CB		 2751 /* For each frame attempted in aggregation,
2752 * update driver's record of tx frame's status. */
b481de9c 2753 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 2754 ack = bitmap & (1 << i);
2755 successes += !!ack;
b481de9c 2756 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 2757 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
2758 agg->start_idx + i);
2759 }
2760
e039fa4a
JB		 2761 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
2762 memset(&info->status, 0, sizeof(info->status));
2763 info->flags = IEEE80211_TX_STAT_ACK;
2764 info->flags |= IEEE80211_TX_STAT_AMPDU;
2765 info->status.ampdu_ack_map = successes;
2766 info->status.ampdu_ack_len = agg->frame_count;
e7d326ac 2767 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
fe01b477 2768
f868f4e1 2769 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 2770
2771 return 0;
2772}
2773
2774/**
2775 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
2776 */
c79dd5b5 2777static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 2778 u16 txq_id)
2779{
2780 /* Simply stop the queue, but don't change any configuration;
2781 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 2782 iwl_write_prph(priv,
12a81f60 2783 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 2784 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
2785 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
fe01b477 2786}
b481de9c 2787
fe01b477 2788/**
7f3e4bb6 2789 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
b095d03a 2790 * priv->lock must be held by the caller
fe01b477 2791 */
30e553e3
TW		 2792static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
2793 u16 ssn_idx, u8 tx_fifo)
fe01b477 2794{
b095d03a
RR		 2795 int ret = 0;
2796
7f3e4bb6 2797 if (IWL49_FIRST_AMPDU_QUEUE > txq_id) {
fe01b477 2798 IWL_WARNING("queue number too small: %d, must be > %d\n",
7f3e4bb6 2799 txq_id, IWL49_FIRST_AMPDU_QUEUE);
fe01b477 2800 return -EINVAL;
b481de9c
ZY		 2801 }
2802
3395f6e9 2803 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 2804 if (ret)
2805 return ret;
2806
fe01b477
RR		 2807 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
2808
12a81f60 2809 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 2810
2811 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2812 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
2813 /* supposes that ssn_idx is valid (!= 0xFFF) */
2814 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
2815
12a81f60 2816 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
36470749 2817 iwl_txq_ctx_deactivate(priv, txq_id);
fe01b477
RR		 2818 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
2819
3395f6e9 2820 iwl_release_nic_access(priv);
b095d03a 2821
fe01b477
RR		 2822 return 0;
2823}
b481de9c 2824
b481de9c 2825
8b6eaea8
CB		 2826/**
2827 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
2828 *
2829 * Handles block-acknowledge notification from device, which reports success
2830 * of frames sent via aggregation.
2831 */
c79dd5b5 2832static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
a55360e4 2833 struct iwl_rx_mem_buffer *rxb)
b481de9c 2834{
db11d634 2835 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
bb8c093b 2836 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 2837 int index;
16466903 2838 struct iwl_tx_queue *txq = NULL;
6def9761 2839 struct iwl_ht_agg *agg;
fe01b477 2840 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 2841
2842 /* "flow" corresponds to Tx queue */
fe01b477 2843 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 2844
2845 /* "ssn" is start of block-ack Tx window, corresponds to index
2846 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 2847 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
2848
dfe7d458 2849 if (scd_flow >= priv->hw_params.max_txq_num) {
b481de9c
ZY		 2850 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
2851 return;
2852 }
2853
fe01b477 2854 txq = &priv->txq[scd_flow];
b481de9c 2855 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 2856
2857 /* Find index just before block-ack window */
443cfd45 2858 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 2859
01ebd063 2860 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 2861
0795af57
JP		 2862 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
2863 "sta_id = %d\n",
b481de9c 2864 agg->wait_for_ba,
0795af57 2865 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 2866 ba_resp->sta_id);
fe01b477 2867 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 2868 "%d, scd_ssn = %d\n",
2869 ba_resp->tid,
fe01b477 2870 ba_resp->seq_ctl,
0310ae72 2871 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 2872 ba_resp->scd_flow,
2873 ba_resp->scd_ssn);
fe01b477 2874 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 2875 agg->start_idx,
f868f4e1 2876 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 2877
2878 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 2879 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 2880
2881 /* Release all TFDs before the SSN, i.e. all TFDs in front of
2882 * block-ack window (we assume that they've been successfully
2883 * transmitted ... if not, it's too late anyway). */
fe01b477 2884 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
0d0b2c1c
RR		 2885 /* calculate mac80211 ampdu sw queue to wake */
2886 int ampdu_q =
7f3e4bb6 2887 scd_flow - priv->hw_params.first_ampdu_q + priv->hw->queues;
17b88929 2888 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
fe01b477
RR		 2889 priv->stations[ba_resp->sta_id].
2890 tid[ba_resp->tid].tfds_in_queue -= freed;
443cfd45 2891 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
fe01b477
RR		 2892 priv->mac80211_registered &&
2893 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
0d0b2c1c 2894 ieee80211_wake_queue(priv->hw, ampdu_q);
30e553e3
TW		 2895
2896 iwl_txq_check_empty(priv, ba_resp->sta_id,
2897 ba_resp->tid, scd_flow);
fe01b477 2898 }
b481de9c
ZY		 2899}
2900
8b6eaea8
CB		 2901/**
2902 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
2903 */
c79dd5b5 2904static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 2905 u16 txq_id)
2906{
2907 u32 tbl_dw_addr;
2908 u32 tbl_dw;
2909 u16 scd_q2ratid;
2910
30e553e3 2911 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
b481de9c
ZY		 2912
2913 tbl_dw_addr = priv->scd_base_addr +
038669e4 2914 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
b481de9c 2915
3395f6e9 2916 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 2917
2918 if (txq_id & 0x1)
2919 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
2920 else
2921 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
2922
3395f6e9 2923 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 2924
2925 return 0;
2926}
2927
fe01b477 2928
b481de9c 2929/**
8b6eaea8
CB		 2930 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
2931 *
7f3e4bb6 2932 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
8b6eaea8 2933 * i.e. it must be one of the higher queues used for aggregation
b481de9c 2934 */
30e553e3
TW		 2935static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
2936 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
b481de9c
ZY		 2937{
2938 unsigned long flags;
30e553e3 2939 int ret;
b481de9c
ZY		 2940 u16 ra_tid;
2941
7f3e4bb6 2942 if (IWL49_FIRST_AMPDU_QUEUE > txq_id)
b481de9c 2943 IWL_WARNING("queue number too small: %d, must be > %d\n",
7f3e4bb6 2944 txq_id, IWL49_FIRST_AMPDU_QUEUE);
b481de9c
ZY		 2945
2946 ra_tid = BUILD_RAxTID(sta_id, tid);
2947
8b6eaea8 2948 /* Modify device's station table to Tx this TID */
5083e563 2949 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 2950
2951 spin_lock_irqsave(&priv->lock, flags);
30e553e3
TW		 2952 ret = iwl_grab_nic_access(priv);
2953 if (ret) {
b481de9c 2954 spin_unlock_irqrestore(&priv->lock, flags);
30e553e3 2955 return ret;
b481de9c
ZY		 2956 }
2957
8b6eaea8 2958 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 2959 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
2960
8b6eaea8 2961 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 2962 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
2963
8b6eaea8 2964 /* Set this queue as a chain-building queue */
12a81f60 2965 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 2966
8b6eaea8
CB		 2967 /* Place first TFD at index corresponding to start sequence number.
2968 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 2969 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
2970 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 2971 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
2972
8b6eaea8 2973 /* Set up Tx window size and frame limit for this queue */
3395f6e9 2974 iwl_write_targ_mem(priv,
038669e4
EG		 2975 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
2976 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
2977 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
b481de9c 2978
3395f6e9 2979 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 2980 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
2981 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
2982 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c 2983
12a81f60 2984 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 2985
8b6eaea8 2986 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 2987 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
2988
3395f6e9 2989 iwl_release_nic_access(priv);
b481de9c
ZY		 2990 spin_unlock_irqrestore(&priv->lock, flags);
2991
2992 return 0;
2993}
2994
fe07aa7a
RR		 2995static int iwl4965_rx_agg_start(struct iwl_priv *priv,
2996 const u8 *addr, int tid, u16 ssn)
b481de9c
ZY		 2997{
2998 unsigned long flags;
fe07aa7a
RR		 2999 int sta_id;
3000
3001 sta_id = iwl_find_station(priv, addr);
3002 if (sta_id == IWL_INVALID_STATION)
3003 return -ENXIO;
b481de9c
ZY		 3004
3005 spin_lock_irqsave(&priv->sta_lock, flags);
3006 priv->stations[sta_id].sta.station_flags_msk = 0;
3007 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3008 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
3009 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3010 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3011 spin_unlock_irqrestore(&priv->sta_lock, flags);
3012
133636de 3013 return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
fe07aa7a 3014 CMD_ASYNC);
b481de9c
ZY		 3015}
3016
fe07aa7a
RR		 3017static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
3018 const u8 *addr, int tid)
b481de9c
ZY		 3019{
3020 unsigned long flags;
fe07aa7a
RR		 3021 int sta_id;
3022
3023 sta_id = iwl_find_station(priv, addr);
3024 if (sta_id == IWL_INVALID_STATION)
3025 return -ENXIO;
b481de9c
ZY		 3026
3027 spin_lock_irqsave(&priv->sta_lock, flags);
3028 priv->stations[sta_id].sta.station_flags_msk = 0;
3029 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3030 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
3031 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3032 spin_unlock_irqrestore(&priv->sta_lock, flags);
3033
133636de 3034 return iwl_send_add_sta(priv, &priv->stations[sta_id].sta,
fe07aa7a 3035 CMD_ASYNC);
b481de9c
ZY		 3036}
3037
8114fcf1
RR		 3038int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
3039 enum ieee80211_ampdu_mlme_action action,
3040 const u8 *addr, u16 tid, u16 *ssn)
3041{
c79dd5b5 3042 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 3043 DECLARE_MAC_BUF(mac);
3044
fe07aa7a
RR		 3045 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
3046 print_mac(mac, addr), tid);
3047
8114fcf1
RR		 3048 switch (action) {
3049 case IEEE80211_AMPDU_RX_START:
3050 IWL_DEBUG_HT("start Rx\n");
fe07aa7a 3051 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
8114fcf1
RR		 3052 case IEEE80211_AMPDU_RX_STOP:
3053 IWL_DEBUG_HT("stop Rx\n");
fe07aa7a 3054 return iwl4965_rx_agg_stop(priv, addr, tid);
8114fcf1
RR		 3055 case IEEE80211_AMPDU_TX_START:
3056 IWL_DEBUG_HT("start Tx\n");
30e553e3 3057 return iwl_tx_agg_start(priv, addr, tid, ssn);
8114fcf1
RR		 3058 case IEEE80211_AMPDU_TX_STOP:
3059 IWL_DEBUG_HT("stop Tx\n");
30e553e3 3060 return iwl_tx_agg_stop(priv, addr, tid);
8114fcf1
RR		 3061 default:
3062 IWL_DEBUG_HT("unknown\n");
3063 return -EINVAL;
3064 break;
3065 }
3066 return 0;
3067}
133636de 3068
c1adf9fb
GG		 3069static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
3070{
3071 switch (cmd_id) {
3072 case REPLY_RXON:
3073 return (u16) sizeof(struct iwl4965_rxon_cmd);
3074 default:
3075 return len;
3076 }
3077}
3078
133636de
TW		 3079static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
3080{
3081 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
3082 addsta->mode = cmd->mode;
3083 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
3084 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
3085 addsta->station_flags = cmd->station_flags;
3086 addsta->station_flags_msk = cmd->station_flags_msk;
3087 addsta->tid_disable_tx = cmd->tid_disable_tx;
3088 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
3089 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
3090 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
3091 addsta->reserved1 = __constant_cpu_to_le16(0);
3092 addsta->reserved2 = __constant_cpu_to_le32(0);
3093
3094 return (u16)sizeof(struct iwl4965_addsta_cmd);
3095}
f20217d9 3096
f20217d9
TW		 3097static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
3098{
25a6572c 3099 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
f20217d9
TW		 3100}
3101
3102/**
3103 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
3104 */
3105static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
3106 struct iwl_ht_agg *agg,
25a6572c
TW		 3107 struct iwl4965_tx_resp *tx_resp,
3108 int txq_id, u16 start_idx)
f20217d9
TW		 3109{
3110 u16 status;
25a6572c 3111 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
f20217d9
TW		 3112 struct ieee80211_tx_info *info = NULL;
3113 struct ieee80211_hdr *hdr = NULL;
e7d326ac 3114 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 3115 int i, sh, idx;
f20217d9 3116 u16 seq;
f20217d9
TW		 3117 if (agg->wait_for_ba)
3118 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
3119
3120 agg->frame_count = tx_resp->frame_count;
3121 agg->start_idx = start_idx;
e7d326ac 3122 agg->rate_n_flags = rate_n_flags;
f20217d9
TW		 3123 agg->bitmap = 0;
3124
3125 /* # frames attempted by Tx command */
3126 if (agg->frame_count == 1) {
3127 /* Only one frame was attempted; no block-ack will arrive */
3128 status = le16_to_cpu(frame_status[0].status);
25a6572c 3129 idx = start_idx;
f20217d9
TW		 3130
3131 /* FIXME: code repetition */
3132 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
3133 agg->frame_count, agg->start_idx, idx);
3134
3135 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
3136 info->status.retry_count = tx_resp->failure_frame;
3137 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
3138 info->flags |= iwl_is_tx_success(status)?
3139 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 3140 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
f20217d9
TW		 3141 /* FIXME: code repetition end */
3142
3143 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
3144 status & 0xff, tx_resp->failure_frame);
e7d326ac 3145 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
f20217d9
TW		 3146
3147 agg->wait_for_ba = 0;
3148 } else {
3149 /* Two or more frames were attempted; expect block-ack */
3150 u64 bitmap = 0;
3151 int start = agg->start_idx;
3152
3153 /* Construct bit-map of pending frames within Tx window */
3154 for (i = 0; i < agg->frame_count; i++) {
3155 u16 sc;
3156 status = le16_to_cpu(frame_status[i].status);
3157 seq = le16_to_cpu(frame_status[i].sequence);
3158 idx = SEQ_TO_INDEX(seq);
3159 txq_id = SEQ_TO_QUEUE(seq);
3160
3161 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
3162 AGG_TX_STATE_ABORT_MSK))
3163 continue;
3164
3165 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
3166 agg->frame_count, txq_id, idx);
3167
3168 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
3169
3170 sc = le16_to_cpu(hdr->seq_ctrl);
3171 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
3172 IWL_ERROR("BUG_ON idx doesn't match seq control"
3173 " idx=%d, seq_idx=%d, seq=%d\n",
3174 idx, SEQ_TO_SN(sc),
3175 hdr->seq_ctrl);
3176 return -1;
3177 }
3178
3179 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
3180 i, idx, SEQ_TO_SN(sc));
3181
3182 sh = idx - start;
3183 if (sh > 64) {
3184 sh = (start - idx) + 0xff;
3185 bitmap = bitmap << sh;
3186 sh = 0;
3187 start = idx;
3188 } else if (sh < -64)
3189 sh = 0xff - (start - idx);
3190 else if (sh < 0) {
3191 sh = start - idx;
3192 start = idx;
3193 bitmap = bitmap << sh;
3194 sh = 0;
3195 }
3196 bitmap |= (1 << sh);
3197 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
3198 start, (u32)(bitmap & 0xFFFFFFFF));
3199 }
3200
3201 agg->bitmap = bitmap;
3202 agg->start_idx = start;
f20217d9
TW		 3203 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
3204 agg->frame_count, agg->start_idx,
3205 (unsigned long long)agg->bitmap);
3206
3207 if (bitmap)
3208 agg->wait_for_ba = 1;
3209 }
3210 return 0;
3211}
f20217d9
TW		 3212
3213/**
3214 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
3215 */
3216static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
3217 struct iwl_rx_mem_buffer *rxb)
3218{
3219 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
3220 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3221 int txq_id = SEQ_TO_QUEUE(sequence);
3222 int index = SEQ_TO_INDEX(sequence);
3223 struct iwl_tx_queue *txq = &priv->txq[txq_id];
3224 struct ieee80211_tx_info *info;
3225 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
25a6572c 3226 u32 status = le32_to_cpu(tx_resp->u.status);
f20217d9
TW		 3227 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
3228 u16 fc;
3229 struct ieee80211_hdr *hdr;
3230 u8 *qc = NULL;
f20217d9
TW		 3231
3232 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
3233 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
3234 "is out of range [0-%d] %d %d\n", txq_id,
3235 index, txq->q.n_bd, txq->q.write_ptr,
3236 txq->q.read_ptr);
3237 return;
3238 }
3239
3240 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
3241 memset(&info->status, 0, sizeof(info->status));
3242
f20217d9
TW		 3243 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
3244 fc = le16_to_cpu(hdr->frame_control);
3245 if (ieee80211_is_qos_data(fc)) {
3246 qc = ieee80211_get_qos_ctrl(hdr, ieee80211_get_hdrlen(fc));
3247 tid = qc[0] & 0xf;
3248 }
3249
3250 sta_id = iwl_get_ra_sta_id(priv, hdr);
3251 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
3252 IWL_ERROR("Station not known\n");
3253 return;
3254 }
3255
3256 if (txq->sched_retry) {
3257 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
3258 struct iwl_ht_agg *agg = NULL;
3259
3260 if (!qc)
3261 return;
3262
3263 agg = &priv->stations[sta_id].tid[tid].agg;
3264
25a6572c 3265 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
f20217d9
TW		 3266
3267 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) {
3268 /* TODO: send BAR */
3269 }
3270
3271 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
3272 int freed, ampdu_q;
3273 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
3274 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
3275 "%d index %d\n", scd_ssn , index);
17b88929 3276 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
f20217d9
TW		 3277 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3278
3279 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
3280 txq_id >= 0 && priv->mac80211_registered &&
3281 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
3282 /* calculate mac80211 ampdu sw queue to wake */
7f3e4bb6 3283 ampdu_q = txq_id - IWL49_FIRST_AMPDU_QUEUE +
f20217d9
TW		 3284 priv->hw->queues;
3285 if (agg->state == IWL_AGG_OFF)
3286 ieee80211_wake_queue(priv->hw, txq_id);
3287 else
3288 ieee80211_wake_queue(priv->hw, ampdu_q);
3289 }
30e553e3 3290 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
f20217d9
TW		 3291 }
3292 } else {
4f85f5b3
RR		 3293 info->status.retry_count = tx_resp->failure_frame;
3294 info->flags |=
3295 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
e7d326ac 3296 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 3297 le32_to_cpu(tx_resp->rate_n_flags),
3298 info);
3299
3300 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
3301 "0x%x retries %d\n", txq_id,
3302 iwl_get_tx_fail_reason(status),
3303 status, le32_to_cpu(tx_resp->rate_n_flags),
3304 tx_resp->failure_frame);
3305
3306 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
e7d326ac 3307
4f85f5b3
RR		 3308 if (index != -1) {
3309 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
3310 if (tid != MAX_TID_COUNT)
f20217d9 3311 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
4f85f5b3 3312 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
f20217d9
TW		 3313 (txq_id >= 0) && priv->mac80211_registered)
3314 ieee80211_wake_queue(priv->hw, txq_id);
4f85f5b3 3315 if (tid != MAX_TID_COUNT)
30e553e3 3316 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
4f85f5b3 3317 }
f20217d9 3318 }
f20217d9
TW		 3319
3320 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
3321 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
3322}
3323
3324
b481de9c 3325/* Set up 4965-specific Rx frame reply handlers */
d4789efe 3326static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 3327{
3328 /* Legacy Rx frames */
857485c0 3329 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
37a44211 3330 /* Tx response */
f20217d9 3331 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
4f85f5b3 3332 /* block ack */
b481de9c 3333 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
b481de9c
ZY		 3334}
3335
4e39317d 3336static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 3337{
3338 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
b481de9c
ZY		 3339}
3340
4e39317d 3341static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3342{
4e39317d 3343 cancel_work_sync(&priv->txpower_work);
b481de9c
ZY		 3344}
3345
3c424c28
TW		 3346
3347static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 3348 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 3349};
3350
857485c0 3351static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
c1adf9fb 3352 .get_hcmd_size = iwl4965_get_hcmd_size,
133636de 3353 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
f0832f13
EG		 3354 .chain_noise_reset = iwl4965_chain_noise_reset,
3355 .gain_computation = iwl4965_gain_computation,
857485c0
TW		 3356};
3357
6bc913bd 3358static struct iwl_lib_ops iwl4965_lib = {
5425e490 3359 .set_hw_params = iwl4965_hw_set_hw_params,
399f4900
RR		 3360 .alloc_shared_mem = iwl4965_alloc_shared_mem,
3361 .free_shared_mem = iwl4965_free_shared_mem,
d67f5489 3362 .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
e2a722eb 3363 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
da1bc453 3364 .txq_set_sched = iwl4965_txq_set_sched,
30e553e3
TW		 3365 .txq_agg_enable = iwl4965_txq_agg_enable,
3366 .txq_agg_disable = iwl4965_txq_agg_disable,
d4789efe 3367 .rx_handler_setup = iwl4965_rx_handler_setup,
4e39317d
EG		 3368 .setup_deferred_work = iwl4965_setup_deferred_work,
3369 .cancel_deferred_work = iwl4965_cancel_deferred_work,
57aab75a
TW		 3370 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
3371 .alive_notify = iwl4965_alive_notify,
f3ccc08c 3372 .init_alive_start = iwl4965_init_alive_start,
57aab75a 3373 .load_ucode = iwl4965_load_bsm,
6f4083aa 3374 .apm_ops = {
91238714 3375 .init = iwl4965_apm_init,
7f066108 3376 .reset = iwl4965_apm_reset,
f118a91d 3377 .stop = iwl4965_apm_stop,
694cc56d 3378 .config = iwl4965_nic_config,
6f4083aa
TW		 3379 .set_pwr_src = iwl4965_set_pwr_src,
3380 },
6bc913bd 3381 .eeprom_ops = {
073d3f5f
TW		 3382 .regulatory_bands = {
3383 EEPROM_REGULATORY_BAND_1_CHANNELS,
3384 EEPROM_REGULATORY_BAND_2_CHANNELS,
3385 EEPROM_REGULATORY_BAND_3_CHANNELS,
3386 EEPROM_REGULATORY_BAND_4_CHANNELS,
3387 EEPROM_REGULATORY_BAND_5_CHANNELS,
3388 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
3389 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
3390 },
6bc913bd
AK		 3391 .verify_signature = iwlcore_eeprom_verify_signature,
3392 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
3393 .release_semaphore = iwlcore_eeprom_release_semaphore,
8614f360 3394 .check_version = iwl4965_eeprom_check_version,
073d3f5f 3395 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 3396 },
ad97edd2 3397 .radio_kill_sw = iwl4965_radio_kill_sw,
5da4b55f 3398 .set_power = iwl4965_set_power,
630fe9b6 3399 .send_tx_power = iwl4965_send_tx_power,
5da4b55f 3400 .update_chain_flags = iwl4965_update_chain_flags,
6bc913bd
AK		 3401};
3402
3403static struct iwl_ops iwl4965_ops = {
3404 .lib = &iwl4965_lib,
3c424c28 3405 .hcmd = &iwl4965_hcmd,
857485c0 3406 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 3407};
3408
fed9017e 3409struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 3410 .name = "4965AGN",
4bf775cd 3411 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 3412 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 3413 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
6bc913bd 3414 .ops = &iwl4965_ops,
1ea87396 3415 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 3416};
3417
1ea87396
AK		 3418module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
3419MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
3420module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
3421MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b
EG		 3422module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
3423MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
1ea87396
AK		 3424module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
3425MODULE_PARM_DESC(debug, "debug output mask");
3426module_param_named(
3427 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
3428MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
3429
3430module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
3431MODULE_PARM_DESC(queues_num, "number of hw queues.");
3432
3433/* QoS */
3434module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
3435MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
3436module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
3437MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
3a1081e8
EK		 3438module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
3439MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
Linux kernel - Deliverables
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