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iwlwifi: remove the statistics work
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
b481de9c 42#include "iwl-4965.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c
ZY		 45#include "iwl-helpers.h"
46
1ea87396
AK		 47/* module parameters */
48static struct iwl_mod_params iwl4965_mod_params = {
49 .num_of_queues = IWL_MAX_NUM_QUEUES,
50 .enable_qos = 1,
51 .amsdu_size_8K = 1,
52 /* the rest are 0 by default */
53};
54
c79dd5b5 55static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
416e1438 56
b481de9c
ZY		 57#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
58 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
59 IWL_RATE_SISO_##s##M_PLCP, \
60 IWL_RATE_MIMO_##s##M_PLCP, \
61 IWL_RATE_##r##M_IEEE, \
62 IWL_RATE_##ip##M_INDEX, \
63 IWL_RATE_##in##M_INDEX, \
64 IWL_RATE_##rp##M_INDEX, \
65 IWL_RATE_##rn##M_INDEX, \
66 IWL_RATE_##pp##M_INDEX, \
67 IWL_RATE_##np##M_INDEX }
68
69/*
70 * Parameter order:
71 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
72 *
73 * If there isn't a valid next or previous rate then INV is used which
74 * maps to IWL_RATE_INVALID
75 *
76 */
bb8c093b 77const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
b481de9c
ZY		 78 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
79 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
80 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
81 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
82 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
83 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
84 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
85 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
86 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
87 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
88 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
89 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
90 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
91};
92
fe01b477
RR		 93#ifdef CONFIG_IWL4965_HT
94
95static const u16 default_tid_to_tx_fifo[] = {
96 IWL_TX_FIFO_AC1,
97 IWL_TX_FIFO_AC0,
98 IWL_TX_FIFO_AC0,
99 IWL_TX_FIFO_AC1,
100 IWL_TX_FIFO_AC2,
101 IWL_TX_FIFO_AC2,
102 IWL_TX_FIFO_AC3,
103 IWL_TX_FIFO_AC3,
104 IWL_TX_FIFO_NONE,
105 IWL_TX_FIFO_NONE,
106 IWL_TX_FIFO_NONE,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_AC3
113};
114
115#endif /*CONFIG_IWL4965_HT */
116
57aab75a
TW		 117/* check contents of special bootstrap uCode SRAM */
118static int iwl4965_verify_bsm(struct iwl_priv *priv)
119{
120 __le32 *image = priv->ucode_boot.v_addr;
121 u32 len = priv->ucode_boot.len;
122 u32 reg;
123 u32 val;
124
125 IWL_DEBUG_INFO("Begin verify bsm\n");
126
127 /* verify BSM SRAM contents */
128 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
129 for (reg = BSM_SRAM_LOWER_BOUND;
130 reg < BSM_SRAM_LOWER_BOUND + len;
131 reg += sizeof(u32), image++) {
132 val = iwl_read_prph(priv, reg);
133 if (val != le32_to_cpu(*image)) {
134 IWL_ERROR("BSM uCode verification failed at "
135 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
136 BSM_SRAM_LOWER_BOUND,
137 reg - BSM_SRAM_LOWER_BOUND, len,
138 val, le32_to_cpu(*image));
139 return -EIO;
140 }
141 }
142
143 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
144
145 return 0;
146}
147
148/**
149 * iwl4965_load_bsm - Load bootstrap instructions
150 *
151 * BSM operation:
152 *
153 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
154 * in special SRAM that does not power down during RFKILL. When powering back
155 * up after power-saving sleeps (or during initial uCode load), the BSM loads
156 * the bootstrap program into the on-board processor, and starts it.
157 *
158 * The bootstrap program loads (via DMA) instructions and data for a new
159 * program from host DRAM locations indicated by the host driver in the
160 * BSM_DRAM_* registers. Once the new program is loaded, it starts
161 * automatically.
162 *
163 * When initializing the NIC, the host driver points the BSM to the
164 * "initialize" uCode image. This uCode sets up some internal data, then
165 * notifies host via "initialize alive" that it is complete.
166 *
167 * The host then replaces the BSM_DRAM_* pointer values to point to the
168 * normal runtime uCode instructions and a backup uCode data cache buffer
169 * (filled initially with starting data values for the on-board processor),
170 * then triggers the "initialize" uCode to load and launch the runtime uCode,
171 * which begins normal operation.
172 *
173 * When doing a power-save shutdown, runtime uCode saves data SRAM into
174 * the backup data cache in DRAM before SRAM is powered down.
175 *
176 * When powering back up, the BSM loads the bootstrap program. This reloads
177 * the runtime uCode instructions and the backup data cache into SRAM,
178 * and re-launches the runtime uCode from where it left off.
179 */
180static int iwl4965_load_bsm(struct iwl_priv *priv)
181{
182 __le32 *image = priv->ucode_boot.v_addr;
183 u32 len = priv->ucode_boot.len;
184 dma_addr_t pinst;
185 dma_addr_t pdata;
186 u32 inst_len;
187 u32 data_len;
188 int i;
189 u32 done;
190 u32 reg_offset;
191 int ret;
192
193 IWL_DEBUG_INFO("Begin load bsm\n");
194
195 /* make sure bootstrap program is no larger than BSM's SRAM size */
196 if (len > IWL_MAX_BSM_SIZE)
197 return -EINVAL;
198
199 /* Tell bootstrap uCode where to find the "Initialize" uCode
200 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
201 * NOTE: iwl4965_initialize_alive_start() will replace these values,
202 * after the "initialize" uCode has run, to point to
203 * runtime/protocol instructions and backup data cache. */
204 pinst = priv->ucode_init.p_addr >> 4;
205 pdata = priv->ucode_init_data.p_addr >> 4;
206 inst_len = priv->ucode_init.len;
207 data_len = priv->ucode_init_data.len;
208
209 ret = iwl_grab_nic_access(priv);
210 if (ret)
211 return ret;
212
213 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
214 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
215 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
216 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
217
218 /* Fill BSM memory with bootstrap instructions */
219 for (reg_offset = BSM_SRAM_LOWER_BOUND;
220 reg_offset < BSM_SRAM_LOWER_BOUND + len;
221 reg_offset += sizeof(u32), image++)
222 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
223
224 ret = iwl4965_verify_bsm(priv);
225 if (ret) {
226 iwl_release_nic_access(priv);
227 return ret;
228 }
229
230 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
231 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
232 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
233 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
234
235 /* Load bootstrap code into instruction SRAM now,
236 * to prepare to load "initialize" uCode */
237 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
238
239 /* Wait for load of bootstrap uCode to finish */
240 for (i = 0; i < 100; i++) {
241 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
242 if (!(done & BSM_WR_CTRL_REG_BIT_START))
243 break;
244 udelay(10);
245 }
246 if (i < 100)
247 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
248 else {
249 IWL_ERROR("BSM write did not complete!\n");
250 return -EIO;
251 }
252
253 /* Enable future boot loads whenever power management unit triggers it
254 * (e.g. when powering back up after power-save shutdown) */
255 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
256
257 iwl_release_nic_access(priv);
258
259 return 0;
260}
261
bf85ea4f
AK		 262static int iwl4965_init_drv(struct iwl_priv *priv)
263{
264 int ret;
265 int i;
266
1ea87396 267 priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
bf85ea4f
AK		 268 priv->retry_rate = 1;
269 priv->ibss_beacon = NULL;
270
271 spin_lock_init(&priv->lock);
272 spin_lock_init(&priv->power_data.lock);
273 spin_lock_init(&priv->sta_lock);
274 spin_lock_init(&priv->hcmd_lock);
275 spin_lock_init(&priv->lq_mngr.lock);
276
059ff826
TW		 277 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
278 sizeof(struct iwl4965_shared),
279 &priv->shared_phys);
280
281 if (!priv->shared_virt) {
282 ret = -ENOMEM;
283 goto err;
284 }
285
286 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
287
288
bf85ea4f
AK		 289 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
290 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
291
292 INIT_LIST_HEAD(&priv->free_frames);
293
294 mutex_init(&priv->mutex);
295
296 /* Clear the driver's (not device's) station table */
297 iwlcore_clear_stations_table(priv);
298
299 priv->data_retry_limit = -1;
300 priv->ieee_channels = NULL;
301 priv->ieee_rates = NULL;
302 priv->band = IEEE80211_BAND_2GHZ;
303
304 priv->iw_mode = IEEE80211_IF_TYPE_STA;
305
306 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
307 priv->valid_antenna = 0x7; /* assume all 3 connected */
308 priv->ps_mode = IWL_MIMO_PS_NONE;
309
310 /* Choose which receivers/antennas to use */
311 iwl4965_set_rxon_chain(priv);
312
313 iwlcore_reset_qos(priv);
314
315 priv->qos_data.qos_active = 0;
316 priv->qos_data.qos_cap.val = 0;
317
318 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
319
320 priv->rates_mask = IWL_RATES_MASK;
321 /* If power management is turned on, default to AC mode */
322 priv->power_mode = IWL_POWER_AC;
323 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
324
325 ret = iwl_init_channel_map(priv);
326 if (ret) {
327 IWL_ERROR("initializing regulatory failed: %d\n", ret);
328 goto err;
329 }
330
331 ret = iwl4965_init_geos(priv);
332 if (ret) {
333 IWL_ERROR("initializing geos failed: %d\n", ret);
334 goto err_free_channel_map;
335 }
336
bf85ea4f
AK		 337 ret = ieee80211_register_hw(priv->hw);
338 if (ret) {
339 IWL_ERROR("Failed to register network device (error %d)\n",
340 ret);
341 goto err_free_geos;
342 }
343
344 priv->hw->conf.beacon_int = 100;
345 priv->mac80211_registered = 1;
346
347 return 0;
348
349err_free_geos:
350 iwl4965_free_geos(priv);
351err_free_channel_map:
352 iwl_free_channel_map(priv);
353err:
354 return ret;
355}
356
b481de9c
ZY		 357static int is_fat_channel(__le32 rxon_flags)
358{
359 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
360 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
361}
362
c79dd5b5 363static u8 is_single_stream(struct iwl_priv *priv)
b481de9c 364{
c8b0e6e1 365#ifdef CONFIG_IWL4965_HT
fd105e79
RR		 366 if (!priv->current_ht_config.is_ht ||
367 (priv->current_ht_config.supp_mcs_set[1] == 0) ||
b481de9c
ZY		 368 (priv->ps_mode == IWL_MIMO_PS_STATIC))
369 return 1;
370#else
371 return 1;
c8b0e6e1 372#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 373 return 0;
374}
375
17744ff6
TW		 376int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
377{
378 int idx = 0;
379
380 /* 4965 HT rate format */
381 if (rate_n_flags & RATE_MCS_HT_MSK) {
382 idx = (rate_n_flags & 0xff);
383
384 if (idx >= IWL_RATE_MIMO_6M_PLCP)
385 idx = idx - IWL_RATE_MIMO_6M_PLCP;
386
387 idx += IWL_FIRST_OFDM_RATE;
388 /* skip 9M not supported in ht*/
389 if (idx >= IWL_RATE_9M_INDEX)
390 idx += 1;
391 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
392 return idx;
393
394 /* 4965 legacy rate format, search for match in table */
395 } else {
396 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
397 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
398 return idx;
399 }
400
401 return -1;
402}
403
4c424e4c
RR		 404/**
405 * translate ucode response to mac80211 tx status control values
406 */
c79dd5b5 407void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
4c424e4c
RR		 408 struct ieee80211_tx_control *control)
409{
410 int rate_index;
411
412 control->antenna_sel_tx =
413 ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_A_POS);
414 if (rate_n_flags & RATE_MCS_HT_MSK)
415 control->flags |= IEEE80211_TXCTL_OFDM_HT;
416 if (rate_n_flags & RATE_MCS_GF_MSK)
417 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
418 if (rate_n_flags & RATE_MCS_FAT_MSK)
419 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
420 if (rate_n_flags & RATE_MCS_DUP_MSK)
421 control->flags |= IEEE80211_TXCTL_DUP_DATA;
422 if (rate_n_flags & RATE_MCS_SGI_MSK)
423 control->flags |= IEEE80211_TXCTL_SHORT_GI;
424 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
425 * IEEE80211_BAND_2GHZ band as it contains all the rates */
426 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
427 if (rate_index == -1)
428 control->tx_rate = NULL;
429 else
430 control->tx_rate =
431 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
432}
17744ff6 433
b481de9c
ZY		 434/*
435 * Determine how many receiver/antenna chains to use.
436 * More provides better reception via diversity. Fewer saves power.
437 * MIMO (dual stream) requires at least 2, but works better with 3.
438 * This does not determine *which* chains to use, just how many.
439 */
c79dd5b5 440static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
b481de9c
ZY		 441 u8 *idle_state, u8 *rx_state)
442{
443 u8 is_single = is_single_stream(priv);
444 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
445
446 /* # of Rx chains to use when expecting MIMO. */
447 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
448 *rx_state = 2;
449 else
450 *rx_state = 3;
451
452 /* # Rx chains when idling and maybe trying to save power */
453 switch (priv->ps_mode) {
454 case IWL_MIMO_PS_STATIC:
455 case IWL_MIMO_PS_DYNAMIC:
456 *idle_state = (is_cam) ? 2 : 1;
457 break;
458 case IWL_MIMO_PS_NONE:
459 *idle_state = (is_cam) ? *rx_state : 1;
460 break;
461 default:
462 *idle_state = 1;
463 break;
464 }
465
466 return 0;
467}
468
c79dd5b5 469int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 470{
471 int rc;
472 unsigned long flags;
473
474 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 475 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 476 if (rc) {
477 spin_unlock_irqrestore(&priv->lock, flags);
478 return rc;
479 }
480
8b6eaea8 481 /* stop Rx DMA */
3395f6e9
TW		 482 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
483 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
b481de9c
ZY		 484 (1 << 24), 1000);
485 if (rc < 0)
486 IWL_ERROR("Can't stop Rx DMA.\n");
487
3395f6e9 488 iwl_release_nic_access(priv);
b481de9c
ZY		 489 spin_unlock_irqrestore(&priv->lock, flags);
490
491 return 0;
492}
493
c79dd5b5 494u8 iwl4965_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c
ZY		 495{
496 int i;
497 int start = 0;
498 int ret = IWL_INVALID_STATION;
499 unsigned long flags;
0795af57 500 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 501
502 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
503 (priv->iw_mode == IEEE80211_IF_TYPE_AP))
504 start = IWL_STA_ID;
505
506 if (is_broadcast_ether_addr(addr))
a4062b8f 507 return priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 508
509 spin_lock_irqsave(&priv->sta_lock, flags);
510 for (i = start; i < priv->hw_setting.max_stations; i++)
511 if ((priv->stations[i].used) &&
512 (!compare_ether_addr
513 (priv->stations[i].sta.sta.addr, addr))) {
514 ret = i;
515 goto out;
516 }
517
a50e2e3f 518 IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
0795af57 519 print_mac(mac, addr), priv->num_stations);
b481de9c
ZY		 520
521 out:
522 spin_unlock_irqrestore(&priv->sta_lock, flags);
523 return ret;
524}
525
c79dd5b5 526static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
b481de9c 527{
d8609652 528 int ret;
b481de9c
ZY		 529 unsigned long flags;
530
531 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 532 ret = iwl_grab_nic_access(priv);
d8609652 533 if (ret) {
b481de9c 534 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 535 return ret;
b481de9c
ZY		 536 }
537
538 if (!pwr_max) {
539 u32 val;
540
d8609652 541 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
b481de9c
ZY		 542 &val);
543
544 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
3395f6e9 545 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 546 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
547 ~APMG_PS_CTRL_MSK_PWR_SRC);
548 } else
3395f6e9 549 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 550 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
551 ~APMG_PS_CTRL_MSK_PWR_SRC);
552
3395f6e9 553 iwl_release_nic_access(priv);
b481de9c
ZY		 554 spin_unlock_irqrestore(&priv->lock, flags);
555
d8609652 556 return ret;
b481de9c
ZY		 557}
558
c79dd5b5 559static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c 560{
059ff826 561 int ret;
b481de9c 562 unsigned long flags;
9ee1ba47 563 unsigned int rb_size;
b481de9c
ZY		 564
565 spin_lock_irqsave(&priv->lock, flags);
059ff826
TW		 566 ret = iwl_grab_nic_access(priv);
567 if (ret) {
b481de9c 568 spin_unlock_irqrestore(&priv->lock, flags);
059ff826 569 return ret;
b481de9c
ZY		 570 }
571
1ea87396 572 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 573 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
574 else
575 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
576
8b6eaea8 577 /* Stop Rx DMA */
3395f6e9 578 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
b481de9c 579
8b6eaea8 580 /* Reset driver's Rx queue write index */
3395f6e9 581 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
8b6eaea8
CB		 582
583 /* Tell device where to find RBD circular buffer in DRAM */
3395f6e9
TW		 584 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
585 rxq->dma_addr >> 8);
b481de9c 586
8b6eaea8 587 /* Tell device where in DRAM to update its Rx status */
3395f6e9 588 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
059ff826
TW		 589 (priv->shared_phys +
590 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
b481de9c 591
8b6eaea8 592 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
3395f6e9
TW		 593 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
594 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
595 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
596 rb_size |
059ff826 597 /* 0x10 << 4 | */
3395f6e9 598 (RX_QUEUE_SIZE_LOG <<
b481de9c
ZY		 599 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
600
601 /*
3395f6e9 602 * iwl_write32(priv,CSR_INT_COAL_REG,0);
b481de9c
ZY		 603 */
604
3395f6e9 605 iwl_release_nic_access(priv);
b481de9c
ZY		 606 spin_unlock_irqrestore(&priv->lock, flags);
607
608 return 0;
609}
610
8b6eaea8 611/* Tell 4965 where to find the "keep warm" buffer */
c79dd5b5 612static int iwl4965_kw_init(struct iwl_priv *priv)
b481de9c
ZY		 613{
614 unsigned long flags;
615 int rc;
616
617 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 618 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 619 if (rc)
620 goto out;
621
3395f6e9 622 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
b481de9c 623 priv->kw.dma_addr >> 4);
3395f6e9 624 iwl_release_nic_access(priv);
b481de9c
ZY		 625out:
626 spin_unlock_irqrestore(&priv->lock, flags);
627 return rc;
628}
629
c79dd5b5 630static int iwl4965_kw_alloc(struct iwl_priv *priv)
b481de9c
ZY		 631{
632 struct pci_dev *dev = priv->pci_dev;
bb8c093b 633 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 634
635 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
636 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
637 if (!kw->v_addr)
638 return -ENOMEM;
639
640 return 0;
641}
642
8b6eaea8
CB		 643/**
644 * iwl4965_kw_free - Free the "keep warm" buffer
645 */
c79dd5b5 646static void iwl4965_kw_free(struct iwl_priv *priv)
b481de9c
ZY		 647{
648 struct pci_dev *dev = priv->pci_dev;
bb8c093b 649 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 650
651 if (kw->v_addr) {
652 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
653 memset(kw, 0, sizeof(*kw));
654 }
655}
656
657/**
658 * iwl4965_txq_ctx_reset - Reset TX queue context
659 * Destroys all DMA structures and initialise them again
660 *
661 * @param priv
662 * @return error code
663 */
c79dd5b5 664static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 665{
666 int rc = 0;
667 int txq_id, slots_num;
668 unsigned long flags;
669
670 iwl4965_kw_free(priv);
671
8b6eaea8 672 /* Free all tx/cmd queues and keep-warm buffer */
bb8c093b 673 iwl4965_hw_txq_ctx_free(priv);
b481de9c 674
8b6eaea8 675 /* Alloc keep-warm buffer */
b481de9c
ZY		 676 rc = iwl4965_kw_alloc(priv);
677 if (rc) {
678 IWL_ERROR("Keep Warm allocation failed");
679 goto error_kw;
680 }
681
682 spin_lock_irqsave(&priv->lock, flags);
683
3395f6e9 684 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 685 if (unlikely(rc)) {
686 IWL_ERROR("TX reset failed");
687 spin_unlock_irqrestore(&priv->lock, flags);
688 goto error_reset;
689 }
690
8b6eaea8 691 /* Turn off all Tx DMA channels */
12a81f60 692 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
3395f6e9 693 iwl_release_nic_access(priv);
b481de9c
ZY		 694 spin_unlock_irqrestore(&priv->lock, flags);
695
8b6eaea8 696 /* Tell 4965 where to find the keep-warm buffer */
b481de9c
ZY		 697 rc = iwl4965_kw_init(priv);
698 if (rc) {
699 IWL_ERROR("kw_init failed\n");
700 goto error_reset;
701 }
702
8b6eaea8
CB		 703 /* Alloc and init all (default 16) Tx queues,
704 * including the command queue (#4) */
b481de9c
ZY		 705 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
706 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
707 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 708 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 709 txq_id);
710 if (rc) {
711 IWL_ERROR("Tx %d queue init failed\n", txq_id);
712 goto error;
713 }
714 }
715
716 return rc;
717
718 error:
bb8c093b 719 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 720 error_reset:
721 iwl4965_kw_free(priv);
722 error_kw:
723 return rc;
724}
725
c79dd5b5 726int iwl4965_hw_nic_init(struct iwl_priv *priv)
b481de9c
ZY		 727{
728 int rc;
729 unsigned long flags;
bb8c093b 730 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 731 u8 rev_id;
732 u32 val;
733 u8 val_link;
734
bb8c093b 735 iwl4965_power_init_handle(priv);
b481de9c
ZY		 736
737 /* nic_init */
738 spin_lock_irqsave(&priv->lock, flags);
739
3395f6e9 740 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 741 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
742
3395f6e9
TW		 743 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
744 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 745 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
746 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
747 if (rc < 0) {
748 spin_unlock_irqrestore(&priv->lock, flags);
749 IWL_DEBUG_INFO("Failed to init the card\n");
750 return rc;
751 }
752
3395f6e9 753 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 754 if (rc) {
755 spin_unlock_irqrestore(&priv->lock, flags);
756 return rc;
757 }
758
3395f6e9 759 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c 760
3395f6e9
TW		 761 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
762 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
763 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c
ZY		 764
765 udelay(20);
766
3395f6e9
TW		 767 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
768 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 769
3395f6e9
TW		 770 iwl_release_nic_access(priv);
771 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
b481de9c
ZY		 772 spin_unlock_irqrestore(&priv->lock, flags);
773
774 /* Determine HW type */
775 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
776 if (rc)
777 return rc;
778
779 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
780
781 iwl4965_nic_set_pwr_src(priv, 1);
782 spin_lock_irqsave(&priv->lock, flags);
783
784 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
785 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
786 /* Enable No Snoop field */
787 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
788 val & ~(1 << 11));
789 }
790
791 spin_unlock_irqrestore(&priv->lock, flags);
792
b481de9c
ZY		 793 if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
794 IWL_ERROR("Older EEPROM detected! Aborting.\n");
795 return -EINVAL;
796 }
797
798 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
799
800 /* disable L1 entry -- workaround for pre-B1 */
801 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
802
803 spin_lock_irqsave(&priv->lock, flags);
804
805 /* set CSR_HW_CONFIG_REG for uCode use */
806
3395f6e9
TW		 807 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
808 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
809 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
810 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 811
3395f6e9 812 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 813 if (rc < 0) {
814 spin_unlock_irqrestore(&priv->lock, flags);
815 IWL_DEBUG_INFO("Failed to init the card\n");
816 return rc;
817 }
818
3395f6e9
TW		 819 iwl_read_prph(priv, APMG_PS_CTRL_REG);
820 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 821 udelay(5);
3395f6e9 822 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 823
3395f6e9 824 iwl_release_nic_access(priv);
b481de9c
ZY		 825 spin_unlock_irqrestore(&priv->lock, flags);
826
bb8c093b 827 iwl4965_hw_card_show_info(priv);
b481de9c
ZY		 828
829 /* end nic_init */
830
831 /* Allocate the RX queue, or reset if it is already allocated */
832 if (!rxq->bd) {
bb8c093b 833 rc = iwl4965_rx_queue_alloc(priv);
b481de9c
ZY		 834 if (rc) {
835 IWL_ERROR("Unable to initialize Rx queue\n");
836 return -ENOMEM;
837 }
838 } else
bb8c093b 839 iwl4965_rx_queue_reset(priv, rxq);
b481de9c 840
bb8c093b 841 iwl4965_rx_replenish(priv);
b481de9c
ZY		 842
843 iwl4965_rx_init(priv, rxq);
844
845 spin_lock_irqsave(&priv->lock, flags);
846
847 rxq->need_update = 1;
bb8c093b 848 iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 849
850 spin_unlock_irqrestore(&priv->lock, flags);
8b6eaea8
CB		 851
852 /* Allocate and init all Tx and Command queues */
b481de9c
ZY		 853 rc = iwl4965_txq_ctx_reset(priv);
854 if (rc)
855 return rc;
856
857 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
858 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
859
860 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
861 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
862
863 set_bit(STATUS_INIT, &priv->status);
864
865 return 0;
866}
867
c79dd5b5 868int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 869{
870 int rc = 0;
871 u32 reg_val;
872 unsigned long flags;
873
874 spin_lock_irqsave(&priv->lock, flags);
875
876 /* set stop master bit */
3395f6e9 877 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 878
3395f6e9 879 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 880
881 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
882 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
883 IWL_DEBUG_INFO("Card in power save, master is already "
884 "stopped\n");
885 else {
3395f6e9 886 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 887 CSR_RESET_REG_FLAG_MASTER_DISABLED,
888 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
889 if (rc < 0) {
890 spin_unlock_irqrestore(&priv->lock, flags);
891 return rc;
892 }
893 }
894
895 spin_unlock_irqrestore(&priv->lock, flags);
896 IWL_DEBUG_INFO("stop master\n");
897
898 return rc;
899}
900
8b6eaea8
CB		 901/**
902 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
903 */
c79dd5b5 904void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c
ZY		 905{
906
907 int txq_id;
908 unsigned long flags;
909
8b6eaea8 910 /* Stop each Tx DMA channel, and wait for it to be idle */
b481de9c
ZY		 911 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
912 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 913 if (iwl_grab_nic_access(priv)) {
b481de9c
ZY		 914 spin_unlock_irqrestore(&priv->lock, flags);
915 continue;
916 }
917
3395f6e9
TW		 918 iwl_write_direct32(priv,
919 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
920 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
921 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
922 (txq_id), 200);
923 iwl_release_nic_access(priv);
b481de9c
ZY		 924 spin_unlock_irqrestore(&priv->lock, flags);
925 }
926
8b6eaea8 927 /* Deallocate memory for all Tx queues */
bb8c093b 928 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 929}
930
c79dd5b5 931int iwl4965_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 932{
933 int rc = 0;
934 unsigned long flags;
935
bb8c093b 936 iwl4965_hw_nic_stop_master(priv);
b481de9c
ZY		 937
938 spin_lock_irqsave(&priv->lock, flags);
939
3395f6e9 940 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 941
942 udelay(10);
943
3395f6e9
TW		 944 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
945 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 946 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
947 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
948
949 udelay(10);
950
3395f6e9 951 rc = iwl_grab_nic_access(priv);
b481de9c 952 if (!rc) {
3395f6e9
TW		 953 iwl_write_prph(priv, APMG_CLK_EN_REG,
954 APMG_CLK_VAL_DMA_CLK_RQT |
955 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 956
957 udelay(10);
958
3395f6e9
TW		 959 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
960 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 961
3395f6e9 962 iwl_release_nic_access(priv);
b481de9c
ZY		 963 }
964
965 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
966 wake_up_interruptible(&priv->wait_command_queue);
967
968 spin_unlock_irqrestore(&priv->lock, flags);
969
970 return rc;
971
972}
973
974#define REG_RECALIB_PERIOD (60)
975
976/**
977 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
978 *
49ea8596 979 * This callback is provided in order to send a statistics request.
b481de9c
ZY		 980 *
981 * This timer function is continually reset to execute within
982 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
983 * was received. We need to ensure we receive the statistics in order
49ea8596 984 * to update the temperature used for calibrating the TXPOWER.
b481de9c
ZY		 985 */
986static void iwl4965_bg_statistics_periodic(unsigned long data)
987{
c79dd5b5 988 struct iwl_priv *priv = (struct iwl_priv *)data;
b481de9c 989
b481de9c
ZY		 990 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
991 return;
992
49ea8596 993 iwl_send_statistics_request(priv, CMD_ASYNC);
b481de9c
ZY		 994}
995
996#define CT_LIMIT_CONST 259
997#define TM_CT_KILL_THRESHOLD 110
998
c79dd5b5 999void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 1000{
bb8c093b 1001 struct iwl4965_ct_kill_config cmd;
b481de9c
ZY		 1002 u32 R1, R2, R3;
1003 u32 temp_th;
1004 u32 crit_temperature;
1005 unsigned long flags;
857485c0 1006 int ret = 0;
b481de9c
ZY		 1007
1008 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1009 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 1010 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1011 spin_unlock_irqrestore(&priv->lock, flags);
1012
1013 if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
1014 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1015 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1016 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1017 } else {
1018 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1019 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1020 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1021 }
1022
1023 temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
1024
1025 crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
1026 cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
857485c0
TW		 1027 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1028 sizeof(cmd), &cmd);
1029 if (ret)
b481de9c
ZY		 1030 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1031 else
1032 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
1033}
1034
c8b0e6e1 1035#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 1036
1037/* "false alarms" are signals that our DSP tries to lock onto,
1038 * but then determines that they are either noise, or transmissions
1039 * from a distant wireless network (also "noise", really) that get
1040 * "stepped on" by stronger transmissions within our own network.
1041 * This algorithm attempts to set a sensitivity level that is high
1042 * enough to receive all of our own network traffic, but not so
1043 * high that our DSP gets too busy trying to lock onto non-network
1044 * activity/noise. */
c79dd5b5 1045static int iwl4965_sens_energy_cck(struct iwl_priv *priv,
b481de9c
ZY		 1046 u32 norm_fa,
1047 u32 rx_enable_time,
1048 struct statistics_general_data *rx_info)
1049{
1050 u32 max_nrg_cck = 0;
1051 int i = 0;
1052 u8 max_silence_rssi = 0;
1053 u32 silence_ref = 0;
1054 u8 silence_rssi_a = 0;
1055 u8 silence_rssi_b = 0;
1056 u8 silence_rssi_c = 0;
1057 u32 val;
1058
1059 /* "false_alarms" values below are cross-multiplications to assess the
1060 * numbers of false alarms within the measured period of actual Rx
1061 * (Rx is off when we're txing), vs the min/max expected false alarms
1062 * (some should be expected if rx is sensitive enough) in a
1063 * hypothetical listening period of 200 time units (TU), 204.8 msec:
1064 *
1065 * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
1066 *
1067 * */
1068 u32 false_alarms = norm_fa * 200 * 1024;
1069 u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
1070 u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
bb8c093b 1071 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1072
1073 data = &(priv->sensitivity_data);
1074
1075 data->nrg_auto_corr_silence_diff = 0;
1076
1077 /* Find max silence rssi among all 3 receivers.
1078 * This is background noise, which may include transmissions from other
1079 * networks, measured during silence before our network's beacon */
1080 silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
8a1b0245 1081 ALL_BAND_FILTER) >> 8);
b481de9c 1082 silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
8a1b0245 1083 ALL_BAND_FILTER) >> 8);
b481de9c 1084 silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
8a1b0245 1085 ALL_BAND_FILTER) >> 8);
b481de9c
ZY		 1086
1087 val = max(silence_rssi_b, silence_rssi_c);
1088 max_silence_rssi = max(silence_rssi_a, (u8) val);
1089
1090 /* Store silence rssi in 20-beacon history table */
1091 data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
1092 data->nrg_silence_idx++;
1093 if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
1094 data->nrg_silence_idx = 0;
1095
1096 /* Find max silence rssi across 20 beacon history */
1097 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
1098 val = data->nrg_silence_rssi[i];
1099 silence_ref = max(silence_ref, val);
1100 }
1101 IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
1102 silence_rssi_a, silence_rssi_b, silence_rssi_c,
1103 silence_ref);
1104
1105 /* Find max rx energy (min value!) among all 3 receivers,
1106 * measured during beacon frame.
1107 * Save it in 10-beacon history table. */
1108 i = data->nrg_energy_idx;
1109 val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
1110 data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
1111
1112 data->nrg_energy_idx++;
1113 if (data->nrg_energy_idx >= 10)
1114 data->nrg_energy_idx = 0;
1115
1116 /* Find min rx energy (max value) across 10 beacon history.
1117 * This is the minimum signal level that we want to receive well.
1118 * Add backoff (margin so we don't miss slightly lower energy frames).
1119 * This establishes an upper bound (min value) for energy threshold. */
1120 max_nrg_cck = data->nrg_value[0];
1121 for (i = 1; i < 10; i++)
1122 max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
1123 max_nrg_cck += 6;
1124
1125 IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
1126 rx_info->beacon_energy_a, rx_info->beacon_energy_b,
1127 rx_info->beacon_energy_c, max_nrg_cck - 6);
1128
1129 /* Count number of consecutive beacons with fewer-than-desired
1130 * false alarms. */
1131 if (false_alarms < min_false_alarms)
1132 data->num_in_cck_no_fa++;
1133 else
1134 data->num_in_cck_no_fa = 0;
1135 IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
1136 data->num_in_cck_no_fa);
1137
1138 /* If we got too many false alarms this time, reduce sensitivity */
1139 if (false_alarms > max_false_alarms) {
1140 IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
1141 false_alarms, max_false_alarms);
1142 IWL_DEBUG_CALIB("... reducing sensitivity\n");
1143 data->nrg_curr_state = IWL_FA_TOO_MANY;
1144
1145 if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
1146 /* Store for "fewer than desired" on later beacon */
1147 data->nrg_silence_ref = silence_ref;
1148
1149 /* increase energy threshold (reduce nrg value)
1150 * to decrease sensitivity */
1151 if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
1152 data->nrg_th_cck = data->nrg_th_cck
1153 - NRG_STEP_CCK;
1154 }
1155
1156 /* increase auto_corr values to decrease sensitivity */
1157 if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
1158 data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
1159 else {
1160 val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
1161 data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
1162 }
1163 val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
1164 data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
1165
1166 /* Else if we got fewer than desired, increase sensitivity */
1167 } else if (false_alarms < min_false_alarms) {
1168 data->nrg_curr_state = IWL_FA_TOO_FEW;
1169
1170 /* Compare silence level with silence level for most recent
1171 * healthy number or too many false alarms */
1172 data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
1173 (s32)silence_ref;
1174
1175 IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
1176 false_alarms, min_false_alarms,
1177 data->nrg_auto_corr_silence_diff);
1178
1179 /* Increase value to increase sensitivity, but only if:
1180 * 1a) previous beacon did *not* have *too many* false alarms
1181 * 1b) AND there's a significant difference in Rx levels
1182 * from a previous beacon with too many, or healthy # FAs
1183 * OR 2) We've seen a lot of beacons (100) with too few
1184 * false alarms */
1185 if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
1186 ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
1187 (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
1188
1189 IWL_DEBUG_CALIB("... increasing sensitivity\n");
1190 /* Increase nrg value to increase sensitivity */
1191 val = data->nrg_th_cck + NRG_STEP_CCK;
1192 data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
1193
1194 /* Decrease auto_corr values to increase sensitivity */
1195 val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
1196 data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
1197
1198 val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
1199 data->auto_corr_cck_mrc =
1200 max((u32)AUTO_CORR_MIN_CCK_MRC, val);
1201
1202 } else
1203 IWL_DEBUG_CALIB("... but not changing sensitivity\n");
1204
1205 /* Else we got a healthy number of false alarms, keep status quo */
1206 } else {
1207 IWL_DEBUG_CALIB(" FA in safe zone\n");
1208 data->nrg_curr_state = IWL_FA_GOOD_RANGE;
1209
1210 /* Store for use in "fewer than desired" with later beacon */
1211 data->nrg_silence_ref = silence_ref;
1212
1213 /* If previous beacon had too many false alarms,
1214 * give it some extra margin by reducing sensitivity again
1215 * (but don't go below measured energy of desired Rx) */
1216 if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
1217 IWL_DEBUG_CALIB("... increasing margin\n");
1218 data->nrg_th_cck -= NRG_MARGIN;
1219 }
1220 }
1221
1222 /* Make sure the energy threshold does not go above the measured
1223 * energy of the desired Rx signals (reduced by backoff margin),
1224 * or else we might start missing Rx frames.
1225 * Lower value is higher energy, so we use max()!
1226 */
1227 data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
1228 IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
1229
1230 data->nrg_prev_state = data->nrg_curr_state;
1231
1232 return 0;
1233}
1234
1235
c79dd5b5 1236static int iwl4965_sens_auto_corr_ofdm(struct iwl_priv *priv,
b481de9c
ZY		 1237 u32 norm_fa,
1238 u32 rx_enable_time)
1239{
1240 u32 val;
1241 u32 false_alarms = norm_fa * 200 * 1024;
1242 u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
1243 u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
bb8c093b 1244 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1245
1246 data = &(priv->sensitivity_data);
1247
1248 /* If we got too many false alarms this time, reduce sensitivity */
1249 if (false_alarms > max_false_alarms) {
1250
1251 IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
1252 false_alarms, max_false_alarms);
1253
1254 val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
1255 data->auto_corr_ofdm =
1256 min((u32)AUTO_CORR_MAX_OFDM, val);
1257
1258 val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
1259 data->auto_corr_ofdm_mrc =
1260 min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
1261
1262 val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
1263 data->auto_corr_ofdm_x1 =
1264 min((u32)AUTO_CORR_MAX_OFDM_X1, val);
1265
1266 val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
1267 data->auto_corr_ofdm_mrc_x1 =
1268 min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
1269 }
1270
1271 /* Else if we got fewer than desired, increase sensitivity */
1272 else if (false_alarms < min_false_alarms) {
1273
1274 IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
1275 false_alarms, min_false_alarms);
1276
1277 val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
1278 data->auto_corr_ofdm =
1279 max((u32)AUTO_CORR_MIN_OFDM, val);
1280
1281 val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
1282 data->auto_corr_ofdm_mrc =
1283 max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
1284
1285 val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
1286 data->auto_corr_ofdm_x1 =
1287 max((u32)AUTO_CORR_MIN_OFDM_X1, val);
1288
1289 val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
1290 data->auto_corr_ofdm_mrc_x1 =
1291 max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
1292 }
1293
1294 else
1295 IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
1296 min_false_alarms, false_alarms, max_false_alarms);
1297
1298 return 0;
1299}
1300
c79dd5b5 1301static int iwl4965_sensitivity_callback(struct iwl_priv *priv,
857485c0 1302 struct iwl_cmd *cmd, struct sk_buff *skb)
b481de9c
ZY		 1303{
1304 /* We didn't cache the SKB; let the caller free it */
1305 return 1;
1306}
1307
1308/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
c79dd5b5 1309static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
b481de9c 1310{
bb8c093b
CH		 1311 struct iwl4965_sensitivity_cmd cmd ;
1312 struct iwl4965_sensitivity_data *data = NULL;
857485c0 1313 struct iwl_host_cmd cmd_out = {
b481de9c 1314 .id = SENSITIVITY_CMD,
bb8c093b 1315 .len = sizeof(struct iwl4965_sensitivity_cmd),
b481de9c
ZY		 1316 .meta.flags = flags,
1317 .data = &cmd,
1318 };
857485c0 1319 int ret;
b481de9c
ZY		 1320
1321 data = &(priv->sensitivity_data);
1322
1323 memset(&cmd, 0, sizeof(cmd));
1324
1325 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
1326 cpu_to_le16((u16)data->auto_corr_ofdm);
1327 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
1328 cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
1329 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
1330 cpu_to_le16((u16)data->auto_corr_ofdm_x1);
1331 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
1332 cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
1333
1334 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
1335 cpu_to_le16((u16)data->auto_corr_cck);
1336 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
1337 cpu_to_le16((u16)data->auto_corr_cck_mrc);
1338
1339 cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
1340 cpu_to_le16((u16)data->nrg_th_cck);
1341 cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
1342 cpu_to_le16((u16)data->nrg_th_ofdm);
1343
1344 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
1345 __constant_cpu_to_le16(190);
1346 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
1347 __constant_cpu_to_le16(390);
1348 cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
1349 __constant_cpu_to_le16(62);
1350
1351 IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
1352 data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
1353 data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
1354 data->nrg_th_ofdm);
1355
1356 IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
1357 data->auto_corr_cck, data->auto_corr_cck_mrc,
1358 data->nrg_th_cck);
1359
f7d09d7c 1360 /* Update uCode's "work" table, and copy it to DSP */
b481de9c
ZY		 1361 cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
1362
1363 if (flags & CMD_ASYNC)
bb8c093b 1364 cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
b481de9c
ZY		 1365
1366 /* Don't send command to uCode if nothing has changed */
1367 if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
1368 sizeof(u16)*HD_TABLE_SIZE)) {
1369 IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
1370 return 0;
1371 }
1372
1373 /* Copy table for comparison next time */
1374 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
1375 sizeof(u16)*HD_TABLE_SIZE);
1376
857485c0
TW		 1377 ret = iwl_send_cmd(priv, &cmd_out);
1378 if (ret)
1379 IWL_ERROR("SENSITIVITY_CMD failed\n");
b481de9c 1380
857485c0 1381 return ret;
b481de9c
ZY		 1382}
1383
c79dd5b5 1384void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
b481de9c 1385{
bb8c093b 1386 struct iwl4965_sensitivity_data *data = NULL;
857485c0
TW		 1387 int i;
1388 int ret = 0;
b481de9c
ZY		 1389
1390 IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
1391
1392 if (force)
1393 memset(&(priv->sensitivity_tbl[0]), 0,
1394 sizeof(u16)*HD_TABLE_SIZE);
1395
1396 /* Clear driver's sensitivity algo data */
1397 data = &(priv->sensitivity_data);
bb8c093b 1398 memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
b481de9c
ZY		 1399
1400 data->num_in_cck_no_fa = 0;
1401 data->nrg_curr_state = IWL_FA_TOO_MANY;
1402 data->nrg_prev_state = IWL_FA_TOO_MANY;
1403 data->nrg_silence_ref = 0;
1404 data->nrg_silence_idx = 0;
1405 data->nrg_energy_idx = 0;
1406
1407 for (i = 0; i < 10; i++)
1408 data->nrg_value[i] = 0;
1409
1410 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
1411 data->nrg_silence_rssi[i] = 0;
1412
1413 data->auto_corr_ofdm = 90;
1414 data->auto_corr_ofdm_mrc = 170;
1415 data->auto_corr_ofdm_x1 = 105;
1416 data->auto_corr_ofdm_mrc_x1 = 220;
1417 data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
1418 data->auto_corr_cck_mrc = 200;
1419 data->nrg_th_cck = 100;
1420 data->nrg_th_ofdm = 100;
1421
1422 data->last_bad_plcp_cnt_ofdm = 0;
1423 data->last_fa_cnt_ofdm = 0;
1424 data->last_bad_plcp_cnt_cck = 0;
1425 data->last_fa_cnt_cck = 0;
1426
1427 /* Clear prior Sensitivity command data to force send to uCode */
1428 if (force)
1429 memset(&(priv->sensitivity_tbl[0]), 0,
1430 sizeof(u16)*HD_TABLE_SIZE);
1431
857485c0
TW		 1432 ret |= iwl4965_sensitivity_write(priv, flags);
1433 IWL_DEBUG_CALIB("<<return 0x%X\n", ret);
b481de9c
ZY		 1434
1435 return;
1436}
1437
1438
1439/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1440 * Called after every association, but this runs only once!
1441 * ... once chain noise is calibrated the first time, it's good forever. */
c79dd5b5 1442void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 1443{
bb8c093b 1444 struct iwl4965_chain_noise_data *data = NULL;
b481de9c
ZY		 1445
1446 data = &(priv->chain_noise_data);
3109ece1 1447 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 1448 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1449
1450 memset(&cmd, 0, sizeof(cmd));
1451 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1452 cmd.diff_gain_a = 0;
1453 cmd.diff_gain_b = 0;
1454 cmd.diff_gain_c = 0;
e5472978
TW		 1455 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
1456 sizeof(cmd), &cmd, NULL);
b481de9c
ZY		 1457 msleep(4);
1458 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1459 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1460 }
1461 return;
1462}
1463
1464/*
1465 * Accumulate 20 beacons of signal and noise statistics for each of
1466 * 3 receivers/antennas/rx-chains, then figure out:
1467 * 1) Which antennas are connected.
1468 * 2) Differential rx gain settings to balance the 3 receivers.
1469 */
c79dd5b5 1470static void iwl4965_noise_calibration(struct iwl_priv *priv,
bb8c093b 1471 struct iwl4965_notif_statistics *stat_resp)
b481de9c 1472{
bb8c093b 1473 struct iwl4965_chain_noise_data *data = NULL;
857485c0 1474 int ret = 0;
b481de9c
ZY		 1475
1476 u32 chain_noise_a;
1477 u32 chain_noise_b;
1478 u32 chain_noise_c;
1479 u32 chain_sig_a;
1480 u32 chain_sig_b;
1481 u32 chain_sig_c;
1482 u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1483 u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1484 u32 max_average_sig;
1485 u16 max_average_sig_antenna_i;
1486 u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
1487 u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
1488 u16 i = 0;
1489 u16 chan_num = INITIALIZATION_VALUE;
1490 u32 band = INITIALIZATION_VALUE;
1491 u32 active_chains = 0;
1492 unsigned long flags;
1493 struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
1494
1495 data = &(priv->chain_noise_data);
1496
1497 /* Accumulate just the first 20 beacons after the first association,
1498 * then we're done forever. */
1499 if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
1500 if (data->state == IWL_CHAIN_NOISE_ALIVE)
1501 IWL_DEBUG_CALIB("Wait for noise calib reset\n");
1502 return;
1503 }
1504
1505 spin_lock_irqsave(&priv->lock, flags);
1506 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1507 IWL_DEBUG_CALIB(" << Interference data unavailable\n");
1508 spin_unlock_irqrestore(&priv->lock, flags);
1509 return;
1510 }
1511
1512 band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
1513 chan_num = le16_to_cpu(priv->staging_rxon.channel);
1514
1515 /* Make sure we accumulate data for just the associated channel
1516 * (even if scanning). */
1517 if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
1518 ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
1519 (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
1520 IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
1521 chan_num, band);
1522 spin_unlock_irqrestore(&priv->lock, flags);
1523 return;
1524 }
1525
1526 /* Accumulate beacon statistics values across 20 beacons */
1527 chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
1528 IN_BAND_FILTER;
1529 chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
1530 IN_BAND_FILTER;
1531 chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
1532 IN_BAND_FILTER;
1533
1534 chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
1535 chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
1536 chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
1537
1538 spin_unlock_irqrestore(&priv->lock, flags);
1539
1540 data->beacon_count++;
1541
1542 data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
1543 data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
1544 data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
1545
1546 data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
1547 data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
1548 data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
1549
1550 IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
1551 data->beacon_count);
1552 IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
1553 chain_sig_a, chain_sig_b, chain_sig_c);
1554 IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
1555 chain_noise_a, chain_noise_b, chain_noise_c);
1556
1557 /* If this is the 20th beacon, determine:
1558 * 1) Disconnected antennas (using signal strengths)
1559 * 2) Differential gain (using silence noise) to balance receivers */
1560 if (data->beacon_count == CAL_NUM_OF_BEACONS) {
1561
1562 /* Analyze signal for disconnected antenna */
1563 average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
1564 average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
1565 average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
1566
1567 if (average_sig[0] >= average_sig[1]) {
1568 max_average_sig = average_sig[0];
1569 max_average_sig_antenna_i = 0;
1570 active_chains = (1 << max_average_sig_antenna_i);
1571 } else {
1572 max_average_sig = average_sig[1];
1573 max_average_sig_antenna_i = 1;
1574 active_chains = (1 << max_average_sig_antenna_i);
1575 }
1576
1577 if (average_sig[2] >= max_average_sig) {
1578 max_average_sig = average_sig[2];
1579 max_average_sig_antenna_i = 2;
1580 active_chains = (1 << max_average_sig_antenna_i);
1581 }
1582
1583 IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
1584 average_sig[0], average_sig[1], average_sig[2]);
1585 IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
1586 max_average_sig, max_average_sig_antenna_i);
1587
1588 /* Compare signal strengths for all 3 receivers. */
1589 for (i = 0; i < NUM_RX_CHAINS; i++) {
1590 if (i != max_average_sig_antenna_i) {
1591 s32 rssi_delta = (max_average_sig -
1592 average_sig[i]);
1593
1594 /* If signal is very weak, compared with
1595 * strongest, mark it as disconnected. */
1596 if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
1597 data->disconn_array[i] = 1;
1598 else
1599 active_chains |= (1 << i);
1600 IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
1601 "disconn_array[i] = %d\n",
1602 i, rssi_delta, data->disconn_array[i]);
1603 }
1604 }
1605
1606 /*If both chains A & B are disconnected -
1607 * connect B and leave A as is */
1608 if (data->disconn_array[CHAIN_A] &&
1609 data->disconn_array[CHAIN_B]) {
1610 data->disconn_array[CHAIN_B] = 0;
1611 active_chains |= (1 << CHAIN_B);
1612 IWL_DEBUG_CALIB("both A & B chains are disconnected! "
1613 "W/A - declare B as connected\n");
1614 }
1615
1616 IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
1617 active_chains);
1618
1619 /* Save for use within RXON, TX, SCAN commands, etc. */
1620 priv->valid_antenna = active_chains;
1621
1622 /* Analyze noise for rx balance */
1623 average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
1624 average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
1625 average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
1626
1627 for (i = 0; i < NUM_RX_CHAINS; i++) {
1628 if (!(data->disconn_array[i]) &&
1629 (average_noise[i] <= min_average_noise)) {
1630 /* This means that chain i is active and has
1631 * lower noise values so far: */
1632 min_average_noise = average_noise[i];
1633 min_average_noise_antenna_i = i;
1634 }
1635 }
1636
1637 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1638
1639 IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
1640 average_noise[0], average_noise[1],
1641 average_noise[2]);
1642
1643 IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
1644 min_average_noise, min_average_noise_antenna_i);
1645
1646 for (i = 0; i < NUM_RX_CHAINS; i++) {
1647 s32 delta_g = 0;
1648
1649 if (!(data->disconn_array[i]) &&
1650 (data->delta_gain_code[i] ==
1651 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1652 delta_g = average_noise[i] - min_average_noise;
1653 data->delta_gain_code[i] = (u8)((delta_g *
1654 10) / 15);
1655 if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
1656 data->delta_gain_code[i])
1657 data->delta_gain_code[i] =
1658 CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
1659
1660 data->delta_gain_code[i] =
1661 (data->delta_gain_code[i] | (1 << 2));
1662 } else
1663 data->delta_gain_code[i] = 0;
1664 }
1665 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1666 data->delta_gain_code[0],
1667 data->delta_gain_code[1],
1668 data->delta_gain_code[2]);
1669
1670 /* Differential gain gets sent to uCode only once */
1671 if (!data->radio_write) {
bb8c093b 1672 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1673 data->radio_write = 1;
1674
1675 memset(&cmd, 0, sizeof(cmd));
1676 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1677 cmd.diff_gain_a = data->delta_gain_code[0];
1678 cmd.diff_gain_b = data->delta_gain_code[1];
1679 cmd.diff_gain_c = data->delta_gain_code[2];
857485c0 1680 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
b481de9c 1681 sizeof(cmd), &cmd);
857485c0 1682 if (ret)
b481de9c
ZY		 1683 IWL_DEBUG_CALIB("fail sending cmd "
1684 "REPLY_PHY_CALIBRATION_CMD \n");
1685
1686 /* TODO we might want recalculate
1687 * rx_chain in rxon cmd */
1688
1689 /* Mark so we run this algo only once! */
1690 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1691 }
1692 data->chain_noise_a = 0;
1693 data->chain_noise_b = 0;
1694 data->chain_noise_c = 0;
1695 data->chain_signal_a = 0;
1696 data->chain_signal_b = 0;
1697 data->chain_signal_c = 0;
1698 data->beacon_count = 0;
1699 }
1700 return;
1701}
1702
c79dd5b5 1703static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
bb8c093b 1704 struct iwl4965_notif_statistics *resp)
b481de9c 1705{
b481de9c
ZY		 1706 u32 rx_enable_time;
1707 u32 fa_cck;
1708 u32 fa_ofdm;
1709 u32 bad_plcp_cck;
1710 u32 bad_plcp_ofdm;
1711 u32 norm_fa_ofdm;
1712 u32 norm_fa_cck;
bb8c093b 1713 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1714 struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
1715 struct statistics_rx *statistics = &(resp->rx);
1716 unsigned long flags;
1717 struct statistics_general_data statis;
857485c0 1718 int ret;
b481de9c
ZY		 1719
1720 data = &(priv->sensitivity_data);
1721
3109ece1 1722 if (!iwl_is_associated(priv)) {
b481de9c
ZY		 1723 IWL_DEBUG_CALIB("<< - not associated\n");
1724 return;
1725 }
1726
1727 spin_lock_irqsave(&priv->lock, flags);
1728 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1729 IWL_DEBUG_CALIB("<< invalid data.\n");
1730 spin_unlock_irqrestore(&priv->lock, flags);
1731 return;
1732 }
1733
1734 /* Extract Statistics: */
1735 rx_enable_time = le32_to_cpu(rx_info->channel_load);
1736 fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
1737 fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
1738 bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
1739 bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
1740
1741 statis.beacon_silence_rssi_a =
1742 le32_to_cpu(statistics->general.beacon_silence_rssi_a);
1743 statis.beacon_silence_rssi_b =
1744 le32_to_cpu(statistics->general.beacon_silence_rssi_b);
1745 statis.beacon_silence_rssi_c =
1746 le32_to_cpu(statistics->general.beacon_silence_rssi_c);
1747 statis.beacon_energy_a =
1748 le32_to_cpu(statistics->general.beacon_energy_a);
1749 statis.beacon_energy_b =
1750 le32_to_cpu(statistics->general.beacon_energy_b);
1751 statis.beacon_energy_c =
1752 le32_to_cpu(statistics->general.beacon_energy_c);
1753
1754 spin_unlock_irqrestore(&priv->lock, flags);
1755
1756 IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
1757
1758 if (!rx_enable_time) {
1759 IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
1760 return;
1761 }
1762
1763 /* These statistics increase monotonically, and do not reset
1764 * at each beacon. Calculate difference from last value, or just
1765 * use the new statistics value if it has reset or wrapped around. */
1766 if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
1767 data->last_bad_plcp_cnt_cck = bad_plcp_cck;
1768 else {
1769 bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
1770 data->last_bad_plcp_cnt_cck += bad_plcp_cck;
1771 }
1772
1773 if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
1774 data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
1775 else {
1776 bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
1777 data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
1778 }
1779
1780 if (data->last_fa_cnt_ofdm > fa_ofdm)
1781 data->last_fa_cnt_ofdm = fa_ofdm;
1782 else {
1783 fa_ofdm -= data->last_fa_cnt_ofdm;
1784 data->last_fa_cnt_ofdm += fa_ofdm;
1785 }
1786
1787 if (data->last_fa_cnt_cck > fa_cck)
1788 data->last_fa_cnt_cck = fa_cck;
1789 else {
1790 fa_cck -= data->last_fa_cnt_cck;
1791 data->last_fa_cnt_cck += fa_cck;
1792 }
1793
1794 /* Total aborted signal locks */
1795 norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
1796 norm_fa_cck = fa_cck + bad_plcp_cck;
1797
1798 IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
1799 bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
1800
1801 iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
1802 iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
857485c0 1803 ret = iwl4965_sensitivity_write(priv, CMD_ASYNC);
b481de9c
ZY		 1804
1805 return;
1806}
1807
1808static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1809{
c79dd5b5 1810 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1811 sensitivity_work);
1812
1813 mutex_lock(&priv->mutex);
1814
1815 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1816 test_bit(STATUS_SCANNING, &priv->status)) {
1817 mutex_unlock(&priv->mutex);
1818 return;
1819 }
1820
1821 if (priv->start_calib) {
1822 iwl4965_noise_calibration(priv, &priv->statistics);
1823
1824 if (priv->sensitivity_data.state ==
1825 IWL_SENS_CALIB_NEED_REINIT) {
1826 iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
1827 priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
1828 } else
1829 iwl4965_sensitivity_calibration(priv,
1830 &priv->statistics);
1831 }
1832
1833 mutex_unlock(&priv->mutex);
1834 return;
1835}
c8b0e6e1 1836#endif /*CONFIG_IWL4965_SENSITIVITY*/
b481de9c
ZY		 1837
1838static void iwl4965_bg_txpower_work(struct work_struct *work)
1839{
c79dd5b5 1840 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1841 txpower_work);
1842
1843 /* If a scan happened to start before we got here
1844 * then just return; the statistics notification will
1845 * kick off another scheduled work to compensate for
1846 * any temperature delta we missed here. */
1847 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1848 test_bit(STATUS_SCANNING, &priv->status))
1849 return;
1850
1851 mutex_lock(&priv->mutex);
1852
1853 /* Regardless of if we are assocaited, we must reconfigure the
1854 * TX power since frames can be sent on non-radar channels while
1855 * not associated */
bb8c093b 1856 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 1857
1858 /* Update last_temperature to keep is_calib_needed from running
1859 * when it isn't needed... */
1860 priv->last_temperature = priv->temperature;
1861
1862 mutex_unlock(&priv->mutex);
1863}
1864
1865/*
1866 * Acquire priv->lock before calling this function !
1867 */
c79dd5b5 1868static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 1869{
3395f6e9 1870 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 1871 (index & 0xff) | (txq_id << 8));
12a81f60 1872 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 1873}
1874
8b6eaea8
CB		 1875/**
1876 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1877 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1878 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1879 *
1880 * NOTE: Acquire priv->lock before calling this function !
b481de9c 1881 */
c79dd5b5 1882static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
bb8c093b 1883 struct iwl4965_tx_queue *txq,
b481de9c
ZY		 1884 int tx_fifo_id, int scd_retry)
1885{
1886 int txq_id = txq->q.id;
8b6eaea8
CB		 1887
1888 /* Find out whether to activate Tx queue */
b481de9c
ZY		 1889 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1890
8b6eaea8 1891 /* Set up and activate */
12a81f60 1892 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
b481de9c
ZY		 1893 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1894 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1895 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1896 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1897 SCD_QUEUE_STTS_REG_MSK);
1898
1899 txq->sched_retry = scd_retry;
1900
1901 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 1902 active ? "Activate" : "Deactivate",
b481de9c
ZY		 1903 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1904}
1905
1906static const u16 default_queue_to_tx_fifo[] = {
1907 IWL_TX_FIFO_AC3,
1908 IWL_TX_FIFO_AC2,
1909 IWL_TX_FIFO_AC1,
1910 IWL_TX_FIFO_AC0,
1911 IWL_CMD_FIFO_NUM,
1912 IWL_TX_FIFO_HCCA_1,
1913 IWL_TX_FIFO_HCCA_2
1914};
1915
c79dd5b5 1916static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1917{
1918 set_bit(txq_id, &priv->txq_ctx_active_msk);
1919}
1920
c79dd5b5 1921static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1922{
1923 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1924}
1925
c79dd5b5 1926int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 1927{
1928 u32 a;
1929 int i = 0;
1930 unsigned long flags;
857485c0 1931 int ret;
b481de9c
ZY		 1932
1933 spin_lock_irqsave(&priv->lock, flags);
1934
c8b0e6e1 1935#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c 1936 memset(&(priv->sensitivity_data), 0,
bb8c093b 1937 sizeof(struct iwl4965_sensitivity_data));
b481de9c 1938 memset(&(priv->chain_noise_data), 0,
bb8c093b 1939 sizeof(struct iwl4965_chain_noise_data));
b481de9c
ZY		 1940 for (i = 0; i < NUM_RX_CHAINS; i++)
1941 priv->chain_noise_data.delta_gain_code[i] =
1942 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
c8b0e6e1 1943#endif /* CONFIG_IWL4965_SENSITIVITY*/
3395f6e9 1944 ret = iwl_grab_nic_access(priv);
857485c0 1945 if (ret) {
b481de9c 1946 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 1947 return ret;
b481de9c
ZY		 1948 }
1949
8b6eaea8 1950 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 1951 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
b481de9c
ZY		 1952 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1953 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 1954 iwl_write_targ_mem(priv, a, 0);
b481de9c 1955 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 1956 iwl_write_targ_mem(priv, a, 0);
b481de9c 1957 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
3395f6e9 1958 iwl_write_targ_mem(priv, a, 0);
b481de9c 1959
8b6eaea8 1960 /* Tel 4965 where to find Tx byte count tables */
12a81f60 1961 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 1962 (priv->shared_phys +
bb8c093b 1963 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 1964
1965 /* Disable chain mode for all queues */
12a81f60 1966 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 1967
8b6eaea8 1968 /* Initialize each Tx queue (including the command queue) */
b481de9c 1969 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
8b6eaea8
CB		 1970
1971 /* TFD circular buffer read/write indexes */
12a81f60 1972 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 1973 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 1974
1975 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 1976 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1977 SCD_CONTEXT_QUEUE_OFFSET(i),
1978 (SCD_WIN_SIZE <<
1979 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1980 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 1981
1982 /* Frame limit */
3395f6e9 1983 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1984 SCD_CONTEXT_QUEUE_OFFSET(i) +
1985 sizeof(u32),
1986 (SCD_FRAME_LIMIT <<
1987 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1988 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1989
1990 }
12a81f60 1991 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
b481de9c
ZY		 1992 (1 << priv->hw_setting.max_txq_num) - 1);
1993
8b6eaea8 1994 /* Activate all Tx DMA/FIFO channels */
12a81f60 1995 iwl_write_prph(priv, IWL49_SCD_TXFACT,
b481de9c
ZY		 1996 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1997
1998 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 1999
2000 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 2001 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
2002 int ac = default_queue_to_tx_fifo[i];
2003 iwl4965_txq_ctx_activate(priv, i);
2004 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
2005 }
2006
3395f6e9 2007 iwl_release_nic_access(priv);
b481de9c
ZY		 2008 spin_unlock_irqrestore(&priv->lock, flags);
2009
49ea8596
EG		 2010 /* Ask for statistics now, the uCode will send statistics notification
2011 * periodically after association */
2012 iwl_send_statistics_request(priv, CMD_ASYNC);
857485c0 2013 return ret;
b481de9c
ZY		 2014}
2015
8b6eaea8
CB		 2016/**
2017 * iwl4965_hw_set_hw_setting
2018 *
2019 * Called when initializing driver
2020 */
c79dd5b5 2021int iwl4965_hw_set_hw_setting(struct iwl_priv *priv)
b481de9c 2022{
316c30d9 2023
1ea87396
AK		 2024 if ((priv->cfg->mod_params->num_of_queues > IWL_MAX_NUM_QUEUES) ||
2025 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9
AK		 2026 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
2027 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
059ff826 2028 return -EINVAL;
316c30d9 2029 }
b481de9c 2030
1ea87396 2031 priv->hw_setting.max_txq_num = priv->cfg->mod_params->num_of_queues;
bb8c093b 2032 priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
b481de9c
ZY		 2033 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2034 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 2035 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 2036 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
2037 else
2038 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
2039 priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
b481de9c
ZY		 2040 priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
2041 priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822
TW		 2042
2043 priv->hw_setting.tx_ant_num = 2;
2044
059ff826 2045 return 0;
b481de9c
ZY		 2046}
2047
2048/**
bb8c093b 2049 * iwl4965_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 2050 *
2051 * Destroy all TX DMA queues and structures
2052 */
c79dd5b5 2053void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 2054{
2055 int txq_id;
2056
2057 /* Tx queues */
2058 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
bb8c093b 2059 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c 2060
8b6eaea8 2061 /* Keep-warm buffer */
b481de9c
ZY		 2062 iwl4965_kw_free(priv);
2063}
2064
2065/**
8b6eaea8 2066 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
b481de9c 2067 *
8b6eaea8
CB		 2068 * Does NOT advance any TFD circular buffer read/write indexes
2069 * Does NOT free the TFD itself (which is within circular buffer)
b481de9c 2070 */
c79dd5b5 2071int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 2072{
bb8c093b
CH		 2073 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
2074 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 2075 struct pci_dev *dev = priv->pci_dev;
2076 int i;
2077 int counter = 0;
2078 int index, is_odd;
2079
8b6eaea8 2080 /* Host command buffers stay mapped in memory, nothing to clean */
b481de9c 2081 if (txq->q.id == IWL_CMD_QUEUE_NUM)
b481de9c
ZY		 2082 return 0;
2083
8b6eaea8 2084 /* Sanity check on number of chunks */
b481de9c
ZY		 2085 counter = IWL_GET_BITS(*bd, num_tbs);
2086 if (counter > MAX_NUM_OF_TBS) {
2087 IWL_ERROR("Too many chunks: %i\n", counter);
2088 /* @todo issue fatal error, it is quite serious situation */
2089 return 0;
2090 }
2091
8b6eaea8
CB		 2092 /* Unmap chunks, if any.
2093 * TFD info for odd chunks is different format than for even chunks. */
b481de9c
ZY		 2094 for (i = 0; i < counter; i++) {
2095 index = i / 2;
2096 is_odd = i & 0x1;
2097
2098 if (is_odd)
2099 pci_unmap_single(
2100 dev,
2101 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
2102 (IWL_GET_BITS(bd->pa[index],
2103 tb2_addr_hi20) << 16),
2104 IWL_GET_BITS(bd->pa[index], tb2_len),
2105 PCI_DMA_TODEVICE);
2106
2107 else if (i > 0)
2108 pci_unmap_single(dev,
2109 le32_to_cpu(bd->pa[index].tb1_addr),
2110 IWL_GET_BITS(bd->pa[index], tb1_len),
2111 PCI_DMA_TODEVICE);
2112
8b6eaea8 2113 /* Free SKB, if any, for this chunk */
fc4b6853
TW		 2114 if (txq->txb[txq->q.read_ptr].skb[i]) {
2115 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
b481de9c
ZY		 2116
2117 dev_kfree_skb(skb);
fc4b6853 2118 txq->txb[txq->q.read_ptr].skb[i] = NULL;
b481de9c
ZY		 2119 }
2120 }
2121 return 0;
2122}
2123
c79dd5b5 2124int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 2125{
bb8c093b 2126 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
b481de9c
ZY		 2127 return -EINVAL;
2128}
2129
2130static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
2131{
2132 s32 sign = 1;
2133
2134 if (num < 0) {
2135 sign = -sign;
2136 num = -num;
2137 }
2138 if (denom < 0) {
2139 sign = -sign;
2140 denom = -denom;
2141 }
2142 *res = 1;
2143 *res = ((num * 2 + denom) / (denom * 2)) * sign;
2144
2145 return 1;
2146}
2147
8b6eaea8
CB		 2148/**
2149 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
2150 *
2151 * Determines power supply voltage compensation for txpower calculations.
2152 * Returns number of 1/2-dB steps to subtract from gain table index,
2153 * to compensate for difference between power supply voltage during
2154 * factory measurements, vs. current power supply voltage.
2155 *
2156 * Voltage indication is higher for lower voltage.
2157 * Lower voltage requires more gain (lower gain table index).
2158 */
b481de9c
ZY		 2159static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
2160 s32 current_voltage)
2161{
2162 s32 comp = 0;
2163
2164 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
2165 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
2166 return 0;
2167
2168 iwl4965_math_div_round(current_voltage - eeprom_voltage,
2169 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
2170
2171 if (current_voltage > eeprom_voltage)
2172 comp *= 2;
2173 if ((comp < -2) || (comp > 2))
2174 comp = 0;
2175
2176 return comp;
2177}
2178
bf85ea4f 2179static const struct iwl_channel_info *
c79dd5b5 2180iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
8318d78a 2181 enum ieee80211_band band, u16 channel)
b481de9c 2182{
bf85ea4f 2183 const struct iwl_channel_info *ch_info;
b481de9c 2184
8622e705 2185 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 2186
2187 if (!is_channel_valid(ch_info))
2188 return NULL;
2189
2190 return ch_info;
2191}
2192
2193static s32 iwl4965_get_tx_atten_grp(u16 channel)
2194{
2195 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
2196 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
2197 return CALIB_CH_GROUP_5;
2198
2199 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
2200 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
2201 return CALIB_CH_GROUP_1;
2202
2203 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
2204 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
2205 return CALIB_CH_GROUP_2;
2206
2207 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
2208 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
2209 return CALIB_CH_GROUP_3;
2210
2211 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
2212 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
2213 return CALIB_CH_GROUP_4;
2214
2215 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
2216 return -1;
2217}
2218
c79dd5b5 2219static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 2220{
2221 s32 b = -1;
2222
2223 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
2224 if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
2225 continue;
2226
2227 if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
2228 && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
2229 break;
2230 }
2231
2232 return b;
2233}
2234
2235static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
2236{
2237 s32 val;
2238
2239 if (x2 == x1)
2240 return y1;
2241 else {
2242 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
2243 return val + y2;
2244 }
2245}
2246
8b6eaea8
CB		 2247/**
2248 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
2249 *
2250 * Interpolates factory measurements from the two sample channels within a
2251 * sub-band, to apply to channel of interest. Interpolation is proportional to
2252 * differences in channel frequencies, which is proportional to differences
2253 * in channel number.
2254 */
c79dd5b5 2255static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
bb8c093b 2256 struct iwl4965_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 2257{
2258 s32 s = -1;
2259 u32 c;
2260 u32 m;
bb8c093b
CH		 2261 const struct iwl4965_eeprom_calib_measure *m1;
2262 const struct iwl4965_eeprom_calib_measure *m2;
2263 struct iwl4965_eeprom_calib_measure *omeas;
b481de9c
ZY		 2264 u32 ch_i1;
2265 u32 ch_i2;
2266
2267 s = iwl4965_get_sub_band(priv, channel);
2268 if (s >= EEPROM_TX_POWER_BANDS) {
2269 IWL_ERROR("Tx Power can not find channel %d ", channel);
2270 return -1;
2271 }
2272
2273 ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
2274 ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
2275 chan_info->ch_num = (u8) channel;
2276
2277 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
2278 channel, s, ch_i1, ch_i2);
2279
2280 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
2281 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
2282 m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
2283 measurements[c][m]);
2284 m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
2285 measurements[c][m]);
2286 omeas = &(chan_info->measurements[c][m]);
2287
2288 omeas->actual_pow =
2289 (u8) iwl4965_interpolate_value(channel, ch_i1,
2290 m1->actual_pow,
2291 ch_i2,
2292 m2->actual_pow);
2293 omeas->gain_idx =
2294 (u8) iwl4965_interpolate_value(channel, ch_i1,
2295 m1->gain_idx, ch_i2,
2296 m2->gain_idx);
2297 omeas->temperature =
2298 (u8) iwl4965_interpolate_value(channel, ch_i1,
2299 m1->temperature,
2300 ch_i2,
2301 m2->temperature);
2302 omeas->pa_det =
2303 (s8) iwl4965_interpolate_value(channel, ch_i1,
2304 m1->pa_det, ch_i2,
2305 m2->pa_det);
2306
2307 IWL_DEBUG_TXPOWER
2308 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
2309 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
2310 IWL_DEBUG_TXPOWER
2311 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
2312 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
2313 IWL_DEBUG_TXPOWER
2314 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
2315 m1->pa_det, m2->pa_det, omeas->pa_det);
2316 IWL_DEBUG_TXPOWER
2317 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
2318 m1->temperature, m2->temperature,
2319 omeas->temperature);
2320 }
2321 }
2322
2323 return 0;
2324}
2325
2326/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
2327 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
2328static s32 back_off_table[] = {
2329 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
2330 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
2331 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
2332 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
2333 10 /* CCK */
2334};
2335
2336/* Thermal compensation values for txpower for various frequency ranges ...
2337 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 2338static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 2339 s32 degrees_per_05db_a;
2340 s32 degrees_per_05db_a_denom;
2341} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
2342 {9, 2}, /* group 0 5.2, ch 34-43 */
2343 {4, 1}, /* group 1 5.2, ch 44-70 */
2344 {4, 1}, /* group 2 5.2, ch 71-124 */
2345 {4, 1}, /* group 3 5.2, ch 125-200 */
2346 {3, 1} /* group 4 2.4, ch all */
2347};
2348
2349static s32 get_min_power_index(s32 rate_power_index, u32 band)
2350{
2351 if (!band) {
2352 if ((rate_power_index & 7) <= 4)
2353 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
2354 }
2355 return MIN_TX_GAIN_INDEX;
2356}
2357
2358struct gain_entry {
2359 u8 dsp;
2360 u8 radio;
2361};
2362
2363static const struct gain_entry gain_table[2][108] = {
2364 /* 5.2GHz power gain index table */
2365 {
2366 {123, 0x3F}, /* highest txpower */
2367 {117, 0x3F},
2368 {110, 0x3F},
2369 {104, 0x3F},
2370 {98, 0x3F},
2371 {110, 0x3E},
2372 {104, 0x3E},
2373 {98, 0x3E},
2374 {110, 0x3D},
2375 {104, 0x3D},
2376 {98, 0x3D},
2377 {110, 0x3C},
2378 {104, 0x3C},
2379 {98, 0x3C},
2380 {110, 0x3B},
2381 {104, 0x3B},
2382 {98, 0x3B},
2383 {110, 0x3A},
2384 {104, 0x3A},
2385 {98, 0x3A},
2386 {110, 0x39},
2387 {104, 0x39},
2388 {98, 0x39},
2389 {110, 0x38},
2390 {104, 0x38},
2391 {98, 0x38},
2392 {110, 0x37},
2393 {104, 0x37},
2394 {98, 0x37},
2395 {110, 0x36},
2396 {104, 0x36},
2397 {98, 0x36},
2398 {110, 0x35},
2399 {104, 0x35},
2400 {98, 0x35},
2401 {110, 0x34},
2402 {104, 0x34},
2403 {98, 0x34},
2404 {110, 0x33},
2405 {104, 0x33},
2406 {98, 0x33},
2407 {110, 0x32},
2408 {104, 0x32},
2409 {98, 0x32},
2410 {110, 0x31},
2411 {104, 0x31},
2412 {98, 0x31},
2413 {110, 0x30},
2414 {104, 0x30},
2415 {98, 0x30},
2416 {110, 0x25},
2417 {104, 0x25},
2418 {98, 0x25},
2419 {110, 0x24},
2420 {104, 0x24},
2421 {98, 0x24},
2422 {110, 0x23},
2423 {104, 0x23},
2424 {98, 0x23},
2425 {110, 0x22},
2426 {104, 0x18},
2427 {98, 0x18},
2428 {110, 0x17},
2429 {104, 0x17},
2430 {98, 0x17},
2431 {110, 0x16},
2432 {104, 0x16},
2433 {98, 0x16},
2434 {110, 0x15},
2435 {104, 0x15},
2436 {98, 0x15},
2437 {110, 0x14},
2438 {104, 0x14},
2439 {98, 0x14},
2440 {110, 0x13},
2441 {104, 0x13},
2442 {98, 0x13},
2443 {110, 0x12},
2444 {104, 0x08},
2445 {98, 0x08},
2446 {110, 0x07},
2447 {104, 0x07},
2448 {98, 0x07},
2449 {110, 0x06},
2450 {104, 0x06},
2451 {98, 0x06},
2452 {110, 0x05},
2453 {104, 0x05},
2454 {98, 0x05},
2455 {110, 0x04},
2456 {104, 0x04},
2457 {98, 0x04},
2458 {110, 0x03},
2459 {104, 0x03},
2460 {98, 0x03},
2461 {110, 0x02},
2462 {104, 0x02},
2463 {98, 0x02},
2464 {110, 0x01},
2465 {104, 0x01},
2466 {98, 0x01},
2467 {110, 0x00},
2468 {104, 0x00},
2469 {98, 0x00},
2470 {93, 0x00},
2471 {88, 0x00},
2472 {83, 0x00},
2473 {78, 0x00},
2474 },
2475 /* 2.4GHz power gain index table */
2476 {
2477 {110, 0x3f}, /* highest txpower */
2478 {104, 0x3f},
2479 {98, 0x3f},
2480 {110, 0x3e},
2481 {104, 0x3e},
2482 {98, 0x3e},
2483 {110, 0x3d},
2484 {104, 0x3d},
2485 {98, 0x3d},
2486 {110, 0x3c},
2487 {104, 0x3c},
2488 {98, 0x3c},
2489 {110, 0x3b},
2490 {104, 0x3b},
2491 {98, 0x3b},
2492 {110, 0x3a},
2493 {104, 0x3a},
2494 {98, 0x3a},
2495 {110, 0x39},
2496 {104, 0x39},
2497 {98, 0x39},
2498 {110, 0x38},
2499 {104, 0x38},
2500 {98, 0x38},
2501 {110, 0x37},
2502 {104, 0x37},
2503 {98, 0x37},
2504 {110, 0x36},
2505 {104, 0x36},
2506 {98, 0x36},
2507 {110, 0x35},
2508 {104, 0x35},
2509 {98, 0x35},
2510 {110, 0x34},
2511 {104, 0x34},
2512 {98, 0x34},
2513 {110, 0x33},
2514 {104, 0x33},
2515 {98, 0x33},
2516 {110, 0x32},
2517 {104, 0x32},
2518 {98, 0x32},
2519 {110, 0x31},
2520 {104, 0x31},
2521 {98, 0x31},
2522 {110, 0x30},
2523 {104, 0x30},
2524 {98, 0x30},
2525 {110, 0x6},
2526 {104, 0x6},
2527 {98, 0x6},
2528 {110, 0x5},
2529 {104, 0x5},
2530 {98, 0x5},
2531 {110, 0x4},
2532 {104, 0x4},
2533 {98, 0x4},
2534 {110, 0x3},
2535 {104, 0x3},
2536 {98, 0x3},
2537 {110, 0x2},
2538 {104, 0x2},
2539 {98, 0x2},
2540 {110, 0x1},
2541 {104, 0x1},
2542 {98, 0x1},
2543 {110, 0x0},
2544 {104, 0x0},
2545 {98, 0x0},
2546 {97, 0},
2547 {96, 0},
2548 {95, 0},
2549 {94, 0},
2550 {93, 0},
2551 {92, 0},
2552 {91, 0},
2553 {90, 0},
2554 {89, 0},
2555 {88, 0},
2556 {87, 0},
2557 {86, 0},
2558 {85, 0},
2559 {84, 0},
2560 {83, 0},
2561 {82, 0},
2562 {81, 0},
2563 {80, 0},
2564 {79, 0},
2565 {78, 0},
2566 {77, 0},
2567 {76, 0},
2568 {75, 0},
2569 {74, 0},
2570 {73, 0},
2571 {72, 0},
2572 {71, 0},
2573 {70, 0},
2574 {69, 0},
2575 {68, 0},
2576 {67, 0},
2577 {66, 0},
2578 {65, 0},
2579 {64, 0},
2580 {63, 0},
2581 {62, 0},
2582 {61, 0},
2583 {60, 0},
2584 {59, 0},
2585 }
2586};
2587
c79dd5b5 2588static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 2589 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 2590 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 2591{
2592 u8 saturation_power;
2593 s32 target_power;
2594 s32 user_target_power;
2595 s32 power_limit;
2596 s32 current_temp;
2597 s32 reg_limit;
2598 s32 current_regulatory;
2599 s32 txatten_grp = CALIB_CH_GROUP_MAX;
2600 int i;
2601 int c;
bf85ea4f 2602 const struct iwl_channel_info *ch_info = NULL;
bb8c093b
CH		 2603 struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
2604 const struct iwl4965_eeprom_calib_measure *measurement;
b481de9c
ZY		 2605 s16 voltage;
2606 s32 init_voltage;
2607 s32 voltage_compensation;
2608 s32 degrees_per_05db_num;
2609 s32 degrees_per_05db_denom;
2610 s32 factory_temp;
2611 s32 temperature_comp[2];
2612 s32 factory_gain_index[2];
2613 s32 factory_actual_pwr[2];
2614 s32 power_index;
2615
2616 /* Sanity check requested level (dBm) */
2617 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
2618 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
2619 priv->user_txpower_limit);
2620 return -EINVAL;
2621 }
2622 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
2623 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
2624 priv->user_txpower_limit);
2625 return -EINVAL;
2626 }
2627
2628 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
2629 * are used for indexing into txpower table) */
2630 user_target_power = 2 * priv->user_txpower_limit;
2631
2632 /* Get current (RXON) channel, band, width */
2633 ch_info =
8318d78a 2634 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
b481de9c
ZY		 2635
2636 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
2637 is_fat);
2638
2639 if (!ch_info)
2640 return -EINVAL;
2641
2642 /* get txatten group, used to select 1) thermal txpower adjustment
2643 * and 2) mimo txpower balance between Tx chains. */
2644 txatten_grp = iwl4965_get_tx_atten_grp(channel);
2645 if (txatten_grp < 0)
2646 return -EINVAL;
2647
2648 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
2649 channel, txatten_grp);
2650
2651 if (is_fat) {
2652 if (ctrl_chan_high)
2653 channel -= 2;
2654 else
2655 channel += 2;
2656 }
2657
2658 /* hardware txpower limits ...
2659 * saturation (clipping distortion) txpowers are in half-dBm */
2660 if (band)
2661 saturation_power = priv->eeprom.calib_info.saturation_power24;
2662 else
2663 saturation_power = priv->eeprom.calib_info.saturation_power52;
2664
2665 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
2666 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
2667 if (band)
2668 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
2669 else
2670 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
2671 }
2672
2673 /* regulatory txpower limits ... reg_limit values are in half-dBm,
2674 * max_power_avg values are in dBm, convert * 2 */
2675 if (is_fat)
2676 reg_limit = ch_info->fat_max_power_avg * 2;
2677 else
2678 reg_limit = ch_info->max_power_avg * 2;
2679
2680 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2681 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2682 if (band)
2683 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2684 else
2685 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2686 }
2687
2688 /* Interpolate txpower calibration values for this channel,
2689 * based on factory calibration tests on spaced channels. */
2690 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2691
2692 /* calculate tx gain adjustment based on power supply voltage */
2693 voltage = priv->eeprom.calib_info.voltage;
2694 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2695 voltage_compensation =
2696 iwl4965_get_voltage_compensation(voltage, init_voltage);
2697
2698 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2699 init_voltage,
2700 voltage, voltage_compensation);
2701
2702 /* get current temperature (Celsius) */
2703 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2704 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2705 current_temp = KELVIN_TO_CELSIUS(current_temp);
2706
2707 /* select thermal txpower adjustment params, based on channel group
2708 * (same frequency group used for mimo txatten adjustment) */
2709 degrees_per_05db_num =
2710 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2711 degrees_per_05db_denom =
2712 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2713
2714 /* get per-chain txpower values from factory measurements */
2715 for (c = 0; c < 2; c++) {
2716 measurement = &ch_eeprom_info.measurements[c][1];
2717
2718 /* txgain adjustment (in half-dB steps) based on difference
2719 * between factory and current temperature */
2720 factory_temp = measurement->temperature;
2721 iwl4965_math_div_round((current_temp - factory_temp) *
2722 degrees_per_05db_denom,
2723 degrees_per_05db_num,
2724 &temperature_comp[c]);
2725
2726 factory_gain_index[c] = measurement->gain_idx;
2727 factory_actual_pwr[c] = measurement->actual_pow;
2728
2729 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2730 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2731 "curr tmp %d, comp %d steps\n",
2732 factory_temp, current_temp,
2733 temperature_comp[c]);
2734
2735 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2736 factory_gain_index[c],
2737 factory_actual_pwr[c]);
2738 }
2739
2740 /* for each of 33 bit-rates (including 1 for CCK) */
2741 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2742 u8 is_mimo_rate;
bb8c093b 2743 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 2744
2745 /* for mimo, reduce each chain's txpower by half
2746 * (3dB, 6 steps), so total output power is regulatory
2747 * compliant. */
2748 if (i & 0x8) {
2749 current_regulatory = reg_limit -
2750 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2751 is_mimo_rate = 1;
2752 } else {
2753 current_regulatory = reg_limit;
2754 is_mimo_rate = 0;
2755 }
2756
2757 /* find txpower limit, either hardware or regulatory */
2758 power_limit = saturation_power - back_off_table[i];
2759 if (power_limit > current_regulatory)
2760 power_limit = current_regulatory;
2761
2762 /* reduce user's txpower request if necessary
2763 * for this rate on this channel */
2764 target_power = user_target_power;
2765 if (target_power > power_limit)
2766 target_power = power_limit;
2767
2768 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2769 i, saturation_power - back_off_table[i],
2770 current_regulatory, user_target_power,
2771 target_power);
2772
2773 /* for each of 2 Tx chains (radio transmitters) */
2774 for (c = 0; c < 2; c++) {
2775 s32 atten_value;
2776
2777 if (is_mimo_rate)
2778 atten_value =
2779 (s32)le32_to_cpu(priv->card_alive_init.
2780 tx_atten[txatten_grp][c]);
2781 else
2782 atten_value = 0;
2783
2784 /* calculate index; higher index means lower txpower */
2785 power_index = (u8) (factory_gain_index[c] -
2786 (target_power -
2787 factory_actual_pwr[c]) -
2788 temperature_comp[c] -
2789 voltage_compensation +
2790 atten_value);
2791
2792/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2793 power_index); */
2794
2795 if (power_index < get_min_power_index(i, band))
2796 power_index = get_min_power_index(i, band);
2797
2798 /* adjust 5 GHz index to support negative indexes */
2799 if (!band)
2800 power_index += 9;
2801
2802 /* CCK, rate 32, reduce txpower for CCK */
2803 if (i == POWER_TABLE_CCK_ENTRY)
2804 power_index +=
2805 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2806
2807 /* stay within the table! */
2808 if (power_index > 107) {
2809 IWL_WARNING("txpower index %d > 107\n",
2810 power_index);
2811 power_index = 107;
2812 }
2813 if (power_index < 0) {
2814 IWL_WARNING("txpower index %d < 0\n",
2815 power_index);
2816 power_index = 0;
2817 }
2818
2819 /* fill txpower command for this rate/chain */
2820 tx_power.s.radio_tx_gain[c] =
2821 gain_table[band][power_index].radio;
2822 tx_power.s.dsp_predis_atten[c] =
2823 gain_table[band][power_index].dsp;
2824
2825 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2826 "gain 0x%02x dsp %d\n",
2827 c, atten_value, power_index,
2828 tx_power.s.radio_tx_gain[c],
2829 tx_power.s.dsp_predis_atten[c]);
2830 }/* for each chain */
2831
2832 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2833
2834 }/* for each rate */
2835
2836 return 0;
2837}
2838
2839/**
bb8c093b 2840 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
b481de9c
ZY		 2841 *
2842 * Uses the active RXON for channel, band, and characteristics (fat, high)
2843 * The power limit is taken from priv->user_txpower_limit.
2844 */
c79dd5b5 2845int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 2846{
bb8c093b 2847 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 2848 int ret;
b481de9c
ZY		 2849 u8 band = 0;
2850 u8 is_fat = 0;
2851 u8 ctrl_chan_high = 0;
2852
2853 if (test_bit(STATUS_SCANNING, &priv->status)) {
2854 /* If this gets hit a lot, switch it to a BUG() and catch
2855 * the stack trace to find out who is calling this during
2856 * a scan. */
2857 IWL_WARNING("TX Power requested while scanning!\n");
2858 return -EAGAIN;
2859 }
2860
8318d78a 2861 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 2862
2863 is_fat = is_fat_channel(priv->active_rxon.flags);
2864
2865 if (is_fat &&
2866 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2867 ctrl_chan_high = 1;
2868
2869 cmd.band = band;
2870 cmd.channel = priv->active_rxon.channel;
2871
857485c0 2872 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 2873 le16_to_cpu(priv->active_rxon.channel),
2874 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 2875 if (ret)
2876 goto out;
b481de9c 2877
857485c0
TW		 2878 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2879
2880out:
2881 return ret;
b481de9c
ZY		 2882}
2883
c79dd5b5 2884int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2885{
2886 int rc;
2887 u8 band = 0;
2888 u8 is_fat = 0;
2889 u8 ctrl_chan_high = 0;
bb8c093b 2890 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 2891 const struct iwl_channel_info *ch_info;
b481de9c 2892
8318d78a 2893 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 2894
8622e705 2895 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 2896
2897 is_fat = is_fat_channel(priv->staging_rxon.flags);
2898
2899 if (is_fat &&
2900 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2901 ctrl_chan_high = 1;
2902
2903 cmd.band = band;
2904 cmd.expect_beacon = 0;
2905 cmd.channel = cpu_to_le16(channel);
2906 cmd.rxon_flags = priv->active_rxon.flags;
2907 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2908 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2909 if (ch_info)
2910 cmd.expect_beacon = is_channel_radar(ch_info);
2911 else
2912 cmd.expect_beacon = 1;
2913
2914 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2915 ctrl_chan_high, &cmd.tx_power);
2916 if (rc) {
2917 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2918 return rc;
2919 }
2920
857485c0 2921 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 2922 return rc;
2923}
2924
2925#define RTS_HCCA_RETRY_LIMIT 3
2926#define RTS_DFAULT_RETRY_LIMIT 60
2927
c79dd5b5 2928void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
857485c0 2929 struct iwl_cmd *cmd,
b481de9c
ZY		 2930 struct ieee80211_tx_control *ctrl,
2931 struct ieee80211_hdr *hdr, int sta_id,
2932 int is_hcca)
2933{
87e4f7df 2934 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
b481de9c
ZY		 2935 u8 rts_retry_limit = 0;
2936 u8 data_retry_limit = 0;
b481de9c 2937 u16 fc = le16_to_cpu(hdr->frame_control);
87e4f7df
TW		 2938 u8 rate_plcp;
2939 u16 rate_flags = 0;
8318d78a 2940 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c 2941
87e4f7df 2942 rate_plcp = iwl4965_rates[rate_idx].plcp;
b481de9c
ZY		 2943
2944 rts_retry_limit = (is_hcca) ?
2945 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2946
87e4f7df
TW		 2947 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2948 rate_flags |= RATE_MCS_CCK_MSK;
2949
2950
b481de9c
ZY		 2951 if (ieee80211_is_probe_response(fc)) {
2952 data_retry_limit = 3;
2953 if (data_retry_limit < rts_retry_limit)
2954 rts_retry_limit = data_retry_limit;
2955 } else
2956 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2957
2958 if (priv->data_retry_limit != -1)
2959 data_retry_limit = priv->data_retry_limit;
2960
87e4f7df
TW		 2961
2962 if (ieee80211_is_data(fc)) {
2963 tx->initial_rate_index = 0;
2964 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2965 } else {
b481de9c
ZY		 2966 switch (fc & IEEE80211_FCTL_STYPE) {
2967 case IEEE80211_STYPE_AUTH:
2968 case IEEE80211_STYPE_DEAUTH:
2969 case IEEE80211_STYPE_ASSOC_REQ:
2970 case IEEE80211_STYPE_REASSOC_REQ:
87e4f7df
TW		 2971 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2972 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2973 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
b481de9c
ZY		 2974 }
2975 break;
2976 default:
2977 break;
2978 }
87e4f7df
TW		 2979
2980 /* Alternate between antenna A and B for successive frames */
2981 if (priv->use_ant_b_for_management_frame) {
2982 priv->use_ant_b_for_management_frame = 0;
2983 rate_flags |= RATE_MCS_ANT_B_MSK;
2984 } else {
2985 priv->use_ant_b_for_management_frame = 1;
2986 rate_flags |= RATE_MCS_ANT_A_MSK;
2987 }
b481de9c
ZY		 2988 }
2989
87e4f7df
TW		 2990 tx->rts_retry_limit = rts_retry_limit;
2991 tx->data_retry_limit = data_retry_limit;
2992 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
b481de9c
ZY		 2993}
2994
c79dd5b5 2995int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2996{
059ff826
TW		 2997 struct iwl4965_shared *s = priv->shared_virt;
2998 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 2999}
3000
c79dd5b5 3001int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 3002{
3003 return priv->temperature;
3004}
3005
c79dd5b5 3006unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 3007 struct iwl4965_frame *frame, u8 rate)
b481de9c 3008{
bb8c093b 3009 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 3010 unsigned int frame_size;
3011
3012 tx_beacon_cmd = &frame->u.beacon;
3013 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3014
a4062b8f 3015 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 3016 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
3017
bb8c093b 3018 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 3019 tx_beacon_cmd->frame,
bb8c093b 3020 iwl4965_broadcast_addr,
b481de9c
ZY		 3021 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
3022
3023 BUG_ON(frame_size > MAX_MPDU_SIZE);
3024 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
3025
3026 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
3027 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 3028 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 3029 else
3030 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 3031 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 3032
3033 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
3034 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
3035 return (sizeof(*tx_beacon_cmd) + frame_size);
3036}
3037
8b6eaea8
CB		 3038/*
3039 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
3040 * given Tx queue, and enable the DMA channel used for that queue.
3041 *
3042 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3043 * channels supported in hardware.
3044 */
c79dd5b5 3045int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c
ZY		 3046{
3047 int rc;
3048 unsigned long flags;
3049 int txq_id = txq->q.id;
3050
3051 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 3052 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3053 if (rc) {
3054 spin_unlock_irqrestore(&priv->lock, flags);
3055 return rc;
3056 }
3057
8b6eaea8 3058 /* Circular buffer (TFD queue in DRAM) physical base address */
3395f6e9 3059 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
b481de9c 3060 txq->q.dma_addr >> 8);
8b6eaea8
CB		 3061
3062 /* Enable DMA channel, using same id as for TFD queue */
3395f6e9 3063 iwl_write_direct32(
b481de9c
ZY		 3064 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
3065 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
3066 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
3395f6e9 3067 iwl_release_nic_access(priv);
b481de9c
ZY		 3068 spin_unlock_irqrestore(&priv->lock, flags);
3069
3070 return 0;
3071}
3072
c79dd5b5 3073int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 3074 dma_addr_t addr, u16 len)
3075{
3076 int index, is_odd;
bb8c093b 3077 struct iwl4965_tfd_frame *tfd = ptr;
b481de9c
ZY		 3078 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
3079
8b6eaea8 3080 /* Each TFD can point to a maximum 20 Tx buffers */
b481de9c
ZY		 3081 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
3082 IWL_ERROR("Error can not send more than %d chunks\n",
3083 MAX_NUM_OF_TBS);
3084 return -EINVAL;
3085 }
3086
3087 index = num_tbs / 2;
3088 is_odd = num_tbs & 0x1;
3089
3090 if (!is_odd) {
3091 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
3092 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
6a218f6f 3093 iwl_get_dma_hi_address(addr));
b481de9c
ZY		 3094 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
3095 } else {
3096 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
3097 (u32) (addr & 0xffff));
3098 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
3099 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
3100 }
3101
3102 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
3103
3104 return 0;
3105}
3106
c79dd5b5 3107static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
b481de9c
ZY		 3108{
3109 u16 hw_version = priv->eeprom.board_revision_4965;
3110
3111 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
3112 ((hw_version >> 8) & 0x0F),
3113 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
3114
3115 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
3116 priv->eeprom.board_pba_number_4965);
3117}
3118
3119#define IWL_TX_CRC_SIZE 4
3120#define IWL_TX_DELIMITER_SIZE 4
3121
8b6eaea8 3122/**
e2a722eb 3123 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 3124 */
e2a722eb
TW		 3125static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
3126 struct iwl4965_tx_queue *txq,
3127 u16 byte_cnt)
b481de9c
ZY		 3128{
3129 int len;
3130 int txq_id = txq->q.id;
059ff826 3131 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 3132
b481de9c
ZY		 3133 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
3134
8b6eaea8 3135 /* Set up byte count within first 256 entries */
b481de9c 3136 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 3137 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 3138
8b6eaea8 3139 /* If within first 64 entries, duplicate at end */
fc4b6853 3140 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
b481de9c 3141 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 3142 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 3143 byte_cnt, len);
b481de9c
ZY		 3144}
3145
8b6eaea8
CB		 3146/**
3147 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
3148 *
3149 * Selects how many and which Rx receivers/antennas/chains to use.
3150 * This should not be used for scan command ... it puts data in wrong place.
3151 */
c79dd5b5 3152void iwl4965_set_rxon_chain(struct iwl_priv *priv)
b481de9c
ZY		 3153{
3154 u8 is_single = is_single_stream(priv);
3155 u8 idle_state, rx_state;
3156
3157 priv->staging_rxon.rx_chain = 0;
3158 rx_state = idle_state = 3;
3159
3160 /* Tell uCode which antennas are actually connected.
3161 * Before first association, we assume all antennas are connected.
3162 * Just after first association, iwl4965_noise_calibration()
3163 * checks which antennas actually *are* connected. */
3164 priv->staging_rxon.rx_chain |=
3165 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
3166
3167 /* How many receivers should we use? */
3168 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
3169 priv->staging_rxon.rx_chain |=
3170 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
3171 priv->staging_rxon.rx_chain |=
3172 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
3173
3174 if (!is_single && (rx_state >= 2) &&
3175 !test_bit(STATUS_POWER_PMI, &priv->status))
3176 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
3177 else
3178 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
3179
3180 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
3181}
3182
b481de9c
ZY		 3183/**
3184 * sign_extend - Sign extend a value using specified bit as sign-bit
3185 *
3186 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
3187 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
3188 *
3189 * @param oper value to sign extend
3190 * @param index 0 based bit index (0<=index<32) to sign bit
3191 */
3192static s32 sign_extend(u32 oper, int index)
3193{
3194 u8 shift = 31 - index;
3195
3196 return (s32)(oper << shift) >> shift;
3197}
3198
3199/**
3200 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
3201 * @statistics: Provides the temperature reading from the uCode
3202 *
3203 * A return of <0 indicates bogus data in the statistics
3204 */
c79dd5b5 3205int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 3206{
3207 s32 temperature;
3208 s32 vt;
3209 s32 R1, R2, R3;
3210 u32 R4;
3211
3212 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
3213 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
3214 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
3215 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
3216 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
3217 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
3218 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
3219 } else {
3220 IWL_DEBUG_TEMP("Running temperature calibration\n");
3221 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
3222 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
3223 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
3224 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
3225 }
3226
3227 /*
8b6eaea8 3228 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 3229 *
3230 * NOTE If we haven't received a statistics notification yet
3231 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 3232 * "initialize" ALIVE response.
3233 */
b481de9c
ZY		 3234 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
3235 vt = sign_extend(R4, 23);
3236 else
3237 vt = sign_extend(
3238 le32_to_cpu(priv->statistics.general.temperature), 23);
3239
3240 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
3241 R1, R2, R3, vt);
3242
3243 if (R3 == R1) {
3244 IWL_ERROR("Calibration conflict R1 == R3\n");
3245 return -1;
3246 }
3247
3248 /* Calculate temperature in degrees Kelvin, adjust by 97%.
3249 * Add offset to center the adjustment around 0 degrees Centigrade. */
3250 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
3251 temperature /= (R3 - R1);
3252 temperature = (temperature * 97) / 100 +
3253 TEMPERATURE_CALIB_KELVIN_OFFSET;
3254
3255 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
3256 KELVIN_TO_CELSIUS(temperature));
3257
3258 return temperature;
3259}
3260
3261/* Adjust Txpower only if temperature variance is greater than threshold. */
3262#define IWL_TEMPERATURE_THRESHOLD 3
3263
3264/**
3265 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
3266 *
3267 * If the temperature changed has changed sufficiently, then a recalibration
3268 * is needed.
3269 *
3270 * Assumes caller will replace priv->last_temperature once calibration
3271 * executed.
3272 */
c79dd5b5 3273static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 3274{
3275 int temp_diff;
3276
3277 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
3278 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
3279 return 0;
3280 }
3281
3282 temp_diff = priv->temperature - priv->last_temperature;
3283
3284 /* get absolute value */
3285 if (temp_diff < 0) {
3286 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
3287 temp_diff = -temp_diff;
3288 } else if (temp_diff == 0)
3289 IWL_DEBUG_POWER("Same temp, \n");
3290 else
3291 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
3292
3293 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
3294 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
3295 return 0;
3296 }
3297
3298 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
3299
3300 return 1;
3301}
3302
3303/* Calculate noise level, based on measurements during network silence just
3304 * before arriving beacon. This measurement can be done only if we know
3305 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 3306static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 3307{
3308 struct statistics_rx_non_phy *rx_info
3309 = &(priv->statistics.rx.general);
3310 int num_active_rx = 0;
3311 int total_silence = 0;
3312 int bcn_silence_a =
3313 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
3314 int bcn_silence_b =
3315 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
3316 int bcn_silence_c =
3317 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
3318
3319 if (bcn_silence_a) {
3320 total_silence += bcn_silence_a;
3321 num_active_rx++;
3322 }
3323 if (bcn_silence_b) {
3324 total_silence += bcn_silence_b;
3325 num_active_rx++;
3326 }
3327 if (bcn_silence_c) {
3328 total_silence += bcn_silence_c;
3329 num_active_rx++;
3330 }
3331
3332 /* Average among active antennas */
3333 if (num_active_rx)
3334 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
3335 else
3336 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3337
3338 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
3339 bcn_silence_a, bcn_silence_b, bcn_silence_c,
3340 priv->last_rx_noise);
3341}
3342
c79dd5b5 3343void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3344{
bb8c093b 3345 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3346 int change;
3347 s32 temp;
3348
3349 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
3350 (int)sizeof(priv->statistics), pkt->len);
3351
3352 change = ((priv->statistics.general.temperature !=
3353 pkt->u.stats.general.temperature) ||
3354 ((priv->statistics.flag &
3355 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
3356 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
3357
3358 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
3359
3360 set_bit(STATUS_STATISTICS, &priv->status);
3361
3362 /* Reschedule the statistics timer to occur in
3363 * REG_RECALIB_PERIOD seconds to ensure we get a
3364 * thermal update even if the uCode doesn't give
3365 * us one */
3366 mod_timer(&priv->statistics_periodic, jiffies +
3367 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
3368
3369 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3370 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
3371 iwl4965_rx_calc_noise(priv);
c8b0e6e1 3372#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 3373 queue_work(priv->workqueue, &priv->sensitivity_work);
3374#endif
3375 }
3376
ab53d8af
MA		 3377 iwl_leds_background(priv);
3378
b481de9c
ZY		 3379 /* If the hardware hasn't reported a change in
3380 * temperature then don't bother computing a
3381 * calibrated temperature value */
3382 if (!change)
3383 return;
3384
3385 temp = iwl4965_get_temperature(priv);
3386 if (temp < 0)
3387 return;
3388
3389 if (priv->temperature != temp) {
3390 if (priv->temperature)
3391 IWL_DEBUG_TEMP("Temperature changed "
3392 "from %dC to %dC\n",
3393 KELVIN_TO_CELSIUS(priv->temperature),
3394 KELVIN_TO_CELSIUS(temp));
3395 else
3396 IWL_DEBUG_TEMP("Temperature "
3397 "initialized to %dC\n",
3398 KELVIN_TO_CELSIUS(temp));
3399 }
3400
3401 priv->temperature = temp;
3402 set_bit(STATUS_TEMPERATURE, &priv->status);
3403
3404 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3405 iwl4965_is_temp_calib_needed(priv))
3406 queue_work(priv->workqueue, &priv->txpower_work);
3407}
3408
c79dd5b5 3409static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 3410 struct sk_buff *skb,
3411 struct iwl4965_rx_phy_res *rx_start,
3412 struct ieee80211_rx_status *stats,
3413 u32 ampdu_status)
3414{
3415 s8 signal = stats->ssi;
3416 s8 noise = 0;
8318d78a 3417 int rate = stats->rate_idx;
12342c47 3418 u64 tsf = stats->mactime;
a0b484fe 3419 __le16 antenna;
12342c47
ZY		 3420 __le16 phy_flags_hw = rx_start->phy_flags;
3421 struct iwl4965_rt_rx_hdr {
3422 struct ieee80211_radiotap_header rt_hdr;
3423 __le64 rt_tsf; /* TSF */
3424 u8 rt_flags; /* radiotap packet flags */
3425 u8 rt_rate; /* rate in 500kb/s */
3426 __le16 rt_channelMHz; /* channel in MHz */
3427 __le16 rt_chbitmask; /* channel bitfield */
3428 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
3429 s8 rt_dbmnoise;
3430 u8 rt_antenna; /* antenna number */
3431 } __attribute__ ((packed)) *iwl4965_rt;
3432
3433 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
3434 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
3435 if (net_ratelimit())
3436 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 3437 "radiotap head [%zd]\n",
12342c47
ZY		 3438 skb_headroom(skb), sizeof(*iwl4965_rt));
3439 return;
3440 }
3441
3442 /* put radiotap header in front of 802.11 header and data */
3443 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
3444
3445 /* initialise radiotap header */
3446 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
3447 iwl4965_rt->rt_hdr.it_pad = 0;
3448
3449 /* total header + data */
3450 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
3451 &iwl4965_rt->rt_hdr.it_len);
3452
3453 /* Indicate all the fields we add to the radiotap header */
3454 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
3455 (1 << IEEE80211_RADIOTAP_FLAGS) |
3456 (1 << IEEE80211_RADIOTAP_RATE) |
3457 (1 << IEEE80211_RADIOTAP_CHANNEL) |
3458 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
3459 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
3460 (1 << IEEE80211_RADIOTAP_ANTENNA)),
3461 &iwl4965_rt->rt_hdr.it_present);
3462
3463 /* Zero the flags, we'll add to them as we go */
3464 iwl4965_rt->rt_flags = 0;
3465
3466 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
3467
3468 iwl4965_rt->rt_dbmsignal = signal;
3469 iwl4965_rt->rt_dbmnoise = noise;
3470
3471 /* Convert the channel frequency and set the flags */
3472 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
3473 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
3474 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3475 IEEE80211_CHAN_5GHZ),
3476 &iwl4965_rt->rt_chbitmask);
3477 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
3478 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
3479 IEEE80211_CHAN_2GHZ),
3480 &iwl4965_rt->rt_chbitmask);
3481 else /* 802.11g */
3482 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3483 IEEE80211_CHAN_2GHZ),
3484 &iwl4965_rt->rt_chbitmask);
3485
12342c47
ZY		 3486 if (rate == -1)
3487 iwl4965_rt->rt_rate = 0;
3488 else
3489 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
3490
3491 /*
3492 * "antenna number"
3493 *
3494 * It seems that the antenna field in the phy flags value
3495 * is actually a bitfield. This is undefined by radiotap,
3496 * it wants an actual antenna number but I always get "7"
3497 * for most legacy frames I receive indicating that the
3498 * same frame was received on all three RX chains.
3499 *
3500 * I think this field should be removed in favour of a
3501 * new 802.11n radiotap field "RX chains" that is defined
3502 * as a bitmask.
3503 */
a0b484fe
JB		 3504 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
3505 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 3506
3507 /* set the preamble flag if appropriate */
3508 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
3509 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3510
3511 stats->flag |= RX_FLAG_RADIOTAP;
3512}
3513
19758bef
TW		 3514static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
3515{
3516 /* 0 - mgmt, 1 - cnt, 2 - data */
3517 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
3518 priv->rx_stats[idx].cnt++;
3519 priv->rx_stats[idx].bytes += len;
3520}
3521
17e476b8
EG		 3522static u32 iwl4965_translate_rx_status(u32 decrypt_in)
3523{
3524 u32 decrypt_out = 0;
3525
3526 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
3527 RX_RES_STATUS_STATION_FOUND)
3528 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
3529 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
3530
3531 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
3532
3533 /* packet was not encrypted */
3534 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3535 RX_RES_STATUS_SEC_TYPE_NONE)
3536 return decrypt_out;
3537
3538 /* packet was encrypted with unknown alg */
3539 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3540 RX_RES_STATUS_SEC_TYPE_ERR)
3541 return decrypt_out;
3542
3543 /* decryption was not done in HW */
3544 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
3545 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
3546 return decrypt_out;
3547
3548 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
3549
3550 case RX_RES_STATUS_SEC_TYPE_CCMP:
3551 /* alg is CCM: check MIC only */
3552 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
3553 /* Bad MIC */
3554 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3555 else
3556 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3557
3558 break;
3559
3560 case RX_RES_STATUS_SEC_TYPE_TKIP:
3561 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
3562 /* Bad TTAK */
3563 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
3564 break;
3565 }
3566 /* fall through if TTAK OK */
3567 default:
3568 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
3569 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3570 else
3571 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3572 break;
3573 };
3574
3575 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
3576 decrypt_in, decrypt_out);
3577
3578 return decrypt_out;
3579}
3580
c79dd5b5 3581static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 3582 int include_phy,
bb8c093b 3583 struct iwl4965_rx_mem_buffer *rxb,
b481de9c
ZY		 3584 struct ieee80211_rx_status *stats)
3585{
bb8c093b 3586 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3587 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3588 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3589 struct ieee80211_hdr *hdr;
3590 u16 len;
3591 __le32 *rx_end;
3592 unsigned int skblen;
3593 u32 ampdu_status;
17e476b8 3594 u32 ampdu_status_legacy;
b481de9c
ZY		 3595
3596 if (!include_phy && priv->last_phy_res[0])
3597 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3598
3599 if (!rx_start) {
3600 IWL_ERROR("MPDU frame without a PHY data\n");
3601 return;
3602 }
3603 if (include_phy) {
3604 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3605 rx_start->cfg_phy_cnt);
3606
3607 len = le16_to_cpu(rx_start->byte_count);
3608
3609 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3610 sizeof(struct iwl4965_rx_phy_res) +
3611 rx_start->cfg_phy_cnt + len);
3612
3613 } else {
3614 struct iwl4965_rx_mpdu_res_start *amsdu =
3615 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3616
3617 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3618 sizeof(struct iwl4965_rx_mpdu_res_start));
3619 len = le16_to_cpu(amsdu->byte_count);
3620 rx_start->byte_count = amsdu->byte_count;
3621 rx_end = (__le32 *) (((u8 *) hdr) + len);
3622 }
9ee1ba47 3623 if (len > priv->hw_setting.max_pkt_size || len < 16) {
12342c47 3624 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 3625 return;
3626 }
3627
3628 ampdu_status = le32_to_cpu(*rx_end);
3629 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3630
17e476b8
EG		 3631 if (!include_phy) {
3632 /* New status scheme, need to translate */
3633 ampdu_status_legacy = ampdu_status;
3634 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3635 }
3636
b481de9c
ZY		 3637 /* start from MAC */
3638 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3639 skb_put(rxb->skb, len); /* end where data ends */
3640
3641 /* We only process data packets if the interface is open */
3642 if (unlikely(!priv->is_open)) {
3643 IWL_DEBUG_DROP_LIMIT
3644 ("Dropping packet while interface is not open.\n");
3645 return;
3646 }
3647
b481de9c
ZY		 3648 stats->flag = 0;
3649 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3650
1ea87396 3651 if (priv->cfg->mod_params->hw_crypto)
bb8c093b 3652 iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
b481de9c 3653
12342c47
ZY		 3654 if (priv->add_radiotap)
3655 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3656
19758bef 3657 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 3658 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3659 priv->alloc_rxb_skb--;
3660 rxb->skb = NULL;
b481de9c
ZY		 3661}
3662
3663/* Calc max signal level (dBm) among 3 possible receivers */
3664static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3665{
3666 /* data from PHY/DSP regarding signal strength, etc.,
3667 * contents are always there, not configurable by host. */
3668 struct iwl4965_rx_non_cfg_phy *ncphy =
3669 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3670 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3671 >> IWL_AGC_DB_POS;
3672
3673 u32 valid_antennae =
3674 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3675 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3676 u8 max_rssi = 0;
3677 u32 i;
3678
3679 /* Find max rssi among 3 possible receivers.
3680 * These values are measured by the digital signal processor (DSP).
3681 * They should stay fairly constant even as the signal strength varies,
3682 * if the radio's automatic gain control (AGC) is working right.
3683 * AGC value (see below) will provide the "interesting" info. */
3684 for (i = 0; i < 3; i++)
3685 if (valid_antennae & (1 << i))
3686 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3687
3688 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3689 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3690 max_rssi, agc);
3691
3692 /* dBm = max_rssi dB - agc dB - constant.
3693 * Higher AGC (higher radio gain) means lower signal. */
3694 return (max_rssi - agc - IWL_RSSI_OFFSET);
3695}
3696
c8b0e6e1 3697#ifdef CONFIG_IWL4965_HT
b481de9c 3698
1ea87396
AK		 3699void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
3700 struct ieee80211_ht_info *ht_info,
78330fdd 3701 enum ieee80211_band band)
326eeee8
RR		 3702{
3703 ht_info->cap = 0;
3704 memset(ht_info->supp_mcs_set, 0, 16);
3705
3706 ht_info->ht_supported = 1;
3707
78330fdd 3708 if (band == IEEE80211_BAND_5GHZ) {
326eeee8
RR		 3709 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3710 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3711 ht_info->supp_mcs_set[4] = 0x01;
3712 }
3713 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3714 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3715 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3716 (IWL_MIMO_PS_NONE << 2));
1ea87396
AK		 3717
3718 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47 3719 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
326eeee8
RR		 3720
3721 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3722 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3723
3724 ht_info->supp_mcs_set[0] = 0xFF;
3725 ht_info->supp_mcs_set[1] = 0xFF;
3726}
c8b0e6e1 3727#endif /* CONFIG_IWL4965_HT */
b481de9c 3728
c79dd5b5 3729static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 3730{
3731 unsigned long flags;
3732
3733 spin_lock_irqsave(&priv->sta_lock, flags);
3734 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3735 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3736 priv->stations[sta_id].sta.sta.modify_mask = 0;
3737 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3738 spin_unlock_irqrestore(&priv->sta_lock, flags);
3739
bb8c093b 3740 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3741}
3742
c79dd5b5 3743static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 3744{
3745 /* FIXME: need locking over ps_status ??? */
bb8c093b 3746 u8 sta_id = iwl4965_hw_find_station(priv, addr);
b481de9c
ZY		 3747
3748 if (sta_id != IWL_INVALID_STATION) {
3749 u8 sta_awake = priv->stations[sta_id].
3750 ps_status == STA_PS_STATUS_WAKE;
3751
3752 if (sta_awake && ps_bit)
3753 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3754 else if (!sta_awake && !ps_bit) {
3755 iwl4965_sta_modify_ps_wake(priv, sta_id);
3756 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3757 }
3758 }
3759}
0a6857e7 3760#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 3761
3762/**
3763 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3764 *
3765 * You may hack this function to show different aspects of received frames,
3766 * including selective frame dumps.
3767 * group100 parameter selects whether to show 1 out of 100 good frames.
3768 *
3769 * TODO: This was originally written for 3945, need to audit for
3770 * proper operation with 4965.
3771 */
c79dd5b5 3772static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3773 struct iwl4965_rx_packet *pkt,
3774 struct ieee80211_hdr *header, int group100)
3775{
3776 u32 to_us;
3777 u32 print_summary = 0;
3778 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3779 u32 hundred = 0;
3780 u32 dataframe = 0;
3781 u16 fc;
3782 u16 seq_ctl;
3783 u16 channel;
3784 u16 phy_flags;
3785 int rate_sym;
3786 u16 length;
3787 u16 status;
3788 u16 bcn_tmr;
3789 u32 tsf_low;
3790 u64 tsf;
3791 u8 rssi;
3792 u8 agc;
3793 u16 sig_avg;
3794 u16 noise_diff;
3795 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3796 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3797 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3798 u8 *data = IWL_RX_DATA(pkt);
3799
0a6857e7 3800 if (likely(!(iwl_debug_level & IWL_DL_RX)))
17744ff6
TW		 3801 return;
3802
3803 /* MAC header */
3804 fc = le16_to_cpu(header->frame_control);
3805 seq_ctl = le16_to_cpu(header->seq_ctrl);
3806
3807 /* metadata */
3808 channel = le16_to_cpu(rx_hdr->channel);
3809 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3810 rate_sym = rx_hdr->rate;
3811 length = le16_to_cpu(rx_hdr->len);
3812
3813 /* end-of-frame status and timestamp */
3814 status = le32_to_cpu(rx_end->status);
3815 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3816 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3817 tsf = le64_to_cpu(rx_end->timestamp);
3818
3819 /* signal statistics */
3820 rssi = rx_stats->rssi;
3821 agc = rx_stats->agc;
3822 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3823 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3824
3825 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3826
3827 /* if data frame is to us and all is good,
3828 * (optionally) print summary for only 1 out of every 100 */
3829 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3830 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3831 dataframe = 1;
3832 if (!group100)
3833 print_summary = 1; /* print each frame */
3834 else if (priv->framecnt_to_us < 100) {
3835 priv->framecnt_to_us++;
3836 print_summary = 0;
3837 } else {
3838 priv->framecnt_to_us = 0;
3839 print_summary = 1;
3840 hundred = 1;
3841 }
3842 } else {
3843 /* print summary for all other frames */
3844 print_summary = 1;
3845 }
3846
3847 if (print_summary) {
3848 char *title;
3849 int rate_idx;
3850 u32 bitrate;
3851
3852 if (hundred)
3853 title = "100Frames";
3854 else if (fc & IEEE80211_FCTL_RETRY)
3855 title = "Retry";
3856 else if (ieee80211_is_assoc_response(fc))
3857 title = "AscRsp";
3858 else if (ieee80211_is_reassoc_response(fc))
3859 title = "RasRsp";
3860 else if (ieee80211_is_probe_response(fc)) {
3861 title = "PrbRsp";
3862 print_dump = 1; /* dump frame contents */
3863 } else if (ieee80211_is_beacon(fc)) {
3864 title = "Beacon";
3865 print_dump = 1; /* dump frame contents */
3866 } else if (ieee80211_is_atim(fc))
3867 title = "ATIM";
3868 else if (ieee80211_is_auth(fc))
3869 title = "Auth";
3870 else if (ieee80211_is_deauth(fc))
3871 title = "DeAuth";
3872 else if (ieee80211_is_disassoc(fc))
3873 title = "DisAssoc";
3874 else
3875 title = "Frame";
3876
3877 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3878 if (unlikely(rate_idx == -1))
3879 bitrate = 0;
3880 else
3881 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3882
3883 /* print frame summary.
3884 * MAC addresses show just the last byte (for brevity),
3885 * but you can hack it to show more, if you'd like to. */
3886 if (dataframe)
3887 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3888 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3889 title, fc, header->addr1[5],
3890 length, rssi, channel, bitrate);
3891 else {
3892 /* src/dst addresses assume managed mode */
3893 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3894 "src=0x%02x, rssi=%u, tim=%lu usec, "
3895 "phy=0x%02x, chnl=%d\n",
3896 title, fc, header->addr1[5],
3897 header->addr3[5], rssi,
3898 tsf_low - priv->scan_start_tsf,
3899 phy_flags, channel);
3900 }
3901 }
3902 if (print_dump)
0a6857e7 3903 iwl_print_hex_dump(IWL_DL_RX, data, length);
17744ff6
TW		 3904}
3905#else
c79dd5b5 3906static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3907 struct iwl4965_rx_packet *pkt,
3908 struct ieee80211_hdr *header,
3909 int group100)
3910{
3911}
3912#endif
3913
b481de9c 3914
7878a5a4 3915
857485c0 3916/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 3917 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
c79dd5b5 3918static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
bb8c093b 3919 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3920{
17744ff6
TW		 3921 struct ieee80211_hdr *header;
3922 struct ieee80211_rx_status rx_status;
bb8c093b 3923 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3924 /* Use phy data (Rx signal strength, etc.) contained within
3925 * this rx packet for legacy frames,
3926 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 3927 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 3928 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3929 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3930 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3931 __le32 *rx_end;
3932 unsigned int len = 0;
b481de9c 3933 u16 fc;
b481de9c
ZY		 3934 u8 network_packet;
3935
17744ff6 3936 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
dc92e497
TW		 3937 rx_status.freq =
3938 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
17744ff6
TW		 3939 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3940 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
dc92e497
TW		 3941 rx_status.rate_idx =
3942 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
17744ff6
TW		 3943 if (rx_status.band == IEEE80211_BAND_5GHZ)
3944 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3945
3946 rx_status.antenna = 0;
3947 rx_status.flag = 0;
3948
b481de9c 3949 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
dc92e497
TW		 3950 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3951 rx_start->cfg_phy_cnt);
b481de9c
ZY		 3952 return;
3953 }
17744ff6 3954
b481de9c
ZY		 3955 if (!include_phy) {
3956 if (priv->last_phy_res[0])
3957 rx_start = (struct iwl4965_rx_phy_res *)
3958 &priv->last_phy_res[1];
3959 else
3960 rx_start = NULL;
3961 }
3962
3963 if (!rx_start) {
3964 IWL_ERROR("MPDU frame without a PHY data\n");
3965 return;
3966 }
3967
3968 if (include_phy) {
3969 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3970 + rx_start->cfg_phy_cnt);
3971
3972 len = le16_to_cpu(rx_start->byte_count);
17744ff6 3973 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 3974 sizeof(struct iwl4965_rx_phy_res) + len);
3975 } else {
3976 struct iwl4965_rx_mpdu_res_start *amsdu =
3977 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3978
3979 header = (void *)(pkt->u.raw +
3980 sizeof(struct iwl4965_rx_mpdu_res_start));
3981 len = le16_to_cpu(amsdu->byte_count);
3982 rx_end = (__le32 *) (pkt->u.raw +
3983 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3984 }
3985
3986 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3987 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3988 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3989 le32_to_cpu(*rx_end));
3990 return;
3991 }
3992
3993 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3994
b481de9c 3995 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
17744ff6 3996 rx_status.ssi = iwl4965_calc_rssi(rx_start);
b481de9c
ZY		 3997
3998 /* Meaningful noise values are available only from beacon statistics,
3999 * which are gathered only when associated, and indicate noise
4000 * only for the associated network channel ...
4001 * Ignore these noise values while scanning (other channels) */
3109ece1 4002 if (iwl_is_associated(priv) &&
b481de9c 4003 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6
TW		 4004 rx_status.noise = priv->last_rx_noise;
4005 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
4006 rx_status.noise);
b481de9c 4007 } else {
17744ff6
TW		 4008 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
4009 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
b481de9c
ZY		 4010 }
4011
4012 /* Reset beacon noise level if not associated. */
3109ece1 4013 if (!iwl_is_associated(priv))
b481de9c
ZY		 4014 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
4015
17744ff6
TW		 4016 /* Set "1" to report good data frames in groups of 100 */
4017 /* FIXME: need to optimze the call: */
4018 iwl4965_dbg_report_frame(priv, pkt, header, 1);
4019
4020 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
4021 rx_status.ssi, rx_status.noise, rx_status.signal,
06501d29 4022 (unsigned long long)rx_status.mactime);
b481de9c 4023
bb8c093b 4024 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 4025 if (network_packet) {
17744ff6 4026 priv->last_rx_rssi = rx_status.ssi;
b481de9c
ZY		 4027 priv->last_beacon_time = priv->ucode_beacon_time;
4028 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
4029 }
4030
4031 fc = le16_to_cpu(header->frame_control);
4032 switch (fc & IEEE80211_FCTL_FTYPE) {
4033 case IEEE80211_FTYPE_MGMT:
b481de9c
ZY		 4034 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4035 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4036 header->addr2);
17744ff6 4037 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 4038 break;
4039
4040 case IEEE80211_FTYPE_CTL:
9ab46173 4041#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 4042 switch (fc & IEEE80211_FCTL_STYPE) {
4043 case IEEE80211_STYPE_BACK_REQ:
4044 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
4045 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 4046 rxb, &rx_status);
b481de9c
ZY		 4047 break;
4048 default:
4049 break;
4050 }
4051#endif
b481de9c
ZY		 4052 break;
4053
0795af57
JP		 4054 case IEEE80211_FTYPE_DATA: {
4055 DECLARE_MAC_BUF(mac1);
4056 DECLARE_MAC_BUF(mac2);
4057 DECLARE_MAC_BUF(mac3);
4058
b481de9c
ZY		 4059 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4060 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4061 header->addr2);
4062
4063 if (unlikely(!network_packet))
4064 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 4065 "%s, %s, %s\n",
4066 print_mac(mac1, header->addr1),
4067 print_mac(mac2, header->addr2),
4068 print_mac(mac3, header->addr3));
bb8c093b 4069 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 4070 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
4071 print_mac(mac1, header->addr1),
4072 print_mac(mac2, header->addr2),
4073 print_mac(mac3, header->addr3));
b481de9c
ZY		 4074 else
4075 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 4076 &rx_status);
b481de9c 4077 break;
0795af57 4078 }
b481de9c
ZY		 4079 default:
4080 break;
4081
4082 }
4083}
4084
4085/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
4086 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
c79dd5b5 4087static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
bb8c093b 4088 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4089{
bb8c093b 4090 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 4091 priv->last_phy_res[0] = 1;
4092 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
4093 sizeof(struct iwl4965_rx_phy_res));
4094}
c79dd5b5 4095static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
bb8c093b 4096 struct iwl4965_rx_mem_buffer *rxb)
b481de9c
ZY		 4097
4098{
c8b0e6e1 4099#ifdef CONFIG_IWL4965_SENSITIVITY
bb8c093b
CH		 4100 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4101 struct iwl4965_missed_beacon_notif *missed_beacon;
b481de9c
ZY		 4102
4103 missed_beacon = &pkt->u.missed_beacon;
4104 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
4105 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
4106 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
4107 le32_to_cpu(missed_beacon->total_missed_becons),
4108 le32_to_cpu(missed_beacon->num_recvd_beacons),
4109 le32_to_cpu(missed_beacon->num_expected_beacons));
4110 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
4111 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
4112 queue_work(priv->workqueue, &priv->sensitivity_work);
4113 }
c8b0e6e1 4114#endif /*CONFIG_IWL4965_SENSITIVITY*/
b481de9c 4115}
c8b0e6e1 4116#ifdef CONFIG_IWL4965_HT
b481de9c 4117
8b6eaea8
CB		 4118/**
4119 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
4120 */
c79dd5b5 4121static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
b481de9c
ZY		 4122 int sta_id, int tid)
4123{
4124 unsigned long flags;
4125
8b6eaea8 4126 /* Remove "disable" flag, to enable Tx for this TID */
b481de9c
ZY		 4127 spin_lock_irqsave(&priv->sta_lock, flags);
4128 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
4129 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
4130 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4131 spin_unlock_irqrestore(&priv->sta_lock, flags);
4132
bb8c093b 4133 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4134}
4135
8b6eaea8
CB		 4136/**
4137 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
4138 *
4139 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
4140 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
4141 */
c79dd5b5 4142static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b
CH		 4143 struct iwl4965_ht_agg *agg,
4144 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 4145 ba_resp)
4146
4147{
4148 int i, sh, ack;
fe01b477
RR		 4149 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
4150 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
4151 u64 bitmap;
4152 int successes = 0;
4153 struct ieee80211_tx_status *tx_status;
b481de9c
ZY		 4154
4155 if (unlikely(!agg->wait_for_ba)) {
4156 IWL_ERROR("Received BA when not expected\n");
4157 return -EINVAL;
4158 }
8b6eaea8
CB		 4159
4160 /* Mark that the expected block-ack response arrived */
b481de9c 4161 agg->wait_for_ba = 0;
fe01b477 4162 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 4163
4164 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 4165 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 4166 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 4167 sh += 0x100;
4168
8b6eaea8 4169 /* don't use 64-bit values for now */
fe01b477 4170 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 4171
4172 if (agg->frame_count > (64 - sh)) {
4173 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
4174 return -1;
4175 }
4176
4177 /* check for success or failure according to the
8b6eaea8 4178 * transmitted bitmap and block-ack bitmap */
fe01b477 4179 bitmap &= agg->bitmap;
b481de9c 4180
8b6eaea8
CB		 4181 /* For each frame attempted in aggregation,
4182 * update driver's record of tx frame's status. */
b481de9c 4183 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 4184 ack = bitmap & (1 << i);
4185 successes += !!ack;
b481de9c 4186 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 4187 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
4188 agg->start_idx + i);
4189 }
4190
4191 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
4192 tx_status->flags = IEEE80211_TX_STATUS_ACK;
99556438
RR		 4193 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
4194 tx_status->ampdu_ack_map = successes;
4195 tx_status->ampdu_ack_len = agg->frame_count;
4c424e4c
RR		 4196 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
4197 &tx_status->control);
fe01b477 4198
f868f4e1 4199 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 4200
4201 return 0;
4202}
4203
4204/**
4205 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
4206 */
c79dd5b5 4207static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 4208 u16 txq_id)
4209{
4210 /* Simply stop the queue, but don't change any configuration;
4211 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 4212 iwl_write_prph(priv,
12a81f60 4213 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
fe01b477
RR		 4214 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
4215 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
4216}
b481de9c 4217
fe01b477
RR		 4218/**
4219 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
b095d03a 4220 * priv->lock must be held by the caller
fe01b477 4221 */
c79dd5b5 4222static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
fe01b477
RR		 4223 u16 ssn_idx, u8 tx_fifo)
4224{
b095d03a
RR		 4225 int ret = 0;
4226
fe01b477
RR		 4227 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
4228 IWL_WARNING("queue number too small: %d, must be > %d\n",
4229 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4230 return -EINVAL;
b481de9c
ZY		 4231 }
4232
3395f6e9 4233 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 4234 if (ret)
4235 return ret;
4236
fe01b477
RR		 4237 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4238
12a81f60 4239 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 4240
4241 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4242 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
4243 /* supposes that ssn_idx is valid (!= 0xFFF) */
4244 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4245
12a81f60 4246 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
fe01b477
RR		 4247 iwl4965_txq_ctx_deactivate(priv, txq_id);
4248 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4249
3395f6e9 4250 iwl_release_nic_access(priv);
b095d03a 4251
fe01b477
RR		 4252 return 0;
4253}
b481de9c 4254
c79dd5b5 4255int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
fe01b477
RR		 4256 u8 tid, int txq_id)
4257{
4258 struct iwl4965_queue *q = &priv->txq[txq_id].q;
4259 u8 *addr = priv->stations[sta_id].sta.sta.addr;
4260 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
4261
4262 switch (priv->stations[sta_id].tid[tid].agg.state) {
4263 case IWL_EMPTYING_HW_QUEUE_DELBA:
4264 /* We are reclaiming the last packet of the */
4265 /* aggregated HW queue */
4266 if (txq_id == tid_data->agg.txq_id &&
4267 q->read_ptr == q->write_ptr) {
4268 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
4269 int tx_fifo = default_tid_to_tx_fifo[tid];
4270 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
4271 iwl4965_tx_queue_agg_disable(priv, txq_id,
4272 ssn, tx_fifo);
4273 tid_data->agg.state = IWL_AGG_OFF;
4274 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4275 }
4276 break;
4277 case IWL_EMPTYING_HW_QUEUE_ADDBA:
4278 /* We are reclaiming the last packet of the queue */
4279 if (tid_data->tfds_in_queue == 0) {
4280 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
4281 tid_data->agg.state = IWL_AGG_ON;
4282 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4283 }
4284 break;
4285 }
b481de9c
ZY		 4286 return 0;
4287}
4288
8b6eaea8
CB		 4289/**
4290 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
4291 * @index -- current index
4292 * @n_bd -- total number of entries in queue (s/b power of 2)
4293 */
bb8c093b 4294static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 4295{
4296 return (index == 0) ? n_bd - 1 : index - 1;
4297}
4298
8b6eaea8
CB		 4299/**
4300 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
4301 *
4302 * Handles block-acknowledge notification from device, which reports success
4303 * of frames sent via aggregation.
4304 */
c79dd5b5 4305static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b 4306 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4307{
bb8c093b
CH		 4308 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4309 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 4310 int index;
bb8c093b
CH		 4311 struct iwl4965_tx_queue *txq = NULL;
4312 struct iwl4965_ht_agg *agg;
fe01b477 4313 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 4314
4315 /* "flow" corresponds to Tx queue */
fe01b477 4316 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 4317
4318 /* "ssn" is start of block-ack Tx window, corresponds to index
4319 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 4320 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
4321
fe01b477 4322 if (scd_flow >= ARRAY_SIZE(priv->txq)) {
b481de9c
ZY		 4323 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
4324 return;
4325 }
4326
fe01b477 4327 txq = &priv->txq[scd_flow];
b481de9c 4328 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 4329
4330 /* Find index just before block-ack window */
bb8c093b 4331 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 4332
01ebd063 4333 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 4334
0795af57
JP		 4335 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
4336 "sta_id = %d\n",
b481de9c 4337 agg->wait_for_ba,
0795af57 4338 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 4339 ba_resp->sta_id);
fe01b477 4340 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 4341 "%d, scd_ssn = %d\n",
4342 ba_resp->tid,
fe01b477 4343 ba_resp->seq_ctl,
0310ae72 4344 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 4345 ba_resp->scd_flow,
4346 ba_resp->scd_ssn);
fe01b477 4347 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 4348 agg->start_idx,
f868f4e1 4349 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 4350
4351 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 4352 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 4353
4354 /* Release all TFDs before the SSN, i.e. all TFDs in front of
4355 * block-ack window (we assume that they've been successfully
4356 * transmitted ... if not, it's too late anyway). */
fe01b477
RR		 4357 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
4358 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
4359 priv->stations[ba_resp->sta_id].
4360 tid[ba_resp->tid].tfds_in_queue -= freed;
4361 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
4362 priv->mac80211_registered &&
4363 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
4364 ieee80211_wake_queue(priv->hw, scd_flow);
4365 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
4366 ba_resp->tid, scd_flow);
4367 }
b481de9c
ZY		 4368}
4369
8b6eaea8
CB		 4370/**
4371 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
4372 */
c79dd5b5 4373static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 4374 u16 txq_id)
4375{
4376 u32 tbl_dw_addr;
4377 u32 tbl_dw;
4378 u16 scd_q2ratid;
4379
4380 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
4381
4382 tbl_dw_addr = priv->scd_base_addr +
4383 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
4384
3395f6e9 4385 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 4386
4387 if (txq_id & 0x1)
4388 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
4389 else
4390 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
4391
3395f6e9 4392 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 4393
4394 return 0;
4395}
4396
fe01b477 4397
b481de9c 4398/**
8b6eaea8
CB		 4399 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
4400 *
4401 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
4402 * i.e. it must be one of the higher queues used for aggregation
b481de9c 4403 */
c79dd5b5 4404static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
b481de9c
ZY		 4405 int tx_fifo, int sta_id, int tid,
4406 u16 ssn_idx)
4407{
4408 unsigned long flags;
4409 int rc;
4410 u16 ra_tid;
4411
4412 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
4413 IWL_WARNING("queue number too small: %d, must be > %d\n",
4414 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4415
4416 ra_tid = BUILD_RAxTID(sta_id, tid);
4417
8b6eaea8 4418 /* Modify device's station table to Tx this TID */
bb8c093b 4419 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 4420
4421 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 4422 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 4423 if (rc) {
4424 spin_unlock_irqrestore(&priv->lock, flags);
4425 return rc;
4426 }
4427
8b6eaea8 4428 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 4429 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4430
8b6eaea8 4431 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 4432 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
4433
8b6eaea8 4434 /* Set this queue as a chain-building queue */
12a81f60 4435 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 4436
8b6eaea8
CB		 4437 /* Place first TFD at index corresponding to start sequence number.
4438 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 4439 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4440 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 4441 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4442
8b6eaea8 4443 /* Set up Tx window size and frame limit for this queue */
3395f6e9 4444 iwl_write_targ_mem(priv,
b481de9c
ZY		 4445 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
4446 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4447 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4448
3395f6e9 4449 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 4450 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
4451 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4452 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4453
12a81f60 4454 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 4455
8b6eaea8 4456 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 4457 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4458
3395f6e9 4459 iwl_release_nic_access(priv);
b481de9c
ZY		 4460 spin_unlock_irqrestore(&priv->lock, flags);
4461
4462 return 0;
4463}
4464
c8b0e6e1 4465#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4466
4467/**
4468 * iwl4965_add_station - Initialize a station's hardware rate table
4469 *
8b6eaea8 4470 * The uCode's station table contains a table of fallback rates
b481de9c
ZY		 4471 * for automatic fallback during transmission.
4472 *
8b6eaea8
CB		 4473 * NOTE: This sets up a default set of values. These will be replaced later
4474 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
4475 * rc80211_simple.
b481de9c 4476 *
8b6eaea8
CB		 4477 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
4478 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
4479 * which requires station table entry to exist).
b481de9c 4480 */
c79dd5b5 4481void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 4482{
4483 int i, r;
bb8c093b 4484 struct iwl4965_link_quality_cmd link_cmd = {
b481de9c
ZY		 4485 .reserved1 = 0,
4486 };
4487 u16 rate_flags;
4488
8b6eaea8
CB		 4489 /* Set up the rate scaling to start at selected rate, fall back
4490 * all the way down to 1M in IEEE order, and then spin on 1M */
b481de9c
ZY		 4491 if (is_ap)
4492 r = IWL_RATE_54M_INDEX;
8318d78a 4493 else if (priv->band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4494 r = IWL_RATE_6M_INDEX;
4495 else
4496 r = IWL_RATE_1M_INDEX;
4497
4498 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
4499 rate_flags = 0;
4500 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
4501 rate_flags |= RATE_MCS_CCK_MSK;
4502
8b6eaea8 4503 /* Use Tx antenna B only */
b481de9c
ZY		 4504 rate_flags |= RATE_MCS_ANT_B_MSK;
4505 rate_flags &= ~RATE_MCS_ANT_A_MSK;
8b6eaea8 4506
b481de9c 4507 link_cmd.rs_table[i].rate_n_flags =
bb8c093b
CH		 4508 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
4509 r = iwl4965_get_prev_ieee_rate(r);
b481de9c
ZY		 4510 }
4511
4512 link_cmd.general_params.single_stream_ant_msk = 2;
4513 link_cmd.general_params.dual_stream_ant_msk = 3;
4514 link_cmd.agg_params.agg_dis_start_th = 3;
4515 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
4516
4517 /* Update the rate scaling for control frame Tx to AP */
a4062b8f 4518 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_setting.bcast_sta_id;
b481de9c 4519
e5472978
TW		 4520 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
4521 sizeof(link_cmd), &link_cmd, NULL);
b481de9c
ZY		 4522}
4523
c8b0e6e1 4524#ifdef CONFIG_IWL4965_HT
b481de9c 4525
c79dd5b5 4526static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
8318d78a 4527 enum ieee80211_band band,
78330fdd 4528 u16 channel, u8 extension_chan_offset)
b481de9c 4529{
bf85ea4f 4530 const struct iwl_channel_info *ch_info;
b481de9c 4531
8622e705 4532 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 4533 if (!is_channel_valid(ch_info))
4534 return 0;
4535
134eb5d3 4536 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
b481de9c
ZY		 4537 return 0;
4538
4539 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
4540 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
4541 return 1;
4542
4543 return 0;
4544}
4545
c79dd5b5 4546static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
fd105e79 4547 struct ieee80211_ht_info *sta_ht_inf)
b481de9c 4548{
fd105e79 4549 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
b481de9c 4550
fd105e79
RR		 4551 if ((!iwl_ht_conf->is_ht) ||
4552 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
134eb5d3 4553 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
b481de9c
ZY		 4554 return 0;
4555
fd105e79
RR		 4556 if (sta_ht_inf) {
4557 if ((!sta_ht_inf->ht_supported) ||
194c7ca6 4558 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
fd105e79
RR		 4559 return 0;
4560 }
b481de9c 4561
78330fdd 4562 return (iwl4965_is_channel_extension(priv, priv->band,
fd105e79
RR		 4563 iwl_ht_conf->control_channel,
4564 iwl_ht_conf->extension_chan_offset));
b481de9c
ZY		 4565}
4566
c79dd5b5 4567void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
b481de9c 4568{
bb8c093b 4569 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 4570 u32 val;
4571
4572 if (!ht_info->is_ht)
4573 return;
4574
8b6eaea8 4575 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
fd105e79 4576 if (iwl4965_is_fat_tx_allowed(priv, NULL))
b481de9c
ZY		 4577 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4578 else
4579 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4580 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
4581
4582 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
4583 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4584 le16_to_cpu(rxon->channel),
4585 ht_info->control_channel);
4586 rxon->channel = cpu_to_le16(ht_info->control_channel);
4587 return;
4588 }
4589
8b6eaea8 4590 /* Note: control channel is opposite of extension channel */
b481de9c
ZY		 4591 switch (ht_info->extension_chan_offset) {
4592 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4593 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4594 break;
4595 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4596 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4597 break;
134eb5d3 4598 case IWL_EXT_CHANNEL_OFFSET_NONE:
b481de9c
ZY		 4599 default:
4600 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4601 break;
4602 }
4603
fd105e79 4604 val = ht_info->ht_protection;
b481de9c
ZY		 4605
4606 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4607
b481de9c
ZY		 4608 iwl4965_set_rxon_chain(priv);
4609
4610 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
4611 "rxon flags 0x%X operation mode :0x%X "
4612 "extension channel offset 0x%x "
4613 "control chan %d\n",
fd105e79
RR		 4614 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
4615 le32_to_cpu(rxon->flags), ht_info->ht_protection,
b481de9c
ZY		 4616 ht_info->extension_chan_offset,
4617 ht_info->control_channel);
4618 return;
4619}
4620
c79dd5b5 4621void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
67d62035 4622 struct ieee80211_ht_info *sta_ht_inf)
b481de9c
ZY		 4623{
4624 __le32 sta_flags;
e53cfe0e 4625 u8 mimo_ps_mode;
b481de9c 4626
67d62035 4627 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
b481de9c
ZY		 4628 goto done;
4629
e53cfe0e
TW		 4630 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4631
b481de9c
ZY		 4632 sta_flags = priv->stations[index].sta.station_flags;
4633
e53cfe0e
TW		 4634 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4635
4636 switch (mimo_ps_mode) {
4637 case WLAN_HT_CAP_MIMO_PS_STATIC:
4638 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4639 break;
4640 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
b481de9c 4641 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
e53cfe0e
TW		 4642 break;
4643 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4644 break;
4645 default:
4646 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4647 break;
4648 }
b481de9c
ZY		 4649
4650 sta_flags |= cpu_to_le32(
67d62035 4651 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
b481de9c
ZY		 4652
4653 sta_flags |= cpu_to_le32(
67d62035 4654 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
b481de9c 4655
67d62035 4656 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
b481de9c 4657 sta_flags |= STA_FLG_FAT_EN_MSK;
67d62035 4658 else
e53cfe0e 4659 sta_flags &= ~STA_FLG_FAT_EN_MSK;
67d62035 4660
b481de9c
ZY		 4661 priv->stations[index].sta.station_flags = sta_flags;
4662 done:
4663 return;
4664}
4665
c79dd5b5 4666static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
b481de9c
ZY		 4667 int sta_id, int tid, u16 ssn)
4668{
4669 unsigned long flags;
4670
4671 spin_lock_irqsave(&priv->sta_lock, flags);
4672 priv->stations[sta_id].sta.station_flags_msk = 0;
4673 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4674 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4675 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4676 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4677 spin_unlock_irqrestore(&priv->sta_lock, flags);
4678
bb8c093b 4679 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4680}
4681
c79dd5b5 4682static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
b481de9c
ZY		 4683 int sta_id, int tid)
4684{
4685 unsigned long flags;
4686
4687 spin_lock_irqsave(&priv->sta_lock, flags);
4688 priv->stations[sta_id].sta.station_flags_msk = 0;
4689 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4690 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4691 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4692 spin_unlock_irqrestore(&priv->sta_lock, flags);
4693
bb8c093b 4694 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4695}
4696
8b6eaea8
CB		 4697/*
4698 * Find first available (lowest unused) Tx Queue, mark it "active".
4699 * Called only when finding queue for aggregation.
4700 * Should never return anything < 7, because they should already
4701 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4702 */
c79dd5b5 4703static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
b481de9c
ZY		 4704{
4705 int txq_id;
4706
4707 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
4708 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4709 return txq_id;
4710 return -1;
4711}
4712
fe01b477
RR		 4713static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
4714 u16 tid, u16 *start_seq_num)
b481de9c 4715{
c79dd5b5 4716 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 4717 int sta_id;
4718 int tx_fifo;
4719 int txq_id;
4720 int ssn = -1;
b095d03a 4721 int ret = 0;
b481de9c 4722 unsigned long flags;
bb8c093b 4723 struct iwl4965_tid_data *tid_data;
0795af57 4724 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 4725
4726 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4727 tx_fifo = default_tid_to_tx_fifo[tid];
4728 else
4729 return -EINVAL;
4730
fe01b477
RR		 4731 IWL_WARNING("%s on da = %s tid = %d\n",
4732 __func__, print_mac(mac, da), tid);
b481de9c 4733
bb8c093b 4734 sta_id = iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 4735 if (sta_id == IWL_INVALID_STATION)
4736 return -ENXIO;
4737
fe01b477
RR		 4738 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4739 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4740 return -ENXIO;
4741 }
4742
bb8c093b 4743 txq_id = iwl4965_txq_ctx_activate_free(priv);
b481de9c
ZY		 4744 if (txq_id == -1)
4745 return -ENXIO;
4746
4747 spin_lock_irqsave(&priv->sta_lock, flags);
4748 tid_data = &priv->stations[sta_id].tid[tid];
4749 ssn = SEQ_TO_SN(tid_data->seq_number);
4750 tid_data->agg.txq_id = txq_id;
4751 spin_unlock_irqrestore(&priv->sta_lock, flags);
4752
4753 *start_seq_num = ssn;
b095d03a
RR		 4754 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4755 sta_id, tid, ssn);
4756 if (ret)
4757 return ret;
b481de9c 4758
b095d03a 4759 ret = 0;
fe01b477
RR		 4760 if (tid_data->tfds_in_queue == 0) {
4761 printk(KERN_ERR "HW queue is empty\n");
4762 tid_data->agg.state = IWL_AGG_ON;
4763 ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
4764 } else {
4765 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4766 tid_data->tfds_in_queue);
4767 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4768 }
b095d03a 4769 return ret;
fe01b477 4770}
b481de9c 4771
fe01b477
RR		 4772static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
4773 u16 tid)
b481de9c
ZY		 4774{
4775
c79dd5b5 4776 struct iwl_priv *priv = hw->priv;
b481de9c 4777 int tx_fifo_id, txq_id, sta_id, ssn = -1;
bb8c093b 4778 struct iwl4965_tid_data *tid_data;
b095d03a 4779 int ret, write_ptr, read_ptr;
fe01b477 4780 unsigned long flags;
0795af57
JP		 4781 DECLARE_MAC_BUF(mac);
4782
b481de9c 4783 if (!da) {
fe01b477 4784 IWL_ERROR("da = NULL\n");
b481de9c
ZY		 4785 return -EINVAL;
4786 }
4787
4788 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4789 tx_fifo_id = default_tid_to_tx_fifo[tid];
4790 else
4791 return -EINVAL;
4792
bb8c093b 4793 sta_id = iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 4794
4795 if (sta_id == IWL_INVALID_STATION)
4796 return -ENXIO;
4797
fe01b477
RR		 4798 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4799 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4800
b481de9c
ZY		 4801 tid_data = &priv->stations[sta_id].tid[tid];
4802 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4803 txq_id = tid_data->agg.txq_id;
fe01b477
RR		 4804 write_ptr = priv->txq[txq_id].q.write_ptr;
4805 read_ptr = priv->txq[txq_id].q.read_ptr;
4806
4807 /* The queue is not empty */
4808 if (write_ptr != read_ptr) {
4809 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4810 priv->stations[sta_id].tid[tid].agg.state =
4811 IWL_EMPTYING_HW_QUEUE_DELBA;
4812 return 0;
4813 }
4814
4815 IWL_DEBUG_HT("HW queue empty\n");;
4816 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
b481de9c 4817
fe01b477 4818 spin_lock_irqsave(&priv->lock, flags);
b095d03a 4819 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
fe01b477
RR		 4820 spin_unlock_irqrestore(&priv->lock, flags);
4821
b095d03a
RR		 4822 if (ret)
4823 return ret;
b481de9c 4824
fe01b477 4825 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
b481de9c 4826
fe01b477
RR		 4827 IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
4828 print_mac(mac, da), tid);
8114fcf1 4829
8114fcf1
RR		 4830 return 0;
4831}
4832
4833int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4834 enum ieee80211_ampdu_mlme_action action,
4835 const u8 *addr, u16 tid, u16 *ssn)
4836{
c79dd5b5 4837 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 4838 int sta_id;
4839 DECLARE_MAC_BUF(mac);
4840
4841 IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
4842 print_mac(mac, addr), tid);
4843 sta_id = iwl4965_hw_find_station(priv, addr);
4844 switch (action) {
4845 case IEEE80211_AMPDU_RX_START:
4846 IWL_DEBUG_HT("start Rx\n");
4847 iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
4848 break;
4849 case IEEE80211_AMPDU_RX_STOP:
4850 IWL_DEBUG_HT("stop Rx\n");
4851 iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
4852 break;
4853 case IEEE80211_AMPDU_TX_START:
4854 IWL_DEBUG_HT("start Tx\n");
4855 return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
4856 case IEEE80211_AMPDU_TX_STOP:
4857 IWL_DEBUG_HT("stop Tx\n");
4858 return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
4859 default:
4860 IWL_DEBUG_HT("unknown\n");
4861 return -EINVAL;
4862 break;
4863 }
4864 return 0;
4865}
4866
c8b0e6e1 4867#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4868
4869/* Set up 4965-specific Rx frame reply handlers */
c79dd5b5 4870void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 4871{
4872 /* Legacy Rx frames */
857485c0 4873 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
b481de9c
ZY		 4874
4875 /* High-throughput (HT) Rx frames */
4876 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4877 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4878
4879 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4880 iwl4965_rx_missed_beacon_notif;
4881
c8b0e6e1 4882#ifdef CONFIG_IWL4965_HT
b481de9c 4883 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
c8b0e6e1 4884#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4885}
4886
c79dd5b5 4887void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4888{
4889 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
c8b0e6e1 4890#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 4891 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4892#endif
b481de9c
ZY		 4893 init_timer(&priv->statistics_periodic);
4894 priv->statistics_periodic.data = (unsigned long)priv;
4895 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4896}
4897
c79dd5b5 4898void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4899{
4900 del_timer_sync(&priv->statistics_periodic);
4901
4902 cancel_delayed_work(&priv->init_alive_start);
4903}
4904
857485c0
TW		 4905static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4906 .enqueue_hcmd = iwl4965_enqueue_hcmd,
4907};
4908
6bc913bd 4909static struct iwl_lib_ops iwl4965_lib = {
bf85ea4f 4910 .init_drv = iwl4965_init_drv,
e2a722eb 4911 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
57aab75a
TW		 4912 .hw_nic_init = iwl4965_hw_nic_init,
4913 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4914 .alive_notify = iwl4965_alive_notify,
4915 .load_ucode = iwl4965_load_bsm,
6bc913bd
AK		 4916 .eeprom_ops = {
4917 .verify_signature = iwlcore_eeprom_verify_signature,
4918 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4919 .release_semaphore = iwlcore_eeprom_release_semaphore,
4920 },
ad97edd2 4921 .radio_kill_sw = iwl4965_radio_kill_sw,
6bc913bd
AK		 4922};
4923
4924static struct iwl_ops iwl4965_ops = {
4925 .lib = &iwl4965_lib,
857485c0 4926 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 4927};
4928
82b9a121
TW		 4929static struct iwl_cfg iwl4965_agn_cfg = {
4930 .name = "4965AGN",
4bf775cd 4931 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 4932 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
6bc913bd 4933 .ops = &iwl4965_ops,
1ea87396 4934 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 4935};
4936
bb8c093b 4937struct pci_device_id iwl4965_hw_card_ids[] = {
82b9a121
TW		 4938 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4939 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
b481de9c
ZY		 4940 {0}
4941};
4942
bb8c093b 4943MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);
1ea87396
AK		 4944
4945module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4946MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4947module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4948MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
4949module_param_named(hwcrypto, iwl4965_mod_params.hw_crypto, int, 0444);
4950MODULE_PARM_DESC(hwcrypto,
4951 "using hardware crypto engine (default 0 [software])\n");
4952module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4953MODULE_PARM_DESC(debug, "debug output mask");
4954module_param_named(
4955 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4956MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4957
4958module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4959MODULE_PARM_DESC(queues_num, "number of hw queues.");
4960
4961/* QoS */
4962module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4963MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4964module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4965MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4966
Linux kernel - Deliverables
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