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iwlwifi: rename iwl-4965-commands to iwl-commands.h
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
b481de9c 42#include "iwl-4965.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c 45#include "iwl-helpers.h"
f0832f13 46#include "iwl-calib.h"
b481de9c 47
1ea87396
AK		 48/* module parameters */
49static struct iwl_mod_params iwl4965_mod_params = {
038669e4 50 .num_of_queues = IWL49_NUM_QUEUES,
1ea87396
AK		 51 .enable_qos = 1,
52 .amsdu_size_8K = 1,
53 /* the rest are 0 by default */
54};
55
c79dd5b5 56static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
416e1438 57
fe01b477
RR		 58#ifdef CONFIG_IWL4965_HT
59
60static const u16 default_tid_to_tx_fifo[] = {
61 IWL_TX_FIFO_AC1,
62 IWL_TX_FIFO_AC0,
63 IWL_TX_FIFO_AC0,
64 IWL_TX_FIFO_AC1,
65 IWL_TX_FIFO_AC2,
66 IWL_TX_FIFO_AC2,
67 IWL_TX_FIFO_AC3,
68 IWL_TX_FIFO_AC3,
69 IWL_TX_FIFO_NONE,
70 IWL_TX_FIFO_NONE,
71 IWL_TX_FIFO_NONE,
72 IWL_TX_FIFO_NONE,
73 IWL_TX_FIFO_NONE,
74 IWL_TX_FIFO_NONE,
75 IWL_TX_FIFO_NONE,
76 IWL_TX_FIFO_NONE,
77 IWL_TX_FIFO_AC3
78};
79
80#endif /*CONFIG_IWL4965_HT */
81
57aab75a
TW		 82/* check contents of special bootstrap uCode SRAM */
83static int iwl4965_verify_bsm(struct iwl_priv *priv)
84{
85 __le32 *image = priv->ucode_boot.v_addr;
86 u32 len = priv->ucode_boot.len;
87 u32 reg;
88 u32 val;
89
90 IWL_DEBUG_INFO("Begin verify bsm\n");
91
92 /* verify BSM SRAM contents */
93 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
94 for (reg = BSM_SRAM_LOWER_BOUND;
95 reg < BSM_SRAM_LOWER_BOUND + len;
96 reg += sizeof(u32), image++) {
97 val = iwl_read_prph(priv, reg);
98 if (val != le32_to_cpu(*image)) {
99 IWL_ERROR("BSM uCode verification failed at "
100 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
101 BSM_SRAM_LOWER_BOUND,
102 reg - BSM_SRAM_LOWER_BOUND, len,
103 val, le32_to_cpu(*image));
104 return -EIO;
105 }
106 }
107
108 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
109
110 return 0;
111}
112
113/**
114 * iwl4965_load_bsm - Load bootstrap instructions
115 *
116 * BSM operation:
117 *
118 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
119 * in special SRAM that does not power down during RFKILL. When powering back
120 * up after power-saving sleeps (or during initial uCode load), the BSM loads
121 * the bootstrap program into the on-board processor, and starts it.
122 *
123 * The bootstrap program loads (via DMA) instructions and data for a new
124 * program from host DRAM locations indicated by the host driver in the
125 * BSM_DRAM_* registers. Once the new program is loaded, it starts
126 * automatically.
127 *
128 * When initializing the NIC, the host driver points the BSM to the
129 * "initialize" uCode image. This uCode sets up some internal data, then
130 * notifies host via "initialize alive" that it is complete.
131 *
132 * The host then replaces the BSM_DRAM_* pointer values to point to the
133 * normal runtime uCode instructions and a backup uCode data cache buffer
134 * (filled initially with starting data values for the on-board processor),
135 * then triggers the "initialize" uCode to load and launch the runtime uCode,
136 * which begins normal operation.
137 *
138 * When doing a power-save shutdown, runtime uCode saves data SRAM into
139 * the backup data cache in DRAM before SRAM is powered down.
140 *
141 * When powering back up, the BSM loads the bootstrap program. This reloads
142 * the runtime uCode instructions and the backup data cache into SRAM,
143 * and re-launches the runtime uCode from where it left off.
144 */
145static int iwl4965_load_bsm(struct iwl_priv *priv)
146{
147 __le32 *image = priv->ucode_boot.v_addr;
148 u32 len = priv->ucode_boot.len;
149 dma_addr_t pinst;
150 dma_addr_t pdata;
151 u32 inst_len;
152 u32 data_len;
153 int i;
154 u32 done;
155 u32 reg_offset;
156 int ret;
157
158 IWL_DEBUG_INFO("Begin load bsm\n");
159
160 /* make sure bootstrap program is no larger than BSM's SRAM size */
161 if (len > IWL_MAX_BSM_SIZE)
162 return -EINVAL;
163
164 /* Tell bootstrap uCode where to find the "Initialize" uCode
165 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
166 * NOTE: iwl4965_initialize_alive_start() will replace these values,
167 * after the "initialize" uCode has run, to point to
168 * runtime/protocol instructions and backup data cache. */
169 pinst = priv->ucode_init.p_addr >> 4;
170 pdata = priv->ucode_init_data.p_addr >> 4;
171 inst_len = priv->ucode_init.len;
172 data_len = priv->ucode_init_data.len;
173
174 ret = iwl_grab_nic_access(priv);
175 if (ret)
176 return ret;
177
178 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
179 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
180 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
181 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
182
183 /* Fill BSM memory with bootstrap instructions */
184 for (reg_offset = BSM_SRAM_LOWER_BOUND;
185 reg_offset < BSM_SRAM_LOWER_BOUND + len;
186 reg_offset += sizeof(u32), image++)
187 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
188
189 ret = iwl4965_verify_bsm(priv);
190 if (ret) {
191 iwl_release_nic_access(priv);
192 return ret;
193 }
194
195 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
196 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
197 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
198 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
199
200 /* Load bootstrap code into instruction SRAM now,
201 * to prepare to load "initialize" uCode */
202 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
203
204 /* Wait for load of bootstrap uCode to finish */
205 for (i = 0; i < 100; i++) {
206 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
207 if (!(done & BSM_WR_CTRL_REG_BIT_START))
208 break;
209 udelay(10);
210 }
211 if (i < 100)
212 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
213 else {
214 IWL_ERROR("BSM write did not complete!\n");
215 return -EIO;
216 }
217
218 /* Enable future boot loads whenever power management unit triggers it
219 * (e.g. when powering back up after power-save shutdown) */
220 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
221
222 iwl_release_nic_access(priv);
223
224 return 0;
225}
226
b481de9c
ZY		 227static int is_fat_channel(__le32 rxon_flags)
228{
229 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
230 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
231}
232
17744ff6
TW		 233int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
234{
235 int idx = 0;
236
237 /* 4965 HT rate format */
238 if (rate_n_flags & RATE_MCS_HT_MSK) {
239 idx = (rate_n_flags & 0xff);
240
fde0db31
GC		 241 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
242 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
17744ff6
TW		 243
244 idx += IWL_FIRST_OFDM_RATE;
245 /* skip 9M not supported in ht*/
246 if (idx >= IWL_RATE_9M_INDEX)
247 idx += 1;
248 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
249 return idx;
250
251 /* 4965 legacy rate format, search for match in table */
252 } else {
253 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
254 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
255 return idx;
256 }
257
258 return -1;
259}
260
4c424e4c
RR		 261/**
262 * translate ucode response to mac80211 tx status control values
263 */
c79dd5b5 264void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
4c424e4c
RR		 265 struct ieee80211_tx_control *control)
266{
267 int rate_index;
268
269 control->antenna_sel_tx =
fde0db31 270 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
4c424e4c
RR		 271 if (rate_n_flags & RATE_MCS_HT_MSK)
272 control->flags |= IEEE80211_TXCTL_OFDM_HT;
273 if (rate_n_flags & RATE_MCS_GF_MSK)
274 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
275 if (rate_n_flags & RATE_MCS_FAT_MSK)
276 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
277 if (rate_n_flags & RATE_MCS_DUP_MSK)
278 control->flags |= IEEE80211_TXCTL_DUP_DATA;
279 if (rate_n_flags & RATE_MCS_SGI_MSK)
280 control->flags |= IEEE80211_TXCTL_SHORT_GI;
281 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
282 * IEEE80211_BAND_2GHZ band as it contains all the rates */
283 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
284 if (rate_index == -1)
285 control->tx_rate = NULL;
286 else
287 control->tx_rate =
288 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
289}
17744ff6 290
c79dd5b5 291int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 292{
293 int rc;
294 unsigned long flags;
295
296 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 297 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 298 if (rc) {
299 spin_unlock_irqrestore(&priv->lock, flags);
300 return rc;
301 }
302
8b6eaea8 303 /* stop Rx DMA */
3395f6e9
TW		 304 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
305 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
b481de9c
ZY		 306 (1 << 24), 1000);
307 if (rc < 0)
308 IWL_ERROR("Can't stop Rx DMA.\n");
309
3395f6e9 310 iwl_release_nic_access(priv);
b481de9c
ZY		 311 spin_unlock_irqrestore(&priv->lock, flags);
312
313 return 0;
314}
315
8614f360
TW		 316/*
317 * EEPROM handlers
318 */
319
320static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
321{
322 u16 eeprom_ver;
323 u16 calib_ver;
324
325 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
326
327 calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
328
329 if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
330 calib_ver < EEPROM_4965_TX_POWER_VERSION)
331 goto err;
332
333 return 0;
334err:
335 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
336 eeprom_ver, EEPROM_4965_EEPROM_VERSION,
337 calib_ver, EEPROM_4965_TX_POWER_VERSION);
338 return -EINVAL;
339
340}
079a2533 341int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 342{
d8609652 343 int ret;
b481de9c
ZY		 344 unsigned long flags;
345
346 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 347 ret = iwl_grab_nic_access(priv);
d8609652 348 if (ret) {
b481de9c 349 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 350 return ret;
b481de9c
ZY		 351 }
352
6f4083aa 353 if (src == IWL_PWR_SRC_VAUX) {
b481de9c 354 u32 val;
d8609652 355 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
6f4083aa 356 &val);
b481de9c 357
6f4083aa 358 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
3395f6e9 359 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 360 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
361 ~APMG_PS_CTRL_MSK_PWR_SRC);
362 }
363 } else {
3395f6e9 364 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 365 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
366 ~APMG_PS_CTRL_MSK_PWR_SRC);
367 }
b481de9c 368
3395f6e9 369 iwl_release_nic_access(priv);
b481de9c
ZY		 370 spin_unlock_irqrestore(&priv->lock, flags);
371
d8609652 372 return ret;
b481de9c
ZY		 373}
374
c79dd5b5 375static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c 376{
059ff826 377 int ret;
b481de9c 378 unsigned long flags;
9ee1ba47 379 unsigned int rb_size;
b481de9c
ZY		 380
381 spin_lock_irqsave(&priv->lock, flags);
059ff826
TW		 382 ret = iwl_grab_nic_access(priv);
383 if (ret) {
b481de9c 384 spin_unlock_irqrestore(&priv->lock, flags);
059ff826 385 return ret;
b481de9c
ZY		 386 }
387
1ea87396 388 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 389 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
390 else
391 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
392
8b6eaea8 393 /* Stop Rx DMA */
3395f6e9 394 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
b481de9c 395
8b6eaea8 396 /* Reset driver's Rx queue write index */
3395f6e9 397 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
8b6eaea8
CB		 398
399 /* Tell device where to find RBD circular buffer in DRAM */
3395f6e9
TW		 400 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
401 rxq->dma_addr >> 8);
b481de9c 402
8b6eaea8 403 /* Tell device where in DRAM to update its Rx status */
3395f6e9 404 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
059ff826
TW		 405 (priv->shared_phys +
406 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
b481de9c 407
8b6eaea8 408 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
3395f6e9
TW		 409 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
410 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
411 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
412 rb_size |
059ff826 413 /* 0x10 << 4 | */
3395f6e9 414 (RX_QUEUE_SIZE_LOG <<
b481de9c
ZY		 415 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
416
417 /*
3395f6e9 418 * iwl_write32(priv,CSR_INT_COAL_REG,0);
b481de9c
ZY		 419 */
420
3395f6e9 421 iwl_release_nic_access(priv);
b481de9c
ZY		 422 spin_unlock_irqrestore(&priv->lock, flags);
423
424 return 0;
425}
426
8b6eaea8 427/* Tell 4965 where to find the "keep warm" buffer */
c79dd5b5 428static int iwl4965_kw_init(struct iwl_priv *priv)
b481de9c
ZY		 429{
430 unsigned long flags;
431 int rc;
432
433 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 434 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 435 if (rc)
436 goto out;
437
4b52c39d 438 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
b481de9c 439 priv->kw.dma_addr >> 4);
3395f6e9 440 iwl_release_nic_access(priv);
b481de9c
ZY		 441out:
442 spin_unlock_irqrestore(&priv->lock, flags);
443 return rc;
444}
445
c79dd5b5 446static int iwl4965_kw_alloc(struct iwl_priv *priv)
b481de9c
ZY		 447{
448 struct pci_dev *dev = priv->pci_dev;
bb8c093b 449 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 450
451 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
452 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
453 if (!kw->v_addr)
454 return -ENOMEM;
455
456 return 0;
457}
458
8b6eaea8
CB		 459/**
460 * iwl4965_kw_free - Free the "keep warm" buffer
461 */
c79dd5b5 462static void iwl4965_kw_free(struct iwl_priv *priv)
b481de9c
ZY		 463{
464 struct pci_dev *dev = priv->pci_dev;
bb8c093b 465 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 466
467 if (kw->v_addr) {
468 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
469 memset(kw, 0, sizeof(*kw));
470 }
471}
472
473/**
474 * iwl4965_txq_ctx_reset - Reset TX queue context
475 * Destroys all DMA structures and initialise them again
476 *
477 * @param priv
478 * @return error code
479 */
c79dd5b5 480static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 481{
482 int rc = 0;
483 int txq_id, slots_num;
484 unsigned long flags;
485
486 iwl4965_kw_free(priv);
487
8b6eaea8 488 /* Free all tx/cmd queues and keep-warm buffer */
bb8c093b 489 iwl4965_hw_txq_ctx_free(priv);
b481de9c 490
8b6eaea8 491 /* Alloc keep-warm buffer */
b481de9c
ZY		 492 rc = iwl4965_kw_alloc(priv);
493 if (rc) {
494 IWL_ERROR("Keep Warm allocation failed");
495 goto error_kw;
496 }
497
498 spin_lock_irqsave(&priv->lock, flags);
499
3395f6e9 500 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 501 if (unlikely(rc)) {
502 IWL_ERROR("TX reset failed");
503 spin_unlock_irqrestore(&priv->lock, flags);
504 goto error_reset;
505 }
506
8b6eaea8 507 /* Turn off all Tx DMA channels */
12a81f60 508 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
3395f6e9 509 iwl_release_nic_access(priv);
b481de9c
ZY		 510 spin_unlock_irqrestore(&priv->lock, flags);
511
8b6eaea8 512 /* Tell 4965 where to find the keep-warm buffer */
b481de9c
ZY		 513 rc = iwl4965_kw_init(priv);
514 if (rc) {
515 IWL_ERROR("kw_init failed\n");
516 goto error_reset;
517 }
518
8b6eaea8
CB		 519 /* Alloc and init all (default 16) Tx queues,
520 * including the command queue (#4) */
5425e490 521 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 522 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
523 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 524 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 525 txq_id);
526 if (rc) {
527 IWL_ERROR("Tx %d queue init failed\n", txq_id);
528 goto error;
529 }
530 }
531
532 return rc;
533
534 error:
bb8c093b 535 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 536 error_reset:
537 iwl4965_kw_free(priv);
538 error_kw:
539 return rc;
540}
91238714 541static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 542{
b481de9c 543 unsigned long flags;
91238714 544 int ret = 0;
b481de9c 545
b481de9c 546 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 547 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 548 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 549
91238714
TW		 550 /* set "initialization complete" bit to move adapter
551 * D0U* --> D0A* state */
3395f6e9 552 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 553
91238714
TW		 554 /* wait for clock stabilization */
555 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
556 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
557 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
558 if (ret < 0) {
559 IWL_DEBUG_INFO("Failed to init the card\n");
560 goto out;
b481de9c
ZY		 561 }
562
91238714
TW		 563 ret = iwl_grab_nic_access(priv);
564 if (ret)
565 goto out;
b481de9c 566
91238714 567 /* enable DMA */
3395f6e9
TW		 568 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
569 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 570
571 udelay(20);
572
3395f6e9 573 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 574 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 575
3395f6e9 576 iwl_release_nic_access(priv);
91238714
TW		 577out:
578 spin_unlock_irqrestore(&priv->lock, flags);
579 return ret;
580}
581
694cc56d
TW		 582
583static void iwl4965_nic_config(struct iwl_priv *priv)
91238714
TW		 584{
585 unsigned long flags;
91238714 586 u32 val;
694cc56d
TW		 587 u16 radio_cfg;
588 u8 val_link;
6f4083aa 589
b481de9c
ZY		 590 spin_lock_irqsave(&priv->lock, flags);
591
b661c819 592 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
b481de9c
ZY		 593 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
594 /* Enable No Snoop field */
595 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
596 val & ~(1 << 11));
597 }
598
b481de9c
ZY		 599 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
600
601 /* disable L1 entry -- workaround for pre-B1 */
602 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
603
694cc56d 604 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
b481de9c 605
694cc56d
TW		 606 /* write radio config values to register */
607 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
608 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
609 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
610 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
611 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
b481de9c 612
694cc56d 613 /* set CSR_HW_CONFIG_REG for uCode use */
3395f6e9 614 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
a395b920
TW		 615 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
616 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 617
694cc56d
TW		 618 priv->calib_info = (struct iwl_eeprom_calib_info *)
619 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
620
621 spin_unlock_irqrestore(&priv->lock, flags);
622}
623
624
625int iwl4965_hw_nic_init(struct iwl_priv *priv)
626{
627 unsigned long flags;
628 struct iwl4965_rx_queue *rxq = &priv->rxq;
629 int ret;
630
631 /* nic_init */
632 priv->cfg->ops->lib->apm_ops.init(priv);
633
634 spin_lock_irqsave(&priv->lock, flags);
635 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
b481de9c
ZY		 636 spin_unlock_irqrestore(&priv->lock, flags);
637
694cc56d
TW		 638 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
639
640 priv->cfg->ops->lib->apm_ops.config(priv);
641
bb8c093b 642 iwl4965_hw_card_show_info(priv);
b481de9c
ZY		 643
644 /* end nic_init */
645
646 /* Allocate the RX queue, or reset if it is already allocated */
647 if (!rxq->bd) {
91238714
TW		 648 ret = iwl4965_rx_queue_alloc(priv);
649 if (ret) {
b481de9c
ZY		 650 IWL_ERROR("Unable to initialize Rx queue\n");
651 return -ENOMEM;
652 }
653 } else
bb8c093b 654 iwl4965_rx_queue_reset(priv, rxq);
b481de9c 655
bb8c093b 656 iwl4965_rx_replenish(priv);
b481de9c
ZY		 657
658 iwl4965_rx_init(priv, rxq);
659
660 spin_lock_irqsave(&priv->lock, flags);
661
662 rxq->need_update = 1;
bb8c093b 663 iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 664
665 spin_unlock_irqrestore(&priv->lock, flags);
8b6eaea8
CB		 666
667 /* Allocate and init all Tx and Command queues */
91238714
TW		 668 ret = iwl4965_txq_ctx_reset(priv);
669 if (ret)
670 return ret;
b481de9c
ZY		 671
672 set_bit(STATUS_INIT, &priv->status);
673
674 return 0;
675}
676
c79dd5b5 677int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 678{
679 int rc = 0;
680 u32 reg_val;
681 unsigned long flags;
682
683 spin_lock_irqsave(&priv->lock, flags);
684
685 /* set stop master bit */
3395f6e9 686 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 687
3395f6e9 688 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 689
690 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
691 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
692 IWL_DEBUG_INFO("Card in power save, master is already "
693 "stopped\n");
694 else {
3395f6e9 695 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 696 CSR_RESET_REG_FLAG_MASTER_DISABLED,
697 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
698 if (rc < 0) {
699 spin_unlock_irqrestore(&priv->lock, flags);
700 return rc;
701 }
702 }
703
704 spin_unlock_irqrestore(&priv->lock, flags);
705 IWL_DEBUG_INFO("stop master\n");
706
707 return rc;
708}
709
8b6eaea8
CB		 710/**
711 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
712 */
c79dd5b5 713void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c
ZY		 714{
715
716 int txq_id;
717 unsigned long flags;
718
8b6eaea8 719 /* Stop each Tx DMA channel, and wait for it to be idle */
5425e490 720 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c 721 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 722 if (iwl_grab_nic_access(priv)) {
b481de9c
ZY		 723 spin_unlock_irqrestore(&priv->lock, flags);
724 continue;
725 }
726
3395f6e9 727 iwl_write_direct32(priv,
4b52c39d
EG		 728 FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
729 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
730 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
3395f6e9
TW		 731 (txq_id), 200);
732 iwl_release_nic_access(priv);
b481de9c
ZY		 733 spin_unlock_irqrestore(&priv->lock, flags);
734 }
735
8b6eaea8 736 /* Deallocate memory for all Tx queues */
bb8c093b 737 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 738}
739
c79dd5b5 740int iwl4965_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 741{
742 int rc = 0;
743 unsigned long flags;
744
bb8c093b 745 iwl4965_hw_nic_stop_master(priv);
b481de9c
ZY		 746
747 spin_lock_irqsave(&priv->lock, flags);
748
3395f6e9 749 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 750
751 udelay(10);
752
3395f6e9
TW		 753 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
754 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 755 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
756 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
757
758 udelay(10);
759
3395f6e9 760 rc = iwl_grab_nic_access(priv);
b481de9c 761 if (!rc) {
3395f6e9
TW		 762 iwl_write_prph(priv, APMG_CLK_EN_REG,
763 APMG_CLK_VAL_DMA_CLK_RQT |
764 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 765
766 udelay(10);
767
3395f6e9
TW		 768 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
769 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 770
3395f6e9 771 iwl_release_nic_access(priv);
b481de9c
ZY		 772 }
773
774 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
775 wake_up_interruptible(&priv->wait_command_queue);
776
777 spin_unlock_irqrestore(&priv->lock, flags);
778
779 return rc;
780
781}
782
783#define REG_RECALIB_PERIOD (60)
784
785/**
786 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
787 *
49ea8596 788 * This callback is provided in order to send a statistics request.
b481de9c
ZY		 789 *
790 * This timer function is continually reset to execute within
791 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
792 * was received. We need to ensure we receive the statistics in order
49ea8596 793 * to update the temperature used for calibrating the TXPOWER.
b481de9c
ZY		 794 */
795static void iwl4965_bg_statistics_periodic(unsigned long data)
796{
c79dd5b5 797 struct iwl_priv *priv = (struct iwl_priv *)data;
b481de9c 798
b481de9c
ZY		 799 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
800 return;
801
49ea8596 802 iwl_send_statistics_request(priv, CMD_ASYNC);
b481de9c
ZY		 803}
804
c79dd5b5 805void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 806{
bb8c093b 807 struct iwl4965_ct_kill_config cmd;
b481de9c 808 unsigned long flags;
857485c0 809 int ret = 0;
b481de9c
ZY		 810
811 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 812 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 813 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
814 spin_unlock_irqrestore(&priv->lock, flags);
815
099b40b7 816 cmd.critical_temperature_R =
b73cdf27
EG		 817 cpu_to_le32(priv->hw_params.ct_kill_threshold);
818
857485c0
TW		 819 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
820 sizeof(cmd), &cmd);
821 if (ret)
b481de9c
ZY		 822 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
823 else
b73cdf27
EG		 824 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
825 "critical temperature is %d\n",
826 cmd.critical_temperature_R);
b481de9c
ZY		 827}
828
f0832f13 829#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 830
831/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
832 * Called after every association, but this runs only once!
833 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 834static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 835{
f0832f13 836 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 837
3109ece1 838 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 839 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 840
841 memset(&cmd, 0, sizeof(cmd));
842 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
843 cmd.diff_gain_a = 0;
844 cmd.diff_gain_b = 0;
845 cmd.diff_gain_c = 0;
f0832f13
EG		 846 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
847 sizeof(cmd), &cmd))
848 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 849 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
850 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
851 }
b481de9c
ZY		 852}
853
f0832f13
EG		 854static void iwl4965_gain_computation(struct iwl_priv *priv,
855 u32 *average_noise,
856 u16 min_average_noise_antenna_i,
857 u32 min_average_noise)
b481de9c 858{
f0832f13
EG		 859 int i, ret;
860 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 861
f0832f13 862 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 863
f0832f13
EG		 864 for (i = 0; i < NUM_RX_CHAINS; i++) {
865 s32 delta_g = 0;
b481de9c 866
f0832f13
EG		 867 if (!(data->disconn_array[i]) &&
868 (data->delta_gain_code[i] ==
b481de9c 869 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 870 delta_g = average_noise[i] - min_average_noise;
871 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
872 data->delta_gain_code[i] =
873 min(data->delta_gain_code[i],
874 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
875
876 data->delta_gain_code[i] =
877 (data->delta_gain_code[i] | (1 << 2));
878 } else {
879 data->delta_gain_code[i] = 0;
b481de9c 880 }
b481de9c 881 }
f0832f13
EG		 882 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
883 data->delta_gain_code[0],
884 data->delta_gain_code[1],
885 data->delta_gain_code[2]);
b481de9c 886
f0832f13
EG		 887 /* Differential gain gets sent to uCode only once */
888 if (!data->radio_write) {
889 struct iwl4965_calibration_cmd cmd;
890 data->radio_write = 1;
b481de9c 891
f0832f13
EG		 892 memset(&cmd, 0, sizeof(cmd));
893 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
894 cmd.diff_gain_a = data->delta_gain_code[0];
895 cmd.diff_gain_b = data->delta_gain_code[1];
896 cmd.diff_gain_c = data->delta_gain_code[2];
897 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
898 sizeof(cmd), &cmd);
899 if (ret)
900 IWL_DEBUG_CALIB("fail sending cmd "
901 "REPLY_PHY_CALIBRATION_CMD \n");
902
903 /* TODO we might want recalculate
904 * rx_chain in rxon cmd */
905
906 /* Mark so we run this algo only once! */
907 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 908 }
f0832f13
EG		 909 data->chain_noise_a = 0;
910 data->chain_noise_b = 0;
911 data->chain_noise_c = 0;
912 data->chain_signal_a = 0;
913 data->chain_signal_b = 0;
914 data->chain_signal_c = 0;
915 data->beacon_count = 0;
b481de9c
ZY		 916}
917
918static void iwl4965_bg_sensitivity_work(struct work_struct *work)
919{
c79dd5b5 920 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 921 sensitivity_work);
922
923 mutex_lock(&priv->mutex);
924
925 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
926 test_bit(STATUS_SCANNING, &priv->status)) {
927 mutex_unlock(&priv->mutex);
928 return;
929 }
930
931 if (priv->start_calib) {
f0832f13
EG		 932 iwl_chain_noise_calibration(priv, &priv->statistics);
933
934 iwl_sensitivity_calibration(priv, &priv->statistics);
b481de9c
ZY		 935 }
936
937 mutex_unlock(&priv->mutex);
938 return;
939}
f0832f13 940#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c
ZY		 941
942static void iwl4965_bg_txpower_work(struct work_struct *work)
943{
c79dd5b5 944 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 945 txpower_work);
946
947 /* If a scan happened to start before we got here
948 * then just return; the statistics notification will
949 * kick off another scheduled work to compensate for
950 * any temperature delta we missed here. */
951 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
952 test_bit(STATUS_SCANNING, &priv->status))
953 return;
954
955 mutex_lock(&priv->mutex);
956
957 /* Regardless of if we are assocaited, we must reconfigure the
958 * TX power since frames can be sent on non-radar channels while
959 * not associated */
bb8c093b 960 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 961
962 /* Update last_temperature to keep is_calib_needed from running
963 * when it isn't needed... */
964 priv->last_temperature = priv->temperature;
965
966 mutex_unlock(&priv->mutex);
967}
968
969/*
970 * Acquire priv->lock before calling this function !
971 */
c79dd5b5 972static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 973{
3395f6e9 974 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 975 (index & 0xff) | (txq_id << 8));
12a81f60 976 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 977}
978
8b6eaea8
CB		 979/**
980 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
981 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
982 * @scd_retry: (1) Indicates queue will be used in aggregation mode
983 *
984 * NOTE: Acquire priv->lock before calling this function !
b481de9c 985 */
c79dd5b5 986static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
bb8c093b 987 struct iwl4965_tx_queue *txq,
b481de9c
ZY		 988 int tx_fifo_id, int scd_retry)
989{
990 int txq_id = txq->q.id;
8b6eaea8
CB		 991
992 /* Find out whether to activate Tx queue */
b481de9c
ZY		 993 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
994
8b6eaea8 995 /* Set up and activate */
12a81f60 996 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 997 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
998 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
999 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
1000 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1001 IWL49_SCD_QUEUE_STTS_REG_MSK);
b481de9c
ZY		 1002
1003 txq->sched_retry = scd_retry;
1004
1005 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 1006 active ? "Activate" : "Deactivate",
b481de9c
ZY		 1007 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1008}
1009
1010static const u16 default_queue_to_tx_fifo[] = {
1011 IWL_TX_FIFO_AC3,
1012 IWL_TX_FIFO_AC2,
1013 IWL_TX_FIFO_AC1,
1014 IWL_TX_FIFO_AC0,
038669e4 1015 IWL49_CMD_FIFO_NUM,
b481de9c
ZY		 1016 IWL_TX_FIFO_HCCA_1,
1017 IWL_TX_FIFO_HCCA_2
1018};
1019
c79dd5b5 1020static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1021{
1022 set_bit(txq_id, &priv->txq_ctx_active_msk);
1023}
1024
c79dd5b5 1025static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1026{
1027 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1028}
1029
c79dd5b5 1030int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 1031{
1032 u32 a;
1033 int i = 0;
1034 unsigned long flags;
857485c0 1035 int ret;
b481de9c
ZY		 1036
1037 spin_lock_irqsave(&priv->lock, flags);
1038
f0832f13 1039#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c 1040 memset(&(priv->sensitivity_data), 0,
f0832f13 1041 sizeof(struct iwl_sensitivity_data));
b481de9c 1042 memset(&(priv->chain_noise_data), 0,
f0832f13 1043 sizeof(struct iwl_chain_noise_data));
b481de9c
ZY		 1044 for (i = 0; i < NUM_RX_CHAINS; i++)
1045 priv->chain_noise_data.delta_gain_code[i] =
1046 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
f0832f13 1047#endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
3395f6e9 1048 ret = iwl_grab_nic_access(priv);
857485c0 1049 if (ret) {
b481de9c 1050 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 1051 return ret;
b481de9c
ZY		 1052 }
1053
8b6eaea8 1054 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 1055 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
038669e4
EG		 1056 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
1057 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 1058 iwl_write_targ_mem(priv, a, 0);
038669e4 1059 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 1060 iwl_write_targ_mem(priv, a, 0);
5425e490 1061 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 1062 iwl_write_targ_mem(priv, a, 0);
b481de9c 1063
8b6eaea8 1064 /* Tel 4965 where to find Tx byte count tables */
12a81f60 1065 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 1066 (priv->shared_phys +
bb8c093b 1067 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 1068
1069 /* Disable chain mode for all queues */
12a81f60 1070 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 1071
8b6eaea8 1072 /* Initialize each Tx queue (including the command queue) */
5425e490 1073 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 1074
1075 /* TFD circular buffer read/write indexes */
12a81f60 1076 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 1077 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 1078
1079 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 1080 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 1081 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
1082 (SCD_WIN_SIZE <<
1083 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1084 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 1085
1086 /* Frame limit */
3395f6e9 1087 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 1088 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
1089 sizeof(u32),
1090 (SCD_FRAME_LIMIT <<
1091 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1092 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c
ZY		 1093
1094 }
12a81f60 1095 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 1096 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 1097
8b6eaea8 1098 /* Activate all Tx DMA/FIFO channels */
12a81f60 1099 iwl_write_prph(priv, IWL49_SCD_TXFACT,
b481de9c
ZY		 1100 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1101
1102 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 1103
1104 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 1105 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1106 int ac = default_queue_to_tx_fifo[i];
1107 iwl4965_txq_ctx_activate(priv, i);
1108 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1109 }
1110
3395f6e9 1111 iwl_release_nic_access(priv);
b481de9c
ZY		 1112 spin_unlock_irqrestore(&priv->lock, flags);
1113
49ea8596
EG		 1114 /* Ask for statistics now, the uCode will send statistics notification
1115 * periodically after association */
1116 iwl_send_statistics_request(priv, CMD_ASYNC);
857485c0 1117 return ret;
b481de9c
ZY		 1118}
1119
f0832f13
EG		 1120#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1121static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1122 .min_nrg_cck = 97,
1123 .max_nrg_cck = 0,
1124
1125 .auto_corr_min_ofdm = 85,
1126 .auto_corr_min_ofdm_mrc = 170,
1127 .auto_corr_min_ofdm_x1 = 105,
1128 .auto_corr_min_ofdm_mrc_x1 = 220,
1129
1130 .auto_corr_max_ofdm = 120,
1131 .auto_corr_max_ofdm_mrc = 210,
1132 .auto_corr_max_ofdm_x1 = 140,
1133 .auto_corr_max_ofdm_mrc_x1 = 270,
1134
1135 .auto_corr_min_cck = 125,
1136 .auto_corr_max_cck = 200,
1137 .auto_corr_min_cck_mrc = 200,
1138 .auto_corr_max_cck_mrc = 400,
1139
1140 .nrg_th_cck = 100,
1141 .nrg_th_ofdm = 100,
1142};
1143#endif
1144
8b6eaea8 1145/**
5425e490 1146 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 1147 *
1148 * Called when initializing driver
1149 */
5425e490 1150int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 1151{
316c30d9 1152
038669e4 1153 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1ea87396 1154 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 1155 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
038669e4 1156 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
059ff826 1157 return -EINVAL;
316c30d9 1158 }
b481de9c 1159
5425e490 1160 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
099b40b7 1161 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
5425e490
TW		 1162 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1163 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1164 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 1165 if (priv->cfg->mod_params->amsdu_size_8K)
5425e490 1166 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
9ee1ba47 1167 else
5425e490
TW		 1168 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1169 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1170 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1171 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822 1172
099b40b7
RR		 1173 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1174 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1175 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1176 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1177
ec35cf2a
TW		 1178 priv->hw_params.tx_chains_num = 2;
1179 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 1180 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
1181 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 1182 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1183
f0832f13
EG		 1184#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1185 priv->hw_params.sens = &iwl4965_sensitivity;
1186#endif
3e82a822 1187
059ff826 1188 return 0;
b481de9c
ZY		 1189}
1190
1191/**
bb8c093b 1192 * iwl4965_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1193 *
1194 * Destroy all TX DMA queues and structures
1195 */
c79dd5b5 1196void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1197{
1198 int txq_id;
1199
1200 /* Tx queues */
5425e490 1201 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
bb8c093b 1202 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c 1203
8b6eaea8 1204 /* Keep-warm buffer */
b481de9c
ZY		 1205 iwl4965_kw_free(priv);
1206}
1207
1208/**
8b6eaea8 1209 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
b481de9c 1210 *
8b6eaea8
CB		 1211 * Does NOT advance any TFD circular buffer read/write indexes
1212 * Does NOT free the TFD itself (which is within circular buffer)
b481de9c 1213 */
c79dd5b5 1214int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 1215{
bb8c093b
CH		 1216 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1217 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 1218 struct pci_dev *dev = priv->pci_dev;
1219 int i;
1220 int counter = 0;
1221 int index, is_odd;
1222
8b6eaea8 1223 /* Host command buffers stay mapped in memory, nothing to clean */
b481de9c 1224 if (txq->q.id == IWL_CMD_QUEUE_NUM)
b481de9c
ZY		 1225 return 0;
1226
8b6eaea8 1227 /* Sanity check on number of chunks */
b481de9c
ZY		 1228 counter = IWL_GET_BITS(*bd, num_tbs);
1229 if (counter > MAX_NUM_OF_TBS) {
1230 IWL_ERROR("Too many chunks: %i\n", counter);
1231 /* @todo issue fatal error, it is quite serious situation */
1232 return 0;
1233 }
1234
8b6eaea8
CB		 1235 /* Unmap chunks, if any.
1236 * TFD info for odd chunks is different format than for even chunks. */
b481de9c
ZY		 1237 for (i = 0; i < counter; i++) {
1238 index = i / 2;
1239 is_odd = i & 0x1;
1240
1241 if (is_odd)
1242 pci_unmap_single(
1243 dev,
1244 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1245 (IWL_GET_BITS(bd->pa[index],
1246 tb2_addr_hi20) << 16),
1247 IWL_GET_BITS(bd->pa[index], tb2_len),
1248 PCI_DMA_TODEVICE);
1249
1250 else if (i > 0)
1251 pci_unmap_single(dev,
1252 le32_to_cpu(bd->pa[index].tb1_addr),
1253 IWL_GET_BITS(bd->pa[index], tb1_len),
1254 PCI_DMA_TODEVICE);
1255
8b6eaea8 1256 /* Free SKB, if any, for this chunk */
fc4b6853
TW		 1257 if (txq->txb[txq->q.read_ptr].skb[i]) {
1258 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
b481de9c
ZY		 1259
1260 dev_kfree_skb(skb);
fc4b6853 1261 txq->txb[txq->q.read_ptr].skb[i] = NULL;
b481de9c
ZY		 1262 }
1263 }
1264 return 0;
1265}
1266
5da4b55f
MA		 1267/* set card power command */
1268static int iwl4965_set_power(struct iwl_priv *priv,
1269 void *cmd)
1270{
1271 int ret = 0;
1272
1273 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1274 sizeof(struct iwl4965_powertable_cmd),
1275 cmd, NULL);
1276 return ret;
1277}
c79dd5b5 1278int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1279{
bb8c093b 1280 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
b481de9c
ZY		 1281 return -EINVAL;
1282}
1283
1284static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1285{
1286 s32 sign = 1;
1287
1288 if (num < 0) {
1289 sign = -sign;
1290 num = -num;
1291 }
1292 if (denom < 0) {
1293 sign = -sign;
1294 denom = -denom;
1295 }
1296 *res = 1;
1297 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1298
1299 return 1;
1300}
1301
8b6eaea8
CB		 1302/**
1303 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1304 *
1305 * Determines power supply voltage compensation for txpower calculations.
1306 * Returns number of 1/2-dB steps to subtract from gain table index,
1307 * to compensate for difference between power supply voltage during
1308 * factory measurements, vs. current power supply voltage.
1309 *
1310 * Voltage indication is higher for lower voltage.
1311 * Lower voltage requires more gain (lower gain table index).
1312 */
b481de9c
ZY		 1313static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1314 s32 current_voltage)
1315{
1316 s32 comp = 0;
1317
1318 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1319 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1320 return 0;
1321
1322 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1323 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1324
1325 if (current_voltage > eeprom_voltage)
1326 comp *= 2;
1327 if ((comp < -2) || (comp > 2))
1328 comp = 0;
1329
1330 return comp;
1331}
1332
bf85ea4f 1333static const struct iwl_channel_info *
c79dd5b5 1334iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
8318d78a 1335 enum ieee80211_band band, u16 channel)
b481de9c 1336{
bf85ea4f 1337 const struct iwl_channel_info *ch_info;
b481de9c 1338
8622e705 1339 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 1340
1341 if (!is_channel_valid(ch_info))
1342 return NULL;
1343
1344 return ch_info;
1345}
1346
1347static s32 iwl4965_get_tx_atten_grp(u16 channel)
1348{
1349 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1350 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1351 return CALIB_CH_GROUP_5;
1352
1353 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1354 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1355 return CALIB_CH_GROUP_1;
1356
1357 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1358 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1359 return CALIB_CH_GROUP_2;
1360
1361 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1362 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1363 return CALIB_CH_GROUP_3;
1364
1365 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1366 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1367 return CALIB_CH_GROUP_4;
1368
1369 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1370 return -1;
1371}
1372
c79dd5b5 1373static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 1374{
1375 s32 b = -1;
1376
1377 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 1378 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 1379 continue;
1380
073d3f5f
TW		 1381 if ((channel >= priv->calib_info->band_info[b].ch_from)
1382 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 1383 break;
1384 }
1385
1386 return b;
1387}
1388
1389static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1390{
1391 s32 val;
1392
1393 if (x2 == x1)
1394 return y1;
1395 else {
1396 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1397 return val + y2;
1398 }
1399}
1400
8b6eaea8
CB		 1401/**
1402 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1403 *
1404 * Interpolates factory measurements from the two sample channels within a
1405 * sub-band, to apply to channel of interest. Interpolation is proportional to
1406 * differences in channel frequencies, which is proportional to differences
1407 * in channel number.
1408 */
c79dd5b5 1409static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 1410 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 1411{
1412 s32 s = -1;
1413 u32 c;
1414 u32 m;
073d3f5f
TW		 1415 const struct iwl_eeprom_calib_measure *m1;
1416 const struct iwl_eeprom_calib_measure *m2;
1417 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 1418 u32 ch_i1;
1419 u32 ch_i2;
1420
1421 s = iwl4965_get_sub_band(priv, channel);
1422 if (s >= EEPROM_TX_POWER_BANDS) {
1423 IWL_ERROR("Tx Power can not find channel %d ", channel);
1424 return -1;
1425 }
1426
073d3f5f
TW		 1427 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1428 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 1429 chan_info->ch_num = (u8) channel;
1430
1431 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1432 channel, s, ch_i1, ch_i2);
1433
1434 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1435 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 1436 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 1437 measurements[c][m]);
073d3f5f 1438 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 1439 measurements[c][m]);
1440 omeas = &(chan_info->measurements[c][m]);
1441
1442 omeas->actual_pow =
1443 (u8) iwl4965_interpolate_value(channel, ch_i1,
1444 m1->actual_pow,
1445 ch_i2,
1446 m2->actual_pow);
1447 omeas->gain_idx =
1448 (u8) iwl4965_interpolate_value(channel, ch_i1,
1449 m1->gain_idx, ch_i2,
1450 m2->gain_idx);
1451 omeas->temperature =
1452 (u8) iwl4965_interpolate_value(channel, ch_i1,
1453 m1->temperature,
1454 ch_i2,
1455 m2->temperature);
1456 omeas->pa_det =
1457 (s8) iwl4965_interpolate_value(channel, ch_i1,
1458 m1->pa_det, ch_i2,
1459 m2->pa_det);
1460
1461 IWL_DEBUG_TXPOWER
1462 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1463 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1464 IWL_DEBUG_TXPOWER
1465 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1466 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1467 IWL_DEBUG_TXPOWER
1468 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1469 m1->pa_det, m2->pa_det, omeas->pa_det);
1470 IWL_DEBUG_TXPOWER
1471 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1472 m1->temperature, m2->temperature,
1473 omeas->temperature);
1474 }
1475 }
1476
1477 return 0;
1478}
1479
1480/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1481 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1482static s32 back_off_table[] = {
1483 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1484 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1485 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1486 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1487 10 /* CCK */
1488};
1489
1490/* Thermal compensation values for txpower for various frequency ranges ...
1491 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1492static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1493 s32 degrees_per_05db_a;
1494 s32 degrees_per_05db_a_denom;
1495} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1496 {9, 2}, /* group 0 5.2, ch 34-43 */
1497 {4, 1}, /* group 1 5.2, ch 44-70 */
1498 {4, 1}, /* group 2 5.2, ch 71-124 */
1499 {4, 1}, /* group 3 5.2, ch 125-200 */
1500 {3, 1} /* group 4 2.4, ch all */
1501};
1502
1503static s32 get_min_power_index(s32 rate_power_index, u32 band)
1504{
1505 if (!band) {
1506 if ((rate_power_index & 7) <= 4)
1507 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1508 }
1509 return MIN_TX_GAIN_INDEX;
1510}
1511
1512struct gain_entry {
1513 u8 dsp;
1514 u8 radio;
1515};
1516
1517static const struct gain_entry gain_table[2][108] = {
1518 /* 5.2GHz power gain index table */
1519 {
1520 {123, 0x3F}, /* highest txpower */
1521 {117, 0x3F},
1522 {110, 0x3F},
1523 {104, 0x3F},
1524 {98, 0x3F},
1525 {110, 0x3E},
1526 {104, 0x3E},
1527 {98, 0x3E},
1528 {110, 0x3D},
1529 {104, 0x3D},
1530 {98, 0x3D},
1531 {110, 0x3C},
1532 {104, 0x3C},
1533 {98, 0x3C},
1534 {110, 0x3B},
1535 {104, 0x3B},
1536 {98, 0x3B},
1537 {110, 0x3A},
1538 {104, 0x3A},
1539 {98, 0x3A},
1540 {110, 0x39},
1541 {104, 0x39},
1542 {98, 0x39},
1543 {110, 0x38},
1544 {104, 0x38},
1545 {98, 0x38},
1546 {110, 0x37},
1547 {104, 0x37},
1548 {98, 0x37},
1549 {110, 0x36},
1550 {104, 0x36},
1551 {98, 0x36},
1552 {110, 0x35},
1553 {104, 0x35},
1554 {98, 0x35},
1555 {110, 0x34},
1556 {104, 0x34},
1557 {98, 0x34},
1558 {110, 0x33},
1559 {104, 0x33},
1560 {98, 0x33},
1561 {110, 0x32},
1562 {104, 0x32},
1563 {98, 0x32},
1564 {110, 0x31},
1565 {104, 0x31},
1566 {98, 0x31},
1567 {110, 0x30},
1568 {104, 0x30},
1569 {98, 0x30},
1570 {110, 0x25},
1571 {104, 0x25},
1572 {98, 0x25},
1573 {110, 0x24},
1574 {104, 0x24},
1575 {98, 0x24},
1576 {110, 0x23},
1577 {104, 0x23},
1578 {98, 0x23},
1579 {110, 0x22},
1580 {104, 0x18},
1581 {98, 0x18},
1582 {110, 0x17},
1583 {104, 0x17},
1584 {98, 0x17},
1585 {110, 0x16},
1586 {104, 0x16},
1587 {98, 0x16},
1588 {110, 0x15},
1589 {104, 0x15},
1590 {98, 0x15},
1591 {110, 0x14},
1592 {104, 0x14},
1593 {98, 0x14},
1594 {110, 0x13},
1595 {104, 0x13},
1596 {98, 0x13},
1597 {110, 0x12},
1598 {104, 0x08},
1599 {98, 0x08},
1600 {110, 0x07},
1601 {104, 0x07},
1602 {98, 0x07},
1603 {110, 0x06},
1604 {104, 0x06},
1605 {98, 0x06},
1606 {110, 0x05},
1607 {104, 0x05},
1608 {98, 0x05},
1609 {110, 0x04},
1610 {104, 0x04},
1611 {98, 0x04},
1612 {110, 0x03},
1613 {104, 0x03},
1614 {98, 0x03},
1615 {110, 0x02},
1616 {104, 0x02},
1617 {98, 0x02},
1618 {110, 0x01},
1619 {104, 0x01},
1620 {98, 0x01},
1621 {110, 0x00},
1622 {104, 0x00},
1623 {98, 0x00},
1624 {93, 0x00},
1625 {88, 0x00},
1626 {83, 0x00},
1627 {78, 0x00},
1628 },
1629 /* 2.4GHz power gain index table */
1630 {
1631 {110, 0x3f}, /* highest txpower */
1632 {104, 0x3f},
1633 {98, 0x3f},
1634 {110, 0x3e},
1635 {104, 0x3e},
1636 {98, 0x3e},
1637 {110, 0x3d},
1638 {104, 0x3d},
1639 {98, 0x3d},
1640 {110, 0x3c},
1641 {104, 0x3c},
1642 {98, 0x3c},
1643 {110, 0x3b},
1644 {104, 0x3b},
1645 {98, 0x3b},
1646 {110, 0x3a},
1647 {104, 0x3a},
1648 {98, 0x3a},
1649 {110, 0x39},
1650 {104, 0x39},
1651 {98, 0x39},
1652 {110, 0x38},
1653 {104, 0x38},
1654 {98, 0x38},
1655 {110, 0x37},
1656 {104, 0x37},
1657 {98, 0x37},
1658 {110, 0x36},
1659 {104, 0x36},
1660 {98, 0x36},
1661 {110, 0x35},
1662 {104, 0x35},
1663 {98, 0x35},
1664 {110, 0x34},
1665 {104, 0x34},
1666 {98, 0x34},
1667 {110, 0x33},
1668 {104, 0x33},
1669 {98, 0x33},
1670 {110, 0x32},
1671 {104, 0x32},
1672 {98, 0x32},
1673 {110, 0x31},
1674 {104, 0x31},
1675 {98, 0x31},
1676 {110, 0x30},
1677 {104, 0x30},
1678 {98, 0x30},
1679 {110, 0x6},
1680 {104, 0x6},
1681 {98, 0x6},
1682 {110, 0x5},
1683 {104, 0x5},
1684 {98, 0x5},
1685 {110, 0x4},
1686 {104, 0x4},
1687 {98, 0x4},
1688 {110, 0x3},
1689 {104, 0x3},
1690 {98, 0x3},
1691 {110, 0x2},
1692 {104, 0x2},
1693 {98, 0x2},
1694 {110, 0x1},
1695 {104, 0x1},
1696 {98, 0x1},
1697 {110, 0x0},
1698 {104, 0x0},
1699 {98, 0x0},
1700 {97, 0},
1701 {96, 0},
1702 {95, 0},
1703 {94, 0},
1704 {93, 0},
1705 {92, 0},
1706 {91, 0},
1707 {90, 0},
1708 {89, 0},
1709 {88, 0},
1710 {87, 0},
1711 {86, 0},
1712 {85, 0},
1713 {84, 0},
1714 {83, 0},
1715 {82, 0},
1716 {81, 0},
1717 {80, 0},
1718 {79, 0},
1719 {78, 0},
1720 {77, 0},
1721 {76, 0},
1722 {75, 0},
1723 {74, 0},
1724 {73, 0},
1725 {72, 0},
1726 {71, 0},
1727 {70, 0},
1728 {69, 0},
1729 {68, 0},
1730 {67, 0},
1731 {66, 0},
1732 {65, 0},
1733 {64, 0},
1734 {63, 0},
1735 {62, 0},
1736 {61, 0},
1737 {60, 0},
1738 {59, 0},
1739 }
1740};
1741
c79dd5b5 1742static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1743 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1744 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1745{
1746 u8 saturation_power;
1747 s32 target_power;
1748 s32 user_target_power;
1749 s32 power_limit;
1750 s32 current_temp;
1751 s32 reg_limit;
1752 s32 current_regulatory;
1753 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1754 int i;
1755 int c;
bf85ea4f 1756 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1757 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1758 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1759 s16 voltage;
1760 s32 init_voltage;
1761 s32 voltage_compensation;
1762 s32 degrees_per_05db_num;
1763 s32 degrees_per_05db_denom;
1764 s32 factory_temp;
1765 s32 temperature_comp[2];
1766 s32 factory_gain_index[2];
1767 s32 factory_actual_pwr[2];
1768 s32 power_index;
1769
1770 /* Sanity check requested level (dBm) */
1771 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1772 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1773 priv->user_txpower_limit);
1774 return -EINVAL;
1775 }
1776 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1777 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1778 priv->user_txpower_limit);
1779 return -EINVAL;
1780 }
1781
1782 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1783 * are used for indexing into txpower table) */
1784 user_target_power = 2 * priv->user_txpower_limit;
1785
1786 /* Get current (RXON) channel, band, width */
1787 ch_info =
8318d78a 1788 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
b481de9c
ZY		 1789
1790 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1791 is_fat);
1792
1793 if (!ch_info)
1794 return -EINVAL;
1795
1796 /* get txatten group, used to select 1) thermal txpower adjustment
1797 * and 2) mimo txpower balance between Tx chains. */
1798 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1799 if (txatten_grp < 0)
1800 return -EINVAL;
1801
1802 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1803 channel, txatten_grp);
1804
1805 if (is_fat) {
1806 if (ctrl_chan_high)
1807 channel -= 2;
1808 else
1809 channel += 2;
1810 }
1811
1812 /* hardware txpower limits ...
1813 * saturation (clipping distortion) txpowers are in half-dBm */
1814 if (band)
073d3f5f 1815 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1816 else
073d3f5f 1817 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1818
1819 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1820 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1821 if (band)
1822 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1823 else
1824 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1825 }
1826
1827 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1828 * max_power_avg values are in dBm, convert * 2 */
1829 if (is_fat)
1830 reg_limit = ch_info->fat_max_power_avg * 2;
1831 else
1832 reg_limit = ch_info->max_power_avg * 2;
1833
1834 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1835 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1836 if (band)
1837 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1838 else
1839 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1840 }
1841
1842 /* Interpolate txpower calibration values for this channel,
1843 * based on factory calibration tests on spaced channels. */
1844 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1845
1846 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 1847 voltage = priv->calib_info->voltage;
b481de9c
ZY		 1848 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1849 voltage_compensation =
1850 iwl4965_get_voltage_compensation(voltage, init_voltage);
1851
1852 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1853 init_voltage,
1854 voltage, voltage_compensation);
1855
1856 /* get current temperature (Celsius) */
1857 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1858 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1859 current_temp = KELVIN_TO_CELSIUS(current_temp);
1860
1861 /* select thermal txpower adjustment params, based on channel group
1862 * (same frequency group used for mimo txatten adjustment) */
1863 degrees_per_05db_num =
1864 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1865 degrees_per_05db_denom =
1866 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1867
1868 /* get per-chain txpower values from factory measurements */
1869 for (c = 0; c < 2; c++) {
1870 measurement = &ch_eeprom_info.measurements[c][1];
1871
1872 /* txgain adjustment (in half-dB steps) based on difference
1873 * between factory and current temperature */
1874 factory_temp = measurement->temperature;
1875 iwl4965_math_div_round((current_temp - factory_temp) *
1876 degrees_per_05db_denom,
1877 degrees_per_05db_num,
1878 &temperature_comp[c]);
1879
1880 factory_gain_index[c] = measurement->gain_idx;
1881 factory_actual_pwr[c] = measurement->actual_pow;
1882
1883 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1884 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1885 "curr tmp %d, comp %d steps\n",
1886 factory_temp, current_temp,
1887 temperature_comp[c]);
1888
1889 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1890 factory_gain_index[c],
1891 factory_actual_pwr[c]);
1892 }
1893
1894 /* for each of 33 bit-rates (including 1 for CCK) */
1895 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1896 u8 is_mimo_rate;
bb8c093b 1897 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 1898
1899 /* for mimo, reduce each chain's txpower by half
1900 * (3dB, 6 steps), so total output power is regulatory
1901 * compliant. */
1902 if (i & 0x8) {
1903 current_regulatory = reg_limit -
1904 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1905 is_mimo_rate = 1;
1906 } else {
1907 current_regulatory = reg_limit;
1908 is_mimo_rate = 0;
1909 }
1910
1911 /* find txpower limit, either hardware or regulatory */
1912 power_limit = saturation_power - back_off_table[i];
1913 if (power_limit > current_regulatory)
1914 power_limit = current_regulatory;
1915
1916 /* reduce user's txpower request if necessary
1917 * for this rate on this channel */
1918 target_power = user_target_power;
1919 if (target_power > power_limit)
1920 target_power = power_limit;
1921
1922 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1923 i, saturation_power - back_off_table[i],
1924 current_regulatory, user_target_power,
1925 target_power);
1926
1927 /* for each of 2 Tx chains (radio transmitters) */
1928 for (c = 0; c < 2; c++) {
1929 s32 atten_value;
1930
1931 if (is_mimo_rate)
1932 atten_value =
1933 (s32)le32_to_cpu(priv->card_alive_init.
1934 tx_atten[txatten_grp][c]);
1935 else
1936 atten_value = 0;
1937
1938 /* calculate index; higher index means lower txpower */
1939 power_index = (u8) (factory_gain_index[c] -
1940 (target_power -
1941 factory_actual_pwr[c]) -
1942 temperature_comp[c] -
1943 voltage_compensation +
1944 atten_value);
1945
1946/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1947 power_index); */
1948
1949 if (power_index < get_min_power_index(i, band))
1950 power_index = get_min_power_index(i, band);
1951
1952 /* adjust 5 GHz index to support negative indexes */
1953 if (!band)
1954 power_index += 9;
1955
1956 /* CCK, rate 32, reduce txpower for CCK */
1957 if (i == POWER_TABLE_CCK_ENTRY)
1958 power_index +=
1959 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1960
1961 /* stay within the table! */
1962 if (power_index > 107) {
1963 IWL_WARNING("txpower index %d > 107\n",
1964 power_index);
1965 power_index = 107;
1966 }
1967 if (power_index < 0) {
1968 IWL_WARNING("txpower index %d < 0\n",
1969 power_index);
1970 power_index = 0;
1971 }
1972
1973 /* fill txpower command for this rate/chain */
1974 tx_power.s.radio_tx_gain[c] =
1975 gain_table[band][power_index].radio;
1976 tx_power.s.dsp_predis_atten[c] =
1977 gain_table[band][power_index].dsp;
1978
1979 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1980 "gain 0x%02x dsp %d\n",
1981 c, atten_value, power_index,
1982 tx_power.s.radio_tx_gain[c],
1983 tx_power.s.dsp_predis_atten[c]);
1984 }/* for each chain */
1985
1986 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1987
1988 }/* for each rate */
1989
1990 return 0;
1991}
1992
1993/**
bb8c093b 1994 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
b481de9c
ZY		 1995 *
1996 * Uses the active RXON for channel, band, and characteristics (fat, high)
1997 * The power limit is taken from priv->user_txpower_limit.
1998 */
c79dd5b5 1999int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 2000{
bb8c093b 2001 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 2002 int ret;
b481de9c
ZY		 2003 u8 band = 0;
2004 u8 is_fat = 0;
2005 u8 ctrl_chan_high = 0;
2006
2007 if (test_bit(STATUS_SCANNING, &priv->status)) {
2008 /* If this gets hit a lot, switch it to a BUG() and catch
2009 * the stack trace to find out who is calling this during
2010 * a scan. */
2011 IWL_WARNING("TX Power requested while scanning!\n");
2012 return -EAGAIN;
2013 }
2014
8318d78a 2015 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 2016
2017 is_fat = is_fat_channel(priv->active_rxon.flags);
2018
2019 if (is_fat &&
2020 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2021 ctrl_chan_high = 1;
2022
2023 cmd.band = band;
2024 cmd.channel = priv->active_rxon.channel;
2025
857485c0 2026 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 2027 le16_to_cpu(priv->active_rxon.channel),
2028 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 2029 if (ret)
2030 goto out;
b481de9c 2031
857485c0
TW		 2032 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2033
2034out:
2035 return ret;
b481de9c
ZY		 2036}
2037
7e8c519e
TW		 2038static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2039{
2040 int ret = 0;
2041 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2042 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2043 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2044
2045 if ((rxon1->flags == rxon2->flags) &&
2046 (rxon1->filter_flags == rxon2->filter_flags) &&
2047 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2048 (rxon1->ofdm_ht_single_stream_basic_rates ==
2049 rxon2->ofdm_ht_single_stream_basic_rates) &&
2050 (rxon1->ofdm_ht_dual_stream_basic_rates ==
2051 rxon2->ofdm_ht_dual_stream_basic_rates) &&
2052 (rxon1->rx_chain == rxon2->rx_chain) &&
2053 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2054 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
2055 return 0;
2056 }
2057
2058 rxon_assoc.flags = priv->staging_rxon.flags;
2059 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2060 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2061 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2062 rxon_assoc.reserved = 0;
2063 rxon_assoc.ofdm_ht_single_stream_basic_rates =
2064 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2065 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2066 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2067 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2068
2069 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2070 sizeof(rxon_assoc), &rxon_assoc, NULL);
2071 if (ret)
2072 return ret;
2073
2074 return ret;
2075}
2076
2077
c79dd5b5 2078int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2079{
2080 int rc;
2081 u8 band = 0;
2082 u8 is_fat = 0;
2083 u8 ctrl_chan_high = 0;
bb8c093b 2084 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 2085 const struct iwl_channel_info *ch_info;
b481de9c 2086
8318d78a 2087 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 2088
8622e705 2089 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 2090
2091 is_fat = is_fat_channel(priv->staging_rxon.flags);
2092
2093 if (is_fat &&
2094 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2095 ctrl_chan_high = 1;
2096
2097 cmd.band = band;
2098 cmd.expect_beacon = 0;
2099 cmd.channel = cpu_to_le16(channel);
2100 cmd.rxon_flags = priv->active_rxon.flags;
2101 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2102 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2103 if (ch_info)
2104 cmd.expect_beacon = is_channel_radar(ch_info);
2105 else
2106 cmd.expect_beacon = 1;
2107
2108 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2109 ctrl_chan_high, &cmd.tx_power);
2110 if (rc) {
2111 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2112 return rc;
2113 }
2114
857485c0 2115 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 2116 return rc;
2117}
2118
2119#define RTS_HCCA_RETRY_LIMIT 3
2120#define RTS_DFAULT_RETRY_LIMIT 60
2121
c79dd5b5 2122void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
857485c0 2123 struct iwl_cmd *cmd,
b481de9c
ZY		 2124 struct ieee80211_tx_control *ctrl,
2125 struct ieee80211_hdr *hdr, int sta_id,
2126 int is_hcca)
2127{
87e4f7df 2128 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
b481de9c
ZY		 2129 u8 rts_retry_limit = 0;
2130 u8 data_retry_limit = 0;
b481de9c 2131 u16 fc = le16_to_cpu(hdr->frame_control);
87e4f7df
TW		 2132 u8 rate_plcp;
2133 u16 rate_flags = 0;
8318d78a 2134 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c 2135
87e4f7df 2136 rate_plcp = iwl4965_rates[rate_idx].plcp;
b481de9c
ZY		 2137
2138 rts_retry_limit = (is_hcca) ?
2139 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2140
87e4f7df
TW		 2141 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2142 rate_flags |= RATE_MCS_CCK_MSK;
2143
2144
b481de9c
ZY		 2145 if (ieee80211_is_probe_response(fc)) {
2146 data_retry_limit = 3;
2147 if (data_retry_limit < rts_retry_limit)
2148 rts_retry_limit = data_retry_limit;
2149 } else
2150 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2151
2152 if (priv->data_retry_limit != -1)
2153 data_retry_limit = priv->data_retry_limit;
2154
87e4f7df
TW		 2155
2156 if (ieee80211_is_data(fc)) {
2157 tx->initial_rate_index = 0;
2158 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2159 } else {
b481de9c
ZY		 2160 switch (fc & IEEE80211_FCTL_STYPE) {
2161 case IEEE80211_STYPE_AUTH:
2162 case IEEE80211_STYPE_DEAUTH:
2163 case IEEE80211_STYPE_ASSOC_REQ:
2164 case IEEE80211_STYPE_REASSOC_REQ:
87e4f7df
TW		 2165 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2166 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2167 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
b481de9c
ZY		 2168 }
2169 break;
2170 default:
2171 break;
2172 }
87e4f7df
TW		 2173
2174 /* Alternate between antenna A and B for successive frames */
2175 if (priv->use_ant_b_for_management_frame) {
2176 priv->use_ant_b_for_management_frame = 0;
2177 rate_flags |= RATE_MCS_ANT_B_MSK;
2178 } else {
2179 priv->use_ant_b_for_management_frame = 1;
2180 rate_flags |= RATE_MCS_ANT_A_MSK;
2181 }
b481de9c
ZY		 2182 }
2183
87e4f7df
TW		 2184 tx->rts_retry_limit = rts_retry_limit;
2185 tx->data_retry_limit = data_retry_limit;
2186 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
b481de9c
ZY		 2187}
2188
c79dd5b5 2189int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2190{
059ff826
TW		 2191 struct iwl4965_shared *s = priv->shared_virt;
2192 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 2193}
2194
c79dd5b5 2195int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 2196{
2197 return priv->temperature;
2198}
2199
c79dd5b5 2200unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2201 struct iwl4965_frame *frame, u8 rate)
b481de9c 2202{
bb8c093b 2203 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2204 unsigned int frame_size;
2205
2206 tx_beacon_cmd = &frame->u.beacon;
2207 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2208
5425e490 2209 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2210 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2211
bb8c093b 2212 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 2213 tx_beacon_cmd->frame,
bb8c093b 2214 iwl4965_broadcast_addr,
b481de9c
ZY		 2215 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2216
2217 BUG_ON(frame_size > MAX_MPDU_SIZE);
2218 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2219
2220 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2221 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2222 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 2223 else
2224 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2225 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 2226
2227 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2228 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2229 return (sizeof(*tx_beacon_cmd) + frame_size);
2230}
2231
8b6eaea8
CB		 2232/*
2233 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2234 * given Tx queue, and enable the DMA channel used for that queue.
2235 *
2236 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2237 * channels supported in hardware.
2238 */
c79dd5b5 2239int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c
ZY		 2240{
2241 int rc;
2242 unsigned long flags;
2243 int txq_id = txq->q.id;
2244
2245 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 2246 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2247 if (rc) {
2248 spin_unlock_irqrestore(&priv->lock, flags);
2249 return rc;
2250 }
2251
8b6eaea8 2252 /* Circular buffer (TFD queue in DRAM) physical base address */
3395f6e9 2253 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
b481de9c 2254 txq->q.dma_addr >> 8);
8b6eaea8
CB		 2255
2256 /* Enable DMA channel, using same id as for TFD queue */
3395f6e9 2257 iwl_write_direct32(
4b52c39d
EG		 2258 priv, FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2259 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2260 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
3395f6e9 2261 iwl_release_nic_access(priv);
b481de9c
ZY		 2262 spin_unlock_irqrestore(&priv->lock, flags);
2263
2264 return 0;
2265}
2266
c79dd5b5 2267int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 2268 dma_addr_t addr, u16 len)
2269{
2270 int index, is_odd;
bb8c093b 2271 struct iwl4965_tfd_frame *tfd = ptr;
b481de9c
ZY		 2272 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2273
8b6eaea8 2274 /* Each TFD can point to a maximum 20 Tx buffers */
b481de9c
ZY		 2275 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2276 IWL_ERROR("Error can not send more than %d chunks\n",
2277 MAX_NUM_OF_TBS);
2278 return -EINVAL;
2279 }
2280
2281 index = num_tbs / 2;
2282 is_odd = num_tbs & 0x1;
2283
2284 if (!is_odd) {
2285 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2286 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
6a218f6f 2287 iwl_get_dma_hi_address(addr));
b481de9c
ZY		 2288 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2289 } else {
2290 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2291 (u32) (addr & 0xffff));
2292 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2293 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2294 }
2295
2296 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2297
2298 return 0;
2299}
2300
c79dd5b5 2301static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
b481de9c 2302{
073d3f5f 2303 u16 hw_version = iwl_eeprom_query16(priv, EEPROM_4965_BOARD_REVISION);
b481de9c
ZY		 2304
2305 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2306 ((hw_version >> 8) & 0x0F),
2307 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2308
2309 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
073d3f5f 2310 &priv->eeprom[EEPROM_4965_BOARD_PBA]);
b481de9c
ZY		 2311}
2312
399f4900
RR		 2313static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
2314{
2315 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
2316 sizeof(struct iwl4965_shared),
2317 &priv->shared_phys);
2318 if (!priv->shared_virt)
2319 return -ENOMEM;
2320
2321 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
2322
2323 return 0;
2324}
2325
2326static void iwl4965_free_shared_mem(struct iwl_priv *priv)
2327{
2328 if (priv->shared_virt)
2329 pci_free_consistent(priv->pci_dev,
2330 sizeof(struct iwl4965_shared),
2331 priv->shared_virt,
2332 priv->shared_phys);
2333}
2334
8b6eaea8 2335/**
e2a722eb 2336 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 2337 */
e2a722eb
TW		 2338static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2339 struct iwl4965_tx_queue *txq,
2340 u16 byte_cnt)
b481de9c
ZY		 2341{
2342 int len;
2343 int txq_id = txq->q.id;
059ff826 2344 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 2345
b481de9c
ZY		 2346 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2347
8b6eaea8 2348 /* Set up byte count within first 256 entries */
b481de9c 2349 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 2350 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 2351
8b6eaea8 2352 /* If within first 64 entries, duplicate at end */
038669e4 2353 if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
b481de9c 2354 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
038669e4 2355 tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 2356 byte_cnt, len);
b481de9c
ZY		 2357}
2358
b481de9c
ZY		 2359/**
2360 * sign_extend - Sign extend a value using specified bit as sign-bit
2361 *
2362 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2363 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2364 *
2365 * @param oper value to sign extend
2366 * @param index 0 based bit index (0<=index<32) to sign bit
2367 */
2368static s32 sign_extend(u32 oper, int index)
2369{
2370 u8 shift = 31 - index;
2371
2372 return (s32)(oper << shift) >> shift;
2373}
2374
2375/**
2376 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2377 * @statistics: Provides the temperature reading from the uCode
2378 *
2379 * A return of <0 indicates bogus data in the statistics
2380 */
c79dd5b5 2381int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 2382{
2383 s32 temperature;
2384 s32 vt;
2385 s32 R1, R2, R3;
2386 u32 R4;
2387
2388 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2389 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2390 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2391 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2392 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2393 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2394 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2395 } else {
2396 IWL_DEBUG_TEMP("Running temperature calibration\n");
2397 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2398 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2399 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2400 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2401 }
2402
2403 /*
8b6eaea8 2404 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 2405 *
2406 * NOTE If we haven't received a statistics notification yet
2407 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 2408 * "initialize" ALIVE response.
2409 */
b481de9c
ZY		 2410 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2411 vt = sign_extend(R4, 23);
2412 else
2413 vt = sign_extend(
2414 le32_to_cpu(priv->statistics.general.temperature), 23);
2415
2416 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2417 R1, R2, R3, vt);
2418
2419 if (R3 == R1) {
2420 IWL_ERROR("Calibration conflict R1 == R3\n");
2421 return -1;
2422 }
2423
2424 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2425 * Add offset to center the adjustment around 0 degrees Centigrade. */
2426 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2427 temperature /= (R3 - R1);
2428 temperature = (temperature * 97) / 100 +
2429 TEMPERATURE_CALIB_KELVIN_OFFSET;
2430
2431 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2432 KELVIN_TO_CELSIUS(temperature));
2433
2434 return temperature;
2435}
2436
2437/* Adjust Txpower only if temperature variance is greater than threshold. */
2438#define IWL_TEMPERATURE_THRESHOLD 3
2439
2440/**
2441 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2442 *
2443 * If the temperature changed has changed sufficiently, then a recalibration
2444 * is needed.
2445 *
2446 * Assumes caller will replace priv->last_temperature once calibration
2447 * executed.
2448 */
c79dd5b5 2449static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 2450{
2451 int temp_diff;
2452
2453 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2454 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2455 return 0;
2456 }
2457
2458 temp_diff = priv->temperature - priv->last_temperature;
2459
2460 /* get absolute value */
2461 if (temp_diff < 0) {
2462 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2463 temp_diff = -temp_diff;
2464 } else if (temp_diff == 0)
2465 IWL_DEBUG_POWER("Same temp, \n");
2466 else
2467 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2468
2469 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2470 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2471 return 0;
2472 }
2473
2474 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2475
2476 return 1;
2477}
2478
2479/* Calculate noise level, based on measurements during network silence just
2480 * before arriving beacon. This measurement can be done only if we know
2481 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 2482static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 2483{
2484 struct statistics_rx_non_phy *rx_info
2485 = &(priv->statistics.rx.general);
2486 int num_active_rx = 0;
2487 int total_silence = 0;
2488 int bcn_silence_a =
2489 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2490 int bcn_silence_b =
2491 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2492 int bcn_silence_c =
2493 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2494
2495 if (bcn_silence_a) {
2496 total_silence += bcn_silence_a;
2497 num_active_rx++;
2498 }
2499 if (bcn_silence_b) {
2500 total_silence += bcn_silence_b;
2501 num_active_rx++;
2502 }
2503 if (bcn_silence_c) {
2504 total_silence += bcn_silence_c;
2505 num_active_rx++;
2506 }
2507
2508 /* Average among active antennas */
2509 if (num_active_rx)
2510 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2511 else
2512 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2513
2514 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2515 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2516 priv->last_rx_noise);
2517}
2518
c79dd5b5 2519void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 2520{
bb8c093b 2521 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2522 int change;
2523 s32 temp;
2524
2525 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2526 (int)sizeof(priv->statistics), pkt->len);
2527
2528 change = ((priv->statistics.general.temperature !=
2529 pkt->u.stats.general.temperature) ||
2530 ((priv->statistics.flag &
2531 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2532 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2533
2534 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2535
2536 set_bit(STATUS_STATISTICS, &priv->status);
2537
2538 /* Reschedule the statistics timer to occur in
2539 * REG_RECALIB_PERIOD seconds to ensure we get a
2540 * thermal update even if the uCode doesn't give
2541 * us one */
2542 mod_timer(&priv->statistics_periodic, jiffies +
2543 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2544
2545 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2546 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2547 iwl4965_rx_calc_noise(priv);
f0832f13 2548#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 2549 queue_work(priv->workqueue, &priv->sensitivity_work);
2550#endif
2551 }
2552
ab53d8af
MA		 2553 iwl_leds_background(priv);
2554
b481de9c
ZY		 2555 /* If the hardware hasn't reported a change in
2556 * temperature then don't bother computing a
2557 * calibrated temperature value */
2558 if (!change)
2559 return;
2560
2561 temp = iwl4965_get_temperature(priv);
2562 if (temp < 0)
2563 return;
2564
2565 if (priv->temperature != temp) {
2566 if (priv->temperature)
2567 IWL_DEBUG_TEMP("Temperature changed "
2568 "from %dC to %dC\n",
2569 KELVIN_TO_CELSIUS(priv->temperature),
2570 KELVIN_TO_CELSIUS(temp));
2571 else
2572 IWL_DEBUG_TEMP("Temperature "
2573 "initialized to %dC\n",
2574 KELVIN_TO_CELSIUS(temp));
2575 }
2576
2577 priv->temperature = temp;
2578 set_bit(STATUS_TEMPERATURE, &priv->status);
2579
2580 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2581 iwl4965_is_temp_calib_needed(priv))
2582 queue_work(priv->workqueue, &priv->txpower_work);
2583}
2584
c79dd5b5 2585static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 2586 struct sk_buff *skb,
2587 struct iwl4965_rx_phy_res *rx_start,
2588 struct ieee80211_rx_status *stats,
2589 u32 ampdu_status)
2590{
2591 s8 signal = stats->ssi;
2592 s8 noise = 0;
8318d78a 2593 int rate = stats->rate_idx;
12342c47 2594 u64 tsf = stats->mactime;
a0b484fe 2595 __le16 antenna;
12342c47
ZY		 2596 __le16 phy_flags_hw = rx_start->phy_flags;
2597 struct iwl4965_rt_rx_hdr {
2598 struct ieee80211_radiotap_header rt_hdr;
2599 __le64 rt_tsf; /* TSF */
2600 u8 rt_flags; /* radiotap packet flags */
2601 u8 rt_rate; /* rate in 500kb/s */
2602 __le16 rt_channelMHz; /* channel in MHz */
2603 __le16 rt_chbitmask; /* channel bitfield */
2604 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2605 s8 rt_dbmnoise;
2606 u8 rt_antenna; /* antenna number */
2607 } __attribute__ ((packed)) *iwl4965_rt;
2608
2609 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2610 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2611 if (net_ratelimit())
2612 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 2613 "radiotap head [%zd]\n",
12342c47
ZY		 2614 skb_headroom(skb), sizeof(*iwl4965_rt));
2615 return;
2616 }
2617
2618 /* put radiotap header in front of 802.11 header and data */
2619 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2620
2621 /* initialise radiotap header */
2622 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2623 iwl4965_rt->rt_hdr.it_pad = 0;
2624
2625 /* total header + data */
2626 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2627 &iwl4965_rt->rt_hdr.it_len);
2628
2629 /* Indicate all the fields we add to the radiotap header */
2630 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2631 (1 << IEEE80211_RADIOTAP_FLAGS) |
2632 (1 << IEEE80211_RADIOTAP_RATE) |
2633 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2634 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2635 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2636 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2637 &iwl4965_rt->rt_hdr.it_present);
2638
2639 /* Zero the flags, we'll add to them as we go */
2640 iwl4965_rt->rt_flags = 0;
2641
2642 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2643
2644 iwl4965_rt->rt_dbmsignal = signal;
2645 iwl4965_rt->rt_dbmnoise = noise;
2646
2647 /* Convert the channel frequency and set the flags */
2648 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2649 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2650 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2651 IEEE80211_CHAN_5GHZ),
2652 &iwl4965_rt->rt_chbitmask);
2653 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2654 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2655 IEEE80211_CHAN_2GHZ),
2656 &iwl4965_rt->rt_chbitmask);
2657 else /* 802.11g */
2658 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2659 IEEE80211_CHAN_2GHZ),
2660 &iwl4965_rt->rt_chbitmask);
2661
12342c47
ZY		 2662 if (rate == -1)
2663 iwl4965_rt->rt_rate = 0;
2664 else
2665 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2666
2667 /*
2668 * "antenna number"
2669 *
2670 * It seems that the antenna field in the phy flags value
2671 * is actually a bitfield. This is undefined by radiotap,
2672 * it wants an actual antenna number but I always get "7"
2673 * for most legacy frames I receive indicating that the
2674 * same frame was received on all three RX chains.
2675 *
2676 * I think this field should be removed in favour of a
2677 * new 802.11n radiotap field "RX chains" that is defined
2678 * as a bitmask.
2679 */
a0b484fe
JB		 2680 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2681 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 2682
2683 /* set the preamble flag if appropriate */
2684 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2685 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2686
2687 stats->flag |= RX_FLAG_RADIOTAP;
2688}
2689
19758bef
TW		 2690static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2691{
2692 /* 0 - mgmt, 1 - cnt, 2 - data */
2693 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2694 priv->rx_stats[idx].cnt++;
2695 priv->rx_stats[idx].bytes += len;
2696}
2697
3ec47732
EG		 2698/*
2699 * returns non-zero if packet should be dropped
2700 */
2701static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2702 struct ieee80211_hdr *hdr,
2703 u32 decrypt_res,
2704 struct ieee80211_rx_status *stats)
2705{
2706 u16 fc = le16_to_cpu(hdr->frame_control);
2707
2708 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2709 return 0;
2710
2711 if (!(fc & IEEE80211_FCTL_PROTECTED))
2712 return 0;
2713
2714 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2715 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2716 case RX_RES_STATUS_SEC_TYPE_TKIP:
2717 /* The uCode has got a bad phase 1 Key, pushes the packet.
2718 * Decryption will be done in SW. */
2719 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2720 RX_RES_STATUS_BAD_KEY_TTAK)
2721 break;
2722
2723 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2724 RX_RES_STATUS_BAD_ICV_MIC) {
2725 /* bad ICV, the packet is destroyed since the
2726 * decryption is inplace, drop it */
2727 IWL_DEBUG_RX("Packet destroyed\n");
2728 return -1;
2729 }
2730 case RX_RES_STATUS_SEC_TYPE_WEP:
2731 case RX_RES_STATUS_SEC_TYPE_CCMP:
2732 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2733 RX_RES_STATUS_DECRYPT_OK) {
2734 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2735 stats->flag |= RX_FLAG_DECRYPTED;
2736 }
2737 break;
2738
2739 default:
2740 break;
2741 }
2742 return 0;
2743}
2744
17e476b8
EG		 2745static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2746{
2747 u32 decrypt_out = 0;
2748
2749 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2750 RX_RES_STATUS_STATION_FOUND)
2751 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2752 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2753
2754 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2755
2756 /* packet was not encrypted */
2757 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2758 RX_RES_STATUS_SEC_TYPE_NONE)
2759 return decrypt_out;
2760
2761 /* packet was encrypted with unknown alg */
2762 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2763 RX_RES_STATUS_SEC_TYPE_ERR)
2764 return decrypt_out;
2765
2766 /* decryption was not done in HW */
2767 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2768 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2769 return decrypt_out;
2770
2771 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2772
2773 case RX_RES_STATUS_SEC_TYPE_CCMP:
2774 /* alg is CCM: check MIC only */
2775 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2776 /* Bad MIC */
2777 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2778 else
2779 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2780
2781 break;
2782
2783 case RX_RES_STATUS_SEC_TYPE_TKIP:
2784 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2785 /* Bad TTAK */
2786 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2787 break;
2788 }
2789 /* fall through if TTAK OK */
2790 default:
2791 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2792 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2793 else
2794 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2795 break;
2796 };
2797
2798 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2799 decrypt_in, decrypt_out);
2800
2801 return decrypt_out;
2802}
2803
c79dd5b5 2804static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 2805 int include_phy,
bb8c093b 2806 struct iwl4965_rx_mem_buffer *rxb,
b481de9c
ZY		 2807 struct ieee80211_rx_status *stats)
2808{
bb8c093b 2809 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 2810 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2811 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2812 struct ieee80211_hdr *hdr;
2813 u16 len;
2814 __le32 *rx_end;
2815 unsigned int skblen;
2816 u32 ampdu_status;
17e476b8 2817 u32 ampdu_status_legacy;
b481de9c
ZY		 2818
2819 if (!include_phy && priv->last_phy_res[0])
2820 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2821
2822 if (!rx_start) {
2823 IWL_ERROR("MPDU frame without a PHY data\n");
2824 return;
2825 }
2826 if (include_phy) {
2827 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
2828 rx_start->cfg_phy_cnt);
2829
2830 len = le16_to_cpu(rx_start->byte_count);
2831
2832 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
2833 sizeof(struct iwl4965_rx_phy_res) +
2834 rx_start->cfg_phy_cnt + len);
2835
2836 } else {
2837 struct iwl4965_rx_mpdu_res_start *amsdu =
2838 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2839
2840 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
2841 sizeof(struct iwl4965_rx_mpdu_res_start));
2842 len = le16_to_cpu(amsdu->byte_count);
2843 rx_start->byte_count = amsdu->byte_count;
2844 rx_end = (__le32 *) (((u8 *) hdr) + len);
2845 }
5425e490 2846 if (len > priv->hw_params.max_pkt_size || len < 16) {
12342c47 2847 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 2848 return;
2849 }
2850
2851 ampdu_status = le32_to_cpu(*rx_end);
2852 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
2853
17e476b8
EG		 2854 if (!include_phy) {
2855 /* New status scheme, need to translate */
2856 ampdu_status_legacy = ampdu_status;
2857 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
2858 }
2859
b481de9c
ZY		 2860 /* start from MAC */
2861 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
2862 skb_put(rxb->skb, len); /* end where data ends */
2863
2864 /* We only process data packets if the interface is open */
2865 if (unlikely(!priv->is_open)) {
2866 IWL_DEBUG_DROP_LIMIT
2867 ("Dropping packet while interface is not open.\n");
2868 return;
2869 }
2870
b481de9c
ZY		 2871 stats->flag = 0;
2872 hdr = (struct ieee80211_hdr *)rxb->skb->data;
2873
3ec47732 2874 /* in case of HW accelerated crypto and bad decryption, drop */
099b40b7 2875 if (!priv->hw_params.sw_crypto &&
3ec47732
EG		 2876 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
2877 return;
b481de9c 2878
12342c47
ZY		 2879 if (priv->add_radiotap)
2880 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
2881
19758bef 2882 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 2883 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
2884 priv->alloc_rxb_skb--;
2885 rxb->skb = NULL;
b481de9c
ZY		 2886}
2887
2888/* Calc max signal level (dBm) among 3 possible receivers */
2889static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
2890{
2891 /* data from PHY/DSP regarding signal strength, etc.,
2892 * contents are always there, not configurable by host. */
2893 struct iwl4965_rx_non_cfg_phy *ncphy =
2894 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
2895 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
2896 >> IWL_AGC_DB_POS;
2897
2898 u32 valid_antennae =
2899 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
2900 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
2901 u8 max_rssi = 0;
2902 u32 i;
2903
2904 /* Find max rssi among 3 possible receivers.
2905 * These values are measured by the digital signal processor (DSP).
2906 * They should stay fairly constant even as the signal strength varies,
2907 * if the radio's automatic gain control (AGC) is working right.
2908 * AGC value (see below) will provide the "interesting" info. */
2909 for (i = 0; i < 3; i++)
2910 if (valid_antennae & (1 << i))
2911 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2912
2913 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2914 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2915 max_rssi, agc);
2916
2917 /* dBm = max_rssi dB - agc dB - constant.
2918 * Higher AGC (higher radio gain) means lower signal. */
2919 return (max_rssi - agc - IWL_RSSI_OFFSET);
2920}
2921
c79dd5b5 2922static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 2923{
2924 unsigned long flags;
2925
2926 spin_lock_irqsave(&priv->sta_lock, flags);
2927 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
2928 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
2929 priv->stations[sta_id].sta.sta.modify_mask = 0;
2930 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
2931 spin_unlock_irqrestore(&priv->sta_lock, flags);
2932
bb8c093b 2933 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 2934}
2935
c79dd5b5 2936static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 2937{
2938 /* FIXME: need locking over ps_status ??? */
947b13a7 2939 u8 sta_id = iwl_find_station(priv, addr);
b481de9c
ZY		 2940
2941 if (sta_id != IWL_INVALID_STATION) {
2942 u8 sta_awake = priv->stations[sta_id].
2943 ps_status == STA_PS_STATUS_WAKE;
2944
2945 if (sta_awake && ps_bit)
2946 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
2947 else if (!sta_awake && !ps_bit) {
2948 iwl4965_sta_modify_ps_wake(priv, sta_id);
2949 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
2950 }
2951 }
2952}
0a6857e7 2953#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 2954
2955/**
2956 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
2957 *
2958 * You may hack this function to show different aspects of received frames,
2959 * including selective frame dumps.
2960 * group100 parameter selects whether to show 1 out of 100 good frames.
2961 *
2962 * TODO: This was originally written for 3945, need to audit for
2963 * proper operation with 4965.
2964 */
c79dd5b5 2965static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 2966 struct iwl4965_rx_packet *pkt,
2967 struct ieee80211_hdr *header, int group100)
2968{
2969 u32 to_us;
2970 u32 print_summary = 0;
2971 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
2972 u32 hundred = 0;
2973 u32 dataframe = 0;
2974 u16 fc;
2975 u16 seq_ctl;
2976 u16 channel;
2977 u16 phy_flags;
2978 int rate_sym;
2979 u16 length;
2980 u16 status;
2981 u16 bcn_tmr;
2982 u32 tsf_low;
2983 u64 tsf;
2984 u8 rssi;
2985 u8 agc;
2986 u16 sig_avg;
2987 u16 noise_diff;
2988 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
2989 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
2990 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
2991 u8 *data = IWL_RX_DATA(pkt);
2992
0a6857e7 2993 if (likely(!(iwl_debug_level & IWL_DL_RX)))
17744ff6
TW		 2994 return;
2995
2996 /* MAC header */
2997 fc = le16_to_cpu(header->frame_control);
2998 seq_ctl = le16_to_cpu(header->seq_ctrl);
2999
3000 /* metadata */
3001 channel = le16_to_cpu(rx_hdr->channel);
3002 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3003 rate_sym = rx_hdr->rate;
3004 length = le16_to_cpu(rx_hdr->len);
3005
3006 /* end-of-frame status and timestamp */
3007 status = le32_to_cpu(rx_end->status);
3008 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3009 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3010 tsf = le64_to_cpu(rx_end->timestamp);
3011
3012 /* signal statistics */
3013 rssi = rx_stats->rssi;
3014 agc = rx_stats->agc;
3015 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3016 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3017
3018 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3019
3020 /* if data frame is to us and all is good,
3021 * (optionally) print summary for only 1 out of every 100 */
3022 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3023 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3024 dataframe = 1;
3025 if (!group100)
3026 print_summary = 1; /* print each frame */
3027 else if (priv->framecnt_to_us < 100) {
3028 priv->framecnt_to_us++;
3029 print_summary = 0;
3030 } else {
3031 priv->framecnt_to_us = 0;
3032 print_summary = 1;
3033 hundred = 1;
3034 }
3035 } else {
3036 /* print summary for all other frames */
3037 print_summary = 1;
3038 }
3039
3040 if (print_summary) {
3041 char *title;
3042 int rate_idx;
3043 u32 bitrate;
3044
3045 if (hundred)
3046 title = "100Frames";
3047 else if (fc & IEEE80211_FCTL_RETRY)
3048 title = "Retry";
3049 else if (ieee80211_is_assoc_response(fc))
3050 title = "AscRsp";
3051 else if (ieee80211_is_reassoc_response(fc))
3052 title = "RasRsp";
3053 else if (ieee80211_is_probe_response(fc)) {
3054 title = "PrbRsp";
3055 print_dump = 1; /* dump frame contents */
3056 } else if (ieee80211_is_beacon(fc)) {
3057 title = "Beacon";
3058 print_dump = 1; /* dump frame contents */
3059 } else if (ieee80211_is_atim(fc))
3060 title = "ATIM";
3061 else if (ieee80211_is_auth(fc))
3062 title = "Auth";
3063 else if (ieee80211_is_deauth(fc))
3064 title = "DeAuth";
3065 else if (ieee80211_is_disassoc(fc))
3066 title = "DisAssoc";
3067 else
3068 title = "Frame";
3069
3070 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3071 if (unlikely(rate_idx == -1))
3072 bitrate = 0;
3073 else
3074 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3075
3076 /* print frame summary.
3077 * MAC addresses show just the last byte (for brevity),
3078 * but you can hack it to show more, if you'd like to. */
3079 if (dataframe)
3080 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3081 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3082 title, fc, header->addr1[5],
3083 length, rssi, channel, bitrate);
3084 else {
3085 /* src/dst addresses assume managed mode */
3086 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3087 "src=0x%02x, rssi=%u, tim=%lu usec, "
3088 "phy=0x%02x, chnl=%d\n",
3089 title, fc, header->addr1[5],
3090 header->addr3[5], rssi,
3091 tsf_low - priv->scan_start_tsf,
3092 phy_flags, channel);
3093 }
3094 }
3095 if (print_dump)
0a6857e7 3096 iwl_print_hex_dump(IWL_DL_RX, data, length);
17744ff6
TW		 3097}
3098#else
c79dd5b5 3099static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3100 struct iwl4965_rx_packet *pkt,
3101 struct ieee80211_hdr *header,
3102 int group100)
3103{
3104}
3105#endif
3106
b481de9c 3107
7878a5a4 3108
857485c0 3109/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 3110 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
c79dd5b5 3111static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
bb8c093b 3112 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3113{
17744ff6
TW		 3114 struct ieee80211_hdr *header;
3115 struct ieee80211_rx_status rx_status;
bb8c093b 3116 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3117 /* Use phy data (Rx signal strength, etc.) contained within
3118 * this rx packet for legacy frames,
3119 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 3120 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 3121 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3122 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3123 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3124 __le32 *rx_end;
3125 unsigned int len = 0;
b481de9c 3126 u16 fc;
b481de9c
ZY		 3127 u8 network_packet;
3128
17744ff6 3129 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
dc92e497
TW		 3130 rx_status.freq =
3131 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
17744ff6
TW		 3132 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3133 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
dc92e497
TW		 3134 rx_status.rate_idx =
3135 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
17744ff6
TW		 3136 if (rx_status.band == IEEE80211_BAND_5GHZ)
3137 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3138
3139 rx_status.antenna = 0;
3140 rx_status.flag = 0;
3141
b481de9c 3142 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
dc92e497
TW		 3143 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3144 rx_start->cfg_phy_cnt);
b481de9c
ZY		 3145 return;
3146 }
17744ff6 3147
b481de9c
ZY		 3148 if (!include_phy) {
3149 if (priv->last_phy_res[0])
3150 rx_start = (struct iwl4965_rx_phy_res *)
3151 &priv->last_phy_res[1];
3152 else
3153 rx_start = NULL;
3154 }
3155
3156 if (!rx_start) {
3157 IWL_ERROR("MPDU frame without a PHY data\n");
3158 return;
3159 }
3160
3161 if (include_phy) {
3162 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3163 + rx_start->cfg_phy_cnt);
3164
3165 len = le16_to_cpu(rx_start->byte_count);
17744ff6 3166 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 3167 sizeof(struct iwl4965_rx_phy_res) + len);
3168 } else {
3169 struct iwl4965_rx_mpdu_res_start *amsdu =
3170 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3171
3172 header = (void *)(pkt->u.raw +
3173 sizeof(struct iwl4965_rx_mpdu_res_start));
3174 len = le16_to_cpu(amsdu->byte_count);
3175 rx_end = (__le32 *) (pkt->u.raw +
3176 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3177 }
3178
3179 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3180 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3181 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3182 le32_to_cpu(*rx_end));
3183 return;
3184 }
3185
3186 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3187
b481de9c 3188 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
17744ff6 3189 rx_status.ssi = iwl4965_calc_rssi(rx_start);
b481de9c
ZY		 3190
3191 /* Meaningful noise values are available only from beacon statistics,
3192 * which are gathered only when associated, and indicate noise
3193 * only for the associated network channel ...
3194 * Ignore these noise values while scanning (other channels) */
3109ece1 3195 if (iwl_is_associated(priv) &&
b481de9c 3196 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6
TW		 3197 rx_status.noise = priv->last_rx_noise;
3198 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3199 rx_status.noise);
b481de9c 3200 } else {
17744ff6
TW		 3201 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3202 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
b481de9c
ZY		 3203 }
3204
3205 /* Reset beacon noise level if not associated. */
3109ece1 3206 if (!iwl_is_associated(priv))
b481de9c
ZY		 3207 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3208
17744ff6
TW		 3209 /* Set "1" to report good data frames in groups of 100 */
3210 /* FIXME: need to optimze the call: */
3211 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3212
3213 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3214 rx_status.ssi, rx_status.noise, rx_status.signal,
06501d29 3215 (unsigned long long)rx_status.mactime);
b481de9c 3216
bb8c093b 3217 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 3218 if (network_packet) {
17744ff6 3219 priv->last_rx_rssi = rx_status.ssi;
b481de9c
ZY		 3220 priv->last_beacon_time = priv->ucode_beacon_time;
3221 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3222 }
3223
3224 fc = le16_to_cpu(header->frame_control);
3225 switch (fc & IEEE80211_FCTL_FTYPE) {
3226 case IEEE80211_FTYPE_MGMT:
b481de9c
ZY		 3227 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3228 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3229 header->addr2);
17744ff6 3230 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 3231 break;
3232
3233 case IEEE80211_FTYPE_CTL:
9ab46173 3234#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 3235 switch (fc & IEEE80211_FCTL_STYPE) {
3236 case IEEE80211_STYPE_BACK_REQ:
3237 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3238 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 3239 rxb, &rx_status);
b481de9c
ZY		 3240 break;
3241 default:
3242 break;
3243 }
3244#endif
b481de9c
ZY		 3245 break;
3246
0795af57
JP		 3247 case IEEE80211_FTYPE_DATA: {
3248 DECLARE_MAC_BUF(mac1);
3249 DECLARE_MAC_BUF(mac2);
3250 DECLARE_MAC_BUF(mac3);
3251
b481de9c
ZY		 3252 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3253 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3254 header->addr2);
3255
3256 if (unlikely(!network_packet))
3257 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 3258 "%s, %s, %s\n",
3259 print_mac(mac1, header->addr1),
3260 print_mac(mac2, header->addr2),
3261 print_mac(mac3, header->addr3));
bb8c093b 3262 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 3263 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3264 print_mac(mac1, header->addr1),
3265 print_mac(mac2, header->addr2),
3266 print_mac(mac3, header->addr3));
b481de9c
ZY		 3267 else
3268 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 3269 &rx_status);
b481de9c 3270 break;
0795af57 3271 }
b481de9c
ZY		 3272 default:
3273 break;
3274
3275 }
3276}
3277
3278/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3279 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
c79dd5b5 3280static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
bb8c093b 3281 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3282{
bb8c093b 3283 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3284 priv->last_phy_res[0] = 1;
3285 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3286 sizeof(struct iwl4965_rx_phy_res));
3287}
c79dd5b5 3288static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
bb8c093b 3289 struct iwl4965_rx_mem_buffer *rxb)
b481de9c
ZY		 3290
3291{
f0832f13 3292#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
bb8c093b
CH		 3293 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3294 struct iwl4965_missed_beacon_notif *missed_beacon;
b481de9c
ZY		 3295
3296 missed_beacon = &pkt->u.missed_beacon;
3297 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3298 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3299 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3300 le32_to_cpu(missed_beacon->total_missed_becons),
3301 le32_to_cpu(missed_beacon->num_recvd_beacons),
3302 le32_to_cpu(missed_beacon->num_expected_beacons));
f0832f13
EG		 3303 if (!test_bit(STATUS_SCANNING, &priv->status))
3304 iwl_init_sensitivity(priv);
b481de9c 3305 }
f0832f13 3306#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c 3307}
c8b0e6e1 3308#ifdef CONFIG_IWL4965_HT
b481de9c 3309
8b6eaea8
CB		 3310/**
3311 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3312 */
c79dd5b5 3313static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
b481de9c
ZY		 3314 int sta_id, int tid)
3315{
3316 unsigned long flags;
3317
8b6eaea8 3318 /* Remove "disable" flag, to enable Tx for this TID */
b481de9c
ZY		 3319 spin_lock_irqsave(&priv->sta_lock, flags);
3320 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3321 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3322 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3323 spin_unlock_irqrestore(&priv->sta_lock, flags);
3324
bb8c093b 3325 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3326}
3327
8b6eaea8
CB		 3328/**
3329 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3330 *
3331 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3332 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3333 */
c79dd5b5 3334static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b
CH		 3335 struct iwl4965_ht_agg *agg,
3336 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 3337 ba_resp)
3338
3339{
3340 int i, sh, ack;
fe01b477
RR		 3341 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3342 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3343 u64 bitmap;
3344 int successes = 0;
3345 struct ieee80211_tx_status *tx_status;
b481de9c
ZY		 3346
3347 if (unlikely(!agg->wait_for_ba)) {
3348 IWL_ERROR("Received BA when not expected\n");
3349 return -EINVAL;
3350 }
8b6eaea8
CB		 3351
3352 /* Mark that the expected block-ack response arrived */
b481de9c 3353 agg->wait_for_ba = 0;
fe01b477 3354 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 3355
3356 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 3357 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 3358 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 3359 sh += 0x100;
3360
8b6eaea8 3361 /* don't use 64-bit values for now */
fe01b477 3362 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 3363
3364 if (agg->frame_count > (64 - sh)) {
3365 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3366 return -1;
3367 }
3368
3369 /* check for success or failure according to the
8b6eaea8 3370 * transmitted bitmap and block-ack bitmap */
fe01b477 3371 bitmap &= agg->bitmap;
b481de9c 3372
8b6eaea8
CB		 3373 /* For each frame attempted in aggregation,
3374 * update driver's record of tx frame's status. */
b481de9c 3375 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 3376 ack = bitmap & (1 << i);
3377 successes += !!ack;
b481de9c 3378 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 3379 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3380 agg->start_idx + i);
3381 }
3382
3383 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3384 tx_status->flags = IEEE80211_TX_STATUS_ACK;
99556438
RR		 3385 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3386 tx_status->ampdu_ack_map = successes;
3387 tx_status->ampdu_ack_len = agg->frame_count;
4c424e4c
RR		 3388 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3389 &tx_status->control);
fe01b477 3390
f868f4e1 3391 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 3392
3393 return 0;
3394}
3395
3396/**
3397 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3398 */
c79dd5b5 3399static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 3400 u16 txq_id)
3401{
3402 /* Simply stop the queue, but don't change any configuration;
3403 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 3404 iwl_write_prph(priv,
12a81f60 3405 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 3406 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3407 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
fe01b477 3408}
b481de9c 3409
fe01b477
RR		 3410/**
3411 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
b095d03a 3412 * priv->lock must be held by the caller
fe01b477 3413 */
c79dd5b5 3414static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
fe01b477
RR		 3415 u16 ssn_idx, u8 tx_fifo)
3416{
b095d03a
RR		 3417 int ret = 0;
3418
fe01b477
RR		 3419 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3420 IWL_WARNING("queue number too small: %d, must be > %d\n",
3421 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3422 return -EINVAL;
b481de9c
ZY		 3423 }
3424
3395f6e9 3425 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 3426 if (ret)
3427 return ret;
3428
fe01b477
RR		 3429 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3430
12a81f60 3431 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 3432
3433 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3434 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3435 /* supposes that ssn_idx is valid (!= 0xFFF) */
3436 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3437
12a81f60 3438 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
fe01b477
RR		 3439 iwl4965_txq_ctx_deactivate(priv, txq_id);
3440 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3441
3395f6e9 3442 iwl_release_nic_access(priv);
b095d03a 3443
fe01b477
RR		 3444 return 0;
3445}
b481de9c 3446
c79dd5b5 3447int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
fe01b477
RR		 3448 u8 tid, int txq_id)
3449{
3450 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3451 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3452 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3453
3454 switch (priv->stations[sta_id].tid[tid].agg.state) {
3455 case IWL_EMPTYING_HW_QUEUE_DELBA:
3456 /* We are reclaiming the last packet of the */
3457 /* aggregated HW queue */
3458 if (txq_id == tid_data->agg.txq_id &&
3459 q->read_ptr == q->write_ptr) {
3460 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3461 int tx_fifo = default_tid_to_tx_fifo[tid];
3462 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3463 iwl4965_tx_queue_agg_disable(priv, txq_id,
3464 ssn, tx_fifo);
3465 tid_data->agg.state = IWL_AGG_OFF;
3466 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3467 }
3468 break;
3469 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3470 /* We are reclaiming the last packet of the queue */
3471 if (tid_data->tfds_in_queue == 0) {
3472 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3473 tid_data->agg.state = IWL_AGG_ON;
3474 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3475 }
3476 break;
3477 }
b481de9c
ZY		 3478 return 0;
3479}
3480
8b6eaea8
CB		 3481/**
3482 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3483 * @index -- current index
3484 * @n_bd -- total number of entries in queue (s/b power of 2)
3485 */
bb8c093b 3486static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 3487{
3488 return (index == 0) ? n_bd - 1 : index - 1;
3489}
3490
8b6eaea8
CB		 3491/**
3492 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3493 *
3494 * Handles block-acknowledge notification from device, which reports success
3495 * of frames sent via aggregation.
3496 */
c79dd5b5 3497static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b 3498 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3499{
bb8c093b
CH		 3500 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3501 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 3502 int index;
bb8c093b
CH		 3503 struct iwl4965_tx_queue *txq = NULL;
3504 struct iwl4965_ht_agg *agg;
fe01b477 3505 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 3506
3507 /* "flow" corresponds to Tx queue */
fe01b477 3508 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 3509
3510 /* "ssn" is start of block-ack Tx window, corresponds to index
3511 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 3512 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3513
dfe7d458 3514 if (scd_flow >= priv->hw_params.max_txq_num) {
b481de9c
ZY		 3515 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3516 return;
3517 }
3518
fe01b477 3519 txq = &priv->txq[scd_flow];
b481de9c 3520 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 3521
3522 /* Find index just before block-ack window */
bb8c093b 3523 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 3524
01ebd063 3525 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 3526
0795af57
JP		 3527 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3528 "sta_id = %d\n",
b481de9c 3529 agg->wait_for_ba,
0795af57 3530 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 3531 ba_resp->sta_id);
fe01b477 3532 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 3533 "%d, scd_ssn = %d\n",
3534 ba_resp->tid,
fe01b477 3535 ba_resp->seq_ctl,
0310ae72 3536 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 3537 ba_resp->scd_flow,
3538 ba_resp->scd_ssn);
fe01b477 3539 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 3540 agg->start_idx,
f868f4e1 3541 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 3542
3543 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 3544 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 3545
3546 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3547 * block-ack window (we assume that they've been successfully
3548 * transmitted ... if not, it's too late anyway). */
fe01b477
RR		 3549 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3550 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3551 priv->stations[ba_resp->sta_id].
3552 tid[ba_resp->tid].tfds_in_queue -= freed;
3553 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3554 priv->mac80211_registered &&
3555 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3556 ieee80211_wake_queue(priv->hw, scd_flow);
3557 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3558 ba_resp->tid, scd_flow);
3559 }
b481de9c
ZY		 3560}
3561
8b6eaea8
CB		 3562/**
3563 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3564 */
c79dd5b5 3565static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 3566 u16 txq_id)
3567{
3568 u32 tbl_dw_addr;
3569 u32 tbl_dw;
3570 u16 scd_q2ratid;
3571
038669e4 3572 scd_q2ratid = ra_tid & IWL49_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
b481de9c
ZY		 3573
3574 tbl_dw_addr = priv->scd_base_addr +
038669e4 3575 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
b481de9c 3576
3395f6e9 3577 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 3578
3579 if (txq_id & 0x1)
3580 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3581 else
3582 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3583
3395f6e9 3584 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 3585
3586 return 0;
3587}
3588
fe01b477 3589
b481de9c 3590/**
8b6eaea8
CB		 3591 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3592 *
3593 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3594 * i.e. it must be one of the higher queues used for aggregation
b481de9c 3595 */
c79dd5b5 3596static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
b481de9c
ZY		 3597 int tx_fifo, int sta_id, int tid,
3598 u16 ssn_idx)
3599{
3600 unsigned long flags;
3601 int rc;
3602 u16 ra_tid;
3603
3604 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3605 IWL_WARNING("queue number too small: %d, must be > %d\n",
3606 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3607
3608 ra_tid = BUILD_RAxTID(sta_id, tid);
3609
8b6eaea8 3610 /* Modify device's station table to Tx this TID */
bb8c093b 3611 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 3612
3613 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 3614 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3615 if (rc) {
3616 spin_unlock_irqrestore(&priv->lock, flags);
3617 return rc;
3618 }
3619
8b6eaea8 3620 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 3621 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3622
8b6eaea8 3623 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 3624 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3625
8b6eaea8 3626 /* Set this queue as a chain-building queue */
12a81f60 3627 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 3628
8b6eaea8
CB		 3629 /* Place first TFD at index corresponding to start sequence number.
3630 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 3631 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3632 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 3633 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3634
8b6eaea8 3635 /* Set up Tx window size and frame limit for this queue */
3395f6e9 3636 iwl_write_targ_mem(priv,
038669e4
EG		 3637 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3638 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3639 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
b481de9c 3640
3395f6e9 3641 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 3642 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3643 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3644 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c 3645
12a81f60 3646 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 3647
8b6eaea8 3648 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 3649 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3650
3395f6e9 3651 iwl_release_nic_access(priv);
b481de9c
ZY		 3652 spin_unlock_irqrestore(&priv->lock, flags);
3653
3654 return 0;
3655}
3656
c8b0e6e1 3657#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 3658
3659/**
3660 * iwl4965_add_station - Initialize a station's hardware rate table
3661 *
8b6eaea8 3662 * The uCode's station table contains a table of fallback rates
b481de9c
ZY		 3663 * for automatic fallback during transmission.
3664 *
8b6eaea8
CB		 3665 * NOTE: This sets up a default set of values. These will be replaced later
3666 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3667 * rc80211_simple.
b481de9c 3668 *
8b6eaea8
CB		 3669 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3670 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3671 * which requires station table entry to exist).
b481de9c 3672 */
c79dd5b5 3673void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 3674{
3675 int i, r;
66c73db7 3676 struct iwl_link_quality_cmd link_cmd = {
b481de9c
ZY		 3677 .reserved1 = 0,
3678 };
3679 u16 rate_flags;
3680
8b6eaea8
CB		 3681 /* Set up the rate scaling to start at selected rate, fall back
3682 * all the way down to 1M in IEEE order, and then spin on 1M */
b481de9c
ZY		 3683 if (is_ap)
3684 r = IWL_RATE_54M_INDEX;
8318d78a 3685 else if (priv->band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 3686 r = IWL_RATE_6M_INDEX;
3687 else
3688 r = IWL_RATE_1M_INDEX;
3689
3690 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3691 rate_flags = 0;
3692 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3693 rate_flags |= RATE_MCS_CCK_MSK;
3694
8b6eaea8 3695 /* Use Tx antenna B only */
fde0db31 3696 rate_flags |= RATE_MCS_ANT_B_MSK; /*FIXME:RS*/
8b6eaea8 3697
b481de9c 3698 link_cmd.rs_table[i].rate_n_flags =
bb8c093b
CH		 3699 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3700 r = iwl4965_get_prev_ieee_rate(r);
b481de9c
ZY		 3701 }
3702
3703 link_cmd.general_params.single_stream_ant_msk = 2;
3704 link_cmd.general_params.dual_stream_ant_msk = 3;
3705 link_cmd.agg_params.agg_dis_start_th = 3;
3706 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3707
3708 /* Update the rate scaling for control frame Tx to AP */
5425e490 3709 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
b481de9c 3710
e5472978
TW		 3711 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3712 sizeof(link_cmd), &link_cmd, NULL);
b481de9c
ZY		 3713}
3714
c8b0e6e1 3715#ifdef CONFIG_IWL4965_HT
b481de9c 3716
c79dd5b5 3717static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
8318d78a 3718 enum ieee80211_band band,
78330fdd 3719 u16 channel, u8 extension_chan_offset)
b481de9c 3720{
bf85ea4f 3721 const struct iwl_channel_info *ch_info;
b481de9c 3722
8622e705 3723 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 3724 if (!is_channel_valid(ch_info))
3725 return 0;
3726
134eb5d3 3727 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
b481de9c
ZY		 3728 return 0;
3729
3730 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3731 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3732 return 1;
3733
3734 return 0;
3735}
3736
c79dd5b5 3737static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
fd105e79 3738 struct ieee80211_ht_info *sta_ht_inf)
b481de9c 3739{
fd105e79 3740 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
b481de9c 3741
fd105e79
RR		 3742 if ((!iwl_ht_conf->is_ht) ||
3743 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
134eb5d3 3744 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
b481de9c
ZY		 3745 return 0;
3746
fd105e79
RR		 3747 if (sta_ht_inf) {
3748 if ((!sta_ht_inf->ht_supported) ||
194c7ca6 3749 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
fd105e79
RR		 3750 return 0;
3751 }
b481de9c 3752
78330fdd 3753 return (iwl4965_is_channel_extension(priv, priv->band,
fd105e79
RR		 3754 iwl_ht_conf->control_channel,
3755 iwl_ht_conf->extension_chan_offset));
b481de9c
ZY		 3756}
3757
c79dd5b5 3758void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
b481de9c 3759{
bb8c093b 3760 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 3761 u32 val;
3762
3763 if (!ht_info->is_ht)
3764 return;
3765
8b6eaea8 3766 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
fd105e79 3767 if (iwl4965_is_fat_tx_allowed(priv, NULL))
b481de9c
ZY		 3768 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3769 else
3770 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
3771 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
3772
3773 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
3774 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
3775 le16_to_cpu(rxon->channel),
3776 ht_info->control_channel);
3777 rxon->channel = cpu_to_le16(ht_info->control_channel);
3778 return;
3779 }
3780
8b6eaea8 3781 /* Note: control channel is opposite of extension channel */
b481de9c
ZY		 3782 switch (ht_info->extension_chan_offset) {
3783 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
3784 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
3785 break;
3786 case IWL_EXT_CHANNEL_OFFSET_BELOW:
3787 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3788 break;
134eb5d3 3789 case IWL_EXT_CHANNEL_OFFSET_NONE:
b481de9c
ZY		 3790 default:
3791 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3792 break;
3793 }
3794
fd105e79 3795 val = ht_info->ht_protection;
b481de9c
ZY		 3796
3797 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
3798
c7de35cd 3799 iwl_set_rxon_chain(priv);
b481de9c 3800
fde0db31 3801 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
b481de9c
ZY		 3802 "rxon flags 0x%X operation mode :0x%X "
3803 "extension channel offset 0x%x "
3804 "control chan %d\n",
fde0db31
GC		 3805 ht_info->supp_mcs_set[0],
3806 ht_info->supp_mcs_set[1],
3807 ht_info->supp_mcs_set[2],
fd105e79 3808 le32_to_cpu(rxon->flags), ht_info->ht_protection,
b481de9c
ZY		 3809 ht_info->extension_chan_offset,
3810 ht_info->control_channel);
3811 return;
3812}
3813
c79dd5b5 3814void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
67d62035 3815 struct ieee80211_ht_info *sta_ht_inf)
b481de9c
ZY		 3816{
3817 __le32 sta_flags;
e53cfe0e 3818 u8 mimo_ps_mode;
b481de9c 3819
67d62035 3820 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
b481de9c
ZY		 3821 goto done;
3822
e53cfe0e
TW		 3823 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
3824
b481de9c
ZY		 3825 sta_flags = priv->stations[index].sta.station_flags;
3826
e53cfe0e
TW		 3827 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
3828
3829 switch (mimo_ps_mode) {
3830 case WLAN_HT_CAP_MIMO_PS_STATIC:
3831 sta_flags |= STA_FLG_MIMO_DIS_MSK;
3832 break;
3833 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
b481de9c 3834 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
e53cfe0e
TW		 3835 break;
3836 case WLAN_HT_CAP_MIMO_PS_DISABLED:
3837 break;
3838 default:
3839 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
3840 break;
3841 }
b481de9c
ZY		 3842
3843 sta_flags |= cpu_to_le32(
67d62035 3844 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
b481de9c
ZY		 3845
3846 sta_flags |= cpu_to_le32(
67d62035 3847 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
b481de9c 3848
67d62035 3849 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
b481de9c 3850 sta_flags |= STA_FLG_FAT_EN_MSK;
67d62035 3851 else
e53cfe0e 3852 sta_flags &= ~STA_FLG_FAT_EN_MSK;
67d62035 3853
b481de9c
ZY		 3854 priv->stations[index].sta.station_flags = sta_flags;
3855 done:
3856 return;
3857}
3858
fe07aa7a
RR		 3859static int iwl4965_rx_agg_start(struct iwl_priv *priv,
3860 const u8 *addr, int tid, u16 ssn)
b481de9c
ZY		 3861{
3862 unsigned long flags;
fe07aa7a
RR		 3863 int sta_id;
3864
3865 sta_id = iwl_find_station(priv, addr);
3866 if (sta_id == IWL_INVALID_STATION)
3867 return -ENXIO;
b481de9c
ZY		 3868
3869 spin_lock_irqsave(&priv->sta_lock, flags);
3870 priv->stations[sta_id].sta.station_flags_msk = 0;
3871 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
3872 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
3873 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
3874 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3875 spin_unlock_irqrestore(&priv->sta_lock, flags);
3876
fe07aa7a
RR		 3877 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
3878 CMD_ASYNC);
b481de9c
ZY		 3879}
3880
fe07aa7a
RR		 3881static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
3882 const u8 *addr, int tid)
b481de9c
ZY		 3883{
3884 unsigned long flags;
fe07aa7a
RR		 3885 int sta_id;
3886
3887 sta_id = iwl_find_station(priv, addr);
3888 if (sta_id == IWL_INVALID_STATION)
3889 return -ENXIO;
b481de9c
ZY		 3890
3891 spin_lock_irqsave(&priv->sta_lock, flags);
3892 priv->stations[sta_id].sta.station_flags_msk = 0;
3893 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
3894 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
3895 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3896 spin_unlock_irqrestore(&priv->sta_lock, flags);
3897
fe07aa7a
RR		 3898 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
3899 CMD_ASYNC);
b481de9c
ZY		 3900}
3901
8b6eaea8
CB		 3902/*
3903 * Find first available (lowest unused) Tx Queue, mark it "active".
3904 * Called only when finding queue for aggregation.
3905 * Should never return anything < 7, because they should already
3906 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
3907 */
c79dd5b5 3908static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
b481de9c
ZY		 3909{
3910 int txq_id;
3911
5425e490 3912 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
b481de9c
ZY		 3913 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
3914 return txq_id;
3915 return -1;
3916}
3917
fe07aa7a
RR		 3918static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
3919 u16 tid, u16 *start_seq_num)
b481de9c 3920{
c79dd5b5 3921 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 3922 int sta_id;
3923 int tx_fifo;
3924 int txq_id;
3925 int ssn = -1;
b095d03a 3926 int ret = 0;
b481de9c 3927 unsigned long flags;
bb8c093b 3928 struct iwl4965_tid_data *tid_data;
0795af57 3929 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 3930
3931 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
3932 tx_fifo = default_tid_to_tx_fifo[tid];
3933 else
3934 return -EINVAL;
3935
fe07aa7a
RR		 3936 IWL_WARNING("%s on ra = %s tid = %d\n",
3937 __func__, print_mac(mac, ra), tid);
b481de9c 3938
fe07aa7a 3939 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 3940 if (sta_id == IWL_INVALID_STATION)
3941 return -ENXIO;
3942
fe01b477
RR		 3943 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
3944 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
3945 return -ENXIO;
3946 }
3947
bb8c093b 3948 txq_id = iwl4965_txq_ctx_activate_free(priv);
b481de9c
ZY		 3949 if (txq_id == -1)
3950 return -ENXIO;
3951
3952 spin_lock_irqsave(&priv->sta_lock, flags);
3953 tid_data = &priv->stations[sta_id].tid[tid];
3954 ssn = SEQ_TO_SN(tid_data->seq_number);
3955 tid_data->agg.txq_id = txq_id;
3956 spin_unlock_irqrestore(&priv->sta_lock, flags);
3957
3958 *start_seq_num = ssn;
b095d03a
RR		 3959 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
3960 sta_id, tid, ssn);
3961 if (ret)
3962 return ret;
b481de9c 3963
b095d03a 3964 ret = 0;
fe01b477
RR		 3965 if (tid_data->tfds_in_queue == 0) {
3966 printk(KERN_ERR "HW queue is empty\n");
3967 tid_data->agg.state = IWL_AGG_ON;
fe07aa7a 3968 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
fe01b477
RR		 3969 } else {
3970 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
3971 tid_data->tfds_in_queue);
3972 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
3973 }
b095d03a 3974 return ret;
fe01b477 3975}
b481de9c 3976
fe07aa7a 3977static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
b481de9c 3978{
c79dd5b5 3979 struct iwl_priv *priv = hw->priv;
b481de9c 3980 int tx_fifo_id, txq_id, sta_id, ssn = -1;
bb8c093b 3981 struct iwl4965_tid_data *tid_data;
b095d03a 3982 int ret, write_ptr, read_ptr;
fe01b477 3983 unsigned long flags;
0795af57
JP		 3984 DECLARE_MAC_BUF(mac);
3985
fe07aa7a
RR		 3986 if (!ra) {
3987 IWL_ERROR("ra = NULL\n");
b481de9c
ZY		 3988 return -EINVAL;
3989 }
3990
3991 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
3992 tx_fifo_id = default_tid_to_tx_fifo[tid];
3993 else
3994 return -EINVAL;
3995
fe07aa7a 3996 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 3997
3998 if (sta_id == IWL_INVALID_STATION)
3999 return -ENXIO;
4000
fe01b477
RR		 4001 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4002 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4003
b481de9c
ZY		 4004 tid_data = &priv->stations[sta_id].tid[tid];
4005 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4006 txq_id = tid_data->agg.txq_id;
fe01b477
RR		 4007 write_ptr = priv->txq[txq_id].q.write_ptr;
4008 read_ptr = priv->txq[txq_id].q.read_ptr;
4009
4010 /* The queue is not empty */
4011 if (write_ptr != read_ptr) {
4012 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4013 priv->stations[sta_id].tid[tid].agg.state =
4014 IWL_EMPTYING_HW_QUEUE_DELBA;
4015 return 0;
4016 }
4017
fe07aa7a 4018 IWL_DEBUG_HT("HW queue is empty\n");
fe01b477 4019 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
b481de9c 4020
fe01b477 4021 spin_lock_irqsave(&priv->lock, flags);
b095d03a 4022 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
fe01b477
RR		 4023 spin_unlock_irqrestore(&priv->lock, flags);
4024
b095d03a
RR		 4025 if (ret)
4026 return ret;
b481de9c 4027
fe07aa7a 4028 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
8114fcf1 4029
8114fcf1
RR		 4030 return 0;
4031}
4032
4033int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4034 enum ieee80211_ampdu_mlme_action action,
4035 const u8 *addr, u16 tid, u16 *ssn)
4036{
c79dd5b5 4037 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 4038 DECLARE_MAC_BUF(mac);
4039
fe07aa7a
RR		 4040 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4041 print_mac(mac, addr), tid);
4042
8114fcf1
RR		 4043 switch (action) {
4044 case IEEE80211_AMPDU_RX_START:
4045 IWL_DEBUG_HT("start Rx\n");
fe07aa7a 4046 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
8114fcf1
RR		 4047 case IEEE80211_AMPDU_RX_STOP:
4048 IWL_DEBUG_HT("stop Rx\n");
fe07aa7a 4049 return iwl4965_rx_agg_stop(priv, addr, tid);
8114fcf1
RR		 4050 case IEEE80211_AMPDU_TX_START:
4051 IWL_DEBUG_HT("start Tx\n");
fe07aa7a 4052 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
8114fcf1
RR		 4053 case IEEE80211_AMPDU_TX_STOP:
4054 IWL_DEBUG_HT("stop Tx\n");
fe07aa7a 4055 return iwl4965_tx_agg_stop(hw, addr, tid);
8114fcf1
RR		 4056 default:
4057 IWL_DEBUG_HT("unknown\n");
4058 return -EINVAL;
4059 break;
4060 }
4061 return 0;
4062}
4063
c8b0e6e1 4064#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4065
4066/* Set up 4965-specific Rx frame reply handlers */
d4789efe 4067static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 4068{
4069 /* Legacy Rx frames */
857485c0 4070 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
b481de9c
ZY		 4071
4072 /* High-throughput (HT) Rx frames */
4073 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4074 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4075
4076 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4077 iwl4965_rx_missed_beacon_notif;
4078
c8b0e6e1 4079#ifdef CONFIG_IWL4965_HT
b481de9c 4080 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
c8b0e6e1 4081#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4082}
4083
c79dd5b5 4084void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4085{
4086 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
f0832f13 4087#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 4088 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4089#endif
b481de9c
ZY		 4090 init_timer(&priv->statistics_periodic);
4091 priv->statistics_periodic.data = (unsigned long)priv;
4092 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4093}
4094
c79dd5b5 4095void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4096{
4097 del_timer_sync(&priv->statistics_periodic);
4098
4099 cancel_delayed_work(&priv->init_alive_start);
4100}
4101
3c424c28
TW		 4102
4103static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 4104 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 4105};
4106
857485c0
TW		 4107static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4108 .enqueue_hcmd = iwl4965_enqueue_hcmd,
f0832f13
EG		 4109#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4110 .chain_noise_reset = iwl4965_chain_noise_reset,
4111 .gain_computation = iwl4965_gain_computation,
4112#endif
857485c0
TW		 4113};
4114
6bc913bd 4115static struct iwl_lib_ops iwl4965_lib = {
5425e490 4116 .set_hw_params = iwl4965_hw_set_hw_params,
399f4900
RR		 4117 .alloc_shared_mem = iwl4965_alloc_shared_mem,
4118 .free_shared_mem = iwl4965_free_shared_mem,
e2a722eb 4119 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
57aab75a 4120 .hw_nic_init = iwl4965_hw_nic_init,
d4789efe 4121 .rx_handler_setup = iwl4965_rx_handler_setup,
57aab75a
TW		 4122 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4123 .alive_notify = iwl4965_alive_notify,
4124 .load_ucode = iwl4965_load_bsm,
6f4083aa 4125 .apm_ops = {
91238714 4126 .init = iwl4965_apm_init,
694cc56d 4127 .config = iwl4965_nic_config,
6f4083aa
TW		 4128 .set_pwr_src = iwl4965_set_pwr_src,
4129 },
6bc913bd 4130 .eeprom_ops = {
073d3f5f
TW		 4131 .regulatory_bands = {
4132 EEPROM_REGULATORY_BAND_1_CHANNELS,
4133 EEPROM_REGULATORY_BAND_2_CHANNELS,
4134 EEPROM_REGULATORY_BAND_3_CHANNELS,
4135 EEPROM_REGULATORY_BAND_4_CHANNELS,
4136 EEPROM_REGULATORY_BAND_5_CHANNELS,
4137 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
4138 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
4139 },
6bc913bd
AK		 4140 .verify_signature = iwlcore_eeprom_verify_signature,
4141 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4142 .release_semaphore = iwlcore_eeprom_release_semaphore,
8614f360 4143 .check_version = iwl4965_eeprom_check_version,
073d3f5f 4144 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 4145 },
ad97edd2 4146 .radio_kill_sw = iwl4965_radio_kill_sw,
5da4b55f
MA		 4147 .set_power = iwl4965_set_power,
4148 .update_chain_flags = iwl4965_update_chain_flags,
6bc913bd
AK		 4149};
4150
4151static struct iwl_ops iwl4965_ops = {
4152 .lib = &iwl4965_lib,
3c424c28 4153 .hcmd = &iwl4965_hcmd,
857485c0 4154 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 4155};
4156
fed9017e 4157struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 4158 .name = "4965AGN",
4bf775cd 4159 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 4160 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 4161 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
6bc913bd 4162 .ops = &iwl4965_ops,
1ea87396 4163 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 4164};
4165
1ea87396
AK		 4166module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4167MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4168module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4169MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b
EG		 4170module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4171MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
1ea87396
AK		 4172module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4173MODULE_PARM_DESC(debug, "debug output mask");
4174module_param_named(
4175 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4176MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4177
4178module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4179MODULE_PARM_DESC(queues_num, "number of hw queues.");
4180
4181/* QoS */
4182module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4183MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4184module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4185MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4186
Linux kernel - Deliverables
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