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iwlwifi: add apm init handler
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
b481de9c 42#include "iwl-4965.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c 45#include "iwl-helpers.h"
f0832f13 46#include "iwl-calib.h"
b481de9c 47
1ea87396
AK		 48/* module parameters */
49static struct iwl_mod_params iwl4965_mod_params = {
dfe7d458 50 .num_of_queues = IWL4965_MAX_NUM_QUEUES,
1ea87396
AK		 51 .enable_qos = 1,
52 .amsdu_size_8K = 1,
53 /* the rest are 0 by default */
54};
55
c79dd5b5 56static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
416e1438 57
b481de9c
ZY		 58#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
59 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
60 IWL_RATE_SISO_##s##M_PLCP, \
fde0db31
GC		 61 IWL_RATE_MIMO2_##s##M_PLCP,\
62 IWL_RATE_MIMO3_##s##M_PLCP,\
b481de9c
ZY		 63 IWL_RATE_##r##M_IEEE, \
64 IWL_RATE_##ip##M_INDEX, \
65 IWL_RATE_##in##M_INDEX, \
66 IWL_RATE_##rp##M_INDEX, \
67 IWL_RATE_##rn##M_INDEX, \
68 IWL_RATE_##pp##M_INDEX, \
69 IWL_RATE_##np##M_INDEX }
70
71/*
72 * Parameter order:
73 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
74 *
75 * If there isn't a valid next or previous rate then INV is used which
76 * maps to IWL_RATE_INVALID
77 *
78 */
bb8c093b 79const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
b481de9c
ZY		 80 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
81 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
82 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
83 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
84 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
85 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
86 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
87 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
88 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
89 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
90 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
91 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
92 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
fde0db31 93 /* FIXME:RS: ^^ should be INV (legacy) */
b481de9c
ZY		 94};
95
fe01b477
RR		 96#ifdef CONFIG_IWL4965_HT
97
98static const u16 default_tid_to_tx_fifo[] = {
99 IWL_TX_FIFO_AC1,
100 IWL_TX_FIFO_AC0,
101 IWL_TX_FIFO_AC0,
102 IWL_TX_FIFO_AC1,
103 IWL_TX_FIFO_AC2,
104 IWL_TX_FIFO_AC2,
105 IWL_TX_FIFO_AC3,
106 IWL_TX_FIFO_AC3,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_NONE,
113 IWL_TX_FIFO_NONE,
114 IWL_TX_FIFO_NONE,
115 IWL_TX_FIFO_AC3
116};
117
118#endif /*CONFIG_IWL4965_HT */
119
57aab75a
TW		 120/* check contents of special bootstrap uCode SRAM */
121static int iwl4965_verify_bsm(struct iwl_priv *priv)
122{
123 __le32 *image = priv->ucode_boot.v_addr;
124 u32 len = priv->ucode_boot.len;
125 u32 reg;
126 u32 val;
127
128 IWL_DEBUG_INFO("Begin verify bsm\n");
129
130 /* verify BSM SRAM contents */
131 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
132 for (reg = BSM_SRAM_LOWER_BOUND;
133 reg < BSM_SRAM_LOWER_BOUND + len;
134 reg += sizeof(u32), image++) {
135 val = iwl_read_prph(priv, reg);
136 if (val != le32_to_cpu(*image)) {
137 IWL_ERROR("BSM uCode verification failed at "
138 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
139 BSM_SRAM_LOWER_BOUND,
140 reg - BSM_SRAM_LOWER_BOUND, len,
141 val, le32_to_cpu(*image));
142 return -EIO;
143 }
144 }
145
146 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
147
148 return 0;
149}
150
151/**
152 * iwl4965_load_bsm - Load bootstrap instructions
153 *
154 * BSM operation:
155 *
156 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
157 * in special SRAM that does not power down during RFKILL. When powering back
158 * up after power-saving sleeps (or during initial uCode load), the BSM loads
159 * the bootstrap program into the on-board processor, and starts it.
160 *
161 * The bootstrap program loads (via DMA) instructions and data for a new
162 * program from host DRAM locations indicated by the host driver in the
163 * BSM_DRAM_* registers. Once the new program is loaded, it starts
164 * automatically.
165 *
166 * When initializing the NIC, the host driver points the BSM to the
167 * "initialize" uCode image. This uCode sets up some internal data, then
168 * notifies host via "initialize alive" that it is complete.
169 *
170 * The host then replaces the BSM_DRAM_* pointer values to point to the
171 * normal runtime uCode instructions and a backup uCode data cache buffer
172 * (filled initially with starting data values for the on-board processor),
173 * then triggers the "initialize" uCode to load and launch the runtime uCode,
174 * which begins normal operation.
175 *
176 * When doing a power-save shutdown, runtime uCode saves data SRAM into
177 * the backup data cache in DRAM before SRAM is powered down.
178 *
179 * When powering back up, the BSM loads the bootstrap program. This reloads
180 * the runtime uCode instructions and the backup data cache into SRAM,
181 * and re-launches the runtime uCode from where it left off.
182 */
183static int iwl4965_load_bsm(struct iwl_priv *priv)
184{
185 __le32 *image = priv->ucode_boot.v_addr;
186 u32 len = priv->ucode_boot.len;
187 dma_addr_t pinst;
188 dma_addr_t pdata;
189 u32 inst_len;
190 u32 data_len;
191 int i;
192 u32 done;
193 u32 reg_offset;
194 int ret;
195
196 IWL_DEBUG_INFO("Begin load bsm\n");
197
198 /* make sure bootstrap program is no larger than BSM's SRAM size */
199 if (len > IWL_MAX_BSM_SIZE)
200 return -EINVAL;
201
202 /* Tell bootstrap uCode where to find the "Initialize" uCode
203 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
204 * NOTE: iwl4965_initialize_alive_start() will replace these values,
205 * after the "initialize" uCode has run, to point to
206 * runtime/protocol instructions and backup data cache. */
207 pinst = priv->ucode_init.p_addr >> 4;
208 pdata = priv->ucode_init_data.p_addr >> 4;
209 inst_len = priv->ucode_init.len;
210 data_len = priv->ucode_init_data.len;
211
212 ret = iwl_grab_nic_access(priv);
213 if (ret)
214 return ret;
215
216 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
217 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
218 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
219 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
220
221 /* Fill BSM memory with bootstrap instructions */
222 for (reg_offset = BSM_SRAM_LOWER_BOUND;
223 reg_offset < BSM_SRAM_LOWER_BOUND + len;
224 reg_offset += sizeof(u32), image++)
225 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
226
227 ret = iwl4965_verify_bsm(priv);
228 if (ret) {
229 iwl_release_nic_access(priv);
230 return ret;
231 }
232
233 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
234 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
235 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
236 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
237
238 /* Load bootstrap code into instruction SRAM now,
239 * to prepare to load "initialize" uCode */
240 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
241
242 /* Wait for load of bootstrap uCode to finish */
243 for (i = 0; i < 100; i++) {
244 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
245 if (!(done & BSM_WR_CTRL_REG_BIT_START))
246 break;
247 udelay(10);
248 }
249 if (i < 100)
250 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
251 else {
252 IWL_ERROR("BSM write did not complete!\n");
253 return -EIO;
254 }
255
256 /* Enable future boot loads whenever power management unit triggers it
257 * (e.g. when powering back up after power-save shutdown) */
258 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
259
260 iwl_release_nic_access(priv);
261
262 return 0;
263}
264
bf85ea4f
AK		 265static int iwl4965_init_drv(struct iwl_priv *priv)
266{
267 int ret;
268 int i;
269
bf85ea4f
AK		 270 priv->retry_rate = 1;
271 priv->ibss_beacon = NULL;
272
273 spin_lock_init(&priv->lock);
274 spin_lock_init(&priv->power_data.lock);
275 spin_lock_init(&priv->sta_lock);
276 spin_lock_init(&priv->hcmd_lock);
277 spin_lock_init(&priv->lq_mngr.lock);
278
059ff826
TW		 279 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
280 sizeof(struct iwl4965_shared),
281 &priv->shared_phys);
282
283 if (!priv->shared_virt) {
284 ret = -ENOMEM;
285 goto err;
286 }
287
288 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
289
290
bf85ea4f
AK		 291 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
292 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
293
294 INIT_LIST_HEAD(&priv->free_frames);
295
296 mutex_init(&priv->mutex);
297
298 /* Clear the driver's (not device's) station table */
299 iwlcore_clear_stations_table(priv);
300
301 priv->data_retry_limit = -1;
302 priv->ieee_channels = NULL;
303 priv->ieee_rates = NULL;
304 priv->band = IEEE80211_BAND_2GHZ;
305
306 priv->iw_mode = IEEE80211_IF_TYPE_STA;
307
308 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
bf85ea4f
AK		 309 priv->ps_mode = IWL_MIMO_PS_NONE;
310
311 /* Choose which receivers/antennas to use */
312 iwl4965_set_rxon_chain(priv);
313
314 iwlcore_reset_qos(priv);
315
316 priv->qos_data.qos_active = 0;
317 priv->qos_data.qos_cap.val = 0;
318
319 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
320
321 priv->rates_mask = IWL_RATES_MASK;
322 /* If power management is turned on, default to AC mode */
323 priv->power_mode = IWL_POWER_AC;
324 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
325
326 ret = iwl_init_channel_map(priv);
327 if (ret) {
328 IWL_ERROR("initializing regulatory failed: %d\n", ret);
329 goto err;
330 }
331
332 ret = iwl4965_init_geos(priv);
333 if (ret) {
334 IWL_ERROR("initializing geos failed: %d\n", ret);
335 goto err_free_channel_map;
336 }
337
bf85ea4f
AK		 338 ret = ieee80211_register_hw(priv->hw);
339 if (ret) {
340 IWL_ERROR("Failed to register network device (error %d)\n",
341 ret);
342 goto err_free_geos;
343 }
344
345 priv->hw->conf.beacon_int = 100;
346 priv->mac80211_registered = 1;
347
348 return 0;
349
350err_free_geos:
351 iwl4965_free_geos(priv);
352err_free_channel_map:
353 iwl_free_channel_map(priv);
354err:
355 return ret;
356}
357
b481de9c
ZY		 358static int is_fat_channel(__le32 rxon_flags)
359{
360 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
361 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
362}
363
c8b0e6e1 364#ifdef CONFIG_IWL4965_HT
fde0db31
GC		 365static u8 is_single_rx_stream(struct iwl_priv *priv)
366{
367 return !priv->current_ht_config.is_ht ||
368 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
369 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
370 priv->ps_mode == IWL_MIMO_PS_STATIC;
371}
b481de9c 372#else
fde0db31
GC		 373static inline u8 is_single_rx_stream(struct iwl_priv *priv)
374{
b481de9c 375 return 1;
b481de9c 376}
fde0db31 377#endif /*CONFIG_IWL4965_HT */
b481de9c 378
17744ff6
TW		 379int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
380{
381 int idx = 0;
382
383 /* 4965 HT rate format */
384 if (rate_n_flags & RATE_MCS_HT_MSK) {
385 idx = (rate_n_flags & 0xff);
386
fde0db31
GC		 387 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
388 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
17744ff6
TW		 389
390 idx += IWL_FIRST_OFDM_RATE;
391 /* skip 9M not supported in ht*/
392 if (idx >= IWL_RATE_9M_INDEX)
393 idx += 1;
394 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
395 return idx;
396
397 /* 4965 legacy rate format, search for match in table */
398 } else {
399 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
400 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
401 return idx;
402 }
403
404 return -1;
405}
406
4c424e4c
RR		 407/**
408 * translate ucode response to mac80211 tx status control values
409 */
c79dd5b5 410void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
4c424e4c
RR		 411 struct ieee80211_tx_control *control)
412{
413 int rate_index;
414
415 control->antenna_sel_tx =
fde0db31 416 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
4c424e4c
RR		 417 if (rate_n_flags & RATE_MCS_HT_MSK)
418 control->flags |= IEEE80211_TXCTL_OFDM_HT;
419 if (rate_n_flags & RATE_MCS_GF_MSK)
420 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
421 if (rate_n_flags & RATE_MCS_FAT_MSK)
422 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
423 if (rate_n_flags & RATE_MCS_DUP_MSK)
424 control->flags |= IEEE80211_TXCTL_DUP_DATA;
425 if (rate_n_flags & RATE_MCS_SGI_MSK)
426 control->flags |= IEEE80211_TXCTL_SHORT_GI;
427 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
428 * IEEE80211_BAND_2GHZ band as it contains all the rates */
429 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
430 if (rate_index == -1)
431 control->tx_rate = NULL;
432 else
433 control->tx_rate =
434 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
435}
17744ff6 436
b481de9c
ZY		 437/*
438 * Determine how many receiver/antenna chains to use.
439 * More provides better reception via diversity. Fewer saves power.
440 * MIMO (dual stream) requires at least 2, but works better with 3.
441 * This does not determine *which* chains to use, just how many.
442 */
c79dd5b5 443static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
b481de9c
ZY		 444 u8 *idle_state, u8 *rx_state)
445{
fde0db31 446 u8 is_single = is_single_rx_stream(priv);
b481de9c
ZY		 447 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
448
449 /* # of Rx chains to use when expecting MIMO. */
450 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
451 *rx_state = 2;
452 else
453 *rx_state = 3;
454
455 /* # Rx chains when idling and maybe trying to save power */
456 switch (priv->ps_mode) {
457 case IWL_MIMO_PS_STATIC:
458 case IWL_MIMO_PS_DYNAMIC:
459 *idle_state = (is_cam) ? 2 : 1;
460 break;
461 case IWL_MIMO_PS_NONE:
462 *idle_state = (is_cam) ? *rx_state : 1;
463 break;
464 default:
465 *idle_state = 1;
466 break;
467 }
468
469 return 0;
470}
471
c79dd5b5 472int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 473{
474 int rc;
475 unsigned long flags;
476
477 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 478 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 479 if (rc) {
480 spin_unlock_irqrestore(&priv->lock, flags);
481 return rc;
482 }
483
8b6eaea8 484 /* stop Rx DMA */
3395f6e9
TW		 485 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
486 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
b481de9c
ZY		 487 (1 << 24), 1000);
488 if (rc < 0)
489 IWL_ERROR("Can't stop Rx DMA.\n");
490
3395f6e9 491 iwl_release_nic_access(priv);
b481de9c
ZY		 492 spin_unlock_irqrestore(&priv->lock, flags);
493
494 return 0;
495}
496
079a2533 497int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 498{
d8609652 499 int ret;
b481de9c
ZY		 500 unsigned long flags;
501
502 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 503 ret = iwl_grab_nic_access(priv);
d8609652 504 if (ret) {
b481de9c 505 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 506 return ret;
b481de9c
ZY		 507 }
508
6f4083aa 509 if (src == IWL_PWR_SRC_VAUX) {
b481de9c 510 u32 val;
d8609652 511 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
6f4083aa 512 &val);
b481de9c 513
6f4083aa 514 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
3395f6e9 515 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 516 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
517 ~APMG_PS_CTRL_MSK_PWR_SRC);
518 }
519 } else {
3395f6e9 520 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 521 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
522 ~APMG_PS_CTRL_MSK_PWR_SRC);
523 }
b481de9c 524
3395f6e9 525 iwl_release_nic_access(priv);
b481de9c
ZY		 526 spin_unlock_irqrestore(&priv->lock, flags);
527
d8609652 528 return ret;
b481de9c
ZY		 529}
530
c79dd5b5 531static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c 532{
059ff826 533 int ret;
b481de9c 534 unsigned long flags;
9ee1ba47 535 unsigned int rb_size;
b481de9c
ZY		 536
537 spin_lock_irqsave(&priv->lock, flags);
059ff826
TW		 538 ret = iwl_grab_nic_access(priv);
539 if (ret) {
b481de9c 540 spin_unlock_irqrestore(&priv->lock, flags);
059ff826 541 return ret;
b481de9c
ZY		 542 }
543
1ea87396 544 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 545 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
546 else
547 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
548
8b6eaea8 549 /* Stop Rx DMA */
3395f6e9 550 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
b481de9c 551
8b6eaea8 552 /* Reset driver's Rx queue write index */
3395f6e9 553 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
8b6eaea8
CB		 554
555 /* Tell device where to find RBD circular buffer in DRAM */
3395f6e9
TW		 556 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
557 rxq->dma_addr >> 8);
b481de9c 558
8b6eaea8 559 /* Tell device where in DRAM to update its Rx status */
3395f6e9 560 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
059ff826
TW		 561 (priv->shared_phys +
562 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
b481de9c 563
8b6eaea8 564 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
3395f6e9
TW		 565 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
566 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
567 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
568 rb_size |
059ff826 569 /* 0x10 << 4 | */
3395f6e9 570 (RX_QUEUE_SIZE_LOG <<
b481de9c
ZY		 571 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
572
573 /*
3395f6e9 574 * iwl_write32(priv,CSR_INT_COAL_REG,0);
b481de9c
ZY		 575 */
576
3395f6e9 577 iwl_release_nic_access(priv);
b481de9c
ZY		 578 spin_unlock_irqrestore(&priv->lock, flags);
579
580 return 0;
581}
582
8b6eaea8 583/* Tell 4965 where to find the "keep warm" buffer */
c79dd5b5 584static int iwl4965_kw_init(struct iwl_priv *priv)
b481de9c
ZY		 585{
586 unsigned long flags;
587 int rc;
588
589 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 590 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 591 if (rc)
592 goto out;
593
3395f6e9 594 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
b481de9c 595 priv->kw.dma_addr >> 4);
3395f6e9 596 iwl_release_nic_access(priv);
b481de9c
ZY		 597out:
598 spin_unlock_irqrestore(&priv->lock, flags);
599 return rc;
600}
601
c79dd5b5 602static int iwl4965_kw_alloc(struct iwl_priv *priv)
b481de9c
ZY		 603{
604 struct pci_dev *dev = priv->pci_dev;
bb8c093b 605 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 606
607 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
608 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
609 if (!kw->v_addr)
610 return -ENOMEM;
611
612 return 0;
613}
614
8b6eaea8
CB		 615/**
616 * iwl4965_kw_free - Free the "keep warm" buffer
617 */
c79dd5b5 618static void iwl4965_kw_free(struct iwl_priv *priv)
b481de9c
ZY		 619{
620 struct pci_dev *dev = priv->pci_dev;
bb8c093b 621 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 622
623 if (kw->v_addr) {
624 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
625 memset(kw, 0, sizeof(*kw));
626 }
627}
628
629/**
630 * iwl4965_txq_ctx_reset - Reset TX queue context
631 * Destroys all DMA structures and initialise them again
632 *
633 * @param priv
634 * @return error code
635 */
c79dd5b5 636static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 637{
638 int rc = 0;
639 int txq_id, slots_num;
640 unsigned long flags;
641
642 iwl4965_kw_free(priv);
643
8b6eaea8 644 /* Free all tx/cmd queues and keep-warm buffer */
bb8c093b 645 iwl4965_hw_txq_ctx_free(priv);
b481de9c 646
8b6eaea8 647 /* Alloc keep-warm buffer */
b481de9c
ZY		 648 rc = iwl4965_kw_alloc(priv);
649 if (rc) {
650 IWL_ERROR("Keep Warm allocation failed");
651 goto error_kw;
652 }
653
654 spin_lock_irqsave(&priv->lock, flags);
655
3395f6e9 656 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 657 if (unlikely(rc)) {
658 IWL_ERROR("TX reset failed");
659 spin_unlock_irqrestore(&priv->lock, flags);
660 goto error_reset;
661 }
662
8b6eaea8 663 /* Turn off all Tx DMA channels */
12a81f60 664 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
3395f6e9 665 iwl_release_nic_access(priv);
b481de9c
ZY		 666 spin_unlock_irqrestore(&priv->lock, flags);
667
8b6eaea8 668 /* Tell 4965 where to find the keep-warm buffer */
b481de9c
ZY		 669 rc = iwl4965_kw_init(priv);
670 if (rc) {
671 IWL_ERROR("kw_init failed\n");
672 goto error_reset;
673 }
674
8b6eaea8
CB		 675 /* Alloc and init all (default 16) Tx queues,
676 * including the command queue (#4) */
5425e490 677 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 678 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
679 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 680 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 681 txq_id);
682 if (rc) {
683 IWL_ERROR("Tx %d queue init failed\n", txq_id);
684 goto error;
685 }
686 }
687
688 return rc;
689
690 error:
bb8c093b 691 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 692 error_reset:
693 iwl4965_kw_free(priv);
694 error_kw:
695 return rc;
696}
91238714 697static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 698{
b481de9c 699 unsigned long flags;
91238714 700 int ret = 0;
b481de9c 701
b481de9c 702 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 703 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 704 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 705
91238714
TW		 706 /* set "initialization complete" bit to move adapter
707 * D0U* --> D0A* state */
3395f6e9 708 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 709
91238714
TW		 710 /* wait for clock stabilization */
711 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
712 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
713 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
714 if (ret < 0) {
715 IWL_DEBUG_INFO("Failed to init the card\n");
716 goto out;
b481de9c
ZY		 717 }
718
91238714
TW		 719 ret = iwl_grab_nic_access(priv);
720 if (ret)
721 goto out;
b481de9c 722
91238714 723 /* enable DMA */
3395f6e9
TW		 724 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
725 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 726
727 udelay(20);
728
3395f6e9 729 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 730 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 731
3395f6e9 732 iwl_release_nic_access(priv);
91238714
TW		 733out:
734 spin_unlock_irqrestore(&priv->lock, flags);
735 return ret;
736}
737
738int iwl4965_hw_nic_init(struct iwl_priv *priv)
739{
740 unsigned long flags;
741 struct iwl4965_rx_queue *rxq = &priv->rxq;
742 u8 rev_id;
743 u8 val_link;
744 u32 val;
745 int ret;
746
747 /* nic_init */
748 priv->cfg->ops->lib->apm_ops.init(priv);
749
750 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 751 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
b481de9c
ZY		 752 spin_unlock_irqrestore(&priv->lock, flags);
753
754 /* Determine HW type */
91238714
TW		 755 ret = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
756 if (ret)
757 return ret;
b481de9c
ZY		 758
759 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
760
91238714 761 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
6f4083aa 762
b481de9c
ZY		 763 spin_lock_irqsave(&priv->lock, flags);
764
765 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
766 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
767 /* Enable No Snoop field */
768 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
769 val & ~(1 << 11));
770 }
771
772 spin_unlock_irqrestore(&priv->lock, flags);
773
073d3f5f
TW		 774 if (iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET) <
775 EEPROM_4965_TX_POWER_VERSION) {
b481de9c
ZY		 776 IWL_ERROR("Older EEPROM detected! Aborting.\n");
777 return -EINVAL;
778 }
779
780 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
781
782 /* disable L1 entry -- workaround for pre-B1 */
783 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
784
785 spin_lock_irqsave(&priv->lock, flags);
786
787 /* set CSR_HW_CONFIG_REG for uCode use */
788
3395f6e9
TW		 789 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
790 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
791 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
792 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 793
91238714
TW		 794 ret = iwl_grab_nic_access(priv);
795 if (ret < 0) {
b481de9c
ZY		 796 spin_unlock_irqrestore(&priv->lock, flags);
797 IWL_DEBUG_INFO("Failed to init the card\n");
91238714 798 return ret;
b481de9c
ZY		 799 }
800
3395f6e9
TW		 801 iwl_read_prph(priv, APMG_PS_CTRL_REG);
802 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 803 udelay(5);
3395f6e9 804 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 805
3395f6e9 806 iwl_release_nic_access(priv);
b481de9c
ZY		 807 spin_unlock_irqrestore(&priv->lock, flags);
808
bb8c093b 809 iwl4965_hw_card_show_info(priv);
b481de9c
ZY		 810
811 /* end nic_init */
812
813 /* Allocate the RX queue, or reset if it is already allocated */
814 if (!rxq->bd) {
91238714
TW		 815 ret = iwl4965_rx_queue_alloc(priv);
816 if (ret) {
b481de9c
ZY		 817 IWL_ERROR("Unable to initialize Rx queue\n");
818 return -ENOMEM;
819 }
820 } else
bb8c093b 821 iwl4965_rx_queue_reset(priv, rxq);
b481de9c 822
bb8c093b 823 iwl4965_rx_replenish(priv);
b481de9c
ZY		 824
825 iwl4965_rx_init(priv, rxq);
826
827 spin_lock_irqsave(&priv->lock, flags);
828
829 rxq->need_update = 1;
bb8c093b 830 iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c 831
073d3f5f
TW		 832 /* init the txpower calibration pointer */
833 priv->calib_info = (struct iwl_eeprom_calib_info *)
834 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
835
b481de9c 836 spin_unlock_irqrestore(&priv->lock, flags);
8b6eaea8
CB		 837
838 /* Allocate and init all Tx and Command queues */
91238714
TW		 839 ret = iwl4965_txq_ctx_reset(priv);
840 if (ret)
841 return ret;
b481de9c
ZY		 842
843 set_bit(STATUS_INIT, &priv->status);
844
845 return 0;
846}
847
c79dd5b5 848int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 849{
850 int rc = 0;
851 u32 reg_val;
852 unsigned long flags;
853
854 spin_lock_irqsave(&priv->lock, flags);
855
856 /* set stop master bit */
3395f6e9 857 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 858
3395f6e9 859 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 860
861 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
862 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
863 IWL_DEBUG_INFO("Card in power save, master is already "
864 "stopped\n");
865 else {
3395f6e9 866 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 867 CSR_RESET_REG_FLAG_MASTER_DISABLED,
868 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
869 if (rc < 0) {
870 spin_unlock_irqrestore(&priv->lock, flags);
871 return rc;
872 }
873 }
874
875 spin_unlock_irqrestore(&priv->lock, flags);
876 IWL_DEBUG_INFO("stop master\n");
877
878 return rc;
879}
880
8b6eaea8
CB		 881/**
882 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
883 */
c79dd5b5 884void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c
ZY		 885{
886
887 int txq_id;
888 unsigned long flags;
889
8b6eaea8 890 /* Stop each Tx DMA channel, and wait for it to be idle */
5425e490 891 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c 892 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 893 if (iwl_grab_nic_access(priv)) {
b481de9c
ZY		 894 spin_unlock_irqrestore(&priv->lock, flags);
895 continue;
896 }
897
3395f6e9
TW		 898 iwl_write_direct32(priv,
899 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
900 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
901 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
902 (txq_id), 200);
903 iwl_release_nic_access(priv);
b481de9c
ZY		 904 spin_unlock_irqrestore(&priv->lock, flags);
905 }
906
8b6eaea8 907 /* Deallocate memory for all Tx queues */
bb8c093b 908 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 909}
910
c79dd5b5 911int iwl4965_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 912{
913 int rc = 0;
914 unsigned long flags;
915
bb8c093b 916 iwl4965_hw_nic_stop_master(priv);
b481de9c
ZY		 917
918 spin_lock_irqsave(&priv->lock, flags);
919
3395f6e9 920 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 921
922 udelay(10);
923
3395f6e9
TW		 924 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
925 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 926 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
927 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
928
929 udelay(10);
930
3395f6e9 931 rc = iwl_grab_nic_access(priv);
b481de9c 932 if (!rc) {
3395f6e9
TW		 933 iwl_write_prph(priv, APMG_CLK_EN_REG,
934 APMG_CLK_VAL_DMA_CLK_RQT |
935 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 936
937 udelay(10);
938
3395f6e9
TW		 939 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
940 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 941
3395f6e9 942 iwl_release_nic_access(priv);
b481de9c
ZY		 943 }
944
945 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
946 wake_up_interruptible(&priv->wait_command_queue);
947
948 spin_unlock_irqrestore(&priv->lock, flags);
949
950 return rc;
951
952}
953
954#define REG_RECALIB_PERIOD (60)
955
956/**
957 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
958 *
49ea8596 959 * This callback is provided in order to send a statistics request.
b481de9c
ZY		 960 *
961 * This timer function is continually reset to execute within
962 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
963 * was received. We need to ensure we receive the statistics in order
49ea8596 964 * to update the temperature used for calibrating the TXPOWER.
b481de9c
ZY		 965 */
966static void iwl4965_bg_statistics_periodic(unsigned long data)
967{
c79dd5b5 968 struct iwl_priv *priv = (struct iwl_priv *)data;
b481de9c 969
b481de9c
ZY		 970 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
971 return;
972
49ea8596 973 iwl_send_statistics_request(priv, CMD_ASYNC);
b481de9c
ZY		 974}
975
c79dd5b5 976void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 977{
bb8c093b 978 struct iwl4965_ct_kill_config cmd;
b481de9c 979 unsigned long flags;
857485c0 980 int ret = 0;
b481de9c
ZY		 981
982 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 983 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 984 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
985 spin_unlock_irqrestore(&priv->lock, flags);
986
099b40b7 987 cmd.critical_temperature_R =
b73cdf27
EG		 988 cpu_to_le32(priv->hw_params.ct_kill_threshold);
989
857485c0
TW		 990 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
991 sizeof(cmd), &cmd);
992 if (ret)
b481de9c
ZY		 993 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
994 else
b73cdf27
EG		 995 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
996 "critical temperature is %d\n",
997 cmd.critical_temperature_R);
b481de9c
ZY		 998}
999
f0832f13 1000#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 1001
1002/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1003 * Called after every association, but this runs only once!
1004 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 1005static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 1006{
f0832f13 1007 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 1008
3109ece1 1009 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 1010 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1011
1012 memset(&cmd, 0, sizeof(cmd));
1013 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1014 cmd.diff_gain_a = 0;
1015 cmd.diff_gain_b = 0;
1016 cmd.diff_gain_c = 0;
f0832f13
EG		 1017 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1018 sizeof(cmd), &cmd))
1019 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 1020 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1021 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1022 }
b481de9c
ZY		 1023}
1024
f0832f13
EG		 1025static void iwl4965_gain_computation(struct iwl_priv *priv,
1026 u32 *average_noise,
1027 u16 min_average_noise_antenna_i,
1028 u32 min_average_noise)
b481de9c 1029{
f0832f13
EG		 1030 int i, ret;
1031 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 1032
f0832f13 1033 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 1034
f0832f13
EG		 1035 for (i = 0; i < NUM_RX_CHAINS; i++) {
1036 s32 delta_g = 0;
b481de9c 1037
f0832f13
EG		 1038 if (!(data->disconn_array[i]) &&
1039 (data->delta_gain_code[i] ==
b481de9c 1040 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 1041 delta_g = average_noise[i] - min_average_noise;
1042 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
1043 data->delta_gain_code[i] =
1044 min(data->delta_gain_code[i],
1045 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
1046
1047 data->delta_gain_code[i] =
1048 (data->delta_gain_code[i] | (1 << 2));
1049 } else {
1050 data->delta_gain_code[i] = 0;
b481de9c 1051 }
b481de9c 1052 }
f0832f13
EG		 1053 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1054 data->delta_gain_code[0],
1055 data->delta_gain_code[1],
1056 data->delta_gain_code[2]);
b481de9c 1057
f0832f13
EG		 1058 /* Differential gain gets sent to uCode only once */
1059 if (!data->radio_write) {
1060 struct iwl4965_calibration_cmd cmd;
1061 data->radio_write = 1;
b481de9c 1062
f0832f13
EG		 1063 memset(&cmd, 0, sizeof(cmd));
1064 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1065 cmd.diff_gain_a = data->delta_gain_code[0];
1066 cmd.diff_gain_b = data->delta_gain_code[1];
1067 cmd.diff_gain_c = data->delta_gain_code[2];
1068 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1069 sizeof(cmd), &cmd);
1070 if (ret)
1071 IWL_DEBUG_CALIB("fail sending cmd "
1072 "REPLY_PHY_CALIBRATION_CMD \n");
1073
1074 /* TODO we might want recalculate
1075 * rx_chain in rxon cmd */
1076
1077 /* Mark so we run this algo only once! */
1078 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 1079 }
f0832f13
EG		 1080 data->chain_noise_a = 0;
1081 data->chain_noise_b = 0;
1082 data->chain_noise_c = 0;
1083 data->chain_signal_a = 0;
1084 data->chain_signal_b = 0;
1085 data->chain_signal_c = 0;
1086 data->beacon_count = 0;
b481de9c
ZY		 1087}
1088
1089static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1090{
c79dd5b5 1091 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1092 sensitivity_work);
1093
1094 mutex_lock(&priv->mutex);
1095
1096 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1097 test_bit(STATUS_SCANNING, &priv->status)) {
1098 mutex_unlock(&priv->mutex);
1099 return;
1100 }
1101
1102 if (priv->start_calib) {
f0832f13
EG		 1103 iwl_chain_noise_calibration(priv, &priv->statistics);
1104
1105 iwl_sensitivity_calibration(priv, &priv->statistics);
b481de9c
ZY		 1106 }
1107
1108 mutex_unlock(&priv->mutex);
1109 return;
1110}
f0832f13 1111#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c
ZY		 1112
1113static void iwl4965_bg_txpower_work(struct work_struct *work)
1114{
c79dd5b5 1115 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1116 txpower_work);
1117
1118 /* If a scan happened to start before we got here
1119 * then just return; the statistics notification will
1120 * kick off another scheduled work to compensate for
1121 * any temperature delta we missed here. */
1122 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1123 test_bit(STATUS_SCANNING, &priv->status))
1124 return;
1125
1126 mutex_lock(&priv->mutex);
1127
1128 /* Regardless of if we are assocaited, we must reconfigure the
1129 * TX power since frames can be sent on non-radar channels while
1130 * not associated */
bb8c093b 1131 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 1132
1133 /* Update last_temperature to keep is_calib_needed from running
1134 * when it isn't needed... */
1135 priv->last_temperature = priv->temperature;
1136
1137 mutex_unlock(&priv->mutex);
1138}
1139
1140/*
1141 * Acquire priv->lock before calling this function !
1142 */
c79dd5b5 1143static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 1144{
3395f6e9 1145 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 1146 (index & 0xff) | (txq_id << 8));
12a81f60 1147 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 1148}
1149
8b6eaea8
CB		 1150/**
1151 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1152 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1153 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1154 *
1155 * NOTE: Acquire priv->lock before calling this function !
b481de9c 1156 */
c79dd5b5 1157static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
bb8c093b 1158 struct iwl4965_tx_queue *txq,
b481de9c
ZY		 1159 int tx_fifo_id, int scd_retry)
1160{
1161 int txq_id = txq->q.id;
8b6eaea8
CB		 1162
1163 /* Find out whether to activate Tx queue */
b481de9c
ZY		 1164 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1165
8b6eaea8 1166 /* Set up and activate */
12a81f60 1167 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
b481de9c
ZY		 1168 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1169 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1170 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1171 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1172 SCD_QUEUE_STTS_REG_MSK);
1173
1174 txq->sched_retry = scd_retry;
1175
1176 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 1177 active ? "Activate" : "Deactivate",
b481de9c
ZY		 1178 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1179}
1180
1181static const u16 default_queue_to_tx_fifo[] = {
1182 IWL_TX_FIFO_AC3,
1183 IWL_TX_FIFO_AC2,
1184 IWL_TX_FIFO_AC1,
1185 IWL_TX_FIFO_AC0,
1186 IWL_CMD_FIFO_NUM,
1187 IWL_TX_FIFO_HCCA_1,
1188 IWL_TX_FIFO_HCCA_2
1189};
1190
c79dd5b5 1191static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1192{
1193 set_bit(txq_id, &priv->txq_ctx_active_msk);
1194}
1195
c79dd5b5 1196static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1197{
1198 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1199}
1200
c79dd5b5 1201int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 1202{
1203 u32 a;
1204 int i = 0;
1205 unsigned long flags;
857485c0 1206 int ret;
b481de9c
ZY		 1207
1208 spin_lock_irqsave(&priv->lock, flags);
1209
f0832f13 1210#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c 1211 memset(&(priv->sensitivity_data), 0,
f0832f13 1212 sizeof(struct iwl_sensitivity_data));
b481de9c 1213 memset(&(priv->chain_noise_data), 0,
f0832f13 1214 sizeof(struct iwl_chain_noise_data));
b481de9c
ZY		 1215 for (i = 0; i < NUM_RX_CHAINS; i++)
1216 priv->chain_noise_data.delta_gain_code[i] =
1217 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
f0832f13 1218#endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
3395f6e9 1219 ret = iwl_grab_nic_access(priv);
857485c0 1220 if (ret) {
b481de9c 1221 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 1222 return ret;
b481de9c
ZY		 1223 }
1224
8b6eaea8 1225 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 1226 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
b481de9c
ZY		 1227 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1228 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 1229 iwl_write_targ_mem(priv, a, 0);
b481de9c 1230 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 1231 iwl_write_targ_mem(priv, a, 0);
5425e490 1232 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 1233 iwl_write_targ_mem(priv, a, 0);
b481de9c 1234
8b6eaea8 1235 /* Tel 4965 where to find Tx byte count tables */
12a81f60 1236 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 1237 (priv->shared_phys +
bb8c093b 1238 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 1239
1240 /* Disable chain mode for all queues */
12a81f60 1241 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 1242
8b6eaea8 1243 /* Initialize each Tx queue (including the command queue) */
5425e490 1244 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 1245
1246 /* TFD circular buffer read/write indexes */
12a81f60 1247 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 1248 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 1249
1250 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 1251 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1252 SCD_CONTEXT_QUEUE_OFFSET(i),
1253 (SCD_WIN_SIZE <<
1254 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1255 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 1256
1257 /* Frame limit */
3395f6e9 1258 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1259 SCD_CONTEXT_QUEUE_OFFSET(i) +
1260 sizeof(u32),
1261 (SCD_FRAME_LIMIT <<
1262 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1263 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1264
1265 }
12a81f60 1266 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 1267 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 1268
8b6eaea8 1269 /* Activate all Tx DMA/FIFO channels */
12a81f60 1270 iwl_write_prph(priv, IWL49_SCD_TXFACT,
b481de9c
ZY		 1271 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1272
1273 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 1274
1275 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 1276 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1277 int ac = default_queue_to_tx_fifo[i];
1278 iwl4965_txq_ctx_activate(priv, i);
1279 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1280 }
1281
3395f6e9 1282 iwl_release_nic_access(priv);
b481de9c
ZY		 1283 spin_unlock_irqrestore(&priv->lock, flags);
1284
49ea8596
EG		 1285 /* Ask for statistics now, the uCode will send statistics notification
1286 * periodically after association */
1287 iwl_send_statistics_request(priv, CMD_ASYNC);
857485c0 1288 return ret;
b481de9c
ZY		 1289}
1290
f0832f13
EG		 1291#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1292static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1293 .min_nrg_cck = 97,
1294 .max_nrg_cck = 0,
1295
1296 .auto_corr_min_ofdm = 85,
1297 .auto_corr_min_ofdm_mrc = 170,
1298 .auto_corr_min_ofdm_x1 = 105,
1299 .auto_corr_min_ofdm_mrc_x1 = 220,
1300
1301 .auto_corr_max_ofdm = 120,
1302 .auto_corr_max_ofdm_mrc = 210,
1303 .auto_corr_max_ofdm_x1 = 140,
1304 .auto_corr_max_ofdm_mrc_x1 = 270,
1305
1306 .auto_corr_min_cck = 125,
1307 .auto_corr_max_cck = 200,
1308 .auto_corr_min_cck_mrc = 200,
1309 .auto_corr_max_cck_mrc = 400,
1310
1311 .nrg_th_cck = 100,
1312 .nrg_th_ofdm = 100,
1313};
1314#endif
1315
8b6eaea8 1316/**
5425e490 1317 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 1318 *
1319 * Called when initializing driver
1320 */
5425e490 1321int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 1322{
316c30d9 1323
dfe7d458 1324 if ((priv->cfg->mod_params->num_of_queues > IWL4965_MAX_NUM_QUEUES) ||
1ea87396 1325 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 1326 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 1327 IWL_MIN_NUM_QUEUES, IWL4965_MAX_NUM_QUEUES);
059ff826 1328 return -EINVAL;
316c30d9 1329 }
b481de9c 1330
5425e490 1331 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
099b40b7 1332 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
5425e490
TW		 1333 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1334 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1335 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 1336 if (priv->cfg->mod_params->amsdu_size_8K)
5425e490 1337 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
9ee1ba47 1338 else
5425e490
TW		 1339 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1340 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1341 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1342 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822 1343
099b40b7
RR		 1344 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1345 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1346 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1347 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1348
ec35cf2a
TW		 1349 priv->hw_params.tx_chains_num = 2;
1350 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 1351 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
1352 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 1353 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1354
f0832f13
EG		 1355#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1356 priv->hw_params.sens = &iwl4965_sensitivity;
1357#endif
3e82a822 1358
059ff826 1359 return 0;
b481de9c
ZY		 1360}
1361
1362/**
bb8c093b 1363 * iwl4965_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1364 *
1365 * Destroy all TX DMA queues and structures
1366 */
c79dd5b5 1367void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1368{
1369 int txq_id;
1370
1371 /* Tx queues */
5425e490 1372 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
bb8c093b 1373 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c 1374
8b6eaea8 1375 /* Keep-warm buffer */
b481de9c
ZY		 1376 iwl4965_kw_free(priv);
1377}
1378
1379/**
8b6eaea8 1380 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
b481de9c 1381 *
8b6eaea8
CB		 1382 * Does NOT advance any TFD circular buffer read/write indexes
1383 * Does NOT free the TFD itself (which is within circular buffer)
b481de9c 1384 */
c79dd5b5 1385int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 1386{
bb8c093b
CH		 1387 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1388 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 1389 struct pci_dev *dev = priv->pci_dev;
1390 int i;
1391 int counter = 0;
1392 int index, is_odd;
1393
8b6eaea8 1394 /* Host command buffers stay mapped in memory, nothing to clean */
b481de9c 1395 if (txq->q.id == IWL_CMD_QUEUE_NUM)
b481de9c
ZY		 1396 return 0;
1397
8b6eaea8 1398 /* Sanity check on number of chunks */
b481de9c
ZY		 1399 counter = IWL_GET_BITS(*bd, num_tbs);
1400 if (counter > MAX_NUM_OF_TBS) {
1401 IWL_ERROR("Too many chunks: %i\n", counter);
1402 /* @todo issue fatal error, it is quite serious situation */
1403 return 0;
1404 }
1405
8b6eaea8
CB		 1406 /* Unmap chunks, if any.
1407 * TFD info for odd chunks is different format than for even chunks. */
b481de9c
ZY		 1408 for (i = 0; i < counter; i++) {
1409 index = i / 2;
1410 is_odd = i & 0x1;
1411
1412 if (is_odd)
1413 pci_unmap_single(
1414 dev,
1415 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1416 (IWL_GET_BITS(bd->pa[index],
1417 tb2_addr_hi20) << 16),
1418 IWL_GET_BITS(bd->pa[index], tb2_len),
1419 PCI_DMA_TODEVICE);
1420
1421 else if (i > 0)
1422 pci_unmap_single(dev,
1423 le32_to_cpu(bd->pa[index].tb1_addr),
1424 IWL_GET_BITS(bd->pa[index], tb1_len),
1425 PCI_DMA_TODEVICE);
1426
8b6eaea8 1427 /* Free SKB, if any, for this chunk */
fc4b6853
TW		 1428 if (txq->txb[txq->q.read_ptr].skb[i]) {
1429 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
b481de9c
ZY		 1430
1431 dev_kfree_skb(skb);
fc4b6853 1432 txq->txb[txq->q.read_ptr].skb[i] = NULL;
b481de9c
ZY		 1433 }
1434 }
1435 return 0;
1436}
1437
5da4b55f
MA		 1438/* set card power command */
1439static int iwl4965_set_power(struct iwl_priv *priv,
1440 void *cmd)
1441{
1442 int ret = 0;
1443
1444 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1445 sizeof(struct iwl4965_powertable_cmd),
1446 cmd, NULL);
1447 return ret;
1448}
c79dd5b5 1449int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1450{
bb8c093b 1451 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
b481de9c
ZY		 1452 return -EINVAL;
1453}
1454
1455static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1456{
1457 s32 sign = 1;
1458
1459 if (num < 0) {
1460 sign = -sign;
1461 num = -num;
1462 }
1463 if (denom < 0) {
1464 sign = -sign;
1465 denom = -denom;
1466 }
1467 *res = 1;
1468 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1469
1470 return 1;
1471}
1472
8b6eaea8
CB		 1473/**
1474 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1475 *
1476 * Determines power supply voltage compensation for txpower calculations.
1477 * Returns number of 1/2-dB steps to subtract from gain table index,
1478 * to compensate for difference between power supply voltage during
1479 * factory measurements, vs. current power supply voltage.
1480 *
1481 * Voltage indication is higher for lower voltage.
1482 * Lower voltage requires more gain (lower gain table index).
1483 */
b481de9c
ZY		 1484static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1485 s32 current_voltage)
1486{
1487 s32 comp = 0;
1488
1489 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1490 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1491 return 0;
1492
1493 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1494 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1495
1496 if (current_voltage > eeprom_voltage)
1497 comp *= 2;
1498 if ((comp < -2) || (comp > 2))
1499 comp = 0;
1500
1501 return comp;
1502}
1503
bf85ea4f 1504static const struct iwl_channel_info *
c79dd5b5 1505iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
8318d78a 1506 enum ieee80211_band band, u16 channel)
b481de9c 1507{
bf85ea4f 1508 const struct iwl_channel_info *ch_info;
b481de9c 1509
8622e705 1510 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 1511
1512 if (!is_channel_valid(ch_info))
1513 return NULL;
1514
1515 return ch_info;
1516}
1517
1518static s32 iwl4965_get_tx_atten_grp(u16 channel)
1519{
1520 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1521 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1522 return CALIB_CH_GROUP_5;
1523
1524 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1525 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1526 return CALIB_CH_GROUP_1;
1527
1528 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1529 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1530 return CALIB_CH_GROUP_2;
1531
1532 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1533 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1534 return CALIB_CH_GROUP_3;
1535
1536 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1537 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1538 return CALIB_CH_GROUP_4;
1539
1540 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1541 return -1;
1542}
1543
c79dd5b5 1544static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 1545{
1546 s32 b = -1;
1547
1548 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 1549 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 1550 continue;
1551
073d3f5f
TW		 1552 if ((channel >= priv->calib_info->band_info[b].ch_from)
1553 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 1554 break;
1555 }
1556
1557 return b;
1558}
1559
1560static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1561{
1562 s32 val;
1563
1564 if (x2 == x1)
1565 return y1;
1566 else {
1567 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1568 return val + y2;
1569 }
1570}
1571
8b6eaea8
CB		 1572/**
1573 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1574 *
1575 * Interpolates factory measurements from the two sample channels within a
1576 * sub-band, to apply to channel of interest. Interpolation is proportional to
1577 * differences in channel frequencies, which is proportional to differences
1578 * in channel number.
1579 */
c79dd5b5 1580static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 1581 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 1582{
1583 s32 s = -1;
1584 u32 c;
1585 u32 m;
073d3f5f
TW		 1586 const struct iwl_eeprom_calib_measure *m1;
1587 const struct iwl_eeprom_calib_measure *m2;
1588 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 1589 u32 ch_i1;
1590 u32 ch_i2;
1591
1592 s = iwl4965_get_sub_band(priv, channel);
1593 if (s >= EEPROM_TX_POWER_BANDS) {
1594 IWL_ERROR("Tx Power can not find channel %d ", channel);
1595 return -1;
1596 }
1597
073d3f5f
TW		 1598 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1599 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 1600 chan_info->ch_num = (u8) channel;
1601
1602 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1603 channel, s, ch_i1, ch_i2);
1604
1605 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1606 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 1607 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 1608 measurements[c][m]);
073d3f5f 1609 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 1610 measurements[c][m]);
1611 omeas = &(chan_info->measurements[c][m]);
1612
1613 omeas->actual_pow =
1614 (u8) iwl4965_interpolate_value(channel, ch_i1,
1615 m1->actual_pow,
1616 ch_i2,
1617 m2->actual_pow);
1618 omeas->gain_idx =
1619 (u8) iwl4965_interpolate_value(channel, ch_i1,
1620 m1->gain_idx, ch_i2,
1621 m2->gain_idx);
1622 omeas->temperature =
1623 (u8) iwl4965_interpolate_value(channel, ch_i1,
1624 m1->temperature,
1625 ch_i2,
1626 m2->temperature);
1627 omeas->pa_det =
1628 (s8) iwl4965_interpolate_value(channel, ch_i1,
1629 m1->pa_det, ch_i2,
1630 m2->pa_det);
1631
1632 IWL_DEBUG_TXPOWER
1633 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1634 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1635 IWL_DEBUG_TXPOWER
1636 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1637 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1638 IWL_DEBUG_TXPOWER
1639 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1640 m1->pa_det, m2->pa_det, omeas->pa_det);
1641 IWL_DEBUG_TXPOWER
1642 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1643 m1->temperature, m2->temperature,
1644 omeas->temperature);
1645 }
1646 }
1647
1648 return 0;
1649}
1650
1651/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1652 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1653static s32 back_off_table[] = {
1654 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1655 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1656 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1657 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1658 10 /* CCK */
1659};
1660
1661/* Thermal compensation values for txpower for various frequency ranges ...
1662 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1663static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1664 s32 degrees_per_05db_a;
1665 s32 degrees_per_05db_a_denom;
1666} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1667 {9, 2}, /* group 0 5.2, ch 34-43 */
1668 {4, 1}, /* group 1 5.2, ch 44-70 */
1669 {4, 1}, /* group 2 5.2, ch 71-124 */
1670 {4, 1}, /* group 3 5.2, ch 125-200 */
1671 {3, 1} /* group 4 2.4, ch all */
1672};
1673
1674static s32 get_min_power_index(s32 rate_power_index, u32 band)
1675{
1676 if (!band) {
1677 if ((rate_power_index & 7) <= 4)
1678 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1679 }
1680 return MIN_TX_GAIN_INDEX;
1681}
1682
1683struct gain_entry {
1684 u8 dsp;
1685 u8 radio;
1686};
1687
1688static const struct gain_entry gain_table[2][108] = {
1689 /* 5.2GHz power gain index table */
1690 {
1691 {123, 0x3F}, /* highest txpower */
1692 {117, 0x3F},
1693 {110, 0x3F},
1694 {104, 0x3F},
1695 {98, 0x3F},
1696 {110, 0x3E},
1697 {104, 0x3E},
1698 {98, 0x3E},
1699 {110, 0x3D},
1700 {104, 0x3D},
1701 {98, 0x3D},
1702 {110, 0x3C},
1703 {104, 0x3C},
1704 {98, 0x3C},
1705 {110, 0x3B},
1706 {104, 0x3B},
1707 {98, 0x3B},
1708 {110, 0x3A},
1709 {104, 0x3A},
1710 {98, 0x3A},
1711 {110, 0x39},
1712 {104, 0x39},
1713 {98, 0x39},
1714 {110, 0x38},
1715 {104, 0x38},
1716 {98, 0x38},
1717 {110, 0x37},
1718 {104, 0x37},
1719 {98, 0x37},
1720 {110, 0x36},
1721 {104, 0x36},
1722 {98, 0x36},
1723 {110, 0x35},
1724 {104, 0x35},
1725 {98, 0x35},
1726 {110, 0x34},
1727 {104, 0x34},
1728 {98, 0x34},
1729 {110, 0x33},
1730 {104, 0x33},
1731 {98, 0x33},
1732 {110, 0x32},
1733 {104, 0x32},
1734 {98, 0x32},
1735 {110, 0x31},
1736 {104, 0x31},
1737 {98, 0x31},
1738 {110, 0x30},
1739 {104, 0x30},
1740 {98, 0x30},
1741 {110, 0x25},
1742 {104, 0x25},
1743 {98, 0x25},
1744 {110, 0x24},
1745 {104, 0x24},
1746 {98, 0x24},
1747 {110, 0x23},
1748 {104, 0x23},
1749 {98, 0x23},
1750 {110, 0x22},
1751 {104, 0x18},
1752 {98, 0x18},
1753 {110, 0x17},
1754 {104, 0x17},
1755 {98, 0x17},
1756 {110, 0x16},
1757 {104, 0x16},
1758 {98, 0x16},
1759 {110, 0x15},
1760 {104, 0x15},
1761 {98, 0x15},
1762 {110, 0x14},
1763 {104, 0x14},
1764 {98, 0x14},
1765 {110, 0x13},
1766 {104, 0x13},
1767 {98, 0x13},
1768 {110, 0x12},
1769 {104, 0x08},
1770 {98, 0x08},
1771 {110, 0x07},
1772 {104, 0x07},
1773 {98, 0x07},
1774 {110, 0x06},
1775 {104, 0x06},
1776 {98, 0x06},
1777 {110, 0x05},
1778 {104, 0x05},
1779 {98, 0x05},
1780 {110, 0x04},
1781 {104, 0x04},
1782 {98, 0x04},
1783 {110, 0x03},
1784 {104, 0x03},
1785 {98, 0x03},
1786 {110, 0x02},
1787 {104, 0x02},
1788 {98, 0x02},
1789 {110, 0x01},
1790 {104, 0x01},
1791 {98, 0x01},
1792 {110, 0x00},
1793 {104, 0x00},
1794 {98, 0x00},
1795 {93, 0x00},
1796 {88, 0x00},
1797 {83, 0x00},
1798 {78, 0x00},
1799 },
1800 /* 2.4GHz power gain index table */
1801 {
1802 {110, 0x3f}, /* highest txpower */
1803 {104, 0x3f},
1804 {98, 0x3f},
1805 {110, 0x3e},
1806 {104, 0x3e},
1807 {98, 0x3e},
1808 {110, 0x3d},
1809 {104, 0x3d},
1810 {98, 0x3d},
1811 {110, 0x3c},
1812 {104, 0x3c},
1813 {98, 0x3c},
1814 {110, 0x3b},
1815 {104, 0x3b},
1816 {98, 0x3b},
1817 {110, 0x3a},
1818 {104, 0x3a},
1819 {98, 0x3a},
1820 {110, 0x39},
1821 {104, 0x39},
1822 {98, 0x39},
1823 {110, 0x38},
1824 {104, 0x38},
1825 {98, 0x38},
1826 {110, 0x37},
1827 {104, 0x37},
1828 {98, 0x37},
1829 {110, 0x36},
1830 {104, 0x36},
1831 {98, 0x36},
1832 {110, 0x35},
1833 {104, 0x35},
1834 {98, 0x35},
1835 {110, 0x34},
1836 {104, 0x34},
1837 {98, 0x34},
1838 {110, 0x33},
1839 {104, 0x33},
1840 {98, 0x33},
1841 {110, 0x32},
1842 {104, 0x32},
1843 {98, 0x32},
1844 {110, 0x31},
1845 {104, 0x31},
1846 {98, 0x31},
1847 {110, 0x30},
1848 {104, 0x30},
1849 {98, 0x30},
1850 {110, 0x6},
1851 {104, 0x6},
1852 {98, 0x6},
1853 {110, 0x5},
1854 {104, 0x5},
1855 {98, 0x5},
1856 {110, 0x4},
1857 {104, 0x4},
1858 {98, 0x4},
1859 {110, 0x3},
1860 {104, 0x3},
1861 {98, 0x3},
1862 {110, 0x2},
1863 {104, 0x2},
1864 {98, 0x2},
1865 {110, 0x1},
1866 {104, 0x1},
1867 {98, 0x1},
1868 {110, 0x0},
1869 {104, 0x0},
1870 {98, 0x0},
1871 {97, 0},
1872 {96, 0},
1873 {95, 0},
1874 {94, 0},
1875 {93, 0},
1876 {92, 0},
1877 {91, 0},
1878 {90, 0},
1879 {89, 0},
1880 {88, 0},
1881 {87, 0},
1882 {86, 0},
1883 {85, 0},
1884 {84, 0},
1885 {83, 0},
1886 {82, 0},
1887 {81, 0},
1888 {80, 0},
1889 {79, 0},
1890 {78, 0},
1891 {77, 0},
1892 {76, 0},
1893 {75, 0},
1894 {74, 0},
1895 {73, 0},
1896 {72, 0},
1897 {71, 0},
1898 {70, 0},
1899 {69, 0},
1900 {68, 0},
1901 {67, 0},
1902 {66, 0},
1903 {65, 0},
1904 {64, 0},
1905 {63, 0},
1906 {62, 0},
1907 {61, 0},
1908 {60, 0},
1909 {59, 0},
1910 }
1911};
1912
c79dd5b5 1913static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1914 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1915 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1916{
1917 u8 saturation_power;
1918 s32 target_power;
1919 s32 user_target_power;
1920 s32 power_limit;
1921 s32 current_temp;
1922 s32 reg_limit;
1923 s32 current_regulatory;
1924 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1925 int i;
1926 int c;
bf85ea4f 1927 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1928 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1929 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1930 s16 voltage;
1931 s32 init_voltage;
1932 s32 voltage_compensation;
1933 s32 degrees_per_05db_num;
1934 s32 degrees_per_05db_denom;
1935 s32 factory_temp;
1936 s32 temperature_comp[2];
1937 s32 factory_gain_index[2];
1938 s32 factory_actual_pwr[2];
1939 s32 power_index;
1940
1941 /* Sanity check requested level (dBm) */
1942 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1943 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1944 priv->user_txpower_limit);
1945 return -EINVAL;
1946 }
1947 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1948 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1949 priv->user_txpower_limit);
1950 return -EINVAL;
1951 }
1952
1953 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1954 * are used for indexing into txpower table) */
1955 user_target_power = 2 * priv->user_txpower_limit;
1956
1957 /* Get current (RXON) channel, band, width */
1958 ch_info =
8318d78a 1959 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
b481de9c
ZY		 1960
1961 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1962 is_fat);
1963
1964 if (!ch_info)
1965 return -EINVAL;
1966
1967 /* get txatten group, used to select 1) thermal txpower adjustment
1968 * and 2) mimo txpower balance between Tx chains. */
1969 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1970 if (txatten_grp < 0)
1971 return -EINVAL;
1972
1973 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1974 channel, txatten_grp);
1975
1976 if (is_fat) {
1977 if (ctrl_chan_high)
1978 channel -= 2;
1979 else
1980 channel += 2;
1981 }
1982
1983 /* hardware txpower limits ...
1984 * saturation (clipping distortion) txpowers are in half-dBm */
1985 if (band)
073d3f5f 1986 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1987 else
073d3f5f 1988 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1989
1990 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1991 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1992 if (band)
1993 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1994 else
1995 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1996 }
1997
1998 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1999 * max_power_avg values are in dBm, convert * 2 */
2000 if (is_fat)
2001 reg_limit = ch_info->fat_max_power_avg * 2;
2002 else
2003 reg_limit = ch_info->max_power_avg * 2;
2004
2005 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2006 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2007 if (band)
2008 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2009 else
2010 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2011 }
2012
2013 /* Interpolate txpower calibration values for this channel,
2014 * based on factory calibration tests on spaced channels. */
2015 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2016
2017 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 2018 voltage = priv->calib_info->voltage;
b481de9c
ZY		 2019 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2020 voltage_compensation =
2021 iwl4965_get_voltage_compensation(voltage, init_voltage);
2022
2023 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2024 init_voltage,
2025 voltage, voltage_compensation);
2026
2027 /* get current temperature (Celsius) */
2028 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2029 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2030 current_temp = KELVIN_TO_CELSIUS(current_temp);
2031
2032 /* select thermal txpower adjustment params, based on channel group
2033 * (same frequency group used for mimo txatten adjustment) */
2034 degrees_per_05db_num =
2035 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2036 degrees_per_05db_denom =
2037 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2038
2039 /* get per-chain txpower values from factory measurements */
2040 for (c = 0; c < 2; c++) {
2041 measurement = &ch_eeprom_info.measurements[c][1];
2042
2043 /* txgain adjustment (in half-dB steps) based on difference
2044 * between factory and current temperature */
2045 factory_temp = measurement->temperature;
2046 iwl4965_math_div_round((current_temp - factory_temp) *
2047 degrees_per_05db_denom,
2048 degrees_per_05db_num,
2049 &temperature_comp[c]);
2050
2051 factory_gain_index[c] = measurement->gain_idx;
2052 factory_actual_pwr[c] = measurement->actual_pow;
2053
2054 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2055 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2056 "curr tmp %d, comp %d steps\n",
2057 factory_temp, current_temp,
2058 temperature_comp[c]);
2059
2060 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2061 factory_gain_index[c],
2062 factory_actual_pwr[c]);
2063 }
2064
2065 /* for each of 33 bit-rates (including 1 for CCK) */
2066 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2067 u8 is_mimo_rate;
bb8c093b 2068 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 2069
2070 /* for mimo, reduce each chain's txpower by half
2071 * (3dB, 6 steps), so total output power is regulatory
2072 * compliant. */
2073 if (i & 0x8) {
2074 current_regulatory = reg_limit -
2075 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2076 is_mimo_rate = 1;
2077 } else {
2078 current_regulatory = reg_limit;
2079 is_mimo_rate = 0;
2080 }
2081
2082 /* find txpower limit, either hardware or regulatory */
2083 power_limit = saturation_power - back_off_table[i];
2084 if (power_limit > current_regulatory)
2085 power_limit = current_regulatory;
2086
2087 /* reduce user's txpower request if necessary
2088 * for this rate on this channel */
2089 target_power = user_target_power;
2090 if (target_power > power_limit)
2091 target_power = power_limit;
2092
2093 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2094 i, saturation_power - back_off_table[i],
2095 current_regulatory, user_target_power,
2096 target_power);
2097
2098 /* for each of 2 Tx chains (radio transmitters) */
2099 for (c = 0; c < 2; c++) {
2100 s32 atten_value;
2101
2102 if (is_mimo_rate)
2103 atten_value =
2104 (s32)le32_to_cpu(priv->card_alive_init.
2105 tx_atten[txatten_grp][c]);
2106 else
2107 atten_value = 0;
2108
2109 /* calculate index; higher index means lower txpower */
2110 power_index = (u8) (factory_gain_index[c] -
2111 (target_power -
2112 factory_actual_pwr[c]) -
2113 temperature_comp[c] -
2114 voltage_compensation +
2115 atten_value);
2116
2117/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2118 power_index); */
2119
2120 if (power_index < get_min_power_index(i, band))
2121 power_index = get_min_power_index(i, band);
2122
2123 /* adjust 5 GHz index to support negative indexes */
2124 if (!band)
2125 power_index += 9;
2126
2127 /* CCK, rate 32, reduce txpower for CCK */
2128 if (i == POWER_TABLE_CCK_ENTRY)
2129 power_index +=
2130 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2131
2132 /* stay within the table! */
2133 if (power_index > 107) {
2134 IWL_WARNING("txpower index %d > 107\n",
2135 power_index);
2136 power_index = 107;
2137 }
2138 if (power_index < 0) {
2139 IWL_WARNING("txpower index %d < 0\n",
2140 power_index);
2141 power_index = 0;
2142 }
2143
2144 /* fill txpower command for this rate/chain */
2145 tx_power.s.radio_tx_gain[c] =
2146 gain_table[band][power_index].radio;
2147 tx_power.s.dsp_predis_atten[c] =
2148 gain_table[band][power_index].dsp;
2149
2150 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2151 "gain 0x%02x dsp %d\n",
2152 c, atten_value, power_index,
2153 tx_power.s.radio_tx_gain[c],
2154 tx_power.s.dsp_predis_atten[c]);
2155 }/* for each chain */
2156
2157 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2158
2159 }/* for each rate */
2160
2161 return 0;
2162}
2163
2164/**
bb8c093b 2165 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
b481de9c
ZY		 2166 *
2167 * Uses the active RXON for channel, band, and characteristics (fat, high)
2168 * The power limit is taken from priv->user_txpower_limit.
2169 */
c79dd5b5 2170int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 2171{
bb8c093b 2172 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 2173 int ret;
b481de9c
ZY		 2174 u8 band = 0;
2175 u8 is_fat = 0;
2176 u8 ctrl_chan_high = 0;
2177
2178 if (test_bit(STATUS_SCANNING, &priv->status)) {
2179 /* If this gets hit a lot, switch it to a BUG() and catch
2180 * the stack trace to find out who is calling this during
2181 * a scan. */
2182 IWL_WARNING("TX Power requested while scanning!\n");
2183 return -EAGAIN;
2184 }
2185
8318d78a 2186 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 2187
2188 is_fat = is_fat_channel(priv->active_rxon.flags);
2189
2190 if (is_fat &&
2191 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2192 ctrl_chan_high = 1;
2193
2194 cmd.band = band;
2195 cmd.channel = priv->active_rxon.channel;
2196
857485c0 2197 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 2198 le16_to_cpu(priv->active_rxon.channel),
2199 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 2200 if (ret)
2201 goto out;
b481de9c 2202
857485c0
TW		 2203 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2204
2205out:
2206 return ret;
b481de9c
ZY		 2207}
2208
7e8c519e
TW		 2209static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2210{
2211 int ret = 0;
2212 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2213 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2214 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2215
2216 if ((rxon1->flags == rxon2->flags) &&
2217 (rxon1->filter_flags == rxon2->filter_flags) &&
2218 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2219 (rxon1->ofdm_ht_single_stream_basic_rates ==
2220 rxon2->ofdm_ht_single_stream_basic_rates) &&
2221 (rxon1->ofdm_ht_dual_stream_basic_rates ==
2222 rxon2->ofdm_ht_dual_stream_basic_rates) &&
2223 (rxon1->rx_chain == rxon2->rx_chain) &&
2224 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2225 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
2226 return 0;
2227 }
2228
2229 rxon_assoc.flags = priv->staging_rxon.flags;
2230 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2231 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2232 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2233 rxon_assoc.reserved = 0;
2234 rxon_assoc.ofdm_ht_single_stream_basic_rates =
2235 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2236 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2237 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2238 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2239
2240 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2241 sizeof(rxon_assoc), &rxon_assoc, NULL);
2242 if (ret)
2243 return ret;
2244
2245 return ret;
2246}
2247
2248
c79dd5b5 2249int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2250{
2251 int rc;
2252 u8 band = 0;
2253 u8 is_fat = 0;
2254 u8 ctrl_chan_high = 0;
bb8c093b 2255 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 2256 const struct iwl_channel_info *ch_info;
b481de9c 2257
8318d78a 2258 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 2259
8622e705 2260 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 2261
2262 is_fat = is_fat_channel(priv->staging_rxon.flags);
2263
2264 if (is_fat &&
2265 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2266 ctrl_chan_high = 1;
2267
2268 cmd.band = band;
2269 cmd.expect_beacon = 0;
2270 cmd.channel = cpu_to_le16(channel);
2271 cmd.rxon_flags = priv->active_rxon.flags;
2272 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2273 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2274 if (ch_info)
2275 cmd.expect_beacon = is_channel_radar(ch_info);
2276 else
2277 cmd.expect_beacon = 1;
2278
2279 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2280 ctrl_chan_high, &cmd.tx_power);
2281 if (rc) {
2282 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2283 return rc;
2284 }
2285
857485c0 2286 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 2287 return rc;
2288}
2289
2290#define RTS_HCCA_RETRY_LIMIT 3
2291#define RTS_DFAULT_RETRY_LIMIT 60
2292
c79dd5b5 2293void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
857485c0 2294 struct iwl_cmd *cmd,
b481de9c
ZY		 2295 struct ieee80211_tx_control *ctrl,
2296 struct ieee80211_hdr *hdr, int sta_id,
2297 int is_hcca)
2298{
87e4f7df 2299 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
b481de9c
ZY		 2300 u8 rts_retry_limit = 0;
2301 u8 data_retry_limit = 0;
b481de9c 2302 u16 fc = le16_to_cpu(hdr->frame_control);
87e4f7df
TW		 2303 u8 rate_plcp;
2304 u16 rate_flags = 0;
8318d78a 2305 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c 2306
87e4f7df 2307 rate_plcp = iwl4965_rates[rate_idx].plcp;
b481de9c
ZY		 2308
2309 rts_retry_limit = (is_hcca) ?
2310 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2311
87e4f7df
TW		 2312 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2313 rate_flags |= RATE_MCS_CCK_MSK;
2314
2315
b481de9c
ZY		 2316 if (ieee80211_is_probe_response(fc)) {
2317 data_retry_limit = 3;
2318 if (data_retry_limit < rts_retry_limit)
2319 rts_retry_limit = data_retry_limit;
2320 } else
2321 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2322
2323 if (priv->data_retry_limit != -1)
2324 data_retry_limit = priv->data_retry_limit;
2325
87e4f7df
TW		 2326
2327 if (ieee80211_is_data(fc)) {
2328 tx->initial_rate_index = 0;
2329 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2330 } else {
b481de9c
ZY		 2331 switch (fc & IEEE80211_FCTL_STYPE) {
2332 case IEEE80211_STYPE_AUTH:
2333 case IEEE80211_STYPE_DEAUTH:
2334 case IEEE80211_STYPE_ASSOC_REQ:
2335 case IEEE80211_STYPE_REASSOC_REQ:
87e4f7df
TW		 2336 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2337 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2338 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
b481de9c
ZY		 2339 }
2340 break;
2341 default:
2342 break;
2343 }
87e4f7df
TW		 2344
2345 /* Alternate between antenna A and B for successive frames */
2346 if (priv->use_ant_b_for_management_frame) {
2347 priv->use_ant_b_for_management_frame = 0;
2348 rate_flags |= RATE_MCS_ANT_B_MSK;
2349 } else {
2350 priv->use_ant_b_for_management_frame = 1;
2351 rate_flags |= RATE_MCS_ANT_A_MSK;
2352 }
b481de9c
ZY		 2353 }
2354
87e4f7df
TW		 2355 tx->rts_retry_limit = rts_retry_limit;
2356 tx->data_retry_limit = data_retry_limit;
2357 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
b481de9c
ZY		 2358}
2359
c79dd5b5 2360int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2361{
059ff826
TW		 2362 struct iwl4965_shared *s = priv->shared_virt;
2363 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 2364}
2365
c79dd5b5 2366int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 2367{
2368 return priv->temperature;
2369}
2370
c79dd5b5 2371unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2372 struct iwl4965_frame *frame, u8 rate)
b481de9c 2373{
bb8c093b 2374 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2375 unsigned int frame_size;
2376
2377 tx_beacon_cmd = &frame->u.beacon;
2378 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2379
5425e490 2380 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2381 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2382
bb8c093b 2383 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 2384 tx_beacon_cmd->frame,
bb8c093b 2385 iwl4965_broadcast_addr,
b481de9c
ZY		 2386 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2387
2388 BUG_ON(frame_size > MAX_MPDU_SIZE);
2389 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2390
2391 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2392 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2393 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 2394 else
2395 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2396 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 2397
2398 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2399 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2400 return (sizeof(*tx_beacon_cmd) + frame_size);
2401}
2402
8b6eaea8
CB		 2403/*
2404 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2405 * given Tx queue, and enable the DMA channel used for that queue.
2406 *
2407 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2408 * channels supported in hardware.
2409 */
c79dd5b5 2410int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c
ZY		 2411{
2412 int rc;
2413 unsigned long flags;
2414 int txq_id = txq->q.id;
2415
2416 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 2417 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2418 if (rc) {
2419 spin_unlock_irqrestore(&priv->lock, flags);
2420 return rc;
2421 }
2422
8b6eaea8 2423 /* Circular buffer (TFD queue in DRAM) physical base address */
3395f6e9 2424 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
b481de9c 2425 txq->q.dma_addr >> 8);
8b6eaea8
CB		 2426
2427 /* Enable DMA channel, using same id as for TFD queue */
3395f6e9 2428 iwl_write_direct32(
b481de9c
ZY		 2429 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2430 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2431 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
3395f6e9 2432 iwl_release_nic_access(priv);
b481de9c
ZY		 2433 spin_unlock_irqrestore(&priv->lock, flags);
2434
2435 return 0;
2436}
2437
c79dd5b5 2438int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 2439 dma_addr_t addr, u16 len)
2440{
2441 int index, is_odd;
bb8c093b 2442 struct iwl4965_tfd_frame *tfd = ptr;
b481de9c
ZY		 2443 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2444
8b6eaea8 2445 /* Each TFD can point to a maximum 20 Tx buffers */
b481de9c
ZY		 2446 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2447 IWL_ERROR("Error can not send more than %d chunks\n",
2448 MAX_NUM_OF_TBS);
2449 return -EINVAL;
2450 }
2451
2452 index = num_tbs / 2;
2453 is_odd = num_tbs & 0x1;
2454
2455 if (!is_odd) {
2456 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2457 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
6a218f6f 2458 iwl_get_dma_hi_address(addr));
b481de9c
ZY		 2459 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2460 } else {
2461 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2462 (u32) (addr & 0xffff));
2463 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2464 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2465 }
2466
2467 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2468
2469 return 0;
2470}
2471
c79dd5b5 2472static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
b481de9c 2473{
073d3f5f 2474 u16 hw_version = iwl_eeprom_query16(priv, EEPROM_4965_BOARD_REVISION);
b481de9c
ZY		 2475
2476 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2477 ((hw_version >> 8) & 0x0F),
2478 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2479
2480 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
073d3f5f 2481 &priv->eeprom[EEPROM_4965_BOARD_PBA]);
b481de9c
ZY		 2482}
2483
2484#define IWL_TX_CRC_SIZE 4
2485#define IWL_TX_DELIMITER_SIZE 4
2486
8b6eaea8 2487/**
e2a722eb 2488 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 2489 */
e2a722eb
TW		 2490static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2491 struct iwl4965_tx_queue *txq,
2492 u16 byte_cnt)
b481de9c
ZY		 2493{
2494 int len;
2495 int txq_id = txq->q.id;
059ff826 2496 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 2497
b481de9c
ZY		 2498 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2499
8b6eaea8 2500 /* Set up byte count within first 256 entries */
b481de9c 2501 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 2502 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 2503
8b6eaea8 2504 /* If within first 64 entries, duplicate at end */
fc4b6853 2505 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
b481de9c 2506 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 2507 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 2508 byte_cnt, len);
b481de9c
ZY		 2509}
2510
8b6eaea8
CB		 2511/**
2512 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2513 *
2514 * Selects how many and which Rx receivers/antennas/chains to use.
2515 * This should not be used for scan command ... it puts data in wrong place.
2516 */
c79dd5b5 2517void iwl4965_set_rxon_chain(struct iwl_priv *priv)
b481de9c 2518{
fde0db31 2519 u8 is_single = is_single_rx_stream(priv);
b481de9c
ZY		 2520 u8 idle_state, rx_state;
2521
2522 priv->staging_rxon.rx_chain = 0;
2523 rx_state = idle_state = 3;
2524
2525 /* Tell uCode which antennas are actually connected.
2526 * Before first association, we assume all antennas are connected.
f0832f13 2527 * Just after first association, iwl_chain_noise_calibration()
b481de9c
ZY		 2528 * checks which antennas actually *are* connected. */
2529 priv->staging_rxon.rx_chain |=
fde0db31
GC		 2530 cpu_to_le16(priv->hw_params.valid_rx_ant <<
2531 RXON_RX_CHAIN_VALID_POS);
b481de9c
ZY		 2532
2533 /* How many receivers should we use? */
2534 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2535 priv->staging_rxon.rx_chain |=
2536 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2537 priv->staging_rxon.rx_chain |=
2538 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2539
2540 if (!is_single && (rx_state >= 2) &&
2541 !test_bit(STATUS_POWER_PMI, &priv->status))
2542 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2543 else
2544 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2545
2546 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2547}
2548
b481de9c
ZY		 2549/**
2550 * sign_extend - Sign extend a value using specified bit as sign-bit
2551 *
2552 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2553 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2554 *
2555 * @param oper value to sign extend
2556 * @param index 0 based bit index (0<=index<32) to sign bit
2557 */
2558static s32 sign_extend(u32 oper, int index)
2559{
2560 u8 shift = 31 - index;
2561
2562 return (s32)(oper << shift) >> shift;
2563}
2564
2565/**
2566 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2567 * @statistics: Provides the temperature reading from the uCode
2568 *
2569 * A return of <0 indicates bogus data in the statistics
2570 */
c79dd5b5 2571int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 2572{
2573 s32 temperature;
2574 s32 vt;
2575 s32 R1, R2, R3;
2576 u32 R4;
2577
2578 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2579 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2580 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2581 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2582 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2583 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2584 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2585 } else {
2586 IWL_DEBUG_TEMP("Running temperature calibration\n");
2587 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2588 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2589 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2590 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2591 }
2592
2593 /*
8b6eaea8 2594 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 2595 *
2596 * NOTE If we haven't received a statistics notification yet
2597 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 2598 * "initialize" ALIVE response.
2599 */
b481de9c
ZY		 2600 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2601 vt = sign_extend(R4, 23);
2602 else
2603 vt = sign_extend(
2604 le32_to_cpu(priv->statistics.general.temperature), 23);
2605
2606 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2607 R1, R2, R3, vt);
2608
2609 if (R3 == R1) {
2610 IWL_ERROR("Calibration conflict R1 == R3\n");
2611 return -1;
2612 }
2613
2614 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2615 * Add offset to center the adjustment around 0 degrees Centigrade. */
2616 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2617 temperature /= (R3 - R1);
2618 temperature = (temperature * 97) / 100 +
2619 TEMPERATURE_CALIB_KELVIN_OFFSET;
2620
2621 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2622 KELVIN_TO_CELSIUS(temperature));
2623
2624 return temperature;
2625}
2626
2627/* Adjust Txpower only if temperature variance is greater than threshold. */
2628#define IWL_TEMPERATURE_THRESHOLD 3
2629
2630/**
2631 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2632 *
2633 * If the temperature changed has changed sufficiently, then a recalibration
2634 * is needed.
2635 *
2636 * Assumes caller will replace priv->last_temperature once calibration
2637 * executed.
2638 */
c79dd5b5 2639static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 2640{
2641 int temp_diff;
2642
2643 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2644 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2645 return 0;
2646 }
2647
2648 temp_diff = priv->temperature - priv->last_temperature;
2649
2650 /* get absolute value */
2651 if (temp_diff < 0) {
2652 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2653 temp_diff = -temp_diff;
2654 } else if (temp_diff == 0)
2655 IWL_DEBUG_POWER("Same temp, \n");
2656 else
2657 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2658
2659 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2660 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2661 return 0;
2662 }
2663
2664 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2665
2666 return 1;
2667}
2668
2669/* Calculate noise level, based on measurements during network silence just
2670 * before arriving beacon. This measurement can be done only if we know
2671 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 2672static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 2673{
2674 struct statistics_rx_non_phy *rx_info
2675 = &(priv->statistics.rx.general);
2676 int num_active_rx = 0;
2677 int total_silence = 0;
2678 int bcn_silence_a =
2679 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2680 int bcn_silence_b =
2681 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2682 int bcn_silence_c =
2683 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2684
2685 if (bcn_silence_a) {
2686 total_silence += bcn_silence_a;
2687 num_active_rx++;
2688 }
2689 if (bcn_silence_b) {
2690 total_silence += bcn_silence_b;
2691 num_active_rx++;
2692 }
2693 if (bcn_silence_c) {
2694 total_silence += bcn_silence_c;
2695 num_active_rx++;
2696 }
2697
2698 /* Average among active antennas */
2699 if (num_active_rx)
2700 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2701 else
2702 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2703
2704 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2705 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2706 priv->last_rx_noise);
2707}
2708
c79dd5b5 2709void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 2710{
bb8c093b 2711 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2712 int change;
2713 s32 temp;
2714
2715 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2716 (int)sizeof(priv->statistics), pkt->len);
2717
2718 change = ((priv->statistics.general.temperature !=
2719 pkt->u.stats.general.temperature) ||
2720 ((priv->statistics.flag &
2721 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2722 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2723
2724 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2725
2726 set_bit(STATUS_STATISTICS, &priv->status);
2727
2728 /* Reschedule the statistics timer to occur in
2729 * REG_RECALIB_PERIOD seconds to ensure we get a
2730 * thermal update even if the uCode doesn't give
2731 * us one */
2732 mod_timer(&priv->statistics_periodic, jiffies +
2733 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2734
2735 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2736 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2737 iwl4965_rx_calc_noise(priv);
f0832f13 2738#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 2739 queue_work(priv->workqueue, &priv->sensitivity_work);
2740#endif
2741 }
2742
ab53d8af
MA		 2743 iwl_leds_background(priv);
2744
b481de9c
ZY		 2745 /* If the hardware hasn't reported a change in
2746 * temperature then don't bother computing a
2747 * calibrated temperature value */
2748 if (!change)
2749 return;
2750
2751 temp = iwl4965_get_temperature(priv);
2752 if (temp < 0)
2753 return;
2754
2755 if (priv->temperature != temp) {
2756 if (priv->temperature)
2757 IWL_DEBUG_TEMP("Temperature changed "
2758 "from %dC to %dC\n",
2759 KELVIN_TO_CELSIUS(priv->temperature),
2760 KELVIN_TO_CELSIUS(temp));
2761 else
2762 IWL_DEBUG_TEMP("Temperature "
2763 "initialized to %dC\n",
2764 KELVIN_TO_CELSIUS(temp));
2765 }
2766
2767 priv->temperature = temp;
2768 set_bit(STATUS_TEMPERATURE, &priv->status);
2769
2770 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2771 iwl4965_is_temp_calib_needed(priv))
2772 queue_work(priv->workqueue, &priv->txpower_work);
2773}
2774
c79dd5b5 2775static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 2776 struct sk_buff *skb,
2777 struct iwl4965_rx_phy_res *rx_start,
2778 struct ieee80211_rx_status *stats,
2779 u32 ampdu_status)
2780{
2781 s8 signal = stats->ssi;
2782 s8 noise = 0;
8318d78a 2783 int rate = stats->rate_idx;
12342c47 2784 u64 tsf = stats->mactime;
a0b484fe 2785 __le16 antenna;
12342c47
ZY		 2786 __le16 phy_flags_hw = rx_start->phy_flags;
2787 struct iwl4965_rt_rx_hdr {
2788 struct ieee80211_radiotap_header rt_hdr;
2789 __le64 rt_tsf; /* TSF */
2790 u8 rt_flags; /* radiotap packet flags */
2791 u8 rt_rate; /* rate in 500kb/s */
2792 __le16 rt_channelMHz; /* channel in MHz */
2793 __le16 rt_chbitmask; /* channel bitfield */
2794 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2795 s8 rt_dbmnoise;
2796 u8 rt_antenna; /* antenna number */
2797 } __attribute__ ((packed)) *iwl4965_rt;
2798
2799 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2800 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2801 if (net_ratelimit())
2802 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 2803 "radiotap head [%zd]\n",
12342c47
ZY		 2804 skb_headroom(skb), sizeof(*iwl4965_rt));
2805 return;
2806 }
2807
2808 /* put radiotap header in front of 802.11 header and data */
2809 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2810
2811 /* initialise radiotap header */
2812 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2813 iwl4965_rt->rt_hdr.it_pad = 0;
2814
2815 /* total header + data */
2816 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2817 &iwl4965_rt->rt_hdr.it_len);
2818
2819 /* Indicate all the fields we add to the radiotap header */
2820 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2821 (1 << IEEE80211_RADIOTAP_FLAGS) |
2822 (1 << IEEE80211_RADIOTAP_RATE) |
2823 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2824 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2825 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2826 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2827 &iwl4965_rt->rt_hdr.it_present);
2828
2829 /* Zero the flags, we'll add to them as we go */
2830 iwl4965_rt->rt_flags = 0;
2831
2832 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2833
2834 iwl4965_rt->rt_dbmsignal = signal;
2835 iwl4965_rt->rt_dbmnoise = noise;
2836
2837 /* Convert the channel frequency and set the flags */
2838 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2839 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2840 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2841 IEEE80211_CHAN_5GHZ),
2842 &iwl4965_rt->rt_chbitmask);
2843 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2844 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2845 IEEE80211_CHAN_2GHZ),
2846 &iwl4965_rt->rt_chbitmask);
2847 else /* 802.11g */
2848 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2849 IEEE80211_CHAN_2GHZ),
2850 &iwl4965_rt->rt_chbitmask);
2851
12342c47
ZY		 2852 if (rate == -1)
2853 iwl4965_rt->rt_rate = 0;
2854 else
2855 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2856
2857 /*
2858 * "antenna number"
2859 *
2860 * It seems that the antenna field in the phy flags value
2861 * is actually a bitfield. This is undefined by radiotap,
2862 * it wants an actual antenna number but I always get "7"
2863 * for most legacy frames I receive indicating that the
2864 * same frame was received on all three RX chains.
2865 *
2866 * I think this field should be removed in favour of a
2867 * new 802.11n radiotap field "RX chains" that is defined
2868 * as a bitmask.
2869 */
a0b484fe
JB		 2870 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2871 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 2872
2873 /* set the preamble flag if appropriate */
2874 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2875 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2876
2877 stats->flag |= RX_FLAG_RADIOTAP;
2878}
2879
19758bef
TW		 2880static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2881{
2882 /* 0 - mgmt, 1 - cnt, 2 - data */
2883 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2884 priv->rx_stats[idx].cnt++;
2885 priv->rx_stats[idx].bytes += len;
2886}
2887
3ec47732
EG		 2888/*
2889 * returns non-zero if packet should be dropped
2890 */
2891static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2892 struct ieee80211_hdr *hdr,
2893 u32 decrypt_res,
2894 struct ieee80211_rx_status *stats)
2895{
2896 u16 fc = le16_to_cpu(hdr->frame_control);
2897
2898 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2899 return 0;
2900
2901 if (!(fc & IEEE80211_FCTL_PROTECTED))
2902 return 0;
2903
2904 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2905 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2906 case RX_RES_STATUS_SEC_TYPE_TKIP:
2907 /* The uCode has got a bad phase 1 Key, pushes the packet.
2908 * Decryption will be done in SW. */
2909 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2910 RX_RES_STATUS_BAD_KEY_TTAK)
2911 break;
2912
2913 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2914 RX_RES_STATUS_BAD_ICV_MIC) {
2915 /* bad ICV, the packet is destroyed since the
2916 * decryption is inplace, drop it */
2917 IWL_DEBUG_RX("Packet destroyed\n");
2918 return -1;
2919 }
2920 case RX_RES_STATUS_SEC_TYPE_WEP:
2921 case RX_RES_STATUS_SEC_TYPE_CCMP:
2922 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2923 RX_RES_STATUS_DECRYPT_OK) {
2924 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2925 stats->flag |= RX_FLAG_DECRYPTED;
2926 }
2927 break;
2928
2929 default:
2930 break;
2931 }
2932 return 0;
2933}
2934
17e476b8
EG		 2935static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2936{
2937 u32 decrypt_out = 0;
2938
2939 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2940 RX_RES_STATUS_STATION_FOUND)
2941 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2942 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2943
2944 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2945
2946 /* packet was not encrypted */
2947 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2948 RX_RES_STATUS_SEC_TYPE_NONE)
2949 return decrypt_out;
2950
2951 /* packet was encrypted with unknown alg */
2952 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2953 RX_RES_STATUS_SEC_TYPE_ERR)
2954 return decrypt_out;
2955
2956 /* decryption was not done in HW */
2957 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2958 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2959 return decrypt_out;
2960
2961 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2962
2963 case RX_RES_STATUS_SEC_TYPE_CCMP:
2964 /* alg is CCM: check MIC only */
2965 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2966 /* Bad MIC */
2967 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2968 else
2969 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2970
2971 break;
2972
2973 case RX_RES_STATUS_SEC_TYPE_TKIP:
2974 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2975 /* Bad TTAK */
2976 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2977 break;
2978 }
2979 /* fall through if TTAK OK */
2980 default:
2981 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2982 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2983 else
2984 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2985 break;
2986 };
2987
2988 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2989 decrypt_in, decrypt_out);
2990
2991 return decrypt_out;
2992}
2993
c79dd5b5 2994static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 2995 int include_phy,
bb8c093b 2996 struct iwl4965_rx_mem_buffer *rxb,
b481de9c
ZY		 2997 struct ieee80211_rx_status *stats)
2998{
bb8c093b 2999 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3000 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3001 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3002 struct ieee80211_hdr *hdr;
3003 u16 len;
3004 __le32 *rx_end;
3005 unsigned int skblen;
3006 u32 ampdu_status;
17e476b8 3007 u32 ampdu_status_legacy;
b481de9c
ZY		 3008
3009 if (!include_phy && priv->last_phy_res[0])
3010 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3011
3012 if (!rx_start) {
3013 IWL_ERROR("MPDU frame without a PHY data\n");
3014 return;
3015 }
3016 if (include_phy) {
3017 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3018 rx_start->cfg_phy_cnt);
3019
3020 len = le16_to_cpu(rx_start->byte_count);
3021
3022 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3023 sizeof(struct iwl4965_rx_phy_res) +
3024 rx_start->cfg_phy_cnt + len);
3025
3026 } else {
3027 struct iwl4965_rx_mpdu_res_start *amsdu =
3028 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3029
3030 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3031 sizeof(struct iwl4965_rx_mpdu_res_start));
3032 len = le16_to_cpu(amsdu->byte_count);
3033 rx_start->byte_count = amsdu->byte_count;
3034 rx_end = (__le32 *) (((u8 *) hdr) + len);
3035 }
5425e490 3036 if (len > priv->hw_params.max_pkt_size || len < 16) {
12342c47 3037 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 3038 return;
3039 }
3040
3041 ampdu_status = le32_to_cpu(*rx_end);
3042 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3043
17e476b8
EG		 3044 if (!include_phy) {
3045 /* New status scheme, need to translate */
3046 ampdu_status_legacy = ampdu_status;
3047 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3048 }
3049
b481de9c
ZY		 3050 /* start from MAC */
3051 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3052 skb_put(rxb->skb, len); /* end where data ends */
3053
3054 /* We only process data packets if the interface is open */
3055 if (unlikely(!priv->is_open)) {
3056 IWL_DEBUG_DROP_LIMIT
3057 ("Dropping packet while interface is not open.\n");
3058 return;
3059 }
3060
b481de9c
ZY		 3061 stats->flag = 0;
3062 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3063
3ec47732 3064 /* in case of HW accelerated crypto and bad decryption, drop */
099b40b7 3065 if (!priv->hw_params.sw_crypto &&
3ec47732
EG		 3066 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
3067 return;
b481de9c 3068
12342c47
ZY		 3069 if (priv->add_radiotap)
3070 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3071
19758bef 3072 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 3073 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3074 priv->alloc_rxb_skb--;
3075 rxb->skb = NULL;
b481de9c
ZY		 3076}
3077
3078/* Calc max signal level (dBm) among 3 possible receivers */
3079static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3080{
3081 /* data from PHY/DSP regarding signal strength, etc.,
3082 * contents are always there, not configurable by host. */
3083 struct iwl4965_rx_non_cfg_phy *ncphy =
3084 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3085 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3086 >> IWL_AGC_DB_POS;
3087
3088 u32 valid_antennae =
3089 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3090 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3091 u8 max_rssi = 0;
3092 u32 i;
3093
3094 /* Find max rssi among 3 possible receivers.
3095 * These values are measured by the digital signal processor (DSP).
3096 * They should stay fairly constant even as the signal strength varies,
3097 * if the radio's automatic gain control (AGC) is working right.
3098 * AGC value (see below) will provide the "interesting" info. */
3099 for (i = 0; i < 3; i++)
3100 if (valid_antennae & (1 << i))
3101 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3102
3103 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3104 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3105 max_rssi, agc);
3106
3107 /* dBm = max_rssi dB - agc dB - constant.
3108 * Higher AGC (higher radio gain) means lower signal. */
3109 return (max_rssi - agc - IWL_RSSI_OFFSET);
3110}
3111
c8b0e6e1 3112#ifdef CONFIG_IWL4965_HT
b481de9c 3113
fde0db31 3114void iwl4965_init_ht_hw_capab(const struct iwl_priv *priv,
1ea87396 3115 struct ieee80211_ht_info *ht_info,
78330fdd 3116 enum ieee80211_band band)
326eeee8
RR		 3117{
3118 ht_info->cap = 0;
3119 memset(ht_info->supp_mcs_set, 0, 16);
3120
3121 ht_info->ht_supported = 1;
3122
099b40b7 3123 if (priv->hw_params.fat_channel & BIT(band)) {
326eeee8
RR		 3124 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3125 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3126 ht_info->supp_mcs_set[4] = 0x01;
3127 }
3128 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3129 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3130 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3131 (IWL_MIMO_PS_NONE << 2));
1ea87396
AK		 3132
3133 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47 3134 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
326eeee8
RR		 3135
3136 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3137 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3138
3139 ht_info->supp_mcs_set[0] = 0xFF;
fde0db31
GC		 3140 if (priv->hw_params.tx_chains_num >= 2)
3141 ht_info->supp_mcs_set[1] = 0xFF;
3142 if (priv->hw_params.tx_chains_num >= 3)
3143 ht_info->supp_mcs_set[2] = 0xFF;
326eeee8 3144}
c8b0e6e1 3145#endif /* CONFIG_IWL4965_HT */
b481de9c 3146
c79dd5b5 3147static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 3148{
3149 unsigned long flags;
3150
3151 spin_lock_irqsave(&priv->sta_lock, flags);
3152 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3153 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3154 priv->stations[sta_id].sta.sta.modify_mask = 0;
3155 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3156 spin_unlock_irqrestore(&priv->sta_lock, flags);
3157
bb8c093b 3158 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3159}
3160
c79dd5b5 3161static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 3162{
3163 /* FIXME: need locking over ps_status ??? */
947b13a7 3164 u8 sta_id = iwl_find_station(priv, addr);
b481de9c
ZY		 3165
3166 if (sta_id != IWL_INVALID_STATION) {
3167 u8 sta_awake = priv->stations[sta_id].
3168 ps_status == STA_PS_STATUS_WAKE;
3169
3170 if (sta_awake && ps_bit)
3171 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3172 else if (!sta_awake && !ps_bit) {
3173 iwl4965_sta_modify_ps_wake(priv, sta_id);
3174 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3175 }
3176 }
3177}
0a6857e7 3178#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 3179
3180/**
3181 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3182 *
3183 * You may hack this function to show different aspects of received frames,
3184 * including selective frame dumps.
3185 * group100 parameter selects whether to show 1 out of 100 good frames.
3186 *
3187 * TODO: This was originally written for 3945, need to audit for
3188 * proper operation with 4965.
3189 */
c79dd5b5 3190static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3191 struct iwl4965_rx_packet *pkt,
3192 struct ieee80211_hdr *header, int group100)
3193{
3194 u32 to_us;
3195 u32 print_summary = 0;
3196 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3197 u32 hundred = 0;
3198 u32 dataframe = 0;
3199 u16 fc;
3200 u16 seq_ctl;
3201 u16 channel;
3202 u16 phy_flags;
3203 int rate_sym;
3204 u16 length;
3205 u16 status;
3206 u16 bcn_tmr;
3207 u32 tsf_low;
3208 u64 tsf;
3209 u8 rssi;
3210 u8 agc;
3211 u16 sig_avg;
3212 u16 noise_diff;
3213 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3214 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3215 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3216 u8 *data = IWL_RX_DATA(pkt);
3217
0a6857e7 3218 if (likely(!(iwl_debug_level & IWL_DL_RX)))
17744ff6
TW		 3219 return;
3220
3221 /* MAC header */
3222 fc = le16_to_cpu(header->frame_control);
3223 seq_ctl = le16_to_cpu(header->seq_ctrl);
3224
3225 /* metadata */
3226 channel = le16_to_cpu(rx_hdr->channel);
3227 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3228 rate_sym = rx_hdr->rate;
3229 length = le16_to_cpu(rx_hdr->len);
3230
3231 /* end-of-frame status and timestamp */
3232 status = le32_to_cpu(rx_end->status);
3233 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3234 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3235 tsf = le64_to_cpu(rx_end->timestamp);
3236
3237 /* signal statistics */
3238 rssi = rx_stats->rssi;
3239 agc = rx_stats->agc;
3240 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3241 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3242
3243 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3244
3245 /* if data frame is to us and all is good,
3246 * (optionally) print summary for only 1 out of every 100 */
3247 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3248 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3249 dataframe = 1;
3250 if (!group100)
3251 print_summary = 1; /* print each frame */
3252 else if (priv->framecnt_to_us < 100) {
3253 priv->framecnt_to_us++;
3254 print_summary = 0;
3255 } else {
3256 priv->framecnt_to_us = 0;
3257 print_summary = 1;
3258 hundred = 1;
3259 }
3260 } else {
3261 /* print summary for all other frames */
3262 print_summary = 1;
3263 }
3264
3265 if (print_summary) {
3266 char *title;
3267 int rate_idx;
3268 u32 bitrate;
3269
3270 if (hundred)
3271 title = "100Frames";
3272 else if (fc & IEEE80211_FCTL_RETRY)
3273 title = "Retry";
3274 else if (ieee80211_is_assoc_response(fc))
3275 title = "AscRsp";
3276 else if (ieee80211_is_reassoc_response(fc))
3277 title = "RasRsp";
3278 else if (ieee80211_is_probe_response(fc)) {
3279 title = "PrbRsp";
3280 print_dump = 1; /* dump frame contents */
3281 } else if (ieee80211_is_beacon(fc)) {
3282 title = "Beacon";
3283 print_dump = 1; /* dump frame contents */
3284 } else if (ieee80211_is_atim(fc))
3285 title = "ATIM";
3286 else if (ieee80211_is_auth(fc))
3287 title = "Auth";
3288 else if (ieee80211_is_deauth(fc))
3289 title = "DeAuth";
3290 else if (ieee80211_is_disassoc(fc))
3291 title = "DisAssoc";
3292 else
3293 title = "Frame";
3294
3295 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3296 if (unlikely(rate_idx == -1))
3297 bitrate = 0;
3298 else
3299 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3300
3301 /* print frame summary.
3302 * MAC addresses show just the last byte (for brevity),
3303 * but you can hack it to show more, if you'd like to. */
3304 if (dataframe)
3305 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3306 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3307 title, fc, header->addr1[5],
3308 length, rssi, channel, bitrate);
3309 else {
3310 /* src/dst addresses assume managed mode */
3311 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3312 "src=0x%02x, rssi=%u, tim=%lu usec, "
3313 "phy=0x%02x, chnl=%d\n",
3314 title, fc, header->addr1[5],
3315 header->addr3[5], rssi,
3316 tsf_low - priv->scan_start_tsf,
3317 phy_flags, channel);
3318 }
3319 }
3320 if (print_dump)
0a6857e7 3321 iwl_print_hex_dump(IWL_DL_RX, data, length);
17744ff6
TW		 3322}
3323#else
c79dd5b5 3324static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3325 struct iwl4965_rx_packet *pkt,
3326 struct ieee80211_hdr *header,
3327 int group100)
3328{
3329}
3330#endif
3331
b481de9c 3332
7878a5a4 3333
857485c0 3334/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 3335 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
c79dd5b5 3336static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
bb8c093b 3337 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3338{
17744ff6
TW		 3339 struct ieee80211_hdr *header;
3340 struct ieee80211_rx_status rx_status;
bb8c093b 3341 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3342 /* Use phy data (Rx signal strength, etc.) contained within
3343 * this rx packet for legacy frames,
3344 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 3345 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 3346 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3347 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3348 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3349 __le32 *rx_end;
3350 unsigned int len = 0;
b481de9c 3351 u16 fc;
b481de9c
ZY		 3352 u8 network_packet;
3353
17744ff6 3354 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
dc92e497
TW		 3355 rx_status.freq =
3356 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
17744ff6
TW		 3357 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3358 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
dc92e497
TW		 3359 rx_status.rate_idx =
3360 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
17744ff6
TW		 3361 if (rx_status.band == IEEE80211_BAND_5GHZ)
3362 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3363
3364 rx_status.antenna = 0;
3365 rx_status.flag = 0;
3366
b481de9c 3367 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
dc92e497
TW		 3368 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3369 rx_start->cfg_phy_cnt);
b481de9c
ZY		 3370 return;
3371 }
17744ff6 3372
b481de9c
ZY		 3373 if (!include_phy) {
3374 if (priv->last_phy_res[0])
3375 rx_start = (struct iwl4965_rx_phy_res *)
3376 &priv->last_phy_res[1];
3377 else
3378 rx_start = NULL;
3379 }
3380
3381 if (!rx_start) {
3382 IWL_ERROR("MPDU frame without a PHY data\n");
3383 return;
3384 }
3385
3386 if (include_phy) {
3387 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3388 + rx_start->cfg_phy_cnt);
3389
3390 len = le16_to_cpu(rx_start->byte_count);
17744ff6 3391 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 3392 sizeof(struct iwl4965_rx_phy_res) + len);
3393 } else {
3394 struct iwl4965_rx_mpdu_res_start *amsdu =
3395 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3396
3397 header = (void *)(pkt->u.raw +
3398 sizeof(struct iwl4965_rx_mpdu_res_start));
3399 len = le16_to_cpu(amsdu->byte_count);
3400 rx_end = (__le32 *) (pkt->u.raw +
3401 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3402 }
3403
3404 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3405 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3406 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3407 le32_to_cpu(*rx_end));
3408 return;
3409 }
3410
3411 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3412
b481de9c 3413 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
17744ff6 3414 rx_status.ssi = iwl4965_calc_rssi(rx_start);
b481de9c
ZY		 3415
3416 /* Meaningful noise values are available only from beacon statistics,
3417 * which are gathered only when associated, and indicate noise
3418 * only for the associated network channel ...
3419 * Ignore these noise values while scanning (other channels) */
3109ece1 3420 if (iwl_is_associated(priv) &&
b481de9c 3421 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6
TW		 3422 rx_status.noise = priv->last_rx_noise;
3423 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3424 rx_status.noise);
b481de9c 3425 } else {
17744ff6
TW		 3426 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3427 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
b481de9c
ZY		 3428 }
3429
3430 /* Reset beacon noise level if not associated. */
3109ece1 3431 if (!iwl_is_associated(priv))
b481de9c
ZY		 3432 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3433
17744ff6
TW		 3434 /* Set "1" to report good data frames in groups of 100 */
3435 /* FIXME: need to optimze the call: */
3436 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3437
3438 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3439 rx_status.ssi, rx_status.noise, rx_status.signal,
06501d29 3440 (unsigned long long)rx_status.mactime);
b481de9c 3441
bb8c093b 3442 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 3443 if (network_packet) {
17744ff6 3444 priv->last_rx_rssi = rx_status.ssi;
b481de9c
ZY		 3445 priv->last_beacon_time = priv->ucode_beacon_time;
3446 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3447 }
3448
3449 fc = le16_to_cpu(header->frame_control);
3450 switch (fc & IEEE80211_FCTL_FTYPE) {
3451 case IEEE80211_FTYPE_MGMT:
b481de9c
ZY		 3452 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3453 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3454 header->addr2);
17744ff6 3455 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 3456 break;
3457
3458 case IEEE80211_FTYPE_CTL:
9ab46173 3459#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 3460 switch (fc & IEEE80211_FCTL_STYPE) {
3461 case IEEE80211_STYPE_BACK_REQ:
3462 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3463 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 3464 rxb, &rx_status);
b481de9c
ZY		 3465 break;
3466 default:
3467 break;
3468 }
3469#endif
b481de9c
ZY		 3470 break;
3471
0795af57
JP		 3472 case IEEE80211_FTYPE_DATA: {
3473 DECLARE_MAC_BUF(mac1);
3474 DECLARE_MAC_BUF(mac2);
3475 DECLARE_MAC_BUF(mac3);
3476
b481de9c
ZY		 3477 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3478 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3479 header->addr2);
3480
3481 if (unlikely(!network_packet))
3482 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 3483 "%s, %s, %s\n",
3484 print_mac(mac1, header->addr1),
3485 print_mac(mac2, header->addr2),
3486 print_mac(mac3, header->addr3));
bb8c093b 3487 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 3488 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3489 print_mac(mac1, header->addr1),
3490 print_mac(mac2, header->addr2),
3491 print_mac(mac3, header->addr3));
b481de9c
ZY		 3492 else
3493 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 3494 &rx_status);
b481de9c 3495 break;
0795af57 3496 }
b481de9c
ZY		 3497 default:
3498 break;
3499
3500 }
3501}
3502
3503/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3504 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
c79dd5b5 3505static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
bb8c093b 3506 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3507{
bb8c093b 3508 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3509 priv->last_phy_res[0] = 1;
3510 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3511 sizeof(struct iwl4965_rx_phy_res));
3512}
c79dd5b5 3513static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
bb8c093b 3514 struct iwl4965_rx_mem_buffer *rxb)
b481de9c
ZY		 3515
3516{
f0832f13 3517#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
bb8c093b
CH		 3518 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3519 struct iwl4965_missed_beacon_notif *missed_beacon;
b481de9c
ZY		 3520
3521 missed_beacon = &pkt->u.missed_beacon;
3522 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3523 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3524 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3525 le32_to_cpu(missed_beacon->total_missed_becons),
3526 le32_to_cpu(missed_beacon->num_recvd_beacons),
3527 le32_to_cpu(missed_beacon->num_expected_beacons));
f0832f13
EG		 3528 if (!test_bit(STATUS_SCANNING, &priv->status))
3529 iwl_init_sensitivity(priv);
b481de9c 3530 }
f0832f13 3531#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c 3532}
c8b0e6e1 3533#ifdef CONFIG_IWL4965_HT
b481de9c 3534
8b6eaea8
CB		 3535/**
3536 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3537 */
c79dd5b5 3538static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
b481de9c
ZY		 3539 int sta_id, int tid)
3540{
3541 unsigned long flags;
3542
8b6eaea8 3543 /* Remove "disable" flag, to enable Tx for this TID */
b481de9c
ZY		 3544 spin_lock_irqsave(&priv->sta_lock, flags);
3545 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3546 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3547 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3548 spin_unlock_irqrestore(&priv->sta_lock, flags);
3549
bb8c093b 3550 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3551}
3552
8b6eaea8
CB		 3553/**
3554 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3555 *
3556 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3557 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3558 */
c79dd5b5 3559static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b
CH		 3560 struct iwl4965_ht_agg *agg,
3561 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 3562 ba_resp)
3563
3564{
3565 int i, sh, ack;
fe01b477
RR		 3566 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3567 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3568 u64 bitmap;
3569 int successes = 0;
3570 struct ieee80211_tx_status *tx_status;
b481de9c
ZY		 3571
3572 if (unlikely(!agg->wait_for_ba)) {
3573 IWL_ERROR("Received BA when not expected\n");
3574 return -EINVAL;
3575 }
8b6eaea8
CB		 3576
3577 /* Mark that the expected block-ack response arrived */
b481de9c 3578 agg->wait_for_ba = 0;
fe01b477 3579 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 3580
3581 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 3582 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 3583 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 3584 sh += 0x100;
3585
8b6eaea8 3586 /* don't use 64-bit values for now */
fe01b477 3587 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 3588
3589 if (agg->frame_count > (64 - sh)) {
3590 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3591 return -1;
3592 }
3593
3594 /* check for success or failure according to the
8b6eaea8 3595 * transmitted bitmap and block-ack bitmap */
fe01b477 3596 bitmap &= agg->bitmap;
b481de9c 3597
8b6eaea8
CB		 3598 /* For each frame attempted in aggregation,
3599 * update driver's record of tx frame's status. */
b481de9c 3600 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 3601 ack = bitmap & (1 << i);
3602 successes += !!ack;
b481de9c 3603 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 3604 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3605 agg->start_idx + i);
3606 }
3607
3608 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3609 tx_status->flags = IEEE80211_TX_STATUS_ACK;
99556438
RR		 3610 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3611 tx_status->ampdu_ack_map = successes;
3612 tx_status->ampdu_ack_len = agg->frame_count;
4c424e4c
RR		 3613 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3614 &tx_status->control);
fe01b477 3615
f868f4e1 3616 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 3617
3618 return 0;
3619}
3620
3621/**
3622 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3623 */
c79dd5b5 3624static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 3625 u16 txq_id)
3626{
3627 /* Simply stop the queue, but don't change any configuration;
3628 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 3629 iwl_write_prph(priv,
12a81f60 3630 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
fe01b477
RR		 3631 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3632 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3633}
b481de9c 3634
fe01b477
RR		 3635/**
3636 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
b095d03a 3637 * priv->lock must be held by the caller
fe01b477 3638 */
c79dd5b5 3639static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
fe01b477
RR		 3640 u16 ssn_idx, u8 tx_fifo)
3641{
b095d03a
RR		 3642 int ret = 0;
3643
fe01b477
RR		 3644 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3645 IWL_WARNING("queue number too small: %d, must be > %d\n",
3646 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3647 return -EINVAL;
b481de9c
ZY		 3648 }
3649
3395f6e9 3650 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 3651 if (ret)
3652 return ret;
3653
fe01b477
RR		 3654 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3655
12a81f60 3656 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 3657
3658 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3659 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3660 /* supposes that ssn_idx is valid (!= 0xFFF) */
3661 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3662
12a81f60 3663 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
fe01b477
RR		 3664 iwl4965_txq_ctx_deactivate(priv, txq_id);
3665 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3666
3395f6e9 3667 iwl_release_nic_access(priv);
b095d03a 3668
fe01b477
RR		 3669 return 0;
3670}
b481de9c 3671
c79dd5b5 3672int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
fe01b477
RR		 3673 u8 tid, int txq_id)
3674{
3675 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3676 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3677 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3678
3679 switch (priv->stations[sta_id].tid[tid].agg.state) {
3680 case IWL_EMPTYING_HW_QUEUE_DELBA:
3681 /* We are reclaiming the last packet of the */
3682 /* aggregated HW queue */
3683 if (txq_id == tid_data->agg.txq_id &&
3684 q->read_ptr == q->write_ptr) {
3685 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3686 int tx_fifo = default_tid_to_tx_fifo[tid];
3687 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3688 iwl4965_tx_queue_agg_disable(priv, txq_id,
3689 ssn, tx_fifo);
3690 tid_data->agg.state = IWL_AGG_OFF;
3691 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3692 }
3693 break;
3694 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3695 /* We are reclaiming the last packet of the queue */
3696 if (tid_data->tfds_in_queue == 0) {
3697 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3698 tid_data->agg.state = IWL_AGG_ON;
3699 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3700 }
3701 break;
3702 }
b481de9c
ZY		 3703 return 0;
3704}
3705
8b6eaea8
CB		 3706/**
3707 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3708 * @index -- current index
3709 * @n_bd -- total number of entries in queue (s/b power of 2)
3710 */
bb8c093b 3711static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 3712{
3713 return (index == 0) ? n_bd - 1 : index - 1;
3714}
3715
8b6eaea8
CB		 3716/**
3717 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3718 *
3719 * Handles block-acknowledge notification from device, which reports success
3720 * of frames sent via aggregation.
3721 */
c79dd5b5 3722static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b 3723 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3724{
bb8c093b
CH		 3725 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3726 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 3727 int index;
bb8c093b
CH		 3728 struct iwl4965_tx_queue *txq = NULL;
3729 struct iwl4965_ht_agg *agg;
fe01b477 3730 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 3731
3732 /* "flow" corresponds to Tx queue */
fe01b477 3733 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 3734
3735 /* "ssn" is start of block-ack Tx window, corresponds to index
3736 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 3737 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3738
dfe7d458 3739 if (scd_flow >= priv->hw_params.max_txq_num) {
b481de9c
ZY		 3740 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3741 return;
3742 }
3743
fe01b477 3744 txq = &priv->txq[scd_flow];
b481de9c 3745 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 3746
3747 /* Find index just before block-ack window */
bb8c093b 3748 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 3749
01ebd063 3750 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 3751
0795af57
JP		 3752 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3753 "sta_id = %d\n",
b481de9c 3754 agg->wait_for_ba,
0795af57 3755 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 3756 ba_resp->sta_id);
fe01b477 3757 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 3758 "%d, scd_ssn = %d\n",
3759 ba_resp->tid,
fe01b477 3760 ba_resp->seq_ctl,
0310ae72 3761 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 3762 ba_resp->scd_flow,
3763 ba_resp->scd_ssn);
fe01b477 3764 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 3765 agg->start_idx,
f868f4e1 3766 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 3767
3768 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 3769 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 3770
3771 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3772 * block-ack window (we assume that they've been successfully
3773 * transmitted ... if not, it's too late anyway). */
fe01b477
RR		 3774 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3775 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3776 priv->stations[ba_resp->sta_id].
3777 tid[ba_resp->tid].tfds_in_queue -= freed;
3778 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3779 priv->mac80211_registered &&
3780 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3781 ieee80211_wake_queue(priv->hw, scd_flow);
3782 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3783 ba_resp->tid, scd_flow);
3784 }
b481de9c
ZY		 3785}
3786
8b6eaea8
CB		 3787/**
3788 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3789 */
c79dd5b5 3790static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 3791 u16 txq_id)
3792{
3793 u32 tbl_dw_addr;
3794 u32 tbl_dw;
3795 u16 scd_q2ratid;
3796
3797 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3798
3799 tbl_dw_addr = priv->scd_base_addr +
3800 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3801
3395f6e9 3802 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 3803
3804 if (txq_id & 0x1)
3805 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3806 else
3807 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3808
3395f6e9 3809 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 3810
3811 return 0;
3812}
3813
fe01b477 3814
b481de9c 3815/**
8b6eaea8
CB		 3816 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3817 *
3818 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3819 * i.e. it must be one of the higher queues used for aggregation
b481de9c 3820 */
c79dd5b5 3821static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
b481de9c
ZY		 3822 int tx_fifo, int sta_id, int tid,
3823 u16 ssn_idx)
3824{
3825 unsigned long flags;
3826 int rc;
3827 u16 ra_tid;
3828
3829 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3830 IWL_WARNING("queue number too small: %d, must be > %d\n",
3831 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3832
3833 ra_tid = BUILD_RAxTID(sta_id, tid);
3834
8b6eaea8 3835 /* Modify device's station table to Tx this TID */
bb8c093b 3836 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 3837
3838 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 3839 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3840 if (rc) {
3841 spin_unlock_irqrestore(&priv->lock, flags);
3842 return rc;
3843 }
3844
8b6eaea8 3845 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 3846 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3847
8b6eaea8 3848 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 3849 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3850
8b6eaea8 3851 /* Set this queue as a chain-building queue */
12a81f60 3852 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 3853
8b6eaea8
CB		 3854 /* Place first TFD at index corresponding to start sequence number.
3855 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 3856 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3857 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 3858 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3859
8b6eaea8 3860 /* Set up Tx window size and frame limit for this queue */
3395f6e9 3861 iwl_write_targ_mem(priv,
b481de9c
ZY		 3862 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3863 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3864 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3865
3395f6e9 3866 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 3867 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3868 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3869 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3870
12a81f60 3871 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 3872
8b6eaea8 3873 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 3874 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3875
3395f6e9 3876 iwl_release_nic_access(priv);
b481de9c
ZY		 3877 spin_unlock_irqrestore(&priv->lock, flags);
3878
3879 return 0;
3880}
3881
c8b0e6e1 3882#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 3883
3884/**
3885 * iwl4965_add_station - Initialize a station's hardware rate table
3886 *
8b6eaea8 3887 * The uCode's station table contains a table of fallback rates
b481de9c
ZY		 3888 * for automatic fallback during transmission.
3889 *
8b6eaea8
CB		 3890 * NOTE: This sets up a default set of values. These will be replaced later
3891 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3892 * rc80211_simple.
b481de9c 3893 *
8b6eaea8
CB		 3894 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3895 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3896 * which requires station table entry to exist).
b481de9c 3897 */
c79dd5b5 3898void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 3899{
3900 int i, r;
66c73db7 3901 struct iwl_link_quality_cmd link_cmd = {
b481de9c
ZY		 3902 .reserved1 = 0,
3903 };
3904 u16 rate_flags;
3905
8b6eaea8
CB		 3906 /* Set up the rate scaling to start at selected rate, fall back
3907 * all the way down to 1M in IEEE order, and then spin on 1M */
b481de9c
ZY		 3908 if (is_ap)
3909 r = IWL_RATE_54M_INDEX;
8318d78a 3910 else if (priv->band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 3911 r = IWL_RATE_6M_INDEX;
3912 else
3913 r = IWL_RATE_1M_INDEX;
3914
3915 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3916 rate_flags = 0;
3917 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3918 rate_flags |= RATE_MCS_CCK_MSK;
3919
8b6eaea8 3920 /* Use Tx antenna B only */
fde0db31 3921 rate_flags |= RATE_MCS_ANT_B_MSK; /*FIXME:RS*/
8b6eaea8 3922
b481de9c 3923 link_cmd.rs_table[i].rate_n_flags =
bb8c093b
CH		 3924 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3925 r = iwl4965_get_prev_ieee_rate(r);
b481de9c
ZY		 3926 }
3927
3928 link_cmd.general_params.single_stream_ant_msk = 2;
3929 link_cmd.general_params.dual_stream_ant_msk = 3;
3930 link_cmd.agg_params.agg_dis_start_th = 3;
3931 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3932
3933 /* Update the rate scaling for control frame Tx to AP */
5425e490 3934 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
b481de9c 3935
e5472978
TW		 3936 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3937 sizeof(link_cmd), &link_cmd, NULL);
b481de9c
ZY		 3938}
3939
c8b0e6e1 3940#ifdef CONFIG_IWL4965_HT
b481de9c 3941
c79dd5b5 3942static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
8318d78a 3943 enum ieee80211_band band,
78330fdd 3944 u16 channel, u8 extension_chan_offset)
b481de9c 3945{
bf85ea4f 3946 const struct iwl_channel_info *ch_info;
b481de9c 3947
8622e705 3948 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 3949 if (!is_channel_valid(ch_info))
3950 return 0;
3951
134eb5d3 3952 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
b481de9c
ZY		 3953 return 0;
3954
3955 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3956 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3957 return 1;
3958
3959 return 0;
3960}
3961
c79dd5b5 3962static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
fd105e79 3963 struct ieee80211_ht_info *sta_ht_inf)
b481de9c 3964{
fd105e79 3965 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
b481de9c 3966
fd105e79
RR		 3967 if ((!iwl_ht_conf->is_ht) ||
3968 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
134eb5d3 3969 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
b481de9c
ZY		 3970 return 0;
3971
fd105e79
RR		 3972 if (sta_ht_inf) {
3973 if ((!sta_ht_inf->ht_supported) ||
194c7ca6 3974 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
fd105e79
RR		 3975 return 0;
3976 }
b481de9c 3977
78330fdd 3978 return (iwl4965_is_channel_extension(priv, priv->band,
fd105e79
RR		 3979 iwl_ht_conf->control_channel,
3980 iwl_ht_conf->extension_chan_offset));
b481de9c
ZY		 3981}
3982
c79dd5b5 3983void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
b481de9c 3984{
bb8c093b 3985 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 3986 u32 val;
3987
3988 if (!ht_info->is_ht)
3989 return;
3990
8b6eaea8 3991 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
fd105e79 3992 if (iwl4965_is_fat_tx_allowed(priv, NULL))
b481de9c
ZY		 3993 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3994 else
3995 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
3996 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
3997
3998 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
3999 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4000 le16_to_cpu(rxon->channel),
4001 ht_info->control_channel);
4002 rxon->channel = cpu_to_le16(ht_info->control_channel);
4003 return;
4004 }
4005
8b6eaea8 4006 /* Note: control channel is opposite of extension channel */
b481de9c
ZY		 4007 switch (ht_info->extension_chan_offset) {
4008 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4009 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4010 break;
4011 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4012 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4013 break;
134eb5d3 4014 case IWL_EXT_CHANNEL_OFFSET_NONE:
b481de9c
ZY		 4015 default:
4016 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4017 break;
4018 }
4019
fd105e79 4020 val = ht_info->ht_protection;
b481de9c
ZY		 4021
4022 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4023
b481de9c
ZY		 4024 iwl4965_set_rxon_chain(priv);
4025
fde0db31 4026 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
b481de9c
ZY		 4027 "rxon flags 0x%X operation mode :0x%X "
4028 "extension channel offset 0x%x "
4029 "control chan %d\n",
fde0db31
GC		 4030 ht_info->supp_mcs_set[0],
4031 ht_info->supp_mcs_set[1],
4032 ht_info->supp_mcs_set[2],
fd105e79 4033 le32_to_cpu(rxon->flags), ht_info->ht_protection,
b481de9c
ZY		 4034 ht_info->extension_chan_offset,
4035 ht_info->control_channel);
4036 return;
4037}
4038
c79dd5b5 4039void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
67d62035 4040 struct ieee80211_ht_info *sta_ht_inf)
b481de9c
ZY		 4041{
4042 __le32 sta_flags;
e53cfe0e 4043 u8 mimo_ps_mode;
b481de9c 4044
67d62035 4045 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
b481de9c
ZY		 4046 goto done;
4047
e53cfe0e
TW		 4048 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4049
b481de9c
ZY		 4050 sta_flags = priv->stations[index].sta.station_flags;
4051
e53cfe0e
TW		 4052 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4053
4054 switch (mimo_ps_mode) {
4055 case WLAN_HT_CAP_MIMO_PS_STATIC:
4056 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4057 break;
4058 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
b481de9c 4059 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
e53cfe0e
TW		 4060 break;
4061 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4062 break;
4063 default:
4064 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4065 break;
4066 }
b481de9c
ZY		 4067
4068 sta_flags |= cpu_to_le32(
67d62035 4069 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
b481de9c
ZY		 4070
4071 sta_flags |= cpu_to_le32(
67d62035 4072 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
b481de9c 4073
67d62035 4074 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
b481de9c 4075 sta_flags |= STA_FLG_FAT_EN_MSK;
67d62035 4076 else
e53cfe0e 4077 sta_flags &= ~STA_FLG_FAT_EN_MSK;
67d62035 4078
b481de9c
ZY		 4079 priv->stations[index].sta.station_flags = sta_flags;
4080 done:
4081 return;
4082}
4083
fe07aa7a
RR		 4084static int iwl4965_rx_agg_start(struct iwl_priv *priv,
4085 const u8 *addr, int tid, u16 ssn)
b481de9c
ZY		 4086{
4087 unsigned long flags;
fe07aa7a
RR		 4088 int sta_id;
4089
4090 sta_id = iwl_find_station(priv, addr);
4091 if (sta_id == IWL_INVALID_STATION)
4092 return -ENXIO;
b481de9c
ZY		 4093
4094 spin_lock_irqsave(&priv->sta_lock, flags);
4095 priv->stations[sta_id].sta.station_flags_msk = 0;
4096 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4097 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4098 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4099 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4100 spin_unlock_irqrestore(&priv->sta_lock, flags);
4101
fe07aa7a
RR		 4102 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4103 CMD_ASYNC);
b481de9c
ZY		 4104}
4105
fe07aa7a
RR		 4106static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
4107 const u8 *addr, int tid)
b481de9c
ZY		 4108{
4109 unsigned long flags;
fe07aa7a
RR		 4110 int sta_id;
4111
4112 sta_id = iwl_find_station(priv, addr);
4113 if (sta_id == IWL_INVALID_STATION)
4114 return -ENXIO;
b481de9c
ZY		 4115
4116 spin_lock_irqsave(&priv->sta_lock, flags);
4117 priv->stations[sta_id].sta.station_flags_msk = 0;
4118 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4119 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4120 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4121 spin_unlock_irqrestore(&priv->sta_lock, flags);
4122
fe07aa7a
RR		 4123 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4124 CMD_ASYNC);
b481de9c
ZY		 4125}
4126
8b6eaea8
CB		 4127/*
4128 * Find first available (lowest unused) Tx Queue, mark it "active".
4129 * Called only when finding queue for aggregation.
4130 * Should never return anything < 7, because they should already
4131 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4132 */
c79dd5b5 4133static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
b481de9c
ZY		 4134{
4135 int txq_id;
4136
5425e490 4137 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
b481de9c
ZY		 4138 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4139 return txq_id;
4140 return -1;
4141}
4142
fe07aa7a
RR		 4143static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
4144 u16 tid, u16 *start_seq_num)
b481de9c 4145{
c79dd5b5 4146 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 4147 int sta_id;
4148 int tx_fifo;
4149 int txq_id;
4150 int ssn = -1;
b095d03a 4151 int ret = 0;
b481de9c 4152 unsigned long flags;
bb8c093b 4153 struct iwl4965_tid_data *tid_data;
0795af57 4154 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 4155
4156 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4157 tx_fifo = default_tid_to_tx_fifo[tid];
4158 else
4159 return -EINVAL;
4160
fe07aa7a
RR		 4161 IWL_WARNING("%s on ra = %s tid = %d\n",
4162 __func__, print_mac(mac, ra), tid);
b481de9c 4163
fe07aa7a 4164 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 4165 if (sta_id == IWL_INVALID_STATION)
4166 return -ENXIO;
4167
fe01b477
RR		 4168 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4169 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4170 return -ENXIO;
4171 }
4172
bb8c093b 4173 txq_id = iwl4965_txq_ctx_activate_free(priv);
b481de9c
ZY		 4174 if (txq_id == -1)
4175 return -ENXIO;
4176
4177 spin_lock_irqsave(&priv->sta_lock, flags);
4178 tid_data = &priv->stations[sta_id].tid[tid];
4179 ssn = SEQ_TO_SN(tid_data->seq_number);
4180 tid_data->agg.txq_id = txq_id;
4181 spin_unlock_irqrestore(&priv->sta_lock, flags);
4182
4183 *start_seq_num = ssn;
b095d03a
RR		 4184 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4185 sta_id, tid, ssn);
4186 if (ret)
4187 return ret;
b481de9c 4188
b095d03a 4189 ret = 0;
fe01b477
RR		 4190 if (tid_data->tfds_in_queue == 0) {
4191 printk(KERN_ERR "HW queue is empty\n");
4192 tid_data->agg.state = IWL_AGG_ON;
fe07aa7a 4193 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
fe01b477
RR		 4194 } else {
4195 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4196 tid_data->tfds_in_queue);
4197 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4198 }
b095d03a 4199 return ret;
fe01b477 4200}
b481de9c 4201
fe07aa7a 4202static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
b481de9c 4203{
c79dd5b5 4204 struct iwl_priv *priv = hw->priv;
b481de9c 4205 int tx_fifo_id, txq_id, sta_id, ssn = -1;
bb8c093b 4206 struct iwl4965_tid_data *tid_data;
b095d03a 4207 int ret, write_ptr, read_ptr;
fe01b477 4208 unsigned long flags;
0795af57
JP		 4209 DECLARE_MAC_BUF(mac);
4210
fe07aa7a
RR		 4211 if (!ra) {
4212 IWL_ERROR("ra = NULL\n");
b481de9c
ZY		 4213 return -EINVAL;
4214 }
4215
4216 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4217 tx_fifo_id = default_tid_to_tx_fifo[tid];
4218 else
4219 return -EINVAL;
4220
fe07aa7a 4221 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 4222
4223 if (sta_id == IWL_INVALID_STATION)
4224 return -ENXIO;
4225
fe01b477
RR		 4226 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4227 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4228
b481de9c
ZY		 4229 tid_data = &priv->stations[sta_id].tid[tid];
4230 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4231 txq_id = tid_data->agg.txq_id;
fe01b477
RR		 4232 write_ptr = priv->txq[txq_id].q.write_ptr;
4233 read_ptr = priv->txq[txq_id].q.read_ptr;
4234
4235 /* The queue is not empty */
4236 if (write_ptr != read_ptr) {
4237 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4238 priv->stations[sta_id].tid[tid].agg.state =
4239 IWL_EMPTYING_HW_QUEUE_DELBA;
4240 return 0;
4241 }
4242
fe07aa7a 4243 IWL_DEBUG_HT("HW queue is empty\n");
fe01b477 4244 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
b481de9c 4245
fe01b477 4246 spin_lock_irqsave(&priv->lock, flags);
b095d03a 4247 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
fe01b477
RR		 4248 spin_unlock_irqrestore(&priv->lock, flags);
4249
b095d03a
RR		 4250 if (ret)
4251 return ret;
b481de9c 4252
fe07aa7a 4253 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
8114fcf1 4254
8114fcf1
RR		 4255 return 0;
4256}
4257
4258int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4259 enum ieee80211_ampdu_mlme_action action,
4260 const u8 *addr, u16 tid, u16 *ssn)
4261{
c79dd5b5 4262 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 4263 DECLARE_MAC_BUF(mac);
4264
fe07aa7a
RR		 4265 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4266 print_mac(mac, addr), tid);
4267
8114fcf1
RR		 4268 switch (action) {
4269 case IEEE80211_AMPDU_RX_START:
4270 IWL_DEBUG_HT("start Rx\n");
fe07aa7a 4271 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
8114fcf1
RR		 4272 case IEEE80211_AMPDU_RX_STOP:
4273 IWL_DEBUG_HT("stop Rx\n");
fe07aa7a 4274 return iwl4965_rx_agg_stop(priv, addr, tid);
8114fcf1
RR		 4275 case IEEE80211_AMPDU_TX_START:
4276 IWL_DEBUG_HT("start Tx\n");
fe07aa7a 4277 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
8114fcf1
RR		 4278 case IEEE80211_AMPDU_TX_STOP:
4279 IWL_DEBUG_HT("stop Tx\n");
fe07aa7a 4280 return iwl4965_tx_agg_stop(hw, addr, tid);
8114fcf1
RR		 4281 default:
4282 IWL_DEBUG_HT("unknown\n");
4283 return -EINVAL;
4284 break;
4285 }
4286 return 0;
4287}
4288
c8b0e6e1 4289#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4290
4291/* Set up 4965-specific Rx frame reply handlers */
c79dd5b5 4292void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 4293{
4294 /* Legacy Rx frames */
857485c0 4295 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
b481de9c
ZY		 4296
4297 /* High-throughput (HT) Rx frames */
4298 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4299 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4300
4301 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4302 iwl4965_rx_missed_beacon_notif;
4303
c8b0e6e1 4304#ifdef CONFIG_IWL4965_HT
b481de9c 4305 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
c8b0e6e1 4306#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4307}
4308
c79dd5b5 4309void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4310{
4311 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
f0832f13 4312#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 4313 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4314#endif
b481de9c
ZY		 4315 init_timer(&priv->statistics_periodic);
4316 priv->statistics_periodic.data = (unsigned long)priv;
4317 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4318}
4319
c79dd5b5 4320void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4321{
4322 del_timer_sync(&priv->statistics_periodic);
4323
4324 cancel_delayed_work(&priv->init_alive_start);
4325}
4326
3c424c28
TW		 4327
4328static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 4329 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 4330};
4331
857485c0
TW		 4332static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4333 .enqueue_hcmd = iwl4965_enqueue_hcmd,
f0832f13
EG		 4334#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4335 .chain_noise_reset = iwl4965_chain_noise_reset,
4336 .gain_computation = iwl4965_gain_computation,
4337#endif
857485c0
TW		 4338};
4339
6bc913bd 4340static struct iwl_lib_ops iwl4965_lib = {
bf85ea4f 4341 .init_drv = iwl4965_init_drv,
5425e490 4342 .set_hw_params = iwl4965_hw_set_hw_params,
e2a722eb 4343 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
57aab75a
TW		 4344 .hw_nic_init = iwl4965_hw_nic_init,
4345 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4346 .alive_notify = iwl4965_alive_notify,
4347 .load_ucode = iwl4965_load_bsm,
6f4083aa 4348 .apm_ops = {
91238714 4349 .init = iwl4965_apm_init,
6f4083aa
TW		 4350 .set_pwr_src = iwl4965_set_pwr_src,
4351 },
6bc913bd 4352 .eeprom_ops = {
073d3f5f
TW		 4353 .regulatory_bands = {
4354 EEPROM_REGULATORY_BAND_1_CHANNELS,
4355 EEPROM_REGULATORY_BAND_2_CHANNELS,
4356 EEPROM_REGULATORY_BAND_3_CHANNELS,
4357 EEPROM_REGULATORY_BAND_4_CHANNELS,
4358 EEPROM_REGULATORY_BAND_5_CHANNELS,
4359 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
4360 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
4361 },
6bc913bd
AK		 4362 .verify_signature = iwlcore_eeprom_verify_signature,
4363 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4364 .release_semaphore = iwlcore_eeprom_release_semaphore,
073d3f5f 4365 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 4366 },
ad97edd2 4367 .radio_kill_sw = iwl4965_radio_kill_sw,
5da4b55f
MA		 4368 .set_power = iwl4965_set_power,
4369 .update_chain_flags = iwl4965_update_chain_flags,
6bc913bd
AK		 4370};
4371
4372static struct iwl_ops iwl4965_ops = {
4373 .lib = &iwl4965_lib,
3c424c28 4374 .hcmd = &iwl4965_hcmd,
857485c0 4375 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 4376};
4377
fed9017e 4378struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 4379 .name = "4965AGN",
4bf775cd 4380 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 4381 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 4382 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
6bc913bd 4383 .ops = &iwl4965_ops,
1ea87396 4384 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 4385};
4386
1ea87396
AK		 4387module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4388MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4389module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4390MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b
EG		 4391module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4392MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
1ea87396
AK		 4393module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4394MODULE_PARM_DESC(debug, "debug output mask");
4395module_param_named(
4396 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4397MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4398
4399module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4400MODULE_PARM_DESC(queues_num, "number of hw queues.");
4401
4402/* QoS */
4403module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4404MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4405module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4406MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4407
Linux kernel - Deliverables
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