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iwlwifi: Add led support
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
82b9a121 42#include "iwl-core.h"
b481de9c
ZY		 43#include "iwl-4965.h"
44#include "iwl-helpers.h"
45
1ea87396
AK		 46/* module parameters */
47static struct iwl_mod_params iwl4965_mod_params = {
48 .num_of_queues = IWL_MAX_NUM_QUEUES,
49 .enable_qos = 1,
50 .amsdu_size_8K = 1,
51 /* the rest are 0 by default */
52};
53
c79dd5b5 54static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
416e1438 55
b481de9c
ZY		 56#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
57 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
58 IWL_RATE_SISO_##s##M_PLCP, \
59 IWL_RATE_MIMO_##s##M_PLCP, \
60 IWL_RATE_##r##M_IEEE, \
61 IWL_RATE_##ip##M_INDEX, \
62 IWL_RATE_##in##M_INDEX, \
63 IWL_RATE_##rp##M_INDEX, \
64 IWL_RATE_##rn##M_INDEX, \
65 IWL_RATE_##pp##M_INDEX, \
66 IWL_RATE_##np##M_INDEX }
67
68/*
69 * Parameter order:
70 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
71 *
72 * If there isn't a valid next or previous rate then INV is used which
73 * maps to IWL_RATE_INVALID
74 *
75 */
bb8c093b 76const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
b481de9c
ZY		 77 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
78 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
79 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
80 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
81 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
82 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
83 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
84 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
85 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
86 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
87 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
88 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
89 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
90};
91
fe01b477
RR		 92#ifdef CONFIG_IWL4965_HT
93
94static const u16 default_tid_to_tx_fifo[] = {
95 IWL_TX_FIFO_AC1,
96 IWL_TX_FIFO_AC0,
97 IWL_TX_FIFO_AC0,
98 IWL_TX_FIFO_AC1,
99 IWL_TX_FIFO_AC2,
100 IWL_TX_FIFO_AC2,
101 IWL_TX_FIFO_AC3,
102 IWL_TX_FIFO_AC3,
103 IWL_TX_FIFO_NONE,
104 IWL_TX_FIFO_NONE,
105 IWL_TX_FIFO_NONE,
106 IWL_TX_FIFO_NONE,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_AC3
112};
113
114#endif /*CONFIG_IWL4965_HT */
115
bf85ea4f
AK		 116static int iwl4965_init_drv(struct iwl_priv *priv)
117{
118 int ret;
119 int i;
120
1ea87396 121 priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
bf85ea4f
AK		 122 priv->retry_rate = 1;
123 priv->ibss_beacon = NULL;
124
125 spin_lock_init(&priv->lock);
126 spin_lock_init(&priv->power_data.lock);
127 spin_lock_init(&priv->sta_lock);
128 spin_lock_init(&priv->hcmd_lock);
129 spin_lock_init(&priv->lq_mngr.lock);
130
131 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
132 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
133
134 INIT_LIST_HEAD(&priv->free_frames);
135
136 mutex_init(&priv->mutex);
137
138 /* Clear the driver's (not device's) station table */
139 iwlcore_clear_stations_table(priv);
140
141 priv->data_retry_limit = -1;
142 priv->ieee_channels = NULL;
143 priv->ieee_rates = NULL;
144 priv->band = IEEE80211_BAND_2GHZ;
145
146 priv->iw_mode = IEEE80211_IF_TYPE_STA;
147
148 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
149 priv->valid_antenna = 0x7; /* assume all 3 connected */
150 priv->ps_mode = IWL_MIMO_PS_NONE;
151
152 /* Choose which receivers/antennas to use */
153 iwl4965_set_rxon_chain(priv);
154
155 iwlcore_reset_qos(priv);
156
157 priv->qos_data.qos_active = 0;
158 priv->qos_data.qos_cap.val = 0;
159
160 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
161
162 priv->rates_mask = IWL_RATES_MASK;
163 /* If power management is turned on, default to AC mode */
164 priv->power_mode = IWL_POWER_AC;
165 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
166
167 ret = iwl_init_channel_map(priv);
168 if (ret) {
169 IWL_ERROR("initializing regulatory failed: %d\n", ret);
170 goto err;
171 }
172
173 ret = iwl4965_init_geos(priv);
174 if (ret) {
175 IWL_ERROR("initializing geos failed: %d\n", ret);
176 goto err_free_channel_map;
177 }
178
179 iwl4965_rate_control_register(priv->hw);
180 ret = ieee80211_register_hw(priv->hw);
181 if (ret) {
182 IWL_ERROR("Failed to register network device (error %d)\n",
183 ret);
184 goto err_free_geos;
185 }
186
187 priv->hw->conf.beacon_int = 100;
188 priv->mac80211_registered = 1;
189
190 return 0;
191
192err_free_geos:
193 iwl4965_free_geos(priv);
194err_free_channel_map:
195 iwl_free_channel_map(priv);
196err:
197 return ret;
198}
199
b481de9c
ZY		 200static int is_fat_channel(__le32 rxon_flags)
201{
202 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
203 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
204}
205
c79dd5b5 206static u8 is_single_stream(struct iwl_priv *priv)
b481de9c 207{
c8b0e6e1 208#ifdef CONFIG_IWL4965_HT
fd105e79
RR		 209 if (!priv->current_ht_config.is_ht ||
210 (priv->current_ht_config.supp_mcs_set[1] == 0) ||
b481de9c
ZY		 211 (priv->ps_mode == IWL_MIMO_PS_STATIC))
212 return 1;
213#else
214 return 1;
c8b0e6e1 215#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 216 return 0;
217}
218
17744ff6
TW		 219int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
220{
221 int idx = 0;
222
223 /* 4965 HT rate format */
224 if (rate_n_flags & RATE_MCS_HT_MSK) {
225 idx = (rate_n_flags & 0xff);
226
227 if (idx >= IWL_RATE_MIMO_6M_PLCP)
228 idx = idx - IWL_RATE_MIMO_6M_PLCP;
229
230 idx += IWL_FIRST_OFDM_RATE;
231 /* skip 9M not supported in ht*/
232 if (idx >= IWL_RATE_9M_INDEX)
233 idx += 1;
234 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
235 return idx;
236
237 /* 4965 legacy rate format, search for match in table */
238 } else {
239 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
240 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
241 return idx;
242 }
243
244 return -1;
245}
246
4c424e4c
RR		 247/**
248 * translate ucode response to mac80211 tx status control values
249 */
c79dd5b5 250void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
4c424e4c
RR		 251 struct ieee80211_tx_control *control)
252{
253 int rate_index;
254
255 control->antenna_sel_tx =
256 ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_A_POS);
257 if (rate_n_flags & RATE_MCS_HT_MSK)
258 control->flags |= IEEE80211_TXCTL_OFDM_HT;
259 if (rate_n_flags & RATE_MCS_GF_MSK)
260 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
261 if (rate_n_flags & RATE_MCS_FAT_MSK)
262 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
263 if (rate_n_flags & RATE_MCS_DUP_MSK)
264 control->flags |= IEEE80211_TXCTL_DUP_DATA;
265 if (rate_n_flags & RATE_MCS_SGI_MSK)
266 control->flags |= IEEE80211_TXCTL_SHORT_GI;
267 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
268 * IEEE80211_BAND_2GHZ band as it contains all the rates */
269 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
270 if (rate_index == -1)
271 control->tx_rate = NULL;
272 else
273 control->tx_rate =
274 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
275}
17744ff6 276
b481de9c
ZY		 277/*
278 * Determine how many receiver/antenna chains to use.
279 * More provides better reception via diversity. Fewer saves power.
280 * MIMO (dual stream) requires at least 2, but works better with 3.
281 * This does not determine *which* chains to use, just how many.
282 */
c79dd5b5 283static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
b481de9c
ZY		 284 u8 *idle_state, u8 *rx_state)
285{
286 u8 is_single = is_single_stream(priv);
287 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
288
289 /* # of Rx chains to use when expecting MIMO. */
290 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
291 *rx_state = 2;
292 else
293 *rx_state = 3;
294
295 /* # Rx chains when idling and maybe trying to save power */
296 switch (priv->ps_mode) {
297 case IWL_MIMO_PS_STATIC:
298 case IWL_MIMO_PS_DYNAMIC:
299 *idle_state = (is_cam) ? 2 : 1;
300 break;
301 case IWL_MIMO_PS_NONE:
302 *idle_state = (is_cam) ? *rx_state : 1;
303 break;
304 default:
305 *idle_state = 1;
306 break;
307 }
308
309 return 0;
310}
311
c79dd5b5 312int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 313{
314 int rc;
315 unsigned long flags;
316
317 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 318 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 319 if (rc) {
320 spin_unlock_irqrestore(&priv->lock, flags);
321 return rc;
322 }
323
8b6eaea8 324 /* stop Rx DMA */
bb8c093b
CH		 325 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
326 rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
b481de9c
ZY		 327 (1 << 24), 1000);
328 if (rc < 0)
329 IWL_ERROR("Can't stop Rx DMA.\n");
330
bb8c093b 331 iwl4965_release_nic_access(priv);
b481de9c
ZY		 332 spin_unlock_irqrestore(&priv->lock, flags);
333
334 return 0;
335}
336
c79dd5b5 337u8 iwl4965_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c
ZY		 338{
339 int i;
340 int start = 0;
341 int ret = IWL_INVALID_STATION;
342 unsigned long flags;
0795af57 343 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 344
345 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
346 (priv->iw_mode == IEEE80211_IF_TYPE_AP))
347 start = IWL_STA_ID;
348
349 if (is_broadcast_ether_addr(addr))
a4062b8f 350 return priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 351
352 spin_lock_irqsave(&priv->sta_lock, flags);
353 for (i = start; i < priv->hw_setting.max_stations; i++)
354 if ((priv->stations[i].used) &&
355 (!compare_ether_addr
356 (priv->stations[i].sta.sta.addr, addr))) {
357 ret = i;
358 goto out;
359 }
360
a50e2e3f 361 IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
0795af57 362 print_mac(mac, addr), priv->num_stations);
b481de9c
ZY		 363
364 out:
365 spin_unlock_irqrestore(&priv->sta_lock, flags);
366 return ret;
367}
368
c79dd5b5 369static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
b481de9c 370{
d8609652 371 int ret;
b481de9c
ZY		 372 unsigned long flags;
373
374 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 375 ret = iwl4965_grab_nic_access(priv);
d8609652 376 if (ret) {
b481de9c 377 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 378 return ret;
b481de9c
ZY		 379 }
380
381 if (!pwr_max) {
382 u32 val;
383
d8609652 384 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
b481de9c
ZY		 385 &val);
386
387 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
bb8c093b 388 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 389 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
390 ~APMG_PS_CTRL_MSK_PWR_SRC);
391 } else
bb8c093b 392 iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 393 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
394 ~APMG_PS_CTRL_MSK_PWR_SRC);
395
bb8c093b 396 iwl4965_release_nic_access(priv);
b481de9c
ZY		 397 spin_unlock_irqrestore(&priv->lock, flags);
398
d8609652 399 return ret;
b481de9c
ZY		 400}
401
c79dd5b5 402static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c
ZY		 403{
404 int rc;
405 unsigned long flags;
9ee1ba47 406 unsigned int rb_size;
b481de9c
ZY		 407
408 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 409 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 410 if (rc) {
411 spin_unlock_irqrestore(&priv->lock, flags);
412 return rc;
413 }
414
1ea87396 415 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 416 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
417 else
418 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
419
8b6eaea8 420 /* Stop Rx DMA */
bb8c093b 421 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
b481de9c 422
8b6eaea8 423 /* Reset driver's Rx queue write index */
bb8c093b 424 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
8b6eaea8
CB		 425
426 /* Tell device where to find RBD circular buffer in DRAM */
bb8c093b 427 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
b481de9c
ZY		 428 rxq->dma_addr >> 8);
429
8b6eaea8 430 /* Tell device where in DRAM to update its Rx status */
bb8c093b 431 iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
b481de9c 432 (priv->hw_setting.shared_phys +
bb8c093b 433 offsetof(struct iwl4965_shared, val0)) >> 4);
b481de9c 434
8b6eaea8 435 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
bb8c093b 436 iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
b481de9c
ZY		 437 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
438 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
9ee1ba47 439 rb_size |
b481de9c
ZY		 440 /*0x10 << 4 | */
441 (RX_QUEUE_SIZE_LOG <<
442 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
443
444 /*
bb8c093b 445 * iwl4965_write32(priv,CSR_INT_COAL_REG,0);
b481de9c
ZY		 446 */
447
bb8c093b 448 iwl4965_release_nic_access(priv);
b481de9c
ZY		 449 spin_unlock_irqrestore(&priv->lock, flags);
450
451 return 0;
452}
453
8b6eaea8 454/* Tell 4965 where to find the "keep warm" buffer */
c79dd5b5 455static int iwl4965_kw_init(struct iwl_priv *priv)
b481de9c
ZY		 456{
457 unsigned long flags;
458 int rc;
459
460 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 461 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 462 if (rc)
463 goto out;
464
bb8c093b 465 iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
b481de9c 466 priv->kw.dma_addr >> 4);
bb8c093b 467 iwl4965_release_nic_access(priv);
b481de9c
ZY		 468out:
469 spin_unlock_irqrestore(&priv->lock, flags);
470 return rc;
471}
472
c79dd5b5 473static int iwl4965_kw_alloc(struct iwl_priv *priv)
b481de9c
ZY		 474{
475 struct pci_dev *dev = priv->pci_dev;
bb8c093b 476 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 477
478 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
479 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
480 if (!kw->v_addr)
481 return -ENOMEM;
482
483 return 0;
484}
485
8b6eaea8
CB		 486/**
487 * iwl4965_kw_free - Free the "keep warm" buffer
488 */
c79dd5b5 489static void iwl4965_kw_free(struct iwl_priv *priv)
b481de9c
ZY		 490{
491 struct pci_dev *dev = priv->pci_dev;
bb8c093b 492 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 493
494 if (kw->v_addr) {
495 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
496 memset(kw, 0, sizeof(*kw));
497 }
498}
499
500/**
501 * iwl4965_txq_ctx_reset - Reset TX queue context
502 * Destroys all DMA structures and initialise them again
503 *
504 * @param priv
505 * @return error code
506 */
c79dd5b5 507static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 508{
509 int rc = 0;
510 int txq_id, slots_num;
511 unsigned long flags;
512
513 iwl4965_kw_free(priv);
514
8b6eaea8 515 /* Free all tx/cmd queues and keep-warm buffer */
bb8c093b 516 iwl4965_hw_txq_ctx_free(priv);
b481de9c 517
8b6eaea8 518 /* Alloc keep-warm buffer */
b481de9c
ZY		 519 rc = iwl4965_kw_alloc(priv);
520 if (rc) {
521 IWL_ERROR("Keep Warm allocation failed");
522 goto error_kw;
523 }
524
525 spin_lock_irqsave(&priv->lock, flags);
526
bb8c093b 527 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 528 if (unlikely(rc)) {
529 IWL_ERROR("TX reset failed");
530 spin_unlock_irqrestore(&priv->lock, flags);
531 goto error_reset;
532 }
533
8b6eaea8 534 /* Turn off all Tx DMA channels */
bb8c093b
CH		 535 iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0);
536 iwl4965_release_nic_access(priv);
b481de9c
ZY		 537 spin_unlock_irqrestore(&priv->lock, flags);
538
8b6eaea8 539 /* Tell 4965 where to find the keep-warm buffer */
b481de9c
ZY		 540 rc = iwl4965_kw_init(priv);
541 if (rc) {
542 IWL_ERROR("kw_init failed\n");
543 goto error_reset;
544 }
545
8b6eaea8
CB		 546 /* Alloc and init all (default 16) Tx queues,
547 * including the command queue (#4) */
b481de9c
ZY		 548 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
549 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
550 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 551 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 552 txq_id);
553 if (rc) {
554 IWL_ERROR("Tx %d queue init failed\n", txq_id);
555 goto error;
556 }
557 }
558
559 return rc;
560
561 error:
bb8c093b 562 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 563 error_reset:
564 iwl4965_kw_free(priv);
565 error_kw:
566 return rc;
567}
568
c79dd5b5 569int iwl4965_hw_nic_init(struct iwl_priv *priv)
b481de9c
ZY		 570{
571 int rc;
572 unsigned long flags;
bb8c093b 573 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 574 u8 rev_id;
575 u32 val;
576 u8 val_link;
577
bb8c093b 578 iwl4965_power_init_handle(priv);
b481de9c
ZY		 579
580 /* nic_init */
581 spin_lock_irqsave(&priv->lock, flags);
582
bb8c093b 583 iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 584 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
585
bb8c093b
CH		 586 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
587 rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 588 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
589 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
590 if (rc < 0) {
591 spin_unlock_irqrestore(&priv->lock, flags);
592 IWL_DEBUG_INFO("Failed to init the card\n");
593 return rc;
594 }
595
bb8c093b 596 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 597 if (rc) {
598 spin_unlock_irqrestore(&priv->lock, flags);
599 return rc;
600 }
601
bb8c093b 602 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c 603
bb8c093b 604 iwl4965_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 605 APMG_CLK_VAL_DMA_CLK_RQT |
606 APMG_CLK_VAL_BSM_CLK_RQT);
bb8c093b 607 iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c
ZY		 608
609 udelay(20);
610
bb8c093b 611 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c
ZY		 612 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
613
bb8c093b
CH		 614 iwl4965_release_nic_access(priv);
615 iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32);
b481de9c
ZY		 616 spin_unlock_irqrestore(&priv->lock, flags);
617
618 /* Determine HW type */
619 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
620 if (rc)
621 return rc;
622
623 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
624
625 iwl4965_nic_set_pwr_src(priv, 1);
626 spin_lock_irqsave(&priv->lock, flags);
627
628 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
629 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
630 /* Enable No Snoop field */
631 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
632 val & ~(1 << 11));
633 }
634
635 spin_unlock_irqrestore(&priv->lock, flags);
636
b481de9c
ZY		 637 if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
638 IWL_ERROR("Older EEPROM detected! Aborting.\n");
639 return -EINVAL;
640 }
641
642 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
643
644 /* disable L1 entry -- workaround for pre-B1 */
645 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
646
647 spin_lock_irqsave(&priv->lock, flags);
648
649 /* set CSR_HW_CONFIG_REG for uCode use */
650
9f6adf23 651 iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1
TW		 652 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
653 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
654 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 655
bb8c093b 656 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 657 if (rc < 0) {
658 spin_unlock_irqrestore(&priv->lock, flags);
659 IWL_DEBUG_INFO("Failed to init the card\n");
660 return rc;
661 }
662
bb8c093b
CH		 663 iwl4965_read_prph(priv, APMG_PS_CTRL_REG);
664 iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 665 APMG_PS_CTRL_VAL_RESET_REQ);
666 udelay(5);
bb8c093b 667 iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 668 APMG_PS_CTRL_VAL_RESET_REQ);
669
bb8c093b 670 iwl4965_release_nic_access(priv);
b481de9c
ZY		 671 spin_unlock_irqrestore(&priv->lock, flags);
672
bb8c093b 673 iwl4965_hw_card_show_info(priv);
b481de9c
ZY		 674
675 /* end nic_init */
676
677 /* Allocate the RX queue, or reset if it is already allocated */
678 if (!rxq->bd) {
bb8c093b 679 rc = iwl4965_rx_queue_alloc(priv);
b481de9c
ZY		 680 if (rc) {
681 IWL_ERROR("Unable to initialize Rx queue\n");
682 return -ENOMEM;
683 }
684 } else
bb8c093b 685 iwl4965_rx_queue_reset(priv, rxq);
b481de9c 686
bb8c093b 687 iwl4965_rx_replenish(priv);
b481de9c
ZY		 688
689 iwl4965_rx_init(priv, rxq);
690
691 spin_lock_irqsave(&priv->lock, flags);
692
693 rxq->need_update = 1;
bb8c093b 694 iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 695
696 spin_unlock_irqrestore(&priv->lock, flags);
8b6eaea8
CB		 697
698 /* Allocate and init all Tx and Command queues */
b481de9c
ZY		 699 rc = iwl4965_txq_ctx_reset(priv);
700 if (rc)
701 return rc;
702
703 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
704 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
705
706 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
707 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
708
709 set_bit(STATUS_INIT, &priv->status);
710
711 return 0;
712}
713
c79dd5b5 714int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 715{
716 int rc = 0;
717 u32 reg_val;
718 unsigned long flags;
719
720 spin_lock_irqsave(&priv->lock, flags);
721
722 /* set stop master bit */
bb8c093b 723 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 724
bb8c093b 725 reg_val = iwl4965_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 726
727 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
728 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
729 IWL_DEBUG_INFO("Card in power save, master is already "
730 "stopped\n");
731 else {
bb8c093b 732 rc = iwl4965_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 733 CSR_RESET_REG_FLAG_MASTER_DISABLED,
734 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
735 if (rc < 0) {
736 spin_unlock_irqrestore(&priv->lock, flags);
737 return rc;
738 }
739 }
740
741 spin_unlock_irqrestore(&priv->lock, flags);
742 IWL_DEBUG_INFO("stop master\n");
743
744 return rc;
745}
746
8b6eaea8
CB		 747/**
748 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
749 */
c79dd5b5 750void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c
ZY		 751{
752
753 int txq_id;
754 unsigned long flags;
755
8b6eaea8 756 /* Stop each Tx DMA channel, and wait for it to be idle */
b481de9c
ZY		 757 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
758 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 759 if (iwl4965_grab_nic_access(priv)) {
b481de9c
ZY		 760 spin_unlock_irqrestore(&priv->lock, flags);
761 continue;
762 }
763
bb8c093b 764 iwl4965_write_direct32(priv,
b481de9c
ZY		 765 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
766 0x0);
bb8c093b 767 iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
b481de9c
ZY		 768 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
769 (txq_id), 200);
bb8c093b 770 iwl4965_release_nic_access(priv);
b481de9c
ZY		 771 spin_unlock_irqrestore(&priv->lock, flags);
772 }
773
8b6eaea8 774 /* Deallocate memory for all Tx queues */
bb8c093b 775 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 776}
777
c79dd5b5 778int iwl4965_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 779{
780 int rc = 0;
781 unsigned long flags;
782
bb8c093b 783 iwl4965_hw_nic_stop_master(priv);
b481de9c
ZY		 784
785 spin_lock_irqsave(&priv->lock, flags);
786
bb8c093b 787 iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 788
789 udelay(10);
790
bb8c093b
CH		 791 iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
792 rc = iwl4965_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 793 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
794 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
795
796 udelay(10);
797
bb8c093b 798 rc = iwl4965_grab_nic_access(priv);
b481de9c 799 if (!rc) {
bb8c093b 800 iwl4965_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 801 APMG_CLK_VAL_DMA_CLK_RQT |
802 APMG_CLK_VAL_BSM_CLK_RQT);
803
804 udelay(10);
805
bb8c093b 806 iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c
ZY		 807 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
808
bb8c093b 809 iwl4965_release_nic_access(priv);
b481de9c
ZY		 810 }
811
812 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
813 wake_up_interruptible(&priv->wait_command_queue);
814
815 spin_unlock_irqrestore(&priv->lock, flags);
816
817 return rc;
818
819}
820
821#define REG_RECALIB_PERIOD (60)
822
823/**
824 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
825 *
826 * This callback is provided in order to queue the statistics_work
827 * in work_queue context (v. softirq)
828 *
829 * This timer function is continually reset to execute within
830 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
831 * was received. We need to ensure we receive the statistics in order
832 * to update the temperature used for calibrating the TXPOWER. However,
833 * we can't send the statistics command from softirq context (which
834 * is the context which timers run at) so we have to queue off the
835 * statistics_work to actually send the command to the hardware.
836 */
837static void iwl4965_bg_statistics_periodic(unsigned long data)
838{
c79dd5b5 839 struct iwl_priv *priv = (struct iwl_priv *)data;
b481de9c
ZY		 840
841 queue_work(priv->workqueue, &priv->statistics_work);
842}
843
844/**
845 * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
846 *
bb8c093b 847 * This is queued by iwl4965_bg_statistics_periodic.
b481de9c
ZY		 848 */
849static void iwl4965_bg_statistics_work(struct work_struct *work)
850{
c79dd5b5 851 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 852 statistics_work);
853
854 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
855 return;
856
857 mutex_lock(&priv->mutex);
bb8c093b 858 iwl4965_send_statistics_request(priv);
b481de9c
ZY		 859 mutex_unlock(&priv->mutex);
860}
861
862#define CT_LIMIT_CONST 259
863#define TM_CT_KILL_THRESHOLD 110
864
c79dd5b5 865void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 866{
bb8c093b 867 struct iwl4965_ct_kill_config cmd;
b481de9c
ZY		 868 u32 R1, R2, R3;
869 u32 temp_th;
870 u32 crit_temperature;
871 unsigned long flags;
857485c0 872 int ret = 0;
b481de9c
ZY		 873
874 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 875 iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 876 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
877 spin_unlock_irqrestore(&priv->lock, flags);
878
879 if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
880 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
881 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
882 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
883 } else {
884 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
885 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
886 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
887 }
888
889 temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
890
891 crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
892 cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
857485c0
TW		 893 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
894 sizeof(cmd), &cmd);
895 if (ret)
b481de9c
ZY		 896 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
897 else
898 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
899}
900
c8b0e6e1 901#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 902
903/* "false alarms" are signals that our DSP tries to lock onto,
904 * but then determines that they are either noise, or transmissions
905 * from a distant wireless network (also "noise", really) that get
906 * "stepped on" by stronger transmissions within our own network.
907 * This algorithm attempts to set a sensitivity level that is high
908 * enough to receive all of our own network traffic, but not so
909 * high that our DSP gets too busy trying to lock onto non-network
910 * activity/noise. */
c79dd5b5 911static int iwl4965_sens_energy_cck(struct iwl_priv *priv,
b481de9c
ZY		 912 u32 norm_fa,
913 u32 rx_enable_time,
914 struct statistics_general_data *rx_info)
915{
916 u32 max_nrg_cck = 0;
917 int i = 0;
918 u8 max_silence_rssi = 0;
919 u32 silence_ref = 0;
920 u8 silence_rssi_a = 0;
921 u8 silence_rssi_b = 0;
922 u8 silence_rssi_c = 0;
923 u32 val;
924
925 /* "false_alarms" values below are cross-multiplications to assess the
926 * numbers of false alarms within the measured period of actual Rx
927 * (Rx is off when we're txing), vs the min/max expected false alarms
928 * (some should be expected if rx is sensitive enough) in a
929 * hypothetical listening period of 200 time units (TU), 204.8 msec:
930 *
931 * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
932 *
933 * */
934 u32 false_alarms = norm_fa * 200 * 1024;
935 u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
936 u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
bb8c093b 937 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 938
939 data = &(priv->sensitivity_data);
940
941 data->nrg_auto_corr_silence_diff = 0;
942
943 /* Find max silence rssi among all 3 receivers.
944 * This is background noise, which may include transmissions from other
945 * networks, measured during silence before our network's beacon */
946 silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
8a1b0245 947 ALL_BAND_FILTER) >> 8);
b481de9c 948 silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
8a1b0245 949 ALL_BAND_FILTER) >> 8);
b481de9c 950 silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
8a1b0245 951 ALL_BAND_FILTER) >> 8);
b481de9c
ZY		 952
953 val = max(silence_rssi_b, silence_rssi_c);
954 max_silence_rssi = max(silence_rssi_a, (u8) val);
955
956 /* Store silence rssi in 20-beacon history table */
957 data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
958 data->nrg_silence_idx++;
959 if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
960 data->nrg_silence_idx = 0;
961
962 /* Find max silence rssi across 20 beacon history */
963 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
964 val = data->nrg_silence_rssi[i];
965 silence_ref = max(silence_ref, val);
966 }
967 IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
968 silence_rssi_a, silence_rssi_b, silence_rssi_c,
969 silence_ref);
970
971 /* Find max rx energy (min value!) among all 3 receivers,
972 * measured during beacon frame.
973 * Save it in 10-beacon history table. */
974 i = data->nrg_energy_idx;
975 val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
976 data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
977
978 data->nrg_energy_idx++;
979 if (data->nrg_energy_idx >= 10)
980 data->nrg_energy_idx = 0;
981
982 /* Find min rx energy (max value) across 10 beacon history.
983 * This is the minimum signal level that we want to receive well.
984 * Add backoff (margin so we don't miss slightly lower energy frames).
985 * This establishes an upper bound (min value) for energy threshold. */
986 max_nrg_cck = data->nrg_value[0];
987 for (i = 1; i < 10; i++)
988 max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
989 max_nrg_cck += 6;
990
991 IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
992 rx_info->beacon_energy_a, rx_info->beacon_energy_b,
993 rx_info->beacon_energy_c, max_nrg_cck - 6);
994
995 /* Count number of consecutive beacons with fewer-than-desired
996 * false alarms. */
997 if (false_alarms < min_false_alarms)
998 data->num_in_cck_no_fa++;
999 else
1000 data->num_in_cck_no_fa = 0;
1001 IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
1002 data->num_in_cck_no_fa);
1003
1004 /* If we got too many false alarms this time, reduce sensitivity */
1005 if (false_alarms > max_false_alarms) {
1006 IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
1007 false_alarms, max_false_alarms);
1008 IWL_DEBUG_CALIB("... reducing sensitivity\n");
1009 data->nrg_curr_state = IWL_FA_TOO_MANY;
1010
1011 if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
1012 /* Store for "fewer than desired" on later beacon */
1013 data->nrg_silence_ref = silence_ref;
1014
1015 /* increase energy threshold (reduce nrg value)
1016 * to decrease sensitivity */
1017 if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
1018 data->nrg_th_cck = data->nrg_th_cck
1019 - NRG_STEP_CCK;
1020 }
1021
1022 /* increase auto_corr values to decrease sensitivity */
1023 if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
1024 data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
1025 else {
1026 val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
1027 data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
1028 }
1029 val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
1030 data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
1031
1032 /* Else if we got fewer than desired, increase sensitivity */
1033 } else if (false_alarms < min_false_alarms) {
1034 data->nrg_curr_state = IWL_FA_TOO_FEW;
1035
1036 /* Compare silence level with silence level for most recent
1037 * healthy number or too many false alarms */
1038 data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
1039 (s32)silence_ref;
1040
1041 IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
1042 false_alarms, min_false_alarms,
1043 data->nrg_auto_corr_silence_diff);
1044
1045 /* Increase value to increase sensitivity, but only if:
1046 * 1a) previous beacon did *not* have *too many* false alarms
1047 * 1b) AND there's a significant difference in Rx levels
1048 * from a previous beacon with too many, or healthy # FAs
1049 * OR 2) We've seen a lot of beacons (100) with too few
1050 * false alarms */
1051 if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
1052 ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
1053 (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
1054
1055 IWL_DEBUG_CALIB("... increasing sensitivity\n");
1056 /* Increase nrg value to increase sensitivity */
1057 val = data->nrg_th_cck + NRG_STEP_CCK;
1058 data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
1059
1060 /* Decrease auto_corr values to increase sensitivity */
1061 val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
1062 data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
1063
1064 val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
1065 data->auto_corr_cck_mrc =
1066 max((u32)AUTO_CORR_MIN_CCK_MRC, val);
1067
1068 } else
1069 IWL_DEBUG_CALIB("... but not changing sensitivity\n");
1070
1071 /* Else we got a healthy number of false alarms, keep status quo */
1072 } else {
1073 IWL_DEBUG_CALIB(" FA in safe zone\n");
1074 data->nrg_curr_state = IWL_FA_GOOD_RANGE;
1075
1076 /* Store for use in "fewer than desired" with later beacon */
1077 data->nrg_silence_ref = silence_ref;
1078
1079 /* If previous beacon had too many false alarms,
1080 * give it some extra margin by reducing sensitivity again
1081 * (but don't go below measured energy of desired Rx) */
1082 if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
1083 IWL_DEBUG_CALIB("... increasing margin\n");
1084 data->nrg_th_cck -= NRG_MARGIN;
1085 }
1086 }
1087
1088 /* Make sure the energy threshold does not go above the measured
1089 * energy of the desired Rx signals (reduced by backoff margin),
1090 * or else we might start missing Rx frames.
1091 * Lower value is higher energy, so we use max()!
1092 */
1093 data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
1094 IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
1095
1096 data->nrg_prev_state = data->nrg_curr_state;
1097
1098 return 0;
1099}
1100
1101
c79dd5b5 1102static int iwl4965_sens_auto_corr_ofdm(struct iwl_priv *priv,
b481de9c
ZY		 1103 u32 norm_fa,
1104 u32 rx_enable_time)
1105{
1106 u32 val;
1107 u32 false_alarms = norm_fa * 200 * 1024;
1108 u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
1109 u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
bb8c093b 1110 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1111
1112 data = &(priv->sensitivity_data);
1113
1114 /* If we got too many false alarms this time, reduce sensitivity */
1115 if (false_alarms > max_false_alarms) {
1116
1117 IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
1118 false_alarms, max_false_alarms);
1119
1120 val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
1121 data->auto_corr_ofdm =
1122 min((u32)AUTO_CORR_MAX_OFDM, val);
1123
1124 val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
1125 data->auto_corr_ofdm_mrc =
1126 min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
1127
1128 val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
1129 data->auto_corr_ofdm_x1 =
1130 min((u32)AUTO_CORR_MAX_OFDM_X1, val);
1131
1132 val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
1133 data->auto_corr_ofdm_mrc_x1 =
1134 min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
1135 }
1136
1137 /* Else if we got fewer than desired, increase sensitivity */
1138 else if (false_alarms < min_false_alarms) {
1139
1140 IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
1141 false_alarms, min_false_alarms);
1142
1143 val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
1144 data->auto_corr_ofdm =
1145 max((u32)AUTO_CORR_MIN_OFDM, val);
1146
1147 val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
1148 data->auto_corr_ofdm_mrc =
1149 max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
1150
1151 val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
1152 data->auto_corr_ofdm_x1 =
1153 max((u32)AUTO_CORR_MIN_OFDM_X1, val);
1154
1155 val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
1156 data->auto_corr_ofdm_mrc_x1 =
1157 max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
1158 }
1159
1160 else
1161 IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
1162 min_false_alarms, false_alarms, max_false_alarms);
1163
1164 return 0;
1165}
1166
c79dd5b5 1167static int iwl4965_sensitivity_callback(struct iwl_priv *priv,
857485c0 1168 struct iwl_cmd *cmd, struct sk_buff *skb)
b481de9c
ZY		 1169{
1170 /* We didn't cache the SKB; let the caller free it */
1171 return 1;
1172}
1173
1174/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
c79dd5b5 1175static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
b481de9c 1176{
bb8c093b
CH		 1177 struct iwl4965_sensitivity_cmd cmd ;
1178 struct iwl4965_sensitivity_data *data = NULL;
857485c0 1179 struct iwl_host_cmd cmd_out = {
b481de9c 1180 .id = SENSITIVITY_CMD,
bb8c093b 1181 .len = sizeof(struct iwl4965_sensitivity_cmd),
b481de9c
ZY		 1182 .meta.flags = flags,
1183 .data = &cmd,
1184 };
857485c0 1185 int ret;
b481de9c
ZY		 1186
1187 data = &(priv->sensitivity_data);
1188
1189 memset(&cmd, 0, sizeof(cmd));
1190
1191 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
1192 cpu_to_le16((u16)data->auto_corr_ofdm);
1193 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
1194 cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
1195 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
1196 cpu_to_le16((u16)data->auto_corr_ofdm_x1);
1197 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
1198 cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
1199
1200 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
1201 cpu_to_le16((u16)data->auto_corr_cck);
1202 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
1203 cpu_to_le16((u16)data->auto_corr_cck_mrc);
1204
1205 cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
1206 cpu_to_le16((u16)data->nrg_th_cck);
1207 cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
1208 cpu_to_le16((u16)data->nrg_th_ofdm);
1209
1210 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
1211 __constant_cpu_to_le16(190);
1212 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
1213 __constant_cpu_to_le16(390);
1214 cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
1215 __constant_cpu_to_le16(62);
1216
1217 IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
1218 data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
1219 data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
1220 data->nrg_th_ofdm);
1221
1222 IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
1223 data->auto_corr_cck, data->auto_corr_cck_mrc,
1224 data->nrg_th_cck);
1225
f7d09d7c 1226 /* Update uCode's "work" table, and copy it to DSP */
b481de9c
ZY		 1227 cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
1228
1229 if (flags & CMD_ASYNC)
bb8c093b 1230 cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
b481de9c
ZY		 1231
1232 /* Don't send command to uCode if nothing has changed */
1233 if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
1234 sizeof(u16)*HD_TABLE_SIZE)) {
1235 IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
1236 return 0;
1237 }
1238
1239 /* Copy table for comparison next time */
1240 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
1241 sizeof(u16)*HD_TABLE_SIZE);
1242
857485c0
TW		 1243 ret = iwl_send_cmd(priv, &cmd_out);
1244 if (ret)
1245 IWL_ERROR("SENSITIVITY_CMD failed\n");
b481de9c 1246
857485c0 1247 return ret;
b481de9c
ZY		 1248}
1249
c79dd5b5 1250void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
b481de9c 1251{
bb8c093b 1252 struct iwl4965_sensitivity_data *data = NULL;
857485c0
TW		 1253 int i;
1254 int ret = 0;
b481de9c
ZY		 1255
1256 IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
1257
1258 if (force)
1259 memset(&(priv->sensitivity_tbl[0]), 0,
1260 sizeof(u16)*HD_TABLE_SIZE);
1261
1262 /* Clear driver's sensitivity algo data */
1263 data = &(priv->sensitivity_data);
bb8c093b 1264 memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
b481de9c
ZY		 1265
1266 data->num_in_cck_no_fa = 0;
1267 data->nrg_curr_state = IWL_FA_TOO_MANY;
1268 data->nrg_prev_state = IWL_FA_TOO_MANY;
1269 data->nrg_silence_ref = 0;
1270 data->nrg_silence_idx = 0;
1271 data->nrg_energy_idx = 0;
1272
1273 for (i = 0; i < 10; i++)
1274 data->nrg_value[i] = 0;
1275
1276 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
1277 data->nrg_silence_rssi[i] = 0;
1278
1279 data->auto_corr_ofdm = 90;
1280 data->auto_corr_ofdm_mrc = 170;
1281 data->auto_corr_ofdm_x1 = 105;
1282 data->auto_corr_ofdm_mrc_x1 = 220;
1283 data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
1284 data->auto_corr_cck_mrc = 200;
1285 data->nrg_th_cck = 100;
1286 data->nrg_th_ofdm = 100;
1287
1288 data->last_bad_plcp_cnt_ofdm = 0;
1289 data->last_fa_cnt_ofdm = 0;
1290 data->last_bad_plcp_cnt_cck = 0;
1291 data->last_fa_cnt_cck = 0;
1292
1293 /* Clear prior Sensitivity command data to force send to uCode */
1294 if (force)
1295 memset(&(priv->sensitivity_tbl[0]), 0,
1296 sizeof(u16)*HD_TABLE_SIZE);
1297
857485c0
TW		 1298 ret |= iwl4965_sensitivity_write(priv, flags);
1299 IWL_DEBUG_CALIB("<<return 0x%X\n", ret);
b481de9c
ZY		 1300
1301 return;
1302}
1303
1304
1305/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1306 * Called after every association, but this runs only once!
1307 * ... once chain noise is calibrated the first time, it's good forever. */
c79dd5b5 1308void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 1309{
bb8c093b 1310 struct iwl4965_chain_noise_data *data = NULL;
b481de9c
ZY		 1311
1312 data = &(priv->chain_noise_data);
bb8c093b
CH		 1313 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl4965_is_associated(priv)) {
1314 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1315
1316 memset(&cmd, 0, sizeof(cmd));
1317 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1318 cmd.diff_gain_a = 0;
1319 cmd.diff_gain_b = 0;
1320 cmd.diff_gain_c = 0;
857485c0 1321 iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
b481de9c
ZY		 1322 sizeof(cmd), &cmd);
1323 msleep(4);
1324 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1325 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1326 }
1327 return;
1328}
1329
1330/*
1331 * Accumulate 20 beacons of signal and noise statistics for each of
1332 * 3 receivers/antennas/rx-chains, then figure out:
1333 * 1) Which antennas are connected.
1334 * 2) Differential rx gain settings to balance the 3 receivers.
1335 */
c79dd5b5 1336static void iwl4965_noise_calibration(struct iwl_priv *priv,
bb8c093b 1337 struct iwl4965_notif_statistics *stat_resp)
b481de9c 1338{
bb8c093b 1339 struct iwl4965_chain_noise_data *data = NULL;
857485c0 1340 int ret = 0;
b481de9c
ZY		 1341
1342 u32 chain_noise_a;
1343 u32 chain_noise_b;
1344 u32 chain_noise_c;
1345 u32 chain_sig_a;
1346 u32 chain_sig_b;
1347 u32 chain_sig_c;
1348 u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1349 u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1350 u32 max_average_sig;
1351 u16 max_average_sig_antenna_i;
1352 u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
1353 u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
1354 u16 i = 0;
1355 u16 chan_num = INITIALIZATION_VALUE;
1356 u32 band = INITIALIZATION_VALUE;
1357 u32 active_chains = 0;
1358 unsigned long flags;
1359 struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
1360
1361 data = &(priv->chain_noise_data);
1362
1363 /* Accumulate just the first 20 beacons after the first association,
1364 * then we're done forever. */
1365 if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
1366 if (data->state == IWL_CHAIN_NOISE_ALIVE)
1367 IWL_DEBUG_CALIB("Wait for noise calib reset\n");
1368 return;
1369 }
1370
1371 spin_lock_irqsave(&priv->lock, flags);
1372 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1373 IWL_DEBUG_CALIB(" << Interference data unavailable\n");
1374 spin_unlock_irqrestore(&priv->lock, flags);
1375 return;
1376 }
1377
1378 band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
1379 chan_num = le16_to_cpu(priv->staging_rxon.channel);
1380
1381 /* Make sure we accumulate data for just the associated channel
1382 * (even if scanning). */
1383 if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
1384 ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
1385 (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
1386 IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
1387 chan_num, band);
1388 spin_unlock_irqrestore(&priv->lock, flags);
1389 return;
1390 }
1391
1392 /* Accumulate beacon statistics values across 20 beacons */
1393 chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
1394 IN_BAND_FILTER;
1395 chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
1396 IN_BAND_FILTER;
1397 chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
1398 IN_BAND_FILTER;
1399
1400 chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
1401 chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
1402 chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
1403
1404 spin_unlock_irqrestore(&priv->lock, flags);
1405
1406 data->beacon_count++;
1407
1408 data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
1409 data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
1410 data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
1411
1412 data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
1413 data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
1414 data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
1415
1416 IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
1417 data->beacon_count);
1418 IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
1419 chain_sig_a, chain_sig_b, chain_sig_c);
1420 IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
1421 chain_noise_a, chain_noise_b, chain_noise_c);
1422
1423 /* If this is the 20th beacon, determine:
1424 * 1) Disconnected antennas (using signal strengths)
1425 * 2) Differential gain (using silence noise) to balance receivers */
1426 if (data->beacon_count == CAL_NUM_OF_BEACONS) {
1427
1428 /* Analyze signal for disconnected antenna */
1429 average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
1430 average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
1431 average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
1432
1433 if (average_sig[0] >= average_sig[1]) {
1434 max_average_sig = average_sig[0];
1435 max_average_sig_antenna_i = 0;
1436 active_chains = (1 << max_average_sig_antenna_i);
1437 } else {
1438 max_average_sig = average_sig[1];
1439 max_average_sig_antenna_i = 1;
1440 active_chains = (1 << max_average_sig_antenna_i);
1441 }
1442
1443 if (average_sig[2] >= max_average_sig) {
1444 max_average_sig = average_sig[2];
1445 max_average_sig_antenna_i = 2;
1446 active_chains = (1 << max_average_sig_antenna_i);
1447 }
1448
1449 IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
1450 average_sig[0], average_sig[1], average_sig[2]);
1451 IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
1452 max_average_sig, max_average_sig_antenna_i);
1453
1454 /* Compare signal strengths for all 3 receivers. */
1455 for (i = 0; i < NUM_RX_CHAINS; i++) {
1456 if (i != max_average_sig_antenna_i) {
1457 s32 rssi_delta = (max_average_sig -
1458 average_sig[i]);
1459
1460 /* If signal is very weak, compared with
1461 * strongest, mark it as disconnected. */
1462 if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
1463 data->disconn_array[i] = 1;
1464 else
1465 active_chains |= (1 << i);
1466 IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
1467 "disconn_array[i] = %d\n",
1468 i, rssi_delta, data->disconn_array[i]);
1469 }
1470 }
1471
1472 /*If both chains A & B are disconnected -
1473 * connect B and leave A as is */
1474 if (data->disconn_array[CHAIN_A] &&
1475 data->disconn_array[CHAIN_B]) {
1476 data->disconn_array[CHAIN_B] = 0;
1477 active_chains |= (1 << CHAIN_B);
1478 IWL_DEBUG_CALIB("both A & B chains are disconnected! "
1479 "W/A - declare B as connected\n");
1480 }
1481
1482 IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
1483 active_chains);
1484
1485 /* Save for use within RXON, TX, SCAN commands, etc. */
1486 priv->valid_antenna = active_chains;
1487
1488 /* Analyze noise for rx balance */
1489 average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
1490 average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
1491 average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
1492
1493 for (i = 0; i < NUM_RX_CHAINS; i++) {
1494 if (!(data->disconn_array[i]) &&
1495 (average_noise[i] <= min_average_noise)) {
1496 /* This means that chain i is active and has
1497 * lower noise values so far: */
1498 min_average_noise = average_noise[i];
1499 min_average_noise_antenna_i = i;
1500 }
1501 }
1502
1503 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1504
1505 IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
1506 average_noise[0], average_noise[1],
1507 average_noise[2]);
1508
1509 IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
1510 min_average_noise, min_average_noise_antenna_i);
1511
1512 for (i = 0; i < NUM_RX_CHAINS; i++) {
1513 s32 delta_g = 0;
1514
1515 if (!(data->disconn_array[i]) &&
1516 (data->delta_gain_code[i] ==
1517 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1518 delta_g = average_noise[i] - min_average_noise;
1519 data->delta_gain_code[i] = (u8)((delta_g *
1520 10) / 15);
1521 if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
1522 data->delta_gain_code[i])
1523 data->delta_gain_code[i] =
1524 CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
1525
1526 data->delta_gain_code[i] =
1527 (data->delta_gain_code[i] | (1 << 2));
1528 } else
1529 data->delta_gain_code[i] = 0;
1530 }
1531 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1532 data->delta_gain_code[0],
1533 data->delta_gain_code[1],
1534 data->delta_gain_code[2]);
1535
1536 /* Differential gain gets sent to uCode only once */
1537 if (!data->radio_write) {
bb8c093b 1538 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1539 data->radio_write = 1;
1540
1541 memset(&cmd, 0, sizeof(cmd));
1542 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1543 cmd.diff_gain_a = data->delta_gain_code[0];
1544 cmd.diff_gain_b = data->delta_gain_code[1];
1545 cmd.diff_gain_c = data->delta_gain_code[2];
857485c0 1546 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
b481de9c 1547 sizeof(cmd), &cmd);
857485c0 1548 if (ret)
b481de9c
ZY		 1549 IWL_DEBUG_CALIB("fail sending cmd "
1550 "REPLY_PHY_CALIBRATION_CMD \n");
1551
1552 /* TODO we might want recalculate
1553 * rx_chain in rxon cmd */
1554
1555 /* Mark so we run this algo only once! */
1556 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1557 }
1558 data->chain_noise_a = 0;
1559 data->chain_noise_b = 0;
1560 data->chain_noise_c = 0;
1561 data->chain_signal_a = 0;
1562 data->chain_signal_b = 0;
1563 data->chain_signal_c = 0;
1564 data->beacon_count = 0;
1565 }
1566 return;
1567}
1568
c79dd5b5 1569static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
bb8c093b 1570 struct iwl4965_notif_statistics *resp)
b481de9c 1571{
b481de9c
ZY		 1572 u32 rx_enable_time;
1573 u32 fa_cck;
1574 u32 fa_ofdm;
1575 u32 bad_plcp_cck;
1576 u32 bad_plcp_ofdm;
1577 u32 norm_fa_ofdm;
1578 u32 norm_fa_cck;
bb8c093b 1579 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1580 struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
1581 struct statistics_rx *statistics = &(resp->rx);
1582 unsigned long flags;
1583 struct statistics_general_data statis;
857485c0 1584 int ret;
b481de9c
ZY		 1585
1586 data = &(priv->sensitivity_data);
1587
bb8c093b 1588 if (!iwl4965_is_associated(priv)) {
b481de9c
ZY		 1589 IWL_DEBUG_CALIB("<< - not associated\n");
1590 return;
1591 }
1592
1593 spin_lock_irqsave(&priv->lock, flags);
1594 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1595 IWL_DEBUG_CALIB("<< invalid data.\n");
1596 spin_unlock_irqrestore(&priv->lock, flags);
1597 return;
1598 }
1599
1600 /* Extract Statistics: */
1601 rx_enable_time = le32_to_cpu(rx_info->channel_load);
1602 fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
1603 fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
1604 bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
1605 bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
1606
1607 statis.beacon_silence_rssi_a =
1608 le32_to_cpu(statistics->general.beacon_silence_rssi_a);
1609 statis.beacon_silence_rssi_b =
1610 le32_to_cpu(statistics->general.beacon_silence_rssi_b);
1611 statis.beacon_silence_rssi_c =
1612 le32_to_cpu(statistics->general.beacon_silence_rssi_c);
1613 statis.beacon_energy_a =
1614 le32_to_cpu(statistics->general.beacon_energy_a);
1615 statis.beacon_energy_b =
1616 le32_to_cpu(statistics->general.beacon_energy_b);
1617 statis.beacon_energy_c =
1618 le32_to_cpu(statistics->general.beacon_energy_c);
1619
1620 spin_unlock_irqrestore(&priv->lock, flags);
1621
1622 IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
1623
1624 if (!rx_enable_time) {
1625 IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
1626 return;
1627 }
1628
1629 /* These statistics increase monotonically, and do not reset
1630 * at each beacon. Calculate difference from last value, or just
1631 * use the new statistics value if it has reset or wrapped around. */
1632 if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
1633 data->last_bad_plcp_cnt_cck = bad_plcp_cck;
1634 else {
1635 bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
1636 data->last_bad_plcp_cnt_cck += bad_plcp_cck;
1637 }
1638
1639 if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
1640 data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
1641 else {
1642 bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
1643 data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
1644 }
1645
1646 if (data->last_fa_cnt_ofdm > fa_ofdm)
1647 data->last_fa_cnt_ofdm = fa_ofdm;
1648 else {
1649 fa_ofdm -= data->last_fa_cnt_ofdm;
1650 data->last_fa_cnt_ofdm += fa_ofdm;
1651 }
1652
1653 if (data->last_fa_cnt_cck > fa_cck)
1654 data->last_fa_cnt_cck = fa_cck;
1655 else {
1656 fa_cck -= data->last_fa_cnt_cck;
1657 data->last_fa_cnt_cck += fa_cck;
1658 }
1659
1660 /* Total aborted signal locks */
1661 norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
1662 norm_fa_cck = fa_cck + bad_plcp_cck;
1663
1664 IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
1665 bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
1666
1667 iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
1668 iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
857485c0 1669 ret = iwl4965_sensitivity_write(priv, CMD_ASYNC);
b481de9c
ZY		 1670
1671 return;
1672}
1673
1674static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1675{
c79dd5b5 1676 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1677 sensitivity_work);
1678
1679 mutex_lock(&priv->mutex);
1680
1681 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1682 test_bit(STATUS_SCANNING, &priv->status)) {
1683 mutex_unlock(&priv->mutex);
1684 return;
1685 }
1686
1687 if (priv->start_calib) {
1688 iwl4965_noise_calibration(priv, &priv->statistics);
1689
1690 if (priv->sensitivity_data.state ==
1691 IWL_SENS_CALIB_NEED_REINIT) {
1692 iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
1693 priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
1694 } else
1695 iwl4965_sensitivity_calibration(priv,
1696 &priv->statistics);
1697 }
1698
1699 mutex_unlock(&priv->mutex);
1700 return;
1701}
c8b0e6e1 1702#endif /*CONFIG_IWL4965_SENSITIVITY*/
b481de9c
ZY		 1703
1704static void iwl4965_bg_txpower_work(struct work_struct *work)
1705{
c79dd5b5 1706 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1707 txpower_work);
1708
1709 /* If a scan happened to start before we got here
1710 * then just return; the statistics notification will
1711 * kick off another scheduled work to compensate for
1712 * any temperature delta we missed here. */
1713 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1714 test_bit(STATUS_SCANNING, &priv->status))
1715 return;
1716
1717 mutex_lock(&priv->mutex);
1718
1719 /* Regardless of if we are assocaited, we must reconfigure the
1720 * TX power since frames can be sent on non-radar channels while
1721 * not associated */
bb8c093b 1722 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 1723
1724 /* Update last_temperature to keep is_calib_needed from running
1725 * when it isn't needed... */
1726 priv->last_temperature = priv->temperature;
1727
1728 mutex_unlock(&priv->mutex);
1729}
1730
1731/*
1732 * Acquire priv->lock before calling this function !
1733 */
c79dd5b5 1734static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 1735{
bb8c093b 1736 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 1737 (index & 0xff) | (txq_id << 8));
bb8c093b 1738 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 1739}
1740
8b6eaea8
CB		 1741/**
1742 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1743 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1744 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1745 *
1746 * NOTE: Acquire priv->lock before calling this function !
b481de9c 1747 */
c79dd5b5 1748static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
bb8c093b 1749 struct iwl4965_tx_queue *txq,
b481de9c
ZY		 1750 int tx_fifo_id, int scd_retry)
1751{
1752 int txq_id = txq->q.id;
8b6eaea8
CB		 1753
1754 /* Find out whether to activate Tx queue */
b481de9c
ZY		 1755 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1756
8b6eaea8 1757 /* Set up and activate */
bb8c093b 1758 iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
b481de9c
ZY		 1759 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1760 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1761 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1762 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1763 SCD_QUEUE_STTS_REG_MSK);
1764
1765 txq->sched_retry = scd_retry;
1766
1767 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 1768 active ? "Activate" : "Deactivate",
b481de9c
ZY		 1769 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1770}
1771
1772static const u16 default_queue_to_tx_fifo[] = {
1773 IWL_TX_FIFO_AC3,
1774 IWL_TX_FIFO_AC2,
1775 IWL_TX_FIFO_AC1,
1776 IWL_TX_FIFO_AC0,
1777 IWL_CMD_FIFO_NUM,
1778 IWL_TX_FIFO_HCCA_1,
1779 IWL_TX_FIFO_HCCA_2
1780};
1781
c79dd5b5 1782static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1783{
1784 set_bit(txq_id, &priv->txq_ctx_active_msk);
1785}
1786
c79dd5b5 1787static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1788{
1789 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1790}
1791
c79dd5b5 1792int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 1793{
1794 u32 a;
1795 int i = 0;
1796 unsigned long flags;
857485c0 1797 int ret;
b481de9c
ZY		 1798
1799 spin_lock_irqsave(&priv->lock, flags);
1800
c8b0e6e1 1801#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c 1802 memset(&(priv->sensitivity_data), 0,
bb8c093b 1803 sizeof(struct iwl4965_sensitivity_data));
b481de9c 1804 memset(&(priv->chain_noise_data), 0,
bb8c093b 1805 sizeof(struct iwl4965_chain_noise_data));
b481de9c
ZY		 1806 for (i = 0; i < NUM_RX_CHAINS; i++)
1807 priv->chain_noise_data.delta_gain_code[i] =
1808 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
c8b0e6e1 1809#endif /* CONFIG_IWL4965_SENSITIVITY*/
857485c0
TW		 1810 ret = iwl4965_grab_nic_access(priv);
1811 if (ret) {
b481de9c 1812 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 1813 return ret;
b481de9c
ZY		 1814 }
1815
8b6eaea8 1816 /* Clear 4965's internal Tx Scheduler data base */
bb8c093b 1817 priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
b481de9c
ZY		 1818 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1819 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
bb8c093b 1820 iwl4965_write_targ_mem(priv, a, 0);
b481de9c 1821 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
bb8c093b 1822 iwl4965_write_targ_mem(priv, a, 0);
b481de9c 1823 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
bb8c093b 1824 iwl4965_write_targ_mem(priv, a, 0);
b481de9c 1825
8b6eaea8 1826 /* Tel 4965 where to find Tx byte count tables */
bb8c093b 1827 iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
b481de9c 1828 (priv->hw_setting.shared_phys +
bb8c093b 1829 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 1830
1831 /* Disable chain mode for all queues */
bb8c093b 1832 iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
b481de9c 1833
8b6eaea8 1834 /* Initialize each Tx queue (including the command queue) */
b481de9c 1835 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
8b6eaea8
CB		 1836
1837 /* TFD circular buffer read/write indexes */
bb8c093b
CH		 1838 iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
1839 iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 1840
1841 /* Max Tx Window size for Scheduler-ACK mode */
bb8c093b 1842 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1843 SCD_CONTEXT_QUEUE_OFFSET(i),
1844 (SCD_WIN_SIZE <<
1845 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1846 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 1847
1848 /* Frame limit */
bb8c093b 1849 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1850 SCD_CONTEXT_QUEUE_OFFSET(i) +
1851 sizeof(u32),
1852 (SCD_FRAME_LIMIT <<
1853 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1854 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1855
1856 }
bb8c093b 1857 iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
b481de9c
ZY		 1858 (1 << priv->hw_setting.max_txq_num) - 1);
1859
8b6eaea8 1860 /* Activate all Tx DMA/FIFO channels */
bb8c093b 1861 iwl4965_write_prph(priv, KDR_SCD_TXFACT,
b481de9c
ZY		 1862 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1863
1864 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 1865
1866 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 1867 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1868 int ac = default_queue_to_tx_fifo[i];
1869 iwl4965_txq_ctx_activate(priv, i);
1870 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1871 }
1872
bb8c093b 1873 iwl4965_release_nic_access(priv);
b481de9c
ZY		 1874 spin_unlock_irqrestore(&priv->lock, flags);
1875
857485c0 1876 return ret;
b481de9c
ZY		 1877}
1878
8b6eaea8
CB		 1879/**
1880 * iwl4965_hw_set_hw_setting
1881 *
1882 * Called when initializing driver
1883 */
c79dd5b5 1884int iwl4965_hw_set_hw_setting(struct iwl_priv *priv)
b481de9c 1885{
316c30d9
AK		 1886 int ret = 0;
1887
1ea87396
AK		 1888 if ((priv->cfg->mod_params->num_of_queues > IWL_MAX_NUM_QUEUES) ||
1889 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9
AK		 1890 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
1891 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
1892 ret = -EINVAL;
1893 goto out;
1894 }
1895
8b6eaea8 1896 /* Allocate area for Tx byte count tables and Rx queue status */
b481de9c
ZY		 1897 priv->hw_setting.shared_virt =
1898 pci_alloc_consistent(priv->pci_dev,
bb8c093b 1899 sizeof(struct iwl4965_shared),
b481de9c
ZY		 1900 &priv->hw_setting.shared_phys);
1901
316c30d9
AK		 1902 if (!priv->hw_setting.shared_virt) {
1903 ret = -ENOMEM;
1904 goto out;
1905 }
b481de9c 1906
bb8c093b 1907 memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
b481de9c 1908
1ea87396 1909 priv->hw_setting.max_txq_num = priv->cfg->mod_params->num_of_queues;
bb8c093b 1910 priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
b481de9c
ZY		 1911 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
1912 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 1913 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 1914 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1915 else
1916 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1917 priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
b481de9c
ZY		 1918 priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
1919 priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822
TW		 1920
1921 priv->hw_setting.tx_ant_num = 2;
1922
316c30d9
AK		 1923out:
1924 return ret;
b481de9c
ZY		 1925}
1926
1927/**
bb8c093b 1928 * iwl4965_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1929 *
1930 * Destroy all TX DMA queues and structures
1931 */
c79dd5b5 1932void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1933{
1934 int txq_id;
1935
1936 /* Tx queues */
1937 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
bb8c093b 1938 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c 1939
8b6eaea8 1940 /* Keep-warm buffer */
b481de9c
ZY		 1941 iwl4965_kw_free(priv);
1942}
1943
1944/**
8b6eaea8 1945 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
b481de9c 1946 *
8b6eaea8
CB		 1947 * Does NOT advance any TFD circular buffer read/write indexes
1948 * Does NOT free the TFD itself (which is within circular buffer)
b481de9c 1949 */
c79dd5b5 1950int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 1951{
bb8c093b
CH		 1952 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1953 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 1954 struct pci_dev *dev = priv->pci_dev;
1955 int i;
1956 int counter = 0;
1957 int index, is_odd;
1958
8b6eaea8 1959 /* Host command buffers stay mapped in memory, nothing to clean */
b481de9c 1960 if (txq->q.id == IWL_CMD_QUEUE_NUM)
b481de9c
ZY		 1961 return 0;
1962
8b6eaea8 1963 /* Sanity check on number of chunks */
b481de9c
ZY		 1964 counter = IWL_GET_BITS(*bd, num_tbs);
1965 if (counter > MAX_NUM_OF_TBS) {
1966 IWL_ERROR("Too many chunks: %i\n", counter);
1967 /* @todo issue fatal error, it is quite serious situation */
1968 return 0;
1969 }
1970
8b6eaea8
CB		 1971 /* Unmap chunks, if any.
1972 * TFD info for odd chunks is different format than for even chunks. */
b481de9c
ZY		 1973 for (i = 0; i < counter; i++) {
1974 index = i / 2;
1975 is_odd = i & 0x1;
1976
1977 if (is_odd)
1978 pci_unmap_single(
1979 dev,
1980 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1981 (IWL_GET_BITS(bd->pa[index],
1982 tb2_addr_hi20) << 16),
1983 IWL_GET_BITS(bd->pa[index], tb2_len),
1984 PCI_DMA_TODEVICE);
1985
1986 else if (i > 0)
1987 pci_unmap_single(dev,
1988 le32_to_cpu(bd->pa[index].tb1_addr),
1989 IWL_GET_BITS(bd->pa[index], tb1_len),
1990 PCI_DMA_TODEVICE);
1991
8b6eaea8 1992 /* Free SKB, if any, for this chunk */
fc4b6853
TW		 1993 if (txq->txb[txq->q.read_ptr].skb[i]) {
1994 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
b481de9c
ZY		 1995
1996 dev_kfree_skb(skb);
fc4b6853 1997 txq->txb[txq->q.read_ptr].skb[i] = NULL;
b481de9c
ZY		 1998 }
1999 }
2000 return 0;
2001}
2002
c79dd5b5 2003int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 2004{
bb8c093b 2005 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
b481de9c
ZY		 2006 return -EINVAL;
2007}
2008
2009static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
2010{
2011 s32 sign = 1;
2012
2013 if (num < 0) {
2014 sign = -sign;
2015 num = -num;
2016 }
2017 if (denom < 0) {
2018 sign = -sign;
2019 denom = -denom;
2020 }
2021 *res = 1;
2022 *res = ((num * 2 + denom) / (denom * 2)) * sign;
2023
2024 return 1;
2025}
2026
8b6eaea8
CB		 2027/**
2028 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
2029 *
2030 * Determines power supply voltage compensation for txpower calculations.
2031 * Returns number of 1/2-dB steps to subtract from gain table index,
2032 * to compensate for difference between power supply voltage during
2033 * factory measurements, vs. current power supply voltage.
2034 *
2035 * Voltage indication is higher for lower voltage.
2036 * Lower voltage requires more gain (lower gain table index).
2037 */
b481de9c
ZY		 2038static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
2039 s32 current_voltage)
2040{
2041 s32 comp = 0;
2042
2043 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
2044 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
2045 return 0;
2046
2047 iwl4965_math_div_round(current_voltage - eeprom_voltage,
2048 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
2049
2050 if (current_voltage > eeprom_voltage)
2051 comp *= 2;
2052 if ((comp < -2) || (comp > 2))
2053 comp = 0;
2054
2055 return comp;
2056}
2057
bf85ea4f 2058static const struct iwl_channel_info *
c79dd5b5 2059iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
8318d78a 2060 enum ieee80211_band band, u16 channel)
b481de9c 2061{
bf85ea4f 2062 const struct iwl_channel_info *ch_info;
b481de9c 2063
8622e705 2064 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 2065
2066 if (!is_channel_valid(ch_info))
2067 return NULL;
2068
2069 return ch_info;
2070}
2071
2072static s32 iwl4965_get_tx_atten_grp(u16 channel)
2073{
2074 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
2075 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
2076 return CALIB_CH_GROUP_5;
2077
2078 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
2079 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
2080 return CALIB_CH_GROUP_1;
2081
2082 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
2083 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
2084 return CALIB_CH_GROUP_2;
2085
2086 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
2087 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
2088 return CALIB_CH_GROUP_3;
2089
2090 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
2091 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
2092 return CALIB_CH_GROUP_4;
2093
2094 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
2095 return -1;
2096}
2097
c79dd5b5 2098static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 2099{
2100 s32 b = -1;
2101
2102 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
2103 if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
2104 continue;
2105
2106 if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
2107 && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
2108 break;
2109 }
2110
2111 return b;
2112}
2113
2114static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
2115{
2116 s32 val;
2117
2118 if (x2 == x1)
2119 return y1;
2120 else {
2121 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
2122 return val + y2;
2123 }
2124}
2125
8b6eaea8
CB		 2126/**
2127 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
2128 *
2129 * Interpolates factory measurements from the two sample channels within a
2130 * sub-band, to apply to channel of interest. Interpolation is proportional to
2131 * differences in channel frequencies, which is proportional to differences
2132 * in channel number.
2133 */
c79dd5b5 2134static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
bb8c093b 2135 struct iwl4965_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 2136{
2137 s32 s = -1;
2138 u32 c;
2139 u32 m;
bb8c093b
CH		 2140 const struct iwl4965_eeprom_calib_measure *m1;
2141 const struct iwl4965_eeprom_calib_measure *m2;
2142 struct iwl4965_eeprom_calib_measure *omeas;
b481de9c
ZY		 2143 u32 ch_i1;
2144 u32 ch_i2;
2145
2146 s = iwl4965_get_sub_band(priv, channel);
2147 if (s >= EEPROM_TX_POWER_BANDS) {
2148 IWL_ERROR("Tx Power can not find channel %d ", channel);
2149 return -1;
2150 }
2151
2152 ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
2153 ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
2154 chan_info->ch_num = (u8) channel;
2155
2156 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
2157 channel, s, ch_i1, ch_i2);
2158
2159 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
2160 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
2161 m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
2162 measurements[c][m]);
2163 m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
2164 measurements[c][m]);
2165 omeas = &(chan_info->measurements[c][m]);
2166
2167 omeas->actual_pow =
2168 (u8) iwl4965_interpolate_value(channel, ch_i1,
2169 m1->actual_pow,
2170 ch_i2,
2171 m2->actual_pow);
2172 omeas->gain_idx =
2173 (u8) iwl4965_interpolate_value(channel, ch_i1,
2174 m1->gain_idx, ch_i2,
2175 m2->gain_idx);
2176 omeas->temperature =
2177 (u8) iwl4965_interpolate_value(channel, ch_i1,
2178 m1->temperature,
2179 ch_i2,
2180 m2->temperature);
2181 omeas->pa_det =
2182 (s8) iwl4965_interpolate_value(channel, ch_i1,
2183 m1->pa_det, ch_i2,
2184 m2->pa_det);
2185
2186 IWL_DEBUG_TXPOWER
2187 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
2188 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
2189 IWL_DEBUG_TXPOWER
2190 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
2191 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
2192 IWL_DEBUG_TXPOWER
2193 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
2194 m1->pa_det, m2->pa_det, omeas->pa_det);
2195 IWL_DEBUG_TXPOWER
2196 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
2197 m1->temperature, m2->temperature,
2198 omeas->temperature);
2199 }
2200 }
2201
2202 return 0;
2203}
2204
2205/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
2206 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
2207static s32 back_off_table[] = {
2208 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
2209 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
2210 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
2211 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
2212 10 /* CCK */
2213};
2214
2215/* Thermal compensation values for txpower for various frequency ranges ...
2216 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 2217static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 2218 s32 degrees_per_05db_a;
2219 s32 degrees_per_05db_a_denom;
2220} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
2221 {9, 2}, /* group 0 5.2, ch 34-43 */
2222 {4, 1}, /* group 1 5.2, ch 44-70 */
2223 {4, 1}, /* group 2 5.2, ch 71-124 */
2224 {4, 1}, /* group 3 5.2, ch 125-200 */
2225 {3, 1} /* group 4 2.4, ch all */
2226};
2227
2228static s32 get_min_power_index(s32 rate_power_index, u32 band)
2229{
2230 if (!band) {
2231 if ((rate_power_index & 7) <= 4)
2232 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
2233 }
2234 return MIN_TX_GAIN_INDEX;
2235}
2236
2237struct gain_entry {
2238 u8 dsp;
2239 u8 radio;
2240};
2241
2242static const struct gain_entry gain_table[2][108] = {
2243 /* 5.2GHz power gain index table */
2244 {
2245 {123, 0x3F}, /* highest txpower */
2246 {117, 0x3F},
2247 {110, 0x3F},
2248 {104, 0x3F},
2249 {98, 0x3F},
2250 {110, 0x3E},
2251 {104, 0x3E},
2252 {98, 0x3E},
2253 {110, 0x3D},
2254 {104, 0x3D},
2255 {98, 0x3D},
2256 {110, 0x3C},
2257 {104, 0x3C},
2258 {98, 0x3C},
2259 {110, 0x3B},
2260 {104, 0x3B},
2261 {98, 0x3B},
2262 {110, 0x3A},
2263 {104, 0x3A},
2264 {98, 0x3A},
2265 {110, 0x39},
2266 {104, 0x39},
2267 {98, 0x39},
2268 {110, 0x38},
2269 {104, 0x38},
2270 {98, 0x38},
2271 {110, 0x37},
2272 {104, 0x37},
2273 {98, 0x37},
2274 {110, 0x36},
2275 {104, 0x36},
2276 {98, 0x36},
2277 {110, 0x35},
2278 {104, 0x35},
2279 {98, 0x35},
2280 {110, 0x34},
2281 {104, 0x34},
2282 {98, 0x34},
2283 {110, 0x33},
2284 {104, 0x33},
2285 {98, 0x33},
2286 {110, 0x32},
2287 {104, 0x32},
2288 {98, 0x32},
2289 {110, 0x31},
2290 {104, 0x31},
2291 {98, 0x31},
2292 {110, 0x30},
2293 {104, 0x30},
2294 {98, 0x30},
2295 {110, 0x25},
2296 {104, 0x25},
2297 {98, 0x25},
2298 {110, 0x24},
2299 {104, 0x24},
2300 {98, 0x24},
2301 {110, 0x23},
2302 {104, 0x23},
2303 {98, 0x23},
2304 {110, 0x22},
2305 {104, 0x18},
2306 {98, 0x18},
2307 {110, 0x17},
2308 {104, 0x17},
2309 {98, 0x17},
2310 {110, 0x16},
2311 {104, 0x16},
2312 {98, 0x16},
2313 {110, 0x15},
2314 {104, 0x15},
2315 {98, 0x15},
2316 {110, 0x14},
2317 {104, 0x14},
2318 {98, 0x14},
2319 {110, 0x13},
2320 {104, 0x13},
2321 {98, 0x13},
2322 {110, 0x12},
2323 {104, 0x08},
2324 {98, 0x08},
2325 {110, 0x07},
2326 {104, 0x07},
2327 {98, 0x07},
2328 {110, 0x06},
2329 {104, 0x06},
2330 {98, 0x06},
2331 {110, 0x05},
2332 {104, 0x05},
2333 {98, 0x05},
2334 {110, 0x04},
2335 {104, 0x04},
2336 {98, 0x04},
2337 {110, 0x03},
2338 {104, 0x03},
2339 {98, 0x03},
2340 {110, 0x02},
2341 {104, 0x02},
2342 {98, 0x02},
2343 {110, 0x01},
2344 {104, 0x01},
2345 {98, 0x01},
2346 {110, 0x00},
2347 {104, 0x00},
2348 {98, 0x00},
2349 {93, 0x00},
2350 {88, 0x00},
2351 {83, 0x00},
2352 {78, 0x00},
2353 },
2354 /* 2.4GHz power gain index table */
2355 {
2356 {110, 0x3f}, /* highest txpower */
2357 {104, 0x3f},
2358 {98, 0x3f},
2359 {110, 0x3e},
2360 {104, 0x3e},
2361 {98, 0x3e},
2362 {110, 0x3d},
2363 {104, 0x3d},
2364 {98, 0x3d},
2365 {110, 0x3c},
2366 {104, 0x3c},
2367 {98, 0x3c},
2368 {110, 0x3b},
2369 {104, 0x3b},
2370 {98, 0x3b},
2371 {110, 0x3a},
2372 {104, 0x3a},
2373 {98, 0x3a},
2374 {110, 0x39},
2375 {104, 0x39},
2376 {98, 0x39},
2377 {110, 0x38},
2378 {104, 0x38},
2379 {98, 0x38},
2380 {110, 0x37},
2381 {104, 0x37},
2382 {98, 0x37},
2383 {110, 0x36},
2384 {104, 0x36},
2385 {98, 0x36},
2386 {110, 0x35},
2387 {104, 0x35},
2388 {98, 0x35},
2389 {110, 0x34},
2390 {104, 0x34},
2391 {98, 0x34},
2392 {110, 0x33},
2393 {104, 0x33},
2394 {98, 0x33},
2395 {110, 0x32},
2396 {104, 0x32},
2397 {98, 0x32},
2398 {110, 0x31},
2399 {104, 0x31},
2400 {98, 0x31},
2401 {110, 0x30},
2402 {104, 0x30},
2403 {98, 0x30},
2404 {110, 0x6},
2405 {104, 0x6},
2406 {98, 0x6},
2407 {110, 0x5},
2408 {104, 0x5},
2409 {98, 0x5},
2410 {110, 0x4},
2411 {104, 0x4},
2412 {98, 0x4},
2413 {110, 0x3},
2414 {104, 0x3},
2415 {98, 0x3},
2416 {110, 0x2},
2417 {104, 0x2},
2418 {98, 0x2},
2419 {110, 0x1},
2420 {104, 0x1},
2421 {98, 0x1},
2422 {110, 0x0},
2423 {104, 0x0},
2424 {98, 0x0},
2425 {97, 0},
2426 {96, 0},
2427 {95, 0},
2428 {94, 0},
2429 {93, 0},
2430 {92, 0},
2431 {91, 0},
2432 {90, 0},
2433 {89, 0},
2434 {88, 0},
2435 {87, 0},
2436 {86, 0},
2437 {85, 0},
2438 {84, 0},
2439 {83, 0},
2440 {82, 0},
2441 {81, 0},
2442 {80, 0},
2443 {79, 0},
2444 {78, 0},
2445 {77, 0},
2446 {76, 0},
2447 {75, 0},
2448 {74, 0},
2449 {73, 0},
2450 {72, 0},
2451 {71, 0},
2452 {70, 0},
2453 {69, 0},
2454 {68, 0},
2455 {67, 0},
2456 {66, 0},
2457 {65, 0},
2458 {64, 0},
2459 {63, 0},
2460 {62, 0},
2461 {61, 0},
2462 {60, 0},
2463 {59, 0},
2464 }
2465};
2466
c79dd5b5 2467static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 2468 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 2469 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 2470{
2471 u8 saturation_power;
2472 s32 target_power;
2473 s32 user_target_power;
2474 s32 power_limit;
2475 s32 current_temp;
2476 s32 reg_limit;
2477 s32 current_regulatory;
2478 s32 txatten_grp = CALIB_CH_GROUP_MAX;
2479 int i;
2480 int c;
bf85ea4f 2481 const struct iwl_channel_info *ch_info = NULL;
bb8c093b
CH		 2482 struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
2483 const struct iwl4965_eeprom_calib_measure *measurement;
b481de9c
ZY		 2484 s16 voltage;
2485 s32 init_voltage;
2486 s32 voltage_compensation;
2487 s32 degrees_per_05db_num;
2488 s32 degrees_per_05db_denom;
2489 s32 factory_temp;
2490 s32 temperature_comp[2];
2491 s32 factory_gain_index[2];
2492 s32 factory_actual_pwr[2];
2493 s32 power_index;
2494
2495 /* Sanity check requested level (dBm) */
2496 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
2497 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
2498 priv->user_txpower_limit);
2499 return -EINVAL;
2500 }
2501 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
2502 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
2503 priv->user_txpower_limit);
2504 return -EINVAL;
2505 }
2506
2507 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
2508 * are used for indexing into txpower table) */
2509 user_target_power = 2 * priv->user_txpower_limit;
2510
2511 /* Get current (RXON) channel, band, width */
2512 ch_info =
8318d78a 2513 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
b481de9c
ZY		 2514
2515 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
2516 is_fat);
2517
2518 if (!ch_info)
2519 return -EINVAL;
2520
2521 /* get txatten group, used to select 1) thermal txpower adjustment
2522 * and 2) mimo txpower balance between Tx chains. */
2523 txatten_grp = iwl4965_get_tx_atten_grp(channel);
2524 if (txatten_grp < 0)
2525 return -EINVAL;
2526
2527 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
2528 channel, txatten_grp);
2529
2530 if (is_fat) {
2531 if (ctrl_chan_high)
2532 channel -= 2;
2533 else
2534 channel += 2;
2535 }
2536
2537 /* hardware txpower limits ...
2538 * saturation (clipping distortion) txpowers are in half-dBm */
2539 if (band)
2540 saturation_power = priv->eeprom.calib_info.saturation_power24;
2541 else
2542 saturation_power = priv->eeprom.calib_info.saturation_power52;
2543
2544 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
2545 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
2546 if (band)
2547 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
2548 else
2549 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
2550 }
2551
2552 /* regulatory txpower limits ... reg_limit values are in half-dBm,
2553 * max_power_avg values are in dBm, convert * 2 */
2554 if (is_fat)
2555 reg_limit = ch_info->fat_max_power_avg * 2;
2556 else
2557 reg_limit = ch_info->max_power_avg * 2;
2558
2559 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2560 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2561 if (band)
2562 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2563 else
2564 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2565 }
2566
2567 /* Interpolate txpower calibration values for this channel,
2568 * based on factory calibration tests on spaced channels. */
2569 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2570
2571 /* calculate tx gain adjustment based on power supply voltage */
2572 voltage = priv->eeprom.calib_info.voltage;
2573 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2574 voltage_compensation =
2575 iwl4965_get_voltage_compensation(voltage, init_voltage);
2576
2577 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2578 init_voltage,
2579 voltage, voltage_compensation);
2580
2581 /* get current temperature (Celsius) */
2582 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2583 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2584 current_temp = KELVIN_TO_CELSIUS(current_temp);
2585
2586 /* select thermal txpower adjustment params, based on channel group
2587 * (same frequency group used for mimo txatten adjustment) */
2588 degrees_per_05db_num =
2589 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2590 degrees_per_05db_denom =
2591 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2592
2593 /* get per-chain txpower values from factory measurements */
2594 for (c = 0; c < 2; c++) {
2595 measurement = &ch_eeprom_info.measurements[c][1];
2596
2597 /* txgain adjustment (in half-dB steps) based on difference
2598 * between factory and current temperature */
2599 factory_temp = measurement->temperature;
2600 iwl4965_math_div_round((current_temp - factory_temp) *
2601 degrees_per_05db_denom,
2602 degrees_per_05db_num,
2603 &temperature_comp[c]);
2604
2605 factory_gain_index[c] = measurement->gain_idx;
2606 factory_actual_pwr[c] = measurement->actual_pow;
2607
2608 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2609 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2610 "curr tmp %d, comp %d steps\n",
2611 factory_temp, current_temp,
2612 temperature_comp[c]);
2613
2614 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2615 factory_gain_index[c],
2616 factory_actual_pwr[c]);
2617 }
2618
2619 /* for each of 33 bit-rates (including 1 for CCK) */
2620 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2621 u8 is_mimo_rate;
bb8c093b 2622 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 2623
2624 /* for mimo, reduce each chain's txpower by half
2625 * (3dB, 6 steps), so total output power is regulatory
2626 * compliant. */
2627 if (i & 0x8) {
2628 current_regulatory = reg_limit -
2629 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2630 is_mimo_rate = 1;
2631 } else {
2632 current_regulatory = reg_limit;
2633 is_mimo_rate = 0;
2634 }
2635
2636 /* find txpower limit, either hardware or regulatory */
2637 power_limit = saturation_power - back_off_table[i];
2638 if (power_limit > current_regulatory)
2639 power_limit = current_regulatory;
2640
2641 /* reduce user's txpower request if necessary
2642 * for this rate on this channel */
2643 target_power = user_target_power;
2644 if (target_power > power_limit)
2645 target_power = power_limit;
2646
2647 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2648 i, saturation_power - back_off_table[i],
2649 current_regulatory, user_target_power,
2650 target_power);
2651
2652 /* for each of 2 Tx chains (radio transmitters) */
2653 for (c = 0; c < 2; c++) {
2654 s32 atten_value;
2655
2656 if (is_mimo_rate)
2657 atten_value =
2658 (s32)le32_to_cpu(priv->card_alive_init.
2659 tx_atten[txatten_grp][c]);
2660 else
2661 atten_value = 0;
2662
2663 /* calculate index; higher index means lower txpower */
2664 power_index = (u8) (factory_gain_index[c] -
2665 (target_power -
2666 factory_actual_pwr[c]) -
2667 temperature_comp[c] -
2668 voltage_compensation +
2669 atten_value);
2670
2671/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2672 power_index); */
2673
2674 if (power_index < get_min_power_index(i, band))
2675 power_index = get_min_power_index(i, band);
2676
2677 /* adjust 5 GHz index to support negative indexes */
2678 if (!band)
2679 power_index += 9;
2680
2681 /* CCK, rate 32, reduce txpower for CCK */
2682 if (i == POWER_TABLE_CCK_ENTRY)
2683 power_index +=
2684 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2685
2686 /* stay within the table! */
2687 if (power_index > 107) {
2688 IWL_WARNING("txpower index %d > 107\n",
2689 power_index);
2690 power_index = 107;
2691 }
2692 if (power_index < 0) {
2693 IWL_WARNING("txpower index %d < 0\n",
2694 power_index);
2695 power_index = 0;
2696 }
2697
2698 /* fill txpower command for this rate/chain */
2699 tx_power.s.radio_tx_gain[c] =
2700 gain_table[band][power_index].radio;
2701 tx_power.s.dsp_predis_atten[c] =
2702 gain_table[band][power_index].dsp;
2703
2704 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2705 "gain 0x%02x dsp %d\n",
2706 c, atten_value, power_index,
2707 tx_power.s.radio_tx_gain[c],
2708 tx_power.s.dsp_predis_atten[c]);
2709 }/* for each chain */
2710
2711 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2712
2713 }/* for each rate */
2714
2715 return 0;
2716}
2717
2718/**
bb8c093b 2719 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
b481de9c
ZY		 2720 *
2721 * Uses the active RXON for channel, band, and characteristics (fat, high)
2722 * The power limit is taken from priv->user_txpower_limit.
2723 */
c79dd5b5 2724int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 2725{
bb8c093b 2726 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 2727 int ret;
b481de9c
ZY		 2728 u8 band = 0;
2729 u8 is_fat = 0;
2730 u8 ctrl_chan_high = 0;
2731
2732 if (test_bit(STATUS_SCANNING, &priv->status)) {
2733 /* If this gets hit a lot, switch it to a BUG() and catch
2734 * the stack trace to find out who is calling this during
2735 * a scan. */
2736 IWL_WARNING("TX Power requested while scanning!\n");
2737 return -EAGAIN;
2738 }
2739
8318d78a 2740 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 2741
2742 is_fat = is_fat_channel(priv->active_rxon.flags);
2743
2744 if (is_fat &&
2745 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2746 ctrl_chan_high = 1;
2747
2748 cmd.band = band;
2749 cmd.channel = priv->active_rxon.channel;
2750
857485c0 2751 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 2752 le16_to_cpu(priv->active_rxon.channel),
2753 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 2754 if (ret)
2755 goto out;
b481de9c 2756
857485c0
TW		 2757 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2758
2759out:
2760 return ret;
b481de9c
ZY		 2761}
2762
c79dd5b5 2763int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2764{
2765 int rc;
2766 u8 band = 0;
2767 u8 is_fat = 0;
2768 u8 ctrl_chan_high = 0;
bb8c093b 2769 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 2770 const struct iwl_channel_info *ch_info;
b481de9c 2771
8318d78a 2772 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 2773
8622e705 2774 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 2775
2776 is_fat = is_fat_channel(priv->staging_rxon.flags);
2777
2778 if (is_fat &&
2779 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2780 ctrl_chan_high = 1;
2781
2782 cmd.band = band;
2783 cmd.expect_beacon = 0;
2784 cmd.channel = cpu_to_le16(channel);
2785 cmd.rxon_flags = priv->active_rxon.flags;
2786 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2787 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2788 if (ch_info)
2789 cmd.expect_beacon = is_channel_radar(ch_info);
2790 else
2791 cmd.expect_beacon = 1;
2792
2793 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2794 ctrl_chan_high, &cmd.tx_power);
2795 if (rc) {
2796 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2797 return rc;
2798 }
2799
857485c0 2800 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 2801 return rc;
2802}
2803
2804#define RTS_HCCA_RETRY_LIMIT 3
2805#define RTS_DFAULT_RETRY_LIMIT 60
2806
c79dd5b5 2807void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
857485c0 2808 struct iwl_cmd *cmd,
b481de9c
ZY		 2809 struct ieee80211_tx_control *ctrl,
2810 struct ieee80211_hdr *hdr, int sta_id,
2811 int is_hcca)
2812{
87e4f7df 2813 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
b481de9c
ZY		 2814 u8 rts_retry_limit = 0;
2815 u8 data_retry_limit = 0;
b481de9c 2816 u16 fc = le16_to_cpu(hdr->frame_control);
87e4f7df
TW		 2817 u8 rate_plcp;
2818 u16 rate_flags = 0;
8318d78a 2819 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c 2820
87e4f7df 2821 rate_plcp = iwl4965_rates[rate_idx].plcp;
b481de9c
ZY		 2822
2823 rts_retry_limit = (is_hcca) ?
2824 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2825
87e4f7df
TW		 2826 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2827 rate_flags |= RATE_MCS_CCK_MSK;
2828
2829
b481de9c
ZY		 2830 if (ieee80211_is_probe_response(fc)) {
2831 data_retry_limit = 3;
2832 if (data_retry_limit < rts_retry_limit)
2833 rts_retry_limit = data_retry_limit;
2834 } else
2835 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2836
2837 if (priv->data_retry_limit != -1)
2838 data_retry_limit = priv->data_retry_limit;
2839
87e4f7df
TW		 2840
2841 if (ieee80211_is_data(fc)) {
2842 tx->initial_rate_index = 0;
2843 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2844 } else {
b481de9c
ZY		 2845 switch (fc & IEEE80211_FCTL_STYPE) {
2846 case IEEE80211_STYPE_AUTH:
2847 case IEEE80211_STYPE_DEAUTH:
2848 case IEEE80211_STYPE_ASSOC_REQ:
2849 case IEEE80211_STYPE_REASSOC_REQ:
87e4f7df
TW		 2850 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2851 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2852 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
b481de9c
ZY		 2853 }
2854 break;
2855 default:
2856 break;
2857 }
87e4f7df
TW		 2858
2859 /* Alternate between antenna A and B for successive frames */
2860 if (priv->use_ant_b_for_management_frame) {
2861 priv->use_ant_b_for_management_frame = 0;
2862 rate_flags |= RATE_MCS_ANT_B_MSK;
2863 } else {
2864 priv->use_ant_b_for_management_frame = 1;
2865 rate_flags |= RATE_MCS_ANT_A_MSK;
2866 }
b481de9c
ZY		 2867 }
2868
87e4f7df
TW		 2869 tx->rts_retry_limit = rts_retry_limit;
2870 tx->data_retry_limit = data_retry_limit;
2871 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
b481de9c
ZY		 2872}
2873
c79dd5b5 2874int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2875{
bb8c093b 2876 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2877
2878 return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
2879}
2880
c79dd5b5 2881int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 2882{
2883 return priv->temperature;
2884}
2885
c79dd5b5 2886unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2887 struct iwl4965_frame *frame, u8 rate)
b481de9c 2888{
bb8c093b 2889 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2890 unsigned int frame_size;
2891
2892 tx_beacon_cmd = &frame->u.beacon;
2893 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2894
a4062b8f 2895 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 2896 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2897
bb8c093b 2898 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 2899 tx_beacon_cmd->frame,
bb8c093b 2900 iwl4965_broadcast_addr,
b481de9c
ZY		 2901 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2902
2903 BUG_ON(frame_size > MAX_MPDU_SIZE);
2904 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2905
2906 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2907 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2908 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 2909 else
2910 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2911 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 2912
2913 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2914 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2915 return (sizeof(*tx_beacon_cmd) + frame_size);
2916}
2917
8b6eaea8
CB		 2918/*
2919 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2920 * given Tx queue, and enable the DMA channel used for that queue.
2921 *
2922 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2923 * channels supported in hardware.
2924 */
c79dd5b5 2925int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c
ZY		 2926{
2927 int rc;
2928 unsigned long flags;
2929 int txq_id = txq->q.id;
2930
2931 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2932 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 2933 if (rc) {
2934 spin_unlock_irqrestore(&priv->lock, flags);
2935 return rc;
2936 }
2937
8b6eaea8 2938 /* Circular buffer (TFD queue in DRAM) physical base address */
bb8c093b 2939 iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
b481de9c 2940 txq->q.dma_addr >> 8);
8b6eaea8
CB		 2941
2942 /* Enable DMA channel, using same id as for TFD queue */
bb8c093b 2943 iwl4965_write_direct32(
b481de9c
ZY		 2944 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2945 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2946 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
bb8c093b 2947 iwl4965_release_nic_access(priv);
b481de9c
ZY		 2948 spin_unlock_irqrestore(&priv->lock, flags);
2949
2950 return 0;
2951}
2952
c79dd5b5 2953int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 2954 dma_addr_t addr, u16 len)
2955{
2956 int index, is_odd;
bb8c093b 2957 struct iwl4965_tfd_frame *tfd = ptr;
b481de9c
ZY		 2958 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2959
8b6eaea8 2960 /* Each TFD can point to a maximum 20 Tx buffers */
b481de9c
ZY		 2961 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2962 IWL_ERROR("Error can not send more than %d chunks\n",
2963 MAX_NUM_OF_TBS);
2964 return -EINVAL;
2965 }
2966
2967 index = num_tbs / 2;
2968 is_odd = num_tbs & 0x1;
2969
2970 if (!is_odd) {
2971 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2972 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
6a218f6f 2973 iwl_get_dma_hi_address(addr));
b481de9c
ZY		 2974 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2975 } else {
2976 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2977 (u32) (addr & 0xffff));
2978 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2979 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2980 }
2981
2982 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2983
2984 return 0;
2985}
2986
c79dd5b5 2987static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
b481de9c
ZY		 2988{
2989 u16 hw_version = priv->eeprom.board_revision_4965;
2990
2991 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2992 ((hw_version >> 8) & 0x0F),
2993 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2994
2995 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2996 priv->eeprom.board_pba_number_4965);
2997}
2998
2999#define IWL_TX_CRC_SIZE 4
3000#define IWL_TX_DELIMITER_SIZE 4
3001
8b6eaea8
CB		 3002/**
3003 * iwl4965_tx_queue_update_wr_ptr - Set up entry in Tx byte-count array
3004 */
c79dd5b5 3005int iwl4965_tx_queue_update_wr_ptr(struct iwl_priv *priv,
bb8c093b 3006 struct iwl4965_tx_queue *txq, u16 byte_cnt)
b481de9c
ZY		 3007{
3008 int len;
3009 int txq_id = txq->q.id;
bb8c093b 3010 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 3011
3012 if (txq->need_update == 0)
3013 return 0;
3014
3015 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
3016
8b6eaea8 3017 /* Set up byte count within first 256 entries */
b481de9c 3018 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 3019 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 3020
8b6eaea8 3021 /* If within first 64 entries, duplicate at end */
fc4b6853 3022 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
b481de9c 3023 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 3024 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
b481de9c
ZY		 3025 byte_cnt, len);
3026
3027 return 0;
3028}
3029
8b6eaea8
CB		 3030/**
3031 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
3032 *
3033 * Selects how many and which Rx receivers/antennas/chains to use.
3034 * This should not be used for scan command ... it puts data in wrong place.
3035 */
c79dd5b5 3036void iwl4965_set_rxon_chain(struct iwl_priv *priv)
b481de9c
ZY		 3037{
3038 u8 is_single = is_single_stream(priv);
3039 u8 idle_state, rx_state;
3040
3041 priv->staging_rxon.rx_chain = 0;
3042 rx_state = idle_state = 3;
3043
3044 /* Tell uCode which antennas are actually connected.
3045 * Before first association, we assume all antennas are connected.
3046 * Just after first association, iwl4965_noise_calibration()
3047 * checks which antennas actually *are* connected. */
3048 priv->staging_rxon.rx_chain |=
3049 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
3050
3051 /* How many receivers should we use? */
3052 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
3053 priv->staging_rxon.rx_chain |=
3054 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
3055 priv->staging_rxon.rx_chain |=
3056 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
3057
3058 if (!is_single && (rx_state >= 2) &&
3059 !test_bit(STATUS_POWER_PMI, &priv->status))
3060 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
3061 else
3062 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
3063
3064 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
3065}
3066
b481de9c
ZY		 3067/**
3068 * sign_extend - Sign extend a value using specified bit as sign-bit
3069 *
3070 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
3071 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
3072 *
3073 * @param oper value to sign extend
3074 * @param index 0 based bit index (0<=index<32) to sign bit
3075 */
3076static s32 sign_extend(u32 oper, int index)
3077{
3078 u8 shift = 31 - index;
3079
3080 return (s32)(oper << shift) >> shift;
3081}
3082
3083/**
3084 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
3085 * @statistics: Provides the temperature reading from the uCode
3086 *
3087 * A return of <0 indicates bogus data in the statistics
3088 */
c79dd5b5 3089int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 3090{
3091 s32 temperature;
3092 s32 vt;
3093 s32 R1, R2, R3;
3094 u32 R4;
3095
3096 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
3097 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
3098 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
3099 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
3100 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
3101 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
3102 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
3103 } else {
3104 IWL_DEBUG_TEMP("Running temperature calibration\n");
3105 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
3106 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
3107 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
3108 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
3109 }
3110
3111 /*
8b6eaea8 3112 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 3113 *
3114 * NOTE If we haven't received a statistics notification yet
3115 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 3116 * "initialize" ALIVE response.
3117 */
b481de9c
ZY		 3118 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
3119 vt = sign_extend(R4, 23);
3120 else
3121 vt = sign_extend(
3122 le32_to_cpu(priv->statistics.general.temperature), 23);
3123
3124 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
3125 R1, R2, R3, vt);
3126
3127 if (R3 == R1) {
3128 IWL_ERROR("Calibration conflict R1 == R3\n");
3129 return -1;
3130 }
3131
3132 /* Calculate temperature in degrees Kelvin, adjust by 97%.
3133 * Add offset to center the adjustment around 0 degrees Centigrade. */
3134 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
3135 temperature /= (R3 - R1);
3136 temperature = (temperature * 97) / 100 +
3137 TEMPERATURE_CALIB_KELVIN_OFFSET;
3138
3139 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
3140 KELVIN_TO_CELSIUS(temperature));
3141
3142 return temperature;
3143}
3144
3145/* Adjust Txpower only if temperature variance is greater than threshold. */
3146#define IWL_TEMPERATURE_THRESHOLD 3
3147
3148/**
3149 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
3150 *
3151 * If the temperature changed has changed sufficiently, then a recalibration
3152 * is needed.
3153 *
3154 * Assumes caller will replace priv->last_temperature once calibration
3155 * executed.
3156 */
c79dd5b5 3157static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 3158{
3159 int temp_diff;
3160
3161 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
3162 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
3163 return 0;
3164 }
3165
3166 temp_diff = priv->temperature - priv->last_temperature;
3167
3168 /* get absolute value */
3169 if (temp_diff < 0) {
3170 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
3171 temp_diff = -temp_diff;
3172 } else if (temp_diff == 0)
3173 IWL_DEBUG_POWER("Same temp, \n");
3174 else
3175 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
3176
3177 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
3178 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
3179 return 0;
3180 }
3181
3182 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
3183
3184 return 1;
3185}
3186
3187/* Calculate noise level, based on measurements during network silence just
3188 * before arriving beacon. This measurement can be done only if we know
3189 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 3190static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 3191{
3192 struct statistics_rx_non_phy *rx_info
3193 = &(priv->statistics.rx.general);
3194 int num_active_rx = 0;
3195 int total_silence = 0;
3196 int bcn_silence_a =
3197 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
3198 int bcn_silence_b =
3199 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
3200 int bcn_silence_c =
3201 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
3202
3203 if (bcn_silence_a) {
3204 total_silence += bcn_silence_a;
3205 num_active_rx++;
3206 }
3207 if (bcn_silence_b) {
3208 total_silence += bcn_silence_b;
3209 num_active_rx++;
3210 }
3211 if (bcn_silence_c) {
3212 total_silence += bcn_silence_c;
3213 num_active_rx++;
3214 }
3215
3216 /* Average among active antennas */
3217 if (num_active_rx)
3218 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
3219 else
3220 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3221
3222 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
3223 bcn_silence_a, bcn_silence_b, bcn_silence_c,
3224 priv->last_rx_noise);
3225}
3226
c79dd5b5 3227void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3228{
bb8c093b 3229 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3230 int change;
3231 s32 temp;
3232
3233 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
3234 (int)sizeof(priv->statistics), pkt->len);
3235
3236 change = ((priv->statistics.general.temperature !=
3237 pkt->u.stats.general.temperature) ||
3238 ((priv->statistics.flag &
3239 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
3240 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
3241
3242 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
3243
3244 set_bit(STATUS_STATISTICS, &priv->status);
3245
3246 /* Reschedule the statistics timer to occur in
3247 * REG_RECALIB_PERIOD seconds to ensure we get a
3248 * thermal update even if the uCode doesn't give
3249 * us one */
3250 mod_timer(&priv->statistics_periodic, jiffies +
3251 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
3252
3253 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3254 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
3255 iwl4965_rx_calc_noise(priv);
c8b0e6e1 3256#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 3257 queue_work(priv->workqueue, &priv->sensitivity_work);
3258#endif
3259 }
3260
ab53d8af
MA		 3261 iwl_leds_background(priv);
3262
b481de9c
ZY		 3263 /* If the hardware hasn't reported a change in
3264 * temperature then don't bother computing a
3265 * calibrated temperature value */
3266 if (!change)
3267 return;
3268
3269 temp = iwl4965_get_temperature(priv);
3270 if (temp < 0)
3271 return;
3272
3273 if (priv->temperature != temp) {
3274 if (priv->temperature)
3275 IWL_DEBUG_TEMP("Temperature changed "
3276 "from %dC to %dC\n",
3277 KELVIN_TO_CELSIUS(priv->temperature),
3278 KELVIN_TO_CELSIUS(temp));
3279 else
3280 IWL_DEBUG_TEMP("Temperature "
3281 "initialized to %dC\n",
3282 KELVIN_TO_CELSIUS(temp));
3283 }
3284
3285 priv->temperature = temp;
3286 set_bit(STATUS_TEMPERATURE, &priv->status);
3287
3288 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3289 iwl4965_is_temp_calib_needed(priv))
3290 queue_work(priv->workqueue, &priv->txpower_work);
3291}
3292
c79dd5b5 3293static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 3294 struct sk_buff *skb,
3295 struct iwl4965_rx_phy_res *rx_start,
3296 struct ieee80211_rx_status *stats,
3297 u32 ampdu_status)
3298{
3299 s8 signal = stats->ssi;
3300 s8 noise = 0;
8318d78a 3301 int rate = stats->rate_idx;
12342c47
ZY		 3302 u64 tsf = stats->mactime;
3303 __le16 phy_flags_hw = rx_start->phy_flags;
3304 struct iwl4965_rt_rx_hdr {
3305 struct ieee80211_radiotap_header rt_hdr;
3306 __le64 rt_tsf; /* TSF */
3307 u8 rt_flags; /* radiotap packet flags */
3308 u8 rt_rate; /* rate in 500kb/s */
3309 __le16 rt_channelMHz; /* channel in MHz */
3310 __le16 rt_chbitmask; /* channel bitfield */
3311 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
3312 s8 rt_dbmnoise;
3313 u8 rt_antenna; /* antenna number */
3314 } __attribute__ ((packed)) *iwl4965_rt;
3315
3316 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
3317 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
3318 if (net_ratelimit())
3319 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 3320 "radiotap head [%zd]\n",
12342c47
ZY		 3321 skb_headroom(skb), sizeof(*iwl4965_rt));
3322 return;
3323 }
3324
3325 /* put radiotap header in front of 802.11 header and data */
3326 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
3327
3328 /* initialise radiotap header */
3329 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
3330 iwl4965_rt->rt_hdr.it_pad = 0;
3331
3332 /* total header + data */
3333 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
3334 &iwl4965_rt->rt_hdr.it_len);
3335
3336 /* Indicate all the fields we add to the radiotap header */
3337 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
3338 (1 << IEEE80211_RADIOTAP_FLAGS) |
3339 (1 << IEEE80211_RADIOTAP_RATE) |
3340 (1 << IEEE80211_RADIOTAP_CHANNEL) |
3341 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
3342 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
3343 (1 << IEEE80211_RADIOTAP_ANTENNA)),
3344 &iwl4965_rt->rt_hdr.it_present);
3345
3346 /* Zero the flags, we'll add to them as we go */
3347 iwl4965_rt->rt_flags = 0;
3348
3349 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
3350
3351 iwl4965_rt->rt_dbmsignal = signal;
3352 iwl4965_rt->rt_dbmnoise = noise;
3353
3354 /* Convert the channel frequency and set the flags */
3355 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
3356 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
3357 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3358 IEEE80211_CHAN_5GHZ),
3359 &iwl4965_rt->rt_chbitmask);
3360 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
3361 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
3362 IEEE80211_CHAN_2GHZ),
3363 &iwl4965_rt->rt_chbitmask);
3364 else /* 802.11g */
3365 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3366 IEEE80211_CHAN_2GHZ),
3367 &iwl4965_rt->rt_chbitmask);
3368
12342c47
ZY		 3369 if (rate == -1)
3370 iwl4965_rt->rt_rate = 0;
3371 else
3372 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
3373
3374 /*
3375 * "antenna number"
3376 *
3377 * It seems that the antenna field in the phy flags value
3378 * is actually a bitfield. This is undefined by radiotap,
3379 * it wants an actual antenna number but I always get "7"
3380 * for most legacy frames I receive indicating that the
3381 * same frame was received on all three RX chains.
3382 *
3383 * I think this field should be removed in favour of a
3384 * new 802.11n radiotap field "RX chains" that is defined
3385 * as a bitmask.
3386 */
3387 iwl4965_rt->rt_antenna =
3388 le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
3389
3390 /* set the preamble flag if appropriate */
3391 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
3392 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3393
3394 stats->flag |= RX_FLAG_RADIOTAP;
3395}
3396
19758bef
TW		 3397static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
3398{
3399 /* 0 - mgmt, 1 - cnt, 2 - data */
3400 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
3401 priv->rx_stats[idx].cnt++;
3402 priv->rx_stats[idx].bytes += len;
3403}
3404
17e476b8
EG		 3405static u32 iwl4965_translate_rx_status(u32 decrypt_in)
3406{
3407 u32 decrypt_out = 0;
3408
3409 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
3410 RX_RES_STATUS_STATION_FOUND)
3411 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
3412 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
3413
3414 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
3415
3416 /* packet was not encrypted */
3417 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3418 RX_RES_STATUS_SEC_TYPE_NONE)
3419 return decrypt_out;
3420
3421 /* packet was encrypted with unknown alg */
3422 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3423 RX_RES_STATUS_SEC_TYPE_ERR)
3424 return decrypt_out;
3425
3426 /* decryption was not done in HW */
3427 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
3428 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
3429 return decrypt_out;
3430
3431 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
3432
3433 case RX_RES_STATUS_SEC_TYPE_CCMP:
3434 /* alg is CCM: check MIC only */
3435 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
3436 /* Bad MIC */
3437 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3438 else
3439 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3440
3441 break;
3442
3443 case RX_RES_STATUS_SEC_TYPE_TKIP:
3444 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
3445 /* Bad TTAK */
3446 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
3447 break;
3448 }
3449 /* fall through if TTAK OK */
3450 default:
3451 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
3452 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3453 else
3454 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3455 break;
3456 };
3457
3458 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
3459 decrypt_in, decrypt_out);
3460
3461 return decrypt_out;
3462}
3463
c79dd5b5 3464static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 3465 int include_phy,
bb8c093b 3466 struct iwl4965_rx_mem_buffer *rxb,
b481de9c
ZY		 3467 struct ieee80211_rx_status *stats)
3468{
bb8c093b 3469 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3470 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3471 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3472 struct ieee80211_hdr *hdr;
3473 u16 len;
3474 __le32 *rx_end;
3475 unsigned int skblen;
3476 u32 ampdu_status;
17e476b8 3477 u32 ampdu_status_legacy;
b481de9c
ZY		 3478
3479 if (!include_phy && priv->last_phy_res[0])
3480 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3481
3482 if (!rx_start) {
3483 IWL_ERROR("MPDU frame without a PHY data\n");
3484 return;
3485 }
3486 if (include_phy) {
3487 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3488 rx_start->cfg_phy_cnt);
3489
3490 len = le16_to_cpu(rx_start->byte_count);
3491
3492 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3493 sizeof(struct iwl4965_rx_phy_res) +
3494 rx_start->cfg_phy_cnt + len);
3495
3496 } else {
3497 struct iwl4965_rx_mpdu_res_start *amsdu =
3498 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3499
3500 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3501 sizeof(struct iwl4965_rx_mpdu_res_start));
3502 len = le16_to_cpu(amsdu->byte_count);
3503 rx_start->byte_count = amsdu->byte_count;
3504 rx_end = (__le32 *) (((u8 *) hdr) + len);
3505 }
9ee1ba47 3506 if (len > priv->hw_setting.max_pkt_size || len < 16) {
12342c47 3507 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 3508 return;
3509 }
3510
3511 ampdu_status = le32_to_cpu(*rx_end);
3512 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3513
17e476b8
EG		 3514 if (!include_phy) {
3515 /* New status scheme, need to translate */
3516 ampdu_status_legacy = ampdu_status;
3517 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3518 }
3519
b481de9c
ZY		 3520 /* start from MAC */
3521 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3522 skb_put(rxb->skb, len); /* end where data ends */
3523
3524 /* We only process data packets if the interface is open */
3525 if (unlikely(!priv->is_open)) {
3526 IWL_DEBUG_DROP_LIMIT
3527 ("Dropping packet while interface is not open.\n");
3528 return;
3529 }
3530
b481de9c
ZY		 3531 stats->flag = 0;
3532 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3533
1ea87396 3534 if (priv->cfg->mod_params->hw_crypto)
bb8c093b 3535 iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
b481de9c 3536
12342c47
ZY		 3537 if (priv->add_radiotap)
3538 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3539
19758bef 3540 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 3541 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3542 priv->alloc_rxb_skb--;
3543 rxb->skb = NULL;
b481de9c
ZY		 3544}
3545
3546/* Calc max signal level (dBm) among 3 possible receivers */
3547static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3548{
3549 /* data from PHY/DSP regarding signal strength, etc.,
3550 * contents are always there, not configurable by host. */
3551 struct iwl4965_rx_non_cfg_phy *ncphy =
3552 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3553 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3554 >> IWL_AGC_DB_POS;
3555
3556 u32 valid_antennae =
3557 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3558 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3559 u8 max_rssi = 0;
3560 u32 i;
3561
3562 /* Find max rssi among 3 possible receivers.
3563 * These values are measured by the digital signal processor (DSP).
3564 * They should stay fairly constant even as the signal strength varies,
3565 * if the radio's automatic gain control (AGC) is working right.
3566 * AGC value (see below) will provide the "interesting" info. */
3567 for (i = 0; i < 3; i++)
3568 if (valid_antennae & (1 << i))
3569 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3570
3571 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3572 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3573 max_rssi, agc);
3574
3575 /* dBm = max_rssi dB - agc dB - constant.
3576 * Higher AGC (higher radio gain) means lower signal. */
3577 return (max_rssi - agc - IWL_RSSI_OFFSET);
3578}
3579
c8b0e6e1 3580#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 3581
3582/* Parsed Information Elements */
3583struct ieee802_11_elems {
3584 u8 *ds_params;
3585 u8 ds_params_len;
3586 u8 *tim;
3587 u8 tim_len;
3588 u8 *ibss_params;
3589 u8 ibss_params_len;
3590 u8 *erp_info;
3591 u8 erp_info_len;
3592 u8 *ht_cap_param;
3593 u8 ht_cap_param_len;
3594 u8 *ht_extra_param;
3595 u8 ht_extra_param_len;
3596};
3597
3598static int parse_elems(u8 *start, size_t len, struct ieee802_11_elems *elems)
3599{
3600 size_t left = len;
3601 u8 *pos = start;
3602 int unknown = 0;
3603
3604 memset(elems, 0, sizeof(*elems));
3605
3606 while (left >= 2) {
3607 u8 id, elen;
3608
3609 id = *pos++;
3610 elen = *pos++;
3611 left -= 2;
3612
3613 if (elen > left)
3614 return -1;
3615
3616 switch (id) {
3617 case WLAN_EID_DS_PARAMS:
3618 elems->ds_params = pos;
3619 elems->ds_params_len = elen;
3620 break;
3621 case WLAN_EID_TIM:
3622 elems->tim = pos;
3623 elems->tim_len = elen;
3624 break;
3625 case WLAN_EID_IBSS_PARAMS:
3626 elems->ibss_params = pos;
3627 elems->ibss_params_len = elen;
3628 break;
3629 case WLAN_EID_ERP_INFO:
3630 elems->erp_info = pos;
3631 elems->erp_info_len = elen;
3632 break;
3633 case WLAN_EID_HT_CAPABILITY:
3634 elems->ht_cap_param = pos;
3635 elems->ht_cap_param_len = elen;
3636 break;
3637 case WLAN_EID_HT_EXTRA_INFO:
3638 elems->ht_extra_param = pos;
3639 elems->ht_extra_param_len = elen;
3640 break;
3641 default:
3642 unknown++;
3643 break;
3644 }
3645
3646 left -= elen;
3647 pos += elen;
3648 }
3649
3650 return 0;
3651}
326eeee8 3652
1ea87396
AK		 3653void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
3654 struct ieee80211_ht_info *ht_info,
78330fdd 3655 enum ieee80211_band band)
326eeee8
RR		 3656{
3657 ht_info->cap = 0;
3658 memset(ht_info->supp_mcs_set, 0, 16);
3659
3660 ht_info->ht_supported = 1;
3661
78330fdd 3662 if (band == IEEE80211_BAND_5GHZ) {
326eeee8
RR		 3663 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3664 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3665 ht_info->supp_mcs_set[4] = 0x01;
3666 }
3667 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3668 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3669 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3670 (IWL_MIMO_PS_NONE << 2));
1ea87396
AK		 3671
3672 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47 3673 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
326eeee8
RR		 3674
3675 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3676 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3677
3678 ht_info->supp_mcs_set[0] = 0xFF;
3679 ht_info->supp_mcs_set[1] = 0xFF;
3680}
c8b0e6e1 3681#endif /* CONFIG_IWL4965_HT */
b481de9c 3682
c79dd5b5 3683static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 3684{
3685 unsigned long flags;
3686
3687 spin_lock_irqsave(&priv->sta_lock, flags);
3688 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3689 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3690 priv->stations[sta_id].sta.sta.modify_mask = 0;
3691 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3692 spin_unlock_irqrestore(&priv->sta_lock, flags);
3693
bb8c093b 3694 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3695}
3696
c79dd5b5 3697static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 3698{
3699 /* FIXME: need locking over ps_status ??? */
bb8c093b 3700 u8 sta_id = iwl4965_hw_find_station(priv, addr);
b481de9c
ZY		 3701
3702 if (sta_id != IWL_INVALID_STATION) {
3703 u8 sta_awake = priv->stations[sta_id].
3704 ps_status == STA_PS_STATUS_WAKE;
3705
3706 if (sta_awake && ps_bit)
3707 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3708 else if (!sta_awake && !ps_bit) {
3709 iwl4965_sta_modify_ps_wake(priv, sta_id);
3710 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3711 }
3712 }
3713}
0a6857e7 3714#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 3715
3716/**
3717 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3718 *
3719 * You may hack this function to show different aspects of received frames,
3720 * including selective frame dumps.
3721 * group100 parameter selects whether to show 1 out of 100 good frames.
3722 *
3723 * TODO: This was originally written for 3945, need to audit for
3724 * proper operation with 4965.
3725 */
c79dd5b5 3726static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3727 struct iwl4965_rx_packet *pkt,
3728 struct ieee80211_hdr *header, int group100)
3729{
3730 u32 to_us;
3731 u32 print_summary = 0;
3732 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3733 u32 hundred = 0;
3734 u32 dataframe = 0;
3735 u16 fc;
3736 u16 seq_ctl;
3737 u16 channel;
3738 u16 phy_flags;
3739 int rate_sym;
3740 u16 length;
3741 u16 status;
3742 u16 bcn_tmr;
3743 u32 tsf_low;
3744 u64 tsf;
3745 u8 rssi;
3746 u8 agc;
3747 u16 sig_avg;
3748 u16 noise_diff;
3749 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3750 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3751 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3752 u8 *data = IWL_RX_DATA(pkt);
3753
0a6857e7 3754 if (likely(!(iwl_debug_level & IWL_DL_RX)))
17744ff6
TW		 3755 return;
3756
3757 /* MAC header */
3758 fc = le16_to_cpu(header->frame_control);
3759 seq_ctl = le16_to_cpu(header->seq_ctrl);
3760
3761 /* metadata */
3762 channel = le16_to_cpu(rx_hdr->channel);
3763 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3764 rate_sym = rx_hdr->rate;
3765 length = le16_to_cpu(rx_hdr->len);
3766
3767 /* end-of-frame status and timestamp */
3768 status = le32_to_cpu(rx_end->status);
3769 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3770 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3771 tsf = le64_to_cpu(rx_end->timestamp);
3772
3773 /* signal statistics */
3774 rssi = rx_stats->rssi;
3775 agc = rx_stats->agc;
3776 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3777 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3778
3779 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3780
3781 /* if data frame is to us and all is good,
3782 * (optionally) print summary for only 1 out of every 100 */
3783 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3784 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3785 dataframe = 1;
3786 if (!group100)
3787 print_summary = 1; /* print each frame */
3788 else if (priv->framecnt_to_us < 100) {
3789 priv->framecnt_to_us++;
3790 print_summary = 0;
3791 } else {
3792 priv->framecnt_to_us = 0;
3793 print_summary = 1;
3794 hundred = 1;
3795 }
3796 } else {
3797 /* print summary for all other frames */
3798 print_summary = 1;
3799 }
3800
3801 if (print_summary) {
3802 char *title;
3803 int rate_idx;
3804 u32 bitrate;
3805
3806 if (hundred)
3807 title = "100Frames";
3808 else if (fc & IEEE80211_FCTL_RETRY)
3809 title = "Retry";
3810 else if (ieee80211_is_assoc_response(fc))
3811 title = "AscRsp";
3812 else if (ieee80211_is_reassoc_response(fc))
3813 title = "RasRsp";
3814 else if (ieee80211_is_probe_response(fc)) {
3815 title = "PrbRsp";
3816 print_dump = 1; /* dump frame contents */
3817 } else if (ieee80211_is_beacon(fc)) {
3818 title = "Beacon";
3819 print_dump = 1; /* dump frame contents */
3820 } else if (ieee80211_is_atim(fc))
3821 title = "ATIM";
3822 else if (ieee80211_is_auth(fc))
3823 title = "Auth";
3824 else if (ieee80211_is_deauth(fc))
3825 title = "DeAuth";
3826 else if (ieee80211_is_disassoc(fc))
3827 title = "DisAssoc";
3828 else
3829 title = "Frame";
3830
3831 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3832 if (unlikely(rate_idx == -1))
3833 bitrate = 0;
3834 else
3835 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3836
3837 /* print frame summary.
3838 * MAC addresses show just the last byte (for brevity),
3839 * but you can hack it to show more, if you'd like to. */
3840 if (dataframe)
3841 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3842 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3843 title, fc, header->addr1[5],
3844 length, rssi, channel, bitrate);
3845 else {
3846 /* src/dst addresses assume managed mode */
3847 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3848 "src=0x%02x, rssi=%u, tim=%lu usec, "
3849 "phy=0x%02x, chnl=%d\n",
3850 title, fc, header->addr1[5],
3851 header->addr3[5], rssi,
3852 tsf_low - priv->scan_start_tsf,
3853 phy_flags, channel);
3854 }
3855 }
3856 if (print_dump)
0a6857e7 3857 iwl_print_hex_dump(IWL_DL_RX, data, length);
17744ff6
TW		 3858}
3859#else
c79dd5b5 3860static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3861 struct iwl4965_rx_packet *pkt,
3862 struct ieee80211_hdr *header,
3863 int group100)
3864{
3865}
3866#endif
3867
b481de9c 3868
7878a5a4
MA		 3869#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
3870
857485c0 3871/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 3872 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
c79dd5b5 3873static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
bb8c093b 3874 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3875{
17744ff6
TW		 3876 struct ieee80211_hdr *header;
3877 struct ieee80211_rx_status rx_status;
bb8c093b 3878 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3879 /* Use phy data (Rx signal strength, etc.) contained within
3880 * this rx packet for legacy frames,
3881 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 3882 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 3883 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3884 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3885 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3886 __le32 *rx_end;
3887 unsigned int len = 0;
b481de9c 3888 u16 fc;
b481de9c
ZY		 3889 u8 network_packet;
3890
17744ff6
TW		 3891 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
3892 rx_status.freq = ieee80211chan2mhz(le16_to_cpu(rx_start->channel));
3893 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3894 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
3895 rx_status.rate_idx = iwl4965_hwrate_to_plcp_idx(
3896 le32_to_cpu(rx_start->rate_n_flags));
3897
3898 if (rx_status.band == IEEE80211_BAND_5GHZ)
3899 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3900
3901 rx_status.antenna = 0;
3902 rx_status.flag = 0;
3903
b481de9c
ZY		 3904 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3905 IWL_DEBUG_DROP
3906 ("dsp size out of range [0,20]: "
3907 "%d/n", rx_start->cfg_phy_cnt);
3908 return;
3909 }
17744ff6 3910
b481de9c
ZY		 3911 if (!include_phy) {
3912 if (priv->last_phy_res[0])
3913 rx_start = (struct iwl4965_rx_phy_res *)
3914 &priv->last_phy_res[1];
3915 else
3916 rx_start = NULL;
3917 }
3918
3919 if (!rx_start) {
3920 IWL_ERROR("MPDU frame without a PHY data\n");
3921 return;
3922 }
3923
3924 if (include_phy) {
3925 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3926 + rx_start->cfg_phy_cnt);
3927
3928 len = le16_to_cpu(rx_start->byte_count);
17744ff6 3929 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 3930 sizeof(struct iwl4965_rx_phy_res) + len);
3931 } else {
3932 struct iwl4965_rx_mpdu_res_start *amsdu =
3933 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3934
3935 header = (void *)(pkt->u.raw +
3936 sizeof(struct iwl4965_rx_mpdu_res_start));
3937 len = le16_to_cpu(amsdu->byte_count);
3938 rx_end = (__le32 *) (pkt->u.raw +
3939 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3940 }
3941
3942 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3943 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3944 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3945 le32_to_cpu(*rx_end));
3946 return;
3947 }
3948
3949 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3950
b481de9c 3951 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
17744ff6 3952 rx_status.ssi = iwl4965_calc_rssi(rx_start);
b481de9c
ZY		 3953
3954 /* Meaningful noise values are available only from beacon statistics,
3955 * which are gathered only when associated, and indicate noise
3956 * only for the associated network channel ...
3957 * Ignore these noise values while scanning (other channels) */
bb8c093b 3958 if (iwl4965_is_associated(priv) &&
b481de9c 3959 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6
TW		 3960 rx_status.noise = priv->last_rx_noise;
3961 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3962 rx_status.noise);
b481de9c 3963 } else {
17744ff6
TW		 3964 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3965 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
b481de9c
ZY		 3966 }
3967
3968 /* Reset beacon noise level if not associated. */
bb8c093b 3969 if (!iwl4965_is_associated(priv))
b481de9c
ZY		 3970 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3971
17744ff6
TW		 3972 /* Set "1" to report good data frames in groups of 100 */
3973 /* FIXME: need to optimze the call: */
3974 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3975
3976 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3977 rx_status.ssi, rx_status.noise, rx_status.signal,
3978 rx_status.mactime);
b481de9c 3979
bb8c093b 3980 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 3981 if (network_packet) {
17744ff6 3982 priv->last_rx_rssi = rx_status.ssi;
b481de9c
ZY		 3983 priv->last_beacon_time = priv->ucode_beacon_time;
3984 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3985 }
3986
3987 fc = le16_to_cpu(header->frame_control);
3988 switch (fc & IEEE80211_FCTL_FTYPE) {
3989 case IEEE80211_FTYPE_MGMT:
3990
3991 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3992 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3993 header->addr2);
3994 switch (fc & IEEE80211_FCTL_STYPE) {
3995 case IEEE80211_STYPE_PROBE_RESP:
3996 case IEEE80211_STYPE_BEACON:
3997 if ((priv->iw_mode == IEEE80211_IF_TYPE_STA &&
3998 !compare_ether_addr(header->addr2, priv->bssid)) ||
3999 (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
4000 !compare_ether_addr(header->addr3, priv->bssid))) {
4001 struct ieee80211_mgmt *mgmt =
4002 (struct ieee80211_mgmt *)header;
4003 u64 timestamp =
4004 le64_to_cpu(mgmt->u.beacon.timestamp);
4005
4006 priv->timestamp0 = timestamp & 0xFFFFFFFF;
4007 priv->timestamp1 =
4008 (timestamp >> 32) & 0xFFFFFFFF;
4009 priv->beacon_int = le16_to_cpu(
4010 mgmt->u.beacon.beacon_int);
4011 if (priv->call_post_assoc_from_beacon &&
4012 (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
4013 priv->call_post_assoc_from_beacon = 0;
4014 queue_work(priv->workqueue,
4015 &priv->post_associate.work);
4016 }
4017 }
4018 break;
4019
4020 case IEEE80211_STYPE_ACTION:
4021 break;
4022
4023 /*
471b3efd
JB		 4024 * TODO: Use the new callback function from
4025 * mac80211 instead of sniffing these packets.
b481de9c
ZY		 4026 */
4027 case IEEE80211_STYPE_ASSOC_RESP:
4028 case IEEE80211_STYPE_REASSOC_RESP:
052c4b9f 4029 if (network_packet) {
c8b0e6e1 4030#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 4031 u8 *pos = NULL;
4032 struct ieee802_11_elems elems;
c8b0e6e1 4033#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 4034 struct ieee80211_mgmt *mgnt =
4035 (struct ieee80211_mgmt *)header;
4036
7878a5a4
MA		 4037 /* We have just associated, give some
4038 * time for the 4-way handshake if
4039 * any. Don't start scan too early. */
4040 priv->next_scan_jiffies = jiffies +
4041 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
4042
b481de9c
ZY		 4043 priv->assoc_id = (~((1 << 15) | (1 << 14))
4044 & le16_to_cpu(mgnt->u.assoc_resp.aid));
4045 priv->assoc_capability =
4046 le16_to_cpu(
4047 mgnt->u.assoc_resp.capab_info);
c8b0e6e1 4048#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 4049 pos = mgnt->u.assoc_resp.variable;
4050 if (!parse_elems(pos,
4051 len - (pos - (u8 *) mgnt),
4052 &elems)) {
4053 if (elems.ht_extra_param &&
4054 elems.ht_cap_param)
4055 break;
4056 }
c8b0e6e1 4057#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 4058 /* assoc_id is 0 no association */
4059 if (!priv->assoc_id)
4060 break;
4061 if (priv->beacon_int)
4062 queue_work(priv->workqueue,
4063 &priv->post_associate.work);
4064 else
4065 priv->call_post_assoc_from_beacon = 1;
4066 }
4067
4068 break;
4069
4070 case IEEE80211_STYPE_PROBE_REQ:
4071 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
bb8c093b 4072 !iwl4965_is_associated(priv)) {
0795af57
JP		 4073 DECLARE_MAC_BUF(mac1);
4074 DECLARE_MAC_BUF(mac2);
4075 DECLARE_MAC_BUF(mac3);
4076
b481de9c 4077 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 4078 "%s, %s, %s\n",
4079 print_mac(mac1, header->addr1),
4080 print_mac(mac2, header->addr2),
4081 print_mac(mac3, header->addr3));
b481de9c
ZY		 4082 return;
4083 }
4084 }
17744ff6 4085 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 4086 break;
4087
4088 case IEEE80211_FTYPE_CTL:
9ab46173 4089#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 4090 switch (fc & IEEE80211_FCTL_STYPE) {
4091 case IEEE80211_STYPE_BACK_REQ:
4092 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
4093 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 4094 rxb, &rx_status);
b481de9c
ZY		 4095 break;
4096 default:
4097 break;
4098 }
4099#endif
b481de9c
ZY		 4100 break;
4101
0795af57
JP		 4102 case IEEE80211_FTYPE_DATA: {
4103 DECLARE_MAC_BUF(mac1);
4104 DECLARE_MAC_BUF(mac2);
4105 DECLARE_MAC_BUF(mac3);
4106
b481de9c
ZY		 4107 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4108 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4109 header->addr2);
4110
4111 if (unlikely(!network_packet))
4112 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 4113 "%s, %s, %s\n",
4114 print_mac(mac1, header->addr1),
4115 print_mac(mac2, header->addr2),
4116 print_mac(mac3, header->addr3));
bb8c093b 4117 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 4118 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
4119 print_mac(mac1, header->addr1),
4120 print_mac(mac2, header->addr2),
4121 print_mac(mac3, header->addr3));
b481de9c
ZY		 4122 else
4123 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 4124 &rx_status);
b481de9c 4125 break;
0795af57 4126 }
b481de9c
ZY		 4127 default:
4128 break;
4129
4130 }
4131}
4132
4133/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
4134 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
c79dd5b5 4135static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
bb8c093b 4136 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4137{
bb8c093b 4138 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 4139 priv->last_phy_res[0] = 1;
4140 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
4141 sizeof(struct iwl4965_rx_phy_res));
4142}
4143
c79dd5b5 4144static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
bb8c093b 4145 struct iwl4965_rx_mem_buffer *rxb)
b481de9c
ZY		 4146
4147{
c8b0e6e1 4148#ifdef CONFIG_IWL4965_SENSITIVITY
bb8c093b
CH		 4149 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4150 struct iwl4965_missed_beacon_notif *missed_beacon;
b481de9c
ZY		 4151
4152 missed_beacon = &pkt->u.missed_beacon;
4153 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
4154 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
4155 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
4156 le32_to_cpu(missed_beacon->total_missed_becons),
4157 le32_to_cpu(missed_beacon->num_recvd_beacons),
4158 le32_to_cpu(missed_beacon->num_expected_beacons));
4159 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
4160 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
4161 queue_work(priv->workqueue, &priv->sensitivity_work);
4162 }
c8b0e6e1 4163#endif /*CONFIG_IWL4965_SENSITIVITY*/
b481de9c
ZY		 4164}
4165
c8b0e6e1 4166#ifdef CONFIG_IWL4965_HT
b481de9c 4167
8b6eaea8
CB		 4168/**
4169 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
4170 */
c79dd5b5 4171static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
b481de9c
ZY		 4172 int sta_id, int tid)
4173{
4174 unsigned long flags;
4175
8b6eaea8 4176 /* Remove "disable" flag, to enable Tx for this TID */
b481de9c
ZY		 4177 spin_lock_irqsave(&priv->sta_lock, flags);
4178 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
4179 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
4180 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4181 spin_unlock_irqrestore(&priv->sta_lock, flags);
4182
bb8c093b 4183 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4184}
4185
8b6eaea8
CB		 4186/**
4187 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
4188 *
4189 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
4190 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
4191 */
c79dd5b5 4192static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b
CH		 4193 struct iwl4965_ht_agg *agg,
4194 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 4195 ba_resp)
4196
4197{
4198 int i, sh, ack;
fe01b477
RR		 4199 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
4200 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
4201 u64 bitmap;
4202 int successes = 0;
4203 struct ieee80211_tx_status *tx_status;
b481de9c
ZY		 4204
4205 if (unlikely(!agg->wait_for_ba)) {
4206 IWL_ERROR("Received BA when not expected\n");
4207 return -EINVAL;
4208 }
8b6eaea8
CB		 4209
4210 /* Mark that the expected block-ack response arrived */
b481de9c 4211 agg->wait_for_ba = 0;
fe01b477 4212 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 4213
4214 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 4215 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 4216 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 4217 sh += 0x100;
4218
8b6eaea8 4219 /* don't use 64-bit values for now */
fe01b477 4220 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 4221
4222 if (agg->frame_count > (64 - sh)) {
4223 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
4224 return -1;
4225 }
4226
4227 /* check for success or failure according to the
8b6eaea8 4228 * transmitted bitmap and block-ack bitmap */
fe01b477 4229 bitmap &= agg->bitmap;
b481de9c 4230
8b6eaea8
CB		 4231 /* For each frame attempted in aggregation,
4232 * update driver's record of tx frame's status. */
b481de9c 4233 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 4234 ack = bitmap & (1 << i);
4235 successes += !!ack;
b481de9c 4236 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 4237 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
4238 agg->start_idx + i);
4239 }
4240
4241 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
4242 tx_status->flags = IEEE80211_TX_STATUS_ACK;
99556438
RR		 4243 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
4244 tx_status->ampdu_ack_map = successes;
4245 tx_status->ampdu_ack_len = agg->frame_count;
4c424e4c
RR		 4246 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
4247 &tx_status->control);
fe01b477 4248
f868f4e1 4249 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 4250
4251 return 0;
4252}
4253
4254/**
4255 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
4256 */
c79dd5b5 4257static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 4258 u16 txq_id)
4259{
4260 /* Simply stop the queue, but don't change any configuration;
4261 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
4262 iwl4965_write_prph(priv,
4263 KDR_SCD_QUEUE_STATUS_BITS(txq_id),
4264 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
4265 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
4266}
b481de9c 4267
fe01b477
RR		 4268/**
4269 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
b095d03a 4270 * priv->lock must be held by the caller
fe01b477 4271 */
c79dd5b5 4272static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
fe01b477
RR		 4273 u16 ssn_idx, u8 tx_fifo)
4274{
b095d03a
RR		 4275 int ret = 0;
4276
fe01b477
RR		 4277 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
4278 IWL_WARNING("queue number too small: %d, must be > %d\n",
4279 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4280 return -EINVAL;
b481de9c
ZY		 4281 }
4282
b095d03a
RR		 4283 ret = iwl4965_grab_nic_access(priv);
4284 if (ret)
4285 return ret;
4286
fe01b477
RR		 4287 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4288
4289 iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
4290
4291 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4292 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
4293 /* supposes that ssn_idx is valid (!= 0xFFF) */
4294 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4295
4296 iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
4297 iwl4965_txq_ctx_deactivate(priv, txq_id);
4298 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4299
b095d03a
RR		 4300 iwl4965_release_nic_access(priv);
4301
fe01b477
RR		 4302 return 0;
4303}
b481de9c 4304
c79dd5b5 4305int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
fe01b477
RR		 4306 u8 tid, int txq_id)
4307{
4308 struct iwl4965_queue *q = &priv->txq[txq_id].q;
4309 u8 *addr = priv->stations[sta_id].sta.sta.addr;
4310 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
4311
4312 switch (priv->stations[sta_id].tid[tid].agg.state) {
4313 case IWL_EMPTYING_HW_QUEUE_DELBA:
4314 /* We are reclaiming the last packet of the */
4315 /* aggregated HW queue */
4316 if (txq_id == tid_data->agg.txq_id &&
4317 q->read_ptr == q->write_ptr) {
4318 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
4319 int tx_fifo = default_tid_to_tx_fifo[tid];
4320 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
4321 iwl4965_tx_queue_agg_disable(priv, txq_id,
4322 ssn, tx_fifo);
4323 tid_data->agg.state = IWL_AGG_OFF;
4324 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4325 }
4326 break;
4327 case IWL_EMPTYING_HW_QUEUE_ADDBA:
4328 /* We are reclaiming the last packet of the queue */
4329 if (tid_data->tfds_in_queue == 0) {
4330 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
4331 tid_data->agg.state = IWL_AGG_ON;
4332 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4333 }
4334 break;
4335 }
b481de9c
ZY		 4336 return 0;
4337}
4338
8b6eaea8
CB		 4339/**
4340 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
4341 * @index -- current index
4342 * @n_bd -- total number of entries in queue (s/b power of 2)
4343 */
bb8c093b 4344static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 4345{
4346 return (index == 0) ? n_bd - 1 : index - 1;
4347}
4348
8b6eaea8
CB		 4349/**
4350 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
4351 *
4352 * Handles block-acknowledge notification from device, which reports success
4353 * of frames sent via aggregation.
4354 */
c79dd5b5 4355static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b 4356 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4357{
bb8c093b
CH		 4358 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4359 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 4360 int index;
bb8c093b
CH		 4361 struct iwl4965_tx_queue *txq = NULL;
4362 struct iwl4965_ht_agg *agg;
fe01b477 4363 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 4364
4365 /* "flow" corresponds to Tx queue */
fe01b477 4366 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 4367
4368 /* "ssn" is start of block-ack Tx window, corresponds to index
4369 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 4370 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
4371
fe01b477 4372 if (scd_flow >= ARRAY_SIZE(priv->txq)) {
b481de9c
ZY		 4373 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
4374 return;
4375 }
4376
fe01b477 4377 txq = &priv->txq[scd_flow];
b481de9c 4378 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 4379
4380 /* Find index just before block-ack window */
bb8c093b 4381 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 4382
01ebd063 4383 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 4384
0795af57
JP		 4385 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
4386 "sta_id = %d\n",
b481de9c 4387 agg->wait_for_ba,
0795af57 4388 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 4389 ba_resp->sta_id);
fe01b477 4390 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 4391 "%d, scd_ssn = %d\n",
4392 ba_resp->tid,
fe01b477 4393 ba_resp->seq_ctl,
0310ae72 4394 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 4395 ba_resp->scd_flow,
4396 ba_resp->scd_ssn);
fe01b477 4397 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 4398 agg->start_idx,
f868f4e1 4399 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 4400
4401 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 4402 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 4403
4404 /* Release all TFDs before the SSN, i.e. all TFDs in front of
4405 * block-ack window (we assume that they've been successfully
4406 * transmitted ... if not, it's too late anyway). */
fe01b477
RR		 4407 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
4408 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
4409 priv->stations[ba_resp->sta_id].
4410 tid[ba_resp->tid].tfds_in_queue -= freed;
4411 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
4412 priv->mac80211_registered &&
4413 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
4414 ieee80211_wake_queue(priv->hw, scd_flow);
4415 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
4416 ba_resp->tid, scd_flow);
4417 }
b481de9c
ZY		 4418}
4419
8b6eaea8
CB		 4420/**
4421 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
4422 */
c79dd5b5 4423static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 4424 u16 txq_id)
4425{
4426 u32 tbl_dw_addr;
4427 u32 tbl_dw;
4428 u16 scd_q2ratid;
4429
4430 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
4431
4432 tbl_dw_addr = priv->scd_base_addr +
4433 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
4434
bb8c093b 4435 tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 4436
4437 if (txq_id & 0x1)
4438 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
4439 else
4440 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
4441
bb8c093b 4442 iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 4443
4444 return 0;
4445}
4446
fe01b477 4447
b481de9c 4448/**
8b6eaea8
CB		 4449 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
4450 *
4451 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
4452 * i.e. it must be one of the higher queues used for aggregation
b481de9c 4453 */
c79dd5b5 4454static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
b481de9c
ZY		 4455 int tx_fifo, int sta_id, int tid,
4456 u16 ssn_idx)
4457{
4458 unsigned long flags;
4459 int rc;
4460 u16 ra_tid;
4461
4462 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
4463 IWL_WARNING("queue number too small: %d, must be > %d\n",
4464 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4465
4466 ra_tid = BUILD_RAxTID(sta_id, tid);
4467
8b6eaea8 4468 /* Modify device's station table to Tx this TID */
bb8c093b 4469 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 4470
4471 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 4472 rc = iwl4965_grab_nic_access(priv);
b481de9c
ZY		 4473 if (rc) {
4474 spin_unlock_irqrestore(&priv->lock, flags);
4475 return rc;
4476 }
4477
8b6eaea8 4478 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 4479 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4480
8b6eaea8 4481 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 4482 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
4483
8b6eaea8 4484 /* Set this queue as a chain-building queue */
8a1b0245 4485 iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 4486
8b6eaea8
CB		 4487 /* Place first TFD at index corresponding to start sequence number.
4488 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 4489 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4490 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 4491 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4492
8b6eaea8 4493 /* Set up Tx window size and frame limit for this queue */
bb8c093b 4494 iwl4965_write_targ_mem(priv,
b481de9c
ZY		 4495 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
4496 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4497 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4498
bb8c093b 4499 iwl4965_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 4500 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
4501 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4502 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4503
bb8c093b 4504 iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 4505
8b6eaea8 4506 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 4507 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4508
bb8c093b 4509 iwl4965_release_nic_access(priv);
b481de9c
ZY		 4510 spin_unlock_irqrestore(&priv->lock, flags);
4511
4512 return 0;
4513}
4514
c8b0e6e1 4515#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4516
4517/**
4518 * iwl4965_add_station - Initialize a station's hardware rate table
4519 *
8b6eaea8 4520 * The uCode's station table contains a table of fallback rates
b481de9c
ZY		 4521 * for automatic fallback during transmission.
4522 *
8b6eaea8
CB		 4523 * NOTE: This sets up a default set of values. These will be replaced later
4524 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
4525 * rc80211_simple.
b481de9c 4526 *
8b6eaea8
CB		 4527 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
4528 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
4529 * which requires station table entry to exist).
b481de9c 4530 */
c79dd5b5 4531void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 4532{
4533 int i, r;
bb8c093b 4534 struct iwl4965_link_quality_cmd link_cmd = {
b481de9c
ZY		 4535 .reserved1 = 0,
4536 };
4537 u16 rate_flags;
4538
8b6eaea8
CB		 4539 /* Set up the rate scaling to start at selected rate, fall back
4540 * all the way down to 1M in IEEE order, and then spin on 1M */
b481de9c
ZY		 4541 if (is_ap)
4542 r = IWL_RATE_54M_INDEX;
8318d78a 4543 else if (priv->band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4544 r = IWL_RATE_6M_INDEX;
4545 else
4546 r = IWL_RATE_1M_INDEX;
4547
4548 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
4549 rate_flags = 0;
4550 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
4551 rate_flags |= RATE_MCS_CCK_MSK;
4552
8b6eaea8 4553 /* Use Tx antenna B only */
b481de9c
ZY		 4554 rate_flags |= RATE_MCS_ANT_B_MSK;
4555 rate_flags &= ~RATE_MCS_ANT_A_MSK;
8b6eaea8 4556
b481de9c 4557 link_cmd.rs_table[i].rate_n_flags =
bb8c093b
CH		 4558 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
4559 r = iwl4965_get_prev_ieee_rate(r);
b481de9c
ZY		 4560 }
4561
4562 link_cmd.general_params.single_stream_ant_msk = 2;
4563 link_cmd.general_params.dual_stream_ant_msk = 3;
4564 link_cmd.agg_params.agg_dis_start_th = 3;
4565 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
4566
4567 /* Update the rate scaling for control frame Tx to AP */
a4062b8f 4568 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_setting.bcast_sta_id;
b481de9c 4569
857485c0 4570 iwl_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
b481de9c
ZY		 4571 &link_cmd);
4572}
4573
c8b0e6e1 4574#ifdef CONFIG_IWL4965_HT
b481de9c 4575
c79dd5b5 4576static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
8318d78a 4577 enum ieee80211_band band,
78330fdd 4578 u16 channel, u8 extension_chan_offset)
b481de9c 4579{
bf85ea4f 4580 const struct iwl_channel_info *ch_info;
b481de9c 4581
8622e705 4582 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 4583 if (!is_channel_valid(ch_info))
4584 return 0;
4585
134eb5d3 4586 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
b481de9c
ZY		 4587 return 0;
4588
4589 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
4590 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
4591 return 1;
4592
4593 return 0;
4594}
4595
c79dd5b5 4596static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
fd105e79 4597 struct ieee80211_ht_info *sta_ht_inf)
b481de9c 4598{
fd105e79 4599 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
b481de9c 4600
fd105e79
RR		 4601 if ((!iwl_ht_conf->is_ht) ||
4602 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
134eb5d3 4603 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
b481de9c
ZY		 4604 return 0;
4605
fd105e79
RR		 4606 if (sta_ht_inf) {
4607 if ((!sta_ht_inf->ht_supported) ||
194c7ca6 4608 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
fd105e79
RR		 4609 return 0;
4610 }
b481de9c 4611
78330fdd 4612 return (iwl4965_is_channel_extension(priv, priv->band,
fd105e79
RR		 4613 iwl_ht_conf->control_channel,
4614 iwl_ht_conf->extension_chan_offset));
b481de9c
ZY		 4615}
4616
c79dd5b5 4617void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
b481de9c 4618{
bb8c093b 4619 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 4620 u32 val;
4621
4622 if (!ht_info->is_ht)
4623 return;
4624
8b6eaea8 4625 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
fd105e79 4626 if (iwl4965_is_fat_tx_allowed(priv, NULL))
b481de9c
ZY		 4627 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4628 else
4629 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4630 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
4631
4632 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
4633 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4634 le16_to_cpu(rxon->channel),
4635 ht_info->control_channel);
4636 rxon->channel = cpu_to_le16(ht_info->control_channel);
4637 return;
4638 }
4639
8b6eaea8 4640 /* Note: control channel is opposite of extension channel */
b481de9c
ZY		 4641 switch (ht_info->extension_chan_offset) {
4642 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4643 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4644 break;
4645 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4646 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4647 break;
134eb5d3 4648 case IWL_EXT_CHANNEL_OFFSET_NONE:
b481de9c
ZY		 4649 default:
4650 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4651 break;
4652 }
4653
fd105e79 4654 val = ht_info->ht_protection;
b481de9c
ZY		 4655
4656 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4657
b481de9c
ZY		 4658 iwl4965_set_rxon_chain(priv);
4659
4660 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
4661 "rxon flags 0x%X operation mode :0x%X "
4662 "extension channel offset 0x%x "
4663 "control chan %d\n",
fd105e79
RR		 4664 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
4665 le32_to_cpu(rxon->flags), ht_info->ht_protection,
b481de9c
ZY		 4666 ht_info->extension_chan_offset,
4667 ht_info->control_channel);
4668 return;
4669}
4670
c79dd5b5 4671void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
67d62035 4672 struct ieee80211_ht_info *sta_ht_inf)
b481de9c
ZY		 4673{
4674 __le32 sta_flags;
e53cfe0e 4675 u8 mimo_ps_mode;
b481de9c 4676
67d62035 4677 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
b481de9c
ZY		 4678 goto done;
4679
e53cfe0e
TW		 4680 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4681
b481de9c
ZY		 4682 sta_flags = priv->stations[index].sta.station_flags;
4683
e53cfe0e
TW		 4684 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4685
4686 switch (mimo_ps_mode) {
4687 case WLAN_HT_CAP_MIMO_PS_STATIC:
4688 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4689 break;
4690 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
b481de9c 4691 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
e53cfe0e
TW		 4692 break;
4693 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4694 break;
4695 default:
4696 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4697 break;
4698 }
b481de9c
ZY		 4699
4700 sta_flags |= cpu_to_le32(
67d62035 4701 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
b481de9c
ZY		 4702
4703 sta_flags |= cpu_to_le32(
67d62035 4704 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
b481de9c 4705
67d62035 4706 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
b481de9c 4707 sta_flags |= STA_FLG_FAT_EN_MSK;
67d62035 4708 else
e53cfe0e 4709 sta_flags &= ~STA_FLG_FAT_EN_MSK;
67d62035 4710
b481de9c
ZY		 4711 priv->stations[index].sta.station_flags = sta_flags;
4712 done:
4713 return;
4714}
4715
c79dd5b5 4716static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
b481de9c
ZY		 4717 int sta_id, int tid, u16 ssn)
4718{
4719 unsigned long flags;
4720
4721 spin_lock_irqsave(&priv->sta_lock, flags);
4722 priv->stations[sta_id].sta.station_flags_msk = 0;
4723 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4724 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4725 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4726 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4727 spin_unlock_irqrestore(&priv->sta_lock, flags);
4728
bb8c093b 4729 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4730}
4731
c79dd5b5 4732static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
b481de9c
ZY		 4733 int sta_id, int tid)
4734{
4735 unsigned long flags;
4736
4737 spin_lock_irqsave(&priv->sta_lock, flags);
4738 priv->stations[sta_id].sta.station_flags_msk = 0;
4739 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4740 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4741 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4742 spin_unlock_irqrestore(&priv->sta_lock, flags);
4743
bb8c093b 4744 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4745}
4746
8b6eaea8
CB		 4747/*
4748 * Find first available (lowest unused) Tx Queue, mark it "active".
4749 * Called only when finding queue for aggregation.
4750 * Should never return anything < 7, because they should already
4751 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4752 */
c79dd5b5 4753static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
b481de9c
ZY		 4754{
4755 int txq_id;
4756
4757 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
4758 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4759 return txq_id;
4760 return -1;
4761}
4762
fe01b477
RR		 4763static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
4764 u16 tid, u16 *start_seq_num)
b481de9c 4765{
c79dd5b5 4766 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 4767 int sta_id;
4768 int tx_fifo;
4769 int txq_id;
4770 int ssn = -1;
b095d03a 4771 int ret = 0;
b481de9c 4772 unsigned long flags;
bb8c093b 4773 struct iwl4965_tid_data *tid_data;
0795af57 4774 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 4775
4776 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4777 tx_fifo = default_tid_to_tx_fifo[tid];
4778 else
4779 return -EINVAL;
4780
fe01b477
RR		 4781 IWL_WARNING("%s on da = %s tid = %d\n",
4782 __func__, print_mac(mac, da), tid);
b481de9c 4783
bb8c093b 4784 sta_id = iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 4785 if (sta_id == IWL_INVALID_STATION)
4786 return -ENXIO;
4787
fe01b477
RR		 4788 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4789 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4790 return -ENXIO;
4791 }
4792
bb8c093b 4793 txq_id = iwl4965_txq_ctx_activate_free(priv);
b481de9c
ZY		 4794 if (txq_id == -1)
4795 return -ENXIO;
4796
4797 spin_lock_irqsave(&priv->sta_lock, flags);
4798 tid_data = &priv->stations[sta_id].tid[tid];
4799 ssn = SEQ_TO_SN(tid_data->seq_number);
4800 tid_data->agg.txq_id = txq_id;
4801 spin_unlock_irqrestore(&priv->sta_lock, flags);
4802
4803 *start_seq_num = ssn;
b095d03a
RR		 4804 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4805 sta_id, tid, ssn);
4806 if (ret)
4807 return ret;
b481de9c 4808
b095d03a 4809 ret = 0;
fe01b477
RR		 4810 if (tid_data->tfds_in_queue == 0) {
4811 printk(KERN_ERR "HW queue is empty\n");
4812 tid_data->agg.state = IWL_AGG_ON;
4813 ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
4814 } else {
4815 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4816 tid_data->tfds_in_queue);
4817 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4818 }
b095d03a 4819 return ret;
fe01b477 4820}
b481de9c 4821
fe01b477
RR		 4822static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
4823 u16 tid)
b481de9c
ZY		 4824{
4825
c79dd5b5 4826 struct iwl_priv *priv = hw->priv;
b481de9c 4827 int tx_fifo_id, txq_id, sta_id, ssn = -1;
bb8c093b 4828 struct iwl4965_tid_data *tid_data;
b095d03a 4829 int ret, write_ptr, read_ptr;
fe01b477 4830 unsigned long flags;
0795af57
JP		 4831 DECLARE_MAC_BUF(mac);
4832
b481de9c 4833 if (!da) {
fe01b477 4834 IWL_ERROR("da = NULL\n");
b481de9c
ZY		 4835 return -EINVAL;
4836 }
4837
4838 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4839 tx_fifo_id = default_tid_to_tx_fifo[tid];
4840 else
4841 return -EINVAL;
4842
bb8c093b 4843 sta_id = iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 4844
4845 if (sta_id == IWL_INVALID_STATION)
4846 return -ENXIO;
4847
fe01b477
RR		 4848 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4849 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4850
b481de9c
ZY		 4851 tid_data = &priv->stations[sta_id].tid[tid];
4852 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4853 txq_id = tid_data->agg.txq_id;
fe01b477
RR		 4854 write_ptr = priv->txq[txq_id].q.write_ptr;
4855 read_ptr = priv->txq[txq_id].q.read_ptr;
4856
4857 /* The queue is not empty */
4858 if (write_ptr != read_ptr) {
4859 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4860 priv->stations[sta_id].tid[tid].agg.state =
4861 IWL_EMPTYING_HW_QUEUE_DELBA;
4862 return 0;
4863 }
4864
4865 IWL_DEBUG_HT("HW queue empty\n");;
4866 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
b481de9c 4867
fe01b477 4868 spin_lock_irqsave(&priv->lock, flags);
b095d03a 4869 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
fe01b477
RR		 4870 spin_unlock_irqrestore(&priv->lock, flags);
4871
b095d03a
RR		 4872 if (ret)
4873 return ret;
b481de9c 4874
fe01b477 4875 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
b481de9c 4876
fe01b477
RR		 4877 IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
4878 print_mac(mac, da), tid);
8114fcf1 4879
8114fcf1
RR		 4880 return 0;
4881}
4882
4883int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4884 enum ieee80211_ampdu_mlme_action action,
4885 const u8 *addr, u16 tid, u16 *ssn)
4886{
c79dd5b5 4887 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 4888 int sta_id;
4889 DECLARE_MAC_BUF(mac);
4890
4891 IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
4892 print_mac(mac, addr), tid);
4893 sta_id = iwl4965_hw_find_station(priv, addr);
4894 switch (action) {
4895 case IEEE80211_AMPDU_RX_START:
4896 IWL_DEBUG_HT("start Rx\n");
4897 iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
4898 break;
4899 case IEEE80211_AMPDU_RX_STOP:
4900 IWL_DEBUG_HT("stop Rx\n");
4901 iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
4902 break;
4903 case IEEE80211_AMPDU_TX_START:
4904 IWL_DEBUG_HT("start Tx\n");
4905 return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
4906 case IEEE80211_AMPDU_TX_STOP:
4907 IWL_DEBUG_HT("stop Tx\n");
4908 return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
4909 default:
4910 IWL_DEBUG_HT("unknown\n");
4911 return -EINVAL;
4912 break;
4913 }
4914 return 0;
4915}
4916
c8b0e6e1 4917#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4918
4919/* Set up 4965-specific Rx frame reply handlers */
c79dd5b5 4920void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 4921{
4922 /* Legacy Rx frames */
857485c0 4923 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
b481de9c
ZY		 4924
4925 /* High-throughput (HT) Rx frames */
4926 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4927 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4928
4929 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4930 iwl4965_rx_missed_beacon_notif;
4931
c8b0e6e1 4932#ifdef CONFIG_IWL4965_HT
b481de9c 4933 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
c8b0e6e1 4934#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4935}
4936
c79dd5b5 4937void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4938{
4939 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4940 INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
c8b0e6e1 4941#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 4942 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4943#endif
b481de9c
ZY		 4944 init_timer(&priv->statistics_periodic);
4945 priv->statistics_periodic.data = (unsigned long)priv;
4946 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4947}
4948
c79dd5b5 4949void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4950{
4951 del_timer_sync(&priv->statistics_periodic);
4952
4953 cancel_delayed_work(&priv->init_alive_start);
4954}
4955
857485c0
TW		 4956static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4957 .enqueue_hcmd = iwl4965_enqueue_hcmd,
4958};
4959
6bc913bd 4960static struct iwl_lib_ops iwl4965_lib = {
bf85ea4f 4961 .init_drv = iwl4965_init_drv,
6bc913bd
AK		 4962 .eeprom_ops = {
4963 .verify_signature = iwlcore_eeprom_verify_signature,
4964 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4965 .release_semaphore = iwlcore_eeprom_release_semaphore,
4966 },
4967};
4968
4969static struct iwl_ops iwl4965_ops = {
4970 .lib = &iwl4965_lib,
857485c0 4971 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 4972};
4973
82b9a121
TW		 4974static struct iwl_cfg iwl4965_agn_cfg = {
4975 .name = "4965AGN",
4bf775cd 4976 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 4977 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
6bc913bd 4978 .ops = &iwl4965_ops,
1ea87396 4979 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 4980};
4981
bb8c093b 4982struct pci_device_id iwl4965_hw_card_ids[] = {
82b9a121
TW		 4983 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4984 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
b481de9c
ZY		 4985 {0}
4986};
4987
bb8c093b 4988MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);
1ea87396
AK		 4989
4990module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4991MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4992module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4993MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
4994module_param_named(hwcrypto, iwl4965_mod_params.hw_crypto, int, 0444);
4995MODULE_PARM_DESC(hwcrypto,
4996 "using hardware crypto engine (default 0 [software])\n");
4997module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4998MODULE_PARM_DESC(debug, "debug output mask");
4999module_param_named(
5000 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
5001MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
5002
5003module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
5004MODULE_PARM_DESC(queues_num, "number of hw queues.");
5005
5006/* QoS */
5007module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
5008MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
5009module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
5010MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
5011
Linux kernel - Deliverables
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