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iwlwifi: add iwl_hw_detect function to iwl core
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
b481de9c 42#include "iwl-4965.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c 45#include "iwl-helpers.h"
f0832f13 46#include "iwl-calib.h"
b481de9c 47
1ea87396
AK		 48/* module parameters */
49static struct iwl_mod_params iwl4965_mod_params = {
dfe7d458 50 .num_of_queues = IWL4965_MAX_NUM_QUEUES,
1ea87396
AK		 51 .enable_qos = 1,
52 .amsdu_size_8K = 1,
53 /* the rest are 0 by default */
54};
55
c79dd5b5 56static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
416e1438 57
b481de9c
ZY		 58#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
59 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
60 IWL_RATE_SISO_##s##M_PLCP, \
fde0db31
GC		 61 IWL_RATE_MIMO2_##s##M_PLCP,\
62 IWL_RATE_MIMO3_##s##M_PLCP,\
b481de9c
ZY		 63 IWL_RATE_##r##M_IEEE, \
64 IWL_RATE_##ip##M_INDEX, \
65 IWL_RATE_##in##M_INDEX, \
66 IWL_RATE_##rp##M_INDEX, \
67 IWL_RATE_##rn##M_INDEX, \
68 IWL_RATE_##pp##M_INDEX, \
69 IWL_RATE_##np##M_INDEX }
70
71/*
72 * Parameter order:
73 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
74 *
75 * If there isn't a valid next or previous rate then INV is used which
76 * maps to IWL_RATE_INVALID
77 *
78 */
bb8c093b 79const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
b481de9c
ZY		 80 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
81 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
82 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
83 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
84 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
85 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
86 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
87 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
88 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
89 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
90 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
91 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
92 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
fde0db31 93 /* FIXME:RS: ^^ should be INV (legacy) */
b481de9c
ZY		 94};
95
fe01b477
RR		 96#ifdef CONFIG_IWL4965_HT
97
98static const u16 default_tid_to_tx_fifo[] = {
99 IWL_TX_FIFO_AC1,
100 IWL_TX_FIFO_AC0,
101 IWL_TX_FIFO_AC0,
102 IWL_TX_FIFO_AC1,
103 IWL_TX_FIFO_AC2,
104 IWL_TX_FIFO_AC2,
105 IWL_TX_FIFO_AC3,
106 IWL_TX_FIFO_AC3,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_NONE,
113 IWL_TX_FIFO_NONE,
114 IWL_TX_FIFO_NONE,
115 IWL_TX_FIFO_AC3
116};
117
118#endif /*CONFIG_IWL4965_HT */
119
57aab75a
TW		 120/* check contents of special bootstrap uCode SRAM */
121static int iwl4965_verify_bsm(struct iwl_priv *priv)
122{
123 __le32 *image = priv->ucode_boot.v_addr;
124 u32 len = priv->ucode_boot.len;
125 u32 reg;
126 u32 val;
127
128 IWL_DEBUG_INFO("Begin verify bsm\n");
129
130 /* verify BSM SRAM contents */
131 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
132 for (reg = BSM_SRAM_LOWER_BOUND;
133 reg < BSM_SRAM_LOWER_BOUND + len;
134 reg += sizeof(u32), image++) {
135 val = iwl_read_prph(priv, reg);
136 if (val != le32_to_cpu(*image)) {
137 IWL_ERROR("BSM uCode verification failed at "
138 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
139 BSM_SRAM_LOWER_BOUND,
140 reg - BSM_SRAM_LOWER_BOUND, len,
141 val, le32_to_cpu(*image));
142 return -EIO;
143 }
144 }
145
146 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
147
148 return 0;
149}
150
151/**
152 * iwl4965_load_bsm - Load bootstrap instructions
153 *
154 * BSM operation:
155 *
156 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
157 * in special SRAM that does not power down during RFKILL. When powering back
158 * up after power-saving sleeps (or during initial uCode load), the BSM loads
159 * the bootstrap program into the on-board processor, and starts it.
160 *
161 * The bootstrap program loads (via DMA) instructions and data for a new
162 * program from host DRAM locations indicated by the host driver in the
163 * BSM_DRAM_* registers. Once the new program is loaded, it starts
164 * automatically.
165 *
166 * When initializing the NIC, the host driver points the BSM to the
167 * "initialize" uCode image. This uCode sets up some internal data, then
168 * notifies host via "initialize alive" that it is complete.
169 *
170 * The host then replaces the BSM_DRAM_* pointer values to point to the
171 * normal runtime uCode instructions and a backup uCode data cache buffer
172 * (filled initially with starting data values for the on-board processor),
173 * then triggers the "initialize" uCode to load and launch the runtime uCode,
174 * which begins normal operation.
175 *
176 * When doing a power-save shutdown, runtime uCode saves data SRAM into
177 * the backup data cache in DRAM before SRAM is powered down.
178 *
179 * When powering back up, the BSM loads the bootstrap program. This reloads
180 * the runtime uCode instructions and the backup data cache into SRAM,
181 * and re-launches the runtime uCode from where it left off.
182 */
183static int iwl4965_load_bsm(struct iwl_priv *priv)
184{
185 __le32 *image = priv->ucode_boot.v_addr;
186 u32 len = priv->ucode_boot.len;
187 dma_addr_t pinst;
188 dma_addr_t pdata;
189 u32 inst_len;
190 u32 data_len;
191 int i;
192 u32 done;
193 u32 reg_offset;
194 int ret;
195
196 IWL_DEBUG_INFO("Begin load bsm\n");
197
198 /* make sure bootstrap program is no larger than BSM's SRAM size */
199 if (len > IWL_MAX_BSM_SIZE)
200 return -EINVAL;
201
202 /* Tell bootstrap uCode where to find the "Initialize" uCode
203 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
204 * NOTE: iwl4965_initialize_alive_start() will replace these values,
205 * after the "initialize" uCode has run, to point to
206 * runtime/protocol instructions and backup data cache. */
207 pinst = priv->ucode_init.p_addr >> 4;
208 pdata = priv->ucode_init_data.p_addr >> 4;
209 inst_len = priv->ucode_init.len;
210 data_len = priv->ucode_init_data.len;
211
212 ret = iwl_grab_nic_access(priv);
213 if (ret)
214 return ret;
215
216 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
217 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
218 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
219 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
220
221 /* Fill BSM memory with bootstrap instructions */
222 for (reg_offset = BSM_SRAM_LOWER_BOUND;
223 reg_offset < BSM_SRAM_LOWER_BOUND + len;
224 reg_offset += sizeof(u32), image++)
225 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
226
227 ret = iwl4965_verify_bsm(priv);
228 if (ret) {
229 iwl_release_nic_access(priv);
230 return ret;
231 }
232
233 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
234 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
235 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
236 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
237
238 /* Load bootstrap code into instruction SRAM now,
239 * to prepare to load "initialize" uCode */
240 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
241
242 /* Wait for load of bootstrap uCode to finish */
243 for (i = 0; i < 100; i++) {
244 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
245 if (!(done & BSM_WR_CTRL_REG_BIT_START))
246 break;
247 udelay(10);
248 }
249 if (i < 100)
250 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
251 else {
252 IWL_ERROR("BSM write did not complete!\n");
253 return -EIO;
254 }
255
256 /* Enable future boot loads whenever power management unit triggers it
257 * (e.g. when powering back up after power-save shutdown) */
258 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
259
260 iwl_release_nic_access(priv);
261
262 return 0;
263}
264
bf85ea4f
AK		 265static int iwl4965_init_drv(struct iwl_priv *priv)
266{
267 int ret;
268 int i;
269
bf85ea4f
AK		 270 priv->retry_rate = 1;
271 priv->ibss_beacon = NULL;
272
273 spin_lock_init(&priv->lock);
274 spin_lock_init(&priv->power_data.lock);
275 spin_lock_init(&priv->sta_lock);
276 spin_lock_init(&priv->hcmd_lock);
277 spin_lock_init(&priv->lq_mngr.lock);
278
059ff826
TW		 279 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
280 sizeof(struct iwl4965_shared),
281 &priv->shared_phys);
282
283 if (!priv->shared_virt) {
284 ret = -ENOMEM;
285 goto err;
286 }
287
288 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
289
290
bf85ea4f
AK		 291 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
292 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
293
294 INIT_LIST_HEAD(&priv->free_frames);
295
296 mutex_init(&priv->mutex);
297
298 /* Clear the driver's (not device's) station table */
299 iwlcore_clear_stations_table(priv);
300
301 priv->data_retry_limit = -1;
302 priv->ieee_channels = NULL;
303 priv->ieee_rates = NULL;
304 priv->band = IEEE80211_BAND_2GHZ;
305
306 priv->iw_mode = IEEE80211_IF_TYPE_STA;
307
308 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
bf85ea4f
AK		 309 priv->ps_mode = IWL_MIMO_PS_NONE;
310
311 /* Choose which receivers/antennas to use */
312 iwl4965_set_rxon_chain(priv);
313
314 iwlcore_reset_qos(priv);
315
316 priv->qos_data.qos_active = 0;
317 priv->qos_data.qos_cap.val = 0;
318
319 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
320
321 priv->rates_mask = IWL_RATES_MASK;
322 /* If power management is turned on, default to AC mode */
323 priv->power_mode = IWL_POWER_AC;
324 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
325
326 ret = iwl_init_channel_map(priv);
327 if (ret) {
328 IWL_ERROR("initializing regulatory failed: %d\n", ret);
329 goto err;
330 }
331
332 ret = iwl4965_init_geos(priv);
333 if (ret) {
334 IWL_ERROR("initializing geos failed: %d\n", ret);
335 goto err_free_channel_map;
336 }
337
bf85ea4f
AK		 338 ret = ieee80211_register_hw(priv->hw);
339 if (ret) {
340 IWL_ERROR("Failed to register network device (error %d)\n",
341 ret);
342 goto err_free_geos;
343 }
344
345 priv->hw->conf.beacon_int = 100;
346 priv->mac80211_registered = 1;
347
348 return 0;
349
350err_free_geos:
351 iwl4965_free_geos(priv);
352err_free_channel_map:
353 iwl_free_channel_map(priv);
354err:
355 return ret;
356}
357
b481de9c
ZY		 358static int is_fat_channel(__le32 rxon_flags)
359{
360 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
361 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
362}
363
c8b0e6e1 364#ifdef CONFIG_IWL4965_HT
fde0db31
GC		 365static u8 is_single_rx_stream(struct iwl_priv *priv)
366{
367 return !priv->current_ht_config.is_ht ||
368 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
369 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
370 priv->ps_mode == IWL_MIMO_PS_STATIC;
371}
b481de9c 372#else
fde0db31
GC		 373static inline u8 is_single_rx_stream(struct iwl_priv *priv)
374{
b481de9c 375 return 1;
b481de9c 376}
fde0db31 377#endif /*CONFIG_IWL4965_HT */
b481de9c 378
17744ff6
TW		 379int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
380{
381 int idx = 0;
382
383 /* 4965 HT rate format */
384 if (rate_n_flags & RATE_MCS_HT_MSK) {
385 idx = (rate_n_flags & 0xff);
386
fde0db31
GC		 387 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
388 idx = idx - IWL_RATE_MIMO2_6M_PLCP;
17744ff6
TW		 389
390 idx += IWL_FIRST_OFDM_RATE;
391 /* skip 9M not supported in ht*/
392 if (idx >= IWL_RATE_9M_INDEX)
393 idx += 1;
394 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
395 return idx;
396
397 /* 4965 legacy rate format, search for match in table */
398 } else {
399 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
400 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
401 return idx;
402 }
403
404 return -1;
405}
406
4c424e4c
RR		 407/**
408 * translate ucode response to mac80211 tx status control values
409 */
c79dd5b5 410void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
4c424e4c
RR		 411 struct ieee80211_tx_control *control)
412{
413 int rate_index;
414
415 control->antenna_sel_tx =
fde0db31 416 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
4c424e4c
RR		 417 if (rate_n_flags & RATE_MCS_HT_MSK)
418 control->flags |= IEEE80211_TXCTL_OFDM_HT;
419 if (rate_n_flags & RATE_MCS_GF_MSK)
420 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
421 if (rate_n_flags & RATE_MCS_FAT_MSK)
422 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
423 if (rate_n_flags & RATE_MCS_DUP_MSK)
424 control->flags |= IEEE80211_TXCTL_DUP_DATA;
425 if (rate_n_flags & RATE_MCS_SGI_MSK)
426 control->flags |= IEEE80211_TXCTL_SHORT_GI;
427 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
428 * IEEE80211_BAND_2GHZ band as it contains all the rates */
429 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
430 if (rate_index == -1)
431 control->tx_rate = NULL;
432 else
433 control->tx_rate =
434 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
435}
17744ff6 436
b481de9c
ZY		 437/*
438 * Determine how many receiver/antenna chains to use.
439 * More provides better reception via diversity. Fewer saves power.
440 * MIMO (dual stream) requires at least 2, but works better with 3.
441 * This does not determine *which* chains to use, just how many.
442 */
c79dd5b5 443static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
b481de9c
ZY		 444 u8 *idle_state, u8 *rx_state)
445{
fde0db31 446 u8 is_single = is_single_rx_stream(priv);
b481de9c
ZY		 447 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
448
449 /* # of Rx chains to use when expecting MIMO. */
450 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
451 *rx_state = 2;
452 else
453 *rx_state = 3;
454
455 /* # Rx chains when idling and maybe trying to save power */
456 switch (priv->ps_mode) {
457 case IWL_MIMO_PS_STATIC:
458 case IWL_MIMO_PS_DYNAMIC:
459 *idle_state = (is_cam) ? 2 : 1;
460 break;
461 case IWL_MIMO_PS_NONE:
462 *idle_state = (is_cam) ? *rx_state : 1;
463 break;
464 default:
465 *idle_state = 1;
466 break;
467 }
468
469 return 0;
470}
471
c79dd5b5 472int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 473{
474 int rc;
475 unsigned long flags;
476
477 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 478 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 479 if (rc) {
480 spin_unlock_irqrestore(&priv->lock, flags);
481 return rc;
482 }
483
8b6eaea8 484 /* stop Rx DMA */
3395f6e9
TW		 485 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
486 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
b481de9c
ZY		 487 (1 << 24), 1000);
488 if (rc < 0)
489 IWL_ERROR("Can't stop Rx DMA.\n");
490
3395f6e9 491 iwl_release_nic_access(priv);
b481de9c
ZY		 492 spin_unlock_irqrestore(&priv->lock, flags);
493
494 return 0;
495}
496
079a2533 497int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 498{
d8609652 499 int ret;
b481de9c
ZY		 500 unsigned long flags;
501
502 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 503 ret = iwl_grab_nic_access(priv);
d8609652 504 if (ret) {
b481de9c 505 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 506 return ret;
b481de9c
ZY		 507 }
508
6f4083aa 509 if (src == IWL_PWR_SRC_VAUX) {
b481de9c 510 u32 val;
d8609652 511 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
6f4083aa 512 &val);
b481de9c 513
6f4083aa 514 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
3395f6e9 515 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 516 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
517 ~APMG_PS_CTRL_MSK_PWR_SRC);
518 }
519 } else {
3395f6e9 520 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 521 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
522 ~APMG_PS_CTRL_MSK_PWR_SRC);
523 }
b481de9c 524
3395f6e9 525 iwl_release_nic_access(priv);
b481de9c
ZY		 526 spin_unlock_irqrestore(&priv->lock, flags);
527
d8609652 528 return ret;
b481de9c
ZY		 529}
530
c79dd5b5 531static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c 532{
059ff826 533 int ret;
b481de9c 534 unsigned long flags;
9ee1ba47 535 unsigned int rb_size;
b481de9c
ZY		 536
537 spin_lock_irqsave(&priv->lock, flags);
059ff826
TW		 538 ret = iwl_grab_nic_access(priv);
539 if (ret) {
b481de9c 540 spin_unlock_irqrestore(&priv->lock, flags);
059ff826 541 return ret;
b481de9c
ZY		 542 }
543
1ea87396 544 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 545 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
546 else
547 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
548
8b6eaea8 549 /* Stop Rx DMA */
3395f6e9 550 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
b481de9c 551
8b6eaea8 552 /* Reset driver's Rx queue write index */
3395f6e9 553 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
8b6eaea8
CB		 554
555 /* Tell device where to find RBD circular buffer in DRAM */
3395f6e9
TW		 556 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
557 rxq->dma_addr >> 8);
b481de9c 558
8b6eaea8 559 /* Tell device where in DRAM to update its Rx status */
3395f6e9 560 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
059ff826
TW		 561 (priv->shared_phys +
562 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
b481de9c 563
8b6eaea8 564 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
3395f6e9
TW		 565 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
566 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
567 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
568 rb_size |
059ff826 569 /* 0x10 << 4 | */
3395f6e9 570 (RX_QUEUE_SIZE_LOG <<
b481de9c
ZY		 571 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
572
573 /*
3395f6e9 574 * iwl_write32(priv,CSR_INT_COAL_REG,0);
b481de9c
ZY		 575 */
576
3395f6e9 577 iwl_release_nic_access(priv);
b481de9c
ZY		 578 spin_unlock_irqrestore(&priv->lock, flags);
579
580 return 0;
581}
582
8b6eaea8 583/* Tell 4965 where to find the "keep warm" buffer */
c79dd5b5 584static int iwl4965_kw_init(struct iwl_priv *priv)
b481de9c
ZY		 585{
586 unsigned long flags;
587 int rc;
588
589 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 590 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 591 if (rc)
592 goto out;
593
3395f6e9 594 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
b481de9c 595 priv->kw.dma_addr >> 4);
3395f6e9 596 iwl_release_nic_access(priv);
b481de9c
ZY		 597out:
598 spin_unlock_irqrestore(&priv->lock, flags);
599 return rc;
600}
601
c79dd5b5 602static int iwl4965_kw_alloc(struct iwl_priv *priv)
b481de9c
ZY		 603{
604 struct pci_dev *dev = priv->pci_dev;
bb8c093b 605 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 606
607 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
608 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
609 if (!kw->v_addr)
610 return -ENOMEM;
611
612 return 0;
613}
614
8b6eaea8
CB		 615/**
616 * iwl4965_kw_free - Free the "keep warm" buffer
617 */
c79dd5b5 618static void iwl4965_kw_free(struct iwl_priv *priv)
b481de9c
ZY		 619{
620 struct pci_dev *dev = priv->pci_dev;
bb8c093b 621 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 622
623 if (kw->v_addr) {
624 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
625 memset(kw, 0, sizeof(*kw));
626 }
627}
628
629/**
630 * iwl4965_txq_ctx_reset - Reset TX queue context
631 * Destroys all DMA structures and initialise them again
632 *
633 * @param priv
634 * @return error code
635 */
c79dd5b5 636static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 637{
638 int rc = 0;
639 int txq_id, slots_num;
640 unsigned long flags;
641
642 iwl4965_kw_free(priv);
643
8b6eaea8 644 /* Free all tx/cmd queues and keep-warm buffer */
bb8c093b 645 iwl4965_hw_txq_ctx_free(priv);
b481de9c 646
8b6eaea8 647 /* Alloc keep-warm buffer */
b481de9c
ZY		 648 rc = iwl4965_kw_alloc(priv);
649 if (rc) {
650 IWL_ERROR("Keep Warm allocation failed");
651 goto error_kw;
652 }
653
654 spin_lock_irqsave(&priv->lock, flags);
655
3395f6e9 656 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 657 if (unlikely(rc)) {
658 IWL_ERROR("TX reset failed");
659 spin_unlock_irqrestore(&priv->lock, flags);
660 goto error_reset;
661 }
662
8b6eaea8 663 /* Turn off all Tx DMA channels */
12a81f60 664 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
3395f6e9 665 iwl_release_nic_access(priv);
b481de9c
ZY		 666 spin_unlock_irqrestore(&priv->lock, flags);
667
8b6eaea8 668 /* Tell 4965 where to find the keep-warm buffer */
b481de9c
ZY		 669 rc = iwl4965_kw_init(priv);
670 if (rc) {
671 IWL_ERROR("kw_init failed\n");
672 goto error_reset;
673 }
674
8b6eaea8
CB		 675 /* Alloc and init all (default 16) Tx queues,
676 * including the command queue (#4) */
5425e490 677 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 678 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
679 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 680 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 681 txq_id);
682 if (rc) {
683 IWL_ERROR("Tx %d queue init failed\n", txq_id);
684 goto error;
685 }
686 }
687
688 return rc;
689
690 error:
bb8c093b 691 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 692 error_reset:
693 iwl4965_kw_free(priv);
694 error_kw:
695 return rc;
696}
91238714 697static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 698{
b481de9c 699 unsigned long flags;
91238714 700 int ret = 0;
b481de9c 701
b481de9c 702 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 703 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 704 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 705
91238714
TW		 706 /* set "initialization complete" bit to move adapter
707 * D0U* --> D0A* state */
3395f6e9 708 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 709
91238714
TW		 710 /* wait for clock stabilization */
711 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
712 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
713 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
714 if (ret < 0) {
715 IWL_DEBUG_INFO("Failed to init the card\n");
716 goto out;
b481de9c
ZY		 717 }
718
91238714
TW		 719 ret = iwl_grab_nic_access(priv);
720 if (ret)
721 goto out;
b481de9c 722
91238714 723 /* enable DMA */
3395f6e9
TW		 724 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
725 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 726
727 udelay(20);
728
3395f6e9 729 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 730 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 731
3395f6e9 732 iwl_release_nic_access(priv);
91238714
TW		 733out:
734 spin_unlock_irqrestore(&priv->lock, flags);
735 return ret;
736}
737
738int iwl4965_hw_nic_init(struct iwl_priv *priv)
739{
740 unsigned long flags;
741 struct iwl4965_rx_queue *rxq = &priv->rxq;
91238714
TW		 742 u8 val_link;
743 u32 val;
744 int ret;
745
746 /* nic_init */
747 priv->cfg->ops->lib->apm_ops.init(priv);
748
749 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 750 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
b481de9c
ZY		 751 spin_unlock_irqrestore(&priv->lock, flags);
752
91238714 753 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
6f4083aa 754
b481de9c
ZY		 755 spin_lock_irqsave(&priv->lock, flags);
756
b661c819 757 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
b481de9c
ZY		 758 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
759 /* Enable No Snoop field */
760 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
761 val & ~(1 << 11));
762 }
763
764 spin_unlock_irqrestore(&priv->lock, flags);
765
073d3f5f
TW		 766 if (iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET) <
767 EEPROM_4965_TX_POWER_VERSION) {
b481de9c
ZY		 768 IWL_ERROR("Older EEPROM detected! Aborting.\n");
769 return -EINVAL;
770 }
771
772 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
773
774 /* disable L1 entry -- workaround for pre-B1 */
775 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
776
777 spin_lock_irqsave(&priv->lock, flags);
778
779 /* set CSR_HW_CONFIG_REG for uCode use */
780
3395f6e9
TW		 781 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
782 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
783 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
784 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 785
91238714
TW		 786 ret = iwl_grab_nic_access(priv);
787 if (ret < 0) {
b481de9c
ZY		 788 spin_unlock_irqrestore(&priv->lock, flags);
789 IWL_DEBUG_INFO("Failed to init the card\n");
91238714 790 return ret;
b481de9c
ZY		 791 }
792
3395f6e9
TW		 793 iwl_read_prph(priv, APMG_PS_CTRL_REG);
794 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 795 udelay(5);
3395f6e9 796 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 797
3395f6e9 798 iwl_release_nic_access(priv);
b481de9c
ZY		 799 spin_unlock_irqrestore(&priv->lock, flags);
800
bb8c093b 801 iwl4965_hw_card_show_info(priv);
b481de9c
ZY		 802
803 /* end nic_init */
804
805 /* Allocate the RX queue, or reset if it is already allocated */
806 if (!rxq->bd) {
91238714
TW		 807 ret = iwl4965_rx_queue_alloc(priv);
808 if (ret) {
b481de9c
ZY		 809 IWL_ERROR("Unable to initialize Rx queue\n");
810 return -ENOMEM;
811 }
812 } else
bb8c093b 813 iwl4965_rx_queue_reset(priv, rxq);
b481de9c 814
bb8c093b 815 iwl4965_rx_replenish(priv);
b481de9c
ZY		 816
817 iwl4965_rx_init(priv, rxq);
818
819 spin_lock_irqsave(&priv->lock, flags);
820
821 rxq->need_update = 1;
bb8c093b 822 iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c 823
073d3f5f
TW		 824 /* init the txpower calibration pointer */
825 priv->calib_info = (struct iwl_eeprom_calib_info *)
826 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
827
b481de9c 828 spin_unlock_irqrestore(&priv->lock, flags);
8b6eaea8
CB		 829
830 /* Allocate and init all Tx and Command queues */
91238714
TW		 831 ret = iwl4965_txq_ctx_reset(priv);
832 if (ret)
833 return ret;
b481de9c
ZY		 834
835 set_bit(STATUS_INIT, &priv->status);
836
837 return 0;
838}
839
c79dd5b5 840int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 841{
842 int rc = 0;
843 u32 reg_val;
844 unsigned long flags;
845
846 spin_lock_irqsave(&priv->lock, flags);
847
848 /* set stop master bit */
3395f6e9 849 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 850
3395f6e9 851 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 852
853 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
854 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
855 IWL_DEBUG_INFO("Card in power save, master is already "
856 "stopped\n");
857 else {
3395f6e9 858 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 859 CSR_RESET_REG_FLAG_MASTER_DISABLED,
860 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
861 if (rc < 0) {
862 spin_unlock_irqrestore(&priv->lock, flags);
863 return rc;
864 }
865 }
866
867 spin_unlock_irqrestore(&priv->lock, flags);
868 IWL_DEBUG_INFO("stop master\n");
869
870 return rc;
871}
872
8b6eaea8
CB		 873/**
874 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
875 */
c79dd5b5 876void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c
ZY		 877{
878
879 int txq_id;
880 unsigned long flags;
881
8b6eaea8 882 /* Stop each Tx DMA channel, and wait for it to be idle */
5425e490 883 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c 884 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 885 if (iwl_grab_nic_access(priv)) {
b481de9c
ZY		 886 spin_unlock_irqrestore(&priv->lock, flags);
887 continue;
888 }
889
3395f6e9
TW		 890 iwl_write_direct32(priv,
891 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
892 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
893 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
894 (txq_id), 200);
895 iwl_release_nic_access(priv);
b481de9c
ZY		 896 spin_unlock_irqrestore(&priv->lock, flags);
897 }
898
8b6eaea8 899 /* Deallocate memory for all Tx queues */
bb8c093b 900 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 901}
902
c79dd5b5 903int iwl4965_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 904{
905 int rc = 0;
906 unsigned long flags;
907
bb8c093b 908 iwl4965_hw_nic_stop_master(priv);
b481de9c
ZY		 909
910 spin_lock_irqsave(&priv->lock, flags);
911
3395f6e9 912 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 913
914 udelay(10);
915
3395f6e9
TW		 916 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
917 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 918 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
919 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
920
921 udelay(10);
922
3395f6e9 923 rc = iwl_grab_nic_access(priv);
b481de9c 924 if (!rc) {
3395f6e9
TW		 925 iwl_write_prph(priv, APMG_CLK_EN_REG,
926 APMG_CLK_VAL_DMA_CLK_RQT |
927 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 928
929 udelay(10);
930
3395f6e9
TW		 931 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
932 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 933
3395f6e9 934 iwl_release_nic_access(priv);
b481de9c
ZY		 935 }
936
937 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
938 wake_up_interruptible(&priv->wait_command_queue);
939
940 spin_unlock_irqrestore(&priv->lock, flags);
941
942 return rc;
943
944}
945
946#define REG_RECALIB_PERIOD (60)
947
948/**
949 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
950 *
49ea8596 951 * This callback is provided in order to send a statistics request.
b481de9c
ZY		 952 *
953 * This timer function is continually reset to execute within
954 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
955 * was received. We need to ensure we receive the statistics in order
49ea8596 956 * to update the temperature used for calibrating the TXPOWER.
b481de9c
ZY		 957 */
958static void iwl4965_bg_statistics_periodic(unsigned long data)
959{
c79dd5b5 960 struct iwl_priv *priv = (struct iwl_priv *)data;
b481de9c 961
b481de9c
ZY		 962 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
963 return;
964
49ea8596 965 iwl_send_statistics_request(priv, CMD_ASYNC);
b481de9c
ZY		 966}
967
c79dd5b5 968void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 969{
bb8c093b 970 struct iwl4965_ct_kill_config cmd;
b481de9c 971 unsigned long flags;
857485c0 972 int ret = 0;
b481de9c
ZY		 973
974 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 975 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 976 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
977 spin_unlock_irqrestore(&priv->lock, flags);
978
099b40b7 979 cmd.critical_temperature_R =
b73cdf27
EG		 980 cpu_to_le32(priv->hw_params.ct_kill_threshold);
981
857485c0
TW		 982 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
983 sizeof(cmd), &cmd);
984 if (ret)
b481de9c
ZY		 985 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
986 else
b73cdf27
EG		 987 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
988 "critical temperature is %d\n",
989 cmd.critical_temperature_R);
b481de9c
ZY		 990}
991
f0832f13 992#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 993
994/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
995 * Called after every association, but this runs only once!
996 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 997static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 998{
f0832f13 999 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 1000
3109ece1 1001 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 1002 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1003
1004 memset(&cmd, 0, sizeof(cmd));
1005 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1006 cmd.diff_gain_a = 0;
1007 cmd.diff_gain_b = 0;
1008 cmd.diff_gain_c = 0;
f0832f13
EG		 1009 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1010 sizeof(cmd), &cmd))
1011 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 1012 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1013 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1014 }
b481de9c
ZY		 1015}
1016
f0832f13
EG		 1017static void iwl4965_gain_computation(struct iwl_priv *priv,
1018 u32 *average_noise,
1019 u16 min_average_noise_antenna_i,
1020 u32 min_average_noise)
b481de9c 1021{
f0832f13
EG		 1022 int i, ret;
1023 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 1024
f0832f13 1025 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 1026
f0832f13
EG		 1027 for (i = 0; i < NUM_RX_CHAINS; i++) {
1028 s32 delta_g = 0;
b481de9c 1029
f0832f13
EG		 1030 if (!(data->disconn_array[i]) &&
1031 (data->delta_gain_code[i] ==
b481de9c 1032 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 1033 delta_g = average_noise[i] - min_average_noise;
1034 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
1035 data->delta_gain_code[i] =
1036 min(data->delta_gain_code[i],
1037 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
1038
1039 data->delta_gain_code[i] =
1040 (data->delta_gain_code[i] | (1 << 2));
1041 } else {
1042 data->delta_gain_code[i] = 0;
b481de9c 1043 }
b481de9c 1044 }
f0832f13
EG		 1045 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1046 data->delta_gain_code[0],
1047 data->delta_gain_code[1],
1048 data->delta_gain_code[2]);
b481de9c 1049
f0832f13
EG		 1050 /* Differential gain gets sent to uCode only once */
1051 if (!data->radio_write) {
1052 struct iwl4965_calibration_cmd cmd;
1053 data->radio_write = 1;
b481de9c 1054
f0832f13
EG		 1055 memset(&cmd, 0, sizeof(cmd));
1056 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1057 cmd.diff_gain_a = data->delta_gain_code[0];
1058 cmd.diff_gain_b = data->delta_gain_code[1];
1059 cmd.diff_gain_c = data->delta_gain_code[2];
1060 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1061 sizeof(cmd), &cmd);
1062 if (ret)
1063 IWL_DEBUG_CALIB("fail sending cmd "
1064 "REPLY_PHY_CALIBRATION_CMD \n");
1065
1066 /* TODO we might want recalculate
1067 * rx_chain in rxon cmd */
1068
1069 /* Mark so we run this algo only once! */
1070 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 1071 }
f0832f13
EG		 1072 data->chain_noise_a = 0;
1073 data->chain_noise_b = 0;
1074 data->chain_noise_c = 0;
1075 data->chain_signal_a = 0;
1076 data->chain_signal_b = 0;
1077 data->chain_signal_c = 0;
1078 data->beacon_count = 0;
b481de9c
ZY		 1079}
1080
1081static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1082{
c79dd5b5 1083 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1084 sensitivity_work);
1085
1086 mutex_lock(&priv->mutex);
1087
1088 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1089 test_bit(STATUS_SCANNING, &priv->status)) {
1090 mutex_unlock(&priv->mutex);
1091 return;
1092 }
1093
1094 if (priv->start_calib) {
f0832f13
EG		 1095 iwl_chain_noise_calibration(priv, &priv->statistics);
1096
1097 iwl_sensitivity_calibration(priv, &priv->statistics);
b481de9c
ZY		 1098 }
1099
1100 mutex_unlock(&priv->mutex);
1101 return;
1102}
f0832f13 1103#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c
ZY		 1104
1105static void iwl4965_bg_txpower_work(struct work_struct *work)
1106{
c79dd5b5 1107 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1108 txpower_work);
1109
1110 /* If a scan happened to start before we got here
1111 * then just return; the statistics notification will
1112 * kick off another scheduled work to compensate for
1113 * any temperature delta we missed here. */
1114 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1115 test_bit(STATUS_SCANNING, &priv->status))
1116 return;
1117
1118 mutex_lock(&priv->mutex);
1119
1120 /* Regardless of if we are assocaited, we must reconfigure the
1121 * TX power since frames can be sent on non-radar channels while
1122 * not associated */
bb8c093b 1123 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 1124
1125 /* Update last_temperature to keep is_calib_needed from running
1126 * when it isn't needed... */
1127 priv->last_temperature = priv->temperature;
1128
1129 mutex_unlock(&priv->mutex);
1130}
1131
1132/*
1133 * Acquire priv->lock before calling this function !
1134 */
c79dd5b5 1135static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 1136{
3395f6e9 1137 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 1138 (index & 0xff) | (txq_id << 8));
12a81f60 1139 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 1140}
1141
8b6eaea8
CB		 1142/**
1143 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1144 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1145 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1146 *
1147 * NOTE: Acquire priv->lock before calling this function !
b481de9c 1148 */
c79dd5b5 1149static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
bb8c093b 1150 struct iwl4965_tx_queue *txq,
b481de9c
ZY		 1151 int tx_fifo_id, int scd_retry)
1152{
1153 int txq_id = txq->q.id;
8b6eaea8
CB		 1154
1155 /* Find out whether to activate Tx queue */
b481de9c
ZY		 1156 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1157
8b6eaea8 1158 /* Set up and activate */
12a81f60 1159 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
b481de9c
ZY		 1160 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1161 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1162 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1163 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1164 SCD_QUEUE_STTS_REG_MSK);
1165
1166 txq->sched_retry = scd_retry;
1167
1168 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 1169 active ? "Activate" : "Deactivate",
b481de9c
ZY		 1170 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1171}
1172
1173static const u16 default_queue_to_tx_fifo[] = {
1174 IWL_TX_FIFO_AC3,
1175 IWL_TX_FIFO_AC2,
1176 IWL_TX_FIFO_AC1,
1177 IWL_TX_FIFO_AC0,
1178 IWL_CMD_FIFO_NUM,
1179 IWL_TX_FIFO_HCCA_1,
1180 IWL_TX_FIFO_HCCA_2
1181};
1182
c79dd5b5 1183static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1184{
1185 set_bit(txq_id, &priv->txq_ctx_active_msk);
1186}
1187
c79dd5b5 1188static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1189{
1190 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1191}
1192
c79dd5b5 1193int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 1194{
1195 u32 a;
1196 int i = 0;
1197 unsigned long flags;
857485c0 1198 int ret;
b481de9c
ZY		 1199
1200 spin_lock_irqsave(&priv->lock, flags);
1201
f0832f13 1202#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c 1203 memset(&(priv->sensitivity_data), 0,
f0832f13 1204 sizeof(struct iwl_sensitivity_data));
b481de9c 1205 memset(&(priv->chain_noise_data), 0,
f0832f13 1206 sizeof(struct iwl_chain_noise_data));
b481de9c
ZY		 1207 for (i = 0; i < NUM_RX_CHAINS; i++)
1208 priv->chain_noise_data.delta_gain_code[i] =
1209 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
f0832f13 1210#endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
3395f6e9 1211 ret = iwl_grab_nic_access(priv);
857485c0 1212 if (ret) {
b481de9c 1213 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 1214 return ret;
b481de9c
ZY		 1215 }
1216
8b6eaea8 1217 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 1218 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
b481de9c
ZY		 1219 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1220 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 1221 iwl_write_targ_mem(priv, a, 0);
b481de9c 1222 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 1223 iwl_write_targ_mem(priv, a, 0);
5425e490 1224 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 1225 iwl_write_targ_mem(priv, a, 0);
b481de9c 1226
8b6eaea8 1227 /* Tel 4965 where to find Tx byte count tables */
12a81f60 1228 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 1229 (priv->shared_phys +
bb8c093b 1230 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 1231
1232 /* Disable chain mode for all queues */
12a81f60 1233 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 1234
8b6eaea8 1235 /* Initialize each Tx queue (including the command queue) */
5425e490 1236 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 1237
1238 /* TFD circular buffer read/write indexes */
12a81f60 1239 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 1240 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 1241
1242 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 1243 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1244 SCD_CONTEXT_QUEUE_OFFSET(i),
1245 (SCD_WIN_SIZE <<
1246 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1247 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 1248
1249 /* Frame limit */
3395f6e9 1250 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1251 SCD_CONTEXT_QUEUE_OFFSET(i) +
1252 sizeof(u32),
1253 (SCD_FRAME_LIMIT <<
1254 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1255 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1256
1257 }
12a81f60 1258 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 1259 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 1260
8b6eaea8 1261 /* Activate all Tx DMA/FIFO channels */
12a81f60 1262 iwl_write_prph(priv, IWL49_SCD_TXFACT,
b481de9c
ZY		 1263 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1264
1265 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 1266
1267 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 1268 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1269 int ac = default_queue_to_tx_fifo[i];
1270 iwl4965_txq_ctx_activate(priv, i);
1271 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1272 }
1273
3395f6e9 1274 iwl_release_nic_access(priv);
b481de9c
ZY		 1275 spin_unlock_irqrestore(&priv->lock, flags);
1276
49ea8596
EG		 1277 /* Ask for statistics now, the uCode will send statistics notification
1278 * periodically after association */
1279 iwl_send_statistics_request(priv, CMD_ASYNC);
857485c0 1280 return ret;
b481de9c
ZY		 1281}
1282
f0832f13
EG		 1283#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1284static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1285 .min_nrg_cck = 97,
1286 .max_nrg_cck = 0,
1287
1288 .auto_corr_min_ofdm = 85,
1289 .auto_corr_min_ofdm_mrc = 170,
1290 .auto_corr_min_ofdm_x1 = 105,
1291 .auto_corr_min_ofdm_mrc_x1 = 220,
1292
1293 .auto_corr_max_ofdm = 120,
1294 .auto_corr_max_ofdm_mrc = 210,
1295 .auto_corr_max_ofdm_x1 = 140,
1296 .auto_corr_max_ofdm_mrc_x1 = 270,
1297
1298 .auto_corr_min_cck = 125,
1299 .auto_corr_max_cck = 200,
1300 .auto_corr_min_cck_mrc = 200,
1301 .auto_corr_max_cck_mrc = 400,
1302
1303 .nrg_th_cck = 100,
1304 .nrg_th_ofdm = 100,
1305};
1306#endif
1307
8b6eaea8 1308/**
5425e490 1309 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 1310 *
1311 * Called when initializing driver
1312 */
5425e490 1313int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 1314{
316c30d9 1315
dfe7d458 1316 if ((priv->cfg->mod_params->num_of_queues > IWL4965_MAX_NUM_QUEUES) ||
1ea87396 1317 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 1318 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 1319 IWL_MIN_NUM_QUEUES, IWL4965_MAX_NUM_QUEUES);
059ff826 1320 return -EINVAL;
316c30d9 1321 }
b481de9c 1322
5425e490 1323 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
099b40b7 1324 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
5425e490
TW		 1325 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1326 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1327 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 1328 if (priv->cfg->mod_params->amsdu_size_8K)
5425e490 1329 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
9ee1ba47 1330 else
5425e490
TW		 1331 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1332 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1333 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1334 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822 1335
099b40b7
RR		 1336 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1337 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1338 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1339 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1340
ec35cf2a
TW		 1341 priv->hw_params.tx_chains_num = 2;
1342 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 1343 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
1344 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 1345 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1346
f0832f13
EG		 1347#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1348 priv->hw_params.sens = &iwl4965_sensitivity;
1349#endif
3e82a822 1350
059ff826 1351 return 0;
b481de9c
ZY		 1352}
1353
1354/**
bb8c093b 1355 * iwl4965_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1356 *
1357 * Destroy all TX DMA queues and structures
1358 */
c79dd5b5 1359void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1360{
1361 int txq_id;
1362
1363 /* Tx queues */
5425e490 1364 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
bb8c093b 1365 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c 1366
8b6eaea8 1367 /* Keep-warm buffer */
b481de9c
ZY		 1368 iwl4965_kw_free(priv);
1369}
1370
1371/**
8b6eaea8 1372 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
b481de9c 1373 *
8b6eaea8
CB		 1374 * Does NOT advance any TFD circular buffer read/write indexes
1375 * Does NOT free the TFD itself (which is within circular buffer)
b481de9c 1376 */
c79dd5b5 1377int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 1378{
bb8c093b
CH		 1379 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1380 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 1381 struct pci_dev *dev = priv->pci_dev;
1382 int i;
1383 int counter = 0;
1384 int index, is_odd;
1385
8b6eaea8 1386 /* Host command buffers stay mapped in memory, nothing to clean */
b481de9c 1387 if (txq->q.id == IWL_CMD_QUEUE_NUM)
b481de9c
ZY		 1388 return 0;
1389
8b6eaea8 1390 /* Sanity check on number of chunks */
b481de9c
ZY		 1391 counter = IWL_GET_BITS(*bd, num_tbs);
1392 if (counter > MAX_NUM_OF_TBS) {
1393 IWL_ERROR("Too many chunks: %i\n", counter);
1394 /* @todo issue fatal error, it is quite serious situation */
1395 return 0;
1396 }
1397
8b6eaea8
CB		 1398 /* Unmap chunks, if any.
1399 * TFD info for odd chunks is different format than for even chunks. */
b481de9c
ZY		 1400 for (i = 0; i < counter; i++) {
1401 index = i / 2;
1402 is_odd = i & 0x1;
1403
1404 if (is_odd)
1405 pci_unmap_single(
1406 dev,
1407 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1408 (IWL_GET_BITS(bd->pa[index],
1409 tb2_addr_hi20) << 16),
1410 IWL_GET_BITS(bd->pa[index], tb2_len),
1411 PCI_DMA_TODEVICE);
1412
1413 else if (i > 0)
1414 pci_unmap_single(dev,
1415 le32_to_cpu(bd->pa[index].tb1_addr),
1416 IWL_GET_BITS(bd->pa[index], tb1_len),
1417 PCI_DMA_TODEVICE);
1418
8b6eaea8 1419 /* Free SKB, if any, for this chunk */
fc4b6853
TW		 1420 if (txq->txb[txq->q.read_ptr].skb[i]) {
1421 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
b481de9c
ZY		 1422
1423 dev_kfree_skb(skb);
fc4b6853 1424 txq->txb[txq->q.read_ptr].skb[i] = NULL;
b481de9c
ZY		 1425 }
1426 }
1427 return 0;
1428}
1429
5da4b55f
MA		 1430/* set card power command */
1431static int iwl4965_set_power(struct iwl_priv *priv,
1432 void *cmd)
1433{
1434 int ret = 0;
1435
1436 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1437 sizeof(struct iwl4965_powertable_cmd),
1438 cmd, NULL);
1439 return ret;
1440}
c79dd5b5 1441int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1442{
bb8c093b 1443 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
b481de9c
ZY		 1444 return -EINVAL;
1445}
1446
1447static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1448{
1449 s32 sign = 1;
1450
1451 if (num < 0) {
1452 sign = -sign;
1453 num = -num;
1454 }
1455 if (denom < 0) {
1456 sign = -sign;
1457 denom = -denom;
1458 }
1459 *res = 1;
1460 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1461
1462 return 1;
1463}
1464
8b6eaea8
CB		 1465/**
1466 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1467 *
1468 * Determines power supply voltage compensation for txpower calculations.
1469 * Returns number of 1/2-dB steps to subtract from gain table index,
1470 * to compensate for difference between power supply voltage during
1471 * factory measurements, vs. current power supply voltage.
1472 *
1473 * Voltage indication is higher for lower voltage.
1474 * Lower voltage requires more gain (lower gain table index).
1475 */
b481de9c
ZY		 1476static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1477 s32 current_voltage)
1478{
1479 s32 comp = 0;
1480
1481 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1482 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1483 return 0;
1484
1485 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1486 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1487
1488 if (current_voltage > eeprom_voltage)
1489 comp *= 2;
1490 if ((comp < -2) || (comp > 2))
1491 comp = 0;
1492
1493 return comp;
1494}
1495
bf85ea4f 1496static const struct iwl_channel_info *
c79dd5b5 1497iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
8318d78a 1498 enum ieee80211_band band, u16 channel)
b481de9c 1499{
bf85ea4f 1500 const struct iwl_channel_info *ch_info;
b481de9c 1501
8622e705 1502 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 1503
1504 if (!is_channel_valid(ch_info))
1505 return NULL;
1506
1507 return ch_info;
1508}
1509
1510static s32 iwl4965_get_tx_atten_grp(u16 channel)
1511{
1512 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1513 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1514 return CALIB_CH_GROUP_5;
1515
1516 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1517 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1518 return CALIB_CH_GROUP_1;
1519
1520 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1521 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1522 return CALIB_CH_GROUP_2;
1523
1524 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1525 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1526 return CALIB_CH_GROUP_3;
1527
1528 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1529 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1530 return CALIB_CH_GROUP_4;
1531
1532 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1533 return -1;
1534}
1535
c79dd5b5 1536static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 1537{
1538 s32 b = -1;
1539
1540 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 1541 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 1542 continue;
1543
073d3f5f
TW		 1544 if ((channel >= priv->calib_info->band_info[b].ch_from)
1545 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 1546 break;
1547 }
1548
1549 return b;
1550}
1551
1552static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1553{
1554 s32 val;
1555
1556 if (x2 == x1)
1557 return y1;
1558 else {
1559 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1560 return val + y2;
1561 }
1562}
1563
8b6eaea8
CB		 1564/**
1565 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1566 *
1567 * Interpolates factory measurements from the two sample channels within a
1568 * sub-band, to apply to channel of interest. Interpolation is proportional to
1569 * differences in channel frequencies, which is proportional to differences
1570 * in channel number.
1571 */
c79dd5b5 1572static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 1573 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 1574{
1575 s32 s = -1;
1576 u32 c;
1577 u32 m;
073d3f5f
TW		 1578 const struct iwl_eeprom_calib_measure *m1;
1579 const struct iwl_eeprom_calib_measure *m2;
1580 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 1581 u32 ch_i1;
1582 u32 ch_i2;
1583
1584 s = iwl4965_get_sub_band(priv, channel);
1585 if (s >= EEPROM_TX_POWER_BANDS) {
1586 IWL_ERROR("Tx Power can not find channel %d ", channel);
1587 return -1;
1588 }
1589
073d3f5f
TW		 1590 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1591 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 1592 chan_info->ch_num = (u8) channel;
1593
1594 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1595 channel, s, ch_i1, ch_i2);
1596
1597 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1598 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 1599 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 1600 measurements[c][m]);
073d3f5f 1601 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 1602 measurements[c][m]);
1603 omeas = &(chan_info->measurements[c][m]);
1604
1605 omeas->actual_pow =
1606 (u8) iwl4965_interpolate_value(channel, ch_i1,
1607 m1->actual_pow,
1608 ch_i2,
1609 m2->actual_pow);
1610 omeas->gain_idx =
1611 (u8) iwl4965_interpolate_value(channel, ch_i1,
1612 m1->gain_idx, ch_i2,
1613 m2->gain_idx);
1614 omeas->temperature =
1615 (u8) iwl4965_interpolate_value(channel, ch_i1,
1616 m1->temperature,
1617 ch_i2,
1618 m2->temperature);
1619 omeas->pa_det =
1620 (s8) iwl4965_interpolate_value(channel, ch_i1,
1621 m1->pa_det, ch_i2,
1622 m2->pa_det);
1623
1624 IWL_DEBUG_TXPOWER
1625 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1626 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1627 IWL_DEBUG_TXPOWER
1628 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1629 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1630 IWL_DEBUG_TXPOWER
1631 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1632 m1->pa_det, m2->pa_det, omeas->pa_det);
1633 IWL_DEBUG_TXPOWER
1634 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1635 m1->temperature, m2->temperature,
1636 omeas->temperature);
1637 }
1638 }
1639
1640 return 0;
1641}
1642
1643/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1644 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1645static s32 back_off_table[] = {
1646 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1647 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1648 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1649 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1650 10 /* CCK */
1651};
1652
1653/* Thermal compensation values for txpower for various frequency ranges ...
1654 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1655static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1656 s32 degrees_per_05db_a;
1657 s32 degrees_per_05db_a_denom;
1658} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1659 {9, 2}, /* group 0 5.2, ch 34-43 */
1660 {4, 1}, /* group 1 5.2, ch 44-70 */
1661 {4, 1}, /* group 2 5.2, ch 71-124 */
1662 {4, 1}, /* group 3 5.2, ch 125-200 */
1663 {3, 1} /* group 4 2.4, ch all */
1664};
1665
1666static s32 get_min_power_index(s32 rate_power_index, u32 band)
1667{
1668 if (!band) {
1669 if ((rate_power_index & 7) <= 4)
1670 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1671 }
1672 return MIN_TX_GAIN_INDEX;
1673}
1674
1675struct gain_entry {
1676 u8 dsp;
1677 u8 radio;
1678};
1679
1680static const struct gain_entry gain_table[2][108] = {
1681 /* 5.2GHz power gain index table */
1682 {
1683 {123, 0x3F}, /* highest txpower */
1684 {117, 0x3F},
1685 {110, 0x3F},
1686 {104, 0x3F},
1687 {98, 0x3F},
1688 {110, 0x3E},
1689 {104, 0x3E},
1690 {98, 0x3E},
1691 {110, 0x3D},
1692 {104, 0x3D},
1693 {98, 0x3D},
1694 {110, 0x3C},
1695 {104, 0x3C},
1696 {98, 0x3C},
1697 {110, 0x3B},
1698 {104, 0x3B},
1699 {98, 0x3B},
1700 {110, 0x3A},
1701 {104, 0x3A},
1702 {98, 0x3A},
1703 {110, 0x39},
1704 {104, 0x39},
1705 {98, 0x39},
1706 {110, 0x38},
1707 {104, 0x38},
1708 {98, 0x38},
1709 {110, 0x37},
1710 {104, 0x37},
1711 {98, 0x37},
1712 {110, 0x36},
1713 {104, 0x36},
1714 {98, 0x36},
1715 {110, 0x35},
1716 {104, 0x35},
1717 {98, 0x35},
1718 {110, 0x34},
1719 {104, 0x34},
1720 {98, 0x34},
1721 {110, 0x33},
1722 {104, 0x33},
1723 {98, 0x33},
1724 {110, 0x32},
1725 {104, 0x32},
1726 {98, 0x32},
1727 {110, 0x31},
1728 {104, 0x31},
1729 {98, 0x31},
1730 {110, 0x30},
1731 {104, 0x30},
1732 {98, 0x30},
1733 {110, 0x25},
1734 {104, 0x25},
1735 {98, 0x25},
1736 {110, 0x24},
1737 {104, 0x24},
1738 {98, 0x24},
1739 {110, 0x23},
1740 {104, 0x23},
1741 {98, 0x23},
1742 {110, 0x22},
1743 {104, 0x18},
1744 {98, 0x18},
1745 {110, 0x17},
1746 {104, 0x17},
1747 {98, 0x17},
1748 {110, 0x16},
1749 {104, 0x16},
1750 {98, 0x16},
1751 {110, 0x15},
1752 {104, 0x15},
1753 {98, 0x15},
1754 {110, 0x14},
1755 {104, 0x14},
1756 {98, 0x14},
1757 {110, 0x13},
1758 {104, 0x13},
1759 {98, 0x13},
1760 {110, 0x12},
1761 {104, 0x08},
1762 {98, 0x08},
1763 {110, 0x07},
1764 {104, 0x07},
1765 {98, 0x07},
1766 {110, 0x06},
1767 {104, 0x06},
1768 {98, 0x06},
1769 {110, 0x05},
1770 {104, 0x05},
1771 {98, 0x05},
1772 {110, 0x04},
1773 {104, 0x04},
1774 {98, 0x04},
1775 {110, 0x03},
1776 {104, 0x03},
1777 {98, 0x03},
1778 {110, 0x02},
1779 {104, 0x02},
1780 {98, 0x02},
1781 {110, 0x01},
1782 {104, 0x01},
1783 {98, 0x01},
1784 {110, 0x00},
1785 {104, 0x00},
1786 {98, 0x00},
1787 {93, 0x00},
1788 {88, 0x00},
1789 {83, 0x00},
1790 {78, 0x00},
1791 },
1792 /* 2.4GHz power gain index table */
1793 {
1794 {110, 0x3f}, /* highest txpower */
1795 {104, 0x3f},
1796 {98, 0x3f},
1797 {110, 0x3e},
1798 {104, 0x3e},
1799 {98, 0x3e},
1800 {110, 0x3d},
1801 {104, 0x3d},
1802 {98, 0x3d},
1803 {110, 0x3c},
1804 {104, 0x3c},
1805 {98, 0x3c},
1806 {110, 0x3b},
1807 {104, 0x3b},
1808 {98, 0x3b},
1809 {110, 0x3a},
1810 {104, 0x3a},
1811 {98, 0x3a},
1812 {110, 0x39},
1813 {104, 0x39},
1814 {98, 0x39},
1815 {110, 0x38},
1816 {104, 0x38},
1817 {98, 0x38},
1818 {110, 0x37},
1819 {104, 0x37},
1820 {98, 0x37},
1821 {110, 0x36},
1822 {104, 0x36},
1823 {98, 0x36},
1824 {110, 0x35},
1825 {104, 0x35},
1826 {98, 0x35},
1827 {110, 0x34},
1828 {104, 0x34},
1829 {98, 0x34},
1830 {110, 0x33},
1831 {104, 0x33},
1832 {98, 0x33},
1833 {110, 0x32},
1834 {104, 0x32},
1835 {98, 0x32},
1836 {110, 0x31},
1837 {104, 0x31},
1838 {98, 0x31},
1839 {110, 0x30},
1840 {104, 0x30},
1841 {98, 0x30},
1842 {110, 0x6},
1843 {104, 0x6},
1844 {98, 0x6},
1845 {110, 0x5},
1846 {104, 0x5},
1847 {98, 0x5},
1848 {110, 0x4},
1849 {104, 0x4},
1850 {98, 0x4},
1851 {110, 0x3},
1852 {104, 0x3},
1853 {98, 0x3},
1854 {110, 0x2},
1855 {104, 0x2},
1856 {98, 0x2},
1857 {110, 0x1},
1858 {104, 0x1},
1859 {98, 0x1},
1860 {110, 0x0},
1861 {104, 0x0},
1862 {98, 0x0},
1863 {97, 0},
1864 {96, 0},
1865 {95, 0},
1866 {94, 0},
1867 {93, 0},
1868 {92, 0},
1869 {91, 0},
1870 {90, 0},
1871 {89, 0},
1872 {88, 0},
1873 {87, 0},
1874 {86, 0},
1875 {85, 0},
1876 {84, 0},
1877 {83, 0},
1878 {82, 0},
1879 {81, 0},
1880 {80, 0},
1881 {79, 0},
1882 {78, 0},
1883 {77, 0},
1884 {76, 0},
1885 {75, 0},
1886 {74, 0},
1887 {73, 0},
1888 {72, 0},
1889 {71, 0},
1890 {70, 0},
1891 {69, 0},
1892 {68, 0},
1893 {67, 0},
1894 {66, 0},
1895 {65, 0},
1896 {64, 0},
1897 {63, 0},
1898 {62, 0},
1899 {61, 0},
1900 {60, 0},
1901 {59, 0},
1902 }
1903};
1904
c79dd5b5 1905static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1906 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1907 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1908{
1909 u8 saturation_power;
1910 s32 target_power;
1911 s32 user_target_power;
1912 s32 power_limit;
1913 s32 current_temp;
1914 s32 reg_limit;
1915 s32 current_regulatory;
1916 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1917 int i;
1918 int c;
bf85ea4f 1919 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1920 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1921 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1922 s16 voltage;
1923 s32 init_voltage;
1924 s32 voltage_compensation;
1925 s32 degrees_per_05db_num;
1926 s32 degrees_per_05db_denom;
1927 s32 factory_temp;
1928 s32 temperature_comp[2];
1929 s32 factory_gain_index[2];
1930 s32 factory_actual_pwr[2];
1931 s32 power_index;
1932
1933 /* Sanity check requested level (dBm) */
1934 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1935 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1936 priv->user_txpower_limit);
1937 return -EINVAL;
1938 }
1939 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1940 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1941 priv->user_txpower_limit);
1942 return -EINVAL;
1943 }
1944
1945 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1946 * are used for indexing into txpower table) */
1947 user_target_power = 2 * priv->user_txpower_limit;
1948
1949 /* Get current (RXON) channel, band, width */
1950 ch_info =
8318d78a 1951 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
b481de9c
ZY		 1952
1953 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1954 is_fat);
1955
1956 if (!ch_info)
1957 return -EINVAL;
1958
1959 /* get txatten group, used to select 1) thermal txpower adjustment
1960 * and 2) mimo txpower balance between Tx chains. */
1961 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1962 if (txatten_grp < 0)
1963 return -EINVAL;
1964
1965 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1966 channel, txatten_grp);
1967
1968 if (is_fat) {
1969 if (ctrl_chan_high)
1970 channel -= 2;
1971 else
1972 channel += 2;
1973 }
1974
1975 /* hardware txpower limits ...
1976 * saturation (clipping distortion) txpowers are in half-dBm */
1977 if (band)
073d3f5f 1978 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1979 else
073d3f5f 1980 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1981
1982 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1983 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1984 if (band)
1985 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1986 else
1987 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1988 }
1989
1990 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1991 * max_power_avg values are in dBm, convert * 2 */
1992 if (is_fat)
1993 reg_limit = ch_info->fat_max_power_avg * 2;
1994 else
1995 reg_limit = ch_info->max_power_avg * 2;
1996
1997 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1998 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1999 if (band)
2000 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2001 else
2002 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2003 }
2004
2005 /* Interpolate txpower calibration values for this channel,
2006 * based on factory calibration tests on spaced channels. */
2007 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2008
2009 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 2010 voltage = priv->calib_info->voltage;
b481de9c
ZY		 2011 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2012 voltage_compensation =
2013 iwl4965_get_voltage_compensation(voltage, init_voltage);
2014
2015 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2016 init_voltage,
2017 voltage, voltage_compensation);
2018
2019 /* get current temperature (Celsius) */
2020 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2021 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2022 current_temp = KELVIN_TO_CELSIUS(current_temp);
2023
2024 /* select thermal txpower adjustment params, based on channel group
2025 * (same frequency group used for mimo txatten adjustment) */
2026 degrees_per_05db_num =
2027 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2028 degrees_per_05db_denom =
2029 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2030
2031 /* get per-chain txpower values from factory measurements */
2032 for (c = 0; c < 2; c++) {
2033 measurement = &ch_eeprom_info.measurements[c][1];
2034
2035 /* txgain adjustment (in half-dB steps) based on difference
2036 * between factory and current temperature */
2037 factory_temp = measurement->temperature;
2038 iwl4965_math_div_round((current_temp - factory_temp) *
2039 degrees_per_05db_denom,
2040 degrees_per_05db_num,
2041 &temperature_comp[c]);
2042
2043 factory_gain_index[c] = measurement->gain_idx;
2044 factory_actual_pwr[c] = measurement->actual_pow;
2045
2046 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2047 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2048 "curr tmp %d, comp %d steps\n",
2049 factory_temp, current_temp,
2050 temperature_comp[c]);
2051
2052 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2053 factory_gain_index[c],
2054 factory_actual_pwr[c]);
2055 }
2056
2057 /* for each of 33 bit-rates (including 1 for CCK) */
2058 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2059 u8 is_mimo_rate;
bb8c093b 2060 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 2061
2062 /* for mimo, reduce each chain's txpower by half
2063 * (3dB, 6 steps), so total output power is regulatory
2064 * compliant. */
2065 if (i & 0x8) {
2066 current_regulatory = reg_limit -
2067 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2068 is_mimo_rate = 1;
2069 } else {
2070 current_regulatory = reg_limit;
2071 is_mimo_rate = 0;
2072 }
2073
2074 /* find txpower limit, either hardware or regulatory */
2075 power_limit = saturation_power - back_off_table[i];
2076 if (power_limit > current_regulatory)
2077 power_limit = current_regulatory;
2078
2079 /* reduce user's txpower request if necessary
2080 * for this rate on this channel */
2081 target_power = user_target_power;
2082 if (target_power > power_limit)
2083 target_power = power_limit;
2084
2085 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2086 i, saturation_power - back_off_table[i],
2087 current_regulatory, user_target_power,
2088 target_power);
2089
2090 /* for each of 2 Tx chains (radio transmitters) */
2091 for (c = 0; c < 2; c++) {
2092 s32 atten_value;
2093
2094 if (is_mimo_rate)
2095 atten_value =
2096 (s32)le32_to_cpu(priv->card_alive_init.
2097 tx_atten[txatten_grp][c]);
2098 else
2099 atten_value = 0;
2100
2101 /* calculate index; higher index means lower txpower */
2102 power_index = (u8) (factory_gain_index[c] -
2103 (target_power -
2104 factory_actual_pwr[c]) -
2105 temperature_comp[c] -
2106 voltage_compensation +
2107 atten_value);
2108
2109/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2110 power_index); */
2111
2112 if (power_index < get_min_power_index(i, band))
2113 power_index = get_min_power_index(i, band);
2114
2115 /* adjust 5 GHz index to support negative indexes */
2116 if (!band)
2117 power_index += 9;
2118
2119 /* CCK, rate 32, reduce txpower for CCK */
2120 if (i == POWER_TABLE_CCK_ENTRY)
2121 power_index +=
2122 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2123
2124 /* stay within the table! */
2125 if (power_index > 107) {
2126 IWL_WARNING("txpower index %d > 107\n",
2127 power_index);
2128 power_index = 107;
2129 }
2130 if (power_index < 0) {
2131 IWL_WARNING("txpower index %d < 0\n",
2132 power_index);
2133 power_index = 0;
2134 }
2135
2136 /* fill txpower command for this rate/chain */
2137 tx_power.s.radio_tx_gain[c] =
2138 gain_table[band][power_index].radio;
2139 tx_power.s.dsp_predis_atten[c] =
2140 gain_table[band][power_index].dsp;
2141
2142 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2143 "gain 0x%02x dsp %d\n",
2144 c, atten_value, power_index,
2145 tx_power.s.radio_tx_gain[c],
2146 tx_power.s.dsp_predis_atten[c]);
2147 }/* for each chain */
2148
2149 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2150
2151 }/* for each rate */
2152
2153 return 0;
2154}
2155
2156/**
bb8c093b 2157 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
b481de9c
ZY		 2158 *
2159 * Uses the active RXON for channel, band, and characteristics (fat, high)
2160 * The power limit is taken from priv->user_txpower_limit.
2161 */
c79dd5b5 2162int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 2163{
bb8c093b 2164 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 2165 int ret;
b481de9c
ZY		 2166 u8 band = 0;
2167 u8 is_fat = 0;
2168 u8 ctrl_chan_high = 0;
2169
2170 if (test_bit(STATUS_SCANNING, &priv->status)) {
2171 /* If this gets hit a lot, switch it to a BUG() and catch
2172 * the stack trace to find out who is calling this during
2173 * a scan. */
2174 IWL_WARNING("TX Power requested while scanning!\n");
2175 return -EAGAIN;
2176 }
2177
8318d78a 2178 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 2179
2180 is_fat = is_fat_channel(priv->active_rxon.flags);
2181
2182 if (is_fat &&
2183 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2184 ctrl_chan_high = 1;
2185
2186 cmd.band = band;
2187 cmd.channel = priv->active_rxon.channel;
2188
857485c0 2189 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 2190 le16_to_cpu(priv->active_rxon.channel),
2191 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 2192 if (ret)
2193 goto out;
b481de9c 2194
857485c0
TW		 2195 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2196
2197out:
2198 return ret;
b481de9c
ZY		 2199}
2200
7e8c519e
TW		 2201static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2202{
2203 int ret = 0;
2204 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2205 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2206 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2207
2208 if ((rxon1->flags == rxon2->flags) &&
2209 (rxon1->filter_flags == rxon2->filter_flags) &&
2210 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2211 (rxon1->ofdm_ht_single_stream_basic_rates ==
2212 rxon2->ofdm_ht_single_stream_basic_rates) &&
2213 (rxon1->ofdm_ht_dual_stream_basic_rates ==
2214 rxon2->ofdm_ht_dual_stream_basic_rates) &&
2215 (rxon1->rx_chain == rxon2->rx_chain) &&
2216 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2217 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
2218 return 0;
2219 }
2220
2221 rxon_assoc.flags = priv->staging_rxon.flags;
2222 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2223 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2224 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2225 rxon_assoc.reserved = 0;
2226 rxon_assoc.ofdm_ht_single_stream_basic_rates =
2227 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2228 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2229 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2230 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2231
2232 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2233 sizeof(rxon_assoc), &rxon_assoc, NULL);
2234 if (ret)
2235 return ret;
2236
2237 return ret;
2238}
2239
2240
c79dd5b5 2241int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2242{
2243 int rc;
2244 u8 band = 0;
2245 u8 is_fat = 0;
2246 u8 ctrl_chan_high = 0;
bb8c093b 2247 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 2248 const struct iwl_channel_info *ch_info;
b481de9c 2249
8318d78a 2250 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 2251
8622e705 2252 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 2253
2254 is_fat = is_fat_channel(priv->staging_rxon.flags);
2255
2256 if (is_fat &&
2257 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2258 ctrl_chan_high = 1;
2259
2260 cmd.band = band;
2261 cmd.expect_beacon = 0;
2262 cmd.channel = cpu_to_le16(channel);
2263 cmd.rxon_flags = priv->active_rxon.flags;
2264 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2265 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2266 if (ch_info)
2267 cmd.expect_beacon = is_channel_radar(ch_info);
2268 else
2269 cmd.expect_beacon = 1;
2270
2271 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2272 ctrl_chan_high, &cmd.tx_power);
2273 if (rc) {
2274 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2275 return rc;
2276 }
2277
857485c0 2278 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 2279 return rc;
2280}
2281
2282#define RTS_HCCA_RETRY_LIMIT 3
2283#define RTS_DFAULT_RETRY_LIMIT 60
2284
c79dd5b5 2285void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
857485c0 2286 struct iwl_cmd *cmd,
b481de9c
ZY		 2287 struct ieee80211_tx_control *ctrl,
2288 struct ieee80211_hdr *hdr, int sta_id,
2289 int is_hcca)
2290{
87e4f7df 2291 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
b481de9c
ZY		 2292 u8 rts_retry_limit = 0;
2293 u8 data_retry_limit = 0;
b481de9c 2294 u16 fc = le16_to_cpu(hdr->frame_control);
87e4f7df
TW		 2295 u8 rate_plcp;
2296 u16 rate_flags = 0;
8318d78a 2297 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c 2298
87e4f7df 2299 rate_plcp = iwl4965_rates[rate_idx].plcp;
b481de9c
ZY		 2300
2301 rts_retry_limit = (is_hcca) ?
2302 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2303
87e4f7df
TW		 2304 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2305 rate_flags |= RATE_MCS_CCK_MSK;
2306
2307
b481de9c
ZY		 2308 if (ieee80211_is_probe_response(fc)) {
2309 data_retry_limit = 3;
2310 if (data_retry_limit < rts_retry_limit)
2311 rts_retry_limit = data_retry_limit;
2312 } else
2313 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2314
2315 if (priv->data_retry_limit != -1)
2316 data_retry_limit = priv->data_retry_limit;
2317
87e4f7df
TW		 2318
2319 if (ieee80211_is_data(fc)) {
2320 tx->initial_rate_index = 0;
2321 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2322 } else {
b481de9c
ZY		 2323 switch (fc & IEEE80211_FCTL_STYPE) {
2324 case IEEE80211_STYPE_AUTH:
2325 case IEEE80211_STYPE_DEAUTH:
2326 case IEEE80211_STYPE_ASSOC_REQ:
2327 case IEEE80211_STYPE_REASSOC_REQ:
87e4f7df
TW		 2328 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2329 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2330 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
b481de9c
ZY		 2331 }
2332 break;
2333 default:
2334 break;
2335 }
87e4f7df
TW		 2336
2337 /* Alternate between antenna A and B for successive frames */
2338 if (priv->use_ant_b_for_management_frame) {
2339 priv->use_ant_b_for_management_frame = 0;
2340 rate_flags |= RATE_MCS_ANT_B_MSK;
2341 } else {
2342 priv->use_ant_b_for_management_frame = 1;
2343 rate_flags |= RATE_MCS_ANT_A_MSK;
2344 }
b481de9c
ZY		 2345 }
2346
87e4f7df
TW		 2347 tx->rts_retry_limit = rts_retry_limit;
2348 tx->data_retry_limit = data_retry_limit;
2349 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
b481de9c
ZY		 2350}
2351
c79dd5b5 2352int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2353{
059ff826
TW		 2354 struct iwl4965_shared *s = priv->shared_virt;
2355 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 2356}
2357
c79dd5b5 2358int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 2359{
2360 return priv->temperature;
2361}
2362
c79dd5b5 2363unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2364 struct iwl4965_frame *frame, u8 rate)
b481de9c 2365{
bb8c093b 2366 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2367 unsigned int frame_size;
2368
2369 tx_beacon_cmd = &frame->u.beacon;
2370 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2371
5425e490 2372 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2373 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2374
bb8c093b 2375 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 2376 tx_beacon_cmd->frame,
bb8c093b 2377 iwl4965_broadcast_addr,
b481de9c
ZY		 2378 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2379
2380 BUG_ON(frame_size > MAX_MPDU_SIZE);
2381 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2382
2383 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2384 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2385 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 2386 else
2387 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2388 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 2389
2390 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2391 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2392 return (sizeof(*tx_beacon_cmd) + frame_size);
2393}
2394
8b6eaea8
CB		 2395/*
2396 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2397 * given Tx queue, and enable the DMA channel used for that queue.
2398 *
2399 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2400 * channels supported in hardware.
2401 */
c79dd5b5 2402int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c
ZY		 2403{
2404 int rc;
2405 unsigned long flags;
2406 int txq_id = txq->q.id;
2407
2408 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 2409 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2410 if (rc) {
2411 spin_unlock_irqrestore(&priv->lock, flags);
2412 return rc;
2413 }
2414
8b6eaea8 2415 /* Circular buffer (TFD queue in DRAM) physical base address */
3395f6e9 2416 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
b481de9c 2417 txq->q.dma_addr >> 8);
8b6eaea8
CB		 2418
2419 /* Enable DMA channel, using same id as for TFD queue */
3395f6e9 2420 iwl_write_direct32(
b481de9c
ZY		 2421 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2422 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2423 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
3395f6e9 2424 iwl_release_nic_access(priv);
b481de9c
ZY		 2425 spin_unlock_irqrestore(&priv->lock, flags);
2426
2427 return 0;
2428}
2429
c79dd5b5 2430int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 2431 dma_addr_t addr, u16 len)
2432{
2433 int index, is_odd;
bb8c093b 2434 struct iwl4965_tfd_frame *tfd = ptr;
b481de9c
ZY		 2435 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2436
8b6eaea8 2437 /* Each TFD can point to a maximum 20 Tx buffers */
b481de9c
ZY		 2438 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2439 IWL_ERROR("Error can not send more than %d chunks\n",
2440 MAX_NUM_OF_TBS);
2441 return -EINVAL;
2442 }
2443
2444 index = num_tbs / 2;
2445 is_odd = num_tbs & 0x1;
2446
2447 if (!is_odd) {
2448 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2449 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
6a218f6f 2450 iwl_get_dma_hi_address(addr));
b481de9c
ZY		 2451 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2452 } else {
2453 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2454 (u32) (addr & 0xffff));
2455 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2456 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2457 }
2458
2459 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2460
2461 return 0;
2462}
2463
c79dd5b5 2464static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
b481de9c 2465{
073d3f5f 2466 u16 hw_version = iwl_eeprom_query16(priv, EEPROM_4965_BOARD_REVISION);
b481de9c
ZY		 2467
2468 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2469 ((hw_version >> 8) & 0x0F),
2470 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2471
2472 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
073d3f5f 2473 &priv->eeprom[EEPROM_4965_BOARD_PBA]);
b481de9c
ZY		 2474}
2475
2476#define IWL_TX_CRC_SIZE 4
2477#define IWL_TX_DELIMITER_SIZE 4
2478
8b6eaea8 2479/**
e2a722eb 2480 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 2481 */
e2a722eb
TW		 2482static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2483 struct iwl4965_tx_queue *txq,
2484 u16 byte_cnt)
b481de9c
ZY		 2485{
2486 int len;
2487 int txq_id = txq->q.id;
059ff826 2488 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 2489
b481de9c
ZY		 2490 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2491
8b6eaea8 2492 /* Set up byte count within first 256 entries */
b481de9c 2493 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 2494 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 2495
8b6eaea8 2496 /* If within first 64 entries, duplicate at end */
fc4b6853 2497 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
b481de9c 2498 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 2499 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 2500 byte_cnt, len);
b481de9c
ZY		 2501}
2502
8b6eaea8
CB		 2503/**
2504 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2505 *
2506 * Selects how many and which Rx receivers/antennas/chains to use.
2507 * This should not be used for scan command ... it puts data in wrong place.
2508 */
c79dd5b5 2509void iwl4965_set_rxon_chain(struct iwl_priv *priv)
b481de9c 2510{
fde0db31 2511 u8 is_single = is_single_rx_stream(priv);
b481de9c
ZY		 2512 u8 idle_state, rx_state;
2513
2514 priv->staging_rxon.rx_chain = 0;
2515 rx_state = idle_state = 3;
2516
2517 /* Tell uCode which antennas are actually connected.
2518 * Before first association, we assume all antennas are connected.
f0832f13 2519 * Just after first association, iwl_chain_noise_calibration()
b481de9c
ZY		 2520 * checks which antennas actually *are* connected. */
2521 priv->staging_rxon.rx_chain |=
fde0db31
GC		 2522 cpu_to_le16(priv->hw_params.valid_rx_ant <<
2523 RXON_RX_CHAIN_VALID_POS);
b481de9c
ZY		 2524
2525 /* How many receivers should we use? */
2526 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2527 priv->staging_rxon.rx_chain |=
2528 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2529 priv->staging_rxon.rx_chain |=
2530 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2531
2532 if (!is_single && (rx_state >= 2) &&
2533 !test_bit(STATUS_POWER_PMI, &priv->status))
2534 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2535 else
2536 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2537
2538 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2539}
2540
b481de9c
ZY		 2541/**
2542 * sign_extend - Sign extend a value using specified bit as sign-bit
2543 *
2544 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2545 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2546 *
2547 * @param oper value to sign extend
2548 * @param index 0 based bit index (0<=index<32) to sign bit
2549 */
2550static s32 sign_extend(u32 oper, int index)
2551{
2552 u8 shift = 31 - index;
2553
2554 return (s32)(oper << shift) >> shift;
2555}
2556
2557/**
2558 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2559 * @statistics: Provides the temperature reading from the uCode
2560 *
2561 * A return of <0 indicates bogus data in the statistics
2562 */
c79dd5b5 2563int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 2564{
2565 s32 temperature;
2566 s32 vt;
2567 s32 R1, R2, R3;
2568 u32 R4;
2569
2570 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2571 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2572 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2573 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2574 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2575 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2576 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2577 } else {
2578 IWL_DEBUG_TEMP("Running temperature calibration\n");
2579 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2580 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2581 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2582 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2583 }
2584
2585 /*
8b6eaea8 2586 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 2587 *
2588 * NOTE If we haven't received a statistics notification yet
2589 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 2590 * "initialize" ALIVE response.
2591 */
b481de9c
ZY		 2592 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2593 vt = sign_extend(R4, 23);
2594 else
2595 vt = sign_extend(
2596 le32_to_cpu(priv->statistics.general.temperature), 23);
2597
2598 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2599 R1, R2, R3, vt);
2600
2601 if (R3 == R1) {
2602 IWL_ERROR("Calibration conflict R1 == R3\n");
2603 return -1;
2604 }
2605
2606 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2607 * Add offset to center the adjustment around 0 degrees Centigrade. */
2608 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2609 temperature /= (R3 - R1);
2610 temperature = (temperature * 97) / 100 +
2611 TEMPERATURE_CALIB_KELVIN_OFFSET;
2612
2613 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2614 KELVIN_TO_CELSIUS(temperature));
2615
2616 return temperature;
2617}
2618
2619/* Adjust Txpower only if temperature variance is greater than threshold. */
2620#define IWL_TEMPERATURE_THRESHOLD 3
2621
2622/**
2623 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2624 *
2625 * If the temperature changed has changed sufficiently, then a recalibration
2626 * is needed.
2627 *
2628 * Assumes caller will replace priv->last_temperature once calibration
2629 * executed.
2630 */
c79dd5b5 2631static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 2632{
2633 int temp_diff;
2634
2635 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2636 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2637 return 0;
2638 }
2639
2640 temp_diff = priv->temperature - priv->last_temperature;
2641
2642 /* get absolute value */
2643 if (temp_diff < 0) {
2644 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2645 temp_diff = -temp_diff;
2646 } else if (temp_diff == 0)
2647 IWL_DEBUG_POWER("Same temp, \n");
2648 else
2649 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2650
2651 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2652 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2653 return 0;
2654 }
2655
2656 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2657
2658 return 1;
2659}
2660
2661/* Calculate noise level, based on measurements during network silence just
2662 * before arriving beacon. This measurement can be done only if we know
2663 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 2664static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 2665{
2666 struct statistics_rx_non_phy *rx_info
2667 = &(priv->statistics.rx.general);
2668 int num_active_rx = 0;
2669 int total_silence = 0;
2670 int bcn_silence_a =
2671 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2672 int bcn_silence_b =
2673 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2674 int bcn_silence_c =
2675 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2676
2677 if (bcn_silence_a) {
2678 total_silence += bcn_silence_a;
2679 num_active_rx++;
2680 }
2681 if (bcn_silence_b) {
2682 total_silence += bcn_silence_b;
2683 num_active_rx++;
2684 }
2685 if (bcn_silence_c) {
2686 total_silence += bcn_silence_c;
2687 num_active_rx++;
2688 }
2689
2690 /* Average among active antennas */
2691 if (num_active_rx)
2692 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2693 else
2694 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2695
2696 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2697 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2698 priv->last_rx_noise);
2699}
2700
c79dd5b5 2701void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 2702{
bb8c093b 2703 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2704 int change;
2705 s32 temp;
2706
2707 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2708 (int)sizeof(priv->statistics), pkt->len);
2709
2710 change = ((priv->statistics.general.temperature !=
2711 pkt->u.stats.general.temperature) ||
2712 ((priv->statistics.flag &
2713 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2714 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2715
2716 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2717
2718 set_bit(STATUS_STATISTICS, &priv->status);
2719
2720 /* Reschedule the statistics timer to occur in
2721 * REG_RECALIB_PERIOD seconds to ensure we get a
2722 * thermal update even if the uCode doesn't give
2723 * us one */
2724 mod_timer(&priv->statistics_periodic, jiffies +
2725 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2726
2727 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2728 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2729 iwl4965_rx_calc_noise(priv);
f0832f13 2730#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 2731 queue_work(priv->workqueue, &priv->sensitivity_work);
2732#endif
2733 }
2734
ab53d8af
MA		 2735 iwl_leds_background(priv);
2736
b481de9c
ZY		 2737 /* If the hardware hasn't reported a change in
2738 * temperature then don't bother computing a
2739 * calibrated temperature value */
2740 if (!change)
2741 return;
2742
2743 temp = iwl4965_get_temperature(priv);
2744 if (temp < 0)
2745 return;
2746
2747 if (priv->temperature != temp) {
2748 if (priv->temperature)
2749 IWL_DEBUG_TEMP("Temperature changed "
2750 "from %dC to %dC\n",
2751 KELVIN_TO_CELSIUS(priv->temperature),
2752 KELVIN_TO_CELSIUS(temp));
2753 else
2754 IWL_DEBUG_TEMP("Temperature "
2755 "initialized to %dC\n",
2756 KELVIN_TO_CELSIUS(temp));
2757 }
2758
2759 priv->temperature = temp;
2760 set_bit(STATUS_TEMPERATURE, &priv->status);
2761
2762 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2763 iwl4965_is_temp_calib_needed(priv))
2764 queue_work(priv->workqueue, &priv->txpower_work);
2765}
2766
c79dd5b5 2767static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 2768 struct sk_buff *skb,
2769 struct iwl4965_rx_phy_res *rx_start,
2770 struct ieee80211_rx_status *stats,
2771 u32 ampdu_status)
2772{
2773 s8 signal = stats->ssi;
2774 s8 noise = 0;
8318d78a 2775 int rate = stats->rate_idx;
12342c47 2776 u64 tsf = stats->mactime;
a0b484fe 2777 __le16 antenna;
12342c47
ZY		 2778 __le16 phy_flags_hw = rx_start->phy_flags;
2779 struct iwl4965_rt_rx_hdr {
2780 struct ieee80211_radiotap_header rt_hdr;
2781 __le64 rt_tsf; /* TSF */
2782 u8 rt_flags; /* radiotap packet flags */
2783 u8 rt_rate; /* rate in 500kb/s */
2784 __le16 rt_channelMHz; /* channel in MHz */
2785 __le16 rt_chbitmask; /* channel bitfield */
2786 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2787 s8 rt_dbmnoise;
2788 u8 rt_antenna; /* antenna number */
2789 } __attribute__ ((packed)) *iwl4965_rt;
2790
2791 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2792 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2793 if (net_ratelimit())
2794 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 2795 "radiotap head [%zd]\n",
12342c47
ZY		 2796 skb_headroom(skb), sizeof(*iwl4965_rt));
2797 return;
2798 }
2799
2800 /* put radiotap header in front of 802.11 header and data */
2801 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2802
2803 /* initialise radiotap header */
2804 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2805 iwl4965_rt->rt_hdr.it_pad = 0;
2806
2807 /* total header + data */
2808 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2809 &iwl4965_rt->rt_hdr.it_len);
2810
2811 /* Indicate all the fields we add to the radiotap header */
2812 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2813 (1 << IEEE80211_RADIOTAP_FLAGS) |
2814 (1 << IEEE80211_RADIOTAP_RATE) |
2815 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2816 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2817 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2818 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2819 &iwl4965_rt->rt_hdr.it_present);
2820
2821 /* Zero the flags, we'll add to them as we go */
2822 iwl4965_rt->rt_flags = 0;
2823
2824 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2825
2826 iwl4965_rt->rt_dbmsignal = signal;
2827 iwl4965_rt->rt_dbmnoise = noise;
2828
2829 /* Convert the channel frequency and set the flags */
2830 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2831 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2832 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2833 IEEE80211_CHAN_5GHZ),
2834 &iwl4965_rt->rt_chbitmask);
2835 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2836 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2837 IEEE80211_CHAN_2GHZ),
2838 &iwl4965_rt->rt_chbitmask);
2839 else /* 802.11g */
2840 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2841 IEEE80211_CHAN_2GHZ),
2842 &iwl4965_rt->rt_chbitmask);
2843
12342c47
ZY		 2844 if (rate == -1)
2845 iwl4965_rt->rt_rate = 0;
2846 else
2847 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2848
2849 /*
2850 * "antenna number"
2851 *
2852 * It seems that the antenna field in the phy flags value
2853 * is actually a bitfield. This is undefined by radiotap,
2854 * it wants an actual antenna number but I always get "7"
2855 * for most legacy frames I receive indicating that the
2856 * same frame was received on all three RX chains.
2857 *
2858 * I think this field should be removed in favour of a
2859 * new 802.11n radiotap field "RX chains" that is defined
2860 * as a bitmask.
2861 */
a0b484fe
JB		 2862 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2863 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 2864
2865 /* set the preamble flag if appropriate */
2866 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2867 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2868
2869 stats->flag |= RX_FLAG_RADIOTAP;
2870}
2871
19758bef
TW		 2872static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2873{
2874 /* 0 - mgmt, 1 - cnt, 2 - data */
2875 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2876 priv->rx_stats[idx].cnt++;
2877 priv->rx_stats[idx].bytes += len;
2878}
2879
3ec47732
EG		 2880/*
2881 * returns non-zero if packet should be dropped
2882 */
2883static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2884 struct ieee80211_hdr *hdr,
2885 u32 decrypt_res,
2886 struct ieee80211_rx_status *stats)
2887{
2888 u16 fc = le16_to_cpu(hdr->frame_control);
2889
2890 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2891 return 0;
2892
2893 if (!(fc & IEEE80211_FCTL_PROTECTED))
2894 return 0;
2895
2896 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2897 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2898 case RX_RES_STATUS_SEC_TYPE_TKIP:
2899 /* The uCode has got a bad phase 1 Key, pushes the packet.
2900 * Decryption will be done in SW. */
2901 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2902 RX_RES_STATUS_BAD_KEY_TTAK)
2903 break;
2904
2905 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2906 RX_RES_STATUS_BAD_ICV_MIC) {
2907 /* bad ICV, the packet is destroyed since the
2908 * decryption is inplace, drop it */
2909 IWL_DEBUG_RX("Packet destroyed\n");
2910 return -1;
2911 }
2912 case RX_RES_STATUS_SEC_TYPE_WEP:
2913 case RX_RES_STATUS_SEC_TYPE_CCMP:
2914 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2915 RX_RES_STATUS_DECRYPT_OK) {
2916 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2917 stats->flag |= RX_FLAG_DECRYPTED;
2918 }
2919 break;
2920
2921 default:
2922 break;
2923 }
2924 return 0;
2925}
2926
17e476b8
EG		 2927static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2928{
2929 u32 decrypt_out = 0;
2930
2931 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2932 RX_RES_STATUS_STATION_FOUND)
2933 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2934 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2935
2936 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2937
2938 /* packet was not encrypted */
2939 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2940 RX_RES_STATUS_SEC_TYPE_NONE)
2941 return decrypt_out;
2942
2943 /* packet was encrypted with unknown alg */
2944 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2945 RX_RES_STATUS_SEC_TYPE_ERR)
2946 return decrypt_out;
2947
2948 /* decryption was not done in HW */
2949 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2950 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2951 return decrypt_out;
2952
2953 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2954
2955 case RX_RES_STATUS_SEC_TYPE_CCMP:
2956 /* alg is CCM: check MIC only */
2957 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2958 /* Bad MIC */
2959 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2960 else
2961 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2962
2963 break;
2964
2965 case RX_RES_STATUS_SEC_TYPE_TKIP:
2966 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2967 /* Bad TTAK */
2968 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2969 break;
2970 }
2971 /* fall through if TTAK OK */
2972 default:
2973 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2974 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2975 else
2976 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2977 break;
2978 };
2979
2980 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2981 decrypt_in, decrypt_out);
2982
2983 return decrypt_out;
2984}
2985
c79dd5b5 2986static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 2987 int include_phy,
bb8c093b 2988 struct iwl4965_rx_mem_buffer *rxb,
b481de9c
ZY		 2989 struct ieee80211_rx_status *stats)
2990{
bb8c093b 2991 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 2992 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2993 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2994 struct ieee80211_hdr *hdr;
2995 u16 len;
2996 __le32 *rx_end;
2997 unsigned int skblen;
2998 u32 ampdu_status;
17e476b8 2999 u32 ampdu_status_legacy;
b481de9c
ZY		 3000
3001 if (!include_phy && priv->last_phy_res[0])
3002 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3003
3004 if (!rx_start) {
3005 IWL_ERROR("MPDU frame without a PHY data\n");
3006 return;
3007 }
3008 if (include_phy) {
3009 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3010 rx_start->cfg_phy_cnt);
3011
3012 len = le16_to_cpu(rx_start->byte_count);
3013
3014 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3015 sizeof(struct iwl4965_rx_phy_res) +
3016 rx_start->cfg_phy_cnt + len);
3017
3018 } else {
3019 struct iwl4965_rx_mpdu_res_start *amsdu =
3020 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3021
3022 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3023 sizeof(struct iwl4965_rx_mpdu_res_start));
3024 len = le16_to_cpu(amsdu->byte_count);
3025 rx_start->byte_count = amsdu->byte_count;
3026 rx_end = (__le32 *) (((u8 *) hdr) + len);
3027 }
5425e490 3028 if (len > priv->hw_params.max_pkt_size || len < 16) {
12342c47 3029 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 3030 return;
3031 }
3032
3033 ampdu_status = le32_to_cpu(*rx_end);
3034 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3035
17e476b8
EG		 3036 if (!include_phy) {
3037 /* New status scheme, need to translate */
3038 ampdu_status_legacy = ampdu_status;
3039 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3040 }
3041
b481de9c
ZY		 3042 /* start from MAC */
3043 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3044 skb_put(rxb->skb, len); /* end where data ends */
3045
3046 /* We only process data packets if the interface is open */
3047 if (unlikely(!priv->is_open)) {
3048 IWL_DEBUG_DROP_LIMIT
3049 ("Dropping packet while interface is not open.\n");
3050 return;
3051 }
3052
b481de9c
ZY		 3053 stats->flag = 0;
3054 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3055
3ec47732 3056 /* in case of HW accelerated crypto and bad decryption, drop */
099b40b7 3057 if (!priv->hw_params.sw_crypto &&
3ec47732
EG		 3058 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
3059 return;
b481de9c 3060
12342c47
ZY		 3061 if (priv->add_radiotap)
3062 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3063
19758bef 3064 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 3065 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3066 priv->alloc_rxb_skb--;
3067 rxb->skb = NULL;
b481de9c
ZY		 3068}
3069
3070/* Calc max signal level (dBm) among 3 possible receivers */
3071static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3072{
3073 /* data from PHY/DSP regarding signal strength, etc.,
3074 * contents are always there, not configurable by host. */
3075 struct iwl4965_rx_non_cfg_phy *ncphy =
3076 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3077 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3078 >> IWL_AGC_DB_POS;
3079
3080 u32 valid_antennae =
3081 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3082 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3083 u8 max_rssi = 0;
3084 u32 i;
3085
3086 /* Find max rssi among 3 possible receivers.
3087 * These values are measured by the digital signal processor (DSP).
3088 * They should stay fairly constant even as the signal strength varies,
3089 * if the radio's automatic gain control (AGC) is working right.
3090 * AGC value (see below) will provide the "interesting" info. */
3091 for (i = 0; i < 3; i++)
3092 if (valid_antennae & (1 << i))
3093 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3094
3095 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3096 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3097 max_rssi, agc);
3098
3099 /* dBm = max_rssi dB - agc dB - constant.
3100 * Higher AGC (higher radio gain) means lower signal. */
3101 return (max_rssi - agc - IWL_RSSI_OFFSET);
3102}
3103
c8b0e6e1 3104#ifdef CONFIG_IWL4965_HT
b481de9c 3105
fde0db31 3106void iwl4965_init_ht_hw_capab(const struct iwl_priv *priv,
1ea87396 3107 struct ieee80211_ht_info *ht_info,
78330fdd 3108 enum ieee80211_band band)
326eeee8
RR		 3109{
3110 ht_info->cap = 0;
3111 memset(ht_info->supp_mcs_set, 0, 16);
3112
3113 ht_info->ht_supported = 1;
3114
099b40b7 3115 if (priv->hw_params.fat_channel & BIT(band)) {
326eeee8
RR		 3116 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3117 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3118 ht_info->supp_mcs_set[4] = 0x01;
3119 }
3120 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3121 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3122 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3123 (IWL_MIMO_PS_NONE << 2));
1ea87396
AK		 3124
3125 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47 3126 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
326eeee8
RR		 3127
3128 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3129 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3130
3131 ht_info->supp_mcs_set[0] = 0xFF;
fde0db31
GC		 3132 if (priv->hw_params.tx_chains_num >= 2)
3133 ht_info->supp_mcs_set[1] = 0xFF;
3134 if (priv->hw_params.tx_chains_num >= 3)
3135 ht_info->supp_mcs_set[2] = 0xFF;
326eeee8 3136}
c8b0e6e1 3137#endif /* CONFIG_IWL4965_HT */
b481de9c 3138
c79dd5b5 3139static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 3140{
3141 unsigned long flags;
3142
3143 spin_lock_irqsave(&priv->sta_lock, flags);
3144 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3145 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3146 priv->stations[sta_id].sta.sta.modify_mask = 0;
3147 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3148 spin_unlock_irqrestore(&priv->sta_lock, flags);
3149
bb8c093b 3150 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3151}
3152
c79dd5b5 3153static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 3154{
3155 /* FIXME: need locking over ps_status ??? */
947b13a7 3156 u8 sta_id = iwl_find_station(priv, addr);
b481de9c
ZY		 3157
3158 if (sta_id != IWL_INVALID_STATION) {
3159 u8 sta_awake = priv->stations[sta_id].
3160 ps_status == STA_PS_STATUS_WAKE;
3161
3162 if (sta_awake && ps_bit)
3163 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3164 else if (!sta_awake && !ps_bit) {
3165 iwl4965_sta_modify_ps_wake(priv, sta_id);
3166 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3167 }
3168 }
3169}
0a6857e7 3170#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 3171
3172/**
3173 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3174 *
3175 * You may hack this function to show different aspects of received frames,
3176 * including selective frame dumps.
3177 * group100 parameter selects whether to show 1 out of 100 good frames.
3178 *
3179 * TODO: This was originally written for 3945, need to audit for
3180 * proper operation with 4965.
3181 */
c79dd5b5 3182static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3183 struct iwl4965_rx_packet *pkt,
3184 struct ieee80211_hdr *header, int group100)
3185{
3186 u32 to_us;
3187 u32 print_summary = 0;
3188 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3189 u32 hundred = 0;
3190 u32 dataframe = 0;
3191 u16 fc;
3192 u16 seq_ctl;
3193 u16 channel;
3194 u16 phy_flags;
3195 int rate_sym;
3196 u16 length;
3197 u16 status;
3198 u16 bcn_tmr;
3199 u32 tsf_low;
3200 u64 tsf;
3201 u8 rssi;
3202 u8 agc;
3203 u16 sig_avg;
3204 u16 noise_diff;
3205 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3206 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3207 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3208 u8 *data = IWL_RX_DATA(pkt);
3209
0a6857e7 3210 if (likely(!(iwl_debug_level & IWL_DL_RX)))
17744ff6
TW		 3211 return;
3212
3213 /* MAC header */
3214 fc = le16_to_cpu(header->frame_control);
3215 seq_ctl = le16_to_cpu(header->seq_ctrl);
3216
3217 /* metadata */
3218 channel = le16_to_cpu(rx_hdr->channel);
3219 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3220 rate_sym = rx_hdr->rate;
3221 length = le16_to_cpu(rx_hdr->len);
3222
3223 /* end-of-frame status and timestamp */
3224 status = le32_to_cpu(rx_end->status);
3225 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3226 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3227 tsf = le64_to_cpu(rx_end->timestamp);
3228
3229 /* signal statistics */
3230 rssi = rx_stats->rssi;
3231 agc = rx_stats->agc;
3232 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3233 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3234
3235 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3236
3237 /* if data frame is to us and all is good,
3238 * (optionally) print summary for only 1 out of every 100 */
3239 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3240 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3241 dataframe = 1;
3242 if (!group100)
3243 print_summary = 1; /* print each frame */
3244 else if (priv->framecnt_to_us < 100) {
3245 priv->framecnt_to_us++;
3246 print_summary = 0;
3247 } else {
3248 priv->framecnt_to_us = 0;
3249 print_summary = 1;
3250 hundred = 1;
3251 }
3252 } else {
3253 /* print summary for all other frames */
3254 print_summary = 1;
3255 }
3256
3257 if (print_summary) {
3258 char *title;
3259 int rate_idx;
3260 u32 bitrate;
3261
3262 if (hundred)
3263 title = "100Frames";
3264 else if (fc & IEEE80211_FCTL_RETRY)
3265 title = "Retry";
3266 else if (ieee80211_is_assoc_response(fc))
3267 title = "AscRsp";
3268 else if (ieee80211_is_reassoc_response(fc))
3269 title = "RasRsp";
3270 else if (ieee80211_is_probe_response(fc)) {
3271 title = "PrbRsp";
3272 print_dump = 1; /* dump frame contents */
3273 } else if (ieee80211_is_beacon(fc)) {
3274 title = "Beacon";
3275 print_dump = 1; /* dump frame contents */
3276 } else if (ieee80211_is_atim(fc))
3277 title = "ATIM";
3278 else if (ieee80211_is_auth(fc))
3279 title = "Auth";
3280 else if (ieee80211_is_deauth(fc))
3281 title = "DeAuth";
3282 else if (ieee80211_is_disassoc(fc))
3283 title = "DisAssoc";
3284 else
3285 title = "Frame";
3286
3287 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3288 if (unlikely(rate_idx == -1))
3289 bitrate = 0;
3290 else
3291 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3292
3293 /* print frame summary.
3294 * MAC addresses show just the last byte (for brevity),
3295 * but you can hack it to show more, if you'd like to. */
3296 if (dataframe)
3297 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3298 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3299 title, fc, header->addr1[5],
3300 length, rssi, channel, bitrate);
3301 else {
3302 /* src/dst addresses assume managed mode */
3303 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3304 "src=0x%02x, rssi=%u, tim=%lu usec, "
3305 "phy=0x%02x, chnl=%d\n",
3306 title, fc, header->addr1[5],
3307 header->addr3[5], rssi,
3308 tsf_low - priv->scan_start_tsf,
3309 phy_flags, channel);
3310 }
3311 }
3312 if (print_dump)
0a6857e7 3313 iwl_print_hex_dump(IWL_DL_RX, data, length);
17744ff6
TW		 3314}
3315#else
c79dd5b5 3316static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3317 struct iwl4965_rx_packet *pkt,
3318 struct ieee80211_hdr *header,
3319 int group100)
3320{
3321}
3322#endif
3323
b481de9c 3324
7878a5a4 3325
857485c0 3326/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 3327 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
c79dd5b5 3328static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
bb8c093b 3329 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3330{
17744ff6
TW		 3331 struct ieee80211_hdr *header;
3332 struct ieee80211_rx_status rx_status;
bb8c093b 3333 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3334 /* Use phy data (Rx signal strength, etc.) contained within
3335 * this rx packet for legacy frames,
3336 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 3337 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 3338 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3339 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3340 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3341 __le32 *rx_end;
3342 unsigned int len = 0;
b481de9c 3343 u16 fc;
b481de9c
ZY		 3344 u8 network_packet;
3345
17744ff6 3346 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
dc92e497
TW		 3347 rx_status.freq =
3348 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
17744ff6
TW		 3349 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3350 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
dc92e497
TW		 3351 rx_status.rate_idx =
3352 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
17744ff6
TW		 3353 if (rx_status.band == IEEE80211_BAND_5GHZ)
3354 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3355
3356 rx_status.antenna = 0;
3357 rx_status.flag = 0;
3358
b481de9c 3359 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
dc92e497
TW		 3360 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3361 rx_start->cfg_phy_cnt);
b481de9c
ZY		 3362 return;
3363 }
17744ff6 3364
b481de9c
ZY		 3365 if (!include_phy) {
3366 if (priv->last_phy_res[0])
3367 rx_start = (struct iwl4965_rx_phy_res *)
3368 &priv->last_phy_res[1];
3369 else
3370 rx_start = NULL;
3371 }
3372
3373 if (!rx_start) {
3374 IWL_ERROR("MPDU frame without a PHY data\n");
3375 return;
3376 }
3377
3378 if (include_phy) {
3379 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3380 + rx_start->cfg_phy_cnt);
3381
3382 len = le16_to_cpu(rx_start->byte_count);
17744ff6 3383 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 3384 sizeof(struct iwl4965_rx_phy_res) + len);
3385 } else {
3386 struct iwl4965_rx_mpdu_res_start *amsdu =
3387 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3388
3389 header = (void *)(pkt->u.raw +
3390 sizeof(struct iwl4965_rx_mpdu_res_start));
3391 len = le16_to_cpu(amsdu->byte_count);
3392 rx_end = (__le32 *) (pkt->u.raw +
3393 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3394 }
3395
3396 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3397 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3398 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3399 le32_to_cpu(*rx_end));
3400 return;
3401 }
3402
3403 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3404
b481de9c 3405 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
17744ff6 3406 rx_status.ssi = iwl4965_calc_rssi(rx_start);
b481de9c
ZY		 3407
3408 /* Meaningful noise values are available only from beacon statistics,
3409 * which are gathered only when associated, and indicate noise
3410 * only for the associated network channel ...
3411 * Ignore these noise values while scanning (other channels) */
3109ece1 3412 if (iwl_is_associated(priv) &&
b481de9c 3413 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6
TW		 3414 rx_status.noise = priv->last_rx_noise;
3415 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3416 rx_status.noise);
b481de9c 3417 } else {
17744ff6
TW		 3418 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3419 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
b481de9c
ZY		 3420 }
3421
3422 /* Reset beacon noise level if not associated. */
3109ece1 3423 if (!iwl_is_associated(priv))
b481de9c
ZY		 3424 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3425
17744ff6
TW		 3426 /* Set "1" to report good data frames in groups of 100 */
3427 /* FIXME: need to optimze the call: */
3428 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3429
3430 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3431 rx_status.ssi, rx_status.noise, rx_status.signal,
06501d29 3432 (unsigned long long)rx_status.mactime);
b481de9c 3433
bb8c093b 3434 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 3435 if (network_packet) {
17744ff6 3436 priv->last_rx_rssi = rx_status.ssi;
b481de9c
ZY		 3437 priv->last_beacon_time = priv->ucode_beacon_time;
3438 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3439 }
3440
3441 fc = le16_to_cpu(header->frame_control);
3442 switch (fc & IEEE80211_FCTL_FTYPE) {
3443 case IEEE80211_FTYPE_MGMT:
b481de9c
ZY		 3444 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3445 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3446 header->addr2);
17744ff6 3447 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 3448 break;
3449
3450 case IEEE80211_FTYPE_CTL:
9ab46173 3451#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 3452 switch (fc & IEEE80211_FCTL_STYPE) {
3453 case IEEE80211_STYPE_BACK_REQ:
3454 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3455 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 3456 rxb, &rx_status);
b481de9c
ZY		 3457 break;
3458 default:
3459 break;
3460 }
3461#endif
b481de9c
ZY		 3462 break;
3463
0795af57
JP		 3464 case IEEE80211_FTYPE_DATA: {
3465 DECLARE_MAC_BUF(mac1);
3466 DECLARE_MAC_BUF(mac2);
3467 DECLARE_MAC_BUF(mac3);
3468
b481de9c
ZY		 3469 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3470 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3471 header->addr2);
3472
3473 if (unlikely(!network_packet))
3474 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 3475 "%s, %s, %s\n",
3476 print_mac(mac1, header->addr1),
3477 print_mac(mac2, header->addr2),
3478 print_mac(mac3, header->addr3));
bb8c093b 3479 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 3480 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3481 print_mac(mac1, header->addr1),
3482 print_mac(mac2, header->addr2),
3483 print_mac(mac3, header->addr3));
b481de9c
ZY		 3484 else
3485 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 3486 &rx_status);
b481de9c 3487 break;
0795af57 3488 }
b481de9c
ZY		 3489 default:
3490 break;
3491
3492 }
3493}
3494
3495/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3496 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
c79dd5b5 3497static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
bb8c093b 3498 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3499{
bb8c093b 3500 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3501 priv->last_phy_res[0] = 1;
3502 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3503 sizeof(struct iwl4965_rx_phy_res));
3504}
c79dd5b5 3505static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
bb8c093b 3506 struct iwl4965_rx_mem_buffer *rxb)
b481de9c
ZY		 3507
3508{
f0832f13 3509#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
bb8c093b
CH		 3510 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3511 struct iwl4965_missed_beacon_notif *missed_beacon;
b481de9c
ZY		 3512
3513 missed_beacon = &pkt->u.missed_beacon;
3514 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3515 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3516 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3517 le32_to_cpu(missed_beacon->total_missed_becons),
3518 le32_to_cpu(missed_beacon->num_recvd_beacons),
3519 le32_to_cpu(missed_beacon->num_expected_beacons));
f0832f13
EG		 3520 if (!test_bit(STATUS_SCANNING, &priv->status))
3521 iwl_init_sensitivity(priv);
b481de9c 3522 }
f0832f13 3523#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c 3524}
c8b0e6e1 3525#ifdef CONFIG_IWL4965_HT
b481de9c 3526
8b6eaea8
CB		 3527/**
3528 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3529 */
c79dd5b5 3530static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
b481de9c
ZY		 3531 int sta_id, int tid)
3532{
3533 unsigned long flags;
3534
8b6eaea8 3535 /* Remove "disable" flag, to enable Tx for this TID */
b481de9c
ZY		 3536 spin_lock_irqsave(&priv->sta_lock, flags);
3537 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3538 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3539 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3540 spin_unlock_irqrestore(&priv->sta_lock, flags);
3541
bb8c093b 3542 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3543}
3544
8b6eaea8
CB		 3545/**
3546 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3547 *
3548 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3549 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3550 */
c79dd5b5 3551static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b
CH		 3552 struct iwl4965_ht_agg *agg,
3553 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 3554 ba_resp)
3555
3556{
3557 int i, sh, ack;
fe01b477
RR		 3558 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3559 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3560 u64 bitmap;
3561 int successes = 0;
3562 struct ieee80211_tx_status *tx_status;
b481de9c
ZY		 3563
3564 if (unlikely(!agg->wait_for_ba)) {
3565 IWL_ERROR("Received BA when not expected\n");
3566 return -EINVAL;
3567 }
8b6eaea8
CB		 3568
3569 /* Mark that the expected block-ack response arrived */
b481de9c 3570 agg->wait_for_ba = 0;
fe01b477 3571 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 3572
3573 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 3574 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 3575 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 3576 sh += 0x100;
3577
8b6eaea8 3578 /* don't use 64-bit values for now */
fe01b477 3579 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 3580
3581 if (agg->frame_count > (64 - sh)) {
3582 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3583 return -1;
3584 }
3585
3586 /* check for success or failure according to the
8b6eaea8 3587 * transmitted bitmap and block-ack bitmap */
fe01b477 3588 bitmap &= agg->bitmap;
b481de9c 3589
8b6eaea8
CB		 3590 /* For each frame attempted in aggregation,
3591 * update driver's record of tx frame's status. */
b481de9c 3592 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 3593 ack = bitmap & (1 << i);
3594 successes += !!ack;
b481de9c 3595 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 3596 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3597 agg->start_idx + i);
3598 }
3599
3600 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3601 tx_status->flags = IEEE80211_TX_STATUS_ACK;
99556438
RR		 3602 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3603 tx_status->ampdu_ack_map = successes;
3604 tx_status->ampdu_ack_len = agg->frame_count;
4c424e4c
RR		 3605 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3606 &tx_status->control);
fe01b477 3607
f868f4e1 3608 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 3609
3610 return 0;
3611}
3612
3613/**
3614 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3615 */
c79dd5b5 3616static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 3617 u16 txq_id)
3618{
3619 /* Simply stop the queue, but don't change any configuration;
3620 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 3621 iwl_write_prph(priv,
12a81f60 3622 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
fe01b477
RR		 3623 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3624 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3625}
b481de9c 3626
fe01b477
RR		 3627/**
3628 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
b095d03a 3629 * priv->lock must be held by the caller
fe01b477 3630 */
c79dd5b5 3631static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
fe01b477
RR		 3632 u16 ssn_idx, u8 tx_fifo)
3633{
b095d03a
RR		 3634 int ret = 0;
3635
fe01b477
RR		 3636 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3637 IWL_WARNING("queue number too small: %d, must be > %d\n",
3638 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3639 return -EINVAL;
b481de9c
ZY		 3640 }
3641
3395f6e9 3642 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 3643 if (ret)
3644 return ret;
3645
fe01b477
RR		 3646 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3647
12a81f60 3648 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 3649
3650 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3651 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3652 /* supposes that ssn_idx is valid (!= 0xFFF) */
3653 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3654
12a81f60 3655 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
fe01b477
RR		 3656 iwl4965_txq_ctx_deactivate(priv, txq_id);
3657 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3658
3395f6e9 3659 iwl_release_nic_access(priv);
b095d03a 3660
fe01b477
RR		 3661 return 0;
3662}
b481de9c 3663
c79dd5b5 3664int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
fe01b477
RR		 3665 u8 tid, int txq_id)
3666{
3667 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3668 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3669 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3670
3671 switch (priv->stations[sta_id].tid[tid].agg.state) {
3672 case IWL_EMPTYING_HW_QUEUE_DELBA:
3673 /* We are reclaiming the last packet of the */
3674 /* aggregated HW queue */
3675 if (txq_id == tid_data->agg.txq_id &&
3676 q->read_ptr == q->write_ptr) {
3677 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3678 int tx_fifo = default_tid_to_tx_fifo[tid];
3679 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3680 iwl4965_tx_queue_agg_disable(priv, txq_id,
3681 ssn, tx_fifo);
3682 tid_data->agg.state = IWL_AGG_OFF;
3683 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3684 }
3685 break;
3686 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3687 /* We are reclaiming the last packet of the queue */
3688 if (tid_data->tfds_in_queue == 0) {
3689 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3690 tid_data->agg.state = IWL_AGG_ON;
3691 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3692 }
3693 break;
3694 }
b481de9c
ZY		 3695 return 0;
3696}
3697
8b6eaea8
CB		 3698/**
3699 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3700 * @index -- current index
3701 * @n_bd -- total number of entries in queue (s/b power of 2)
3702 */
bb8c093b 3703static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 3704{
3705 return (index == 0) ? n_bd - 1 : index - 1;
3706}
3707
8b6eaea8
CB		 3708/**
3709 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3710 *
3711 * Handles block-acknowledge notification from device, which reports success
3712 * of frames sent via aggregation.
3713 */
c79dd5b5 3714static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b 3715 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3716{
bb8c093b
CH		 3717 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3718 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 3719 int index;
bb8c093b
CH		 3720 struct iwl4965_tx_queue *txq = NULL;
3721 struct iwl4965_ht_agg *agg;
fe01b477 3722 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 3723
3724 /* "flow" corresponds to Tx queue */
fe01b477 3725 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 3726
3727 /* "ssn" is start of block-ack Tx window, corresponds to index
3728 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 3729 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3730
dfe7d458 3731 if (scd_flow >= priv->hw_params.max_txq_num) {
b481de9c
ZY		 3732 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3733 return;
3734 }
3735
fe01b477 3736 txq = &priv->txq[scd_flow];
b481de9c 3737 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 3738
3739 /* Find index just before block-ack window */
bb8c093b 3740 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 3741
01ebd063 3742 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 3743
0795af57
JP		 3744 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3745 "sta_id = %d\n",
b481de9c 3746 agg->wait_for_ba,
0795af57 3747 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 3748 ba_resp->sta_id);
fe01b477 3749 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 3750 "%d, scd_ssn = %d\n",
3751 ba_resp->tid,
fe01b477 3752 ba_resp->seq_ctl,
0310ae72 3753 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 3754 ba_resp->scd_flow,
3755 ba_resp->scd_ssn);
fe01b477 3756 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 3757 agg->start_idx,
f868f4e1 3758 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 3759
3760 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 3761 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 3762
3763 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3764 * block-ack window (we assume that they've been successfully
3765 * transmitted ... if not, it's too late anyway). */
fe01b477
RR		 3766 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3767 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3768 priv->stations[ba_resp->sta_id].
3769 tid[ba_resp->tid].tfds_in_queue -= freed;
3770 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3771 priv->mac80211_registered &&
3772 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3773 ieee80211_wake_queue(priv->hw, scd_flow);
3774 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3775 ba_resp->tid, scd_flow);
3776 }
b481de9c
ZY		 3777}
3778
8b6eaea8
CB		 3779/**
3780 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3781 */
c79dd5b5 3782static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 3783 u16 txq_id)
3784{
3785 u32 tbl_dw_addr;
3786 u32 tbl_dw;
3787 u16 scd_q2ratid;
3788
3789 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3790
3791 tbl_dw_addr = priv->scd_base_addr +
3792 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3793
3395f6e9 3794 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 3795
3796 if (txq_id & 0x1)
3797 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3798 else
3799 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3800
3395f6e9 3801 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 3802
3803 return 0;
3804}
3805
fe01b477 3806
b481de9c 3807/**
8b6eaea8
CB		 3808 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3809 *
3810 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3811 * i.e. it must be one of the higher queues used for aggregation
b481de9c 3812 */
c79dd5b5 3813static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
b481de9c
ZY		 3814 int tx_fifo, int sta_id, int tid,
3815 u16 ssn_idx)
3816{
3817 unsigned long flags;
3818 int rc;
3819 u16 ra_tid;
3820
3821 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3822 IWL_WARNING("queue number too small: %d, must be > %d\n",
3823 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3824
3825 ra_tid = BUILD_RAxTID(sta_id, tid);
3826
8b6eaea8 3827 /* Modify device's station table to Tx this TID */
bb8c093b 3828 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 3829
3830 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 3831 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3832 if (rc) {
3833 spin_unlock_irqrestore(&priv->lock, flags);
3834 return rc;
3835 }
3836
8b6eaea8 3837 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 3838 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3839
8b6eaea8 3840 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 3841 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3842
8b6eaea8 3843 /* Set this queue as a chain-building queue */
12a81f60 3844 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 3845
8b6eaea8
CB		 3846 /* Place first TFD at index corresponding to start sequence number.
3847 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 3848 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3849 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 3850 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3851
8b6eaea8 3852 /* Set up Tx window size and frame limit for this queue */
3395f6e9 3853 iwl_write_targ_mem(priv,
b481de9c
ZY		 3854 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3855 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3856 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3857
3395f6e9 3858 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 3859 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3860 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3861 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3862
12a81f60 3863 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 3864
8b6eaea8 3865 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 3866 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3867
3395f6e9 3868 iwl_release_nic_access(priv);
b481de9c
ZY		 3869 spin_unlock_irqrestore(&priv->lock, flags);
3870
3871 return 0;
3872}
3873
c8b0e6e1 3874#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 3875
3876/**
3877 * iwl4965_add_station - Initialize a station's hardware rate table
3878 *
8b6eaea8 3879 * The uCode's station table contains a table of fallback rates
b481de9c
ZY		 3880 * for automatic fallback during transmission.
3881 *
8b6eaea8
CB		 3882 * NOTE: This sets up a default set of values. These will be replaced later
3883 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3884 * rc80211_simple.
b481de9c 3885 *
8b6eaea8
CB		 3886 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3887 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3888 * which requires station table entry to exist).
b481de9c 3889 */
c79dd5b5 3890void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 3891{
3892 int i, r;
66c73db7 3893 struct iwl_link_quality_cmd link_cmd = {
b481de9c
ZY		 3894 .reserved1 = 0,
3895 };
3896 u16 rate_flags;
3897
8b6eaea8
CB		 3898 /* Set up the rate scaling to start at selected rate, fall back
3899 * all the way down to 1M in IEEE order, and then spin on 1M */
b481de9c
ZY		 3900 if (is_ap)
3901 r = IWL_RATE_54M_INDEX;
8318d78a 3902 else if (priv->band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 3903 r = IWL_RATE_6M_INDEX;
3904 else
3905 r = IWL_RATE_1M_INDEX;
3906
3907 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3908 rate_flags = 0;
3909 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3910 rate_flags |= RATE_MCS_CCK_MSK;
3911
8b6eaea8 3912 /* Use Tx antenna B only */
fde0db31 3913 rate_flags |= RATE_MCS_ANT_B_MSK; /*FIXME:RS*/
8b6eaea8 3914
b481de9c 3915 link_cmd.rs_table[i].rate_n_flags =
bb8c093b
CH		 3916 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3917 r = iwl4965_get_prev_ieee_rate(r);
b481de9c
ZY		 3918 }
3919
3920 link_cmd.general_params.single_stream_ant_msk = 2;
3921 link_cmd.general_params.dual_stream_ant_msk = 3;
3922 link_cmd.agg_params.agg_dis_start_th = 3;
3923 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3924
3925 /* Update the rate scaling for control frame Tx to AP */
5425e490 3926 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
b481de9c 3927
e5472978
TW		 3928 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3929 sizeof(link_cmd), &link_cmd, NULL);
b481de9c
ZY		 3930}
3931
c8b0e6e1 3932#ifdef CONFIG_IWL4965_HT
b481de9c 3933
c79dd5b5 3934static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
8318d78a 3935 enum ieee80211_band band,
78330fdd 3936 u16 channel, u8 extension_chan_offset)
b481de9c 3937{
bf85ea4f 3938 const struct iwl_channel_info *ch_info;
b481de9c 3939
8622e705 3940 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 3941 if (!is_channel_valid(ch_info))
3942 return 0;
3943
134eb5d3 3944 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
b481de9c
ZY		 3945 return 0;
3946
3947 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3948 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3949 return 1;
3950
3951 return 0;
3952}
3953
c79dd5b5 3954static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
fd105e79 3955 struct ieee80211_ht_info *sta_ht_inf)
b481de9c 3956{
fd105e79 3957 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
b481de9c 3958
fd105e79
RR		 3959 if ((!iwl_ht_conf->is_ht) ||
3960 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
134eb5d3 3961 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
b481de9c
ZY		 3962 return 0;
3963
fd105e79
RR		 3964 if (sta_ht_inf) {
3965 if ((!sta_ht_inf->ht_supported) ||
194c7ca6 3966 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
fd105e79
RR		 3967 return 0;
3968 }
b481de9c 3969
78330fdd 3970 return (iwl4965_is_channel_extension(priv, priv->band,
fd105e79
RR		 3971 iwl_ht_conf->control_channel,
3972 iwl_ht_conf->extension_chan_offset));
b481de9c
ZY		 3973}
3974
c79dd5b5 3975void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
b481de9c 3976{
bb8c093b 3977 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 3978 u32 val;
3979
3980 if (!ht_info->is_ht)
3981 return;
3982
8b6eaea8 3983 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
fd105e79 3984 if (iwl4965_is_fat_tx_allowed(priv, NULL))
b481de9c
ZY		 3985 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3986 else
3987 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
3988 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
3989
3990 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
3991 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
3992 le16_to_cpu(rxon->channel),
3993 ht_info->control_channel);
3994 rxon->channel = cpu_to_le16(ht_info->control_channel);
3995 return;
3996 }
3997
8b6eaea8 3998 /* Note: control channel is opposite of extension channel */
b481de9c
ZY		 3999 switch (ht_info->extension_chan_offset) {
4000 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4001 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4002 break;
4003 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4004 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4005 break;
134eb5d3 4006 case IWL_EXT_CHANNEL_OFFSET_NONE:
b481de9c
ZY		 4007 default:
4008 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4009 break;
4010 }
4011
fd105e79 4012 val = ht_info->ht_protection;
b481de9c
ZY		 4013
4014 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4015
b481de9c
ZY		 4016 iwl4965_set_rxon_chain(priv);
4017
fde0db31 4018 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
b481de9c
ZY		 4019 "rxon flags 0x%X operation mode :0x%X "
4020 "extension channel offset 0x%x "
4021 "control chan %d\n",
fde0db31
GC		 4022 ht_info->supp_mcs_set[0],
4023 ht_info->supp_mcs_set[1],
4024 ht_info->supp_mcs_set[2],
fd105e79 4025 le32_to_cpu(rxon->flags), ht_info->ht_protection,
b481de9c
ZY		 4026 ht_info->extension_chan_offset,
4027 ht_info->control_channel);
4028 return;
4029}
4030
c79dd5b5 4031void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
67d62035 4032 struct ieee80211_ht_info *sta_ht_inf)
b481de9c
ZY		 4033{
4034 __le32 sta_flags;
e53cfe0e 4035 u8 mimo_ps_mode;
b481de9c 4036
67d62035 4037 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
b481de9c
ZY		 4038 goto done;
4039
e53cfe0e
TW		 4040 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4041
b481de9c
ZY		 4042 sta_flags = priv->stations[index].sta.station_flags;
4043
e53cfe0e
TW		 4044 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4045
4046 switch (mimo_ps_mode) {
4047 case WLAN_HT_CAP_MIMO_PS_STATIC:
4048 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4049 break;
4050 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
b481de9c 4051 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
e53cfe0e
TW		 4052 break;
4053 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4054 break;
4055 default:
4056 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4057 break;
4058 }
b481de9c
ZY		 4059
4060 sta_flags |= cpu_to_le32(
67d62035 4061 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
b481de9c
ZY		 4062
4063 sta_flags |= cpu_to_le32(
67d62035 4064 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
b481de9c 4065
67d62035 4066 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
b481de9c 4067 sta_flags |= STA_FLG_FAT_EN_MSK;
67d62035 4068 else
e53cfe0e 4069 sta_flags &= ~STA_FLG_FAT_EN_MSK;
67d62035 4070
b481de9c
ZY		 4071 priv->stations[index].sta.station_flags = sta_flags;
4072 done:
4073 return;
4074}
4075
fe07aa7a
RR		 4076static int iwl4965_rx_agg_start(struct iwl_priv *priv,
4077 const u8 *addr, int tid, u16 ssn)
b481de9c
ZY		 4078{
4079 unsigned long flags;
fe07aa7a
RR		 4080 int sta_id;
4081
4082 sta_id = iwl_find_station(priv, addr);
4083 if (sta_id == IWL_INVALID_STATION)
4084 return -ENXIO;
b481de9c
ZY		 4085
4086 spin_lock_irqsave(&priv->sta_lock, flags);
4087 priv->stations[sta_id].sta.station_flags_msk = 0;
4088 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4089 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4090 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4091 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4092 spin_unlock_irqrestore(&priv->sta_lock, flags);
4093
fe07aa7a
RR		 4094 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4095 CMD_ASYNC);
b481de9c
ZY		 4096}
4097
fe07aa7a
RR		 4098static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
4099 const u8 *addr, int tid)
b481de9c
ZY		 4100{
4101 unsigned long flags;
fe07aa7a
RR		 4102 int sta_id;
4103
4104 sta_id = iwl_find_station(priv, addr);
4105 if (sta_id == IWL_INVALID_STATION)
4106 return -ENXIO;
b481de9c
ZY		 4107
4108 spin_lock_irqsave(&priv->sta_lock, flags);
4109 priv->stations[sta_id].sta.station_flags_msk = 0;
4110 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4111 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4112 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4113 spin_unlock_irqrestore(&priv->sta_lock, flags);
4114
fe07aa7a
RR		 4115 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4116 CMD_ASYNC);
b481de9c
ZY		 4117}
4118
8b6eaea8
CB		 4119/*
4120 * Find first available (lowest unused) Tx Queue, mark it "active".
4121 * Called only when finding queue for aggregation.
4122 * Should never return anything < 7, because they should already
4123 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4124 */
c79dd5b5 4125static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
b481de9c
ZY		 4126{
4127 int txq_id;
4128
5425e490 4129 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
b481de9c
ZY		 4130 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4131 return txq_id;
4132 return -1;
4133}
4134
fe07aa7a
RR		 4135static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
4136 u16 tid, u16 *start_seq_num)
b481de9c 4137{
c79dd5b5 4138 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 4139 int sta_id;
4140 int tx_fifo;
4141 int txq_id;
4142 int ssn = -1;
b095d03a 4143 int ret = 0;
b481de9c 4144 unsigned long flags;
bb8c093b 4145 struct iwl4965_tid_data *tid_data;
0795af57 4146 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 4147
4148 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4149 tx_fifo = default_tid_to_tx_fifo[tid];
4150 else
4151 return -EINVAL;
4152
fe07aa7a
RR		 4153 IWL_WARNING("%s on ra = %s tid = %d\n",
4154 __func__, print_mac(mac, ra), tid);
b481de9c 4155
fe07aa7a 4156 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 4157 if (sta_id == IWL_INVALID_STATION)
4158 return -ENXIO;
4159
fe01b477
RR		 4160 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4161 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4162 return -ENXIO;
4163 }
4164
bb8c093b 4165 txq_id = iwl4965_txq_ctx_activate_free(priv);
b481de9c
ZY		 4166 if (txq_id == -1)
4167 return -ENXIO;
4168
4169 spin_lock_irqsave(&priv->sta_lock, flags);
4170 tid_data = &priv->stations[sta_id].tid[tid];
4171 ssn = SEQ_TO_SN(tid_data->seq_number);
4172 tid_data->agg.txq_id = txq_id;
4173 spin_unlock_irqrestore(&priv->sta_lock, flags);
4174
4175 *start_seq_num = ssn;
b095d03a
RR		 4176 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4177 sta_id, tid, ssn);
4178 if (ret)
4179 return ret;
b481de9c 4180
b095d03a 4181 ret = 0;
fe01b477
RR		 4182 if (tid_data->tfds_in_queue == 0) {
4183 printk(KERN_ERR "HW queue is empty\n");
4184 tid_data->agg.state = IWL_AGG_ON;
fe07aa7a 4185 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
fe01b477
RR		 4186 } else {
4187 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4188 tid_data->tfds_in_queue);
4189 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4190 }
b095d03a 4191 return ret;
fe01b477 4192}
b481de9c 4193
fe07aa7a 4194static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
b481de9c 4195{
c79dd5b5 4196 struct iwl_priv *priv = hw->priv;
b481de9c 4197 int tx_fifo_id, txq_id, sta_id, ssn = -1;
bb8c093b 4198 struct iwl4965_tid_data *tid_data;
b095d03a 4199 int ret, write_ptr, read_ptr;
fe01b477 4200 unsigned long flags;
0795af57
JP		 4201 DECLARE_MAC_BUF(mac);
4202
fe07aa7a
RR		 4203 if (!ra) {
4204 IWL_ERROR("ra = NULL\n");
b481de9c
ZY		 4205 return -EINVAL;
4206 }
4207
4208 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4209 tx_fifo_id = default_tid_to_tx_fifo[tid];
4210 else
4211 return -EINVAL;
4212
fe07aa7a 4213 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 4214
4215 if (sta_id == IWL_INVALID_STATION)
4216 return -ENXIO;
4217
fe01b477
RR		 4218 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4219 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4220
b481de9c
ZY		 4221 tid_data = &priv->stations[sta_id].tid[tid];
4222 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4223 txq_id = tid_data->agg.txq_id;
fe01b477
RR		 4224 write_ptr = priv->txq[txq_id].q.write_ptr;
4225 read_ptr = priv->txq[txq_id].q.read_ptr;
4226
4227 /* The queue is not empty */
4228 if (write_ptr != read_ptr) {
4229 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4230 priv->stations[sta_id].tid[tid].agg.state =
4231 IWL_EMPTYING_HW_QUEUE_DELBA;
4232 return 0;
4233 }
4234
fe07aa7a 4235 IWL_DEBUG_HT("HW queue is empty\n");
fe01b477 4236 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
b481de9c 4237
fe01b477 4238 spin_lock_irqsave(&priv->lock, flags);
b095d03a 4239 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
fe01b477
RR		 4240 spin_unlock_irqrestore(&priv->lock, flags);
4241
b095d03a
RR		 4242 if (ret)
4243 return ret;
b481de9c 4244
fe07aa7a 4245 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
8114fcf1 4246
8114fcf1
RR		 4247 return 0;
4248}
4249
4250int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4251 enum ieee80211_ampdu_mlme_action action,
4252 const u8 *addr, u16 tid, u16 *ssn)
4253{
c79dd5b5 4254 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 4255 DECLARE_MAC_BUF(mac);
4256
fe07aa7a
RR		 4257 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4258 print_mac(mac, addr), tid);
4259
8114fcf1
RR		 4260 switch (action) {
4261 case IEEE80211_AMPDU_RX_START:
4262 IWL_DEBUG_HT("start Rx\n");
fe07aa7a 4263 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
8114fcf1
RR		 4264 case IEEE80211_AMPDU_RX_STOP:
4265 IWL_DEBUG_HT("stop Rx\n");
fe07aa7a 4266 return iwl4965_rx_agg_stop(priv, addr, tid);
8114fcf1
RR		 4267 case IEEE80211_AMPDU_TX_START:
4268 IWL_DEBUG_HT("start Tx\n");
fe07aa7a 4269 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
8114fcf1
RR		 4270 case IEEE80211_AMPDU_TX_STOP:
4271 IWL_DEBUG_HT("stop Tx\n");
fe07aa7a 4272 return iwl4965_tx_agg_stop(hw, addr, tid);
8114fcf1
RR		 4273 default:
4274 IWL_DEBUG_HT("unknown\n");
4275 return -EINVAL;
4276 break;
4277 }
4278 return 0;
4279}
4280
c8b0e6e1 4281#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4282
4283/* Set up 4965-specific Rx frame reply handlers */
c79dd5b5 4284void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 4285{
4286 /* Legacy Rx frames */
857485c0 4287 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
b481de9c
ZY		 4288
4289 /* High-throughput (HT) Rx frames */
4290 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4291 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4292
4293 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4294 iwl4965_rx_missed_beacon_notif;
4295
c8b0e6e1 4296#ifdef CONFIG_IWL4965_HT
b481de9c 4297 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
c8b0e6e1 4298#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4299}
4300
c79dd5b5 4301void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4302{
4303 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
f0832f13 4304#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 4305 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4306#endif
b481de9c
ZY		 4307 init_timer(&priv->statistics_periodic);
4308 priv->statistics_periodic.data = (unsigned long)priv;
4309 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4310}
4311
c79dd5b5 4312void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4313{
4314 del_timer_sync(&priv->statistics_periodic);
4315
4316 cancel_delayed_work(&priv->init_alive_start);
4317}
4318
3c424c28
TW		 4319
4320static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 4321 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 4322};
4323
857485c0
TW		 4324static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4325 .enqueue_hcmd = iwl4965_enqueue_hcmd,
f0832f13
EG		 4326#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4327 .chain_noise_reset = iwl4965_chain_noise_reset,
4328 .gain_computation = iwl4965_gain_computation,
4329#endif
857485c0
TW		 4330};
4331
6bc913bd 4332static struct iwl_lib_ops iwl4965_lib = {
bf85ea4f 4333 .init_drv = iwl4965_init_drv,
5425e490 4334 .set_hw_params = iwl4965_hw_set_hw_params,
e2a722eb 4335 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
57aab75a
TW		 4336 .hw_nic_init = iwl4965_hw_nic_init,
4337 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4338 .alive_notify = iwl4965_alive_notify,
4339 .load_ucode = iwl4965_load_bsm,
6f4083aa 4340 .apm_ops = {
91238714 4341 .init = iwl4965_apm_init,
6f4083aa
TW		 4342 .set_pwr_src = iwl4965_set_pwr_src,
4343 },
6bc913bd 4344 .eeprom_ops = {
073d3f5f
TW		 4345 .regulatory_bands = {
4346 EEPROM_REGULATORY_BAND_1_CHANNELS,
4347 EEPROM_REGULATORY_BAND_2_CHANNELS,
4348 EEPROM_REGULATORY_BAND_3_CHANNELS,
4349 EEPROM_REGULATORY_BAND_4_CHANNELS,
4350 EEPROM_REGULATORY_BAND_5_CHANNELS,
4351 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
4352 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
4353 },
6bc913bd
AK		 4354 .verify_signature = iwlcore_eeprom_verify_signature,
4355 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4356 .release_semaphore = iwlcore_eeprom_release_semaphore,
073d3f5f 4357 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 4358 },
ad97edd2 4359 .radio_kill_sw = iwl4965_radio_kill_sw,
5da4b55f
MA		 4360 .set_power = iwl4965_set_power,
4361 .update_chain_flags = iwl4965_update_chain_flags,
6bc913bd
AK		 4362};
4363
4364static struct iwl_ops iwl4965_ops = {
4365 .lib = &iwl4965_lib,
3c424c28 4366 .hcmd = &iwl4965_hcmd,
857485c0 4367 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 4368};
4369
fed9017e 4370struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 4371 .name = "4965AGN",
4bf775cd 4372 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 4373 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 4374 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
6bc913bd 4375 .ops = &iwl4965_ops,
1ea87396 4376 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 4377};
4378
1ea87396
AK		 4379module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4380MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4381module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4382MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b
EG		 4383module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4384MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
1ea87396
AK		 4385module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4386MODULE_PARM_DESC(debug, "debug output mask");
4387module_param_named(
4388 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4389MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4390
4391module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4392MODULE_PARM_DESC(queues_num, "number of hw queues.");
4393
4394/* QoS */
4395module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4396MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4397module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4398MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4399
Linux kernel - Deliverables
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