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iwlwifi: CT-Kill configuration fix
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
b481de9c 42#include "iwl-4965.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c 45#include "iwl-helpers.h"
f0832f13 46#include "iwl-calib.h"
b481de9c 47
1ea87396
AK		 48/* module parameters */
49static struct iwl_mod_params iwl4965_mod_params = {
dfe7d458 50 .num_of_queues = IWL4965_MAX_NUM_QUEUES,
1ea87396
AK		 51 .enable_qos = 1,
52 .amsdu_size_8K = 1,
53 /* the rest are 0 by default */
54};
55
c79dd5b5 56static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
416e1438 57
b481de9c
ZY		 58#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
59 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
60 IWL_RATE_SISO_##s##M_PLCP, \
61 IWL_RATE_MIMO_##s##M_PLCP, \
62 IWL_RATE_##r##M_IEEE, \
63 IWL_RATE_##ip##M_INDEX, \
64 IWL_RATE_##in##M_INDEX, \
65 IWL_RATE_##rp##M_INDEX, \
66 IWL_RATE_##rn##M_INDEX, \
67 IWL_RATE_##pp##M_INDEX, \
68 IWL_RATE_##np##M_INDEX }
69
70/*
71 * Parameter order:
72 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
73 *
74 * If there isn't a valid next or previous rate then INV is used which
75 * maps to IWL_RATE_INVALID
76 *
77 */
bb8c093b 78const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
b481de9c
ZY		 79 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
80 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
81 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
82 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
83 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
84 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
85 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
86 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
87 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
88 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
89 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
90 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
91 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
92};
93
fe01b477
RR		 94#ifdef CONFIG_IWL4965_HT
95
96static const u16 default_tid_to_tx_fifo[] = {
97 IWL_TX_FIFO_AC1,
98 IWL_TX_FIFO_AC0,
99 IWL_TX_FIFO_AC0,
100 IWL_TX_FIFO_AC1,
101 IWL_TX_FIFO_AC2,
102 IWL_TX_FIFO_AC2,
103 IWL_TX_FIFO_AC3,
104 IWL_TX_FIFO_AC3,
105 IWL_TX_FIFO_NONE,
106 IWL_TX_FIFO_NONE,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_NONE,
113 IWL_TX_FIFO_AC3
114};
115
116#endif /*CONFIG_IWL4965_HT */
117
57aab75a
TW		 118/* check contents of special bootstrap uCode SRAM */
119static int iwl4965_verify_bsm(struct iwl_priv *priv)
120{
121 __le32 *image = priv->ucode_boot.v_addr;
122 u32 len = priv->ucode_boot.len;
123 u32 reg;
124 u32 val;
125
126 IWL_DEBUG_INFO("Begin verify bsm\n");
127
128 /* verify BSM SRAM contents */
129 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
130 for (reg = BSM_SRAM_LOWER_BOUND;
131 reg < BSM_SRAM_LOWER_BOUND + len;
132 reg += sizeof(u32), image++) {
133 val = iwl_read_prph(priv, reg);
134 if (val != le32_to_cpu(*image)) {
135 IWL_ERROR("BSM uCode verification failed at "
136 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
137 BSM_SRAM_LOWER_BOUND,
138 reg - BSM_SRAM_LOWER_BOUND, len,
139 val, le32_to_cpu(*image));
140 return -EIO;
141 }
142 }
143
144 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
145
146 return 0;
147}
148
149/**
150 * iwl4965_load_bsm - Load bootstrap instructions
151 *
152 * BSM operation:
153 *
154 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
155 * in special SRAM that does not power down during RFKILL. When powering back
156 * up after power-saving sleeps (or during initial uCode load), the BSM loads
157 * the bootstrap program into the on-board processor, and starts it.
158 *
159 * The bootstrap program loads (via DMA) instructions and data for a new
160 * program from host DRAM locations indicated by the host driver in the
161 * BSM_DRAM_* registers. Once the new program is loaded, it starts
162 * automatically.
163 *
164 * When initializing the NIC, the host driver points the BSM to the
165 * "initialize" uCode image. This uCode sets up some internal data, then
166 * notifies host via "initialize alive" that it is complete.
167 *
168 * The host then replaces the BSM_DRAM_* pointer values to point to the
169 * normal runtime uCode instructions and a backup uCode data cache buffer
170 * (filled initially with starting data values for the on-board processor),
171 * then triggers the "initialize" uCode to load and launch the runtime uCode,
172 * which begins normal operation.
173 *
174 * When doing a power-save shutdown, runtime uCode saves data SRAM into
175 * the backup data cache in DRAM before SRAM is powered down.
176 *
177 * When powering back up, the BSM loads the bootstrap program. This reloads
178 * the runtime uCode instructions and the backup data cache into SRAM,
179 * and re-launches the runtime uCode from where it left off.
180 */
181static int iwl4965_load_bsm(struct iwl_priv *priv)
182{
183 __le32 *image = priv->ucode_boot.v_addr;
184 u32 len = priv->ucode_boot.len;
185 dma_addr_t pinst;
186 dma_addr_t pdata;
187 u32 inst_len;
188 u32 data_len;
189 int i;
190 u32 done;
191 u32 reg_offset;
192 int ret;
193
194 IWL_DEBUG_INFO("Begin load bsm\n");
195
196 /* make sure bootstrap program is no larger than BSM's SRAM size */
197 if (len > IWL_MAX_BSM_SIZE)
198 return -EINVAL;
199
200 /* Tell bootstrap uCode where to find the "Initialize" uCode
201 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
202 * NOTE: iwl4965_initialize_alive_start() will replace these values,
203 * after the "initialize" uCode has run, to point to
204 * runtime/protocol instructions and backup data cache. */
205 pinst = priv->ucode_init.p_addr >> 4;
206 pdata = priv->ucode_init_data.p_addr >> 4;
207 inst_len = priv->ucode_init.len;
208 data_len = priv->ucode_init_data.len;
209
210 ret = iwl_grab_nic_access(priv);
211 if (ret)
212 return ret;
213
214 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
215 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
216 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
217 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
218
219 /* Fill BSM memory with bootstrap instructions */
220 for (reg_offset = BSM_SRAM_LOWER_BOUND;
221 reg_offset < BSM_SRAM_LOWER_BOUND + len;
222 reg_offset += sizeof(u32), image++)
223 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
224
225 ret = iwl4965_verify_bsm(priv);
226 if (ret) {
227 iwl_release_nic_access(priv);
228 return ret;
229 }
230
231 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
232 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
233 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
234 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
235
236 /* Load bootstrap code into instruction SRAM now,
237 * to prepare to load "initialize" uCode */
238 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
239
240 /* Wait for load of bootstrap uCode to finish */
241 for (i = 0; i < 100; i++) {
242 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
243 if (!(done & BSM_WR_CTRL_REG_BIT_START))
244 break;
245 udelay(10);
246 }
247 if (i < 100)
248 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
249 else {
250 IWL_ERROR("BSM write did not complete!\n");
251 return -EIO;
252 }
253
254 /* Enable future boot loads whenever power management unit triggers it
255 * (e.g. when powering back up after power-save shutdown) */
256 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
257
258 iwl_release_nic_access(priv);
259
260 return 0;
261}
262
bf85ea4f
AK		 263static int iwl4965_init_drv(struct iwl_priv *priv)
264{
265 int ret;
266 int i;
267
1ea87396 268 priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
bf85ea4f
AK		 269 priv->retry_rate = 1;
270 priv->ibss_beacon = NULL;
271
272 spin_lock_init(&priv->lock);
273 spin_lock_init(&priv->power_data.lock);
274 spin_lock_init(&priv->sta_lock);
275 spin_lock_init(&priv->hcmd_lock);
276 spin_lock_init(&priv->lq_mngr.lock);
277
059ff826
TW		 278 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
279 sizeof(struct iwl4965_shared),
280 &priv->shared_phys);
281
282 if (!priv->shared_virt) {
283 ret = -ENOMEM;
284 goto err;
285 }
286
287 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
288
289
bf85ea4f
AK		 290 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
291 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
292
293 INIT_LIST_HEAD(&priv->free_frames);
294
295 mutex_init(&priv->mutex);
296
297 /* Clear the driver's (not device's) station table */
298 iwlcore_clear_stations_table(priv);
299
300 priv->data_retry_limit = -1;
301 priv->ieee_channels = NULL;
302 priv->ieee_rates = NULL;
303 priv->band = IEEE80211_BAND_2GHZ;
304
305 priv->iw_mode = IEEE80211_IF_TYPE_STA;
306
307 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
308 priv->valid_antenna = 0x7; /* assume all 3 connected */
309 priv->ps_mode = IWL_MIMO_PS_NONE;
310
311 /* Choose which receivers/antennas to use */
312 iwl4965_set_rxon_chain(priv);
313
314 iwlcore_reset_qos(priv);
315
316 priv->qos_data.qos_active = 0;
317 priv->qos_data.qos_cap.val = 0;
318
319 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
320
321 priv->rates_mask = IWL_RATES_MASK;
322 /* If power management is turned on, default to AC mode */
323 priv->power_mode = IWL_POWER_AC;
324 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
325
326 ret = iwl_init_channel_map(priv);
327 if (ret) {
328 IWL_ERROR("initializing regulatory failed: %d\n", ret);
329 goto err;
330 }
331
332 ret = iwl4965_init_geos(priv);
333 if (ret) {
334 IWL_ERROR("initializing geos failed: %d\n", ret);
335 goto err_free_channel_map;
336 }
337
bf85ea4f
AK		 338 ret = ieee80211_register_hw(priv->hw);
339 if (ret) {
340 IWL_ERROR("Failed to register network device (error %d)\n",
341 ret);
342 goto err_free_geos;
343 }
344
345 priv->hw->conf.beacon_int = 100;
346 priv->mac80211_registered = 1;
347
348 return 0;
349
350err_free_geos:
351 iwl4965_free_geos(priv);
352err_free_channel_map:
353 iwl_free_channel_map(priv);
354err:
355 return ret;
356}
357
b481de9c
ZY		 358static int is_fat_channel(__le32 rxon_flags)
359{
360 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
361 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
362}
363
c79dd5b5 364static u8 is_single_stream(struct iwl_priv *priv)
b481de9c 365{
c8b0e6e1 366#ifdef CONFIG_IWL4965_HT
fd105e79
RR		 367 if (!priv->current_ht_config.is_ht ||
368 (priv->current_ht_config.supp_mcs_set[1] == 0) ||
b481de9c
ZY		 369 (priv->ps_mode == IWL_MIMO_PS_STATIC))
370 return 1;
371#else
372 return 1;
c8b0e6e1 373#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 374 return 0;
375}
376
17744ff6
TW		 377int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
378{
379 int idx = 0;
380
381 /* 4965 HT rate format */
382 if (rate_n_flags & RATE_MCS_HT_MSK) {
383 idx = (rate_n_flags & 0xff);
384
385 if (idx >= IWL_RATE_MIMO_6M_PLCP)
386 idx = idx - IWL_RATE_MIMO_6M_PLCP;
387
388 idx += IWL_FIRST_OFDM_RATE;
389 /* skip 9M not supported in ht*/
390 if (idx >= IWL_RATE_9M_INDEX)
391 idx += 1;
392 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
393 return idx;
394
395 /* 4965 legacy rate format, search for match in table */
396 } else {
397 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
398 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
399 return idx;
400 }
401
402 return -1;
403}
404
4c424e4c
RR		 405/**
406 * translate ucode response to mac80211 tx status control values
407 */
c79dd5b5 408void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
4c424e4c
RR		 409 struct ieee80211_tx_control *control)
410{
411 int rate_index;
412
413 control->antenna_sel_tx =
ec35cf2a 414 ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_POS);
4c424e4c
RR		 415 if (rate_n_flags & RATE_MCS_HT_MSK)
416 control->flags |= IEEE80211_TXCTL_OFDM_HT;
417 if (rate_n_flags & RATE_MCS_GF_MSK)
418 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
419 if (rate_n_flags & RATE_MCS_FAT_MSK)
420 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
421 if (rate_n_flags & RATE_MCS_DUP_MSK)
422 control->flags |= IEEE80211_TXCTL_DUP_DATA;
423 if (rate_n_flags & RATE_MCS_SGI_MSK)
424 control->flags |= IEEE80211_TXCTL_SHORT_GI;
425 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
426 * IEEE80211_BAND_2GHZ band as it contains all the rates */
427 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
428 if (rate_index == -1)
429 control->tx_rate = NULL;
430 else
431 control->tx_rate =
432 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
433}
17744ff6 434
b481de9c
ZY		 435/*
436 * Determine how many receiver/antenna chains to use.
437 * More provides better reception via diversity. Fewer saves power.
438 * MIMO (dual stream) requires at least 2, but works better with 3.
439 * This does not determine *which* chains to use, just how many.
440 */
c79dd5b5 441static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
b481de9c
ZY		 442 u8 *idle_state, u8 *rx_state)
443{
444 u8 is_single = is_single_stream(priv);
445 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
446
447 /* # of Rx chains to use when expecting MIMO. */
448 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
449 *rx_state = 2;
450 else
451 *rx_state = 3;
452
453 /* # Rx chains when idling and maybe trying to save power */
454 switch (priv->ps_mode) {
455 case IWL_MIMO_PS_STATIC:
456 case IWL_MIMO_PS_DYNAMIC:
457 *idle_state = (is_cam) ? 2 : 1;
458 break;
459 case IWL_MIMO_PS_NONE:
460 *idle_state = (is_cam) ? *rx_state : 1;
461 break;
462 default:
463 *idle_state = 1;
464 break;
465 }
466
467 return 0;
468}
469
c79dd5b5 470int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 471{
472 int rc;
473 unsigned long flags;
474
475 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 476 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 477 if (rc) {
478 spin_unlock_irqrestore(&priv->lock, flags);
479 return rc;
480 }
481
8b6eaea8 482 /* stop Rx DMA */
3395f6e9
TW		 483 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
484 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
b481de9c
ZY		 485 (1 << 24), 1000);
486 if (rc < 0)
487 IWL_ERROR("Can't stop Rx DMA.\n");
488
3395f6e9 489 iwl_release_nic_access(priv);
b481de9c
ZY		 490 spin_unlock_irqrestore(&priv->lock, flags);
491
492 return 0;
493}
494
079a2533 495int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 496{
d8609652 497 int ret;
b481de9c
ZY		 498 unsigned long flags;
499
500 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 501 ret = iwl_grab_nic_access(priv);
d8609652 502 if (ret) {
b481de9c 503 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 504 return ret;
b481de9c
ZY		 505 }
506
6f4083aa 507 if (src == IWL_PWR_SRC_VAUX) {
b481de9c 508 u32 val;
d8609652 509 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
6f4083aa 510 &val);
b481de9c 511
6f4083aa 512 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
3395f6e9 513 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 514 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
515 ~APMG_PS_CTRL_MSK_PWR_SRC);
516 }
517 } else {
3395f6e9 518 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
6f4083aa
TW		 519 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
520 ~APMG_PS_CTRL_MSK_PWR_SRC);
521 }
b481de9c 522
3395f6e9 523 iwl_release_nic_access(priv);
b481de9c
ZY		 524 spin_unlock_irqrestore(&priv->lock, flags);
525
d8609652 526 return ret;
b481de9c
ZY		 527}
528
c79dd5b5 529static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c 530{
059ff826 531 int ret;
b481de9c 532 unsigned long flags;
9ee1ba47 533 unsigned int rb_size;
b481de9c
ZY		 534
535 spin_lock_irqsave(&priv->lock, flags);
059ff826
TW		 536 ret = iwl_grab_nic_access(priv);
537 if (ret) {
b481de9c 538 spin_unlock_irqrestore(&priv->lock, flags);
059ff826 539 return ret;
b481de9c
ZY		 540 }
541
1ea87396 542 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 543 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
544 else
545 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
546
8b6eaea8 547 /* Stop Rx DMA */
3395f6e9 548 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
b481de9c 549
8b6eaea8 550 /* Reset driver's Rx queue write index */
3395f6e9 551 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
8b6eaea8
CB		 552
553 /* Tell device where to find RBD circular buffer in DRAM */
3395f6e9
TW		 554 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
555 rxq->dma_addr >> 8);
b481de9c 556
8b6eaea8 557 /* Tell device where in DRAM to update its Rx status */
3395f6e9 558 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
059ff826
TW		 559 (priv->shared_phys +
560 offsetof(struct iwl4965_shared, rb_closed)) >> 4);
b481de9c 561
8b6eaea8 562 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
3395f6e9
TW		 563 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
564 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
565 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
566 rb_size |
059ff826 567 /* 0x10 << 4 | */
3395f6e9 568 (RX_QUEUE_SIZE_LOG <<
b481de9c
ZY		 569 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
570
571 /*
3395f6e9 572 * iwl_write32(priv,CSR_INT_COAL_REG,0);
b481de9c
ZY		 573 */
574
3395f6e9 575 iwl_release_nic_access(priv);
b481de9c
ZY		 576 spin_unlock_irqrestore(&priv->lock, flags);
577
578 return 0;
579}
580
8b6eaea8 581/* Tell 4965 where to find the "keep warm" buffer */
c79dd5b5 582static int iwl4965_kw_init(struct iwl_priv *priv)
b481de9c
ZY		 583{
584 unsigned long flags;
585 int rc;
586
587 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 588 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 589 if (rc)
590 goto out;
591
3395f6e9 592 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
b481de9c 593 priv->kw.dma_addr >> 4);
3395f6e9 594 iwl_release_nic_access(priv);
b481de9c
ZY		 595out:
596 spin_unlock_irqrestore(&priv->lock, flags);
597 return rc;
598}
599
c79dd5b5 600static int iwl4965_kw_alloc(struct iwl_priv *priv)
b481de9c
ZY		 601{
602 struct pci_dev *dev = priv->pci_dev;
bb8c093b 603 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 604
605 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
606 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
607 if (!kw->v_addr)
608 return -ENOMEM;
609
610 return 0;
611}
612
8b6eaea8
CB		 613/**
614 * iwl4965_kw_free - Free the "keep warm" buffer
615 */
c79dd5b5 616static void iwl4965_kw_free(struct iwl_priv *priv)
b481de9c
ZY		 617{
618 struct pci_dev *dev = priv->pci_dev;
bb8c093b 619 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 620
621 if (kw->v_addr) {
622 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
623 memset(kw, 0, sizeof(*kw));
624 }
625}
626
627/**
628 * iwl4965_txq_ctx_reset - Reset TX queue context
629 * Destroys all DMA structures and initialise them again
630 *
631 * @param priv
632 * @return error code
633 */
c79dd5b5 634static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 635{
636 int rc = 0;
637 int txq_id, slots_num;
638 unsigned long flags;
639
640 iwl4965_kw_free(priv);
641
8b6eaea8 642 /* Free all tx/cmd queues and keep-warm buffer */
bb8c093b 643 iwl4965_hw_txq_ctx_free(priv);
b481de9c 644
8b6eaea8 645 /* Alloc keep-warm buffer */
b481de9c
ZY		 646 rc = iwl4965_kw_alloc(priv);
647 if (rc) {
648 IWL_ERROR("Keep Warm allocation failed");
649 goto error_kw;
650 }
651
652 spin_lock_irqsave(&priv->lock, flags);
653
3395f6e9 654 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 655 if (unlikely(rc)) {
656 IWL_ERROR("TX reset failed");
657 spin_unlock_irqrestore(&priv->lock, flags);
658 goto error_reset;
659 }
660
8b6eaea8 661 /* Turn off all Tx DMA channels */
12a81f60 662 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
3395f6e9 663 iwl_release_nic_access(priv);
b481de9c
ZY		 664 spin_unlock_irqrestore(&priv->lock, flags);
665
8b6eaea8 666 /* Tell 4965 where to find the keep-warm buffer */
b481de9c
ZY		 667 rc = iwl4965_kw_init(priv);
668 if (rc) {
669 IWL_ERROR("kw_init failed\n");
670 goto error_reset;
671 }
672
8b6eaea8
CB		 673 /* Alloc and init all (default 16) Tx queues,
674 * including the command queue (#4) */
5425e490 675 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 676 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
677 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 678 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 679 txq_id);
680 if (rc) {
681 IWL_ERROR("Tx %d queue init failed\n", txq_id);
682 goto error;
683 }
684 }
685
686 return rc;
687
688 error:
bb8c093b 689 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 690 error_reset:
691 iwl4965_kw_free(priv);
692 error_kw:
693 return rc;
694}
695
c79dd5b5 696int iwl4965_hw_nic_init(struct iwl_priv *priv)
b481de9c
ZY		 697{
698 int rc;
699 unsigned long flags;
bb8c093b 700 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c 701 u8 rev_id;
b481de9c 702 u8 val_link;
073d3f5f
TW		 703 u16 sku_cap;
704 u32 val;
b481de9c 705
b481de9c
ZY		 706 /* nic_init */
707 spin_lock_irqsave(&priv->lock, flags);
708
3395f6e9 709 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 710 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
711
3395f6e9
TW		 712 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
713 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 714 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
715 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
716 if (rc < 0) {
717 spin_unlock_irqrestore(&priv->lock, flags);
718 IWL_DEBUG_INFO("Failed to init the card\n");
719 return rc;
720 }
721
3395f6e9 722 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 723 if (rc) {
724 spin_unlock_irqrestore(&priv->lock, flags);
725 return rc;
726 }
727
3395f6e9 728 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c 729
3395f6e9
TW		 730 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
731 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
732 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c
ZY		 733
734 udelay(20);
735
3395f6e9
TW		 736 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
737 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 738
3395f6e9
TW		 739 iwl_release_nic_access(priv);
740 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
b481de9c
ZY		 741 spin_unlock_irqrestore(&priv->lock, flags);
742
743 /* Determine HW type */
744 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
745 if (rc)
746 return rc;
747
748 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
749
6f4083aa
TW		 750 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
751
b481de9c
ZY		 752 spin_lock_irqsave(&priv->lock, flags);
753
754 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
755 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
756 /* Enable No Snoop field */
757 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
758 val & ~(1 << 11));
759 }
760
761 spin_unlock_irqrestore(&priv->lock, flags);
762
073d3f5f
TW		 763 if (iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET) <
764 EEPROM_4965_TX_POWER_VERSION) {
b481de9c
ZY		 765 IWL_ERROR("Older EEPROM detected! Aborting.\n");
766 return -EINVAL;
767 }
768
769 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
770
771 /* disable L1 entry -- workaround for pre-B1 */
772 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
773
774 spin_lock_irqsave(&priv->lock, flags);
775
776 /* set CSR_HW_CONFIG_REG for uCode use */
777
3395f6e9
TW		 778 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
779 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
780 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
781 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 782
3395f6e9 783 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 784 if (rc < 0) {
785 spin_unlock_irqrestore(&priv->lock, flags);
786 IWL_DEBUG_INFO("Failed to init the card\n");
787 return rc;
788 }
789
3395f6e9
TW		 790 iwl_read_prph(priv, APMG_PS_CTRL_REG);
791 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 792 udelay(5);
3395f6e9 793 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 794
3395f6e9 795 iwl_release_nic_access(priv);
b481de9c
ZY		 796 spin_unlock_irqrestore(&priv->lock, flags);
797
bb8c093b 798 iwl4965_hw_card_show_info(priv);
b481de9c
ZY		 799
800 /* end nic_init */
801
802 /* Allocate the RX queue, or reset if it is already allocated */
803 if (!rxq->bd) {
bb8c093b 804 rc = iwl4965_rx_queue_alloc(priv);
b481de9c
ZY		 805 if (rc) {
806 IWL_ERROR("Unable to initialize Rx queue\n");
807 return -ENOMEM;
808 }
809 } else
bb8c093b 810 iwl4965_rx_queue_reset(priv, rxq);
b481de9c 811
bb8c093b 812 iwl4965_rx_replenish(priv);
b481de9c
ZY		 813
814 iwl4965_rx_init(priv, rxq);
815
816 spin_lock_irqsave(&priv->lock, flags);
817
818 rxq->need_update = 1;
bb8c093b 819 iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c 820
073d3f5f
TW		 821 /* init the txpower calibration pointer */
822 priv->calib_info = (struct iwl_eeprom_calib_info *)
823 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
824
b481de9c 825 spin_unlock_irqrestore(&priv->lock, flags);
8b6eaea8
CB		 826
827 /* Allocate and init all Tx and Command queues */
b481de9c
ZY		 828 rc = iwl4965_txq_ctx_reset(priv);
829 if (rc)
830 return rc;
831
073d3f5f
TW		 832 sku_cap = iwl_eeprom_query16(priv, EEPROM_SKU_CAP);
833 if (sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 834 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
835
073d3f5f 836 if (sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c
ZY		 837 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
838
839 set_bit(STATUS_INIT, &priv->status);
840
841 return 0;
842}
843
c79dd5b5 844int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 845{
846 int rc = 0;
847 u32 reg_val;
848 unsigned long flags;
849
850 spin_lock_irqsave(&priv->lock, flags);
851
852 /* set stop master bit */
3395f6e9 853 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 854
3395f6e9 855 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 856
857 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
858 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
859 IWL_DEBUG_INFO("Card in power save, master is already "
860 "stopped\n");
861 else {
3395f6e9 862 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 863 CSR_RESET_REG_FLAG_MASTER_DISABLED,
864 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
865 if (rc < 0) {
866 spin_unlock_irqrestore(&priv->lock, flags);
867 return rc;
868 }
869 }
870
871 spin_unlock_irqrestore(&priv->lock, flags);
872 IWL_DEBUG_INFO("stop master\n");
873
874 return rc;
875}
876
8b6eaea8
CB		 877/**
878 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
879 */
c79dd5b5 880void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c
ZY		 881{
882
883 int txq_id;
884 unsigned long flags;
885
8b6eaea8 886 /* Stop each Tx DMA channel, and wait for it to be idle */
5425e490 887 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c 888 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 889 if (iwl_grab_nic_access(priv)) {
b481de9c
ZY		 890 spin_unlock_irqrestore(&priv->lock, flags);
891 continue;
892 }
893
3395f6e9
TW		 894 iwl_write_direct32(priv,
895 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
896 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
897 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
898 (txq_id), 200);
899 iwl_release_nic_access(priv);
b481de9c
ZY		 900 spin_unlock_irqrestore(&priv->lock, flags);
901 }
902
8b6eaea8 903 /* Deallocate memory for all Tx queues */
bb8c093b 904 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 905}
906
c79dd5b5 907int iwl4965_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 908{
909 int rc = 0;
910 unsigned long flags;
911
bb8c093b 912 iwl4965_hw_nic_stop_master(priv);
b481de9c
ZY		 913
914 spin_lock_irqsave(&priv->lock, flags);
915
3395f6e9 916 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 917
918 udelay(10);
919
3395f6e9
TW		 920 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
921 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 922 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
923 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
924
925 udelay(10);
926
3395f6e9 927 rc = iwl_grab_nic_access(priv);
b481de9c 928 if (!rc) {
3395f6e9
TW		 929 iwl_write_prph(priv, APMG_CLK_EN_REG,
930 APMG_CLK_VAL_DMA_CLK_RQT |
931 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 932
933 udelay(10);
934
3395f6e9
TW		 935 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
936 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 937
3395f6e9 938 iwl_release_nic_access(priv);
b481de9c
ZY		 939 }
940
941 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
942 wake_up_interruptible(&priv->wait_command_queue);
943
944 spin_unlock_irqrestore(&priv->lock, flags);
945
946 return rc;
947
948}
949
950#define REG_RECALIB_PERIOD (60)
951
952/**
953 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
954 *
49ea8596 955 * This callback is provided in order to send a statistics request.
b481de9c
ZY		 956 *
957 * This timer function is continually reset to execute within
958 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
959 * was received. We need to ensure we receive the statistics in order
49ea8596 960 * to update the temperature used for calibrating the TXPOWER.
b481de9c
ZY		 961 */
962static void iwl4965_bg_statistics_periodic(unsigned long data)
963{
c79dd5b5 964 struct iwl_priv *priv = (struct iwl_priv *)data;
b481de9c 965
b481de9c
ZY		 966 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
967 return;
968
49ea8596 969 iwl_send_statistics_request(priv, CMD_ASYNC);
b481de9c
ZY		 970}
971
c79dd5b5 972void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 973{
bb8c093b 974 struct iwl4965_ct_kill_config cmd;
b481de9c 975 unsigned long flags;
857485c0 976 int ret = 0;
b481de9c
ZY		 977
978 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 979 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 980 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
981 spin_unlock_irqrestore(&priv->lock, flags);
982
099b40b7 983 cmd.critical_temperature_R =
b73cdf27
EG		 984 cpu_to_le32(priv->hw_params.ct_kill_threshold);
985
857485c0
TW		 986 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
987 sizeof(cmd), &cmd);
988 if (ret)
b481de9c
ZY		 989 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
990 else
b73cdf27
EG		 991 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
992 "critical temperature is %d\n",
993 cmd.critical_temperature_R);
b481de9c
ZY		 994}
995
f0832f13 996#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 997
998/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
999 * Called after every association, but this runs only once!
1000 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 1001static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 1002{
f0832f13 1003 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 1004
3109ece1 1005 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 1006 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1007
1008 memset(&cmd, 0, sizeof(cmd));
1009 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1010 cmd.diff_gain_a = 0;
1011 cmd.diff_gain_b = 0;
1012 cmd.diff_gain_c = 0;
f0832f13
EG		 1013 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1014 sizeof(cmd), &cmd))
1015 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 1016 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1017 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1018 }
b481de9c
ZY		 1019}
1020
f0832f13
EG		 1021static void iwl4965_gain_computation(struct iwl_priv *priv,
1022 u32 *average_noise,
1023 u16 min_average_noise_antenna_i,
1024 u32 min_average_noise)
b481de9c 1025{
f0832f13
EG		 1026 int i, ret;
1027 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 1028
f0832f13 1029 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 1030
f0832f13
EG		 1031 for (i = 0; i < NUM_RX_CHAINS; i++) {
1032 s32 delta_g = 0;
b481de9c 1033
f0832f13
EG		 1034 if (!(data->disconn_array[i]) &&
1035 (data->delta_gain_code[i] ==
b481de9c 1036 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 1037 delta_g = average_noise[i] - min_average_noise;
1038 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
1039 data->delta_gain_code[i] =
1040 min(data->delta_gain_code[i],
1041 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
1042
1043 data->delta_gain_code[i] =
1044 (data->delta_gain_code[i] | (1 << 2));
1045 } else {
1046 data->delta_gain_code[i] = 0;
b481de9c 1047 }
b481de9c 1048 }
f0832f13
EG		 1049 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1050 data->delta_gain_code[0],
1051 data->delta_gain_code[1],
1052 data->delta_gain_code[2]);
b481de9c 1053
f0832f13
EG		 1054 /* Differential gain gets sent to uCode only once */
1055 if (!data->radio_write) {
1056 struct iwl4965_calibration_cmd cmd;
1057 data->radio_write = 1;
b481de9c 1058
f0832f13
EG		 1059 memset(&cmd, 0, sizeof(cmd));
1060 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1061 cmd.diff_gain_a = data->delta_gain_code[0];
1062 cmd.diff_gain_b = data->delta_gain_code[1];
1063 cmd.diff_gain_c = data->delta_gain_code[2];
1064 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1065 sizeof(cmd), &cmd);
1066 if (ret)
1067 IWL_DEBUG_CALIB("fail sending cmd "
1068 "REPLY_PHY_CALIBRATION_CMD \n");
1069
1070 /* TODO we might want recalculate
1071 * rx_chain in rxon cmd */
1072
1073 /* Mark so we run this algo only once! */
1074 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 1075 }
f0832f13
EG		 1076 data->chain_noise_a = 0;
1077 data->chain_noise_b = 0;
1078 data->chain_noise_c = 0;
1079 data->chain_signal_a = 0;
1080 data->chain_signal_b = 0;
1081 data->chain_signal_c = 0;
1082 data->beacon_count = 0;
b481de9c
ZY		 1083}
1084
1085static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1086{
c79dd5b5 1087 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1088 sensitivity_work);
1089
1090 mutex_lock(&priv->mutex);
1091
1092 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1093 test_bit(STATUS_SCANNING, &priv->status)) {
1094 mutex_unlock(&priv->mutex);
1095 return;
1096 }
1097
1098 if (priv->start_calib) {
f0832f13
EG		 1099 iwl_chain_noise_calibration(priv, &priv->statistics);
1100
1101 iwl_sensitivity_calibration(priv, &priv->statistics);
b481de9c
ZY		 1102 }
1103
1104 mutex_unlock(&priv->mutex);
1105 return;
1106}
f0832f13 1107#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c
ZY		 1108
1109static void iwl4965_bg_txpower_work(struct work_struct *work)
1110{
c79dd5b5 1111 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1112 txpower_work);
1113
1114 /* If a scan happened to start before we got here
1115 * then just return; the statistics notification will
1116 * kick off another scheduled work to compensate for
1117 * any temperature delta we missed here. */
1118 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1119 test_bit(STATUS_SCANNING, &priv->status))
1120 return;
1121
1122 mutex_lock(&priv->mutex);
1123
1124 /* Regardless of if we are assocaited, we must reconfigure the
1125 * TX power since frames can be sent on non-radar channels while
1126 * not associated */
bb8c093b 1127 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 1128
1129 /* Update last_temperature to keep is_calib_needed from running
1130 * when it isn't needed... */
1131 priv->last_temperature = priv->temperature;
1132
1133 mutex_unlock(&priv->mutex);
1134}
1135
1136/*
1137 * Acquire priv->lock before calling this function !
1138 */
c79dd5b5 1139static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 1140{
3395f6e9 1141 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 1142 (index & 0xff) | (txq_id << 8));
12a81f60 1143 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 1144}
1145
8b6eaea8
CB		 1146/**
1147 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1148 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1149 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1150 *
1151 * NOTE: Acquire priv->lock before calling this function !
b481de9c 1152 */
c79dd5b5 1153static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
bb8c093b 1154 struct iwl4965_tx_queue *txq,
b481de9c
ZY		 1155 int tx_fifo_id, int scd_retry)
1156{
1157 int txq_id = txq->q.id;
8b6eaea8
CB		 1158
1159 /* Find out whether to activate Tx queue */
b481de9c
ZY		 1160 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1161
8b6eaea8 1162 /* Set up and activate */
12a81f60 1163 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
b481de9c
ZY		 1164 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1165 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1166 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1167 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1168 SCD_QUEUE_STTS_REG_MSK);
1169
1170 txq->sched_retry = scd_retry;
1171
1172 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 1173 active ? "Activate" : "Deactivate",
b481de9c
ZY		 1174 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1175}
1176
1177static const u16 default_queue_to_tx_fifo[] = {
1178 IWL_TX_FIFO_AC3,
1179 IWL_TX_FIFO_AC2,
1180 IWL_TX_FIFO_AC1,
1181 IWL_TX_FIFO_AC0,
1182 IWL_CMD_FIFO_NUM,
1183 IWL_TX_FIFO_HCCA_1,
1184 IWL_TX_FIFO_HCCA_2
1185};
1186
c79dd5b5 1187static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1188{
1189 set_bit(txq_id, &priv->txq_ctx_active_msk);
1190}
1191
c79dd5b5 1192static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1193{
1194 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1195}
1196
c79dd5b5 1197int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 1198{
1199 u32 a;
1200 int i = 0;
1201 unsigned long flags;
857485c0 1202 int ret;
b481de9c
ZY		 1203
1204 spin_lock_irqsave(&priv->lock, flags);
1205
f0832f13 1206#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c 1207 memset(&(priv->sensitivity_data), 0,
f0832f13 1208 sizeof(struct iwl_sensitivity_data));
b481de9c 1209 memset(&(priv->chain_noise_data), 0,
f0832f13 1210 sizeof(struct iwl_chain_noise_data));
b481de9c
ZY		 1211 for (i = 0; i < NUM_RX_CHAINS; i++)
1212 priv->chain_noise_data.delta_gain_code[i] =
1213 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
f0832f13 1214#endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
3395f6e9 1215 ret = iwl_grab_nic_access(priv);
857485c0 1216 if (ret) {
b481de9c 1217 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 1218 return ret;
b481de9c
ZY		 1219 }
1220
8b6eaea8 1221 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 1222 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
b481de9c
ZY		 1223 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1224 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 1225 iwl_write_targ_mem(priv, a, 0);
b481de9c 1226 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 1227 iwl_write_targ_mem(priv, a, 0);
5425e490 1228 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 1229 iwl_write_targ_mem(priv, a, 0);
b481de9c 1230
8b6eaea8 1231 /* Tel 4965 where to find Tx byte count tables */
12a81f60 1232 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 1233 (priv->shared_phys +
bb8c093b 1234 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 1235
1236 /* Disable chain mode for all queues */
12a81f60 1237 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 1238
8b6eaea8 1239 /* Initialize each Tx queue (including the command queue) */
5425e490 1240 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 1241
1242 /* TFD circular buffer read/write indexes */
12a81f60 1243 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 1244 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 1245
1246 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 1247 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1248 SCD_CONTEXT_QUEUE_OFFSET(i),
1249 (SCD_WIN_SIZE <<
1250 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1251 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 1252
1253 /* Frame limit */
3395f6e9 1254 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1255 SCD_CONTEXT_QUEUE_OFFSET(i) +
1256 sizeof(u32),
1257 (SCD_FRAME_LIMIT <<
1258 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1259 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1260
1261 }
12a81f60 1262 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 1263 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 1264
8b6eaea8 1265 /* Activate all Tx DMA/FIFO channels */
12a81f60 1266 iwl_write_prph(priv, IWL49_SCD_TXFACT,
b481de9c
ZY		 1267 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1268
1269 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 1270
1271 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 1272 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1273 int ac = default_queue_to_tx_fifo[i];
1274 iwl4965_txq_ctx_activate(priv, i);
1275 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1276 }
1277
3395f6e9 1278 iwl_release_nic_access(priv);
b481de9c
ZY		 1279 spin_unlock_irqrestore(&priv->lock, flags);
1280
49ea8596
EG		 1281 /* Ask for statistics now, the uCode will send statistics notification
1282 * periodically after association */
1283 iwl_send_statistics_request(priv, CMD_ASYNC);
857485c0 1284 return ret;
b481de9c
ZY		 1285}
1286
f0832f13
EG		 1287#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1288static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1289 .min_nrg_cck = 97,
1290 .max_nrg_cck = 0,
1291
1292 .auto_corr_min_ofdm = 85,
1293 .auto_corr_min_ofdm_mrc = 170,
1294 .auto_corr_min_ofdm_x1 = 105,
1295 .auto_corr_min_ofdm_mrc_x1 = 220,
1296
1297 .auto_corr_max_ofdm = 120,
1298 .auto_corr_max_ofdm_mrc = 210,
1299 .auto_corr_max_ofdm_x1 = 140,
1300 .auto_corr_max_ofdm_mrc_x1 = 270,
1301
1302 .auto_corr_min_cck = 125,
1303 .auto_corr_max_cck = 200,
1304 .auto_corr_min_cck_mrc = 200,
1305 .auto_corr_max_cck_mrc = 400,
1306
1307 .nrg_th_cck = 100,
1308 .nrg_th_ofdm = 100,
1309};
1310#endif
1311
8b6eaea8 1312/**
5425e490 1313 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 1314 *
1315 * Called when initializing driver
1316 */
5425e490 1317int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 1318{
316c30d9 1319
dfe7d458 1320 if ((priv->cfg->mod_params->num_of_queues > IWL4965_MAX_NUM_QUEUES) ||
1ea87396 1321 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 1322 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
dfe7d458 1323 IWL_MIN_NUM_QUEUES, IWL4965_MAX_NUM_QUEUES);
059ff826 1324 return -EINVAL;
316c30d9 1325 }
b481de9c 1326
5425e490 1327 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
099b40b7 1328 priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
5425e490
TW		 1329 priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1330 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1331 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 1332 if (priv->cfg->mod_params->amsdu_size_8K)
5425e490 1333 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
9ee1ba47 1334 else
5425e490
TW		 1335 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1336 priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1337 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1338 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822 1339
099b40b7
RR		 1340 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
1341 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
1342 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
1343 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
1344
ec35cf2a
TW		 1345 priv->hw_params.tx_chains_num = 2;
1346 priv->hw_params.rx_chains_num = 2;
1347 priv->hw_params.valid_tx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX);
1348 priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX);
099b40b7
RR		 1349 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
1350
f0832f13
EG		 1351#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1352 priv->hw_params.sens = &iwl4965_sensitivity;
1353#endif
3e82a822 1354
059ff826 1355 return 0;
b481de9c
ZY		 1356}
1357
1358/**
bb8c093b 1359 * iwl4965_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1360 *
1361 * Destroy all TX DMA queues and structures
1362 */
c79dd5b5 1363void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1364{
1365 int txq_id;
1366
1367 /* Tx queues */
5425e490 1368 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
bb8c093b 1369 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c 1370
8b6eaea8 1371 /* Keep-warm buffer */
b481de9c
ZY		 1372 iwl4965_kw_free(priv);
1373}
1374
1375/**
8b6eaea8 1376 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
b481de9c 1377 *
8b6eaea8
CB		 1378 * Does NOT advance any TFD circular buffer read/write indexes
1379 * Does NOT free the TFD itself (which is within circular buffer)
b481de9c 1380 */
c79dd5b5 1381int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 1382{
bb8c093b
CH		 1383 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1384 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 1385 struct pci_dev *dev = priv->pci_dev;
1386 int i;
1387 int counter = 0;
1388 int index, is_odd;
1389
8b6eaea8 1390 /* Host command buffers stay mapped in memory, nothing to clean */
b481de9c 1391 if (txq->q.id == IWL_CMD_QUEUE_NUM)
b481de9c
ZY		 1392 return 0;
1393
8b6eaea8 1394 /* Sanity check on number of chunks */
b481de9c
ZY		 1395 counter = IWL_GET_BITS(*bd, num_tbs);
1396 if (counter > MAX_NUM_OF_TBS) {
1397 IWL_ERROR("Too many chunks: %i\n", counter);
1398 /* @todo issue fatal error, it is quite serious situation */
1399 return 0;
1400 }
1401
8b6eaea8
CB		 1402 /* Unmap chunks, if any.
1403 * TFD info for odd chunks is different format than for even chunks. */
b481de9c
ZY		 1404 for (i = 0; i < counter; i++) {
1405 index = i / 2;
1406 is_odd = i & 0x1;
1407
1408 if (is_odd)
1409 pci_unmap_single(
1410 dev,
1411 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1412 (IWL_GET_BITS(bd->pa[index],
1413 tb2_addr_hi20) << 16),
1414 IWL_GET_BITS(bd->pa[index], tb2_len),
1415 PCI_DMA_TODEVICE);
1416
1417 else if (i > 0)
1418 pci_unmap_single(dev,
1419 le32_to_cpu(bd->pa[index].tb1_addr),
1420 IWL_GET_BITS(bd->pa[index], tb1_len),
1421 PCI_DMA_TODEVICE);
1422
8b6eaea8 1423 /* Free SKB, if any, for this chunk */
fc4b6853
TW		 1424 if (txq->txb[txq->q.read_ptr].skb[i]) {
1425 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
b481de9c
ZY		 1426
1427 dev_kfree_skb(skb);
fc4b6853 1428 txq->txb[txq->q.read_ptr].skb[i] = NULL;
b481de9c
ZY		 1429 }
1430 }
1431 return 0;
1432}
1433
5da4b55f
MA		 1434/* set card power command */
1435static int iwl4965_set_power(struct iwl_priv *priv,
1436 void *cmd)
1437{
1438 int ret = 0;
1439
1440 ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD,
1441 sizeof(struct iwl4965_powertable_cmd),
1442 cmd, NULL);
1443 return ret;
1444}
c79dd5b5 1445int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1446{
bb8c093b 1447 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
b481de9c
ZY		 1448 return -EINVAL;
1449}
1450
1451static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1452{
1453 s32 sign = 1;
1454
1455 if (num < 0) {
1456 sign = -sign;
1457 num = -num;
1458 }
1459 if (denom < 0) {
1460 sign = -sign;
1461 denom = -denom;
1462 }
1463 *res = 1;
1464 *res = ((num * 2 + denom) / (denom * 2)) * sign;
1465
1466 return 1;
1467}
1468
8b6eaea8
CB		 1469/**
1470 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1471 *
1472 * Determines power supply voltage compensation for txpower calculations.
1473 * Returns number of 1/2-dB steps to subtract from gain table index,
1474 * to compensate for difference between power supply voltage during
1475 * factory measurements, vs. current power supply voltage.
1476 *
1477 * Voltage indication is higher for lower voltage.
1478 * Lower voltage requires more gain (lower gain table index).
1479 */
b481de9c
ZY		 1480static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1481 s32 current_voltage)
1482{
1483 s32 comp = 0;
1484
1485 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1486 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1487 return 0;
1488
1489 iwl4965_math_div_round(current_voltage - eeprom_voltage,
1490 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1491
1492 if (current_voltage > eeprom_voltage)
1493 comp *= 2;
1494 if ((comp < -2) || (comp > 2))
1495 comp = 0;
1496
1497 return comp;
1498}
1499
bf85ea4f 1500static const struct iwl_channel_info *
c79dd5b5 1501iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
8318d78a 1502 enum ieee80211_band band, u16 channel)
b481de9c 1503{
bf85ea4f 1504 const struct iwl_channel_info *ch_info;
b481de9c 1505
8622e705 1506 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 1507
1508 if (!is_channel_valid(ch_info))
1509 return NULL;
1510
1511 return ch_info;
1512}
1513
1514static s32 iwl4965_get_tx_atten_grp(u16 channel)
1515{
1516 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1517 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1518 return CALIB_CH_GROUP_5;
1519
1520 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1521 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1522 return CALIB_CH_GROUP_1;
1523
1524 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1525 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1526 return CALIB_CH_GROUP_2;
1527
1528 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1529 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1530 return CALIB_CH_GROUP_3;
1531
1532 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1533 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1534 return CALIB_CH_GROUP_4;
1535
1536 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1537 return -1;
1538}
1539
c79dd5b5 1540static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 1541{
1542 s32 b = -1;
1543
1544 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 1545 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 1546 continue;
1547
073d3f5f
TW		 1548 if ((channel >= priv->calib_info->band_info[b].ch_from)
1549 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 1550 break;
1551 }
1552
1553 return b;
1554}
1555
1556static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1557{
1558 s32 val;
1559
1560 if (x2 == x1)
1561 return y1;
1562 else {
1563 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1564 return val + y2;
1565 }
1566}
1567
8b6eaea8
CB		 1568/**
1569 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1570 *
1571 * Interpolates factory measurements from the two sample channels within a
1572 * sub-band, to apply to channel of interest. Interpolation is proportional to
1573 * differences in channel frequencies, which is proportional to differences
1574 * in channel number.
1575 */
c79dd5b5 1576static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 1577 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 1578{
1579 s32 s = -1;
1580 u32 c;
1581 u32 m;
073d3f5f
TW		 1582 const struct iwl_eeprom_calib_measure *m1;
1583 const struct iwl_eeprom_calib_measure *m2;
1584 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 1585 u32 ch_i1;
1586 u32 ch_i2;
1587
1588 s = iwl4965_get_sub_band(priv, channel);
1589 if (s >= EEPROM_TX_POWER_BANDS) {
1590 IWL_ERROR("Tx Power can not find channel %d ", channel);
1591 return -1;
1592 }
1593
073d3f5f
TW		 1594 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
1595 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 1596 chan_info->ch_num = (u8) channel;
1597
1598 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1599 channel, s, ch_i1, ch_i2);
1600
1601 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1602 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 1603 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 1604 measurements[c][m]);
073d3f5f 1605 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 1606 measurements[c][m]);
1607 omeas = &(chan_info->measurements[c][m]);
1608
1609 omeas->actual_pow =
1610 (u8) iwl4965_interpolate_value(channel, ch_i1,
1611 m1->actual_pow,
1612 ch_i2,
1613 m2->actual_pow);
1614 omeas->gain_idx =
1615 (u8) iwl4965_interpolate_value(channel, ch_i1,
1616 m1->gain_idx, ch_i2,
1617 m2->gain_idx);
1618 omeas->temperature =
1619 (u8) iwl4965_interpolate_value(channel, ch_i1,
1620 m1->temperature,
1621 ch_i2,
1622 m2->temperature);
1623 omeas->pa_det =
1624 (s8) iwl4965_interpolate_value(channel, ch_i1,
1625 m1->pa_det, ch_i2,
1626 m2->pa_det);
1627
1628 IWL_DEBUG_TXPOWER
1629 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1630 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1631 IWL_DEBUG_TXPOWER
1632 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1633 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1634 IWL_DEBUG_TXPOWER
1635 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1636 m1->pa_det, m2->pa_det, omeas->pa_det);
1637 IWL_DEBUG_TXPOWER
1638 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1639 m1->temperature, m2->temperature,
1640 omeas->temperature);
1641 }
1642 }
1643
1644 return 0;
1645}
1646
1647/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1648 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1649static s32 back_off_table[] = {
1650 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1651 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1652 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1653 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1654 10 /* CCK */
1655};
1656
1657/* Thermal compensation values for txpower for various frequency ranges ...
1658 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1659static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1660 s32 degrees_per_05db_a;
1661 s32 degrees_per_05db_a_denom;
1662} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1663 {9, 2}, /* group 0 5.2, ch 34-43 */
1664 {4, 1}, /* group 1 5.2, ch 44-70 */
1665 {4, 1}, /* group 2 5.2, ch 71-124 */
1666 {4, 1}, /* group 3 5.2, ch 125-200 */
1667 {3, 1} /* group 4 2.4, ch all */
1668};
1669
1670static s32 get_min_power_index(s32 rate_power_index, u32 band)
1671{
1672 if (!band) {
1673 if ((rate_power_index & 7) <= 4)
1674 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1675 }
1676 return MIN_TX_GAIN_INDEX;
1677}
1678
1679struct gain_entry {
1680 u8 dsp;
1681 u8 radio;
1682};
1683
1684static const struct gain_entry gain_table[2][108] = {
1685 /* 5.2GHz power gain index table */
1686 {
1687 {123, 0x3F}, /* highest txpower */
1688 {117, 0x3F},
1689 {110, 0x3F},
1690 {104, 0x3F},
1691 {98, 0x3F},
1692 {110, 0x3E},
1693 {104, 0x3E},
1694 {98, 0x3E},
1695 {110, 0x3D},
1696 {104, 0x3D},
1697 {98, 0x3D},
1698 {110, 0x3C},
1699 {104, 0x3C},
1700 {98, 0x3C},
1701 {110, 0x3B},
1702 {104, 0x3B},
1703 {98, 0x3B},
1704 {110, 0x3A},
1705 {104, 0x3A},
1706 {98, 0x3A},
1707 {110, 0x39},
1708 {104, 0x39},
1709 {98, 0x39},
1710 {110, 0x38},
1711 {104, 0x38},
1712 {98, 0x38},
1713 {110, 0x37},
1714 {104, 0x37},
1715 {98, 0x37},
1716 {110, 0x36},
1717 {104, 0x36},
1718 {98, 0x36},
1719 {110, 0x35},
1720 {104, 0x35},
1721 {98, 0x35},
1722 {110, 0x34},
1723 {104, 0x34},
1724 {98, 0x34},
1725 {110, 0x33},
1726 {104, 0x33},
1727 {98, 0x33},
1728 {110, 0x32},
1729 {104, 0x32},
1730 {98, 0x32},
1731 {110, 0x31},
1732 {104, 0x31},
1733 {98, 0x31},
1734 {110, 0x30},
1735 {104, 0x30},
1736 {98, 0x30},
1737 {110, 0x25},
1738 {104, 0x25},
1739 {98, 0x25},
1740 {110, 0x24},
1741 {104, 0x24},
1742 {98, 0x24},
1743 {110, 0x23},
1744 {104, 0x23},
1745 {98, 0x23},
1746 {110, 0x22},
1747 {104, 0x18},
1748 {98, 0x18},
1749 {110, 0x17},
1750 {104, 0x17},
1751 {98, 0x17},
1752 {110, 0x16},
1753 {104, 0x16},
1754 {98, 0x16},
1755 {110, 0x15},
1756 {104, 0x15},
1757 {98, 0x15},
1758 {110, 0x14},
1759 {104, 0x14},
1760 {98, 0x14},
1761 {110, 0x13},
1762 {104, 0x13},
1763 {98, 0x13},
1764 {110, 0x12},
1765 {104, 0x08},
1766 {98, 0x08},
1767 {110, 0x07},
1768 {104, 0x07},
1769 {98, 0x07},
1770 {110, 0x06},
1771 {104, 0x06},
1772 {98, 0x06},
1773 {110, 0x05},
1774 {104, 0x05},
1775 {98, 0x05},
1776 {110, 0x04},
1777 {104, 0x04},
1778 {98, 0x04},
1779 {110, 0x03},
1780 {104, 0x03},
1781 {98, 0x03},
1782 {110, 0x02},
1783 {104, 0x02},
1784 {98, 0x02},
1785 {110, 0x01},
1786 {104, 0x01},
1787 {98, 0x01},
1788 {110, 0x00},
1789 {104, 0x00},
1790 {98, 0x00},
1791 {93, 0x00},
1792 {88, 0x00},
1793 {83, 0x00},
1794 {78, 0x00},
1795 },
1796 /* 2.4GHz power gain index table */
1797 {
1798 {110, 0x3f}, /* highest txpower */
1799 {104, 0x3f},
1800 {98, 0x3f},
1801 {110, 0x3e},
1802 {104, 0x3e},
1803 {98, 0x3e},
1804 {110, 0x3d},
1805 {104, 0x3d},
1806 {98, 0x3d},
1807 {110, 0x3c},
1808 {104, 0x3c},
1809 {98, 0x3c},
1810 {110, 0x3b},
1811 {104, 0x3b},
1812 {98, 0x3b},
1813 {110, 0x3a},
1814 {104, 0x3a},
1815 {98, 0x3a},
1816 {110, 0x39},
1817 {104, 0x39},
1818 {98, 0x39},
1819 {110, 0x38},
1820 {104, 0x38},
1821 {98, 0x38},
1822 {110, 0x37},
1823 {104, 0x37},
1824 {98, 0x37},
1825 {110, 0x36},
1826 {104, 0x36},
1827 {98, 0x36},
1828 {110, 0x35},
1829 {104, 0x35},
1830 {98, 0x35},
1831 {110, 0x34},
1832 {104, 0x34},
1833 {98, 0x34},
1834 {110, 0x33},
1835 {104, 0x33},
1836 {98, 0x33},
1837 {110, 0x32},
1838 {104, 0x32},
1839 {98, 0x32},
1840 {110, 0x31},
1841 {104, 0x31},
1842 {98, 0x31},
1843 {110, 0x30},
1844 {104, 0x30},
1845 {98, 0x30},
1846 {110, 0x6},
1847 {104, 0x6},
1848 {98, 0x6},
1849 {110, 0x5},
1850 {104, 0x5},
1851 {98, 0x5},
1852 {110, 0x4},
1853 {104, 0x4},
1854 {98, 0x4},
1855 {110, 0x3},
1856 {104, 0x3},
1857 {98, 0x3},
1858 {110, 0x2},
1859 {104, 0x2},
1860 {98, 0x2},
1861 {110, 0x1},
1862 {104, 0x1},
1863 {98, 0x1},
1864 {110, 0x0},
1865 {104, 0x0},
1866 {98, 0x0},
1867 {97, 0},
1868 {96, 0},
1869 {95, 0},
1870 {94, 0},
1871 {93, 0},
1872 {92, 0},
1873 {91, 0},
1874 {90, 0},
1875 {89, 0},
1876 {88, 0},
1877 {87, 0},
1878 {86, 0},
1879 {85, 0},
1880 {84, 0},
1881 {83, 0},
1882 {82, 0},
1883 {81, 0},
1884 {80, 0},
1885 {79, 0},
1886 {78, 0},
1887 {77, 0},
1888 {76, 0},
1889 {75, 0},
1890 {74, 0},
1891 {73, 0},
1892 {72, 0},
1893 {71, 0},
1894 {70, 0},
1895 {69, 0},
1896 {68, 0},
1897 {67, 0},
1898 {66, 0},
1899 {65, 0},
1900 {64, 0},
1901 {63, 0},
1902 {62, 0},
1903 {61, 0},
1904 {60, 0},
1905 {59, 0},
1906 }
1907};
1908
c79dd5b5 1909static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1910 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1911 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1912{
1913 u8 saturation_power;
1914 s32 target_power;
1915 s32 user_target_power;
1916 s32 power_limit;
1917 s32 current_temp;
1918 s32 reg_limit;
1919 s32 current_regulatory;
1920 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1921 int i;
1922 int c;
bf85ea4f 1923 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1924 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1925 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1926 s16 voltage;
1927 s32 init_voltage;
1928 s32 voltage_compensation;
1929 s32 degrees_per_05db_num;
1930 s32 degrees_per_05db_denom;
1931 s32 factory_temp;
1932 s32 temperature_comp[2];
1933 s32 factory_gain_index[2];
1934 s32 factory_actual_pwr[2];
1935 s32 power_index;
1936
1937 /* Sanity check requested level (dBm) */
1938 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1939 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1940 priv->user_txpower_limit);
1941 return -EINVAL;
1942 }
1943 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1944 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1945 priv->user_txpower_limit);
1946 return -EINVAL;
1947 }
1948
1949 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1950 * are used for indexing into txpower table) */
1951 user_target_power = 2 * priv->user_txpower_limit;
1952
1953 /* Get current (RXON) channel, band, width */
1954 ch_info =
8318d78a 1955 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
b481de9c
ZY		 1956
1957 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1958 is_fat);
1959
1960 if (!ch_info)
1961 return -EINVAL;
1962
1963 /* get txatten group, used to select 1) thermal txpower adjustment
1964 * and 2) mimo txpower balance between Tx chains. */
1965 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1966 if (txatten_grp < 0)
1967 return -EINVAL;
1968
1969 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1970 channel, txatten_grp);
1971
1972 if (is_fat) {
1973 if (ctrl_chan_high)
1974 channel -= 2;
1975 else
1976 channel += 2;
1977 }
1978
1979 /* hardware txpower limits ...
1980 * saturation (clipping distortion) txpowers are in half-dBm */
1981 if (band)
073d3f5f 1982 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1983 else
073d3f5f 1984 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1985
1986 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1987 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1988 if (band)
1989 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1990 else
1991 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1992 }
1993
1994 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1995 * max_power_avg values are in dBm, convert * 2 */
1996 if (is_fat)
1997 reg_limit = ch_info->fat_max_power_avg * 2;
1998 else
1999 reg_limit = ch_info->max_power_avg * 2;
2000
2001 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2002 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2003 if (band)
2004 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2005 else
2006 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2007 }
2008
2009 /* Interpolate txpower calibration values for this channel,
2010 * based on factory calibration tests on spaced channels. */
2011 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2012
2013 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 2014 voltage = priv->calib_info->voltage;
b481de9c
ZY		 2015 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2016 voltage_compensation =
2017 iwl4965_get_voltage_compensation(voltage, init_voltage);
2018
2019 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2020 init_voltage,
2021 voltage, voltage_compensation);
2022
2023 /* get current temperature (Celsius) */
2024 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2025 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2026 current_temp = KELVIN_TO_CELSIUS(current_temp);
2027
2028 /* select thermal txpower adjustment params, based on channel group
2029 * (same frequency group used for mimo txatten adjustment) */
2030 degrees_per_05db_num =
2031 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2032 degrees_per_05db_denom =
2033 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2034
2035 /* get per-chain txpower values from factory measurements */
2036 for (c = 0; c < 2; c++) {
2037 measurement = &ch_eeprom_info.measurements[c][1];
2038
2039 /* txgain adjustment (in half-dB steps) based on difference
2040 * between factory and current temperature */
2041 factory_temp = measurement->temperature;
2042 iwl4965_math_div_round((current_temp - factory_temp) *
2043 degrees_per_05db_denom,
2044 degrees_per_05db_num,
2045 &temperature_comp[c]);
2046
2047 factory_gain_index[c] = measurement->gain_idx;
2048 factory_actual_pwr[c] = measurement->actual_pow;
2049
2050 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2051 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2052 "curr tmp %d, comp %d steps\n",
2053 factory_temp, current_temp,
2054 temperature_comp[c]);
2055
2056 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2057 factory_gain_index[c],
2058 factory_actual_pwr[c]);
2059 }
2060
2061 /* for each of 33 bit-rates (including 1 for CCK) */
2062 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2063 u8 is_mimo_rate;
bb8c093b 2064 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 2065
2066 /* for mimo, reduce each chain's txpower by half
2067 * (3dB, 6 steps), so total output power is regulatory
2068 * compliant. */
2069 if (i & 0x8) {
2070 current_regulatory = reg_limit -
2071 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2072 is_mimo_rate = 1;
2073 } else {
2074 current_regulatory = reg_limit;
2075 is_mimo_rate = 0;
2076 }
2077
2078 /* find txpower limit, either hardware or regulatory */
2079 power_limit = saturation_power - back_off_table[i];
2080 if (power_limit > current_regulatory)
2081 power_limit = current_regulatory;
2082
2083 /* reduce user's txpower request if necessary
2084 * for this rate on this channel */
2085 target_power = user_target_power;
2086 if (target_power > power_limit)
2087 target_power = power_limit;
2088
2089 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2090 i, saturation_power - back_off_table[i],
2091 current_regulatory, user_target_power,
2092 target_power);
2093
2094 /* for each of 2 Tx chains (radio transmitters) */
2095 for (c = 0; c < 2; c++) {
2096 s32 atten_value;
2097
2098 if (is_mimo_rate)
2099 atten_value =
2100 (s32)le32_to_cpu(priv->card_alive_init.
2101 tx_atten[txatten_grp][c]);
2102 else
2103 atten_value = 0;
2104
2105 /* calculate index; higher index means lower txpower */
2106 power_index = (u8) (factory_gain_index[c] -
2107 (target_power -
2108 factory_actual_pwr[c]) -
2109 temperature_comp[c] -
2110 voltage_compensation +
2111 atten_value);
2112
2113/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2114 power_index); */
2115
2116 if (power_index < get_min_power_index(i, band))
2117 power_index = get_min_power_index(i, band);
2118
2119 /* adjust 5 GHz index to support negative indexes */
2120 if (!band)
2121 power_index += 9;
2122
2123 /* CCK, rate 32, reduce txpower for CCK */
2124 if (i == POWER_TABLE_CCK_ENTRY)
2125 power_index +=
2126 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2127
2128 /* stay within the table! */
2129 if (power_index > 107) {
2130 IWL_WARNING("txpower index %d > 107\n",
2131 power_index);
2132 power_index = 107;
2133 }
2134 if (power_index < 0) {
2135 IWL_WARNING("txpower index %d < 0\n",
2136 power_index);
2137 power_index = 0;
2138 }
2139
2140 /* fill txpower command for this rate/chain */
2141 tx_power.s.radio_tx_gain[c] =
2142 gain_table[band][power_index].radio;
2143 tx_power.s.dsp_predis_atten[c] =
2144 gain_table[band][power_index].dsp;
2145
2146 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2147 "gain 0x%02x dsp %d\n",
2148 c, atten_value, power_index,
2149 tx_power.s.radio_tx_gain[c],
2150 tx_power.s.dsp_predis_atten[c]);
2151 }/* for each chain */
2152
2153 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2154
2155 }/* for each rate */
2156
2157 return 0;
2158}
2159
2160/**
bb8c093b 2161 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
b481de9c
ZY		 2162 *
2163 * Uses the active RXON for channel, band, and characteristics (fat, high)
2164 * The power limit is taken from priv->user_txpower_limit.
2165 */
c79dd5b5 2166int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 2167{
bb8c093b 2168 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 2169 int ret;
b481de9c
ZY		 2170 u8 band = 0;
2171 u8 is_fat = 0;
2172 u8 ctrl_chan_high = 0;
2173
2174 if (test_bit(STATUS_SCANNING, &priv->status)) {
2175 /* If this gets hit a lot, switch it to a BUG() and catch
2176 * the stack trace to find out who is calling this during
2177 * a scan. */
2178 IWL_WARNING("TX Power requested while scanning!\n");
2179 return -EAGAIN;
2180 }
2181
8318d78a 2182 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 2183
2184 is_fat = is_fat_channel(priv->active_rxon.flags);
2185
2186 if (is_fat &&
2187 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2188 ctrl_chan_high = 1;
2189
2190 cmd.band = band;
2191 cmd.channel = priv->active_rxon.channel;
2192
857485c0 2193 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 2194 le16_to_cpu(priv->active_rxon.channel),
2195 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 2196 if (ret)
2197 goto out;
b481de9c 2198
857485c0
TW		 2199 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2200
2201out:
2202 return ret;
b481de9c
ZY		 2203}
2204
7e8c519e
TW		 2205static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2206{
2207 int ret = 0;
2208 struct iwl4965_rxon_assoc_cmd rxon_assoc;
2209 const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2210 const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2211
2212 if ((rxon1->flags == rxon2->flags) &&
2213 (rxon1->filter_flags == rxon2->filter_flags) &&
2214 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2215 (rxon1->ofdm_ht_single_stream_basic_rates ==
2216 rxon2->ofdm_ht_single_stream_basic_rates) &&
2217 (rxon1->ofdm_ht_dual_stream_basic_rates ==
2218 rxon2->ofdm_ht_dual_stream_basic_rates) &&
2219 (rxon1->rx_chain == rxon2->rx_chain) &&
2220 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2221 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
2222 return 0;
2223 }
2224
2225 rxon_assoc.flags = priv->staging_rxon.flags;
2226 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2227 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2228 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2229 rxon_assoc.reserved = 0;
2230 rxon_assoc.ofdm_ht_single_stream_basic_rates =
2231 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2232 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2233 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2234 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2235
2236 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2237 sizeof(rxon_assoc), &rxon_assoc, NULL);
2238 if (ret)
2239 return ret;
2240
2241 return ret;
2242}
2243
2244
c79dd5b5 2245int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2246{
2247 int rc;
2248 u8 band = 0;
2249 u8 is_fat = 0;
2250 u8 ctrl_chan_high = 0;
bb8c093b 2251 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 2252 const struct iwl_channel_info *ch_info;
b481de9c 2253
8318d78a 2254 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 2255
8622e705 2256 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 2257
2258 is_fat = is_fat_channel(priv->staging_rxon.flags);
2259
2260 if (is_fat &&
2261 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2262 ctrl_chan_high = 1;
2263
2264 cmd.band = band;
2265 cmd.expect_beacon = 0;
2266 cmd.channel = cpu_to_le16(channel);
2267 cmd.rxon_flags = priv->active_rxon.flags;
2268 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2269 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2270 if (ch_info)
2271 cmd.expect_beacon = is_channel_radar(ch_info);
2272 else
2273 cmd.expect_beacon = 1;
2274
2275 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2276 ctrl_chan_high, &cmd.tx_power);
2277 if (rc) {
2278 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2279 return rc;
2280 }
2281
857485c0 2282 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 2283 return rc;
2284}
2285
2286#define RTS_HCCA_RETRY_LIMIT 3
2287#define RTS_DFAULT_RETRY_LIMIT 60
2288
c79dd5b5 2289void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
857485c0 2290 struct iwl_cmd *cmd,
b481de9c
ZY		 2291 struct ieee80211_tx_control *ctrl,
2292 struct ieee80211_hdr *hdr, int sta_id,
2293 int is_hcca)
2294{
87e4f7df 2295 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
b481de9c
ZY		 2296 u8 rts_retry_limit = 0;
2297 u8 data_retry_limit = 0;
b481de9c 2298 u16 fc = le16_to_cpu(hdr->frame_control);
87e4f7df
TW		 2299 u8 rate_plcp;
2300 u16 rate_flags = 0;
8318d78a 2301 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c 2302
87e4f7df 2303 rate_plcp = iwl4965_rates[rate_idx].plcp;
b481de9c
ZY		 2304
2305 rts_retry_limit = (is_hcca) ?
2306 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2307
87e4f7df
TW		 2308 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2309 rate_flags |= RATE_MCS_CCK_MSK;
2310
2311
b481de9c
ZY		 2312 if (ieee80211_is_probe_response(fc)) {
2313 data_retry_limit = 3;
2314 if (data_retry_limit < rts_retry_limit)
2315 rts_retry_limit = data_retry_limit;
2316 } else
2317 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2318
2319 if (priv->data_retry_limit != -1)
2320 data_retry_limit = priv->data_retry_limit;
2321
87e4f7df
TW		 2322
2323 if (ieee80211_is_data(fc)) {
2324 tx->initial_rate_index = 0;
2325 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2326 } else {
b481de9c
ZY		 2327 switch (fc & IEEE80211_FCTL_STYPE) {
2328 case IEEE80211_STYPE_AUTH:
2329 case IEEE80211_STYPE_DEAUTH:
2330 case IEEE80211_STYPE_ASSOC_REQ:
2331 case IEEE80211_STYPE_REASSOC_REQ:
87e4f7df
TW		 2332 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2333 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2334 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
b481de9c
ZY		 2335 }
2336 break;
2337 default:
2338 break;
2339 }
87e4f7df
TW		 2340
2341 /* Alternate between antenna A and B for successive frames */
2342 if (priv->use_ant_b_for_management_frame) {
2343 priv->use_ant_b_for_management_frame = 0;
2344 rate_flags |= RATE_MCS_ANT_B_MSK;
2345 } else {
2346 priv->use_ant_b_for_management_frame = 1;
2347 rate_flags |= RATE_MCS_ANT_A_MSK;
2348 }
b481de9c
ZY		 2349 }
2350
87e4f7df
TW		 2351 tx->rts_retry_limit = rts_retry_limit;
2352 tx->data_retry_limit = data_retry_limit;
2353 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
b481de9c
ZY		 2354}
2355
c79dd5b5 2356int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2357{
059ff826
TW		 2358 struct iwl4965_shared *s = priv->shared_virt;
2359 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 2360}
2361
c79dd5b5 2362int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 2363{
2364 return priv->temperature;
2365}
2366
c79dd5b5 2367unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2368 struct iwl4965_frame *frame, u8 rate)
b481de9c 2369{
bb8c093b 2370 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2371 unsigned int frame_size;
2372
2373 tx_beacon_cmd = &frame->u.beacon;
2374 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2375
5425e490 2376 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2377 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2378
bb8c093b 2379 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 2380 tx_beacon_cmd->frame,
bb8c093b 2381 iwl4965_broadcast_addr,
b481de9c
ZY		 2382 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2383
2384 BUG_ON(frame_size > MAX_MPDU_SIZE);
2385 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2386
2387 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2388 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2389 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 2390 else
2391 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 2392 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 2393
2394 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2395 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2396 return (sizeof(*tx_beacon_cmd) + frame_size);
2397}
2398
8b6eaea8
CB		 2399/*
2400 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2401 * given Tx queue, and enable the DMA channel used for that queue.
2402 *
2403 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2404 * channels supported in hardware.
2405 */
c79dd5b5 2406int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c
ZY		 2407{
2408 int rc;
2409 unsigned long flags;
2410 int txq_id = txq->q.id;
2411
2412 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 2413 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2414 if (rc) {
2415 spin_unlock_irqrestore(&priv->lock, flags);
2416 return rc;
2417 }
2418
8b6eaea8 2419 /* Circular buffer (TFD queue in DRAM) physical base address */
3395f6e9 2420 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
b481de9c 2421 txq->q.dma_addr >> 8);
8b6eaea8
CB		 2422
2423 /* Enable DMA channel, using same id as for TFD queue */
3395f6e9 2424 iwl_write_direct32(
b481de9c
ZY		 2425 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2426 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2427 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
3395f6e9 2428 iwl_release_nic_access(priv);
b481de9c
ZY		 2429 spin_unlock_irqrestore(&priv->lock, flags);
2430
2431 return 0;
2432}
2433
c79dd5b5 2434int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 2435 dma_addr_t addr, u16 len)
2436{
2437 int index, is_odd;
bb8c093b 2438 struct iwl4965_tfd_frame *tfd = ptr;
b481de9c
ZY		 2439 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2440
8b6eaea8 2441 /* Each TFD can point to a maximum 20 Tx buffers */
b481de9c
ZY		 2442 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2443 IWL_ERROR("Error can not send more than %d chunks\n",
2444 MAX_NUM_OF_TBS);
2445 return -EINVAL;
2446 }
2447
2448 index = num_tbs / 2;
2449 is_odd = num_tbs & 0x1;
2450
2451 if (!is_odd) {
2452 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2453 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
6a218f6f 2454 iwl_get_dma_hi_address(addr));
b481de9c
ZY		 2455 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2456 } else {
2457 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2458 (u32) (addr & 0xffff));
2459 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2460 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2461 }
2462
2463 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2464
2465 return 0;
2466}
2467
c79dd5b5 2468static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
b481de9c 2469{
073d3f5f 2470 u16 hw_version = iwl_eeprom_query16(priv, EEPROM_4965_BOARD_REVISION);
b481de9c
ZY		 2471
2472 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2473 ((hw_version >> 8) & 0x0F),
2474 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2475
2476 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
073d3f5f 2477 &priv->eeprom[EEPROM_4965_BOARD_PBA]);
b481de9c
ZY		 2478}
2479
2480#define IWL_TX_CRC_SIZE 4
2481#define IWL_TX_DELIMITER_SIZE 4
2482
8b6eaea8 2483/**
e2a722eb 2484 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 2485 */
e2a722eb
TW		 2486static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2487 struct iwl4965_tx_queue *txq,
2488 u16 byte_cnt)
b481de9c
ZY		 2489{
2490 int len;
2491 int txq_id = txq->q.id;
059ff826 2492 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 2493
b481de9c
ZY		 2494 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2495
8b6eaea8 2496 /* Set up byte count within first 256 entries */
b481de9c 2497 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 2498 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 2499
8b6eaea8 2500 /* If within first 64 entries, duplicate at end */
fc4b6853 2501 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
b481de9c 2502 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 2503 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 2504 byte_cnt, len);
b481de9c
ZY		 2505}
2506
8b6eaea8
CB		 2507/**
2508 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2509 *
2510 * Selects how many and which Rx receivers/antennas/chains to use.
2511 * This should not be used for scan command ... it puts data in wrong place.
2512 */
c79dd5b5 2513void iwl4965_set_rxon_chain(struct iwl_priv *priv)
b481de9c
ZY		 2514{
2515 u8 is_single = is_single_stream(priv);
2516 u8 idle_state, rx_state;
2517
2518 priv->staging_rxon.rx_chain = 0;
2519 rx_state = idle_state = 3;
2520
2521 /* Tell uCode which antennas are actually connected.
2522 * Before first association, we assume all antennas are connected.
f0832f13 2523 * Just after first association, iwl_chain_noise_calibration()
b481de9c
ZY		 2524 * checks which antennas actually *are* connected. */
2525 priv->staging_rxon.rx_chain |=
2526 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
2527
2528 /* How many receivers should we use? */
2529 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2530 priv->staging_rxon.rx_chain |=
2531 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2532 priv->staging_rxon.rx_chain |=
2533 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2534
2535 if (!is_single && (rx_state >= 2) &&
2536 !test_bit(STATUS_POWER_PMI, &priv->status))
2537 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2538 else
2539 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2540
2541 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2542}
2543
b481de9c
ZY		 2544/**
2545 * sign_extend - Sign extend a value using specified bit as sign-bit
2546 *
2547 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2548 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2549 *
2550 * @param oper value to sign extend
2551 * @param index 0 based bit index (0<=index<32) to sign bit
2552 */
2553static s32 sign_extend(u32 oper, int index)
2554{
2555 u8 shift = 31 - index;
2556
2557 return (s32)(oper << shift) >> shift;
2558}
2559
2560/**
2561 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2562 * @statistics: Provides the temperature reading from the uCode
2563 *
2564 * A return of <0 indicates bogus data in the statistics
2565 */
c79dd5b5 2566int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 2567{
2568 s32 temperature;
2569 s32 vt;
2570 s32 R1, R2, R3;
2571 u32 R4;
2572
2573 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2574 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2575 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2576 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2577 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2578 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2579 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2580 } else {
2581 IWL_DEBUG_TEMP("Running temperature calibration\n");
2582 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2583 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2584 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2585 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2586 }
2587
2588 /*
8b6eaea8 2589 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 2590 *
2591 * NOTE If we haven't received a statistics notification yet
2592 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 2593 * "initialize" ALIVE response.
2594 */
b481de9c
ZY		 2595 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2596 vt = sign_extend(R4, 23);
2597 else
2598 vt = sign_extend(
2599 le32_to_cpu(priv->statistics.general.temperature), 23);
2600
2601 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2602 R1, R2, R3, vt);
2603
2604 if (R3 == R1) {
2605 IWL_ERROR("Calibration conflict R1 == R3\n");
2606 return -1;
2607 }
2608
2609 /* Calculate temperature in degrees Kelvin, adjust by 97%.
2610 * Add offset to center the adjustment around 0 degrees Centigrade. */
2611 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2612 temperature /= (R3 - R1);
2613 temperature = (temperature * 97) / 100 +
2614 TEMPERATURE_CALIB_KELVIN_OFFSET;
2615
2616 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2617 KELVIN_TO_CELSIUS(temperature));
2618
2619 return temperature;
2620}
2621
2622/* Adjust Txpower only if temperature variance is greater than threshold. */
2623#define IWL_TEMPERATURE_THRESHOLD 3
2624
2625/**
2626 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2627 *
2628 * If the temperature changed has changed sufficiently, then a recalibration
2629 * is needed.
2630 *
2631 * Assumes caller will replace priv->last_temperature once calibration
2632 * executed.
2633 */
c79dd5b5 2634static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 2635{
2636 int temp_diff;
2637
2638 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2639 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2640 return 0;
2641 }
2642
2643 temp_diff = priv->temperature - priv->last_temperature;
2644
2645 /* get absolute value */
2646 if (temp_diff < 0) {
2647 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2648 temp_diff = -temp_diff;
2649 } else if (temp_diff == 0)
2650 IWL_DEBUG_POWER("Same temp, \n");
2651 else
2652 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2653
2654 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2655 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2656 return 0;
2657 }
2658
2659 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2660
2661 return 1;
2662}
2663
2664/* Calculate noise level, based on measurements during network silence just
2665 * before arriving beacon. This measurement can be done only if we know
2666 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 2667static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 2668{
2669 struct statistics_rx_non_phy *rx_info
2670 = &(priv->statistics.rx.general);
2671 int num_active_rx = 0;
2672 int total_silence = 0;
2673 int bcn_silence_a =
2674 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2675 int bcn_silence_b =
2676 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2677 int bcn_silence_c =
2678 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2679
2680 if (bcn_silence_a) {
2681 total_silence += bcn_silence_a;
2682 num_active_rx++;
2683 }
2684 if (bcn_silence_b) {
2685 total_silence += bcn_silence_b;
2686 num_active_rx++;
2687 }
2688 if (bcn_silence_c) {
2689 total_silence += bcn_silence_c;
2690 num_active_rx++;
2691 }
2692
2693 /* Average among active antennas */
2694 if (num_active_rx)
2695 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2696 else
2697 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2698
2699 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2700 bcn_silence_a, bcn_silence_b, bcn_silence_c,
2701 priv->last_rx_noise);
2702}
2703
c79dd5b5 2704void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 2705{
bb8c093b 2706 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 2707 int change;
2708 s32 temp;
2709
2710 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2711 (int)sizeof(priv->statistics), pkt->len);
2712
2713 change = ((priv->statistics.general.temperature !=
2714 pkt->u.stats.general.temperature) ||
2715 ((priv->statistics.flag &
2716 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2717 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2718
2719 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2720
2721 set_bit(STATUS_STATISTICS, &priv->status);
2722
2723 /* Reschedule the statistics timer to occur in
2724 * REG_RECALIB_PERIOD seconds to ensure we get a
2725 * thermal update even if the uCode doesn't give
2726 * us one */
2727 mod_timer(&priv->statistics_periodic, jiffies +
2728 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2729
2730 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2731 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2732 iwl4965_rx_calc_noise(priv);
f0832f13 2733#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 2734 queue_work(priv->workqueue, &priv->sensitivity_work);
2735#endif
2736 }
2737
ab53d8af
MA		 2738 iwl_leds_background(priv);
2739
b481de9c
ZY		 2740 /* If the hardware hasn't reported a change in
2741 * temperature then don't bother computing a
2742 * calibrated temperature value */
2743 if (!change)
2744 return;
2745
2746 temp = iwl4965_get_temperature(priv);
2747 if (temp < 0)
2748 return;
2749
2750 if (priv->temperature != temp) {
2751 if (priv->temperature)
2752 IWL_DEBUG_TEMP("Temperature changed "
2753 "from %dC to %dC\n",
2754 KELVIN_TO_CELSIUS(priv->temperature),
2755 KELVIN_TO_CELSIUS(temp));
2756 else
2757 IWL_DEBUG_TEMP("Temperature "
2758 "initialized to %dC\n",
2759 KELVIN_TO_CELSIUS(temp));
2760 }
2761
2762 priv->temperature = temp;
2763 set_bit(STATUS_TEMPERATURE, &priv->status);
2764
2765 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2766 iwl4965_is_temp_calib_needed(priv))
2767 queue_work(priv->workqueue, &priv->txpower_work);
2768}
2769
c79dd5b5 2770static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 2771 struct sk_buff *skb,
2772 struct iwl4965_rx_phy_res *rx_start,
2773 struct ieee80211_rx_status *stats,
2774 u32 ampdu_status)
2775{
2776 s8 signal = stats->ssi;
2777 s8 noise = 0;
8318d78a 2778 int rate = stats->rate_idx;
12342c47 2779 u64 tsf = stats->mactime;
a0b484fe 2780 __le16 antenna;
12342c47
ZY		 2781 __le16 phy_flags_hw = rx_start->phy_flags;
2782 struct iwl4965_rt_rx_hdr {
2783 struct ieee80211_radiotap_header rt_hdr;
2784 __le64 rt_tsf; /* TSF */
2785 u8 rt_flags; /* radiotap packet flags */
2786 u8 rt_rate; /* rate in 500kb/s */
2787 __le16 rt_channelMHz; /* channel in MHz */
2788 __le16 rt_chbitmask; /* channel bitfield */
2789 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
2790 s8 rt_dbmnoise;
2791 u8 rt_antenna; /* antenna number */
2792 } __attribute__ ((packed)) *iwl4965_rt;
2793
2794 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2795 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2796 if (net_ratelimit())
2797 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 2798 "radiotap head [%zd]\n",
12342c47
ZY		 2799 skb_headroom(skb), sizeof(*iwl4965_rt));
2800 return;
2801 }
2802
2803 /* put radiotap header in front of 802.11 header and data */
2804 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2805
2806 /* initialise radiotap header */
2807 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2808 iwl4965_rt->rt_hdr.it_pad = 0;
2809
2810 /* total header + data */
2811 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2812 &iwl4965_rt->rt_hdr.it_len);
2813
2814 /* Indicate all the fields we add to the radiotap header */
2815 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2816 (1 << IEEE80211_RADIOTAP_FLAGS) |
2817 (1 << IEEE80211_RADIOTAP_RATE) |
2818 (1 << IEEE80211_RADIOTAP_CHANNEL) |
2819 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2820 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2821 (1 << IEEE80211_RADIOTAP_ANTENNA)),
2822 &iwl4965_rt->rt_hdr.it_present);
2823
2824 /* Zero the flags, we'll add to them as we go */
2825 iwl4965_rt->rt_flags = 0;
2826
2827 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2828
2829 iwl4965_rt->rt_dbmsignal = signal;
2830 iwl4965_rt->rt_dbmnoise = noise;
2831
2832 /* Convert the channel frequency and set the flags */
2833 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2834 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2835 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2836 IEEE80211_CHAN_5GHZ),
2837 &iwl4965_rt->rt_chbitmask);
2838 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2839 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2840 IEEE80211_CHAN_2GHZ),
2841 &iwl4965_rt->rt_chbitmask);
2842 else /* 802.11g */
2843 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2844 IEEE80211_CHAN_2GHZ),
2845 &iwl4965_rt->rt_chbitmask);
2846
12342c47
ZY		 2847 if (rate == -1)
2848 iwl4965_rt->rt_rate = 0;
2849 else
2850 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2851
2852 /*
2853 * "antenna number"
2854 *
2855 * It seems that the antenna field in the phy flags value
2856 * is actually a bitfield. This is undefined by radiotap,
2857 * it wants an actual antenna number but I always get "7"
2858 * for most legacy frames I receive indicating that the
2859 * same frame was received on all three RX chains.
2860 *
2861 * I think this field should be removed in favour of a
2862 * new 802.11n radiotap field "RX chains" that is defined
2863 * as a bitmask.
2864 */
a0b484fe
JB		 2865 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2866 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 2867
2868 /* set the preamble flag if appropriate */
2869 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2870 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2871
2872 stats->flag |= RX_FLAG_RADIOTAP;
2873}
2874
19758bef
TW		 2875static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2876{
2877 /* 0 - mgmt, 1 - cnt, 2 - data */
2878 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2879 priv->rx_stats[idx].cnt++;
2880 priv->rx_stats[idx].bytes += len;
2881}
2882
3ec47732
EG		 2883/*
2884 * returns non-zero if packet should be dropped
2885 */
2886static int iwl4965_set_decrypted_flag(struct iwl_priv *priv,
2887 struct ieee80211_hdr *hdr,
2888 u32 decrypt_res,
2889 struct ieee80211_rx_status *stats)
2890{
2891 u16 fc = le16_to_cpu(hdr->frame_control);
2892
2893 if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2894 return 0;
2895
2896 if (!(fc & IEEE80211_FCTL_PROTECTED))
2897 return 0;
2898
2899 IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
2900 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2901 case RX_RES_STATUS_SEC_TYPE_TKIP:
2902 /* The uCode has got a bad phase 1 Key, pushes the packet.
2903 * Decryption will be done in SW. */
2904 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2905 RX_RES_STATUS_BAD_KEY_TTAK)
2906 break;
2907
2908 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2909 RX_RES_STATUS_BAD_ICV_MIC) {
2910 /* bad ICV, the packet is destroyed since the
2911 * decryption is inplace, drop it */
2912 IWL_DEBUG_RX("Packet destroyed\n");
2913 return -1;
2914 }
2915 case RX_RES_STATUS_SEC_TYPE_WEP:
2916 case RX_RES_STATUS_SEC_TYPE_CCMP:
2917 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2918 RX_RES_STATUS_DECRYPT_OK) {
2919 IWL_DEBUG_RX("hw decrypt successfully!!!\n");
2920 stats->flag |= RX_FLAG_DECRYPTED;
2921 }
2922 break;
2923
2924 default:
2925 break;
2926 }
2927 return 0;
2928}
2929
17e476b8
EG		 2930static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2931{
2932 u32 decrypt_out = 0;
2933
2934 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2935 RX_RES_STATUS_STATION_FOUND)
2936 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2937 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2938
2939 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2940
2941 /* packet was not encrypted */
2942 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2943 RX_RES_STATUS_SEC_TYPE_NONE)
2944 return decrypt_out;
2945
2946 /* packet was encrypted with unknown alg */
2947 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2948 RX_RES_STATUS_SEC_TYPE_ERR)
2949 return decrypt_out;
2950
2951 /* decryption was not done in HW */
2952 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2953 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2954 return decrypt_out;
2955
2956 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2957
2958 case RX_RES_STATUS_SEC_TYPE_CCMP:
2959 /* alg is CCM: check MIC only */
2960 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2961 /* Bad MIC */
2962 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2963 else
2964 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2965
2966 break;
2967
2968 case RX_RES_STATUS_SEC_TYPE_TKIP:
2969 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2970 /* Bad TTAK */
2971 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2972 break;
2973 }
2974 /* fall through if TTAK OK */
2975 default:
2976 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2977 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2978 else
2979 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2980 break;
2981 };
2982
2983 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
2984 decrypt_in, decrypt_out);
2985
2986 return decrypt_out;
2987}
2988
c79dd5b5 2989static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 2990 int include_phy,
bb8c093b 2991 struct iwl4965_rx_mem_buffer *rxb,
b481de9c
ZY		 2992 struct ieee80211_rx_status *stats)
2993{
bb8c093b 2994 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 2995 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2996 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2997 struct ieee80211_hdr *hdr;
2998 u16 len;
2999 __le32 *rx_end;
3000 unsigned int skblen;
3001 u32 ampdu_status;
17e476b8 3002 u32 ampdu_status_legacy;
b481de9c
ZY		 3003
3004 if (!include_phy && priv->last_phy_res[0])
3005 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3006
3007 if (!rx_start) {
3008 IWL_ERROR("MPDU frame without a PHY data\n");
3009 return;
3010 }
3011 if (include_phy) {
3012 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3013 rx_start->cfg_phy_cnt);
3014
3015 len = le16_to_cpu(rx_start->byte_count);
3016
3017 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3018 sizeof(struct iwl4965_rx_phy_res) +
3019 rx_start->cfg_phy_cnt + len);
3020
3021 } else {
3022 struct iwl4965_rx_mpdu_res_start *amsdu =
3023 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3024
3025 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3026 sizeof(struct iwl4965_rx_mpdu_res_start));
3027 len = le16_to_cpu(amsdu->byte_count);
3028 rx_start->byte_count = amsdu->byte_count;
3029 rx_end = (__le32 *) (((u8 *) hdr) + len);
3030 }
5425e490 3031 if (len > priv->hw_params.max_pkt_size || len < 16) {
12342c47 3032 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 3033 return;
3034 }
3035
3036 ampdu_status = le32_to_cpu(*rx_end);
3037 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3038
17e476b8
EG		 3039 if (!include_phy) {
3040 /* New status scheme, need to translate */
3041 ampdu_status_legacy = ampdu_status;
3042 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3043 }
3044
b481de9c
ZY		 3045 /* start from MAC */
3046 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3047 skb_put(rxb->skb, len); /* end where data ends */
3048
3049 /* We only process data packets if the interface is open */
3050 if (unlikely(!priv->is_open)) {
3051 IWL_DEBUG_DROP_LIMIT
3052 ("Dropping packet while interface is not open.\n");
3053 return;
3054 }
3055
b481de9c
ZY		 3056 stats->flag = 0;
3057 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3058
3ec47732 3059 /* in case of HW accelerated crypto and bad decryption, drop */
099b40b7 3060 if (!priv->hw_params.sw_crypto &&
3ec47732
EG		 3061 iwl4965_set_decrypted_flag(priv, hdr, ampdu_status, stats))
3062 return;
b481de9c 3063
12342c47
ZY		 3064 if (priv->add_radiotap)
3065 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3066
19758bef 3067 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 3068 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3069 priv->alloc_rxb_skb--;
3070 rxb->skb = NULL;
b481de9c
ZY		 3071}
3072
3073/* Calc max signal level (dBm) among 3 possible receivers */
3074static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3075{
3076 /* data from PHY/DSP regarding signal strength, etc.,
3077 * contents are always there, not configurable by host. */
3078 struct iwl4965_rx_non_cfg_phy *ncphy =
3079 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3080 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3081 >> IWL_AGC_DB_POS;
3082
3083 u32 valid_antennae =
3084 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3085 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3086 u8 max_rssi = 0;
3087 u32 i;
3088
3089 /* Find max rssi among 3 possible receivers.
3090 * These values are measured by the digital signal processor (DSP).
3091 * They should stay fairly constant even as the signal strength varies,
3092 * if the radio's automatic gain control (AGC) is working right.
3093 * AGC value (see below) will provide the "interesting" info. */
3094 for (i = 0; i < 3; i++)
3095 if (valid_antennae & (1 << i))
3096 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3097
3098 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3099 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3100 max_rssi, agc);
3101
3102 /* dBm = max_rssi dB - agc dB - constant.
3103 * Higher AGC (higher radio gain) means lower signal. */
3104 return (max_rssi - agc - IWL_RSSI_OFFSET);
3105}
3106
c8b0e6e1 3107#ifdef CONFIG_IWL4965_HT
b481de9c 3108
1ea87396
AK		 3109void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
3110 struct ieee80211_ht_info *ht_info,
78330fdd 3111 enum ieee80211_band band)
326eeee8
RR		 3112{
3113 ht_info->cap = 0;
3114 memset(ht_info->supp_mcs_set, 0, 16);
3115
3116 ht_info->ht_supported = 1;
3117
099b40b7 3118 if (priv->hw_params.fat_channel & BIT(band)) {
326eeee8
RR		 3119 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3120 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3121 ht_info->supp_mcs_set[4] = 0x01;
3122 }
3123 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3124 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3125 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3126 (IWL_MIMO_PS_NONE << 2));
1ea87396
AK		 3127
3128 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47 3129 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
326eeee8
RR		 3130
3131 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3132 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3133
3134 ht_info->supp_mcs_set[0] = 0xFF;
3135 ht_info->supp_mcs_set[1] = 0xFF;
3136}
c8b0e6e1 3137#endif /* CONFIG_IWL4965_HT */
b481de9c 3138
c79dd5b5 3139static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 3140{
3141 unsigned long flags;
3142
3143 spin_lock_irqsave(&priv->sta_lock, flags);
3144 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3145 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3146 priv->stations[sta_id].sta.sta.modify_mask = 0;
3147 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3148 spin_unlock_irqrestore(&priv->sta_lock, flags);
3149
bb8c093b 3150 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3151}
3152
c79dd5b5 3153static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 3154{
3155 /* FIXME: need locking over ps_status ??? */
947b13a7 3156 u8 sta_id = iwl_find_station(priv, addr);
b481de9c
ZY		 3157
3158 if (sta_id != IWL_INVALID_STATION) {
3159 u8 sta_awake = priv->stations[sta_id].
3160 ps_status == STA_PS_STATUS_WAKE;
3161
3162 if (sta_awake && ps_bit)
3163 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3164 else if (!sta_awake && !ps_bit) {
3165 iwl4965_sta_modify_ps_wake(priv, sta_id);
3166 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3167 }
3168 }
3169}
0a6857e7 3170#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 3171
3172/**
3173 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3174 *
3175 * You may hack this function to show different aspects of received frames,
3176 * including selective frame dumps.
3177 * group100 parameter selects whether to show 1 out of 100 good frames.
3178 *
3179 * TODO: This was originally written for 3945, need to audit for
3180 * proper operation with 4965.
3181 */
c79dd5b5 3182static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3183 struct iwl4965_rx_packet *pkt,
3184 struct ieee80211_hdr *header, int group100)
3185{
3186 u32 to_us;
3187 u32 print_summary = 0;
3188 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3189 u32 hundred = 0;
3190 u32 dataframe = 0;
3191 u16 fc;
3192 u16 seq_ctl;
3193 u16 channel;
3194 u16 phy_flags;
3195 int rate_sym;
3196 u16 length;
3197 u16 status;
3198 u16 bcn_tmr;
3199 u32 tsf_low;
3200 u64 tsf;
3201 u8 rssi;
3202 u8 agc;
3203 u16 sig_avg;
3204 u16 noise_diff;
3205 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3206 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3207 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3208 u8 *data = IWL_RX_DATA(pkt);
3209
0a6857e7 3210 if (likely(!(iwl_debug_level & IWL_DL_RX)))
17744ff6
TW		 3211 return;
3212
3213 /* MAC header */
3214 fc = le16_to_cpu(header->frame_control);
3215 seq_ctl = le16_to_cpu(header->seq_ctrl);
3216
3217 /* metadata */
3218 channel = le16_to_cpu(rx_hdr->channel);
3219 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3220 rate_sym = rx_hdr->rate;
3221 length = le16_to_cpu(rx_hdr->len);
3222
3223 /* end-of-frame status and timestamp */
3224 status = le32_to_cpu(rx_end->status);
3225 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3226 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3227 tsf = le64_to_cpu(rx_end->timestamp);
3228
3229 /* signal statistics */
3230 rssi = rx_stats->rssi;
3231 agc = rx_stats->agc;
3232 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3233 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3234
3235 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3236
3237 /* if data frame is to us and all is good,
3238 * (optionally) print summary for only 1 out of every 100 */
3239 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3240 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3241 dataframe = 1;
3242 if (!group100)
3243 print_summary = 1; /* print each frame */
3244 else if (priv->framecnt_to_us < 100) {
3245 priv->framecnt_to_us++;
3246 print_summary = 0;
3247 } else {
3248 priv->framecnt_to_us = 0;
3249 print_summary = 1;
3250 hundred = 1;
3251 }
3252 } else {
3253 /* print summary for all other frames */
3254 print_summary = 1;
3255 }
3256
3257 if (print_summary) {
3258 char *title;
3259 int rate_idx;
3260 u32 bitrate;
3261
3262 if (hundred)
3263 title = "100Frames";
3264 else if (fc & IEEE80211_FCTL_RETRY)
3265 title = "Retry";
3266 else if (ieee80211_is_assoc_response(fc))
3267 title = "AscRsp";
3268 else if (ieee80211_is_reassoc_response(fc))
3269 title = "RasRsp";
3270 else if (ieee80211_is_probe_response(fc)) {
3271 title = "PrbRsp";
3272 print_dump = 1; /* dump frame contents */
3273 } else if (ieee80211_is_beacon(fc)) {
3274 title = "Beacon";
3275 print_dump = 1; /* dump frame contents */
3276 } else if (ieee80211_is_atim(fc))
3277 title = "ATIM";
3278 else if (ieee80211_is_auth(fc))
3279 title = "Auth";
3280 else if (ieee80211_is_deauth(fc))
3281 title = "DeAuth";
3282 else if (ieee80211_is_disassoc(fc))
3283 title = "DisAssoc";
3284 else
3285 title = "Frame";
3286
3287 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3288 if (unlikely(rate_idx == -1))
3289 bitrate = 0;
3290 else
3291 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3292
3293 /* print frame summary.
3294 * MAC addresses show just the last byte (for brevity),
3295 * but you can hack it to show more, if you'd like to. */
3296 if (dataframe)
3297 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3298 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3299 title, fc, header->addr1[5],
3300 length, rssi, channel, bitrate);
3301 else {
3302 /* src/dst addresses assume managed mode */
3303 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3304 "src=0x%02x, rssi=%u, tim=%lu usec, "
3305 "phy=0x%02x, chnl=%d\n",
3306 title, fc, header->addr1[5],
3307 header->addr3[5], rssi,
3308 tsf_low - priv->scan_start_tsf,
3309 phy_flags, channel);
3310 }
3311 }
3312 if (print_dump)
0a6857e7 3313 iwl_print_hex_dump(IWL_DL_RX, data, length);
17744ff6
TW		 3314}
3315#else
c79dd5b5 3316static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3317 struct iwl4965_rx_packet *pkt,
3318 struct ieee80211_hdr *header,
3319 int group100)
3320{
3321}
3322#endif
3323
b481de9c 3324
7878a5a4 3325
857485c0 3326/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 3327 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
c79dd5b5 3328static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
bb8c093b 3329 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3330{
17744ff6
TW		 3331 struct ieee80211_hdr *header;
3332 struct ieee80211_rx_status rx_status;
bb8c093b 3333 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3334 /* Use phy data (Rx signal strength, etc.) contained within
3335 * this rx packet for legacy frames,
3336 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 3337 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 3338 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3339 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3340 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3341 __le32 *rx_end;
3342 unsigned int len = 0;
b481de9c 3343 u16 fc;
b481de9c
ZY		 3344 u8 network_packet;
3345
17744ff6 3346 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
dc92e497
TW		 3347 rx_status.freq =
3348 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
17744ff6
TW		 3349 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3350 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
dc92e497
TW		 3351 rx_status.rate_idx =
3352 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
17744ff6
TW		 3353 if (rx_status.band == IEEE80211_BAND_5GHZ)
3354 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3355
3356 rx_status.antenna = 0;
3357 rx_status.flag = 0;
3358
b481de9c 3359 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
dc92e497
TW		 3360 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3361 rx_start->cfg_phy_cnt);
b481de9c
ZY		 3362 return;
3363 }
17744ff6 3364
b481de9c
ZY		 3365 if (!include_phy) {
3366 if (priv->last_phy_res[0])
3367 rx_start = (struct iwl4965_rx_phy_res *)
3368 &priv->last_phy_res[1];
3369 else
3370 rx_start = NULL;
3371 }
3372
3373 if (!rx_start) {
3374 IWL_ERROR("MPDU frame without a PHY data\n");
3375 return;
3376 }
3377
3378 if (include_phy) {
3379 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3380 + rx_start->cfg_phy_cnt);
3381
3382 len = le16_to_cpu(rx_start->byte_count);
17744ff6 3383 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 3384 sizeof(struct iwl4965_rx_phy_res) + len);
3385 } else {
3386 struct iwl4965_rx_mpdu_res_start *amsdu =
3387 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3388
3389 header = (void *)(pkt->u.raw +
3390 sizeof(struct iwl4965_rx_mpdu_res_start));
3391 len = le16_to_cpu(amsdu->byte_count);
3392 rx_end = (__le32 *) (pkt->u.raw +
3393 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3394 }
3395
3396 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3397 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3398 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3399 le32_to_cpu(*rx_end));
3400 return;
3401 }
3402
3403 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3404
b481de9c 3405 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
17744ff6 3406 rx_status.ssi = iwl4965_calc_rssi(rx_start);
b481de9c
ZY		 3407
3408 /* Meaningful noise values are available only from beacon statistics,
3409 * which are gathered only when associated, and indicate noise
3410 * only for the associated network channel ...
3411 * Ignore these noise values while scanning (other channels) */
3109ece1 3412 if (iwl_is_associated(priv) &&
b481de9c 3413 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6
TW		 3414 rx_status.noise = priv->last_rx_noise;
3415 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3416 rx_status.noise);
b481de9c 3417 } else {
17744ff6
TW		 3418 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3419 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
b481de9c
ZY		 3420 }
3421
3422 /* Reset beacon noise level if not associated. */
3109ece1 3423 if (!iwl_is_associated(priv))
b481de9c
ZY		 3424 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3425
17744ff6
TW		 3426 /* Set "1" to report good data frames in groups of 100 */
3427 /* FIXME: need to optimze the call: */
3428 iwl4965_dbg_report_frame(priv, pkt, header, 1);
3429
3430 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3431 rx_status.ssi, rx_status.noise, rx_status.signal,
06501d29 3432 (unsigned long long)rx_status.mactime);
b481de9c 3433
bb8c093b 3434 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 3435 if (network_packet) {
17744ff6 3436 priv->last_rx_rssi = rx_status.ssi;
b481de9c
ZY		 3437 priv->last_beacon_time = priv->ucode_beacon_time;
3438 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3439 }
3440
3441 fc = le16_to_cpu(header->frame_control);
3442 switch (fc & IEEE80211_FCTL_FTYPE) {
3443 case IEEE80211_FTYPE_MGMT:
b481de9c
ZY		 3444 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3445 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3446 header->addr2);
17744ff6 3447 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 3448 break;
3449
3450 case IEEE80211_FTYPE_CTL:
9ab46173 3451#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 3452 switch (fc & IEEE80211_FCTL_STYPE) {
3453 case IEEE80211_STYPE_BACK_REQ:
3454 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3455 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 3456 rxb, &rx_status);
b481de9c
ZY		 3457 break;
3458 default:
3459 break;
3460 }
3461#endif
b481de9c
ZY		 3462 break;
3463
0795af57
JP		 3464 case IEEE80211_FTYPE_DATA: {
3465 DECLARE_MAC_BUF(mac1);
3466 DECLARE_MAC_BUF(mac2);
3467 DECLARE_MAC_BUF(mac3);
3468
b481de9c
ZY		 3469 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3470 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
3471 header->addr2);
3472
3473 if (unlikely(!network_packet))
3474 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 3475 "%s, %s, %s\n",
3476 print_mac(mac1, header->addr1),
3477 print_mac(mac2, header->addr2),
3478 print_mac(mac3, header->addr3));
bb8c093b 3479 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 3480 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3481 print_mac(mac1, header->addr1),
3482 print_mac(mac2, header->addr2),
3483 print_mac(mac3, header->addr3));
b481de9c
ZY		 3484 else
3485 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 3486 &rx_status);
b481de9c 3487 break;
0795af57 3488 }
b481de9c
ZY		 3489 default:
3490 break;
3491
3492 }
3493}
3494
3495/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3496 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
c79dd5b5 3497static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
bb8c093b 3498 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3499{
bb8c093b 3500 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3501 priv->last_phy_res[0] = 1;
3502 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3503 sizeof(struct iwl4965_rx_phy_res));
3504}
c79dd5b5 3505static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
bb8c093b 3506 struct iwl4965_rx_mem_buffer *rxb)
b481de9c
ZY		 3507
3508{
f0832f13 3509#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
bb8c093b
CH		 3510 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3511 struct iwl4965_missed_beacon_notif *missed_beacon;
b481de9c
ZY		 3512
3513 missed_beacon = &pkt->u.missed_beacon;
3514 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3515 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3516 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3517 le32_to_cpu(missed_beacon->total_missed_becons),
3518 le32_to_cpu(missed_beacon->num_recvd_beacons),
3519 le32_to_cpu(missed_beacon->num_expected_beacons));
f0832f13
EG		 3520 if (!test_bit(STATUS_SCANNING, &priv->status))
3521 iwl_init_sensitivity(priv);
b481de9c 3522 }
f0832f13 3523#endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
b481de9c 3524}
c8b0e6e1 3525#ifdef CONFIG_IWL4965_HT
b481de9c 3526
8b6eaea8
CB		 3527/**
3528 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3529 */
c79dd5b5 3530static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
b481de9c
ZY		 3531 int sta_id, int tid)
3532{
3533 unsigned long flags;
3534
8b6eaea8 3535 /* Remove "disable" flag, to enable Tx for this TID */
b481de9c
ZY		 3536 spin_lock_irqsave(&priv->sta_lock, flags);
3537 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3538 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3539 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3540 spin_unlock_irqrestore(&priv->sta_lock, flags);
3541
bb8c093b 3542 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3543}
3544
8b6eaea8
CB		 3545/**
3546 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3547 *
3548 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3549 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
3550 */
c79dd5b5 3551static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b
CH		 3552 struct iwl4965_ht_agg *agg,
3553 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 3554 ba_resp)
3555
3556{
3557 int i, sh, ack;
fe01b477
RR		 3558 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3559 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3560 u64 bitmap;
3561 int successes = 0;
3562 struct ieee80211_tx_status *tx_status;
b481de9c
ZY		 3563
3564 if (unlikely(!agg->wait_for_ba)) {
3565 IWL_ERROR("Received BA when not expected\n");
3566 return -EINVAL;
3567 }
8b6eaea8
CB		 3568
3569 /* Mark that the expected block-ack response arrived */
b481de9c 3570 agg->wait_for_ba = 0;
fe01b477 3571 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 3572
3573 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 3574 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 3575 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 3576 sh += 0x100;
3577
8b6eaea8 3578 /* don't use 64-bit values for now */
fe01b477 3579 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 3580
3581 if (agg->frame_count > (64 - sh)) {
3582 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3583 return -1;
3584 }
3585
3586 /* check for success or failure according to the
8b6eaea8 3587 * transmitted bitmap and block-ack bitmap */
fe01b477 3588 bitmap &= agg->bitmap;
b481de9c 3589
8b6eaea8
CB		 3590 /* For each frame attempted in aggregation,
3591 * update driver's record of tx frame's status. */
b481de9c 3592 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 3593 ack = bitmap & (1 << i);
3594 successes += !!ack;
b481de9c 3595 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 3596 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3597 agg->start_idx + i);
3598 }
3599
3600 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3601 tx_status->flags = IEEE80211_TX_STATUS_ACK;
99556438
RR		 3602 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3603 tx_status->ampdu_ack_map = successes;
3604 tx_status->ampdu_ack_len = agg->frame_count;
4c424e4c
RR		 3605 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3606 &tx_status->control);
fe01b477 3607
f868f4e1 3608 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 3609
3610 return 0;
3611}
3612
3613/**
3614 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3615 */
c79dd5b5 3616static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 3617 u16 txq_id)
3618{
3619 /* Simply stop the queue, but don't change any configuration;
3620 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 3621 iwl_write_prph(priv,
12a81f60 3622 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
fe01b477
RR		 3623 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3624 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3625}
b481de9c 3626
fe01b477
RR		 3627/**
3628 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
b095d03a 3629 * priv->lock must be held by the caller
fe01b477 3630 */
c79dd5b5 3631static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
fe01b477
RR		 3632 u16 ssn_idx, u8 tx_fifo)
3633{
b095d03a
RR		 3634 int ret = 0;
3635
fe01b477
RR		 3636 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3637 IWL_WARNING("queue number too small: %d, must be > %d\n",
3638 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3639 return -EINVAL;
b481de9c
ZY		 3640 }
3641
3395f6e9 3642 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 3643 if (ret)
3644 return ret;
3645
fe01b477
RR		 3646 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3647
12a81f60 3648 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 3649
3650 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3651 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3652 /* supposes that ssn_idx is valid (!= 0xFFF) */
3653 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3654
12a81f60 3655 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
fe01b477
RR		 3656 iwl4965_txq_ctx_deactivate(priv, txq_id);
3657 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3658
3395f6e9 3659 iwl_release_nic_access(priv);
b095d03a 3660
fe01b477
RR		 3661 return 0;
3662}
b481de9c 3663
c79dd5b5 3664int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
fe01b477
RR		 3665 u8 tid, int txq_id)
3666{
3667 struct iwl4965_queue *q = &priv->txq[txq_id].q;
3668 u8 *addr = priv->stations[sta_id].sta.sta.addr;
3669 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3670
3671 switch (priv->stations[sta_id].tid[tid].agg.state) {
3672 case IWL_EMPTYING_HW_QUEUE_DELBA:
3673 /* We are reclaiming the last packet of the */
3674 /* aggregated HW queue */
3675 if (txq_id == tid_data->agg.txq_id &&
3676 q->read_ptr == q->write_ptr) {
3677 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3678 int tx_fifo = default_tid_to_tx_fifo[tid];
3679 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3680 iwl4965_tx_queue_agg_disable(priv, txq_id,
3681 ssn, tx_fifo);
3682 tid_data->agg.state = IWL_AGG_OFF;
3683 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3684 }
3685 break;
3686 case IWL_EMPTYING_HW_QUEUE_ADDBA:
3687 /* We are reclaiming the last packet of the queue */
3688 if (tid_data->tfds_in_queue == 0) {
3689 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3690 tid_data->agg.state = IWL_AGG_ON;
3691 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3692 }
3693 break;
3694 }
b481de9c
ZY		 3695 return 0;
3696}
3697
8b6eaea8
CB		 3698/**
3699 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3700 * @index -- current index
3701 * @n_bd -- total number of entries in queue (s/b power of 2)
3702 */
bb8c093b 3703static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 3704{
3705 return (index == 0) ? n_bd - 1 : index - 1;
3706}
3707
8b6eaea8
CB		 3708/**
3709 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3710 *
3711 * Handles block-acknowledge notification from device, which reports success
3712 * of frames sent via aggregation.
3713 */
c79dd5b5 3714static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b 3715 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3716{
bb8c093b
CH		 3717 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3718 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 3719 int index;
bb8c093b
CH		 3720 struct iwl4965_tx_queue *txq = NULL;
3721 struct iwl4965_ht_agg *agg;
fe01b477 3722 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 3723
3724 /* "flow" corresponds to Tx queue */
fe01b477 3725 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 3726
3727 /* "ssn" is start of block-ack Tx window, corresponds to index
3728 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 3729 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3730
dfe7d458 3731 if (scd_flow >= priv->hw_params.max_txq_num) {
b481de9c
ZY		 3732 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3733 return;
3734 }
3735
fe01b477 3736 txq = &priv->txq[scd_flow];
b481de9c 3737 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 3738
3739 /* Find index just before block-ack window */
bb8c093b 3740 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 3741
01ebd063 3742 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 3743
0795af57
JP		 3744 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3745 "sta_id = %d\n",
b481de9c 3746 agg->wait_for_ba,
0795af57 3747 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 3748 ba_resp->sta_id);
fe01b477 3749 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 3750 "%d, scd_ssn = %d\n",
3751 ba_resp->tid,
fe01b477 3752 ba_resp->seq_ctl,
0310ae72 3753 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 3754 ba_resp->scd_flow,
3755 ba_resp->scd_ssn);
fe01b477 3756 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 3757 agg->start_idx,
f868f4e1 3758 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 3759
3760 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 3761 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 3762
3763 /* Release all TFDs before the SSN, i.e. all TFDs in front of
3764 * block-ack window (we assume that they've been successfully
3765 * transmitted ... if not, it's too late anyway). */
fe01b477
RR		 3766 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3767 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3768 priv->stations[ba_resp->sta_id].
3769 tid[ba_resp->tid].tfds_in_queue -= freed;
3770 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3771 priv->mac80211_registered &&
3772 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3773 ieee80211_wake_queue(priv->hw, scd_flow);
3774 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3775 ba_resp->tid, scd_flow);
3776 }
b481de9c
ZY		 3777}
3778
8b6eaea8
CB		 3779/**
3780 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3781 */
c79dd5b5 3782static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 3783 u16 txq_id)
3784{
3785 u32 tbl_dw_addr;
3786 u32 tbl_dw;
3787 u16 scd_q2ratid;
3788
3789 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3790
3791 tbl_dw_addr = priv->scd_base_addr +
3792 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3793
3395f6e9 3794 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 3795
3796 if (txq_id & 0x1)
3797 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3798 else
3799 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3800
3395f6e9 3801 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 3802
3803 return 0;
3804}
3805
fe01b477 3806
b481de9c 3807/**
8b6eaea8
CB		 3808 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3809 *
3810 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3811 * i.e. it must be one of the higher queues used for aggregation
b481de9c 3812 */
c79dd5b5 3813static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
b481de9c
ZY		 3814 int tx_fifo, int sta_id, int tid,
3815 u16 ssn_idx)
3816{
3817 unsigned long flags;
3818 int rc;
3819 u16 ra_tid;
3820
3821 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3822 IWL_WARNING("queue number too small: %d, must be > %d\n",
3823 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3824
3825 ra_tid = BUILD_RAxTID(sta_id, tid);
3826
8b6eaea8 3827 /* Modify device's station table to Tx this TID */
bb8c093b 3828 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 3829
3830 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 3831 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3832 if (rc) {
3833 spin_unlock_irqrestore(&priv->lock, flags);
3834 return rc;
3835 }
3836
8b6eaea8 3837 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 3838 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3839
8b6eaea8 3840 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 3841 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3842
8b6eaea8 3843 /* Set this queue as a chain-building queue */
12a81f60 3844 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 3845
8b6eaea8
CB		 3846 /* Place first TFD at index corresponding to start sequence number.
3847 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 3848 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3849 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 3850 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3851
8b6eaea8 3852 /* Set up Tx window size and frame limit for this queue */
3395f6e9 3853 iwl_write_targ_mem(priv,
b481de9c
ZY		 3854 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3855 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3856 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3857
3395f6e9 3858 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 3859 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3860 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3861 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3862
12a81f60 3863 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 3864
8b6eaea8 3865 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 3866 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3867
3395f6e9 3868 iwl_release_nic_access(priv);
b481de9c
ZY		 3869 spin_unlock_irqrestore(&priv->lock, flags);
3870
3871 return 0;
3872}
3873
c8b0e6e1 3874#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 3875
3876/**
3877 * iwl4965_add_station - Initialize a station's hardware rate table
3878 *
8b6eaea8 3879 * The uCode's station table contains a table of fallback rates
b481de9c
ZY		 3880 * for automatic fallback during transmission.
3881 *
8b6eaea8
CB		 3882 * NOTE: This sets up a default set of values. These will be replaced later
3883 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3884 * rc80211_simple.
b481de9c 3885 *
8b6eaea8
CB		 3886 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3887 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3888 * which requires station table entry to exist).
b481de9c 3889 */
c79dd5b5 3890void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 3891{
3892 int i, r;
66c73db7 3893 struct iwl_link_quality_cmd link_cmd = {
b481de9c
ZY		 3894 .reserved1 = 0,
3895 };
3896 u16 rate_flags;
3897
8b6eaea8
CB		 3898 /* Set up the rate scaling to start at selected rate, fall back
3899 * all the way down to 1M in IEEE order, and then spin on 1M */
b481de9c
ZY		 3900 if (is_ap)
3901 r = IWL_RATE_54M_INDEX;
8318d78a 3902 else if (priv->band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 3903 r = IWL_RATE_6M_INDEX;
3904 else
3905 r = IWL_RATE_1M_INDEX;
3906
3907 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3908 rate_flags = 0;
3909 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3910 rate_flags |= RATE_MCS_CCK_MSK;
3911
8b6eaea8 3912 /* Use Tx antenna B only */
b481de9c
ZY		 3913 rate_flags |= RATE_MCS_ANT_B_MSK;
3914 rate_flags &= ~RATE_MCS_ANT_A_MSK;
8b6eaea8 3915
b481de9c 3916 link_cmd.rs_table[i].rate_n_flags =
bb8c093b
CH		 3917 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3918 r = iwl4965_get_prev_ieee_rate(r);
b481de9c
ZY		 3919 }
3920
3921 link_cmd.general_params.single_stream_ant_msk = 2;
3922 link_cmd.general_params.dual_stream_ant_msk = 3;
3923 link_cmd.agg_params.agg_dis_start_th = 3;
3924 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3925
3926 /* Update the rate scaling for control frame Tx to AP */
5425e490 3927 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
b481de9c 3928
e5472978
TW		 3929 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3930 sizeof(link_cmd), &link_cmd, NULL);
b481de9c
ZY		 3931}
3932
c8b0e6e1 3933#ifdef CONFIG_IWL4965_HT
b481de9c 3934
c79dd5b5 3935static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
8318d78a 3936 enum ieee80211_band band,
78330fdd 3937 u16 channel, u8 extension_chan_offset)
b481de9c 3938{
bf85ea4f 3939 const struct iwl_channel_info *ch_info;
b481de9c 3940
8622e705 3941 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 3942 if (!is_channel_valid(ch_info))
3943 return 0;
3944
134eb5d3 3945 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
b481de9c
ZY		 3946 return 0;
3947
3948 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3949 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3950 return 1;
3951
3952 return 0;
3953}
3954
c79dd5b5 3955static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
fd105e79 3956 struct ieee80211_ht_info *sta_ht_inf)
b481de9c 3957{
fd105e79 3958 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
b481de9c 3959
fd105e79
RR		 3960 if ((!iwl_ht_conf->is_ht) ||
3961 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
134eb5d3 3962 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
b481de9c
ZY		 3963 return 0;
3964
fd105e79
RR		 3965 if (sta_ht_inf) {
3966 if ((!sta_ht_inf->ht_supported) ||
194c7ca6 3967 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
fd105e79
RR		 3968 return 0;
3969 }
b481de9c 3970
78330fdd 3971 return (iwl4965_is_channel_extension(priv, priv->band,
fd105e79
RR		 3972 iwl_ht_conf->control_channel,
3973 iwl_ht_conf->extension_chan_offset));
b481de9c
ZY		 3974}
3975
c79dd5b5 3976void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
b481de9c 3977{
bb8c093b 3978 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 3979 u32 val;
3980
3981 if (!ht_info->is_ht)
3982 return;
3983
8b6eaea8 3984 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
fd105e79 3985 if (iwl4965_is_fat_tx_allowed(priv, NULL))
b481de9c
ZY		 3986 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3987 else
3988 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
3989 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
3990
3991 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
3992 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
3993 le16_to_cpu(rxon->channel),
3994 ht_info->control_channel);
3995 rxon->channel = cpu_to_le16(ht_info->control_channel);
3996 return;
3997 }
3998
8b6eaea8 3999 /* Note: control channel is opposite of extension channel */
b481de9c
ZY		 4000 switch (ht_info->extension_chan_offset) {
4001 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4002 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4003 break;
4004 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4005 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4006 break;
134eb5d3 4007 case IWL_EXT_CHANNEL_OFFSET_NONE:
b481de9c
ZY		 4008 default:
4009 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4010 break;
4011 }
4012
fd105e79 4013 val = ht_info->ht_protection;
b481de9c
ZY		 4014
4015 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4016
b481de9c
ZY		 4017 iwl4965_set_rxon_chain(priv);
4018
4019 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
4020 "rxon flags 0x%X operation mode :0x%X "
4021 "extension channel offset 0x%x "
4022 "control chan %d\n",
fd105e79
RR		 4023 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
4024 le32_to_cpu(rxon->flags), ht_info->ht_protection,
b481de9c
ZY		 4025 ht_info->extension_chan_offset,
4026 ht_info->control_channel);
4027 return;
4028}
4029
c79dd5b5 4030void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
67d62035 4031 struct ieee80211_ht_info *sta_ht_inf)
b481de9c
ZY		 4032{
4033 __le32 sta_flags;
e53cfe0e 4034 u8 mimo_ps_mode;
b481de9c 4035
67d62035 4036 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
b481de9c
ZY		 4037 goto done;
4038
e53cfe0e
TW		 4039 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4040
b481de9c
ZY		 4041 sta_flags = priv->stations[index].sta.station_flags;
4042
e53cfe0e
TW		 4043 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4044
4045 switch (mimo_ps_mode) {
4046 case WLAN_HT_CAP_MIMO_PS_STATIC:
4047 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4048 break;
4049 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
b481de9c 4050 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
e53cfe0e
TW		 4051 break;
4052 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4053 break;
4054 default:
4055 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4056 break;
4057 }
b481de9c
ZY		 4058
4059 sta_flags |= cpu_to_le32(
67d62035 4060 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
b481de9c
ZY		 4061
4062 sta_flags |= cpu_to_le32(
67d62035 4063 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
b481de9c 4064
67d62035 4065 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
b481de9c 4066 sta_flags |= STA_FLG_FAT_EN_MSK;
67d62035 4067 else
e53cfe0e 4068 sta_flags &= ~STA_FLG_FAT_EN_MSK;
67d62035 4069
b481de9c
ZY		 4070 priv->stations[index].sta.station_flags = sta_flags;
4071 done:
4072 return;
4073}
4074
fe07aa7a
RR		 4075static int iwl4965_rx_agg_start(struct iwl_priv *priv,
4076 const u8 *addr, int tid, u16 ssn)
b481de9c
ZY		 4077{
4078 unsigned long flags;
fe07aa7a
RR		 4079 int sta_id;
4080
4081 sta_id = iwl_find_station(priv, addr);
4082 if (sta_id == IWL_INVALID_STATION)
4083 return -ENXIO;
b481de9c
ZY		 4084
4085 spin_lock_irqsave(&priv->sta_lock, flags);
4086 priv->stations[sta_id].sta.station_flags_msk = 0;
4087 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4088 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4089 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4090 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4091 spin_unlock_irqrestore(&priv->sta_lock, flags);
4092
fe07aa7a
RR		 4093 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4094 CMD_ASYNC);
b481de9c
ZY		 4095}
4096
fe07aa7a
RR		 4097static int iwl4965_rx_agg_stop(struct iwl_priv *priv,
4098 const u8 *addr, int tid)
b481de9c
ZY		 4099{
4100 unsigned long flags;
fe07aa7a
RR		 4101 int sta_id;
4102
4103 sta_id = iwl_find_station(priv, addr);
4104 if (sta_id == IWL_INVALID_STATION)
4105 return -ENXIO;
b481de9c
ZY		 4106
4107 spin_lock_irqsave(&priv->sta_lock, flags);
4108 priv->stations[sta_id].sta.station_flags_msk = 0;
4109 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4110 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4111 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4112 spin_unlock_irqrestore(&priv->sta_lock, flags);
4113
fe07aa7a
RR		 4114 return iwl4965_send_add_station(priv, &priv->stations[sta_id].sta,
4115 CMD_ASYNC);
b481de9c
ZY		 4116}
4117
8b6eaea8
CB		 4118/*
4119 * Find first available (lowest unused) Tx Queue, mark it "active".
4120 * Called only when finding queue for aggregation.
4121 * Should never return anything < 7, because they should already
4122 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4123 */
c79dd5b5 4124static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
b481de9c
ZY		 4125{
4126 int txq_id;
4127
5425e490 4128 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
b481de9c
ZY		 4129 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4130 return txq_id;
4131 return -1;
4132}
4133
fe07aa7a
RR		 4134static int iwl4965_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
4135 u16 tid, u16 *start_seq_num)
b481de9c 4136{
c79dd5b5 4137 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 4138 int sta_id;
4139 int tx_fifo;
4140 int txq_id;
4141 int ssn = -1;
b095d03a 4142 int ret = 0;
b481de9c 4143 unsigned long flags;
bb8c093b 4144 struct iwl4965_tid_data *tid_data;
0795af57 4145 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 4146
4147 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4148 tx_fifo = default_tid_to_tx_fifo[tid];
4149 else
4150 return -EINVAL;
4151
fe07aa7a
RR		 4152 IWL_WARNING("%s on ra = %s tid = %d\n",
4153 __func__, print_mac(mac, ra), tid);
b481de9c 4154
fe07aa7a 4155 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 4156 if (sta_id == IWL_INVALID_STATION)
4157 return -ENXIO;
4158
fe01b477
RR		 4159 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4160 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4161 return -ENXIO;
4162 }
4163
bb8c093b 4164 txq_id = iwl4965_txq_ctx_activate_free(priv);
b481de9c
ZY		 4165 if (txq_id == -1)
4166 return -ENXIO;
4167
4168 spin_lock_irqsave(&priv->sta_lock, flags);
4169 tid_data = &priv->stations[sta_id].tid[tid];
4170 ssn = SEQ_TO_SN(tid_data->seq_number);
4171 tid_data->agg.txq_id = txq_id;
4172 spin_unlock_irqrestore(&priv->sta_lock, flags);
4173
4174 *start_seq_num = ssn;
b095d03a
RR		 4175 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4176 sta_id, tid, ssn);
4177 if (ret)
4178 return ret;
b481de9c 4179
b095d03a 4180 ret = 0;
fe01b477
RR		 4181 if (tid_data->tfds_in_queue == 0) {
4182 printk(KERN_ERR "HW queue is empty\n");
4183 tid_data->agg.state = IWL_AGG_ON;
fe07aa7a 4184 ieee80211_start_tx_ba_cb_irqsafe(hw, ra, tid);
fe01b477
RR		 4185 } else {
4186 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4187 tid_data->tfds_in_queue);
4188 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4189 }
b095d03a 4190 return ret;
fe01b477 4191}
b481de9c 4192
fe07aa7a 4193static int iwl4965_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid)
b481de9c 4194{
c79dd5b5 4195 struct iwl_priv *priv = hw->priv;
b481de9c 4196 int tx_fifo_id, txq_id, sta_id, ssn = -1;
bb8c093b 4197 struct iwl4965_tid_data *tid_data;
b095d03a 4198 int ret, write_ptr, read_ptr;
fe01b477 4199 unsigned long flags;
0795af57
JP		 4200 DECLARE_MAC_BUF(mac);
4201
fe07aa7a
RR		 4202 if (!ra) {
4203 IWL_ERROR("ra = NULL\n");
b481de9c
ZY		 4204 return -EINVAL;
4205 }
4206
4207 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4208 tx_fifo_id = default_tid_to_tx_fifo[tid];
4209 else
4210 return -EINVAL;
4211
fe07aa7a 4212 sta_id = iwl_find_station(priv, ra);
b481de9c
ZY		 4213
4214 if (sta_id == IWL_INVALID_STATION)
4215 return -ENXIO;
4216
fe01b477
RR		 4217 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4218 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4219
b481de9c
ZY		 4220 tid_data = &priv->stations[sta_id].tid[tid];
4221 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4222 txq_id = tid_data->agg.txq_id;
fe01b477
RR		 4223 write_ptr = priv->txq[txq_id].q.write_ptr;
4224 read_ptr = priv->txq[txq_id].q.read_ptr;
4225
4226 /* The queue is not empty */
4227 if (write_ptr != read_ptr) {
4228 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4229 priv->stations[sta_id].tid[tid].agg.state =
4230 IWL_EMPTYING_HW_QUEUE_DELBA;
4231 return 0;
4232 }
4233
fe07aa7a 4234 IWL_DEBUG_HT("HW queue is empty\n");
fe01b477 4235 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
b481de9c 4236
fe01b477 4237 spin_lock_irqsave(&priv->lock, flags);
b095d03a 4238 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
fe01b477
RR		 4239 spin_unlock_irqrestore(&priv->lock, flags);
4240
b095d03a
RR		 4241 if (ret)
4242 return ret;
b481de9c 4243
fe07aa7a 4244 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
8114fcf1 4245
8114fcf1
RR		 4246 return 0;
4247}
4248
4249int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4250 enum ieee80211_ampdu_mlme_action action,
4251 const u8 *addr, u16 tid, u16 *ssn)
4252{
c79dd5b5 4253 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 4254 DECLARE_MAC_BUF(mac);
4255
fe07aa7a
RR		 4256 IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n",
4257 print_mac(mac, addr), tid);
4258
8114fcf1
RR		 4259 switch (action) {
4260 case IEEE80211_AMPDU_RX_START:
4261 IWL_DEBUG_HT("start Rx\n");
fe07aa7a 4262 return iwl4965_rx_agg_start(priv, addr, tid, *ssn);
8114fcf1
RR		 4263 case IEEE80211_AMPDU_RX_STOP:
4264 IWL_DEBUG_HT("stop Rx\n");
fe07aa7a 4265 return iwl4965_rx_agg_stop(priv, addr, tid);
8114fcf1
RR		 4266 case IEEE80211_AMPDU_TX_START:
4267 IWL_DEBUG_HT("start Tx\n");
fe07aa7a 4268 return iwl4965_tx_agg_start(hw, addr, tid, ssn);
8114fcf1
RR		 4269 case IEEE80211_AMPDU_TX_STOP:
4270 IWL_DEBUG_HT("stop Tx\n");
fe07aa7a 4271 return iwl4965_tx_agg_stop(hw, addr, tid);
8114fcf1
RR		 4272 default:
4273 IWL_DEBUG_HT("unknown\n");
4274 return -EINVAL;
4275 break;
4276 }
4277 return 0;
4278}
4279
c8b0e6e1 4280#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4281
4282/* Set up 4965-specific Rx frame reply handlers */
c79dd5b5 4283void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 4284{
4285 /* Legacy Rx frames */
857485c0 4286 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
b481de9c
ZY		 4287
4288 /* High-throughput (HT) Rx frames */
4289 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4290 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4291
4292 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4293 iwl4965_rx_missed_beacon_notif;
4294
c8b0e6e1 4295#ifdef CONFIG_IWL4965_HT
b481de9c 4296 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
c8b0e6e1 4297#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4298}
4299
c79dd5b5 4300void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4301{
4302 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
f0832f13 4303#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
b481de9c
ZY		 4304 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4305#endif
b481de9c
ZY		 4306 init_timer(&priv->statistics_periodic);
4307 priv->statistics_periodic.data = (unsigned long)priv;
4308 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4309}
4310
c79dd5b5 4311void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4312{
4313 del_timer_sync(&priv->statistics_periodic);
4314
4315 cancel_delayed_work(&priv->init_alive_start);
4316}
4317
3c424c28
TW		 4318
4319static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 4320 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 4321};
4322
857485c0
TW		 4323static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4324 .enqueue_hcmd = iwl4965_enqueue_hcmd,
f0832f13
EG		 4325#ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4326 .chain_noise_reset = iwl4965_chain_noise_reset,
4327 .gain_computation = iwl4965_gain_computation,
4328#endif
857485c0
TW		 4329};
4330
6bc913bd 4331static struct iwl_lib_ops iwl4965_lib = {
bf85ea4f 4332 .init_drv = iwl4965_init_drv,
5425e490 4333 .set_hw_params = iwl4965_hw_set_hw_params,
e2a722eb 4334 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
57aab75a
TW		 4335 .hw_nic_init = iwl4965_hw_nic_init,
4336 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4337 .alive_notify = iwl4965_alive_notify,
4338 .load_ucode = iwl4965_load_bsm,
6f4083aa
TW		 4339 .apm_ops = {
4340 .set_pwr_src = iwl4965_set_pwr_src,
4341 },
6bc913bd 4342 .eeprom_ops = {
073d3f5f
TW		 4343 .regulatory_bands = {
4344 EEPROM_REGULATORY_BAND_1_CHANNELS,
4345 EEPROM_REGULATORY_BAND_2_CHANNELS,
4346 EEPROM_REGULATORY_BAND_3_CHANNELS,
4347 EEPROM_REGULATORY_BAND_4_CHANNELS,
4348 EEPROM_REGULATORY_BAND_5_CHANNELS,
4349 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
4350 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
4351 },
6bc913bd
AK		 4352 .verify_signature = iwlcore_eeprom_verify_signature,
4353 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4354 .release_semaphore = iwlcore_eeprom_release_semaphore,
073d3f5f 4355 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 4356 },
ad97edd2 4357 .radio_kill_sw = iwl4965_radio_kill_sw,
5da4b55f
MA		 4358 .set_power = iwl4965_set_power,
4359 .update_chain_flags = iwl4965_update_chain_flags,
6bc913bd
AK		 4360};
4361
4362static struct iwl_ops iwl4965_ops = {
4363 .lib = &iwl4965_lib,
3c424c28 4364 .hcmd = &iwl4965_hcmd,
857485c0 4365 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 4366};
4367
fed9017e 4368struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 4369 .name = "4965AGN",
4bf775cd 4370 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 4371 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 4372 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
6bc913bd 4373 .ops = &iwl4965_ops,
1ea87396 4374 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 4375};
4376
1ea87396
AK		 4377module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4378MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4379module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4380MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b
EG		 4381module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4382MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
1ea87396
AK		 4383module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4384MODULE_PARM_DESC(debug, "debug output mask");
4385module_param_named(
4386 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4387MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4388
4389module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4390MODULE_PARM_DESC(queues_num, "number of hw queues.");
4391
4392/* QoS */
4393module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4394MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4395module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4396MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4397
Linux kernel - Deliverables
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