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mac80211: fix bss_conf.dtim_period
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
5a6a256e
TW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
5a6a256e
TW		 28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
d43c36dc 32#include <linux/sched.h>
5a6a256e
TW		 33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
37#include <linux/etherdevice.h>
38#include <asm/unaligned.h>
39
40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
5a6a256e
TW		 42#include "iwl-core.h"
43#include "iwl-io.h"
e26e47d9 44#include "iwl-sta.h"
5a6a256e 45#include "iwl-helpers.h"
e932a609 46#include "iwl-agn-led.h"
5a6a256e 47#include "iwl-5000-hw.h"
c0bac76a 48#include "iwl-6000-hw.h"
5a6a256e 49
a0987a8d 50/* Highest firmware API version supported */
c9d2fbf3 51#define IWL5000_UCODE_API_MAX 2
39e6d225 52#define IWL5150_UCODE_API_MAX 2
5a6a256e 53
a0987a8d
RC		 54/* Lowest firmware API version supported */
55#define IWL5000_UCODE_API_MIN 1
56#define IWL5150_UCODE_API_MIN 1
57
58#define IWL5000_FW_PRE "iwlwifi-5000-"
59#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
60#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
61
62#define IWL5150_FW_PRE "iwlwifi-5150-"
63#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
64#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
4e062f99 65
99da1b48
RR		 66static const u16 iwl5000_default_queue_to_tx_fifo[] = {
67 IWL_TX_FIFO_AC3,
68 IWL_TX_FIFO_AC2,
69 IWL_TX_FIFO_AC1,
70 IWL_TX_FIFO_AC0,
71 IWL50_CMD_FIFO_NUM,
72 IWL_TX_FIFO_HCCA_1,
73 IWL_TX_FIFO_HCCA_2
74};
75
9371d4ed 76/* NIC configuration for 5000 series */
672639de 77void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 78{
79 unsigned long flags;
80 u16 radio_cfg;
e86fe9f6
TW		 81
82 spin_lock_irqsave(&priv->lock, flags);
83
e86fe9f6
TW		 84 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
85
86 /* write radio config values to register */
9371d4ed 87 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
e86fe9f6
TW		 88 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
89 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
90 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
91 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
92
93 /* set CSR_HW_CONFIG_REG for uCode use */
94 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
95 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
96 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
97
4c43e0d0
TW		 98 /* W/A : NIC is stuck in a reset state after Early PCIe power off
99 * (PCIe power is lost before PERST# is asserted),
100 * causing ME FW to lose ownership and not being able to obtain it back.
101 */
2d3db679 102 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
4c43e0d0
TW		 103 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
104 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
105
02c06e4a 106
e86fe9f6
TW		 107 spin_unlock_irqrestore(&priv->lock, flags);
108}
109
110
25ae3986
TW		 111/*
112 * EEPROM
113 */
114static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
115{
116 u16 offset = 0;
117
118 if ((address & INDIRECT_ADDRESS) == 0)
119 return address;
120
121 switch (address & INDIRECT_TYPE_MSK) {
122 case INDIRECT_HOST:
123 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
124 break;
125 case INDIRECT_GENERAL:
126 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
127 break;
128 case INDIRECT_REGULATORY:
129 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
130 break;
131 case INDIRECT_CALIBRATION:
132 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
133 break;
134 case INDIRECT_PROCESS_ADJST:
135 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
136 break;
137 case INDIRECT_OTHERS:
138 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
139 break;
140 default:
15b1687c 141 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
25ae3986
TW		 142 address & INDIRECT_TYPE_MSK);
143 break;
144 }
145
146 /* translate the offset from words to byte */
147 return (address & ADDRESS_MSK) + (offset << 1);
148}
149
672639de 150u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
f1f69415 151{
f1f69415
TW		 152 struct iwl_eeprom_calib_hdr {
153 u8 version;
154 u8 pa_type;
155 u16 voltage;
156 } *hdr;
157
f1f69415
TW		 158 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
159 EEPROM_5000_CALIB_ALL);
0ef2ca67 160 return hdr->version;
f1f69415
TW		 161
162}
163
33fd5033
EG		 164static void iwl5000_gain_computation(struct iwl_priv *priv,
165 u32 average_noise[NUM_RX_CHAINS],
166 u16 min_average_noise_antenna_i,
d8c07e7a
WYG		 167 u32 min_average_noise,
168 u8 default_chain)
33fd5033
EG		 169{
170 int i;
171 s32 delta_g;
172 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
173
d8c07e7a
WYG		 174 /*
175 * Find Gain Code for the chains based on "default chain"
176 */
177 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
33fd5033
EG		 178 if ((data->disconn_array[i])) {
179 data->delta_gain_code[i] = 0;
180 continue;
181 }
065e63b0 182 delta_g = (1000 * ((s32)average_noise[default_chain] -
33fd5033
EG		 183 (s32)average_noise[i])) / 1500;
184 /* bound gain by 2 bits value max, 3rd bit is sign */
185 data->delta_gain_code[i] =
886e71de 186 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
33fd5033
EG		 187
188 if (delta_g < 0)
189 /* set negative sign */
190 data->delta_gain_code[i] |= (1 << 2);
191 }
192
e1623446 193 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
33fd5033
EG		 194 data->delta_gain_code[1], data->delta_gain_code[2]);
195
196 if (!data->radio_write) {
f69f42a6 197 struct iwl_calib_chain_noise_gain_cmd cmd;
0d950d84 198
33fd5033
EG		 199 memset(&cmd, 0, sizeof(cmd));
200
0d950d84
TW		 201 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
202 cmd.hdr.first_group = 0;
203 cmd.hdr.groups_num = 1;
204 cmd.hdr.data_valid = 1;
33fd5033
EG		 205 cmd.delta_gain_1 = data->delta_gain_code[1];
206 cmd.delta_gain_2 = data->delta_gain_code[2];
207 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
208 sizeof(cmd), &cmd, NULL);
209
210 data->radio_write = 1;
211 data->state = IWL_CHAIN_NOISE_CALIBRATED;
212 }
213
214 data->chain_noise_a = 0;
215 data->chain_noise_b = 0;
216 data->chain_noise_c = 0;
217 data->chain_signal_a = 0;
218 data->chain_signal_b = 0;
219 data->chain_signal_c = 0;
220 data->beacon_count = 0;
221}
222
223static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
224{
225 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
0d950d84 226 int ret;
33fd5033
EG		 227
228 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 229 struct iwl_calib_chain_noise_reset_cmd cmd;
33fd5033 230 memset(&cmd, 0, sizeof(cmd));
0d950d84
TW		 231
232 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
233 cmd.hdr.first_group = 0;
234 cmd.hdr.groups_num = 1;
235 cmd.hdr.data_valid = 1;
236 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
237 sizeof(cmd), &cmd);
238 if (ret)
15b1687c
WT		 239 IWL_ERR(priv,
240 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
33fd5033 241 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
e1623446 242 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
33fd5033
EG		 243 }
244}
245
e8c00dcb 246void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
a326a5d0
EG		 247 __le32 *tx_flags)
248{
e6a9854b
JB		 249 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
250 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
a326a5d0
EG		 251 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
252 else
253 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
254}
255
33fd5033
EG		 256static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
257 .min_nrg_cck = 95,
fe6efb4b 258 .max_nrg_cck = 0, /* not used, set to 0 */
33fd5033
EG		 259 .auto_corr_min_ofdm = 90,
260 .auto_corr_min_ofdm_mrc = 170,
261 .auto_corr_min_ofdm_x1 = 120,
262 .auto_corr_min_ofdm_mrc_x1 = 240,
263
264 .auto_corr_max_ofdm = 120,
265 .auto_corr_max_ofdm_mrc = 210,
9bead763
WYG		 266 .auto_corr_max_ofdm_x1 = 120,
267 .auto_corr_max_ofdm_mrc_x1 = 240,
33fd5033
EG		 268
269 .auto_corr_min_cck = 125,
270 .auto_corr_max_cck = 200,
271 .auto_corr_min_cck_mrc = 170,
272 .auto_corr_max_cck_mrc = 400,
273 .nrg_th_cck = 95,
274 .nrg_th_ofdm = 95,
55036d66
WYG		 275
276 .barker_corr_th_min = 190,
277 .barker_corr_th_min_mrc = 390,
278 .nrg_th_cca = 62,
33fd5033
EG		 279};
280
9d67187d
WYG		 281static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
282 .min_nrg_cck = 95,
283 .max_nrg_cck = 0, /* not used, set to 0 */
284 .auto_corr_min_ofdm = 90,
285 .auto_corr_min_ofdm_mrc = 170,
286 .auto_corr_min_ofdm_x1 = 105,
287 .auto_corr_min_ofdm_mrc_x1 = 220,
288
289 .auto_corr_max_ofdm = 120,
290 .auto_corr_max_ofdm_mrc = 210,
291 /* max = min for performance bug in 5150 DSP */
292 .auto_corr_max_ofdm_x1 = 105,
293 .auto_corr_max_ofdm_mrc_x1 = 220,
294
295 .auto_corr_min_cck = 125,
296 .auto_corr_max_cck = 200,
297 .auto_corr_min_cck_mrc = 170,
298 .auto_corr_max_cck_mrc = 400,
299 .nrg_th_cck = 95,
300 .nrg_th_ofdm = 95,
55036d66
WYG		 301
302 .barker_corr_th_min = 190,
303 .barker_corr_th_min_mrc = 390,
304 .nrg_th_cca = 62,
9d67187d
WYG		 305};
306
672639de 307const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
25ae3986
TW		 308 size_t offset)
309{
310 u32 address = eeprom_indirect_address(priv, offset);
311 BUG_ON(address >= priv->cfg->eeprom_size);
312 return &priv->eeprom[address];
313}
314
62161aef 315static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
339afc89 316{
62161aef 317 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
672639de 318 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
62161aef
WYG		 319 iwl_temp_calib_to_offset(priv);
320
321 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
322}
323
324static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
325{
326 /* want Celsius */
672639de 327 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
339afc89
TW		 328}
329
7c616cba
TW		 330/*
331 * Calibration
332 */
be5d56ed 333static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
7c616cba 334{
0d950d84 335 struct iwl_calib_xtal_freq_cmd cmd;
b7bb1756
JB		 336 __le16 *xtal_calib =
337 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
7c616cba 338
0d950d84
TW		 339 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
340 cmd.hdr.first_group = 0;
341 cmd.hdr.groups_num = 1;
342 cmd.hdr.data_valid = 1;
b7bb1756
JB		 343 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
344 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
f69f42a6 345 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
0d950d84 346 (u8 *)&cmd, sizeof(cmd));
7c616cba
TW		 347}
348
7c616cba
TW		 349static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
350{
f69f42a6 351 struct iwl_calib_cfg_cmd calib_cfg_cmd;
7c616cba
TW		 352 struct iwl_host_cmd cmd = {
353 .id = CALIBRATION_CFG_CMD,
f69f42a6 354 .len = sizeof(struct iwl_calib_cfg_cmd),
7c616cba
TW		 355 .data = &calib_cfg_cmd,
356 };
357
358 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
359 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
360 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
361 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
362 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
363
364 return iwl_send_cmd(priv, &cmd);
365}
366
367static void iwl5000_rx_calib_result(struct iwl_priv *priv,
368 struct iwl_rx_mem_buffer *rxb)
369{
2f301227 370 struct iwl_rx_packet *pkt = rxb_addr(rxb);
f69f42a6 371 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
396887a2 372 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
6e21f2c1 373 int index;
7c616cba
TW		 374
375 /* reduce the size of the length field itself */
376 len -= 4;
377
6e21f2c1
TW		 378 /* Define the order in which the results will be sent to the runtime
379 * uCode. iwl_send_calib_results sends them in a row according to their
380 * index. We sort them here */
7c616cba 381 switch (hdr->op_code) {
819500c5
TW		 382 case IWL_PHY_CALIBRATE_DC_CMD:
383 index = IWL_CALIB_DC;
384 break;
f69f42a6
TW		 385 case IWL_PHY_CALIBRATE_LO_CMD:
386 index = IWL_CALIB_LO;
7c616cba 387 break;
f69f42a6
TW		 388 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
389 index = IWL_CALIB_TX_IQ;
7c616cba 390 break;
f69f42a6
TW		 391 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
392 index = IWL_CALIB_TX_IQ_PERD;
7c616cba 393 break;
201706ac
TW		 394 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
395 index = IWL_CALIB_BASE_BAND;
396 break;
7c616cba 397 default:
15b1687c 398 IWL_ERR(priv, "Unknown calibration notification %d\n",
7c616cba
TW		 399 hdr->op_code);
400 return;
401 }
6e21f2c1 402 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
7c616cba
TW		 403}
404
405static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
406 struct iwl_rx_mem_buffer *rxb)
407{
e1623446 408 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
7c616cba
TW		 409 queue_work(priv->workqueue, &priv->restart);
410}
411
dbb983b7
RR		 412/*
413 * ucode
414 */
9f1f3cea
JB		 415static int iwl5000_load_section(struct iwl_priv *priv, const char *name,
416 struct fw_desc *image, u32 dst_addr)
dbb983b7 417{
dbb983b7
RR		 418 dma_addr_t phy_addr = image->p_addr;
419 u32 byte_cnt = image->len;
9f1f3cea
JB		 420 int ret;
421
422 priv->ucode_write_complete = 0;
dbb983b7 423
dbb983b7
RR		 424 iwl_write_direct32(priv,
425 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
426 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
427
428 iwl_write_direct32(priv,
429 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
430
431 iwl_write_direct32(priv,
432 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
433 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
434
dbb983b7 435 iwl_write_direct32(priv,
f0b9f5cb 436 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
499b1883 437 (iwl_get_dma_hi_addr(phy_addr)
f0b9f5cb
TW		 438 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
439
dbb983b7
RR		 440 iwl_write_direct32(priv,
441 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
442 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
443 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
444 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
445
446 iwl_write_direct32(priv,
447 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
448 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
9c80c502 449 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
dbb983b7
RR		 450 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
451
9f1f3cea 452 IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
dbb983b7 453 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
9c80c502 454 priv->ucode_write_complete, 5 * HZ);
dbb983b7 455 if (ret == -ERESTARTSYS) {
9f1f3cea
JB		 456 IWL_ERR(priv, "Could not load the %s uCode section due "
457 "to interrupt\n", name);
dbb983b7
RR		 458 return ret;
459 }
460 if (!ret) {
9f1f3cea
JB		 461 IWL_ERR(priv, "Could not load the %s uCode section\n",
462 name);
dbb983b7
RR		 463 return -ETIMEDOUT;
464 }
465
9f1f3cea
JB		 466 return 0;
467}
dbb983b7 468
9f1f3cea
JB		 469static int iwl5000_load_given_ucode(struct iwl_priv *priv,
470 struct fw_desc *inst_image,
471 struct fw_desc *data_image)
472{
473 int ret = 0;
dbb983b7 474
9f1f3cea
JB		 475 ret = iwl5000_load_section(priv, "INST", inst_image,
476 IWL50_RTC_INST_LOWER_BOUND);
477 if (ret)
dbb983b7 478 return ret;
dbb983b7 479
9f1f3cea
JB		 480 return iwl5000_load_section(priv, "DATA", data_image,
481 IWL50_RTC_DATA_LOWER_BOUND);
dbb983b7
RR		 482}
483
672639de 484int iwl5000_load_ucode(struct iwl_priv *priv)
dbb983b7
RR		 485{
486 int ret = 0;
487
488 /* check whether init ucode should be loaded, or rather runtime ucode */
489 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
e1623446 490 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
dbb983b7
RR		 491 ret = iwl5000_load_given_ucode(priv,
492 &priv->ucode_init, &priv->ucode_init_data);
493 if (!ret) {
e1623446 494 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
dbb983b7
RR		 495 priv->ucode_type = UCODE_INIT;
496 }
497 } else {
e1623446 498 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
dbb983b7
RR		 499 "Loading runtime ucode...\n");
500 ret = iwl5000_load_given_ucode(priv,
501 &priv->ucode_code, &priv->ucode_data);
502 if (!ret) {
e1623446 503 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
dbb983b7
RR		 504 priv->ucode_type = UCODE_RT;
505 }
506 }
507
508 return ret;
509}
510
672639de 511void iwl5000_init_alive_start(struct iwl_priv *priv)
99da1b48
RR		 512{
513 int ret = 0;
514
515 /* Check alive response for "valid" sign from uCode */
516 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
517 /* We had an error bringing up the hardware, so take it
518 * all the way back down so we can try again */
e1623446 519 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
99da1b48
RR		 520 goto restart;
521 }
522
523 /* initialize uCode was loaded... verify inst image.
524 * This is a paranoid check, because we would not have gotten the
525 * "initialize" alive if code weren't properly loaded. */
526 if (iwl_verify_ucode(priv)) {
527 /* Runtime instruction load was bad;
528 * take it all the way back down so we can try again */
e1623446 529 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
99da1b48
RR		 530 goto restart;
531 }
532
c587de0b 533 iwl_clear_stations_table(priv);
99da1b48
RR		 534 ret = priv->cfg->ops->lib->alive_notify(priv);
535 if (ret) {
39aadf8c
WT		 536 IWL_WARN(priv,
537 "Could not complete ALIVE transition: %d\n", ret);
99da1b48
RR		 538 goto restart;
539 }
540
7c616cba 541 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 542 return;
543
544restart:
545 /* real restart (first load init_ucode) */
546 queue_work(priv->workqueue, &priv->restart);
547}
548
549static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
550 int txq_id, u32 index)
551{
552 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
553 (index & 0xff) | (txq_id << 8));
554 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
555}
556
557static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
558 struct iwl_tx_queue *txq,
559 int tx_fifo_id, int scd_retry)
560{
561 int txq_id = txq->q.id;
3fd07a1e 562 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
99da1b48
RR		 563
564 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
565 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
566 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
567 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
568 IWL50_SCD_QUEUE_STTS_REG_MSK);
569
570 txq->sched_retry = scd_retry;
571
e1623446 572 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
99da1b48
RR		 573 active ? "Activate" : "Deactivate",
574 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
575}
576
672639de 577int iwl5000_alive_notify(struct iwl_priv *priv)
99da1b48
RR		 578{
579 u32 a;
99da1b48 580 unsigned long flags;
31a73fe4 581 int i, chan;
40fc95d5 582 u32 reg_val;
99da1b48
RR		 583
584 spin_lock_irqsave(&priv->lock, flags);
585
99da1b48
RR		 586 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
587 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
588 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
589 a += 4)
590 iwl_write_targ_mem(priv, a, 0);
591 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
592 a += 4)
593 iwl_write_targ_mem(priv, a, 0);
39d5e0ce
HW		 594 for (; a < priv->scd_base_addr +
595 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
99da1b48
RR		 596 iwl_write_targ_mem(priv, a, 0);
597
598 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
4ddbb7d0 599 priv->scd_bc_tbls.dma >> 10);
31a73fe4
WT		 600
601 /* Enable DMA channel */
602 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
603 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
604 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
605 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
606
40fc95d5
WT		 607 /* Update FH chicken bits */
608 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
609 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
610 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
611
99da1b48 612 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
4ddbb7d0 613 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
99da1b48
RR		 614 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
615
616 /* initiate the queues */
617 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
618 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
619 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
620 iwl_write_targ_mem(priv, priv->scd_base_addr +
621 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
622 iwl_write_targ_mem(priv, priv->scd_base_addr +
623 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
624 sizeof(u32),
625 ((SCD_WIN_SIZE <<
626 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
627 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
628 ((SCD_FRAME_LIMIT <<
629 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
630 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
631 }
632
633 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 634 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 635
da1bc453
TW		 636 /* Activate all Tx DMA/FIFO channels */
637 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 638
639 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
9c80c502 640
99da1b48
RR		 641 /* map qos queues to fifos one-to-one */
642 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
643 int ac = iwl5000_default_queue_to_tx_fifo[i];
644 iwl_txq_ctx_activate(priv, i);
645 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
646 }
a221e6f7
JB		 647
648 /*
649 * TODO - need to initialize these queues and map them to FIFOs
650 * in the loop above, not only mark them as active. We do this
651 * because we want the first aggregation queue to be queue #10,
652 * but do not use 8 or 9 otherwise yet.
653 */
99da1b48
RR		 654 iwl_txq_ctx_activate(priv, 7);
655 iwl_txq_ctx_activate(priv, 8);
656 iwl_txq_ctx_activate(priv, 9);
657
99da1b48
RR		 658 spin_unlock_irqrestore(&priv->lock, flags);
659
7c616cba 660
1933ac4d 661 iwl_send_wimax_coex(priv);
9636e583 662
be5d56ed
TW		 663 iwl5000_set_Xtal_calib(priv);
664 iwl_send_calib_results(priv);
7c616cba 665
99da1b48
RR		 666 return 0;
667}
668
672639de 669int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
fdd3e8a4 670{
88804e2b
WYG		 671 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
672 priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
673 priv->cfg->num_of_queues =
674 priv->cfg->mod_params->num_of_queues;
25ae3986 675
88804e2b 676 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
f3f911d1 677 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
4ddbb7d0 678 priv->hw_params.scd_bc_tbls_size =
88804e2b
WYG		 679 priv->cfg->num_of_queues *
680 sizeof(struct iwl5000_scd_bc_tbl);
a8e74e27 681 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
fdd3e8a4
TW		 682 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
683 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
c0bac76a 684
f3a2a424
WYG		 685 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
686 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
c0bac76a 687
da154e30 688 priv->hw_params.max_bsm_size = 0;
7aafef1c 689 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
fdd3e8a4 690 BIT(IEEE80211_BAND_5GHZ);
141c43a3
WT		 691 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
692
c0bac76a
JS		 693 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
694 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
695 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
696 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
c031bf80 697
62161aef
WYG		 698 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
699 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
c031bf80 700
9d67187d 701 /* Set initial sensitivity parameters */
be5d56ed
TW		 702 /* Set initial calibration set */
703 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
c0bac76a 704 case CSR_HW_REV_TYPE_5150:
9d67187d 705 priv->hw_params.sens = &iwl5150_sensitivity;
be5d56ed 706 priv->hw_params.calib_init_cfg =
c0bac76a 707 BIT(IWL_CALIB_DC) |
f69f42a6 708 BIT(IWL_CALIB_LO) |
201706ac 709 BIT(IWL_CALIB_TX_IQ) |
201706ac 710 BIT(IWL_CALIB_BASE_BAND);
c0bac76a 711
be5d56ed 712 break;
c0bac76a 713 default:
9d67187d 714 priv->hw_params.sens = &iwl5000_sensitivity;
819500c5 715 priv->hw_params.calib_init_cfg =
c0bac76a 716 BIT(IWL_CALIB_XTAL) |
7470d7f5
WT		 717 BIT(IWL_CALIB_LO) |
718 BIT(IWL_CALIB_TX_IQ) |
c0bac76a 719 BIT(IWL_CALIB_TX_IQ_PERD) |
7470d7f5 720 BIT(IWL_CALIB_BASE_BAND);
be5d56ed
TW		 721 break;
722 }
723
fdd3e8a4
TW		 724 return 0;
725}
d4100dd9 726
7839fc03
EG		 727/**
728 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
729 */
672639de 730void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 731 struct iwl_tx_queue *txq,
7839fc03
EG		 732 u16 byte_cnt)
733{
4ddbb7d0 734 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab 735 int write_ptr = txq->q.write_ptr;
7839fc03
EG		 736 int txq_id = txq->q.id;
737 u8 sec_ctl = 0;
127901ab
TW		 738 u8 sta_id = 0;
739 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
740 __le16 bc_ent;
7839fc03 741
127901ab 742 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
7839fc03
EG		 743
744 if (txq_id != IWL_CMD_QUEUE_NUM) {
127901ab 745 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
da99c4b6 746 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 747
748 switch (sec_ctl & TX_CMD_SEC_MSK) {
749 case TX_CMD_SEC_CCM:
750 len += CCMP_MIC_LEN;
751 break;
752 case TX_CMD_SEC_TKIP:
753 len += TKIP_ICV_LEN;
754 break;
755 case TX_CMD_SEC_WEP:
756 len += WEP_IV_LEN + WEP_ICV_LEN;
757 break;
758 }
759 }
760
127901ab 761 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
7839fc03 762
4ddbb7d0 763 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
7839fc03 764
8ce1ef4a 765 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 766 scd_bc_tbl[txq_id].
127901ab 767 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
7839fc03
EG		 768}
769
672639de 770void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
972cf447
TW		 771 struct iwl_tx_queue *txq)
772{
4ddbb7d0 773 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 774 int txq_id = txq->q.id;
775 int read_ptr = txq->q.read_ptr;
776 u8 sta_id = 0;
777 __le16 bc_ent;
778
779 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
972cf447
TW		 780
781 if (txq_id != IWL_CMD_QUEUE_NUM)
127901ab 782 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
972cf447 783
8ce1ef4a 784 bc_ent = cpu_to_le16(1 | (sta_id << 12));
4ddbb7d0 785 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
972cf447 786
8ce1ef4a 787 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 788 scd_bc_tbl[txq_id].
8ce1ef4a 789 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
972cf447
TW		 790}
791
e26e47d9
TW		 792static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
793 u16 txq_id)
794{
795 u32 tbl_dw_addr;
796 u32 tbl_dw;
797 u16 scd_q2ratid;
798
799 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
800
801 tbl_dw_addr = priv->scd_base_addr +
802 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
803
804 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
805
806 if (txq_id & 0x1)
807 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
808 else
809 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
810
811 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
812
813 return 0;
814}
815static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
816{
817 /* Simply stop the queue, but don't change any configuration;
818 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
819 iwl_write_prph(priv,
820 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
821 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
822 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
823}
824
672639de 825int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
e26e47d9
TW		 826 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
827{
828 unsigned long flags;
e26e47d9
TW		 829 u16 ra_tid;
830
9f17b318 831 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
88804e2b
WYG		 832 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
833 <= txq_id)) {
39aadf8c
WT		 834 IWL_WARN(priv,
835 "queue number out of range: %d, must be %d to %d\n",
9f17b318 836 txq_id, IWL50_FIRST_AMPDU_QUEUE,
88804e2b
WYG		 837 IWL50_FIRST_AMPDU_QUEUE +
838 priv->cfg->num_of_ampdu_queues - 1);
9f17b318
TW		 839 return -EINVAL;
840 }
e26e47d9
TW		 841
842 ra_tid = BUILD_RAxTID(sta_id, tid);
843
844 /* Modify device's station table to Tx this TID */
9f58671e 845 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
e26e47d9
TW		 846
847 spin_lock_irqsave(&priv->lock, flags);
e26e47d9
TW		 848
849 /* Stop this Tx queue before configuring it */
850 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
851
852 /* Map receiver-address / traffic-ID to this queue */
853 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
854
855 /* Set this queue as a chain-building queue */
856 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
857
858 /* enable aggregations for the queue */
859 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
860
861 /* Place first TFD at index corresponding to start sequence number.
862 * Assumes that ssn_idx is valid (!= 0xFFF) */
863 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
864 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
865 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
866
867 /* Set up Tx window size and frame limit for this queue */
868 iwl_write_targ_mem(priv, priv->scd_base_addr +
869 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
870 sizeof(u32),
871 ((SCD_WIN_SIZE <<
872 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
873 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
874 ((SCD_FRAME_LIMIT <<
875 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
876 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
877
878 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
879
880 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
881 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
882
e26e47d9
TW		 883 spin_unlock_irqrestore(&priv->lock, flags);
884
885 return 0;
886}
887
672639de 888int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
e26e47d9
TW		 889 u16 ssn_idx, u8 tx_fifo)
890{
9f17b318 891 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
88804e2b
WYG		 892 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
893 <= txq_id)) {
a2f1cbeb 894 IWL_ERR(priv,
39aadf8c 895 "queue number out of range: %d, must be %d to %d\n",
9f17b318 896 txq_id, IWL50_FIRST_AMPDU_QUEUE,
88804e2b
WYG		 897 IWL50_FIRST_AMPDU_QUEUE +
898 priv->cfg->num_of_ampdu_queues - 1);
e26e47d9
TW		 899 return -EINVAL;
900 }
901
e26e47d9
TW		 902 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
903
904 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
905
906 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
907 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
908 /* supposes that ssn_idx is valid (!= 0xFFF) */
909 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
910
911 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
912 iwl_txq_ctx_deactivate(priv, txq_id);
913 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
914
e26e47d9
TW		 915 return 0;
916}
917
e8c00dcb 918u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2469bf2e
TW		 919{
920 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
c587de0b
TW		 921 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
922 memcpy(addsta, cmd, size);
923 /* resrved in 5000 */
924 addsta->rate_n_flags = cpu_to_le16(0);
2469bf2e
TW		 925 return size;
926}
927
928
da1bc453 929/*
a96a27f9 930 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 931 * must be called under priv->lock and mac access
932 */
672639de 933void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 934{
da1bc453 935 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 936}
937
e532fa0e
RR		 938
939static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
940{
3ac7f146 941 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 942 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 943}
944
945static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
946 struct iwl_ht_agg *agg,
947 struct iwl5000_tx_resp *tx_resp,
25a6572c 948 int txq_id, u16 start_idx)
e532fa0e
RR		 949{
950 u16 status;
951 struct agg_tx_status *frame_status = &tx_resp->status;
952 struct ieee80211_tx_info *info = NULL;
953 struct ieee80211_hdr *hdr = NULL;
e7d326ac 954 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 955 int i, sh, idx;
e532fa0e
RR		 956 u16 seq;
957
958 if (agg->wait_for_ba)
e1623446 959 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
e532fa0e
RR		 960
961 agg->frame_count = tx_resp->frame_count;
962 agg->start_idx = start_idx;
e7d326ac 963 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 964 agg->bitmap = 0;
965
966 /* # frames attempted by Tx command */
967 if (agg->frame_count == 1) {
968 /* Only one frame was attempted; no block-ack will arrive */
969 status = le16_to_cpu(frame_status[0].status);
25a6572c 970 idx = start_idx;
e532fa0e
RR		 971
972 /* FIXME: code repetition */
e1623446 973 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
e532fa0e
RR		 974 agg->frame_count, agg->start_idx, idx);
975
976 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 977 info->status.rates[0].count = tx_resp->failure_frame + 1;
e532fa0e 978 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c397bf15 979 info->flags |= iwl_tx_status_to_mac80211(status);
e7d326ac
TW		 980 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
981
e532fa0e
RR		 982 /* FIXME: code repetition end */
983
e1623446 984 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
e532fa0e 985 status & 0xff, tx_resp->failure_frame);
e1623446 986 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 987
988 agg->wait_for_ba = 0;
989 } else {
990 /* Two or more frames were attempted; expect block-ack */
991 u64 bitmap = 0;
992 int start = agg->start_idx;
993
994 /* Construct bit-map of pending frames within Tx window */
995 for (i = 0; i < agg->frame_count; i++) {
996 u16 sc;
997 status = le16_to_cpu(frame_status[i].status);
998 seq = le16_to_cpu(frame_status[i].sequence);
999 idx = SEQ_TO_INDEX(seq);
1000 txq_id = SEQ_TO_QUEUE(seq);
1001
1002 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1003 AGG_TX_STATE_ABORT_MSK))
1004 continue;
1005
e1623446 1006 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
e532fa0e
RR		 1007 agg->frame_count, txq_id, idx);
1008
1009 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
6c6a22e2
SG		 1010 if (!hdr) {
1011 IWL_ERR(priv,
1012 "BUG_ON idx doesn't point to valid skb"
1013 " idx=%d, txq_id=%d\n", idx, txq_id);
1014 return -1;
1015 }
e532fa0e
RR		 1016
1017 sc = le16_to_cpu(hdr->seq_ctrl);
1018 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
15b1687c
WT		 1019 IWL_ERR(priv,
1020 "BUG_ON idx doesn't match seq control"
1021 " idx=%d, seq_idx=%d, seq=%d\n",
e532fa0e
RR		 1022 idx, SEQ_TO_SN(sc),
1023 hdr->seq_ctrl);
1024 return -1;
1025 }
1026
e1623446 1027 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
e532fa0e
RR		 1028 i, idx, SEQ_TO_SN(sc));
1029
1030 sh = idx - start;
1031 if (sh > 64) {
1032 sh = (start - idx) + 0xff;
1033 bitmap = bitmap << sh;
1034 sh = 0;
1035 start = idx;
1036 } else if (sh < -64)
1037 sh = 0xff - (start - idx);
1038 else if (sh < 0) {
1039 sh = start - idx;
1040 start = idx;
1041 bitmap = bitmap << sh;
1042 sh = 0;
1043 }
4aa41f12 1044 bitmap |= 1ULL << sh;
e1623446 1045 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
4aa41f12 1046 start, (unsigned long long)bitmap);
e532fa0e
RR		 1047 }
1048
1049 agg->bitmap = bitmap;
1050 agg->start_idx = start;
e1623446 1051 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
e532fa0e
RR		 1052 agg->frame_count, agg->start_idx,
1053 (unsigned long long)agg->bitmap);
1054
1055 if (bitmap)
1056 agg->wait_for_ba = 1;
1057 }
1058 return 0;
1059}
1060
1061static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1062 struct iwl_rx_mem_buffer *rxb)
1063{
2f301227 1064 struct iwl_rx_packet *pkt = rxb_addr(rxb);
e532fa0e
RR		 1065 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1066 int txq_id = SEQ_TO_QUEUE(sequence);
1067 int index = SEQ_TO_INDEX(sequence);
1068 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1069 struct ieee80211_tx_info *info;
1070 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1071 u32 status = le16_to_cpu(tx_resp->status.status);
3fd07a1e
TW		 1072 int tid;
1073 int sta_id;
1074 int freed;
e532fa0e
RR		 1075
1076 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 1077 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
e532fa0e
RR		 1078 "is out of range [0-%d] %d %d\n", txq_id,
1079 index, txq->q.n_bd, txq->q.write_ptr,
1080 txq->q.read_ptr);
1081 return;
1082 }
1083
1084 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1085 memset(&info->status, 0, sizeof(info->status));
1086
3fd07a1e
TW		 1087 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1088 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
e532fa0e
RR		 1089
1090 if (txq->sched_retry) {
1091 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1092 struct iwl_ht_agg *agg = NULL;
1093
e532fa0e
RR		 1094 agg = &priv->stations[sta_id].tid[tid].agg;
1095
25a6572c 1096 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1097
3235427e
RR		 1098 /* check if BAR is needed */
1099 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1100 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1101
1102 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
e532fa0e 1103 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
e1623446 1104 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
3fd07a1e
TW		 1105 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1106 scd_ssn , index, txq_id, txq->swq_id);
1107
17b88929 1108 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1109 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1110
3fd07a1e
TW		 1111 if (priv->mac80211_registered &&
1112 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1113 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
e532fa0e 1114 if (agg->state == IWL_AGG_OFF)
e4e72fb4 1115 iwl_wake_queue(priv, txq_id);
e532fa0e 1116 else
e4e72fb4 1117 iwl_wake_queue(priv, txq->swq_id);
e532fa0e 1118 }
e532fa0e
RR		 1119 }
1120 } else {
3fd07a1e
TW		 1121 BUG_ON(txq_id != txq->swq_id);
1122
e6a9854b 1123 info->status.rates[0].count = tx_resp->failure_frame + 1;
c397bf15 1124 info->flags |= iwl_tx_status_to_mac80211(status);
e7d326ac 1125 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1126 le32_to_cpu(tx_resp->rate_n_flags),
1127 info);
1128
e1623446 1129 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
3fd07a1e
TW		 1130 "0x%x retries %d\n",
1131 txq_id,
1132 iwl_get_tx_fail_reason(status), status,
1133 le32_to_cpu(tx_resp->rate_n_flags),
1134 tx_resp->failure_frame);
4f85f5b3 1135
3fd07a1e
TW		 1136 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1137 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
e532fa0e 1138 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 1139
1140 if (priv->mac80211_registered &&
1141 (iwl_queue_space(&txq->q) > txq->q.low_mark))
e4e72fb4 1142 iwl_wake_queue(priv, txq_id);
e532fa0e 1143 }
e532fa0e 1144
3fd07a1e
TW		 1145 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1146 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1147
e532fa0e 1148 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 1149 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
e532fa0e
RR		 1150}
1151
a96a27f9 1152/* Currently 5000 is the superset of everything */
e8c00dcb 1153u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
c1adf9fb
GG		 1154{
1155 return len;
1156}
1157
672639de 1158void iwl5000_setup_deferred_work(struct iwl_priv *priv)
203566f3
EG		 1159{
1160 /* in 5000 the tx power calibration is done in uCode */
1161 priv->disable_tx_power_cal = 1;
1162}
1163
672639de 1164void iwl5000_rx_handler_setup(struct iwl_priv *priv)
b600e4e1 1165{
7c616cba
TW		 1166 /* init calibration handlers */
1167 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1168 iwl5000_rx_calib_result;
1169 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1170 iwl5000_rx_calib_complete;
e532fa0e 1171 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1172}
1173
7c616cba 1174
672639de 1175int iwl5000_hw_valid_rtc_data_addr(u32 addr)
87283cc1 1176{
250bdd21 1177 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
87283cc1
RR		 1178 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1179}
1180
fe7a90c2
RR		 1181static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1182{
1183 int ret = 0;
1184 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1185 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1186 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1187
1188 if ((rxon1->flags == rxon2->flags) &&
1189 (rxon1->filter_flags == rxon2->filter_flags) &&
1190 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1191 (rxon1->ofdm_ht_single_stream_basic_rates ==
1192 rxon2->ofdm_ht_single_stream_basic_rates) &&
1193 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1194 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1195 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1196 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1197 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1198 (rxon1->rx_chain == rxon2->rx_chain) &&
1199 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
e1623446 1200 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
fe7a90c2
RR		 1201 return 0;
1202 }
1203
1204 rxon_assoc.flags = priv->staging_rxon.flags;
1205 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1206 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1207 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1208 rxon_assoc.reserved1 = 0;
1209 rxon_assoc.reserved2 = 0;
1210 rxon_assoc.reserved3 = 0;
1211 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1212 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1213 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1214 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1215 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1216 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1217 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1218 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1219
1220 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1221 sizeof(rxon_assoc), &rxon_assoc, NULL);
1222 if (ret)
1223 return ret;
1224
1225 return ret;
1226}
672639de 1227int iwl5000_send_tx_power(struct iwl_priv *priv)
630fe9b6
TW		 1228{
1229 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
76a2407a 1230 u8 tx_ant_cfg_cmd;
630fe9b6
TW		 1231
1232 /* half dBm need to multiply */
1233 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
ae16fc3c
WYG		 1234
1235 if (priv->tx_power_lmt_in_half_dbm &&
1236 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1237 /*
1238 * For the newer devices which using enhanced/extend tx power
1239 * table in EEPROM, the format is in half dBm. driver need to
1240 * convert to dBm format before report to mac80211.
1241 * By doing so, there is a possibility of 1/2 dBm resolution
1242 * lost. driver will perform "round-up" operation before
1243 * reporting, but it will cause 1/2 dBm tx power over the
1244 * regulatory limit. Perform the checking here, if the
1245 * "tx_power_user_lmt" is higher than EEPROM value (in
1246 * half-dBm format), lower the tx power based on EEPROM
1247 */
1248 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1249 }
853554ac 1250 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6 1251 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
76a2407a
JS		 1252
1253 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1254 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1255 else
1256 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1257
1258 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
630fe9b6
TW		 1259 sizeof(tx_power_cmd), &tx_power_cmd,
1260 NULL);
1261}
1262
672639de 1263void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1264{
1265 /* store temperature from statistics (in Celsius) */
5225640b 1266 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
39b73fb1 1267 iwl_tt_handler(priv);
8f91aecb 1268}
fe7a90c2 1269
62161aef
WYG		 1270static void iwl5150_temperature(struct iwl_priv *priv)
1271{
1272 u32 vt = 0;
1273 s32 offset = iwl_temp_calib_to_offset(priv);
1274
1275 vt = le32_to_cpu(priv->statistics.general.temperature);
1276 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1277 /* now vt hold the temperature in Kelvin */
1278 priv->temperature = KELVIN_TO_CELSIUS(vt);
15993e08 1279 iwl_tt_handler(priv);
62161aef
WYG		 1280}
1281
caab8f1a 1282/* Calc max signal level (dBm) among 3 possible receivers */
e8c00dcb 1283int iwl5000_calc_rssi(struct iwl_priv *priv,
caab8f1a
TW		 1284 struct iwl_rx_phy_res *rx_resp)
1285{
1286 /* data from PHY/DSP regarding signal strength, etc.,
1287 * contents are always there, not configurable by host
1288 */
1289 struct iwl5000_non_cfg_phy *ncphy =
1290 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1291 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1292 u8 agc;
1293
1294 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1295 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1296
1297 /* Find max rssi among 3 possible receivers.
1298 * These values are measured by the digital signal processor (DSP).
1299 * They should stay fairly constant even as the signal strength varies,
1300 * if the radio's automatic gain control (AGC) is working right.
1301 * AGC value (see below) will provide the "interesting" info.
1302 */
1303 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1304 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1305 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1306 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1307 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1308
1309 max_rssi = max_t(u32, rssi_a, rssi_b);
1310 max_rssi = max_t(u32, max_rssi, rssi_c);
1311
e1623446 1312 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
caab8f1a
TW		 1313 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1314
1315 /* dBm = max_rssi dB - agc dB - constant.
1316 * Higher AGC (higher radio gain) means lower signal. */
250bdd21 1317 return max_rssi - agc - IWL49_RSSI_OFFSET;
caab8f1a
TW		 1318}
1319
2f748dec
WYG		 1320static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1321{
1322 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1323 .valid = cpu_to_le32(valid_tx_ant),
1324 };
1325
1326 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1327 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1328 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1329 sizeof(struct iwl_tx_ant_config_cmd),
1330 &tx_ant_cmd);
1331 } else {
1332 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1333 return -EOPNOTSUPP;
1334 }
1335}
1336
1337
cc0f555d
JS		 1338#define IWL5000_UCODE_GET(item) \
1339static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1340 u32 api_ver) \
1341{ \
1342 if (api_ver <= 2) \
1343 return le32_to_cpu(ucode->u.v1.item); \
1344 return le32_to_cpu(ucode->u.v2.item); \
1345}
1346
1347static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1348{
1349 if (api_ver <= 2)
1350 return UCODE_HEADER_SIZE(1);
1351 return UCODE_HEADER_SIZE(2);
1352}
1353
1354static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1355 u32 api_ver)
1356{
1357 if (api_ver <= 2)
1358 return 0;
1359 return le32_to_cpu(ucode->u.v2.build);
1360}
1361
1362static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1363 u32 api_ver)
1364{
1365 if (api_ver <= 2)
1366 return (u8 *) ucode->u.v1.data;
1367 return (u8 *) ucode->u.v2.data;
1368}
1369
1370IWL5000_UCODE_GET(inst_size);
1371IWL5000_UCODE_GET(data_size);
1372IWL5000_UCODE_GET(init_size);
1373IWL5000_UCODE_GET(init_data_size);
1374IWL5000_UCODE_GET(boot_size);
1375
4a56e965
WYG		 1376static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1377{
1378 struct iwl5000_channel_switch_cmd cmd;
1379 const struct iwl_channel_info *ch_info;
1380 struct iwl_host_cmd hcmd = {
1381 .id = REPLY_CHANNEL_SWITCH,
1382 .len = sizeof(cmd),
1383 .flags = CMD_SIZE_HUGE,
1384 .data = &cmd,
1385 };
1386
1387 IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1388 priv->active_rxon.channel, channel);
1389 cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1390 cmd.channel = cpu_to_le16(channel);
0924e519
WYG		 1391 cmd.rxon_flags = priv->staging_rxon.flags;
1392 cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
4a56e965
WYG		 1393 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1394 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1395 if (ch_info)
1396 cmd.expect_beacon = is_channel_radar(ch_info);
1397 else {
1398 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1399 priv->active_rxon.channel, channel);
1400 return -EFAULT;
1401 }
0924e519
WYG		 1402 priv->switch_rxon.channel = cpu_to_le16(channel);
1403 priv->switch_rxon.switch_in_progress = true;
4a56e965
WYG		 1404
1405 return iwl_send_cmd_sync(priv, &hcmd);
1406}
1407
e8c00dcb 1408struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1409 .rxon_assoc = iwl5000_send_rxon_assoc,
e0158e61 1410 .commit_rxon = iwl_commit_rxon,
45823531 1411 .set_rxon_chain = iwl_set_rxon_chain,
2f748dec 1412 .set_tx_ant = iwl5000_send_tx_ant_config,
da8dec29
TW		 1413};
1414
e8c00dcb 1415struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1416 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1417 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1418 .gain_computation = iwl5000_gain_computation,
1419 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1420 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1421 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1422};
1423
cc0f555d
JS		 1424struct iwl_ucode_ops iwl5000_ucode = {
1425 .get_header_size = iwl5000_ucode_get_header_size,
1426 .get_build = iwl5000_ucode_get_build,
1427 .get_inst_size = iwl5000_ucode_get_inst_size,
1428 .get_data_size = iwl5000_ucode_get_data_size,
1429 .get_init_size = iwl5000_ucode_get_init_size,
1430 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1431 .get_boot_size = iwl5000_ucode_get_boot_size,
1432 .get_data = iwl5000_ucode_get_data,
1433};
1434
e8c00dcb 1435struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1436 .set_hw_params = iwl5000_hw_set_hw_params,
7839fc03 1437 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1438 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1439 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1440 .txq_agg_enable = iwl5000_txq_agg_enable,
1441 .txq_agg_disable = iwl5000_txq_agg_disable,
7aaa1d79
SO		 1442 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1443 .txq_free_tfd = iwl_hw_txq_free_tfd,
a8e74e27 1444 .txq_init = iwl_hw_tx_queue_init,
b600e4e1 1445 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1446 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1447 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
b7a79404
RC		 1448 .dump_nic_event_log = iwl_dump_nic_event_log,
1449 .dump_nic_error_log = iwl_dump_nic_error_log,
696bdee3 1450 .dump_csr = iwl_dump_csr,
1b3eb823 1451 .dump_fh = iwl_dump_fh,
dbb983b7 1452 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1453 .init_alive_start = iwl5000_init_alive_start,
1454 .alive_notify = iwl5000_alive_notify,
630fe9b6 1455 .send_tx_power = iwl5000_send_tx_power,
5b9f8cd3 1456 .update_chain_flags = iwl_update_chain_flags,
4a56e965 1457 .set_channel_switch = iwl5000_hw_channel_switch,
30d59260 1458 .apm_ops = {
fadb3582 1459 .init = iwl_apm_init,
d68b603c 1460 .stop = iwl_apm_stop,
5a835353 1461 .config = iwl5000_nic_config,
5b9f8cd3 1462 .set_pwr_src = iwl_set_pwr_src,
30d59260 1463 },
da8dec29 1464 .eeprom_ops = {
25ae3986
TW		 1465 .regulatory_bands = {
1466 EEPROM_5000_REG_BAND_1_CHANNELS,
1467 EEPROM_5000_REG_BAND_2_CHANNELS,
1468 EEPROM_5000_REG_BAND_3_CHANNELS,
1469 EEPROM_5000_REG_BAND_4_CHANNELS,
1470 EEPROM_5000_REG_BAND_5_CHANNELS,
7aafef1c
WYG		 1471 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1472 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
25ae3986 1473 },
da8dec29
TW		 1474 .verify_signature = iwlcore_eeprom_verify_signature,
1475 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1476 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 1477 .calib_version = iwl5000_eeprom_calib_version,
25ae3986 1478 .query_addr = iwl5000_eeprom_query_addr,
da8dec29 1479 },
5bbe233b 1480 .post_associate = iwl_post_associate,
ef850d7c 1481 .isr = iwl_isr_ict,
60690a6a 1482 .config_ap = iwl_config_ap,
62161aef
WYG		 1483 .temp_ops = {
1484 .temperature = iwl5000_temperature,
1485 .set_ct_kill = iwl5000_set_ct_threshold,
1486 },
3459ab5a 1487 .add_bcast_station = iwl_add_bcast_station,
62161aef
WYG		 1488};
1489
1490static struct iwl_lib_ops iwl5150_lib = {
1491 .set_hw_params = iwl5000_hw_set_hw_params,
1492 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1493 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1494 .txq_set_sched = iwl5000_txq_set_sched,
1495 .txq_agg_enable = iwl5000_txq_agg_enable,
1496 .txq_agg_disable = iwl5000_txq_agg_disable,
1497 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1498 .txq_free_tfd = iwl_hw_txq_free_tfd,
1499 .txq_init = iwl_hw_tx_queue_init,
1500 .rx_handler_setup = iwl5000_rx_handler_setup,
1501 .setup_deferred_work = iwl5000_setup_deferred_work,
1502 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
b7a79404
RC		 1503 .dump_nic_event_log = iwl_dump_nic_event_log,
1504 .dump_nic_error_log = iwl_dump_nic_error_log,
696bdee3 1505 .dump_csr = iwl_dump_csr,
62161aef
WYG		 1506 .load_ucode = iwl5000_load_ucode,
1507 .init_alive_start = iwl5000_init_alive_start,
1508 .alive_notify = iwl5000_alive_notify,
1509 .send_tx_power = iwl5000_send_tx_power,
1510 .update_chain_flags = iwl_update_chain_flags,
4a56e965 1511 .set_channel_switch = iwl5000_hw_channel_switch,
62161aef 1512 .apm_ops = {
fadb3582 1513 .init = iwl_apm_init,
d68b603c 1514 .stop = iwl_apm_stop,
62161aef
WYG		 1515 .config = iwl5000_nic_config,
1516 .set_pwr_src = iwl_set_pwr_src,
1517 },
1518 .eeprom_ops = {
1519 .regulatory_bands = {
1520 EEPROM_5000_REG_BAND_1_CHANNELS,
1521 EEPROM_5000_REG_BAND_2_CHANNELS,
1522 EEPROM_5000_REG_BAND_3_CHANNELS,
1523 EEPROM_5000_REG_BAND_4_CHANNELS,
1524 EEPROM_5000_REG_BAND_5_CHANNELS,
7aafef1c
WYG		 1525 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1526 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
62161aef
WYG		 1527 },
1528 .verify_signature = iwlcore_eeprom_verify_signature,
1529 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1530 .release_semaphore = iwlcore_eeprom_release_semaphore,
1531 .calib_version = iwl5000_eeprom_calib_version,
1532 .query_addr = iwl5000_eeprom_query_addr,
1533 },
1534 .post_associate = iwl_post_associate,
ef850d7c 1535 .isr = iwl_isr_ict,
62161aef
WYG		 1536 .config_ap = iwl_config_ap,
1537 .temp_ops = {
1538 .temperature = iwl5150_temperature,
1539 .set_ct_kill = iwl5150_set_ct_threshold,
1540 },
3459ab5a 1541 .add_bcast_station = iwl_add_bcast_station,
da8dec29
TW		 1542};
1543
45d5d805 1544static const struct iwl_ops iwl5000_ops = {
cc0f555d 1545 .ucode = &iwl5000_ucode,
da8dec29
TW		 1546 .lib = &iwl5000_lib,
1547 .hcmd = &iwl5000_hcmd,
1548 .utils = &iwl5000_hcmd_utils,
e932a609 1549 .led = &iwlagn_led_ops,
da8dec29
TW		 1550};
1551
45d5d805 1552static const struct iwl_ops iwl5150_ops = {
cc0f555d 1553 .ucode = &iwl5000_ucode,
62161aef
WYG		 1554 .lib = &iwl5150_lib,
1555 .hcmd = &iwl5000_hcmd,
1556 .utils = &iwl5000_hcmd_utils,
e932a609 1557 .led = &iwlagn_led_ops,
62161aef
WYG		 1558};
1559
cec2d3f3 1560struct iwl_mod_params iwl50_mod_params = {
5a6a256e 1561 .amsdu_size_8K = 1,
3a1081e8 1562 .restart_fw = 1,
5a6a256e
TW		 1563 /* the rest are 0 by default */
1564};
1565
1566
1567struct iwl_cfg iwl5300_agn_cfg = {
1568 .name = "5300AGN",
a0987a8d
RC		 1569 .fw_name_pre = IWL5000_FW_PRE,
1570 .ucode_api_max = IWL5000_UCODE_API_MAX,
1571 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1572 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1573 .ops = &iwl5000_ops,
25ae3986 1574 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1575 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1576 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1577 .num_of_queues = IWL50_NUM_QUEUES,
1578 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1579 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1580 .valid_tx_ant = ANT_ABC,
1581 .valid_rx_ant = ANT_ABC,
fadb3582
BC		 1582 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1583 .set_l0s = true,
1584 .use_bsm = false,
b261793d 1585 .ht_greenfield_support = true,
f2d0d0e2 1586 .led_compensation = 51,
1152dcc2 1587 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1588 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1589 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
5a6a256e
TW		 1590};
1591
ac592574
WYG		 1592struct iwl_cfg iwl5100_bgn_cfg = {
1593 .name = "5100BGN",
a0987a8d
RC		 1594 .fw_name_pre = IWL5000_FW_PRE,
1595 .ucode_api_max = IWL5000_UCODE_API_MAX,
1596 .ucode_api_min = IWL5000_UCODE_API_MIN,
ac592574 1597 .sku = IWL_SKU_G|IWL_SKU_N,
47408639
EK		 1598 .ops = &iwl5000_ops,
1599 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1600 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1601 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1602 .num_of_queues = IWL50_NUM_QUEUES,
1603 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
47408639 1604 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1605 .valid_tx_ant = ANT_B,
1606 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1607 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1608 .set_l0s = true,
1609 .use_bsm = false,
b261793d 1610 .ht_greenfield_support = true,
f2d0d0e2 1611 .led_compensation = 51,
1152dcc2 1612 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1613 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1614 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
47408639
EK		 1615};
1616
1617struct iwl_cfg iwl5100_abg_cfg = {
1618 .name = "5100ABG",
a0987a8d
RC		 1619 .fw_name_pre = IWL5000_FW_PRE,
1620 .ucode_api_max = IWL5000_UCODE_API_MAX,
1621 .ucode_api_min = IWL5000_UCODE_API_MIN,
47408639
EK		 1622 .sku = IWL_SKU_A|IWL_SKU_G,
1623 .ops = &iwl5000_ops,
1624 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1625 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1626 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1627 .num_of_queues = IWL50_NUM_QUEUES,
1628 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
47408639 1629 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1630 .valid_tx_ant = ANT_B,
1631 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1632 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1633 .set_l0s = true,
1634 .use_bsm = false,
f2d0d0e2 1635 .led_compensation = 51,
d8c07e7a 1636 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1637 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
47408639
EK		 1638};
1639
5a6a256e
TW		 1640struct iwl_cfg iwl5100_agn_cfg = {
1641 .name = "5100AGN",
a0987a8d
RC		 1642 .fw_name_pre = IWL5000_FW_PRE,
1643 .ucode_api_max = IWL5000_UCODE_API_MAX,
1644 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1645 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1646 .ops = &iwl5000_ops,
25ae3986 1647 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1648 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1649 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1650 .num_of_queues = IWL50_NUM_QUEUES,
1651 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1652 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1653 .valid_tx_ant = ANT_B,
1654 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1655 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1656 .set_l0s = true,
1657 .use_bsm = false,
b261793d 1658 .ht_greenfield_support = true,
f2d0d0e2 1659 .led_compensation = 51,
1152dcc2 1660 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1661 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1662 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
5a6a256e
TW		 1663};
1664
1665struct iwl_cfg iwl5350_agn_cfg = {
1666 .name = "5350AGN",
a0987a8d
RC		 1667 .fw_name_pre = IWL5000_FW_PRE,
1668 .ucode_api_max = IWL5000_UCODE_API_MAX,
1669 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1670 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1671 .ops = &iwl5000_ops,
25ae3986 1672 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1673 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1674 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
88804e2b
WYG		 1675 .num_of_queues = IWL50_NUM_QUEUES,
1676 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1677 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1678 .valid_tx_ant = ANT_ABC,
1679 .valid_rx_ant = ANT_ABC,
fadb3582
BC		 1680 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1681 .set_l0s = true,
1682 .use_bsm = false,
b261793d 1683 .ht_greenfield_support = true,
f2d0d0e2 1684 .led_compensation = 51,
1152dcc2 1685 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1686 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1687 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
5a6a256e
TW		 1688};
1689
7100e924
TW		 1690struct iwl_cfg iwl5150_agn_cfg = {
1691 .name = "5150AGN",
a0987a8d
RC		 1692 .fw_name_pre = IWL5150_FW_PRE,
1693 .ucode_api_max = IWL5150_UCODE_API_MAX,
1694 .ucode_api_min = IWL5150_UCODE_API_MIN,
7100e924 1695 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
62161aef 1696 .ops = &iwl5150_ops,
7100e924 1697 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
fd63edba
TW		 1698 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1699 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
88804e2b
WYG		 1700 .num_of_queues = IWL50_NUM_QUEUES,
1701 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
7100e924 1702 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1703 .valid_tx_ant = ANT_A,
1704 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1705 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1706 .set_l0s = true,
1707 .use_bsm = false,
b261793d 1708 .ht_greenfield_support = true,
f2d0d0e2 1709 .led_compensation = 51,
1152dcc2 1710 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1711 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1712 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
7100e924
TW		 1713};
1714
ac592574
WYG		 1715struct iwl_cfg iwl5150_abg_cfg = {
1716 .name = "5150ABG",
1717 .fw_name_pre = IWL5150_FW_PRE,
1718 .ucode_api_max = IWL5150_UCODE_API_MAX,
1719 .ucode_api_min = IWL5150_UCODE_API_MIN,
1720 .sku = IWL_SKU_A|IWL_SKU_G,
1721 .ops = &iwl5150_ops,
1722 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1723 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1724 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1725 .num_of_queues = IWL50_NUM_QUEUES,
1726 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1727 .mod_params = &iwl50_mod_params,
1728 .valid_tx_ant = ANT_A,
1729 .valid_rx_ant = ANT_AB,
1730 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1731 .set_l0s = true,
1732 .use_bsm = false,
1733 .led_compensation = 51,
1734 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1735 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
7100e924
TW		 1736};
1737
a0987a8d
RC		 1738MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1739MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
c9f79ed2 1740
4e30cb69 1741module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
5a6a256e
TW		 1742MODULE_PARM_DESC(swcrypto50,
1743 "using software crypto engine (default 0 [hardware])\n");
4e30cb69 1744module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
5a6a256e 1745MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
4e30cb69 1746module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
49779293 1747MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
4e30cb69
WYG		 1748module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1749 int, S_IRUGO);
5a6a256e 1750MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
4e30cb69 1751module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
3a1081e8 1752MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Linux kernel - Deliverables
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