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iwlwifi: 4965 define firmware file name once
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
5a6a256e
TW		 28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/skbuff.h>
33#include <linux/netdevice.h>
34#include <linux/wireless.h>
35#include <net/mac80211.h>
36#include <linux/etherdevice.h>
37#include <asm/unaligned.h>
38
39#include "iwl-eeprom.h"
3e0d4cb1 40#include "iwl-dev.h"
5a6a256e
TW		 41#include "iwl-core.h"
42#include "iwl-io.h"
e26e47d9 43#include "iwl-sta.h"
5a6a256e
TW		 44#include "iwl-helpers.h"
45#include "iwl-5000-hw.h"
46
47#define IWL5000_UCODE_API "-1"
48
4e062f99
JS		 49#define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode"
50
99da1b48
RR		 51static const u16 iwl5000_default_queue_to_tx_fifo[] = {
52 IWL_TX_FIFO_AC3,
53 IWL_TX_FIFO_AC2,
54 IWL_TX_FIFO_AC1,
55 IWL_TX_FIFO_AC0,
56 IWL50_CMD_FIFO_NUM,
57 IWL_TX_FIFO_HCCA_1,
58 IWL_TX_FIFO_HCCA_2
59};
60
46315e01
TW		 61/* FIXME: same implementation as 4965 */
62static int iwl5000_apm_stop_master(struct iwl_priv *priv)
63{
64 int ret = 0;
65 unsigned long flags;
66
67 spin_lock_irqsave(&priv->lock, flags);
68
69 /* set stop master bit */
70 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
71
72 ret = iwl_poll_bit(priv, CSR_RESET,
73 CSR_RESET_REG_FLAG_MASTER_DISABLED,
74 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
75 if (ret < 0)
76 goto out;
77
78out:
79 spin_unlock_irqrestore(&priv->lock, flags);
80 IWL_DEBUG_INFO("stop master\n");
81
82 return ret;
83}
84
85
30d59260
TW		 86static int iwl5000_apm_init(struct iwl_priv *priv)
87{
88 int ret = 0;
89
90 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
92
8f061891
TW		 93 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
94 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
95 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
96
a96a27f9 97 /* Set FH wait threshold to maximum (HW error during stress W/A) */
4c43e0d0
TW		 98 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
99
100 /* enable HAP INTA to move device L1a -> L0s */
101 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
102 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
103
30d59260
TW		 104 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
105
106 /* set "initialization complete" bit to move adapter
107 * D0U* --> D0A* state */
108 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
109
110 /* wait for clock stabilization */
111 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
113 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
114 if (ret < 0) {
115 IWL_DEBUG_INFO("Failed to init the card\n");
116 return ret;
117 }
118
119 ret = iwl_grab_nic_access(priv);
120 if (ret)
121 return ret;
122
123 /* enable DMA */
8f061891 124 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
30d59260
TW		 125
126 udelay(20);
127
8f061891 128 /* disable L1-Active */
30d59260 129 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
8f061891 130 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
30d59260
TW		 131
132 iwl_release_nic_access(priv);
133
134 return ret;
135}
136
a96a27f9 137/* FIXME: this is identical to 4965 */
f118a91d
TW		 138static void iwl5000_apm_stop(struct iwl_priv *priv)
139{
140 unsigned long flags;
141
46315e01 142 iwl5000_apm_stop_master(priv);
f118a91d
TW		 143
144 spin_lock_irqsave(&priv->lock, flags);
145
146 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
147
148 udelay(10);
149
1d3e6c61
MA		 150 /* clear "init complete" move adapter D0A* --> D0U state */
151 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d
TW		 152
153 spin_unlock_irqrestore(&priv->lock, flags);
154}
155
156
7f066108
TW		 157static int iwl5000_apm_reset(struct iwl_priv *priv)
158{
159 int ret = 0;
160 unsigned long flags;
161
46315e01 162 iwl5000_apm_stop_master(priv);
7f066108
TW		 163
164 spin_lock_irqsave(&priv->lock, flags);
165
166 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
167
168 udelay(10);
169
170
171 /* FIXME: put here L1A -L0S w/a */
172
173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
174
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
178
179 /* wait for clock stabilization */
180 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
182 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
183 if (ret < 0) {
184 IWL_DEBUG_INFO("Failed to init the card\n");
185 goto out;
186 }
187
188 ret = iwl_grab_nic_access(priv);
189 if (ret)
190 goto out;
191
192 /* enable DMA */
193 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
194
195 udelay(20);
196
197 /* disable L1-Active */
198 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
199 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
200
201 iwl_release_nic_access(priv);
202
203out:
204 spin_unlock_irqrestore(&priv->lock, flags);
205
206 return ret;
207}
208
209
5a835353 210static void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 211{
212 unsigned long flags;
213 u16 radio_cfg;
e7b63581 214 u16 link;
e86fe9f6
TW		 215
216 spin_lock_irqsave(&priv->lock, flags);
217
e7b63581 218 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
e86fe9f6 219
8f061891 220 /* L1 is enabled by BIOS */
e7b63581 221 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
a96a27f9 222 /* disable L0S disabled L1A enabled */
8f061891
TW		 223 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
224 else
225 /* L0S enabled L1A disabled */
226 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
e86fe9f6
TW		 227
228 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
229
230 /* write radio config values to register */
231 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
232 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
233 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
234 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
235 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
236
237 /* set CSR_HW_CONFIG_REG for uCode use */
238 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
239 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
240 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
241
4c43e0d0
TW		 242 /* W/A : NIC is stuck in a reset state after Early PCIe power off
243 * (PCIe power is lost before PERST# is asserted),
244 * causing ME FW to lose ownership and not being able to obtain it back.
245 */
2d3db679
TW		 246 iwl_grab_nic_access(priv);
247 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
4c43e0d0
TW		 248 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
249 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
2d3db679 250 iwl_release_nic_access(priv);
4c43e0d0 251
e86fe9f6
TW		 252 spin_unlock_irqrestore(&priv->lock, flags);
253}
254
255
256
25ae3986
TW		 257/*
258 * EEPROM
259 */
260static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
261{
262 u16 offset = 0;
263
264 if ((address & INDIRECT_ADDRESS) == 0)
265 return address;
266
267 switch (address & INDIRECT_TYPE_MSK) {
268 case INDIRECT_HOST:
269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
270 break;
271 case INDIRECT_GENERAL:
272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
273 break;
274 case INDIRECT_REGULATORY:
275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
276 break;
277 case INDIRECT_CALIBRATION:
278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
279 break;
280 case INDIRECT_PROCESS_ADJST:
281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
282 break;
283 case INDIRECT_OTHERS:
284 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
285 break;
286 default:
287 IWL_ERROR("illegal indirect type: 0x%X\n",
288 address & INDIRECT_TYPE_MSK);
289 break;
290 }
291
292 /* translate the offset from words to byte */
293 return (address & ADDRESS_MSK) + (offset << 1);
294}
295
0ef2ca67 296static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
f1f69415 297{
f1f69415
TW		 298 struct iwl_eeprom_calib_hdr {
299 u8 version;
300 u8 pa_type;
301 u16 voltage;
302 } *hdr;
303
f1f69415
TW		 304 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
305 EEPROM_5000_CALIB_ALL);
0ef2ca67 306 return hdr->version;
f1f69415
TW		 307
308}
309
33fd5033
EG		 310static void iwl5000_gain_computation(struct iwl_priv *priv,
311 u32 average_noise[NUM_RX_CHAINS],
312 u16 min_average_noise_antenna_i,
313 u32 min_average_noise)
314{
315 int i;
316 s32 delta_g;
317 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
318
319 /* Find Gain Code for the antennas B and C */
320 for (i = 1; i < NUM_RX_CHAINS; i++) {
321 if ((data->disconn_array[i])) {
322 data->delta_gain_code[i] = 0;
323 continue;
324 }
325 delta_g = (1000 * ((s32)average_noise[0] -
326 (s32)average_noise[i])) / 1500;
327 /* bound gain by 2 bits value max, 3rd bit is sign */
328 data->delta_gain_code[i] =
329 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
330
331 if (delta_g < 0)
332 /* set negative sign */
333 data->delta_gain_code[i] |= (1 << 2);
334 }
335
336 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
337 data->delta_gain_code[1], data->delta_gain_code[2]);
338
339 if (!data->radio_write) {
f69f42a6 340 struct iwl_calib_chain_noise_gain_cmd cmd;
33fd5033
EG		 341 memset(&cmd, 0, sizeof(cmd));
342
f69f42a6 343 cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
33fd5033
EG		 344 cmd.delta_gain_1 = data->delta_gain_code[1];
345 cmd.delta_gain_2 = data->delta_gain_code[2];
346 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
347 sizeof(cmd), &cmd, NULL);
348
349 data->radio_write = 1;
350 data->state = IWL_CHAIN_NOISE_CALIBRATED;
351 }
352
353 data->chain_noise_a = 0;
354 data->chain_noise_b = 0;
355 data->chain_noise_c = 0;
356 data->chain_signal_a = 0;
357 data->chain_signal_b = 0;
358 data->chain_signal_c = 0;
359 data->beacon_count = 0;
360}
361
362static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
363{
364 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
365
366 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 367 struct iwl_calib_chain_noise_reset_cmd cmd;
33fd5033
EG		 368
369 memset(&cmd, 0, sizeof(cmd));
f69f42a6 370 cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
33fd5033
EG		 371 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
372 sizeof(cmd), &cmd))
373 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
374 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
375 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
376 }
377}
378
a326a5d0
EG		 379static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
380 __le32 *tx_flags)
381{
e6a9854b
JB		 382 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
383 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
a326a5d0
EG		 384 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
385 else
386 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
387}
388
33fd5033
EG		 389static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
390 .min_nrg_cck = 95,
391 .max_nrg_cck = 0,
392 .auto_corr_min_ofdm = 90,
393 .auto_corr_min_ofdm_mrc = 170,
394 .auto_corr_min_ofdm_x1 = 120,
395 .auto_corr_min_ofdm_mrc_x1 = 240,
396
397 .auto_corr_max_ofdm = 120,
398 .auto_corr_max_ofdm_mrc = 210,
399 .auto_corr_max_ofdm_x1 = 155,
400 .auto_corr_max_ofdm_mrc_x1 = 290,
401
402 .auto_corr_min_cck = 125,
403 .auto_corr_max_cck = 200,
404 .auto_corr_min_cck_mrc = 170,
405 .auto_corr_max_cck_mrc = 400,
406 .nrg_th_cck = 95,
407 .nrg_th_ofdm = 95,
408};
409
25ae3986
TW		 410static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
411 size_t offset)
412{
413 u32 address = eeprom_indirect_address(priv, offset);
414 BUG_ON(address >= priv->cfg->eeprom_size);
415 return &priv->eeprom[address];
416}
417
7c616cba
TW		 418/*
419 * Calibration
420 */
be5d56ed 421static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
7c616cba 422{
f69f42a6 423 u8 data[sizeof(struct iwl_calib_hdr) +
be5d56ed 424 sizeof(struct iwl_cal_xtal_freq)];
f69f42a6 425 struct iwl_calib_cmd *cmd = (struct iwl_calib_cmd *)data;
be5d56ed 426 struct iwl_cal_xtal_freq *xtal = (struct iwl_cal_xtal_freq *)cmd->data;
7c616cba
TW		 427 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
428
f69f42a6 429 cmd->hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
be5d56ed
TW		 430 xtal->cap_pin1 = (u8)xtal_calib[0];
431 xtal->cap_pin2 = (u8)xtal_calib[1];
f69f42a6 432 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
be5d56ed 433 data, sizeof(data));
7c616cba
TW		 434}
435
7c616cba
TW		 436static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
437{
f69f42a6 438 struct iwl_calib_cfg_cmd calib_cfg_cmd;
7c616cba
TW		 439 struct iwl_host_cmd cmd = {
440 .id = CALIBRATION_CFG_CMD,
f69f42a6 441 .len = sizeof(struct iwl_calib_cfg_cmd),
7c616cba
TW		 442 .data = &calib_cfg_cmd,
443 };
444
445 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
446 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
447 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
448 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
449 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
450
451 return iwl_send_cmd(priv, &cmd);
452}
453
454static void iwl5000_rx_calib_result(struct iwl_priv *priv,
455 struct iwl_rx_mem_buffer *rxb)
456{
457 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
f69f42a6 458 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
7c616cba 459 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
6e21f2c1 460 int index;
7c616cba
TW		 461
462 /* reduce the size of the length field itself */
463 len -= 4;
464
6e21f2c1
TW		 465 /* Define the order in which the results will be sent to the runtime
466 * uCode. iwl_send_calib_results sends them in a row according to their
467 * index. We sort them here */
7c616cba 468 switch (hdr->op_code) {
f69f42a6
TW		 469 case IWL_PHY_CALIBRATE_LO_CMD:
470 index = IWL_CALIB_LO;
7c616cba 471 break;
f69f42a6
TW		 472 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
473 index = IWL_CALIB_TX_IQ;
7c616cba 474 break;
f69f42a6
TW		 475 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
476 index = IWL_CALIB_TX_IQ_PERD;
7c616cba 477 break;
201706ac
TW		 478 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
479 index = IWL_CALIB_BASE_BAND;
480 break;
7c616cba
TW		 481 default:
482 IWL_ERROR("Unknown calibration notification %d\n",
483 hdr->op_code);
484 return;
485 }
6e21f2c1 486 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
7c616cba
TW		 487}
488
489static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
490 struct iwl_rx_mem_buffer *rxb)
491{
492 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
493 queue_work(priv->workqueue, &priv->restart);
494}
495
dbb983b7
RR		 496/*
497 * ucode
498 */
499static int iwl5000_load_section(struct iwl_priv *priv,
500 struct fw_desc *image,
501 u32 dst_addr)
502{
503 int ret = 0;
504 unsigned long flags;
505
506 dma_addr_t phy_addr = image->p_addr;
507 u32 byte_cnt = image->len;
508
509 spin_lock_irqsave(&priv->lock, flags);
510 ret = iwl_grab_nic_access(priv);
511 if (ret) {
512 spin_unlock_irqrestore(&priv->lock, flags);
513 return ret;
514 }
515
516 iwl_write_direct32(priv,
517 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
518 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
519
520 iwl_write_direct32(priv,
521 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
522
523 iwl_write_direct32(priv,
524 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
525 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
526
dbb983b7 527 iwl_write_direct32(priv,
f0b9f5cb 528 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
499b1883 529 (iwl_get_dma_hi_addr(phy_addr)
f0b9f5cb
TW		 530 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
531
dbb983b7
RR		 532 iwl_write_direct32(priv,
533 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
534 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
535 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
536 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
537
538 iwl_write_direct32(priv,
539 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
540 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
9c80c502 541 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
dbb983b7
RR		 542 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
543
544 iwl_release_nic_access(priv);
545 spin_unlock_irqrestore(&priv->lock, flags);
546 return 0;
547}
548
549static int iwl5000_load_given_ucode(struct iwl_priv *priv,
550 struct fw_desc *inst_image,
551 struct fw_desc *data_image)
552{
553 int ret = 0;
554
9c80c502 555 ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND);
dbb983b7
RR		 556 if (ret)
557 return ret;
558
559 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
560 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
9c80c502 561 priv->ucode_write_complete, 5 * HZ);
dbb983b7
RR		 562 if (ret == -ERESTARTSYS) {
563 IWL_ERROR("Could not load the INST uCode section due "
564 "to interrupt\n");
565 return ret;
566 }
567 if (!ret) {
568 IWL_ERROR("Could not load the INST uCode section\n");
569 return -ETIMEDOUT;
570 }
571
572 priv->ucode_write_complete = 0;
573
574 ret = iwl5000_load_section(
575 priv, data_image, RTC_DATA_LOWER_BOUND);
576 if (ret)
577 return ret;
578
579 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
580
581 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
582 priv->ucode_write_complete, 5 * HZ);
583 if (ret == -ERESTARTSYS) {
584 IWL_ERROR("Could not load the INST uCode section due "
585 "to interrupt\n");
586 return ret;
587 } else if (!ret) {
588 IWL_ERROR("Could not load the DATA uCode section\n");
589 return -ETIMEDOUT;
590 } else
591 ret = 0;
592
593 priv->ucode_write_complete = 0;
594
595 return ret;
596}
597
598static int iwl5000_load_ucode(struct iwl_priv *priv)
599{
600 int ret = 0;
601
602 /* check whether init ucode should be loaded, or rather runtime ucode */
603 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
604 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
605 ret = iwl5000_load_given_ucode(priv,
606 &priv->ucode_init, &priv->ucode_init_data);
607 if (!ret) {
608 IWL_DEBUG_INFO("Init ucode load complete.\n");
609 priv->ucode_type = UCODE_INIT;
610 }
611 } else {
612 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
613 "Loading runtime ucode...\n");
614 ret = iwl5000_load_given_ucode(priv,
615 &priv->ucode_code, &priv->ucode_data);
616 if (!ret) {
617 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
618 priv->ucode_type = UCODE_RT;
619 }
620 }
621
622 return ret;
623}
624
99da1b48
RR		 625static void iwl5000_init_alive_start(struct iwl_priv *priv)
626{
627 int ret = 0;
628
629 /* Check alive response for "valid" sign from uCode */
630 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
631 /* We had an error bringing up the hardware, so take it
632 * all the way back down so we can try again */
633 IWL_DEBUG_INFO("Initialize Alive failed.\n");
634 goto restart;
635 }
636
637 /* initialize uCode was loaded... verify inst image.
638 * This is a paranoid check, because we would not have gotten the
639 * "initialize" alive if code weren't properly loaded. */
640 if (iwl_verify_ucode(priv)) {
641 /* Runtime instruction load was bad;
642 * take it all the way back down so we can try again */
643 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
644 goto restart;
645 }
646
37deb2a0 647 iwl_clear_stations_table(priv);
99da1b48
RR		 648 ret = priv->cfg->ops->lib->alive_notify(priv);
649 if (ret) {
650 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
651 goto restart;
652 }
653
7c616cba 654 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 655 return;
656
657restart:
658 /* real restart (first load init_ucode) */
659 queue_work(priv->workqueue, &priv->restart);
660}
661
662static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
663 int txq_id, u32 index)
664{
665 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
666 (index & 0xff) | (txq_id << 8));
667 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
668}
669
670static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
671 struct iwl_tx_queue *txq,
672 int tx_fifo_id, int scd_retry)
673{
674 int txq_id = txq->q.id;
3fd07a1e 675 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
99da1b48
RR		 676
677 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
678 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
679 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
680 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
681 IWL50_SCD_QUEUE_STTS_REG_MSK);
682
683 txq->sched_retry = scd_retry;
684
685 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
686 active ? "Activate" : "Deactivate",
687 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
688}
689
9636e583
RR		 690static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
691{
692 struct iwl_wimax_coex_cmd coex_cmd;
693
694 memset(&coex_cmd, 0, sizeof(coex_cmd));
695
696 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
697 sizeof(coex_cmd), &coex_cmd);
698}
699
99da1b48
RR		 700static int iwl5000_alive_notify(struct iwl_priv *priv)
701{
702 u32 a;
703 int i = 0;
704 unsigned long flags;
705 int ret;
706
707 spin_lock_irqsave(&priv->lock, flags);
708
709 ret = iwl_grab_nic_access(priv);
710 if (ret) {
711 spin_unlock_irqrestore(&priv->lock, flags);
712 return ret;
713 }
714
715 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
716 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
717 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
718 a += 4)
719 iwl_write_targ_mem(priv, a, 0);
720 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
721 a += 4)
722 iwl_write_targ_mem(priv, a, 0);
723 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
724 iwl_write_targ_mem(priv, a, 0);
725
726 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
4ddbb7d0 727 priv->scd_bc_tbls.dma >> 10);
99da1b48 728 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
4ddbb7d0 729 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
99da1b48
RR		 730 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
731
732 /* initiate the queues */
733 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
734 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
735 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
736 iwl_write_targ_mem(priv, priv->scd_base_addr +
737 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
738 iwl_write_targ_mem(priv, priv->scd_base_addr +
739 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
740 sizeof(u32),
741 ((SCD_WIN_SIZE <<
742 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
743 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
744 ((SCD_FRAME_LIMIT <<
745 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
746 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
747 }
748
749 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 750 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 751
da1bc453
TW		 752 /* Activate all Tx DMA/FIFO channels */
753 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 754
755 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
9c80c502 756
99da1b48
RR		 757 /* map qos queues to fifos one-to-one */
758 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
759 int ac = iwl5000_default_queue_to_tx_fifo[i];
760 iwl_txq_ctx_activate(priv, i);
761 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
762 }
763 /* TODO - need to initialize those FIFOs inside the loop above,
764 * not only mark them as active */
765 iwl_txq_ctx_activate(priv, 4);
766 iwl_txq_ctx_activate(priv, 7);
767 iwl_txq_ctx_activate(priv, 8);
768 iwl_txq_ctx_activate(priv, 9);
769
770 iwl_release_nic_access(priv);
771 spin_unlock_irqrestore(&priv->lock, flags);
772
7c616cba 773
9636e583
RR		 774 iwl5000_send_wimax_coex(priv);
775
be5d56ed
TW		 776 iwl5000_set_Xtal_calib(priv);
777 iwl_send_calib_results(priv);
7c616cba 778
99da1b48
RR		 779 return 0;
780}
781
fdd3e8a4
TW		 782static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
783{
784 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
785 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
786 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
787 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
788 return -EINVAL;
789 }
25ae3986 790
fdd3e8a4 791 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
4ddbb7d0
TW		 792 priv->hw_params.scd_bc_tbls_size =
793 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
fdd3e8a4
TW		 794 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
795 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
796 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
797 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
da154e30 798 priv->hw_params.max_bsm_size = 0;
fdd3e8a4
TW		 799 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
800 BIT(IEEE80211_BAND_5GHZ);
33fd5033 801 priv->hw_params.sens = &iwl5000_sensitivity;
fdd3e8a4
TW		 802
803 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
804 case CSR_HW_REV_TYPE_5100:
5d664a41
TW		 805 priv->hw_params.tx_chains_num = 1;
806 priv->hw_params.rx_chains_num = 2;
807 priv->hw_params.valid_tx_ant = ANT_B;
808 priv->hw_params.valid_rx_ant = ANT_AB;
809 break;
fdd3e8a4
TW		 810 case CSR_HW_REV_TYPE_5150:
811 priv->hw_params.tx_chains_num = 1;
812 priv->hw_params.rx_chains_num = 2;
1179f18d
TW		 813 priv->hw_params.valid_tx_ant = ANT_A;
814 priv->hw_params.valid_rx_ant = ANT_AB;
fdd3e8a4
TW		 815 break;
816 case CSR_HW_REV_TYPE_5300:
817 case CSR_HW_REV_TYPE_5350:
818 priv->hw_params.tx_chains_num = 3;
819 priv->hw_params.rx_chains_num = 3;
1179f18d
TW		 820 priv->hw_params.valid_tx_ant = ANT_ABC;
821 priv->hw_params.valid_rx_ant = ANT_ABC;
fdd3e8a4
TW		 822 break;
823 }
c031bf80
EG		 824
825 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
826 case CSR_HW_REV_TYPE_5100:
827 case CSR_HW_REV_TYPE_5300:
d5d7c584
TW		 828 case CSR_HW_REV_TYPE_5350:
829 /* 5X00 and 5350 wants in Celsius */
c031bf80
EG		 830 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
831 break;
832 case CSR_HW_REV_TYPE_5150:
d5d7c584 833 /* 5150 wants in Kelvin */
c031bf80
EG		 834 priv->hw_params.ct_kill_threshold =
835 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
836 break;
837 }
838
be5d56ed
TW		 839 /* Set initial calibration set */
840 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
841 case CSR_HW_REV_TYPE_5100:
842 case CSR_HW_REV_TYPE_5300:
843 case CSR_HW_REV_TYPE_5350:
844 priv->hw_params.calib_init_cfg =
f69f42a6
TW		 845 BIT(IWL_CALIB_XTAL) |
846 BIT(IWL_CALIB_LO) |
201706ac
TW		 847 BIT(IWL_CALIB_TX_IQ) |
848 BIT(IWL_CALIB_TX_IQ_PERD) |
849 BIT(IWL_CALIB_BASE_BAND);
be5d56ed
TW		 850 break;
851 case CSR_HW_REV_TYPE_5150:
852 priv->hw_params.calib_init_cfg = 0;
853 break;
854 }
855
856
fdd3e8a4
TW		 857 return 0;
858}
d4100dd9 859
7839fc03
EG		 860/**
861 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
862 */
863static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 864 struct iwl_tx_queue *txq,
7839fc03
EG		 865 u16 byte_cnt)
866{
4ddbb7d0 867 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab 868 int write_ptr = txq->q.write_ptr;
7839fc03
EG		 869 int txq_id = txq->q.id;
870 u8 sec_ctl = 0;
127901ab
TW		 871 u8 sta_id = 0;
872 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
873 __le16 bc_ent;
7839fc03 874
127901ab 875 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
7839fc03
EG		 876
877 if (txq_id != IWL_CMD_QUEUE_NUM) {
127901ab 878 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
da99c4b6 879 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 880
881 switch (sec_ctl & TX_CMD_SEC_MSK) {
882 case TX_CMD_SEC_CCM:
883 len += CCMP_MIC_LEN;
884 break;
885 case TX_CMD_SEC_TKIP:
886 len += TKIP_ICV_LEN;
887 break;
888 case TX_CMD_SEC_WEP:
889 len += WEP_IV_LEN + WEP_ICV_LEN;
890 break;
891 }
892 }
893
127901ab 894 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
7839fc03 895
4ddbb7d0 896 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
7839fc03 897
127901ab 898 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 899 scd_bc_tbl[txq_id].
127901ab 900 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
7839fc03
EG		 901}
902
972cf447
TW		 903static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
904 struct iwl_tx_queue *txq)
905{
4ddbb7d0 906 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 907 int txq_id = txq->q.id;
908 int read_ptr = txq->q.read_ptr;
909 u8 sta_id = 0;
910 __le16 bc_ent;
911
912 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
972cf447
TW		 913
914 if (txq_id != IWL_CMD_QUEUE_NUM)
127901ab 915 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
972cf447 916
127901ab 917 bc_ent = cpu_to_le16(1 | (sta_id << 12));
4ddbb7d0 918 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
972cf447 919
127901ab 920 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 921 scd_bc_tbl[txq_id].
127901ab 922 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
972cf447
TW		 923}
924
e26e47d9
TW		 925static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
926 u16 txq_id)
927{
928 u32 tbl_dw_addr;
929 u32 tbl_dw;
930 u16 scd_q2ratid;
931
932 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
933
934 tbl_dw_addr = priv->scd_base_addr +
935 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
936
937 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
938
939 if (txq_id & 0x1)
940 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
941 else
942 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
943
944 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
945
946 return 0;
947}
948static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
949{
950 /* Simply stop the queue, but don't change any configuration;
951 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
952 iwl_write_prph(priv,
953 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
954 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
955 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
956}
957
958static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
959 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
960{
961 unsigned long flags;
962 int ret;
963 u16 ra_tid;
964
9f17b318
TW		 965 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
966 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
967 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
968 txq_id, IWL50_FIRST_AMPDU_QUEUE,
969 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
970 return -EINVAL;
971 }
e26e47d9
TW		 972
973 ra_tid = BUILD_RAxTID(sta_id, tid);
974
975 /* Modify device's station table to Tx this TID */
9f58671e 976 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
e26e47d9
TW		 977
978 spin_lock_irqsave(&priv->lock, flags);
979 ret = iwl_grab_nic_access(priv);
980 if (ret) {
981 spin_unlock_irqrestore(&priv->lock, flags);
982 return ret;
983 }
984
985 /* Stop this Tx queue before configuring it */
986 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
987
988 /* Map receiver-address / traffic-ID to this queue */
989 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
990
991 /* Set this queue as a chain-building queue */
992 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
993
994 /* enable aggregations for the queue */
995 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
996
997 /* Place first TFD at index corresponding to start sequence number.
998 * Assumes that ssn_idx is valid (!= 0xFFF) */
999 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1000 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1001 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1002
1003 /* Set up Tx window size and frame limit for this queue */
1004 iwl_write_targ_mem(priv, priv->scd_base_addr +
1005 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1006 sizeof(u32),
1007 ((SCD_WIN_SIZE <<
1008 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1009 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1010 ((SCD_FRAME_LIMIT <<
1011 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1012 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1013
1014 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1015
1016 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1017 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1018
1019 iwl_release_nic_access(priv);
1020 spin_unlock_irqrestore(&priv->lock, flags);
1021
1022 return 0;
1023}
1024
1025static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1026 u16 ssn_idx, u8 tx_fifo)
1027{
1028 int ret;
1029
9f17b318
TW		 1030 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1031 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1032 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1033 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1034 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
e26e47d9
TW		 1035 return -EINVAL;
1036 }
1037
1038 ret = iwl_grab_nic_access(priv);
1039 if (ret)
1040 return ret;
1041
1042 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1043
1044 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1045
1046 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1047 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1048 /* supposes that ssn_idx is valid (!= 0xFFF) */
1049 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1050
1051 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1052 iwl_txq_ctx_deactivate(priv, txq_id);
1053 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1054
1055 iwl_release_nic_access(priv);
1056
1057 return 0;
1058}
1059
2469bf2e
TW		 1060static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1061{
1062 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1063 memcpy(data, cmd, size);
1064 return size;
1065}
1066
1067
da1bc453 1068/*
a96a27f9 1069 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 1070 * must be called under priv->lock and mac access
1071 */
1072static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 1073{
da1bc453 1074 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 1075}
1076
e532fa0e
RR		 1077
1078static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1079{
3ac7f146 1080 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 1081 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 1082}
1083
1084static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1085 struct iwl_ht_agg *agg,
1086 struct iwl5000_tx_resp *tx_resp,
25a6572c 1087 int txq_id, u16 start_idx)
e532fa0e
RR		 1088{
1089 u16 status;
1090 struct agg_tx_status *frame_status = &tx_resp->status;
1091 struct ieee80211_tx_info *info = NULL;
1092 struct ieee80211_hdr *hdr = NULL;
e7d326ac 1093 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 1094 int i, sh, idx;
e532fa0e
RR		 1095 u16 seq;
1096
1097 if (agg->wait_for_ba)
1098 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1099
1100 agg->frame_count = tx_resp->frame_count;
1101 agg->start_idx = start_idx;
e7d326ac 1102 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 1103 agg->bitmap = 0;
1104
1105 /* # frames attempted by Tx command */
1106 if (agg->frame_count == 1) {
1107 /* Only one frame was attempted; no block-ack will arrive */
1108 status = le16_to_cpu(frame_status[0].status);
25a6572c 1109 idx = start_idx;
e532fa0e
RR		 1110
1111 /* FIXME: code repetition */
1112 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1113 agg->frame_count, agg->start_idx, idx);
1114
1115 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 1116 info->status.rates[0].count = tx_resp->failure_frame + 1;
e532fa0e 1117 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c3056065 1118 info->flags |= iwl_is_tx_success(status) ?
3fd07a1e 1119 IEEE80211_TX_STAT_ACK : 0;
e7d326ac
TW		 1120 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1121
e532fa0e
RR		 1122 /* FIXME: code repetition end */
1123
1124 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1125 status & 0xff, tx_resp->failure_frame);
e7d326ac 1126 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1127
1128 agg->wait_for_ba = 0;
1129 } else {
1130 /* Two or more frames were attempted; expect block-ack */
1131 u64 bitmap = 0;
1132 int start = agg->start_idx;
1133
1134 /* Construct bit-map of pending frames within Tx window */
1135 for (i = 0; i < agg->frame_count; i++) {
1136 u16 sc;
1137 status = le16_to_cpu(frame_status[i].status);
1138 seq = le16_to_cpu(frame_status[i].sequence);
1139 idx = SEQ_TO_INDEX(seq);
1140 txq_id = SEQ_TO_QUEUE(seq);
1141
1142 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1143 AGG_TX_STATE_ABORT_MSK))
1144 continue;
1145
1146 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1147 agg->frame_count, txq_id, idx);
1148
1149 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1150
1151 sc = le16_to_cpu(hdr->seq_ctrl);
1152 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1153 IWL_ERROR("BUG_ON idx doesn't match seq control"
1154 " idx=%d, seq_idx=%d, seq=%d\n",
1155 idx, SEQ_TO_SN(sc),
1156 hdr->seq_ctrl);
1157 return -1;
1158 }
1159
1160 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1161 i, idx, SEQ_TO_SN(sc));
1162
1163 sh = idx - start;
1164 if (sh > 64) {
1165 sh = (start - idx) + 0xff;
1166 bitmap = bitmap << sh;
1167 sh = 0;
1168 start = idx;
1169 } else if (sh < -64)
1170 sh = 0xff - (start - idx);
1171 else if (sh < 0) {
1172 sh = start - idx;
1173 start = idx;
1174 bitmap = bitmap << sh;
1175 sh = 0;
1176 }
4aa41f12
EG		 1177 bitmap |= 1ULL << sh;
1178 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1179 start, (unsigned long long)bitmap);
e532fa0e
RR		 1180 }
1181
1182 agg->bitmap = bitmap;
1183 agg->start_idx = start;
e532fa0e
RR		 1184 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1185 agg->frame_count, agg->start_idx,
1186 (unsigned long long)agg->bitmap);
1187
1188 if (bitmap)
1189 agg->wait_for_ba = 1;
1190 }
1191 return 0;
1192}
1193
1194static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1195 struct iwl_rx_mem_buffer *rxb)
1196{
1197 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1198 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1199 int txq_id = SEQ_TO_QUEUE(sequence);
1200 int index = SEQ_TO_INDEX(sequence);
1201 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1202 struct ieee80211_tx_info *info;
1203 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1204 u32 status = le16_to_cpu(tx_resp->status.status);
3fd07a1e
TW		 1205 int tid;
1206 int sta_id;
1207 int freed;
e532fa0e
RR		 1208
1209 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1210 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1211 "is out of range [0-%d] %d %d\n", txq_id,
1212 index, txq->q.n_bd, txq->q.write_ptr,
1213 txq->q.read_ptr);
1214 return;
1215 }
1216
1217 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1218 memset(&info->status, 0, sizeof(info->status));
1219
3fd07a1e
TW		 1220 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1221 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
e532fa0e
RR		 1222
1223 if (txq->sched_retry) {
1224 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1225 struct iwl_ht_agg *agg = NULL;
1226
e532fa0e
RR		 1227 agg = &priv->stations[sta_id].tid[tid].agg;
1228
25a6572c 1229 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1230
3235427e
RR		 1231 /* check if BAR is needed */
1232 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1233 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1234
1235 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
e532fa0e 1236 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
3fd07a1e
TW		 1237 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1238 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1239 scd_ssn , index, txq_id, txq->swq_id);
1240
17b88929 1241 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1242 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1243
3fd07a1e
TW		 1244 if (priv->mac80211_registered &&
1245 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1246 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
e532fa0e
RR		 1247 if (agg->state == IWL_AGG_OFF)
1248 ieee80211_wake_queue(priv->hw, txq_id);
1249 else
3fd07a1e
TW		 1250 ieee80211_wake_queue(priv->hw,
1251 txq->swq_id);
e532fa0e 1252 }
e532fa0e
RR		 1253 }
1254 } else {
3fd07a1e
TW		 1255 BUG_ON(txq_id != txq->swq_id);
1256
e6a9854b 1257 info->status.rates[0].count = tx_resp->failure_frame + 1;
3fd07a1e
TW		 1258 info->flags |= iwl_is_tx_success(status) ?
1259 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 1260 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1261 le32_to_cpu(tx_resp->rate_n_flags),
1262 info);
1263
3fd07a1e
TW		 1264 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1265 "0x%x retries %d\n",
1266 txq_id,
1267 iwl_get_tx_fail_reason(status), status,
1268 le32_to_cpu(tx_resp->rate_n_flags),
1269 tx_resp->failure_frame);
4f85f5b3 1270
3fd07a1e
TW		 1271 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1272 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
e532fa0e 1273 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 1274
1275 if (priv->mac80211_registered &&
1276 (iwl_queue_space(&txq->q) > txq->q.low_mark))
e532fa0e 1277 ieee80211_wake_queue(priv->hw, txq_id);
e532fa0e 1278 }
e532fa0e 1279
3fd07a1e
TW		 1280 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1281 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1282
e532fa0e
RR		 1283 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1284 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1285}
1286
a96a27f9 1287/* Currently 5000 is the superset of everything */
c1adf9fb
GG		 1288static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1289{
1290 return len;
1291}
1292
203566f3
EG		 1293static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1294{
1295 /* in 5000 the tx power calibration is done in uCode */
1296 priv->disable_tx_power_cal = 1;
1297}
1298
b600e4e1
RR		 1299static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1300{
7c616cba
TW		 1301 /* init calibration handlers */
1302 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1303 iwl5000_rx_calib_result;
1304 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1305 iwl5000_rx_calib_complete;
e532fa0e 1306 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1307}
1308
7c616cba 1309
87283cc1
RR		 1310static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1311{
1312 return (addr >= RTC_DATA_LOWER_BOUND) &&
1313 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1314}
1315
fe7a90c2
RR		 1316static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1317{
1318 int ret = 0;
1319 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1320 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1321 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1322
1323 if ((rxon1->flags == rxon2->flags) &&
1324 (rxon1->filter_flags == rxon2->filter_flags) &&
1325 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1326 (rxon1->ofdm_ht_single_stream_basic_rates ==
1327 rxon2->ofdm_ht_single_stream_basic_rates) &&
1328 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1329 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1330 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1331 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1332 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1333 (rxon1->rx_chain == rxon2->rx_chain) &&
1334 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1335 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1336 return 0;
1337 }
1338
1339 rxon_assoc.flags = priv->staging_rxon.flags;
1340 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1341 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1342 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1343 rxon_assoc.reserved1 = 0;
1344 rxon_assoc.reserved2 = 0;
1345 rxon_assoc.reserved3 = 0;
1346 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1347 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1348 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1349 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1350 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1351 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1352 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1353 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1354
1355 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1356 sizeof(rxon_assoc), &rxon_assoc, NULL);
1357 if (ret)
1358 return ret;
1359
1360 return ret;
1361}
630fe9b6
TW		 1362static int iwl5000_send_tx_power(struct iwl_priv *priv)
1363{
1364 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1365
1366 /* half dBm need to multiply */
1367 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
853554ac 1368 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6
TW		 1369 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1370 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1371 sizeof(tx_power_cmd), &tx_power_cmd,
1372 NULL);
1373}
1374
5225640b 1375static void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1376{
1377 /* store temperature from statistics (in Celsius) */
5225640b 1378 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
8f91aecb 1379}
fe7a90c2 1380
caab8f1a
TW		 1381/* Calc max signal level (dBm) among 3 possible receivers */
1382static int iwl5000_calc_rssi(struct iwl_priv *priv,
1383 struct iwl_rx_phy_res *rx_resp)
1384{
1385 /* data from PHY/DSP regarding signal strength, etc.,
1386 * contents are always there, not configurable by host
1387 */
1388 struct iwl5000_non_cfg_phy *ncphy =
1389 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1390 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1391 u8 agc;
1392
1393 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1394 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1395
1396 /* Find max rssi among 3 possible receivers.
1397 * These values are measured by the digital signal processor (DSP).
1398 * They should stay fairly constant even as the signal strength varies,
1399 * if the radio's automatic gain control (AGC) is working right.
1400 * AGC value (see below) will provide the "interesting" info.
1401 */
1402 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1403 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1404 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1405 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1406 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1407
1408 max_rssi = max_t(u32, rssi_a, rssi_b);
1409 max_rssi = max_t(u32, max_rssi, rssi_c);
1410
1411 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1412 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1413
1414 /* dBm = max_rssi dB - agc dB - constant.
1415 * Higher AGC (higher radio gain) means lower signal. */
1416 return max_rssi - agc - IWL_RSSI_OFFSET;
1417}
1418
da8dec29 1419static struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1420 .rxon_assoc = iwl5000_send_rxon_assoc,
da8dec29
TW		 1421};
1422
1423static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1424 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1425 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1426 .gain_computation = iwl5000_gain_computation,
1427 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1428 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1429 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1430};
1431
1432static struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1433 .set_hw_params = iwl5000_hw_set_hw_params,
7839fc03 1434 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1435 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1436 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1437 .txq_agg_enable = iwl5000_txq_agg_enable,
1438 .txq_agg_disable = iwl5000_txq_agg_disable,
b600e4e1 1439 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1440 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1441 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
dbb983b7 1442 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1443 .init_alive_start = iwl5000_init_alive_start,
1444 .alive_notify = iwl5000_alive_notify,
630fe9b6 1445 .send_tx_power = iwl5000_send_tx_power,
8f91aecb 1446 .temperature = iwl5000_temperature,
5b9f8cd3 1447 .update_chain_flags = iwl_update_chain_flags,
30d59260
TW		 1448 .apm_ops = {
1449 .init = iwl5000_apm_init,
7f066108 1450 .reset = iwl5000_apm_reset,
f118a91d 1451 .stop = iwl5000_apm_stop,
5a835353 1452 .config = iwl5000_nic_config,
5b9f8cd3 1453 .set_pwr_src = iwl_set_pwr_src,
30d59260 1454 },
da8dec29 1455 .eeprom_ops = {
25ae3986
TW		 1456 .regulatory_bands = {
1457 EEPROM_5000_REG_BAND_1_CHANNELS,
1458 EEPROM_5000_REG_BAND_2_CHANNELS,
1459 EEPROM_5000_REG_BAND_3_CHANNELS,
1460 EEPROM_5000_REG_BAND_4_CHANNELS,
1461 EEPROM_5000_REG_BAND_5_CHANNELS,
1462 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1463 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1464 },
da8dec29
TW		 1465 .verify_signature = iwlcore_eeprom_verify_signature,
1466 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1467 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 1468 .calib_version = iwl5000_eeprom_calib_version,
25ae3986 1469 .query_addr = iwl5000_eeprom_query_addr,
da8dec29
TW		 1470 },
1471};
1472
1473static struct iwl_ops iwl5000_ops = {
1474 .lib = &iwl5000_lib,
1475 .hcmd = &iwl5000_hcmd,
1476 .utils = &iwl5000_hcmd_utils,
1477};
1478
5a6a256e
TW		 1479static struct iwl_mod_params iwl50_mod_params = {
1480 .num_of_queues = IWL50_NUM_QUEUES,
9f17b318 1481 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e
TW		 1482 .enable_qos = 1,
1483 .amsdu_size_8K = 1,
3a1081e8 1484 .restart_fw = 1,
5a6a256e
TW		 1485 /* the rest are 0 by default */
1486};
1487
1488
1489struct iwl_cfg iwl5300_agn_cfg = {
1490 .name = "5300AGN",
4e062f99 1491 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1492 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1493 .ops = &iwl5000_ops,
25ae3986 1494 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1495 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1496 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
5a6a256e
TW		 1497 .mod_params = &iwl50_mod_params,
1498};
1499
47408639
EK		 1500struct iwl_cfg iwl5100_bg_cfg = {
1501 .name = "5100BG",
4e062f99 1502 .fw_name = IWL5000_MODULE_FIRMWARE,
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EK		 1503 .sku = IWL_SKU_G,
1504 .ops = &iwl5000_ops,
1505 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1506 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1507 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
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EK		 1508 .mod_params = &iwl50_mod_params,
1509};
1510
1511struct iwl_cfg iwl5100_abg_cfg = {
1512 .name = "5100ABG",
4e062f99 1513 .fw_name = IWL5000_MODULE_FIRMWARE,
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EK		 1514 .sku = IWL_SKU_A|IWL_SKU_G,
1515 .ops = &iwl5000_ops,
1516 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1517 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1518 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
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EK		 1519 .mod_params = &iwl50_mod_params,
1520};
1521
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TW		 1522struct iwl_cfg iwl5100_agn_cfg = {
1523 .name = "5100AGN",
4e062f99 1524 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1525 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1526 .ops = &iwl5000_ops,
25ae3986 1527 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1528 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1529 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
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TW		 1530 .mod_params = &iwl50_mod_params,
1531};
1532
1533struct iwl_cfg iwl5350_agn_cfg = {
1534 .name = "5350AGN",
4e062f99 1535 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1536 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1537 .ops = &iwl5000_ops,
25ae3986 1538 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
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TW		 1539 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1540 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
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TW		 1541 .mod_params = &iwl50_mod_params,
1542};
1543
4e062f99 1544MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE);
c9f79ed2 1545
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TW		 1546module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1547MODULE_PARM_DESC(disable50,
1548 "manually disable the 50XX radio (default 0 [radio on])");
1549module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1550MODULE_PARM_DESC(swcrypto50,
1551 "using software crypto engine (default 0 [hardware])\n");
1552module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1553MODULE_PARM_DESC(debug50, "50XX debug output mask");
1554module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1555MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1556module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1557MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
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RR		 1558module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1559MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
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TW		 1560module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1561MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
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EK		 1562module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1563MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Linux kernel - Deliverables
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