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wl1251: change psm enabled/disabled info to debug
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
5a6a256e
TW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
5a6a256e
TW		 28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/skbuff.h>
33#include <linux/netdevice.h>
34#include <linux/wireless.h>
35#include <net/mac80211.h>
36#include <linux/etherdevice.h>
37#include <asm/unaligned.h>
38
39#include "iwl-eeprom.h"
3e0d4cb1 40#include "iwl-dev.h"
5a6a256e
TW		 41#include "iwl-core.h"
42#include "iwl-io.h"
e26e47d9 43#include "iwl-sta.h"
5a6a256e
TW		 44#include "iwl-helpers.h"
45#include "iwl-5000-hw.h"
c0bac76a 46#include "iwl-6000-hw.h"
5a6a256e 47
a0987a8d 48/* Highest firmware API version supported */
c9d2fbf3 49#define IWL5000_UCODE_API_MAX 2
39e6d225 50#define IWL5150_UCODE_API_MAX 2
5a6a256e 51
a0987a8d
RC		 52/* Lowest firmware API version supported */
53#define IWL5000_UCODE_API_MIN 1
54#define IWL5150_UCODE_API_MIN 1
55
56#define IWL5000_FW_PRE "iwlwifi-5000-"
57#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
58#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
59
60#define IWL5150_FW_PRE "iwlwifi-5150-"
61#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
62#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
4e062f99 63
99da1b48
RR		 64static const u16 iwl5000_default_queue_to_tx_fifo[] = {
65 IWL_TX_FIFO_AC3,
66 IWL_TX_FIFO_AC2,
67 IWL_TX_FIFO_AC1,
68 IWL_TX_FIFO_AC0,
69 IWL50_CMD_FIFO_NUM,
70 IWL_TX_FIFO_HCCA_1,
71 IWL_TX_FIFO_HCCA_2
72};
73
46315e01
TW		 74/* FIXME: same implementation as 4965 */
75static int iwl5000_apm_stop_master(struct iwl_priv *priv)
76{
46315e01
TW		 77 unsigned long flags;
78
79 spin_lock_irqsave(&priv->lock, flags);
80
81 /* set stop master bit */
82 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
83
febf3370 84 iwl_poll_direct_bit(priv, CSR_RESET,
46315e01 85 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
46315e01 86
46315e01 87 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 88 IWL_DEBUG_INFO(priv, "stop master\n");
46315e01 89
febf3370 90 return 0;
46315e01
TW		 91}
92
93
30d59260
TW		 94static int iwl5000_apm_init(struct iwl_priv *priv)
95{
96 int ret = 0;
97
98 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
99 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
100
8f061891
TW		 101 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
102 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
103 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
104
a96a27f9 105 /* Set FH wait threshold to maximum (HW error during stress W/A) */
4c43e0d0
TW		 106 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
107
108 /* enable HAP INTA to move device L1a -> L0s */
109 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
110 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
111
050681b7
JS		 112 if (priv->cfg->need_pll_cfg)
113 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
30d59260
TW		 114
115 /* set "initialization complete" bit to move adapter
116 * D0U* --> D0A* state */
117 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
118
119 /* wait for clock stabilization */
73d7b5ac
ZY		 120 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
121 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
30d59260 122 if (ret < 0) {
e1623446 123 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
30d59260
TW		 124 return ret;
125 }
126
30d59260 127 /* enable DMA */
8f061891 128 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
30d59260
TW		 129
130 udelay(20);
131
8f061891 132 /* disable L1-Active */
30d59260 133 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
8f061891 134 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
30d59260 135
30d59260
TW		 136 return ret;
137}
138
a96a27f9 139/* FIXME: this is identical to 4965 */
f118a91d
TW		 140static void iwl5000_apm_stop(struct iwl_priv *priv)
141{
142 unsigned long flags;
143
46315e01 144 iwl5000_apm_stop_master(priv);
f118a91d
TW		 145
146 spin_lock_irqsave(&priv->lock, flags);
147
148 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
149
150 udelay(10);
151
1d3e6c61
MA		 152 /* clear "init complete" move adapter D0A* --> D0U state */
153 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d
TW		 154
155 spin_unlock_irqrestore(&priv->lock, flags);
156}
157
158
7f066108
TW		 159static int iwl5000_apm_reset(struct iwl_priv *priv)
160{
161 int ret = 0;
7f066108 162
46315e01 163 iwl5000_apm_stop_master(priv);
7f066108 164
7f066108
TW		 165 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
166
167 udelay(10);
168
169
170 /* FIXME: put here L1A -L0S w/a */
171
050681b7
JS		 172 if (priv->cfg->need_pll_cfg)
173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
7f066108
TW		 174
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
178
179 /* wait for clock stabilization */
73d7b5ac
ZY		 180 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
7f066108 182 if (ret < 0) {
e1623446 183 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
7f066108
TW		 184 goto out;
185 }
186
7f066108
TW		 187 /* enable DMA */
188 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
189
190 udelay(20);
191
192 /* disable L1-Active */
193 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
194 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
7f066108 195out:
7f066108
TW		 196
197 return ret;
198}
199
200
5a835353 201static void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 202{
203 unsigned long flags;
204 u16 radio_cfg;
3fdb68de 205 u16 lctl;
e86fe9f6
TW		 206
207 spin_lock_irqsave(&priv->lock, flags);
208
3fdb68de 209 lctl = iwl_pcie_link_ctl(priv);
e86fe9f6 210
3fdb68de
TW		 211 /* HW bug W/A */
212 /* L1-ASPM is enabled by BIOS */
213 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
214 /* L1-APSM enabled: disable L0S */
8f061891
TW		 215 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
216 else
3fdb68de 217 /* L1-ASPM disabled: enable L0S */
8f061891 218 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
e86fe9f6
TW		 219
220 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
221
222 /* write radio config values to register */
223 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
224 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
225 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
226 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
227 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
228
229 /* set CSR_HW_CONFIG_REG for uCode use */
230 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
231 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
232 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
233
4c43e0d0
TW		 234 /* W/A : NIC is stuck in a reset state after Early PCIe power off
235 * (PCIe power is lost before PERST# is asserted),
236 * causing ME FW to lose ownership and not being able to obtain it back.
237 */
2d3db679 238 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
4c43e0d0
TW		 239 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
240 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
241
e86fe9f6
TW		 242 spin_unlock_irqrestore(&priv->lock, flags);
243}
244
245
246
25ae3986
TW		 247/*
248 * EEPROM
249 */
250static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
251{
252 u16 offset = 0;
253
254 if ((address & INDIRECT_ADDRESS) == 0)
255 return address;
256
257 switch (address & INDIRECT_TYPE_MSK) {
258 case INDIRECT_HOST:
259 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
260 break;
261 case INDIRECT_GENERAL:
262 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
263 break;
264 case INDIRECT_REGULATORY:
265 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
266 break;
267 case INDIRECT_CALIBRATION:
268 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
269 break;
270 case INDIRECT_PROCESS_ADJST:
271 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
272 break;
273 case INDIRECT_OTHERS:
274 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
275 break;
276 default:
15b1687c 277 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
25ae3986
TW		 278 address & INDIRECT_TYPE_MSK);
279 break;
280 }
281
282 /* translate the offset from words to byte */
283 return (address & ADDRESS_MSK) + (offset << 1);
284}
285
0ef2ca67 286static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
f1f69415 287{
f1f69415
TW		 288 struct iwl_eeprom_calib_hdr {
289 u8 version;
290 u8 pa_type;
291 u16 voltage;
292 } *hdr;
293
f1f69415
TW		 294 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
295 EEPROM_5000_CALIB_ALL);
0ef2ca67 296 return hdr->version;
f1f69415
TW		 297
298}
299
33fd5033
EG		 300static void iwl5000_gain_computation(struct iwl_priv *priv,
301 u32 average_noise[NUM_RX_CHAINS],
302 u16 min_average_noise_antenna_i,
303 u32 min_average_noise)
304{
305 int i;
306 s32 delta_g;
307 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
308
309 /* Find Gain Code for the antennas B and C */
310 for (i = 1; i < NUM_RX_CHAINS; i++) {
311 if ((data->disconn_array[i])) {
312 data->delta_gain_code[i] = 0;
313 continue;
314 }
315 delta_g = (1000 * ((s32)average_noise[0] -
316 (s32)average_noise[i])) / 1500;
317 /* bound gain by 2 bits value max, 3rd bit is sign */
318 data->delta_gain_code[i] =
319 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
320
321 if (delta_g < 0)
322 /* set negative sign */
323 data->delta_gain_code[i] |= (1 << 2);
324 }
325
e1623446 326 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
33fd5033
EG		 327 data->delta_gain_code[1], data->delta_gain_code[2]);
328
329 if (!data->radio_write) {
f69f42a6 330 struct iwl_calib_chain_noise_gain_cmd cmd;
0d950d84 331
33fd5033
EG		 332 memset(&cmd, 0, sizeof(cmd));
333
0d950d84
TW		 334 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
335 cmd.hdr.first_group = 0;
336 cmd.hdr.groups_num = 1;
337 cmd.hdr.data_valid = 1;
33fd5033
EG		 338 cmd.delta_gain_1 = data->delta_gain_code[1];
339 cmd.delta_gain_2 = data->delta_gain_code[2];
340 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
341 sizeof(cmd), &cmd, NULL);
342
343 data->radio_write = 1;
344 data->state = IWL_CHAIN_NOISE_CALIBRATED;
345 }
346
347 data->chain_noise_a = 0;
348 data->chain_noise_b = 0;
349 data->chain_noise_c = 0;
350 data->chain_signal_a = 0;
351 data->chain_signal_b = 0;
352 data->chain_signal_c = 0;
353 data->beacon_count = 0;
354}
355
356static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
357{
358 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
0d950d84 359 int ret;
33fd5033
EG		 360
361 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 362 struct iwl_calib_chain_noise_reset_cmd cmd;
33fd5033 363 memset(&cmd, 0, sizeof(cmd));
0d950d84
TW		 364
365 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
366 cmd.hdr.first_group = 0;
367 cmd.hdr.groups_num = 1;
368 cmd.hdr.data_valid = 1;
369 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
370 sizeof(cmd), &cmd);
371 if (ret)
15b1687c
WT		 372 IWL_ERR(priv,
373 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
33fd5033 374 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
e1623446 375 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
33fd5033
EG		 376 }
377}
378
e8c00dcb 379void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
a326a5d0
EG		 380 __le32 *tx_flags)
381{
e6a9854b
JB		 382 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
383 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
a326a5d0
EG		 384 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
385 else
386 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
387}
388
33fd5033
EG		 389static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
390 .min_nrg_cck = 95,
391 .max_nrg_cck = 0,
392 .auto_corr_min_ofdm = 90,
393 .auto_corr_min_ofdm_mrc = 170,
394 .auto_corr_min_ofdm_x1 = 120,
395 .auto_corr_min_ofdm_mrc_x1 = 240,
396
397 .auto_corr_max_ofdm = 120,
398 .auto_corr_max_ofdm_mrc = 210,
399 .auto_corr_max_ofdm_x1 = 155,
400 .auto_corr_max_ofdm_mrc_x1 = 290,
401
402 .auto_corr_min_cck = 125,
403 .auto_corr_max_cck = 200,
404 .auto_corr_min_cck_mrc = 170,
405 .auto_corr_max_cck_mrc = 400,
406 .nrg_th_cck = 95,
407 .nrg_th_ofdm = 95,
408};
409
25ae3986
TW		 410static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
411 size_t offset)
412{
413 u32 address = eeprom_indirect_address(priv, offset);
414 BUG_ON(address >= priv->cfg->eeprom_size);
415 return &priv->eeprom[address];
416}
417
62161aef 418static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
339afc89 419{
62161aef
WYG		 420 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
421 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) -
422 iwl_temp_calib_to_offset(priv);
423
424 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
425}
426
427static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
428{
429 /* want Celsius */
430 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
339afc89
TW		 431}
432
7c616cba
TW		 433/*
434 * Calibration
435 */
be5d56ed 436static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
7c616cba 437{
0d950d84 438 struct iwl_calib_xtal_freq_cmd cmd;
7c616cba
TW		 439 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
440
0d950d84
TW		 441 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
442 cmd.hdr.first_group = 0;
443 cmd.hdr.groups_num = 1;
444 cmd.hdr.data_valid = 1;
445 cmd.cap_pin1 = (u8)xtal_calib[0];
446 cmd.cap_pin2 = (u8)xtal_calib[1];
f69f42a6 447 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
0d950d84 448 (u8 *)&cmd, sizeof(cmd));
7c616cba
TW		 449}
450
7c616cba
TW		 451static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
452{
f69f42a6 453 struct iwl_calib_cfg_cmd calib_cfg_cmd;
7c616cba
TW		 454 struct iwl_host_cmd cmd = {
455 .id = CALIBRATION_CFG_CMD,
f69f42a6 456 .len = sizeof(struct iwl_calib_cfg_cmd),
7c616cba
TW		 457 .data = &calib_cfg_cmd,
458 };
459
460 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
461 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
462 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
463 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
464 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
465
466 return iwl_send_cmd(priv, &cmd);
467}
468
469static void iwl5000_rx_calib_result(struct iwl_priv *priv,
470 struct iwl_rx_mem_buffer *rxb)
471{
472 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
f69f42a6 473 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
7c616cba 474 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
6e21f2c1 475 int index;
7c616cba
TW		 476
477 /* reduce the size of the length field itself */
478 len -= 4;
479
6e21f2c1
TW		 480 /* Define the order in which the results will be sent to the runtime
481 * uCode. iwl_send_calib_results sends them in a row according to their
482 * index. We sort them here */
7c616cba 483 switch (hdr->op_code) {
819500c5
TW		 484 case IWL_PHY_CALIBRATE_DC_CMD:
485 index = IWL_CALIB_DC;
486 break;
f69f42a6
TW		 487 case IWL_PHY_CALIBRATE_LO_CMD:
488 index = IWL_CALIB_LO;
7c616cba 489 break;
f69f42a6
TW		 490 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
491 index = IWL_CALIB_TX_IQ;
7c616cba 492 break;
f69f42a6
TW		 493 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
494 index = IWL_CALIB_TX_IQ_PERD;
7c616cba 495 break;
201706ac
TW		 496 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
497 index = IWL_CALIB_BASE_BAND;
498 break;
7c616cba 499 default:
15b1687c 500 IWL_ERR(priv, "Unknown calibration notification %d\n",
7c616cba
TW		 501 hdr->op_code);
502 return;
503 }
6e21f2c1 504 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
7c616cba
TW		 505}
506
507static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
508 struct iwl_rx_mem_buffer *rxb)
509{
e1623446 510 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
7c616cba
TW		 511 queue_work(priv->workqueue, &priv->restart);
512}
513
dbb983b7
RR		 514/*
515 * ucode
516 */
517static int iwl5000_load_section(struct iwl_priv *priv,
518 struct fw_desc *image,
519 u32 dst_addr)
520{
dbb983b7
RR		 521 dma_addr_t phy_addr = image->p_addr;
522 u32 byte_cnt = image->len;
523
dbb983b7
RR		 524 iwl_write_direct32(priv,
525 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
526 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
527
528 iwl_write_direct32(priv,
529 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
530
531 iwl_write_direct32(priv,
532 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
533 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
534
dbb983b7 535 iwl_write_direct32(priv,
f0b9f5cb 536 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
499b1883 537 (iwl_get_dma_hi_addr(phy_addr)
f0b9f5cb
TW		 538 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
539
dbb983b7
RR		 540 iwl_write_direct32(priv,
541 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
542 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
543 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
544 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
545
546 iwl_write_direct32(priv,
547 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
548 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
9c80c502 549 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
dbb983b7
RR		 550 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
551
dbb983b7
RR		 552 return 0;
553}
554
555static int iwl5000_load_given_ucode(struct iwl_priv *priv,
556 struct fw_desc *inst_image,
557 struct fw_desc *data_image)
558{
559 int ret = 0;
560
250bdd21
SO		 561 ret = iwl5000_load_section(priv, inst_image,
562 IWL50_RTC_INST_LOWER_BOUND);
dbb983b7
RR		 563 if (ret)
564 return ret;
565
e1623446 566 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
dbb983b7 567 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
9c80c502 568 priv->ucode_write_complete, 5 * HZ);
dbb983b7 569 if (ret == -ERESTARTSYS) {
15b1687c 570 IWL_ERR(priv, "Could not load the INST uCode section due "
dbb983b7
RR		 571 "to interrupt\n");
572 return ret;
573 }
574 if (!ret) {
15b1687c 575 IWL_ERR(priv, "Could not load the INST uCode section\n");
dbb983b7
RR		 576 return -ETIMEDOUT;
577 }
578
579 priv->ucode_write_complete = 0;
580
581 ret = iwl5000_load_section(
250bdd21 582 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
dbb983b7
RR		 583 if (ret)
584 return ret;
585
e1623446 586 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
dbb983b7
RR		 587
588 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
589 priv->ucode_write_complete, 5 * HZ);
590 if (ret == -ERESTARTSYS) {
15b1687c 591 IWL_ERR(priv, "Could not load the INST uCode section due "
dbb983b7
RR		 592 "to interrupt\n");
593 return ret;
594 } else if (!ret) {
15b1687c 595 IWL_ERR(priv, "Could not load the DATA uCode section\n");
dbb983b7
RR		 596 return -ETIMEDOUT;
597 } else
598 ret = 0;
599
600 priv->ucode_write_complete = 0;
601
602 return ret;
603}
604
605static int iwl5000_load_ucode(struct iwl_priv *priv)
606{
607 int ret = 0;
608
609 /* check whether init ucode should be loaded, or rather runtime ucode */
610 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
e1623446 611 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
dbb983b7
RR		 612 ret = iwl5000_load_given_ucode(priv,
613 &priv->ucode_init, &priv->ucode_init_data);
614 if (!ret) {
e1623446 615 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
dbb983b7
RR		 616 priv->ucode_type = UCODE_INIT;
617 }
618 } else {
e1623446 619 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
dbb983b7
RR		 620 "Loading runtime ucode...\n");
621 ret = iwl5000_load_given_ucode(priv,
622 &priv->ucode_code, &priv->ucode_data);
623 if (!ret) {
e1623446 624 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
dbb983b7
RR		 625 priv->ucode_type = UCODE_RT;
626 }
627 }
628
629 return ret;
630}
631
99da1b48
RR		 632static void iwl5000_init_alive_start(struct iwl_priv *priv)
633{
634 int ret = 0;
635
636 /* Check alive response for "valid" sign from uCode */
637 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
638 /* We had an error bringing up the hardware, so take it
639 * all the way back down so we can try again */
e1623446 640 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
99da1b48
RR		 641 goto restart;
642 }
643
644 /* initialize uCode was loaded... verify inst image.
645 * This is a paranoid check, because we would not have gotten the
646 * "initialize" alive if code weren't properly loaded. */
647 if (iwl_verify_ucode(priv)) {
648 /* Runtime instruction load was bad;
649 * take it all the way back down so we can try again */
e1623446 650 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
99da1b48
RR		 651 goto restart;
652 }
653
c587de0b 654 iwl_clear_stations_table(priv);
99da1b48
RR		 655 ret = priv->cfg->ops->lib->alive_notify(priv);
656 if (ret) {
39aadf8c
WT		 657 IWL_WARN(priv,
658 "Could not complete ALIVE transition: %d\n", ret);
99da1b48
RR		 659 goto restart;
660 }
661
7c616cba 662 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 663 return;
664
665restart:
666 /* real restart (first load init_ucode) */
667 queue_work(priv->workqueue, &priv->restart);
668}
669
670static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
671 int txq_id, u32 index)
672{
673 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
674 (index & 0xff) | (txq_id << 8));
675 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
676}
677
678static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
679 struct iwl_tx_queue *txq,
680 int tx_fifo_id, int scd_retry)
681{
682 int txq_id = txq->q.id;
3fd07a1e 683 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
99da1b48
RR		 684
685 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
686 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
687 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
688 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
689 IWL50_SCD_QUEUE_STTS_REG_MSK);
690
691 txq->sched_retry = scd_retry;
692
e1623446 693 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
99da1b48
RR		 694 active ? "Activate" : "Deactivate",
695 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
696}
697
9636e583
RR		 698static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
699{
700 struct iwl_wimax_coex_cmd coex_cmd;
701
702 memset(&coex_cmd, 0, sizeof(coex_cmd));
703
704 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
705 sizeof(coex_cmd), &coex_cmd);
706}
707
99da1b48
RR		 708static int iwl5000_alive_notify(struct iwl_priv *priv)
709{
710 u32 a;
99da1b48 711 unsigned long flags;
31a73fe4 712 int i, chan;
40fc95d5 713 u32 reg_val;
99da1b48
RR		 714
715 spin_lock_irqsave(&priv->lock, flags);
716
99da1b48
RR		 717 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
718 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
719 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
720 a += 4)
721 iwl_write_targ_mem(priv, a, 0);
722 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
723 a += 4)
724 iwl_write_targ_mem(priv, a, 0);
725 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
726 iwl_write_targ_mem(priv, a, 0);
727
728 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
4ddbb7d0 729 priv->scd_bc_tbls.dma >> 10);
31a73fe4
WT		 730
731 /* Enable DMA channel */
732 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
733 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
734 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
735 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
736
40fc95d5
WT		 737 /* Update FH chicken bits */
738 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
739 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
740 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
741
99da1b48 742 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
4ddbb7d0 743 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
99da1b48
RR		 744 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
745
746 /* initiate the queues */
747 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
748 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
749 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
750 iwl_write_targ_mem(priv, priv->scd_base_addr +
751 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
752 iwl_write_targ_mem(priv, priv->scd_base_addr +
753 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
754 sizeof(u32),
755 ((SCD_WIN_SIZE <<
756 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
757 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
758 ((SCD_FRAME_LIMIT <<
759 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
760 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
761 }
762
763 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 764 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 765
da1bc453
TW		 766 /* Activate all Tx DMA/FIFO channels */
767 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 768
769 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
9c80c502 770
99da1b48
RR		 771 /* map qos queues to fifos one-to-one */
772 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
773 int ac = iwl5000_default_queue_to_tx_fifo[i];
774 iwl_txq_ctx_activate(priv, i);
775 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
776 }
777 /* TODO - need to initialize those FIFOs inside the loop above,
778 * not only mark them as active */
779 iwl_txq_ctx_activate(priv, 4);
780 iwl_txq_ctx_activate(priv, 7);
781 iwl_txq_ctx_activate(priv, 8);
782 iwl_txq_ctx_activate(priv, 9);
783
99da1b48
RR		 784 spin_unlock_irqrestore(&priv->lock, flags);
785
7c616cba 786
9636e583
RR		 787 iwl5000_send_wimax_coex(priv);
788
be5d56ed
TW		 789 iwl5000_set_Xtal_calib(priv);
790 iwl_send_calib_results(priv);
7c616cba 791
99da1b48
RR		 792 return 0;
793}
794
fdd3e8a4
TW		 795static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
796{
797 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
798 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
15b1687c
WT		 799 IWL_ERR(priv,
800 "invalid queues_num, should be between %d and %d\n",
801 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
fdd3e8a4
TW		 802 return -EINVAL;
803 }
25ae3986 804
fdd3e8a4 805 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
f3f911d1 806 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
4ddbb7d0
TW		 807 priv->hw_params.scd_bc_tbls_size =
808 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
a8e74e27 809 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
fdd3e8a4
TW		 810 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
811 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
c0bac76a
JS		 812
813 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
814 case CSR_HW_REV_TYPE_6x00:
815 case CSR_HW_REV_TYPE_6x50:
816 priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
817 priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
818 break;
819 default:
820 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
821 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
822 }
823
da154e30 824 priv->hw_params.max_bsm_size = 0;
fdd3e8a4
TW		 825 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
826 BIT(IEEE80211_BAND_5GHZ);
141c43a3
WT		 827 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
828
33fd5033 829 priv->hw_params.sens = &iwl5000_sensitivity;
fdd3e8a4 830
c0bac76a
JS		 831 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
832 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
833 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
834 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
c031bf80 835
62161aef
WYG		 836 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
837 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
c031bf80 838
be5d56ed
TW		 839 /* Set initial calibration set */
840 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
c0bac76a 841 case CSR_HW_REV_TYPE_5150:
be5d56ed 842 priv->hw_params.calib_init_cfg =
c0bac76a 843 BIT(IWL_CALIB_DC) |
f69f42a6 844 BIT(IWL_CALIB_LO) |
201706ac 845 BIT(IWL_CALIB_TX_IQ) |
201706ac 846 BIT(IWL_CALIB_BASE_BAND);
c0bac76a 847
be5d56ed 848 break;
c0bac76a 849 default:
819500c5 850 priv->hw_params.calib_init_cfg =
c0bac76a 851 BIT(IWL_CALIB_XTAL) |
7470d7f5
WT		 852 BIT(IWL_CALIB_LO) |
853 BIT(IWL_CALIB_TX_IQ) |
c0bac76a 854 BIT(IWL_CALIB_TX_IQ_PERD) |
7470d7f5 855 BIT(IWL_CALIB_BASE_BAND);
be5d56ed
TW		 856 break;
857 }
858
fdd3e8a4
TW		 859 return 0;
860}
d4100dd9 861
7839fc03
EG		 862/**
863 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
864 */
865static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 866 struct iwl_tx_queue *txq,
7839fc03
EG		 867 u16 byte_cnt)
868{
4ddbb7d0 869 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab 870 int write_ptr = txq->q.write_ptr;
7839fc03
EG		 871 int txq_id = txq->q.id;
872 u8 sec_ctl = 0;
127901ab
TW		 873 u8 sta_id = 0;
874 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
875 __le16 bc_ent;
7839fc03 876
127901ab 877 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
7839fc03
EG		 878
879 if (txq_id != IWL_CMD_QUEUE_NUM) {
127901ab 880 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
da99c4b6 881 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 882
883 switch (sec_ctl & TX_CMD_SEC_MSK) {
884 case TX_CMD_SEC_CCM:
885 len += CCMP_MIC_LEN;
886 break;
887 case TX_CMD_SEC_TKIP:
888 len += TKIP_ICV_LEN;
889 break;
890 case TX_CMD_SEC_WEP:
891 len += WEP_IV_LEN + WEP_ICV_LEN;
892 break;
893 }
894 }
895
127901ab 896 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
7839fc03 897
4ddbb7d0 898 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
7839fc03 899
127901ab 900 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 901 scd_bc_tbl[txq_id].
127901ab 902 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
7839fc03
EG		 903}
904
972cf447
TW		 905static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
906 struct iwl_tx_queue *txq)
907{
4ddbb7d0 908 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 909 int txq_id = txq->q.id;
910 int read_ptr = txq->q.read_ptr;
911 u8 sta_id = 0;
912 __le16 bc_ent;
913
914 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
972cf447
TW		 915
916 if (txq_id != IWL_CMD_QUEUE_NUM)
127901ab 917 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
972cf447 918
127901ab 919 bc_ent = cpu_to_le16(1 | (sta_id << 12));
4ddbb7d0 920 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
972cf447 921
127901ab 922 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 923 scd_bc_tbl[txq_id].
127901ab 924 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
972cf447
TW		 925}
926
e26e47d9
TW		 927static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
928 u16 txq_id)
929{
930 u32 tbl_dw_addr;
931 u32 tbl_dw;
932 u16 scd_q2ratid;
933
934 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
935
936 tbl_dw_addr = priv->scd_base_addr +
937 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
938
939 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
940
941 if (txq_id & 0x1)
942 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
943 else
944 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
945
946 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
947
948 return 0;
949}
950static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
951{
952 /* Simply stop the queue, but don't change any configuration;
953 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
954 iwl_write_prph(priv,
955 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
956 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
957 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
958}
959
960static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
961 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
962{
963 unsigned long flags;
e26e47d9
TW		 964 u16 ra_tid;
965
9f17b318
TW		 966 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
967 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
39aadf8c
WT		 968 IWL_WARN(priv,
969 "queue number out of range: %d, must be %d to %d\n",
9f17b318
TW		 970 txq_id, IWL50_FIRST_AMPDU_QUEUE,
971 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
972 return -EINVAL;
973 }
e26e47d9
TW		 974
975 ra_tid = BUILD_RAxTID(sta_id, tid);
976
977 /* Modify device's station table to Tx this TID */
9f58671e 978 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
e26e47d9
TW		 979
980 spin_lock_irqsave(&priv->lock, flags);
e26e47d9
TW		 981
982 /* Stop this Tx queue before configuring it */
983 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
984
985 /* Map receiver-address / traffic-ID to this queue */
986 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
987
988 /* Set this queue as a chain-building queue */
989 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
990
991 /* enable aggregations for the queue */
992 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
993
994 /* Place first TFD at index corresponding to start sequence number.
995 * Assumes that ssn_idx is valid (!= 0xFFF) */
996 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
997 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
998 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
999
1000 /* Set up Tx window size and frame limit for this queue */
1001 iwl_write_targ_mem(priv, priv->scd_base_addr +
1002 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1003 sizeof(u32),
1004 ((SCD_WIN_SIZE <<
1005 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1006 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1007 ((SCD_FRAME_LIMIT <<
1008 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1009 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1010
1011 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1012
1013 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1014 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1015
e26e47d9
TW		 1016 spin_unlock_irqrestore(&priv->lock, flags);
1017
1018 return 0;
1019}
1020
1021static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1022 u16 ssn_idx, u8 tx_fifo)
1023{
9f17b318
TW		 1024 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1025 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
a2f1cbeb 1026 IWL_ERR(priv,
39aadf8c 1027 "queue number out of range: %d, must be %d to %d\n",
9f17b318
TW		 1028 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1029 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
e26e47d9
TW		 1030 return -EINVAL;
1031 }
1032
e26e47d9
TW		 1033 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1034
1035 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1036
1037 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1038 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1039 /* supposes that ssn_idx is valid (!= 0xFFF) */
1040 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1041
1042 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1043 iwl_txq_ctx_deactivate(priv, txq_id);
1044 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1045
e26e47d9
TW		 1046 return 0;
1047}
1048
e8c00dcb 1049u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2469bf2e
TW		 1050{
1051 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
c587de0b
TW		 1052 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1053 memcpy(addsta, cmd, size);
1054 /* resrved in 5000 */
1055 addsta->rate_n_flags = cpu_to_le16(0);
2469bf2e
TW		 1056 return size;
1057}
1058
1059
da1bc453 1060/*
a96a27f9 1061 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 1062 * must be called under priv->lock and mac access
1063 */
1064static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 1065{
da1bc453 1066 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 1067}
1068
e532fa0e
RR		 1069
1070static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1071{
3ac7f146 1072 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 1073 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 1074}
1075
1076static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1077 struct iwl_ht_agg *agg,
1078 struct iwl5000_tx_resp *tx_resp,
25a6572c 1079 int txq_id, u16 start_idx)
e532fa0e
RR		 1080{
1081 u16 status;
1082 struct agg_tx_status *frame_status = &tx_resp->status;
1083 struct ieee80211_tx_info *info = NULL;
1084 struct ieee80211_hdr *hdr = NULL;
e7d326ac 1085 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 1086 int i, sh, idx;
e532fa0e
RR		 1087 u16 seq;
1088
1089 if (agg->wait_for_ba)
e1623446 1090 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
e532fa0e
RR		 1091
1092 agg->frame_count = tx_resp->frame_count;
1093 agg->start_idx = start_idx;
e7d326ac 1094 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 1095 agg->bitmap = 0;
1096
1097 /* # frames attempted by Tx command */
1098 if (agg->frame_count == 1) {
1099 /* Only one frame was attempted; no block-ack will arrive */
1100 status = le16_to_cpu(frame_status[0].status);
25a6572c 1101 idx = start_idx;
e532fa0e
RR		 1102
1103 /* FIXME: code repetition */
e1623446 1104 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
e532fa0e
RR		 1105 agg->frame_count, agg->start_idx, idx);
1106
1107 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 1108 info->status.rates[0].count = tx_resp->failure_frame + 1;
e532fa0e 1109 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c3056065 1110 info->flags |= iwl_is_tx_success(status) ?
3fd07a1e 1111 IEEE80211_TX_STAT_ACK : 0;
e7d326ac
TW		 1112 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1113
e532fa0e
RR		 1114 /* FIXME: code repetition end */
1115
e1623446 1116 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
e532fa0e 1117 status & 0xff, tx_resp->failure_frame);
e1623446 1118 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1119
1120 agg->wait_for_ba = 0;
1121 } else {
1122 /* Two or more frames were attempted; expect block-ack */
1123 u64 bitmap = 0;
1124 int start = agg->start_idx;
1125
1126 /* Construct bit-map of pending frames within Tx window */
1127 for (i = 0; i < agg->frame_count; i++) {
1128 u16 sc;
1129 status = le16_to_cpu(frame_status[i].status);
1130 seq = le16_to_cpu(frame_status[i].sequence);
1131 idx = SEQ_TO_INDEX(seq);
1132 txq_id = SEQ_TO_QUEUE(seq);
1133
1134 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1135 AGG_TX_STATE_ABORT_MSK))
1136 continue;
1137
e1623446 1138 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
e532fa0e
RR		 1139 agg->frame_count, txq_id, idx);
1140
1141 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1142
1143 sc = le16_to_cpu(hdr->seq_ctrl);
1144 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
15b1687c
WT		 1145 IWL_ERR(priv,
1146 "BUG_ON idx doesn't match seq control"
1147 " idx=%d, seq_idx=%d, seq=%d\n",
e532fa0e
RR		 1148 idx, SEQ_TO_SN(sc),
1149 hdr->seq_ctrl);
1150 return -1;
1151 }
1152
e1623446 1153 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
e532fa0e
RR		 1154 i, idx, SEQ_TO_SN(sc));
1155
1156 sh = idx - start;
1157 if (sh > 64) {
1158 sh = (start - idx) + 0xff;
1159 bitmap = bitmap << sh;
1160 sh = 0;
1161 start = idx;
1162 } else if (sh < -64)
1163 sh = 0xff - (start - idx);
1164 else if (sh < 0) {
1165 sh = start - idx;
1166 start = idx;
1167 bitmap = bitmap << sh;
1168 sh = 0;
1169 }
4aa41f12 1170 bitmap |= 1ULL << sh;
e1623446 1171 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
4aa41f12 1172 start, (unsigned long long)bitmap);
e532fa0e
RR		 1173 }
1174
1175 agg->bitmap = bitmap;
1176 agg->start_idx = start;
e1623446 1177 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
e532fa0e
RR		 1178 agg->frame_count, agg->start_idx,
1179 (unsigned long long)agg->bitmap);
1180
1181 if (bitmap)
1182 agg->wait_for_ba = 1;
1183 }
1184 return 0;
1185}
1186
1187static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1188 struct iwl_rx_mem_buffer *rxb)
1189{
1190 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1191 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1192 int txq_id = SEQ_TO_QUEUE(sequence);
1193 int index = SEQ_TO_INDEX(sequence);
1194 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1195 struct ieee80211_tx_info *info;
1196 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1197 u32 status = le16_to_cpu(tx_resp->status.status);
3fd07a1e
TW		 1198 int tid;
1199 int sta_id;
1200 int freed;
e532fa0e
RR		 1201
1202 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 1203 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
e532fa0e
RR		 1204 "is out of range [0-%d] %d %d\n", txq_id,
1205 index, txq->q.n_bd, txq->q.write_ptr,
1206 txq->q.read_ptr);
1207 return;
1208 }
1209
1210 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1211 memset(&info->status, 0, sizeof(info->status));
1212
3fd07a1e
TW		 1213 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1214 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
e532fa0e
RR		 1215
1216 if (txq->sched_retry) {
1217 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1218 struct iwl_ht_agg *agg = NULL;
1219
e532fa0e
RR		 1220 agg = &priv->stations[sta_id].tid[tid].agg;
1221
25a6572c 1222 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1223
3235427e
RR		 1224 /* check if BAR is needed */
1225 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1226 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1227
1228 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
e532fa0e 1229 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
e1623446 1230 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
3fd07a1e
TW		 1231 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1232 scd_ssn , index, txq_id, txq->swq_id);
1233
17b88929 1234 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1235 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1236
3fd07a1e
TW		 1237 if (priv->mac80211_registered &&
1238 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1239 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
e532fa0e 1240 if (agg->state == IWL_AGG_OFF)
e4e72fb4 1241 iwl_wake_queue(priv, txq_id);
e532fa0e 1242 else
e4e72fb4 1243 iwl_wake_queue(priv, txq->swq_id);
e532fa0e 1244 }
e532fa0e
RR		 1245 }
1246 } else {
3fd07a1e
TW		 1247 BUG_ON(txq_id != txq->swq_id);
1248
e6a9854b 1249 info->status.rates[0].count = tx_resp->failure_frame + 1;
3fd07a1e
TW		 1250 info->flags |= iwl_is_tx_success(status) ?
1251 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 1252 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1253 le32_to_cpu(tx_resp->rate_n_flags),
1254 info);
1255
e1623446 1256 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
3fd07a1e
TW		 1257 "0x%x retries %d\n",
1258 txq_id,
1259 iwl_get_tx_fail_reason(status), status,
1260 le32_to_cpu(tx_resp->rate_n_flags),
1261 tx_resp->failure_frame);
4f85f5b3 1262
3fd07a1e
TW		 1263 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1264 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
e532fa0e 1265 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 1266
1267 if (priv->mac80211_registered &&
1268 (iwl_queue_space(&txq->q) > txq->q.low_mark))
e4e72fb4 1269 iwl_wake_queue(priv, txq_id);
e532fa0e 1270 }
e532fa0e 1271
3fd07a1e
TW		 1272 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1273 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1274
e532fa0e 1275 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 1276 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
e532fa0e
RR		 1277}
1278
a96a27f9 1279/* Currently 5000 is the superset of everything */
e8c00dcb 1280u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
c1adf9fb
GG		 1281{
1282 return len;
1283}
1284
203566f3
EG		 1285static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1286{
1287 /* in 5000 the tx power calibration is done in uCode */
1288 priv->disable_tx_power_cal = 1;
1289}
1290
b600e4e1
RR		 1291static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1292{
7c616cba
TW		 1293 /* init calibration handlers */
1294 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1295 iwl5000_rx_calib_result;
1296 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1297 iwl5000_rx_calib_complete;
e532fa0e 1298 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1299}
1300
7c616cba 1301
87283cc1
RR		 1302static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1303{
250bdd21 1304 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
87283cc1
RR		 1305 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1306}
1307
fe7a90c2
RR		 1308static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1309{
1310 int ret = 0;
1311 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1312 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1313 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1314
1315 if ((rxon1->flags == rxon2->flags) &&
1316 (rxon1->filter_flags == rxon2->filter_flags) &&
1317 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1318 (rxon1->ofdm_ht_single_stream_basic_rates ==
1319 rxon2->ofdm_ht_single_stream_basic_rates) &&
1320 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1321 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1322 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1323 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1324 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1325 (rxon1->rx_chain == rxon2->rx_chain) &&
1326 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
e1623446 1327 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
fe7a90c2
RR		 1328 return 0;
1329 }
1330
1331 rxon_assoc.flags = priv->staging_rxon.flags;
1332 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1333 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1334 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1335 rxon_assoc.reserved1 = 0;
1336 rxon_assoc.reserved2 = 0;
1337 rxon_assoc.reserved3 = 0;
1338 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1339 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1340 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1341 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1342 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1343 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1344 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1345 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1346
1347 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1348 sizeof(rxon_assoc), &rxon_assoc, NULL);
1349 if (ret)
1350 return ret;
1351
1352 return ret;
1353}
630fe9b6
TW		 1354static int iwl5000_send_tx_power(struct iwl_priv *priv)
1355{
1356 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
76a2407a 1357 u8 tx_ant_cfg_cmd;
630fe9b6
TW		 1358
1359 /* half dBm need to multiply */
1360 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
853554ac 1361 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6 1362 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
76a2407a
JS		 1363
1364 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1365 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1366 else
1367 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1368
1369 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
630fe9b6
TW		 1370 sizeof(tx_power_cmd), &tx_power_cmd,
1371 NULL);
1372}
1373
5225640b 1374static void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1375{
1376 /* store temperature from statistics (in Celsius) */
5225640b 1377 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
8f91aecb 1378}
fe7a90c2 1379
62161aef
WYG		 1380static void iwl5150_temperature(struct iwl_priv *priv)
1381{
1382 u32 vt = 0;
1383 s32 offset = iwl_temp_calib_to_offset(priv);
1384
1385 vt = le32_to_cpu(priv->statistics.general.temperature);
1386 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1387 /* now vt hold the temperature in Kelvin */
1388 priv->temperature = KELVIN_TO_CELSIUS(vt);
1389}
1390
caab8f1a 1391/* Calc max signal level (dBm) among 3 possible receivers */
e8c00dcb 1392int iwl5000_calc_rssi(struct iwl_priv *priv,
caab8f1a
TW		 1393 struct iwl_rx_phy_res *rx_resp)
1394{
1395 /* data from PHY/DSP regarding signal strength, etc.,
1396 * contents are always there, not configurable by host
1397 */
1398 struct iwl5000_non_cfg_phy *ncphy =
1399 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1400 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1401 u8 agc;
1402
1403 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1404 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1405
1406 /* Find max rssi among 3 possible receivers.
1407 * These values are measured by the digital signal processor (DSP).
1408 * They should stay fairly constant even as the signal strength varies,
1409 * if the radio's automatic gain control (AGC) is working right.
1410 * AGC value (see below) will provide the "interesting" info.
1411 */
1412 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1413 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1414 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1415 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1416 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1417
1418 max_rssi = max_t(u32, rssi_a, rssi_b);
1419 max_rssi = max_t(u32, max_rssi, rssi_c);
1420
e1623446 1421 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
caab8f1a
TW		 1422 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1423
1424 /* dBm = max_rssi dB - agc dB - constant.
1425 * Higher AGC (higher radio gain) means lower signal. */
250bdd21 1426 return max_rssi - agc - IWL49_RSSI_OFFSET;
caab8f1a
TW		 1427}
1428
e8c00dcb 1429struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1430 .rxon_assoc = iwl5000_send_rxon_assoc,
e0158e61 1431 .commit_rxon = iwl_commit_rxon,
45823531 1432 .set_rxon_chain = iwl_set_rxon_chain,
da8dec29
TW		 1433};
1434
e8c00dcb 1435struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1436 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1437 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1438 .gain_computation = iwl5000_gain_computation,
1439 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1440 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1441 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1442};
1443
e8c00dcb 1444struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1445 .set_hw_params = iwl5000_hw_set_hw_params,
7839fc03 1446 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1447 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1448 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1449 .txq_agg_enable = iwl5000_txq_agg_enable,
1450 .txq_agg_disable = iwl5000_txq_agg_disable,
7aaa1d79
SO		 1451 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1452 .txq_free_tfd = iwl_hw_txq_free_tfd,
a8e74e27 1453 .txq_init = iwl_hw_tx_queue_init,
b600e4e1 1454 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1455 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1456 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
dbb983b7 1457 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1458 .init_alive_start = iwl5000_init_alive_start,
1459 .alive_notify = iwl5000_alive_notify,
630fe9b6 1460 .send_tx_power = iwl5000_send_tx_power,
5b9f8cd3 1461 .update_chain_flags = iwl_update_chain_flags,
30d59260
TW		 1462 .apm_ops = {
1463 .init = iwl5000_apm_init,
7f066108 1464 .reset = iwl5000_apm_reset,
f118a91d 1465 .stop = iwl5000_apm_stop,
5a835353 1466 .config = iwl5000_nic_config,
5b9f8cd3 1467 .set_pwr_src = iwl_set_pwr_src,
30d59260 1468 },
da8dec29 1469 .eeprom_ops = {
25ae3986
TW		 1470 .regulatory_bands = {
1471 EEPROM_5000_REG_BAND_1_CHANNELS,
1472 EEPROM_5000_REG_BAND_2_CHANNELS,
1473 EEPROM_5000_REG_BAND_3_CHANNELS,
1474 EEPROM_5000_REG_BAND_4_CHANNELS,
1475 EEPROM_5000_REG_BAND_5_CHANNELS,
1476 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1477 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1478 },
da8dec29
TW		 1479 .verify_signature = iwlcore_eeprom_verify_signature,
1480 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1481 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 1482 .calib_version = iwl5000_eeprom_calib_version,
25ae3986 1483 .query_addr = iwl5000_eeprom_query_addr,
da8dec29 1484 },
5bbe233b 1485 .post_associate = iwl_post_associate,
ef850d7c 1486 .isr = iwl_isr_ict,
60690a6a 1487 .config_ap = iwl_config_ap,
62161aef
WYG		 1488 .temp_ops = {
1489 .temperature = iwl5000_temperature,
1490 .set_ct_kill = iwl5000_set_ct_threshold,
1491 },
1492};
1493
1494static struct iwl_lib_ops iwl5150_lib = {
1495 .set_hw_params = iwl5000_hw_set_hw_params,
1496 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1497 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1498 .txq_set_sched = iwl5000_txq_set_sched,
1499 .txq_agg_enable = iwl5000_txq_agg_enable,
1500 .txq_agg_disable = iwl5000_txq_agg_disable,
1501 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1502 .txq_free_tfd = iwl_hw_txq_free_tfd,
1503 .txq_init = iwl_hw_tx_queue_init,
1504 .rx_handler_setup = iwl5000_rx_handler_setup,
1505 .setup_deferred_work = iwl5000_setup_deferred_work,
1506 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1507 .load_ucode = iwl5000_load_ucode,
1508 .init_alive_start = iwl5000_init_alive_start,
1509 .alive_notify = iwl5000_alive_notify,
1510 .send_tx_power = iwl5000_send_tx_power,
1511 .update_chain_flags = iwl_update_chain_flags,
1512 .apm_ops = {
1513 .init = iwl5000_apm_init,
1514 .reset = iwl5000_apm_reset,
1515 .stop = iwl5000_apm_stop,
1516 .config = iwl5000_nic_config,
1517 .set_pwr_src = iwl_set_pwr_src,
1518 },
1519 .eeprom_ops = {
1520 .regulatory_bands = {
1521 EEPROM_5000_REG_BAND_1_CHANNELS,
1522 EEPROM_5000_REG_BAND_2_CHANNELS,
1523 EEPROM_5000_REG_BAND_3_CHANNELS,
1524 EEPROM_5000_REG_BAND_4_CHANNELS,
1525 EEPROM_5000_REG_BAND_5_CHANNELS,
1526 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1527 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1528 },
1529 .verify_signature = iwlcore_eeprom_verify_signature,
1530 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1531 .release_semaphore = iwlcore_eeprom_release_semaphore,
1532 .calib_version = iwl5000_eeprom_calib_version,
1533 .query_addr = iwl5000_eeprom_query_addr,
1534 },
1535 .post_associate = iwl_post_associate,
ef850d7c 1536 .isr = iwl_isr_ict,
62161aef
WYG		 1537 .config_ap = iwl_config_ap,
1538 .temp_ops = {
1539 .temperature = iwl5150_temperature,
1540 .set_ct_kill = iwl5150_set_ct_threshold,
1541 },
da8dec29
TW		 1542};
1543
cec2d3f3 1544struct iwl_ops iwl5000_ops = {
da8dec29
TW		 1545 .lib = &iwl5000_lib,
1546 .hcmd = &iwl5000_hcmd,
1547 .utils = &iwl5000_hcmd_utils,
1548};
1549
62161aef
WYG		 1550static struct iwl_ops iwl5150_ops = {
1551 .lib = &iwl5150_lib,
1552 .hcmd = &iwl5000_hcmd,
1553 .utils = &iwl5000_hcmd_utils,
62161aef
WYG		 1554};
1555
cec2d3f3 1556struct iwl_mod_params iwl50_mod_params = {
5a6a256e 1557 .num_of_queues = IWL50_NUM_QUEUES,
9f17b318 1558 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1559 .amsdu_size_8K = 1,
3a1081e8 1560 .restart_fw = 1,
5a6a256e
TW		 1561 /* the rest are 0 by default */
1562};
1563
1564
1565struct iwl_cfg iwl5300_agn_cfg = {
1566 .name = "5300AGN",
a0987a8d
RC		 1567 .fw_name_pre = IWL5000_FW_PRE,
1568 .ucode_api_max = IWL5000_UCODE_API_MAX,
1569 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1570 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1571 .ops = &iwl5000_ops,
25ae3986 1572 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1573 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1574 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
5a6a256e 1575 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1576 .valid_tx_ant = ANT_ABC,
1577 .valid_rx_ant = ANT_ABC,
050681b7 1578 .need_pll_cfg = true,
5a6a256e
TW		 1579};
1580
47408639
EK		 1581struct iwl_cfg iwl5100_bg_cfg = {
1582 .name = "5100BG",
a0987a8d
RC		 1583 .fw_name_pre = IWL5000_FW_PRE,
1584 .ucode_api_max = IWL5000_UCODE_API_MAX,
1585 .ucode_api_min = IWL5000_UCODE_API_MIN,
47408639
EK		 1586 .sku = IWL_SKU_G,
1587 .ops = &iwl5000_ops,
1588 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1589 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1590 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
47408639 1591 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1592 .valid_tx_ant = ANT_B,
1593 .valid_rx_ant = ANT_AB,
050681b7 1594 .need_pll_cfg = true,
47408639
EK		 1595};
1596
1597struct iwl_cfg iwl5100_abg_cfg = {
1598 .name = "5100ABG",
a0987a8d
RC		 1599 .fw_name_pre = IWL5000_FW_PRE,
1600 .ucode_api_max = IWL5000_UCODE_API_MAX,
1601 .ucode_api_min = IWL5000_UCODE_API_MIN,
47408639
EK		 1602 .sku = IWL_SKU_A|IWL_SKU_G,
1603 .ops = &iwl5000_ops,
1604 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1605 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1606 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
47408639 1607 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1608 .valid_tx_ant = ANT_B,
1609 .valid_rx_ant = ANT_AB,
050681b7 1610 .need_pll_cfg = true,
47408639
EK		 1611};
1612
5a6a256e
TW		 1613struct iwl_cfg iwl5100_agn_cfg = {
1614 .name = "5100AGN",
a0987a8d
RC		 1615 .fw_name_pre = IWL5000_FW_PRE,
1616 .ucode_api_max = IWL5000_UCODE_API_MAX,
1617 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1618 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1619 .ops = &iwl5000_ops,
25ae3986 1620 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1621 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1622 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
5a6a256e 1623 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1624 .valid_tx_ant = ANT_B,
1625 .valid_rx_ant = ANT_AB,
050681b7 1626 .need_pll_cfg = true,
5a6a256e
TW		 1627};
1628
1629struct iwl_cfg iwl5350_agn_cfg = {
1630 .name = "5350AGN",
a0987a8d
RC		 1631 .fw_name_pre = IWL5000_FW_PRE,
1632 .ucode_api_max = IWL5000_UCODE_API_MAX,
1633 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1634 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1635 .ops = &iwl5000_ops,
25ae3986 1636 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1637 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1638 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
5a6a256e 1639 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1640 .valid_tx_ant = ANT_ABC,
1641 .valid_rx_ant = ANT_ABC,
050681b7 1642 .need_pll_cfg = true,
5a6a256e
TW		 1643};
1644
7100e924
TW		 1645struct iwl_cfg iwl5150_agn_cfg = {
1646 .name = "5150AGN",
a0987a8d
RC		 1647 .fw_name_pre = IWL5150_FW_PRE,
1648 .ucode_api_max = IWL5150_UCODE_API_MAX,
1649 .ucode_api_min = IWL5150_UCODE_API_MIN,
7100e924 1650 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
62161aef 1651 .ops = &iwl5150_ops,
7100e924 1652 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
fd63edba
TW		 1653 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1654 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
7100e924 1655 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1656 .valid_tx_ant = ANT_A,
1657 .valid_rx_ant = ANT_AB,
050681b7 1658 .need_pll_cfg = true,
7100e924
TW		 1659};
1660
a0987a8d
RC		 1661MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1662MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
c9f79ed2 1663
5a6a256e
TW		 1664module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1665MODULE_PARM_DESC(swcrypto50,
1666 "using software crypto engine (default 0 [hardware])\n");
95aa194a 1667module_param_named(debug50, iwl50_mod_params.debug, uint, 0444);
5a6a256e
TW		 1668MODULE_PARM_DESC(debug50, "50XX debug output mask");
1669module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1670MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
49779293
RR		 1671module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1672MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
5a6a256e
TW		 1673module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1674MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
3a1081e8
EK		 1675module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1676MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
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