Commit | Line | Data |
---|---|---|
5a6a256e TW |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
23 | * | |
24 | *****************************************************************************/ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
5a6a256e TW |
28 | #include <linux/init.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/wireless.h> | |
35 | #include <net/mac80211.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <asm/unaligned.h> | |
38 | ||
39 | #include "iwl-eeprom.h" | |
3e0d4cb1 | 40 | #include "iwl-dev.h" |
5a6a256e TW |
41 | #include "iwl-core.h" |
42 | #include "iwl-io.h" | |
e26e47d9 | 43 | #include "iwl-sta.h" |
5a6a256e TW |
44 | #include "iwl-helpers.h" |
45 | #include "iwl-5000-hw.h" | |
46 | ||
47 | #define IWL5000_UCODE_API "-1" | |
48 | ||
4e062f99 JS |
49 | #define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode" |
50 | ||
99da1b48 RR |
51 | static const u16 iwl5000_default_queue_to_tx_fifo[] = { |
52 | IWL_TX_FIFO_AC3, | |
53 | IWL_TX_FIFO_AC2, | |
54 | IWL_TX_FIFO_AC1, | |
55 | IWL_TX_FIFO_AC0, | |
56 | IWL50_CMD_FIFO_NUM, | |
57 | IWL_TX_FIFO_HCCA_1, | |
58 | IWL_TX_FIFO_HCCA_2 | |
59 | }; | |
60 | ||
46315e01 TW |
61 | /* FIXME: same implementation as 4965 */ |
62 | static int iwl5000_apm_stop_master(struct iwl_priv *priv) | |
63 | { | |
64 | int ret = 0; | |
65 | unsigned long flags; | |
66 | ||
67 | spin_lock_irqsave(&priv->lock, flags); | |
68 | ||
69 | /* set stop master bit */ | |
70 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
71 | ||
72 | ret = iwl_poll_bit(priv, CSR_RESET, | |
73 | CSR_RESET_REG_FLAG_MASTER_DISABLED, | |
74 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
75 | if (ret < 0) | |
76 | goto out; | |
77 | ||
78 | out: | |
79 | spin_unlock_irqrestore(&priv->lock, flags); | |
80 | IWL_DEBUG_INFO("stop master\n"); | |
81 | ||
82 | return ret; | |
83 | } | |
84 | ||
85 | ||
30d59260 TW |
86 | static int iwl5000_apm_init(struct iwl_priv *priv) |
87 | { | |
88 | int ret = 0; | |
89 | ||
90 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
91 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
92 | ||
8f061891 TW |
93 | /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ |
94 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
95 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
96 | ||
a96a27f9 | 97 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ |
4c43e0d0 TW |
98 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); |
99 | ||
100 | /* enable HAP INTA to move device L1a -> L0s */ | |
101 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
102 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
103 | ||
30d59260 TW |
104 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); |
105 | ||
106 | /* set "initialization complete" bit to move adapter | |
107 | * D0U* --> D0A* state */ | |
108 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
109 | ||
110 | /* wait for clock stabilization */ | |
111 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
112 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
113 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
114 | if (ret < 0) { | |
115 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
116 | return ret; | |
117 | } | |
118 | ||
119 | ret = iwl_grab_nic_access(priv); | |
120 | if (ret) | |
121 | return ret; | |
122 | ||
123 | /* enable DMA */ | |
8f061891 | 124 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
30d59260 TW |
125 | |
126 | udelay(20); | |
127 | ||
8f061891 | 128 | /* disable L1-Active */ |
30d59260 | 129 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
8f061891 | 130 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
30d59260 TW |
131 | |
132 | iwl_release_nic_access(priv); | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
a96a27f9 | 137 | /* FIXME: this is identical to 4965 */ |
f118a91d TW |
138 | static void iwl5000_apm_stop(struct iwl_priv *priv) |
139 | { | |
140 | unsigned long flags; | |
141 | ||
46315e01 | 142 | iwl5000_apm_stop_master(priv); |
f118a91d TW |
143 | |
144 | spin_lock_irqsave(&priv->lock, flags); | |
145 | ||
146 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
147 | ||
148 | udelay(10); | |
149 | ||
1d3e6c61 MA |
150 | /* clear "init complete" move adapter D0A* --> D0U state */ |
151 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
f118a91d TW |
152 | |
153 | spin_unlock_irqrestore(&priv->lock, flags); | |
154 | } | |
155 | ||
156 | ||
7f066108 TW |
157 | static int iwl5000_apm_reset(struct iwl_priv *priv) |
158 | { | |
159 | int ret = 0; | |
160 | unsigned long flags; | |
161 | ||
46315e01 | 162 | iwl5000_apm_stop_master(priv); |
7f066108 TW |
163 | |
164 | spin_lock_irqsave(&priv->lock, flags); | |
165 | ||
166 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
167 | ||
168 | udelay(10); | |
169 | ||
170 | ||
171 | /* FIXME: put here L1A -L0S w/a */ | |
172 | ||
173 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); | |
174 | ||
175 | /* set "initialization complete" bit to move adapter | |
176 | * D0U* --> D0A* state */ | |
177 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
178 | ||
179 | /* wait for clock stabilization */ | |
180 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
181 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
182 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
183 | if (ret < 0) { | |
184 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
185 | goto out; | |
186 | } | |
187 | ||
188 | ret = iwl_grab_nic_access(priv); | |
189 | if (ret) | |
190 | goto out; | |
191 | ||
192 | /* enable DMA */ | |
193 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
194 | ||
195 | udelay(20); | |
196 | ||
197 | /* disable L1-Active */ | |
198 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | |
199 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
200 | ||
201 | iwl_release_nic_access(priv); | |
202 | ||
203 | out: | |
204 | spin_unlock_irqrestore(&priv->lock, flags); | |
205 | ||
206 | return ret; | |
207 | } | |
208 | ||
209 | ||
5a835353 | 210 | static void iwl5000_nic_config(struct iwl_priv *priv) |
e86fe9f6 TW |
211 | { |
212 | unsigned long flags; | |
213 | u16 radio_cfg; | |
e7b63581 | 214 | u16 link; |
e86fe9f6 TW |
215 | |
216 | spin_lock_irqsave(&priv->lock, flags); | |
217 | ||
e7b63581 | 218 | pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link); |
e86fe9f6 | 219 | |
8f061891 | 220 | /* L1 is enabled by BIOS */ |
e7b63581 | 221 | if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) |
a96a27f9 | 222 | /* disable L0S disabled L1A enabled */ |
8f061891 TW |
223 | iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
224 | else | |
225 | /* L0S enabled L1A disabled */ | |
226 | iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
e86fe9f6 TW |
227 | |
228 | radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); | |
229 | ||
230 | /* write radio config values to register */ | |
231 | if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) | |
232 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
233 | EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | | |
234 | EEPROM_RF_CFG_STEP_MSK(radio_cfg) | | |
235 | EEPROM_RF_CFG_DASH_MSK(radio_cfg)); | |
236 | ||
237 | /* set CSR_HW_CONFIG_REG for uCode use */ | |
238 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
239 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | | |
240 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
241 | ||
4c43e0d0 TW |
242 | /* W/A : NIC is stuck in a reset state after Early PCIe power off |
243 | * (PCIe power is lost before PERST# is asserted), | |
244 | * causing ME FW to lose ownership and not being able to obtain it back. | |
245 | */ | |
2d3db679 TW |
246 | iwl_grab_nic_access(priv); |
247 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
4c43e0d0 TW |
248 | APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, |
249 | ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); | |
2d3db679 | 250 | iwl_release_nic_access(priv); |
4c43e0d0 | 251 | |
e86fe9f6 TW |
252 | spin_unlock_irqrestore(&priv->lock, flags); |
253 | } | |
254 | ||
255 | ||
256 | ||
25ae3986 TW |
257 | /* |
258 | * EEPROM | |
259 | */ | |
260 | static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) | |
261 | { | |
262 | u16 offset = 0; | |
263 | ||
264 | if ((address & INDIRECT_ADDRESS) == 0) | |
265 | return address; | |
266 | ||
267 | switch (address & INDIRECT_TYPE_MSK) { | |
268 | case INDIRECT_HOST: | |
269 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); | |
270 | break; | |
271 | case INDIRECT_GENERAL: | |
272 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); | |
273 | break; | |
274 | case INDIRECT_REGULATORY: | |
275 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); | |
276 | break; | |
277 | case INDIRECT_CALIBRATION: | |
278 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); | |
279 | break; | |
280 | case INDIRECT_PROCESS_ADJST: | |
281 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); | |
282 | break; | |
283 | case INDIRECT_OTHERS: | |
284 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); | |
285 | break; | |
286 | default: | |
287 | IWL_ERROR("illegal indirect type: 0x%X\n", | |
288 | address & INDIRECT_TYPE_MSK); | |
289 | break; | |
290 | } | |
291 | ||
292 | /* translate the offset from words to byte */ | |
293 | return (address & ADDRESS_MSK) + (offset << 1); | |
294 | } | |
295 | ||
0ef2ca67 | 296 | static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) |
f1f69415 | 297 | { |
f1f69415 TW |
298 | struct iwl_eeprom_calib_hdr { |
299 | u8 version; | |
300 | u8 pa_type; | |
301 | u16 voltage; | |
302 | } *hdr; | |
303 | ||
f1f69415 TW |
304 | hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, |
305 | EEPROM_5000_CALIB_ALL); | |
0ef2ca67 | 306 | return hdr->version; |
f1f69415 TW |
307 | |
308 | } | |
309 | ||
33fd5033 EG |
310 | static void iwl5000_gain_computation(struct iwl_priv *priv, |
311 | u32 average_noise[NUM_RX_CHAINS], | |
312 | u16 min_average_noise_antenna_i, | |
313 | u32 min_average_noise) | |
314 | { | |
315 | int i; | |
316 | s32 delta_g; | |
317 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
318 | ||
319 | /* Find Gain Code for the antennas B and C */ | |
320 | for (i = 1; i < NUM_RX_CHAINS; i++) { | |
321 | if ((data->disconn_array[i])) { | |
322 | data->delta_gain_code[i] = 0; | |
323 | continue; | |
324 | } | |
325 | delta_g = (1000 * ((s32)average_noise[0] - | |
326 | (s32)average_noise[i])) / 1500; | |
327 | /* bound gain by 2 bits value max, 3rd bit is sign */ | |
328 | data->delta_gain_code[i] = | |
329 | min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); | |
330 | ||
331 | if (delta_g < 0) | |
332 | /* set negative sign */ | |
333 | data->delta_gain_code[i] |= (1 << 2); | |
334 | } | |
335 | ||
336 | IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n", | |
337 | data->delta_gain_code[1], data->delta_gain_code[2]); | |
338 | ||
339 | if (!data->radio_write) { | |
f69f42a6 | 340 | struct iwl_calib_chain_noise_gain_cmd cmd; |
33fd5033 EG |
341 | memset(&cmd, 0, sizeof(cmd)); |
342 | ||
f69f42a6 | 343 | cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; |
33fd5033 EG |
344 | cmd.delta_gain_1 = data->delta_gain_code[1]; |
345 | cmd.delta_gain_2 = data->delta_gain_code[2]; | |
346 | iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, | |
347 | sizeof(cmd), &cmd, NULL); | |
348 | ||
349 | data->radio_write = 1; | |
350 | data->state = IWL_CHAIN_NOISE_CALIBRATED; | |
351 | } | |
352 | ||
353 | data->chain_noise_a = 0; | |
354 | data->chain_noise_b = 0; | |
355 | data->chain_noise_c = 0; | |
356 | data->chain_signal_a = 0; | |
357 | data->chain_signal_b = 0; | |
358 | data->chain_signal_c = 0; | |
359 | data->beacon_count = 0; | |
360 | } | |
361 | ||
362 | static void iwl5000_chain_noise_reset(struct iwl_priv *priv) | |
363 | { | |
364 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
365 | ||
366 | if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { | |
f69f42a6 | 367 | struct iwl_calib_chain_noise_reset_cmd cmd; |
33fd5033 EG |
368 | |
369 | memset(&cmd, 0, sizeof(cmd)); | |
f69f42a6 | 370 | cmd.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; |
33fd5033 EG |
371 | if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, |
372 | sizeof(cmd), &cmd)) | |
373 | IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); | |
374 | data->state = IWL_CHAIN_NOISE_ACCUMULATE; | |
375 | IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); | |
376 | } | |
377 | } | |
378 | ||
a326a5d0 EG |
379 | static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, |
380 | __le32 *tx_flags) | |
381 | { | |
e6a9854b JB |
382 | if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || |
383 | (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) | |
a326a5d0 EG |
384 | *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; |
385 | else | |
386 | *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; | |
387 | } | |
388 | ||
33fd5033 EG |
389 | static struct iwl_sensitivity_ranges iwl5000_sensitivity = { |
390 | .min_nrg_cck = 95, | |
391 | .max_nrg_cck = 0, | |
392 | .auto_corr_min_ofdm = 90, | |
393 | .auto_corr_min_ofdm_mrc = 170, | |
394 | .auto_corr_min_ofdm_x1 = 120, | |
395 | .auto_corr_min_ofdm_mrc_x1 = 240, | |
396 | ||
397 | .auto_corr_max_ofdm = 120, | |
398 | .auto_corr_max_ofdm_mrc = 210, | |
399 | .auto_corr_max_ofdm_x1 = 155, | |
400 | .auto_corr_max_ofdm_mrc_x1 = 290, | |
401 | ||
402 | .auto_corr_min_cck = 125, | |
403 | .auto_corr_max_cck = 200, | |
404 | .auto_corr_min_cck_mrc = 170, | |
405 | .auto_corr_max_cck_mrc = 400, | |
406 | .nrg_th_cck = 95, | |
407 | .nrg_th_ofdm = 95, | |
408 | }; | |
409 | ||
25ae3986 TW |
410 | static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, |
411 | size_t offset) | |
412 | { | |
413 | u32 address = eeprom_indirect_address(priv, offset); | |
414 | BUG_ON(address >= priv->cfg->eeprom_size); | |
415 | return &priv->eeprom[address]; | |
416 | } | |
417 | ||
7c616cba TW |
418 | /* |
419 | * Calibration | |
420 | */ | |
be5d56ed | 421 | static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) |
7c616cba | 422 | { |
f69f42a6 | 423 | u8 data[sizeof(struct iwl_calib_hdr) + |
be5d56ed | 424 | sizeof(struct iwl_cal_xtal_freq)]; |
f69f42a6 | 425 | struct iwl_calib_cmd *cmd = (struct iwl_calib_cmd *)data; |
be5d56ed | 426 | struct iwl_cal_xtal_freq *xtal = (struct iwl_cal_xtal_freq *)cmd->data; |
7c616cba TW |
427 | u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); |
428 | ||
f69f42a6 | 429 | cmd->hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; |
be5d56ed TW |
430 | xtal->cap_pin1 = (u8)xtal_calib[0]; |
431 | xtal->cap_pin2 = (u8)xtal_calib[1]; | |
f69f42a6 | 432 | return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], |
be5d56ed | 433 | data, sizeof(data)); |
7c616cba TW |
434 | } |
435 | ||
7c616cba TW |
436 | static int iwl5000_send_calib_cfg(struct iwl_priv *priv) |
437 | { | |
f69f42a6 | 438 | struct iwl_calib_cfg_cmd calib_cfg_cmd; |
7c616cba TW |
439 | struct iwl_host_cmd cmd = { |
440 | .id = CALIBRATION_CFG_CMD, | |
f69f42a6 | 441 | .len = sizeof(struct iwl_calib_cfg_cmd), |
7c616cba TW |
442 | .data = &calib_cfg_cmd, |
443 | }; | |
444 | ||
445 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
446 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
447 | calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; | |
448 | calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; | |
449 | calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; | |
450 | ||
451 | return iwl_send_cmd(priv, &cmd); | |
452 | } | |
453 | ||
454 | static void iwl5000_rx_calib_result(struct iwl_priv *priv, | |
455 | struct iwl_rx_mem_buffer *rxb) | |
456 | { | |
457 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; | |
f69f42a6 | 458 | struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; |
7c616cba | 459 | int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; |
6e21f2c1 | 460 | int index; |
7c616cba TW |
461 | |
462 | /* reduce the size of the length field itself */ | |
463 | len -= 4; | |
464 | ||
6e21f2c1 TW |
465 | /* Define the order in which the results will be sent to the runtime |
466 | * uCode. iwl_send_calib_results sends them in a row according to their | |
467 | * index. We sort them here */ | |
7c616cba | 468 | switch (hdr->op_code) { |
f69f42a6 TW |
469 | case IWL_PHY_CALIBRATE_LO_CMD: |
470 | index = IWL_CALIB_LO; | |
7c616cba | 471 | break; |
f69f42a6 TW |
472 | case IWL_PHY_CALIBRATE_TX_IQ_CMD: |
473 | index = IWL_CALIB_TX_IQ; | |
7c616cba | 474 | break; |
f69f42a6 TW |
475 | case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: |
476 | index = IWL_CALIB_TX_IQ_PERD; | |
7c616cba | 477 | break; |
201706ac TW |
478 | case IWL_PHY_CALIBRATE_BASE_BAND_CMD: |
479 | index = IWL_CALIB_BASE_BAND; | |
480 | break; | |
7c616cba TW |
481 | default: |
482 | IWL_ERROR("Unknown calibration notification %d\n", | |
483 | hdr->op_code); | |
484 | return; | |
485 | } | |
6e21f2c1 | 486 | iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); |
7c616cba TW |
487 | } |
488 | ||
489 | static void iwl5000_rx_calib_complete(struct iwl_priv *priv, | |
490 | struct iwl_rx_mem_buffer *rxb) | |
491 | { | |
492 | IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n"); | |
493 | queue_work(priv->workqueue, &priv->restart); | |
494 | } | |
495 | ||
dbb983b7 RR |
496 | /* |
497 | * ucode | |
498 | */ | |
499 | static int iwl5000_load_section(struct iwl_priv *priv, | |
500 | struct fw_desc *image, | |
501 | u32 dst_addr) | |
502 | { | |
503 | int ret = 0; | |
504 | unsigned long flags; | |
505 | ||
506 | dma_addr_t phy_addr = image->p_addr; | |
507 | u32 byte_cnt = image->len; | |
508 | ||
509 | spin_lock_irqsave(&priv->lock, flags); | |
510 | ret = iwl_grab_nic_access(priv); | |
511 | if (ret) { | |
512 | spin_unlock_irqrestore(&priv->lock, flags); | |
513 | return ret; | |
514 | } | |
515 | ||
516 | iwl_write_direct32(priv, | |
517 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
518 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
519 | ||
520 | iwl_write_direct32(priv, | |
521 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); | |
522 | ||
523 | iwl_write_direct32(priv, | |
524 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
525 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
526 | ||
dbb983b7 | 527 | iwl_write_direct32(priv, |
f0b9f5cb | 528 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
499b1883 | 529 | (iwl_get_dma_hi_addr(phy_addr) |
f0b9f5cb TW |
530 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); |
531 | ||
dbb983b7 RR |
532 | iwl_write_direct32(priv, |
533 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
534 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
535 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
536 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
537 | ||
538 | iwl_write_direct32(priv, | |
539 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
540 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
9c80c502 | 541 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | |
dbb983b7 RR |
542 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); |
543 | ||
544 | iwl_release_nic_access(priv); | |
545 | spin_unlock_irqrestore(&priv->lock, flags); | |
546 | return 0; | |
547 | } | |
548 | ||
549 | static int iwl5000_load_given_ucode(struct iwl_priv *priv, | |
550 | struct fw_desc *inst_image, | |
551 | struct fw_desc *data_image) | |
552 | { | |
553 | int ret = 0; | |
554 | ||
9c80c502 | 555 | ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND); |
dbb983b7 RR |
556 | if (ret) |
557 | return ret; | |
558 | ||
559 | IWL_DEBUG_INFO("INST uCode section being loaded...\n"); | |
560 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
9c80c502 | 561 | priv->ucode_write_complete, 5 * HZ); |
dbb983b7 RR |
562 | if (ret == -ERESTARTSYS) { |
563 | IWL_ERROR("Could not load the INST uCode section due " | |
564 | "to interrupt\n"); | |
565 | return ret; | |
566 | } | |
567 | if (!ret) { | |
568 | IWL_ERROR("Could not load the INST uCode section\n"); | |
569 | return -ETIMEDOUT; | |
570 | } | |
571 | ||
572 | priv->ucode_write_complete = 0; | |
573 | ||
574 | ret = iwl5000_load_section( | |
575 | priv, data_image, RTC_DATA_LOWER_BOUND); | |
576 | if (ret) | |
577 | return ret; | |
578 | ||
579 | IWL_DEBUG_INFO("DATA uCode section being loaded...\n"); | |
580 | ||
581 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
582 | priv->ucode_write_complete, 5 * HZ); | |
583 | if (ret == -ERESTARTSYS) { | |
584 | IWL_ERROR("Could not load the INST uCode section due " | |
585 | "to interrupt\n"); | |
586 | return ret; | |
587 | } else if (!ret) { | |
588 | IWL_ERROR("Could not load the DATA uCode section\n"); | |
589 | return -ETIMEDOUT; | |
590 | } else | |
591 | ret = 0; | |
592 | ||
593 | priv->ucode_write_complete = 0; | |
594 | ||
595 | return ret; | |
596 | } | |
597 | ||
598 | static int iwl5000_load_ucode(struct iwl_priv *priv) | |
599 | { | |
600 | int ret = 0; | |
601 | ||
602 | /* check whether init ucode should be loaded, or rather runtime ucode */ | |
603 | if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { | |
604 | IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n"); | |
605 | ret = iwl5000_load_given_ucode(priv, | |
606 | &priv->ucode_init, &priv->ucode_init_data); | |
607 | if (!ret) { | |
608 | IWL_DEBUG_INFO("Init ucode load complete.\n"); | |
609 | priv->ucode_type = UCODE_INIT; | |
610 | } | |
611 | } else { | |
612 | IWL_DEBUG_INFO("Init ucode not found, or already loaded. " | |
613 | "Loading runtime ucode...\n"); | |
614 | ret = iwl5000_load_given_ucode(priv, | |
615 | &priv->ucode_code, &priv->ucode_data); | |
616 | if (!ret) { | |
617 | IWL_DEBUG_INFO("Runtime ucode load complete.\n"); | |
618 | priv->ucode_type = UCODE_RT; | |
619 | } | |
620 | } | |
621 | ||
622 | return ret; | |
623 | } | |
624 | ||
99da1b48 RR |
625 | static void iwl5000_init_alive_start(struct iwl_priv *priv) |
626 | { | |
627 | int ret = 0; | |
628 | ||
629 | /* Check alive response for "valid" sign from uCode */ | |
630 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
631 | /* We had an error bringing up the hardware, so take it | |
632 | * all the way back down so we can try again */ | |
633 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
634 | goto restart; | |
635 | } | |
636 | ||
637 | /* initialize uCode was loaded... verify inst image. | |
638 | * This is a paranoid check, because we would not have gotten the | |
639 | * "initialize" alive if code weren't properly loaded. */ | |
640 | if (iwl_verify_ucode(priv)) { | |
641 | /* Runtime instruction load was bad; | |
642 | * take it all the way back down so we can try again */ | |
643 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
644 | goto restart; | |
645 | } | |
646 | ||
37deb2a0 | 647 | iwl_clear_stations_table(priv); |
99da1b48 RR |
648 | ret = priv->cfg->ops->lib->alive_notify(priv); |
649 | if (ret) { | |
650 | IWL_WARNING("Could not complete ALIVE transition: %d\n", ret); | |
651 | goto restart; | |
652 | } | |
653 | ||
7c616cba | 654 | iwl5000_send_calib_cfg(priv); |
99da1b48 RR |
655 | return; |
656 | ||
657 | restart: | |
658 | /* real restart (first load init_ucode) */ | |
659 | queue_work(priv->workqueue, &priv->restart); | |
660 | } | |
661 | ||
662 | static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, | |
663 | int txq_id, u32 index) | |
664 | { | |
665 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
666 | (index & 0xff) | (txq_id << 8)); | |
667 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); | |
668 | } | |
669 | ||
670 | static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, | |
671 | struct iwl_tx_queue *txq, | |
672 | int tx_fifo_id, int scd_retry) | |
673 | { | |
674 | int txq_id = txq->q.id; | |
3fd07a1e | 675 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; |
99da1b48 RR |
676 | |
677 | iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
678 | (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
679 | (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | | |
680 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | | |
681 | IWL50_SCD_QUEUE_STTS_REG_MSK); | |
682 | ||
683 | txq->sched_retry = scd_retry; | |
684 | ||
685 | IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", | |
686 | active ? "Activate" : "Deactivate", | |
687 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); | |
688 | } | |
689 | ||
9636e583 RR |
690 | static int iwl5000_send_wimax_coex(struct iwl_priv *priv) |
691 | { | |
692 | struct iwl_wimax_coex_cmd coex_cmd; | |
693 | ||
694 | memset(&coex_cmd, 0, sizeof(coex_cmd)); | |
695 | ||
696 | return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, | |
697 | sizeof(coex_cmd), &coex_cmd); | |
698 | } | |
699 | ||
99da1b48 RR |
700 | static int iwl5000_alive_notify(struct iwl_priv *priv) |
701 | { | |
702 | u32 a; | |
99da1b48 RR |
703 | unsigned long flags; |
704 | int ret; | |
31a73fe4 | 705 | int i, chan; |
40fc95d5 | 706 | u32 reg_val; |
99da1b48 RR |
707 | |
708 | spin_lock_irqsave(&priv->lock, flags); | |
709 | ||
710 | ret = iwl_grab_nic_access(priv); | |
711 | if (ret) { | |
712 | spin_unlock_irqrestore(&priv->lock, flags); | |
713 | return ret; | |
714 | } | |
715 | ||
716 | priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); | |
717 | a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; | |
718 | for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; | |
719 | a += 4) | |
720 | iwl_write_targ_mem(priv, a, 0); | |
721 | for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; | |
722 | a += 4) | |
723 | iwl_write_targ_mem(priv, a, 0); | |
724 | for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) | |
725 | iwl_write_targ_mem(priv, a, 0); | |
726 | ||
727 | iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, | |
4ddbb7d0 | 728 | priv->scd_bc_tbls.dma >> 10); |
31a73fe4 WT |
729 | |
730 | /* Enable DMA channel */ | |
731 | for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++) | |
732 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
733 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
734 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
735 | ||
40fc95d5 WT |
736 | /* Update FH chicken bits */ |
737 | reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); | |
738 | iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, | |
739 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
740 | ||
99da1b48 | 741 | iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, |
4ddbb7d0 | 742 | IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); |
99da1b48 RR |
743 | iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); |
744 | ||
745 | /* initiate the queues */ | |
746 | for (i = 0; i < priv->hw_params.max_txq_num; i++) { | |
747 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); | |
748 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
749 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
750 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); | |
751 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
752 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + | |
753 | sizeof(u32), | |
754 | ((SCD_WIN_SIZE << | |
755 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
756 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
757 | ((SCD_FRAME_LIMIT << | |
758 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
759 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
760 | } | |
761 | ||
762 | iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, | |
da1bc453 | 763 | IWL_MASK(0, priv->hw_params.max_txq_num)); |
99da1b48 | 764 | |
da1bc453 TW |
765 | /* Activate all Tx DMA/FIFO channels */ |
766 | priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); | |
99da1b48 RR |
767 | |
768 | iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); | |
9c80c502 | 769 | |
99da1b48 RR |
770 | /* map qos queues to fifos one-to-one */ |
771 | for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { | |
772 | int ac = iwl5000_default_queue_to_tx_fifo[i]; | |
773 | iwl_txq_ctx_activate(priv, i); | |
774 | iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); | |
775 | } | |
776 | /* TODO - need to initialize those FIFOs inside the loop above, | |
777 | * not only mark them as active */ | |
778 | iwl_txq_ctx_activate(priv, 4); | |
779 | iwl_txq_ctx_activate(priv, 7); | |
780 | iwl_txq_ctx_activate(priv, 8); | |
781 | iwl_txq_ctx_activate(priv, 9); | |
782 | ||
783 | iwl_release_nic_access(priv); | |
784 | spin_unlock_irqrestore(&priv->lock, flags); | |
785 | ||
7c616cba | 786 | |
9636e583 RR |
787 | iwl5000_send_wimax_coex(priv); |
788 | ||
be5d56ed TW |
789 | iwl5000_set_Xtal_calib(priv); |
790 | iwl_send_calib_results(priv); | |
7c616cba | 791 | |
99da1b48 RR |
792 | return 0; |
793 | } | |
794 | ||
fdd3e8a4 TW |
795 | static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) |
796 | { | |
797 | if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || | |
798 | (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { | |
799 | IWL_ERROR("invalid queues_num, should be between %d and %d\n", | |
800 | IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); | |
801 | return -EINVAL; | |
802 | } | |
25ae3986 | 803 | |
fdd3e8a4 | 804 | priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; |
4ddbb7d0 TW |
805 | priv->hw_params.scd_bc_tbls_size = |
806 | IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl); | |
fdd3e8a4 TW |
807 | priv->hw_params.max_stations = IWL5000_STATION_COUNT; |
808 | priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; | |
809 | priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; | |
810 | priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; | |
da154e30 | 811 | priv->hw_params.max_bsm_size = 0; |
fdd3e8a4 TW |
812 | priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | |
813 | BIT(IEEE80211_BAND_5GHZ); | |
33fd5033 | 814 | priv->hw_params.sens = &iwl5000_sensitivity; |
fdd3e8a4 TW |
815 | |
816 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
817 | case CSR_HW_REV_TYPE_5100: | |
5d664a41 TW |
818 | priv->hw_params.tx_chains_num = 1; |
819 | priv->hw_params.rx_chains_num = 2; | |
820 | priv->hw_params.valid_tx_ant = ANT_B; | |
821 | priv->hw_params.valid_rx_ant = ANT_AB; | |
822 | break; | |
fdd3e8a4 TW |
823 | case CSR_HW_REV_TYPE_5150: |
824 | priv->hw_params.tx_chains_num = 1; | |
825 | priv->hw_params.rx_chains_num = 2; | |
1179f18d TW |
826 | priv->hw_params.valid_tx_ant = ANT_A; |
827 | priv->hw_params.valid_rx_ant = ANT_AB; | |
fdd3e8a4 TW |
828 | break; |
829 | case CSR_HW_REV_TYPE_5300: | |
830 | case CSR_HW_REV_TYPE_5350: | |
831 | priv->hw_params.tx_chains_num = 3; | |
832 | priv->hw_params.rx_chains_num = 3; | |
1179f18d TW |
833 | priv->hw_params.valid_tx_ant = ANT_ABC; |
834 | priv->hw_params.valid_rx_ant = ANT_ABC; | |
fdd3e8a4 TW |
835 | break; |
836 | } | |
c031bf80 EG |
837 | |
838 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
839 | case CSR_HW_REV_TYPE_5100: | |
840 | case CSR_HW_REV_TYPE_5300: | |
d5d7c584 TW |
841 | case CSR_HW_REV_TYPE_5350: |
842 | /* 5X00 and 5350 wants in Celsius */ | |
c031bf80 EG |
843 | priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; |
844 | break; | |
845 | case CSR_HW_REV_TYPE_5150: | |
d5d7c584 | 846 | /* 5150 wants in Kelvin */ |
c031bf80 EG |
847 | priv->hw_params.ct_kill_threshold = |
848 | CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD); | |
849 | break; | |
850 | } | |
851 | ||
be5d56ed TW |
852 | /* Set initial calibration set */ |
853 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
854 | case CSR_HW_REV_TYPE_5100: | |
855 | case CSR_HW_REV_TYPE_5300: | |
856 | case CSR_HW_REV_TYPE_5350: | |
857 | priv->hw_params.calib_init_cfg = | |
f69f42a6 TW |
858 | BIT(IWL_CALIB_XTAL) | |
859 | BIT(IWL_CALIB_LO) | | |
201706ac TW |
860 | BIT(IWL_CALIB_TX_IQ) | |
861 | BIT(IWL_CALIB_TX_IQ_PERD) | | |
862 | BIT(IWL_CALIB_BASE_BAND); | |
be5d56ed TW |
863 | break; |
864 | case CSR_HW_REV_TYPE_5150: | |
865 | priv->hw_params.calib_init_cfg = 0; | |
866 | break; | |
867 | } | |
868 | ||
869 | ||
fdd3e8a4 TW |
870 | return 0; |
871 | } | |
d4100dd9 | 872 | |
7839fc03 EG |
873 | /** |
874 | * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
875 | */ | |
876 | static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, | |
16466903 | 877 | struct iwl_tx_queue *txq, |
7839fc03 EG |
878 | u16 byte_cnt) |
879 | { | |
4ddbb7d0 | 880 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab | 881 | int write_ptr = txq->q.write_ptr; |
7839fc03 EG |
882 | int txq_id = txq->q.id; |
883 | u8 sec_ctl = 0; | |
127901ab TW |
884 | u8 sta_id = 0; |
885 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
886 | __le16 bc_ent; | |
7839fc03 | 887 | |
127901ab | 888 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
7839fc03 EG |
889 | |
890 | if (txq_id != IWL_CMD_QUEUE_NUM) { | |
127901ab | 891 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; |
da99c4b6 | 892 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; |
7839fc03 EG |
893 | |
894 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
895 | case TX_CMD_SEC_CCM: | |
896 | len += CCMP_MIC_LEN; | |
897 | break; | |
898 | case TX_CMD_SEC_TKIP: | |
899 | len += TKIP_ICV_LEN; | |
900 | break; | |
901 | case TX_CMD_SEC_WEP: | |
902 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
903 | break; | |
904 | } | |
905 | } | |
906 | ||
127901ab | 907 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); |
7839fc03 | 908 | |
4ddbb7d0 | 909 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; |
7839fc03 | 910 | |
127901ab | 911 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 912 | scd_bc_tbl[txq_id]. |
127901ab | 913 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; |
7839fc03 EG |
914 | } |
915 | ||
972cf447 TW |
916 | static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, |
917 | struct iwl_tx_queue *txq) | |
918 | { | |
4ddbb7d0 | 919 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab TW |
920 | int txq_id = txq->q.id; |
921 | int read_ptr = txq->q.read_ptr; | |
922 | u8 sta_id = 0; | |
923 | __le16 bc_ent; | |
924 | ||
925 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
972cf447 TW |
926 | |
927 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
127901ab | 928 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
972cf447 | 929 | |
127901ab | 930 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); |
4ddbb7d0 | 931 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; |
972cf447 | 932 | |
127901ab | 933 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 934 | scd_bc_tbl[txq_id]. |
127901ab | 935 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; |
972cf447 TW |
936 | } |
937 | ||
e26e47d9 TW |
938 | static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, |
939 | u16 txq_id) | |
940 | { | |
941 | u32 tbl_dw_addr; | |
942 | u32 tbl_dw; | |
943 | u16 scd_q2ratid; | |
944 | ||
945 | scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
946 | ||
947 | tbl_dw_addr = priv->scd_base_addr + | |
948 | IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); | |
949 | ||
950 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
951 | ||
952 | if (txq_id & 0x1) | |
953 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
954 | else | |
955 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
956 | ||
957 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
958 | ||
959 | return 0; | |
960 | } | |
961 | static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
962 | { | |
963 | /* Simply stop the queue, but don't change any configuration; | |
964 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
965 | iwl_write_prph(priv, | |
966 | IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
967 | (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
968 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
969 | } | |
970 | ||
971 | static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |
972 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) | |
973 | { | |
974 | unsigned long flags; | |
975 | int ret; | |
976 | u16 ra_tid; | |
977 | ||
9f17b318 TW |
978 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
979 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
980 | IWL_WARNING("queue number out of range: %d, must be %d to %d\n", | |
981 | txq_id, IWL50_FIRST_AMPDU_QUEUE, | |
982 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
983 | return -EINVAL; | |
984 | } | |
e26e47d9 TW |
985 | |
986 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
987 | ||
988 | /* Modify device's station table to Tx this TID */ | |
9f58671e | 989 | iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); |
e26e47d9 TW |
990 | |
991 | spin_lock_irqsave(&priv->lock, flags); | |
992 | ret = iwl_grab_nic_access(priv); | |
993 | if (ret) { | |
994 | spin_unlock_irqrestore(&priv->lock, flags); | |
995 | return ret; | |
996 | } | |
997 | ||
998 | /* Stop this Tx queue before configuring it */ | |
999 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); | |
1000 | ||
1001 | /* Map receiver-address / traffic-ID to this queue */ | |
1002 | iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
1003 | ||
1004 | /* Set this queue as a chain-building queue */ | |
1005 | iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); | |
1006 | ||
1007 | /* enable aggregations for the queue */ | |
1008 | iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); | |
1009 | ||
1010 | /* Place first TFD at index corresponding to start sequence number. | |
1011 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
1012 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
1013 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
1014 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
1015 | ||
1016 | /* Set up Tx window size and frame limit for this queue */ | |
1017 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
1018 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + | |
1019 | sizeof(u32), | |
1020 | ((SCD_WIN_SIZE << | |
1021 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1022 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1023 | ((SCD_FRAME_LIMIT << | |
1024 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1025 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
1026 | ||
1027 | iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
1028 | ||
1029 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
1030 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
1031 | ||
1032 | iwl_release_nic_access(priv); | |
1033 | spin_unlock_irqrestore(&priv->lock, flags); | |
1034 | ||
1035 | return 0; | |
1036 | } | |
1037 | ||
1038 | static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, | |
1039 | u16 ssn_idx, u8 tx_fifo) | |
1040 | { | |
1041 | int ret; | |
1042 | ||
9f17b318 TW |
1043 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
1044 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
1045 | IWL_WARNING("queue number out of range: %d, must be %d to %d\n", | |
1046 | txq_id, IWL50_FIRST_AMPDU_QUEUE, | |
1047 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
e26e47d9 TW |
1048 | return -EINVAL; |
1049 | } | |
1050 | ||
1051 | ret = iwl_grab_nic_access(priv); | |
1052 | if (ret) | |
1053 | return ret; | |
1054 | ||
1055 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); | |
1056 | ||
1057 | iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); | |
1058 | ||
1059 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
1060 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
1061 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
1062 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
1063 | ||
1064 | iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
1065 | iwl_txq_ctx_deactivate(priv, txq_id); | |
1066 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
1067 | ||
1068 | iwl_release_nic_access(priv); | |
1069 | ||
1070 | return 0; | |
1071 | } | |
1072 | ||
2469bf2e TW |
1073 | static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) |
1074 | { | |
1075 | u16 size = (u16)sizeof(struct iwl_addsta_cmd); | |
1076 | memcpy(data, cmd, size); | |
1077 | return size; | |
1078 | } | |
1079 | ||
1080 | ||
da1bc453 | 1081 | /* |
a96a27f9 | 1082 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask |
da1bc453 TW |
1083 | * must be called under priv->lock and mac access |
1084 | */ | |
1085 | static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) | |
5a676bbe | 1086 | { |
da1bc453 | 1087 | iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); |
5a676bbe RR |
1088 | } |
1089 | ||
e532fa0e RR |
1090 | |
1091 | static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) | |
1092 | { | |
3ac7f146 | 1093 | return le32_to_cpup((__le32 *)&tx_resp->status + |
25a6572c | 1094 | tx_resp->frame_count) & MAX_SN; |
e532fa0e RR |
1095 | } |
1096 | ||
1097 | static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, | |
1098 | struct iwl_ht_agg *agg, | |
1099 | struct iwl5000_tx_resp *tx_resp, | |
25a6572c | 1100 | int txq_id, u16 start_idx) |
e532fa0e RR |
1101 | { |
1102 | u16 status; | |
1103 | struct agg_tx_status *frame_status = &tx_resp->status; | |
1104 | struct ieee80211_tx_info *info = NULL; | |
1105 | struct ieee80211_hdr *hdr = NULL; | |
e7d326ac | 1106 | u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); |
25a6572c | 1107 | int i, sh, idx; |
e532fa0e RR |
1108 | u16 seq; |
1109 | ||
1110 | if (agg->wait_for_ba) | |
1111 | IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); | |
1112 | ||
1113 | agg->frame_count = tx_resp->frame_count; | |
1114 | agg->start_idx = start_idx; | |
e7d326ac | 1115 | agg->rate_n_flags = rate_n_flags; |
e532fa0e RR |
1116 | agg->bitmap = 0; |
1117 | ||
1118 | /* # frames attempted by Tx command */ | |
1119 | if (agg->frame_count == 1) { | |
1120 | /* Only one frame was attempted; no block-ack will arrive */ | |
1121 | status = le16_to_cpu(frame_status[0].status); | |
25a6572c | 1122 | idx = start_idx; |
e532fa0e RR |
1123 | |
1124 | /* FIXME: code repetition */ | |
1125 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", | |
1126 | agg->frame_count, agg->start_idx, idx); | |
1127 | ||
1128 | info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); | |
e6a9854b | 1129 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
e532fa0e | 1130 | info->flags &= ~IEEE80211_TX_CTL_AMPDU; |
c3056065 | 1131 | info->flags |= iwl_is_tx_success(status) ? |
3fd07a1e | 1132 | IEEE80211_TX_STAT_ACK : 0; |
e7d326ac TW |
1133 | iwl_hwrate_to_tx_control(priv, rate_n_flags, info); |
1134 | ||
e532fa0e RR |
1135 | /* FIXME: code repetition end */ |
1136 | ||
1137 | IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", | |
1138 | status & 0xff, tx_resp->failure_frame); | |
e7d326ac | 1139 | IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); |
e532fa0e RR |
1140 | |
1141 | agg->wait_for_ba = 0; | |
1142 | } else { | |
1143 | /* Two or more frames were attempted; expect block-ack */ | |
1144 | u64 bitmap = 0; | |
1145 | int start = agg->start_idx; | |
1146 | ||
1147 | /* Construct bit-map of pending frames within Tx window */ | |
1148 | for (i = 0; i < agg->frame_count; i++) { | |
1149 | u16 sc; | |
1150 | status = le16_to_cpu(frame_status[i].status); | |
1151 | seq = le16_to_cpu(frame_status[i].sequence); | |
1152 | idx = SEQ_TO_INDEX(seq); | |
1153 | txq_id = SEQ_TO_QUEUE(seq); | |
1154 | ||
1155 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
1156 | AGG_TX_STATE_ABORT_MSK)) | |
1157 | continue; | |
1158 | ||
1159 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", | |
1160 | agg->frame_count, txq_id, idx); | |
1161 | ||
1162 | hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); | |
1163 | ||
1164 | sc = le16_to_cpu(hdr->seq_ctrl); | |
1165 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
1166 | IWL_ERROR("BUG_ON idx doesn't match seq control" | |
1167 | " idx=%d, seq_idx=%d, seq=%d\n", | |
1168 | idx, SEQ_TO_SN(sc), | |
1169 | hdr->seq_ctrl); | |
1170 | return -1; | |
1171 | } | |
1172 | ||
1173 | IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", | |
1174 | i, idx, SEQ_TO_SN(sc)); | |
1175 | ||
1176 | sh = idx - start; | |
1177 | if (sh > 64) { | |
1178 | sh = (start - idx) + 0xff; | |
1179 | bitmap = bitmap << sh; | |
1180 | sh = 0; | |
1181 | start = idx; | |
1182 | } else if (sh < -64) | |
1183 | sh = 0xff - (start - idx); | |
1184 | else if (sh < 0) { | |
1185 | sh = start - idx; | |
1186 | start = idx; | |
1187 | bitmap = bitmap << sh; | |
1188 | sh = 0; | |
1189 | } | |
4aa41f12 EG |
1190 | bitmap |= 1ULL << sh; |
1191 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", | |
1192 | start, (unsigned long long)bitmap); | |
e532fa0e RR |
1193 | } |
1194 | ||
1195 | agg->bitmap = bitmap; | |
1196 | agg->start_idx = start; | |
e532fa0e RR |
1197 | IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", |
1198 | agg->frame_count, agg->start_idx, | |
1199 | (unsigned long long)agg->bitmap); | |
1200 | ||
1201 | if (bitmap) | |
1202 | agg->wait_for_ba = 1; | |
1203 | } | |
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | static void iwl5000_rx_reply_tx(struct iwl_priv *priv, | |
1208 | struct iwl_rx_mem_buffer *rxb) | |
1209 | { | |
1210 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1211 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
1212 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1213 | int index = SEQ_TO_INDEX(sequence); | |
1214 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1215 | struct ieee80211_tx_info *info; | |
1216 | struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; | |
1217 | u32 status = le16_to_cpu(tx_resp->status.status); | |
3fd07a1e TW |
1218 | int tid; |
1219 | int sta_id; | |
1220 | int freed; | |
e532fa0e RR |
1221 | |
1222 | if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { | |
1223 | IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " | |
1224 | "is out of range [0-%d] %d %d\n", txq_id, | |
1225 | index, txq->q.n_bd, txq->q.write_ptr, | |
1226 | txq->q.read_ptr); | |
1227 | return; | |
1228 | } | |
1229 | ||
1230 | info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); | |
1231 | memset(&info->status, 0, sizeof(info->status)); | |
1232 | ||
3fd07a1e TW |
1233 | tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; |
1234 | sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; | |
e532fa0e RR |
1235 | |
1236 | if (txq->sched_retry) { | |
1237 | const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); | |
1238 | struct iwl_ht_agg *agg = NULL; | |
1239 | ||
e532fa0e RR |
1240 | agg = &priv->stations[sta_id].tid[tid].agg; |
1241 | ||
25a6572c | 1242 | iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); |
e532fa0e | 1243 | |
3235427e RR |
1244 | /* check if BAR is needed */ |
1245 | if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) | |
1246 | info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
e532fa0e RR |
1247 | |
1248 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { | |
e532fa0e | 1249 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); |
3fd07a1e TW |
1250 | IWL_DEBUG_TX_REPLY("Retry scheduler reclaim " |
1251 | "scd_ssn=%d idx=%d txq=%d swq=%d\n", | |
1252 | scd_ssn , index, txq_id, txq->swq_id); | |
1253 | ||
17b88929 | 1254 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
e532fa0e RR |
1255 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
1256 | ||
3fd07a1e TW |
1257 | if (priv->mac80211_registered && |
1258 | (iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1259 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { | |
e532fa0e RR |
1260 | if (agg->state == IWL_AGG_OFF) |
1261 | ieee80211_wake_queue(priv->hw, txq_id); | |
1262 | else | |
3fd07a1e TW |
1263 | ieee80211_wake_queue(priv->hw, |
1264 | txq->swq_id); | |
e532fa0e | 1265 | } |
e532fa0e RR |
1266 | } |
1267 | } else { | |
3fd07a1e TW |
1268 | BUG_ON(txq_id != txq->swq_id); |
1269 | ||
e6a9854b | 1270 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
3fd07a1e TW |
1271 | info->flags |= iwl_is_tx_success(status) ? |
1272 | IEEE80211_TX_STAT_ACK : 0; | |
e7d326ac | 1273 | iwl_hwrate_to_tx_control(priv, |
4f85f5b3 RR |
1274 | le32_to_cpu(tx_resp->rate_n_flags), |
1275 | info); | |
1276 | ||
3fd07a1e TW |
1277 | IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags " |
1278 | "0x%x retries %d\n", | |
1279 | txq_id, | |
1280 | iwl_get_tx_fail_reason(status), status, | |
1281 | le32_to_cpu(tx_resp->rate_n_flags), | |
1282 | tx_resp->failure_frame); | |
4f85f5b3 | 1283 | |
3fd07a1e TW |
1284 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
1285 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) | |
e532fa0e | 1286 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
3fd07a1e TW |
1287 | |
1288 | if (priv->mac80211_registered && | |
1289 | (iwl_queue_space(&txq->q) > txq->q.low_mark)) | |
e532fa0e | 1290 | ieee80211_wake_queue(priv->hw, txq_id); |
e532fa0e | 1291 | } |
e532fa0e | 1292 | |
3fd07a1e TW |
1293 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) |
1294 | iwl_txq_check_empty(priv, sta_id, tid, txq_id); | |
1295 | ||
e532fa0e RR |
1296 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) |
1297 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); | |
1298 | } | |
1299 | ||
a96a27f9 | 1300 | /* Currently 5000 is the superset of everything */ |
c1adf9fb GG |
1301 | static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) |
1302 | { | |
1303 | return len; | |
1304 | } | |
1305 | ||
203566f3 EG |
1306 | static void iwl5000_setup_deferred_work(struct iwl_priv *priv) |
1307 | { | |
1308 | /* in 5000 the tx power calibration is done in uCode */ | |
1309 | priv->disable_tx_power_cal = 1; | |
1310 | } | |
1311 | ||
b600e4e1 RR |
1312 | static void iwl5000_rx_handler_setup(struct iwl_priv *priv) |
1313 | { | |
7c616cba TW |
1314 | /* init calibration handlers */ |
1315 | priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = | |
1316 | iwl5000_rx_calib_result; | |
1317 | priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = | |
1318 | iwl5000_rx_calib_complete; | |
e532fa0e | 1319 | priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; |
b600e4e1 RR |
1320 | } |
1321 | ||
7c616cba | 1322 | |
87283cc1 RR |
1323 | static int iwl5000_hw_valid_rtc_data_addr(u32 addr) |
1324 | { | |
1325 | return (addr >= RTC_DATA_LOWER_BOUND) && | |
1326 | (addr < IWL50_RTC_DATA_UPPER_BOUND); | |
1327 | } | |
1328 | ||
fe7a90c2 RR |
1329 | static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) |
1330 | { | |
1331 | int ret = 0; | |
1332 | struct iwl5000_rxon_assoc_cmd rxon_assoc; | |
1333 | const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; | |
1334 | const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; | |
1335 | ||
1336 | if ((rxon1->flags == rxon2->flags) && | |
1337 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1338 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1339 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
1340 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
1341 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
1342 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
1343 | (rxon1->ofdm_ht_triple_stream_basic_rates == | |
1344 | rxon2->ofdm_ht_triple_stream_basic_rates) && | |
1345 | (rxon1->acquisition_data == rxon2->acquisition_data) && | |
1346 | (rxon1->rx_chain == rxon2->rx_chain) && | |
1347 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
1348 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
1349 | return 0; | |
1350 | } | |
1351 | ||
1352 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1353 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1354 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1355 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1356 | rxon_assoc.reserved1 = 0; | |
1357 | rxon_assoc.reserved2 = 0; | |
1358 | rxon_assoc.reserved3 = 0; | |
1359 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
1360 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
1361 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
1362 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
1363 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
1364 | rxon_assoc.ofdm_ht_triple_stream_basic_rates = | |
1365 | priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; | |
1366 | rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; | |
1367 | ||
1368 | ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, | |
1369 | sizeof(rxon_assoc), &rxon_assoc, NULL); | |
1370 | if (ret) | |
1371 | return ret; | |
1372 | ||
1373 | return ret; | |
1374 | } | |
630fe9b6 TW |
1375 | static int iwl5000_send_tx_power(struct iwl_priv *priv) |
1376 | { | |
1377 | struct iwl5000_tx_power_dbm_cmd tx_power_cmd; | |
1378 | ||
1379 | /* half dBm need to multiply */ | |
1380 | tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); | |
853554ac | 1381 | tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; |
630fe9b6 TW |
1382 | tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; |
1383 | return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD, | |
1384 | sizeof(tx_power_cmd), &tx_power_cmd, | |
1385 | NULL); | |
1386 | } | |
1387 | ||
5225640b | 1388 | static void iwl5000_temperature(struct iwl_priv *priv) |
8f91aecb EG |
1389 | { |
1390 | /* store temperature from statistics (in Celsius) */ | |
5225640b | 1391 | priv->temperature = le32_to_cpu(priv->statistics.general.temperature); |
8f91aecb | 1392 | } |
fe7a90c2 | 1393 | |
caab8f1a TW |
1394 | /* Calc max signal level (dBm) among 3 possible receivers */ |
1395 | static int iwl5000_calc_rssi(struct iwl_priv *priv, | |
1396 | struct iwl_rx_phy_res *rx_resp) | |
1397 | { | |
1398 | /* data from PHY/DSP regarding signal strength, etc., | |
1399 | * contents are always there, not configurable by host | |
1400 | */ | |
1401 | struct iwl5000_non_cfg_phy *ncphy = | |
1402 | (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | |
1403 | u32 val, rssi_a, rssi_b, rssi_c, max_rssi; | |
1404 | u8 agc; | |
1405 | ||
1406 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); | |
1407 | agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; | |
1408 | ||
1409 | /* Find max rssi among 3 possible receivers. | |
1410 | * These values are measured by the digital signal processor (DSP). | |
1411 | * They should stay fairly constant even as the signal strength varies, | |
1412 | * if the radio's automatic gain control (AGC) is working right. | |
1413 | * AGC value (see below) will provide the "interesting" info. | |
1414 | */ | |
1415 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); | |
1416 | rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; | |
1417 | rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; | |
1418 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); | |
1419 | rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; | |
1420 | ||
1421 | max_rssi = max_t(u32, rssi_a, rssi_b); | |
1422 | max_rssi = max_t(u32, max_rssi, rssi_c); | |
1423 | ||
1424 | IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", | |
1425 | rssi_a, rssi_b, rssi_c, max_rssi, agc); | |
1426 | ||
1427 | /* dBm = max_rssi dB - agc dB - constant. | |
1428 | * Higher AGC (higher radio gain) means lower signal. */ | |
1429 | return max_rssi - agc - IWL_RSSI_OFFSET; | |
1430 | } | |
1431 | ||
da8dec29 | 1432 | static struct iwl_hcmd_ops iwl5000_hcmd = { |
fe7a90c2 | 1433 | .rxon_assoc = iwl5000_send_rxon_assoc, |
da8dec29 TW |
1434 | }; |
1435 | ||
1436 | static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { | |
c1adf9fb | 1437 | .get_hcmd_size = iwl5000_get_hcmd_size, |
2469bf2e | 1438 | .build_addsta_hcmd = iwl5000_build_addsta_hcmd, |
33fd5033 EG |
1439 | .gain_computation = iwl5000_gain_computation, |
1440 | .chain_noise_reset = iwl5000_chain_noise_reset, | |
a326a5d0 | 1441 | .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, |
caab8f1a | 1442 | .calc_rssi = iwl5000_calc_rssi, |
da8dec29 TW |
1443 | }; |
1444 | ||
1445 | static struct iwl_lib_ops iwl5000_lib = { | |
fdd3e8a4 | 1446 | .set_hw_params = iwl5000_hw_set_hw_params, |
7839fc03 | 1447 | .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, |
972cf447 | 1448 | .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, |
da1bc453 | 1449 | .txq_set_sched = iwl5000_txq_set_sched, |
e26e47d9 TW |
1450 | .txq_agg_enable = iwl5000_txq_agg_enable, |
1451 | .txq_agg_disable = iwl5000_txq_agg_disable, | |
b600e4e1 | 1452 | .rx_handler_setup = iwl5000_rx_handler_setup, |
203566f3 | 1453 | .setup_deferred_work = iwl5000_setup_deferred_work, |
87283cc1 | 1454 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
dbb983b7 | 1455 | .load_ucode = iwl5000_load_ucode, |
99da1b48 RR |
1456 | .init_alive_start = iwl5000_init_alive_start, |
1457 | .alive_notify = iwl5000_alive_notify, | |
630fe9b6 | 1458 | .send_tx_power = iwl5000_send_tx_power, |
8f91aecb | 1459 | .temperature = iwl5000_temperature, |
5b9f8cd3 | 1460 | .update_chain_flags = iwl_update_chain_flags, |
30d59260 TW |
1461 | .apm_ops = { |
1462 | .init = iwl5000_apm_init, | |
7f066108 | 1463 | .reset = iwl5000_apm_reset, |
f118a91d | 1464 | .stop = iwl5000_apm_stop, |
5a835353 | 1465 | .config = iwl5000_nic_config, |
5b9f8cd3 | 1466 | .set_pwr_src = iwl_set_pwr_src, |
30d59260 | 1467 | }, |
da8dec29 | 1468 | .eeprom_ops = { |
25ae3986 TW |
1469 | .regulatory_bands = { |
1470 | EEPROM_5000_REG_BAND_1_CHANNELS, | |
1471 | EEPROM_5000_REG_BAND_2_CHANNELS, | |
1472 | EEPROM_5000_REG_BAND_3_CHANNELS, | |
1473 | EEPROM_5000_REG_BAND_4_CHANNELS, | |
1474 | EEPROM_5000_REG_BAND_5_CHANNELS, | |
1475 | EEPROM_5000_REG_BAND_24_FAT_CHANNELS, | |
1476 | EEPROM_5000_REG_BAND_52_FAT_CHANNELS | |
1477 | }, | |
da8dec29 TW |
1478 | .verify_signature = iwlcore_eeprom_verify_signature, |
1479 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
1480 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
0ef2ca67 | 1481 | .calib_version = iwl5000_eeprom_calib_version, |
25ae3986 | 1482 | .query_addr = iwl5000_eeprom_query_addr, |
da8dec29 TW |
1483 | }, |
1484 | }; | |
1485 | ||
1486 | static struct iwl_ops iwl5000_ops = { | |
1487 | .lib = &iwl5000_lib, | |
1488 | .hcmd = &iwl5000_hcmd, | |
1489 | .utils = &iwl5000_hcmd_utils, | |
1490 | }; | |
1491 | ||
5a6a256e TW |
1492 | static struct iwl_mod_params iwl50_mod_params = { |
1493 | .num_of_queues = IWL50_NUM_QUEUES, | |
9f17b318 | 1494 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, |
5a6a256e TW |
1495 | .enable_qos = 1, |
1496 | .amsdu_size_8K = 1, | |
3a1081e8 | 1497 | .restart_fw = 1, |
5a6a256e TW |
1498 | /* the rest are 0 by default */ |
1499 | }; | |
1500 | ||
1501 | ||
1502 | struct iwl_cfg iwl5300_agn_cfg = { | |
1503 | .name = "5300AGN", | |
4e062f99 | 1504 | .fw_name = IWL5000_MODULE_FIRMWARE, |
5a6a256e | 1505 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1506 | .ops = &iwl5000_ops, |
25ae3986 | 1507 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1508 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1509 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
5a6a256e TW |
1510 | .mod_params = &iwl50_mod_params, |
1511 | }; | |
1512 | ||
47408639 EK |
1513 | struct iwl_cfg iwl5100_bg_cfg = { |
1514 | .name = "5100BG", | |
4e062f99 | 1515 | .fw_name = IWL5000_MODULE_FIRMWARE, |
47408639 EK |
1516 | .sku = IWL_SKU_G, |
1517 | .ops = &iwl5000_ops, | |
1518 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1519 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1520 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
47408639 EK |
1521 | .mod_params = &iwl50_mod_params, |
1522 | }; | |
1523 | ||
1524 | struct iwl_cfg iwl5100_abg_cfg = { | |
1525 | .name = "5100ABG", | |
4e062f99 | 1526 | .fw_name = IWL5000_MODULE_FIRMWARE, |
47408639 EK |
1527 | .sku = IWL_SKU_A|IWL_SKU_G, |
1528 | .ops = &iwl5000_ops, | |
1529 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1530 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1531 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
47408639 EK |
1532 | .mod_params = &iwl50_mod_params, |
1533 | }; | |
1534 | ||
5a6a256e TW |
1535 | struct iwl_cfg iwl5100_agn_cfg = { |
1536 | .name = "5100AGN", | |
4e062f99 | 1537 | .fw_name = IWL5000_MODULE_FIRMWARE, |
5a6a256e | 1538 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1539 | .ops = &iwl5000_ops, |
25ae3986 | 1540 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1541 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1542 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
5a6a256e TW |
1543 | .mod_params = &iwl50_mod_params, |
1544 | }; | |
1545 | ||
1546 | struct iwl_cfg iwl5350_agn_cfg = { | |
1547 | .name = "5350AGN", | |
4e062f99 | 1548 | .fw_name = IWL5000_MODULE_FIRMWARE, |
5a6a256e | 1549 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1550 | .ops = &iwl5000_ops, |
25ae3986 | 1551 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1552 | .eeprom_ver = EEPROM_5050_EEPROM_VERSION, |
1553 | .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, | |
5a6a256e TW |
1554 | .mod_params = &iwl50_mod_params, |
1555 | }; | |
1556 | ||
4e062f99 | 1557 | MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE); |
c9f79ed2 | 1558 | |
5a6a256e TW |
1559 | module_param_named(disable50, iwl50_mod_params.disable, int, 0444); |
1560 | MODULE_PARM_DESC(disable50, | |
1561 | "manually disable the 50XX radio (default 0 [radio on])"); | |
1562 | module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); | |
1563 | MODULE_PARM_DESC(swcrypto50, | |
1564 | "using software crypto engine (default 0 [hardware])\n"); | |
1565 | module_param_named(debug50, iwl50_mod_params.debug, int, 0444); | |
1566 | MODULE_PARM_DESC(debug50, "50XX debug output mask"); | |
1567 | module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); | |
1568 | MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); | |
1569 | module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444); | |
1570 | MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality"); | |
49779293 RR |
1571 | module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444); |
1572 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); | |
5a6a256e TW |
1573 | module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); |
1574 | MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); | |
3a1081e8 EK |
1575 | module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); |
1576 | MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); |