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5a6a256e TW |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. |
5a6a256e TW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
23 | * | |
24 | *****************************************************************************/ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
5a6a256e TW |
28 | #include <linux/init.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/wireless.h> | |
35 | #include <net/mac80211.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <asm/unaligned.h> | |
38 | ||
39 | #include "iwl-eeprom.h" | |
3e0d4cb1 | 40 | #include "iwl-dev.h" |
5a6a256e TW |
41 | #include "iwl-core.h" |
42 | #include "iwl-io.h" | |
e26e47d9 | 43 | #include "iwl-sta.h" |
5a6a256e TW |
44 | #include "iwl-helpers.h" |
45 | #include "iwl-5000-hw.h" | |
c0bac76a | 46 | #include "iwl-6000-hw.h" |
5a6a256e | 47 | |
a0987a8d | 48 | /* Highest firmware API version supported */ |
c9d2fbf3 | 49 | #define IWL5000_UCODE_API_MAX 2 |
39e6d225 | 50 | #define IWL5150_UCODE_API_MAX 2 |
5a6a256e | 51 | |
a0987a8d RC |
52 | /* Lowest firmware API version supported */ |
53 | #define IWL5000_UCODE_API_MIN 1 | |
54 | #define IWL5150_UCODE_API_MIN 1 | |
55 | ||
56 | #define IWL5000_FW_PRE "iwlwifi-5000-" | |
57 | #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode" | |
58 | #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api) | |
59 | ||
60 | #define IWL5150_FW_PRE "iwlwifi-5150-" | |
61 | #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode" | |
62 | #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api) | |
4e062f99 | 63 | |
99da1b48 RR |
64 | static const u16 iwl5000_default_queue_to_tx_fifo[] = { |
65 | IWL_TX_FIFO_AC3, | |
66 | IWL_TX_FIFO_AC2, | |
67 | IWL_TX_FIFO_AC1, | |
68 | IWL_TX_FIFO_AC0, | |
69 | IWL50_CMD_FIFO_NUM, | |
70 | IWL_TX_FIFO_HCCA_1, | |
71 | IWL_TX_FIFO_HCCA_2 | |
72 | }; | |
73 | ||
46315e01 TW |
74 | /* FIXME: same implementation as 4965 */ |
75 | static int iwl5000_apm_stop_master(struct iwl_priv *priv) | |
76 | { | |
46315e01 TW |
77 | unsigned long flags; |
78 | ||
79 | spin_lock_irqsave(&priv->lock, flags); | |
80 | ||
81 | /* set stop master bit */ | |
82 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
83 | ||
febf3370 | 84 | iwl_poll_direct_bit(priv, CSR_RESET, |
46315e01 | 85 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); |
46315e01 | 86 | |
46315e01 | 87 | spin_unlock_irqrestore(&priv->lock, flags); |
e1623446 | 88 | IWL_DEBUG_INFO(priv, "stop master\n"); |
46315e01 | 89 | |
febf3370 | 90 | return 0; |
46315e01 TW |
91 | } |
92 | ||
93 | ||
672639de | 94 | int iwl5000_apm_init(struct iwl_priv *priv) |
30d59260 TW |
95 | { |
96 | int ret = 0; | |
97 | ||
98 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
99 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
100 | ||
8f061891 TW |
101 | /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ |
102 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
103 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
104 | ||
a96a27f9 | 105 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ |
4c43e0d0 TW |
106 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); |
107 | ||
108 | /* enable HAP INTA to move device L1a -> L0s */ | |
109 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
110 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
111 | ||
050681b7 JS |
112 | if (priv->cfg->need_pll_cfg) |
113 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); | |
30d59260 TW |
114 | |
115 | /* set "initialization complete" bit to move adapter | |
116 | * D0U* --> D0A* state */ | |
117 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
118 | ||
119 | /* wait for clock stabilization */ | |
73d7b5ac ZY |
120 | ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, |
121 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
30d59260 | 122 | if (ret < 0) { |
e1623446 | 123 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); |
30d59260 TW |
124 | return ret; |
125 | } | |
126 | ||
30d59260 | 127 | /* enable DMA */ |
8f061891 | 128 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
30d59260 TW |
129 | |
130 | udelay(20); | |
131 | ||
8f061891 | 132 | /* disable L1-Active */ |
30d59260 | 133 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
8f061891 | 134 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
30d59260 | 135 | |
30d59260 TW |
136 | return ret; |
137 | } | |
138 | ||
a96a27f9 | 139 | /* FIXME: this is identical to 4965 */ |
672639de | 140 | void iwl5000_apm_stop(struct iwl_priv *priv) |
f118a91d TW |
141 | { |
142 | unsigned long flags; | |
143 | ||
46315e01 | 144 | iwl5000_apm_stop_master(priv); |
f118a91d TW |
145 | |
146 | spin_lock_irqsave(&priv->lock, flags); | |
147 | ||
148 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
149 | ||
150 | udelay(10); | |
151 | ||
1d3e6c61 MA |
152 | /* clear "init complete" move adapter D0A* --> D0U state */ |
153 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
f118a91d TW |
154 | |
155 | spin_unlock_irqrestore(&priv->lock, flags); | |
156 | } | |
157 | ||
158 | ||
672639de | 159 | int iwl5000_apm_reset(struct iwl_priv *priv) |
7f066108 TW |
160 | { |
161 | int ret = 0; | |
7f066108 | 162 | |
46315e01 | 163 | iwl5000_apm_stop_master(priv); |
7f066108 | 164 | |
7f066108 TW |
165 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
166 | ||
167 | udelay(10); | |
168 | ||
169 | ||
170 | /* FIXME: put here L1A -L0S w/a */ | |
171 | ||
050681b7 JS |
172 | if (priv->cfg->need_pll_cfg) |
173 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); | |
7f066108 TW |
174 | |
175 | /* set "initialization complete" bit to move adapter | |
176 | * D0U* --> D0A* state */ | |
177 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
178 | ||
179 | /* wait for clock stabilization */ | |
73d7b5ac ZY |
180 | ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, |
181 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
7f066108 | 182 | if (ret < 0) { |
e1623446 | 183 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); |
7f066108 TW |
184 | goto out; |
185 | } | |
186 | ||
7f066108 TW |
187 | /* enable DMA */ |
188 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
189 | ||
190 | udelay(20); | |
191 | ||
192 | /* disable L1-Active */ | |
193 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | |
194 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
7f066108 | 195 | out: |
7f066108 TW |
196 | |
197 | return ret; | |
198 | } | |
199 | ||
200 | ||
9371d4ed | 201 | /* NIC configuration for 5000 series */ |
672639de | 202 | void iwl5000_nic_config(struct iwl_priv *priv) |
e86fe9f6 TW |
203 | { |
204 | unsigned long flags; | |
205 | u16 radio_cfg; | |
3fdb68de | 206 | u16 lctl; |
e86fe9f6 TW |
207 | |
208 | spin_lock_irqsave(&priv->lock, flags); | |
209 | ||
3fdb68de | 210 | lctl = iwl_pcie_link_ctl(priv); |
e86fe9f6 | 211 | |
3fdb68de TW |
212 | /* HW bug W/A */ |
213 | /* L1-ASPM is enabled by BIOS */ | |
214 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) | |
215 | /* L1-APSM enabled: disable L0S */ | |
8f061891 TW |
216 | iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
217 | else | |
3fdb68de | 218 | /* L1-ASPM disabled: enable L0S */ |
8f061891 | 219 | iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
e86fe9f6 TW |
220 | |
221 | radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); | |
222 | ||
223 | /* write radio config values to register */ | |
9371d4ed | 224 | if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX) |
e86fe9f6 TW |
225 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
226 | EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | | |
227 | EEPROM_RF_CFG_STEP_MSK(radio_cfg) | | |
228 | EEPROM_RF_CFG_DASH_MSK(radio_cfg)); | |
229 | ||
230 | /* set CSR_HW_CONFIG_REG for uCode use */ | |
231 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
232 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | | |
233 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
234 | ||
4c43e0d0 TW |
235 | /* W/A : NIC is stuck in a reset state after Early PCIe power off |
236 | * (PCIe power is lost before PERST# is asserted), | |
237 | * causing ME FW to lose ownership and not being able to obtain it back. | |
238 | */ | |
2d3db679 | 239 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
4c43e0d0 TW |
240 | APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, |
241 | ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); | |
242 | ||
02c06e4a | 243 | |
e86fe9f6 TW |
244 | spin_unlock_irqrestore(&priv->lock, flags); |
245 | } | |
246 | ||
247 | ||
25ae3986 TW |
248 | /* |
249 | * EEPROM | |
250 | */ | |
251 | static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) | |
252 | { | |
253 | u16 offset = 0; | |
254 | ||
255 | if ((address & INDIRECT_ADDRESS) == 0) | |
256 | return address; | |
257 | ||
258 | switch (address & INDIRECT_TYPE_MSK) { | |
259 | case INDIRECT_HOST: | |
260 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); | |
261 | break; | |
262 | case INDIRECT_GENERAL: | |
263 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); | |
264 | break; | |
265 | case INDIRECT_REGULATORY: | |
266 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); | |
267 | break; | |
268 | case INDIRECT_CALIBRATION: | |
269 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); | |
270 | break; | |
271 | case INDIRECT_PROCESS_ADJST: | |
272 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); | |
273 | break; | |
274 | case INDIRECT_OTHERS: | |
275 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); | |
276 | break; | |
277 | default: | |
15b1687c | 278 | IWL_ERR(priv, "illegal indirect type: 0x%X\n", |
25ae3986 TW |
279 | address & INDIRECT_TYPE_MSK); |
280 | break; | |
281 | } | |
282 | ||
283 | /* translate the offset from words to byte */ | |
284 | return (address & ADDRESS_MSK) + (offset << 1); | |
285 | } | |
286 | ||
672639de | 287 | u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) |
f1f69415 | 288 | { |
f1f69415 TW |
289 | struct iwl_eeprom_calib_hdr { |
290 | u8 version; | |
291 | u8 pa_type; | |
292 | u16 voltage; | |
293 | } *hdr; | |
294 | ||
f1f69415 TW |
295 | hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, |
296 | EEPROM_5000_CALIB_ALL); | |
0ef2ca67 | 297 | return hdr->version; |
f1f69415 TW |
298 | |
299 | } | |
300 | ||
33fd5033 EG |
301 | static void iwl5000_gain_computation(struct iwl_priv *priv, |
302 | u32 average_noise[NUM_RX_CHAINS], | |
303 | u16 min_average_noise_antenna_i, | |
304 | u32 min_average_noise) | |
305 | { | |
306 | int i; | |
307 | s32 delta_g; | |
308 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
309 | ||
310 | /* Find Gain Code for the antennas B and C */ | |
311 | for (i = 1; i < NUM_RX_CHAINS; i++) { | |
312 | if ((data->disconn_array[i])) { | |
313 | data->delta_gain_code[i] = 0; | |
314 | continue; | |
315 | } | |
316 | delta_g = (1000 * ((s32)average_noise[0] - | |
317 | (s32)average_noise[i])) / 1500; | |
318 | /* bound gain by 2 bits value max, 3rd bit is sign */ | |
319 | data->delta_gain_code[i] = | |
320 | min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); | |
321 | ||
322 | if (delta_g < 0) | |
323 | /* set negative sign */ | |
324 | data->delta_gain_code[i] |= (1 << 2); | |
325 | } | |
326 | ||
e1623446 | 327 | IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n", |
33fd5033 EG |
328 | data->delta_gain_code[1], data->delta_gain_code[2]); |
329 | ||
330 | if (!data->radio_write) { | |
f69f42a6 | 331 | struct iwl_calib_chain_noise_gain_cmd cmd; |
0d950d84 | 332 | |
33fd5033 EG |
333 | memset(&cmd, 0, sizeof(cmd)); |
334 | ||
0d950d84 TW |
335 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; |
336 | cmd.hdr.first_group = 0; | |
337 | cmd.hdr.groups_num = 1; | |
338 | cmd.hdr.data_valid = 1; | |
33fd5033 EG |
339 | cmd.delta_gain_1 = data->delta_gain_code[1]; |
340 | cmd.delta_gain_2 = data->delta_gain_code[2]; | |
341 | iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, | |
342 | sizeof(cmd), &cmd, NULL); | |
343 | ||
344 | data->radio_write = 1; | |
345 | data->state = IWL_CHAIN_NOISE_CALIBRATED; | |
346 | } | |
347 | ||
348 | data->chain_noise_a = 0; | |
349 | data->chain_noise_b = 0; | |
350 | data->chain_noise_c = 0; | |
351 | data->chain_signal_a = 0; | |
352 | data->chain_signal_b = 0; | |
353 | data->chain_signal_c = 0; | |
354 | data->beacon_count = 0; | |
355 | } | |
356 | ||
357 | static void iwl5000_chain_noise_reset(struct iwl_priv *priv) | |
358 | { | |
359 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
0d950d84 | 360 | int ret; |
33fd5033 EG |
361 | |
362 | if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { | |
f69f42a6 | 363 | struct iwl_calib_chain_noise_reset_cmd cmd; |
33fd5033 | 364 | memset(&cmd, 0, sizeof(cmd)); |
0d950d84 TW |
365 | |
366 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; | |
367 | cmd.hdr.first_group = 0; | |
368 | cmd.hdr.groups_num = 1; | |
369 | cmd.hdr.data_valid = 1; | |
370 | ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, | |
371 | sizeof(cmd), &cmd); | |
372 | if (ret) | |
15b1687c WT |
373 | IWL_ERR(priv, |
374 | "Could not send REPLY_PHY_CALIBRATION_CMD\n"); | |
33fd5033 | 375 | data->state = IWL_CHAIN_NOISE_ACCUMULATE; |
e1623446 | 376 | IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n"); |
33fd5033 EG |
377 | } |
378 | } | |
379 | ||
e8c00dcb | 380 | void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, |
a326a5d0 EG |
381 | __le32 *tx_flags) |
382 | { | |
e6a9854b JB |
383 | if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || |
384 | (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) | |
a326a5d0 EG |
385 | *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; |
386 | else | |
387 | *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; | |
388 | } | |
389 | ||
33fd5033 EG |
390 | static struct iwl_sensitivity_ranges iwl5000_sensitivity = { |
391 | .min_nrg_cck = 95, | |
fe6efb4b | 392 | .max_nrg_cck = 0, /* not used, set to 0 */ |
33fd5033 EG |
393 | .auto_corr_min_ofdm = 90, |
394 | .auto_corr_min_ofdm_mrc = 170, | |
395 | .auto_corr_min_ofdm_x1 = 120, | |
396 | .auto_corr_min_ofdm_mrc_x1 = 240, | |
397 | ||
398 | .auto_corr_max_ofdm = 120, | |
399 | .auto_corr_max_ofdm_mrc = 210, | |
400 | .auto_corr_max_ofdm_x1 = 155, | |
401 | .auto_corr_max_ofdm_mrc_x1 = 290, | |
402 | ||
403 | .auto_corr_min_cck = 125, | |
404 | .auto_corr_max_cck = 200, | |
405 | .auto_corr_min_cck_mrc = 170, | |
406 | .auto_corr_max_cck_mrc = 400, | |
407 | .nrg_th_cck = 95, | |
408 | .nrg_th_ofdm = 95, | |
409 | }; | |
410 | ||
9d67187d WYG |
411 | static struct iwl_sensitivity_ranges iwl5150_sensitivity = { |
412 | .min_nrg_cck = 95, | |
413 | .max_nrg_cck = 0, /* not used, set to 0 */ | |
414 | .auto_corr_min_ofdm = 90, | |
415 | .auto_corr_min_ofdm_mrc = 170, | |
416 | .auto_corr_min_ofdm_x1 = 105, | |
417 | .auto_corr_min_ofdm_mrc_x1 = 220, | |
418 | ||
419 | .auto_corr_max_ofdm = 120, | |
420 | .auto_corr_max_ofdm_mrc = 210, | |
421 | /* max = min for performance bug in 5150 DSP */ | |
422 | .auto_corr_max_ofdm_x1 = 105, | |
423 | .auto_corr_max_ofdm_mrc_x1 = 220, | |
424 | ||
425 | .auto_corr_min_cck = 125, | |
426 | .auto_corr_max_cck = 200, | |
427 | .auto_corr_min_cck_mrc = 170, | |
428 | .auto_corr_max_cck_mrc = 400, | |
429 | .nrg_th_cck = 95, | |
430 | .nrg_th_ofdm = 95, | |
431 | }; | |
432 | ||
672639de | 433 | const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, |
25ae3986 TW |
434 | size_t offset) |
435 | { | |
436 | u32 address = eeprom_indirect_address(priv, offset); | |
437 | BUG_ON(address >= priv->cfg->eeprom_size); | |
438 | return &priv->eeprom[address]; | |
439 | } | |
440 | ||
62161aef | 441 | static void iwl5150_set_ct_threshold(struct iwl_priv *priv) |
339afc89 | 442 | { |
62161aef | 443 | const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF; |
672639de | 444 | s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) - |
62161aef WYG |
445 | iwl_temp_calib_to_offset(priv); |
446 | ||
447 | priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef; | |
448 | } | |
449 | ||
450 | static void iwl5000_set_ct_threshold(struct iwl_priv *priv) | |
451 | { | |
452 | /* want Celsius */ | |
672639de | 453 | priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY; |
339afc89 TW |
454 | } |
455 | ||
7c616cba TW |
456 | /* |
457 | * Calibration | |
458 | */ | |
be5d56ed | 459 | static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) |
7c616cba | 460 | { |
0d950d84 | 461 | struct iwl_calib_xtal_freq_cmd cmd; |
7c616cba TW |
462 | u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); |
463 | ||
0d950d84 TW |
464 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; |
465 | cmd.hdr.first_group = 0; | |
466 | cmd.hdr.groups_num = 1; | |
467 | cmd.hdr.data_valid = 1; | |
468 | cmd.cap_pin1 = (u8)xtal_calib[0]; | |
469 | cmd.cap_pin2 = (u8)xtal_calib[1]; | |
f69f42a6 | 470 | return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], |
0d950d84 | 471 | (u8 *)&cmd, sizeof(cmd)); |
7c616cba TW |
472 | } |
473 | ||
7c616cba TW |
474 | static int iwl5000_send_calib_cfg(struct iwl_priv *priv) |
475 | { | |
f69f42a6 | 476 | struct iwl_calib_cfg_cmd calib_cfg_cmd; |
7c616cba TW |
477 | struct iwl_host_cmd cmd = { |
478 | .id = CALIBRATION_CFG_CMD, | |
f69f42a6 | 479 | .len = sizeof(struct iwl_calib_cfg_cmd), |
7c616cba TW |
480 | .data = &calib_cfg_cmd, |
481 | }; | |
482 | ||
483 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
484 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
485 | calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; | |
486 | calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; | |
487 | calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; | |
488 | ||
489 | return iwl_send_cmd(priv, &cmd); | |
490 | } | |
491 | ||
492 | static void iwl5000_rx_calib_result(struct iwl_priv *priv, | |
493 | struct iwl_rx_mem_buffer *rxb) | |
494 | { | |
495 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; | |
f69f42a6 | 496 | struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; |
396887a2 | 497 | int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
6e21f2c1 | 498 | int index; |
7c616cba TW |
499 | |
500 | /* reduce the size of the length field itself */ | |
501 | len -= 4; | |
502 | ||
6e21f2c1 TW |
503 | /* Define the order in which the results will be sent to the runtime |
504 | * uCode. iwl_send_calib_results sends them in a row according to their | |
505 | * index. We sort them here */ | |
7c616cba | 506 | switch (hdr->op_code) { |
819500c5 TW |
507 | case IWL_PHY_CALIBRATE_DC_CMD: |
508 | index = IWL_CALIB_DC; | |
509 | break; | |
f69f42a6 TW |
510 | case IWL_PHY_CALIBRATE_LO_CMD: |
511 | index = IWL_CALIB_LO; | |
7c616cba | 512 | break; |
f69f42a6 TW |
513 | case IWL_PHY_CALIBRATE_TX_IQ_CMD: |
514 | index = IWL_CALIB_TX_IQ; | |
7c616cba | 515 | break; |
f69f42a6 TW |
516 | case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: |
517 | index = IWL_CALIB_TX_IQ_PERD; | |
7c616cba | 518 | break; |
201706ac TW |
519 | case IWL_PHY_CALIBRATE_BASE_BAND_CMD: |
520 | index = IWL_CALIB_BASE_BAND; | |
521 | break; | |
7c616cba | 522 | default: |
15b1687c | 523 | IWL_ERR(priv, "Unknown calibration notification %d\n", |
7c616cba TW |
524 | hdr->op_code); |
525 | return; | |
526 | } | |
6e21f2c1 | 527 | iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); |
7c616cba TW |
528 | } |
529 | ||
530 | static void iwl5000_rx_calib_complete(struct iwl_priv *priv, | |
531 | struct iwl_rx_mem_buffer *rxb) | |
532 | { | |
e1623446 | 533 | IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n"); |
7c616cba TW |
534 | queue_work(priv->workqueue, &priv->restart); |
535 | } | |
536 | ||
dbb983b7 RR |
537 | /* |
538 | * ucode | |
539 | */ | |
540 | static int iwl5000_load_section(struct iwl_priv *priv, | |
541 | struct fw_desc *image, | |
542 | u32 dst_addr) | |
543 | { | |
dbb983b7 RR |
544 | dma_addr_t phy_addr = image->p_addr; |
545 | u32 byte_cnt = image->len; | |
546 | ||
dbb983b7 RR |
547 | iwl_write_direct32(priv, |
548 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
549 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
550 | ||
551 | iwl_write_direct32(priv, | |
552 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); | |
553 | ||
554 | iwl_write_direct32(priv, | |
555 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
556 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
557 | ||
dbb983b7 | 558 | iwl_write_direct32(priv, |
f0b9f5cb | 559 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
499b1883 | 560 | (iwl_get_dma_hi_addr(phy_addr) |
f0b9f5cb TW |
561 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); |
562 | ||
dbb983b7 RR |
563 | iwl_write_direct32(priv, |
564 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
565 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
566 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
567 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
568 | ||
569 | iwl_write_direct32(priv, | |
570 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
571 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
9c80c502 | 572 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | |
dbb983b7 RR |
573 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); |
574 | ||
dbb983b7 RR |
575 | return 0; |
576 | } | |
577 | ||
578 | static int iwl5000_load_given_ucode(struct iwl_priv *priv, | |
579 | struct fw_desc *inst_image, | |
580 | struct fw_desc *data_image) | |
581 | { | |
582 | int ret = 0; | |
583 | ||
250bdd21 SO |
584 | ret = iwl5000_load_section(priv, inst_image, |
585 | IWL50_RTC_INST_LOWER_BOUND); | |
dbb983b7 RR |
586 | if (ret) |
587 | return ret; | |
588 | ||
e1623446 | 589 | IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n"); |
dbb983b7 | 590 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
9c80c502 | 591 | priv->ucode_write_complete, 5 * HZ); |
dbb983b7 | 592 | if (ret == -ERESTARTSYS) { |
15b1687c | 593 | IWL_ERR(priv, "Could not load the INST uCode section due " |
dbb983b7 RR |
594 | "to interrupt\n"); |
595 | return ret; | |
596 | } | |
597 | if (!ret) { | |
15b1687c | 598 | IWL_ERR(priv, "Could not load the INST uCode section\n"); |
dbb983b7 RR |
599 | return -ETIMEDOUT; |
600 | } | |
601 | ||
602 | priv->ucode_write_complete = 0; | |
603 | ||
604 | ret = iwl5000_load_section( | |
250bdd21 | 605 | priv, data_image, IWL50_RTC_DATA_LOWER_BOUND); |
dbb983b7 RR |
606 | if (ret) |
607 | return ret; | |
608 | ||
e1623446 | 609 | IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n"); |
dbb983b7 RR |
610 | |
611 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
612 | priv->ucode_write_complete, 5 * HZ); | |
613 | if (ret == -ERESTARTSYS) { | |
15b1687c | 614 | IWL_ERR(priv, "Could not load the INST uCode section due " |
dbb983b7 RR |
615 | "to interrupt\n"); |
616 | return ret; | |
617 | } else if (!ret) { | |
15b1687c | 618 | IWL_ERR(priv, "Could not load the DATA uCode section\n"); |
dbb983b7 RR |
619 | return -ETIMEDOUT; |
620 | } else | |
621 | ret = 0; | |
622 | ||
623 | priv->ucode_write_complete = 0; | |
624 | ||
625 | return ret; | |
626 | } | |
627 | ||
672639de | 628 | int iwl5000_load_ucode(struct iwl_priv *priv) |
dbb983b7 RR |
629 | { |
630 | int ret = 0; | |
631 | ||
632 | /* check whether init ucode should be loaded, or rather runtime ucode */ | |
633 | if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { | |
e1623446 | 634 | IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n"); |
dbb983b7 RR |
635 | ret = iwl5000_load_given_ucode(priv, |
636 | &priv->ucode_init, &priv->ucode_init_data); | |
637 | if (!ret) { | |
e1623446 | 638 | IWL_DEBUG_INFO(priv, "Init ucode load complete.\n"); |
dbb983b7 RR |
639 | priv->ucode_type = UCODE_INIT; |
640 | } | |
641 | } else { | |
e1623446 | 642 | IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. " |
dbb983b7 RR |
643 | "Loading runtime ucode...\n"); |
644 | ret = iwl5000_load_given_ucode(priv, | |
645 | &priv->ucode_code, &priv->ucode_data); | |
646 | if (!ret) { | |
e1623446 | 647 | IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n"); |
dbb983b7 RR |
648 | priv->ucode_type = UCODE_RT; |
649 | } | |
650 | } | |
651 | ||
652 | return ret; | |
653 | } | |
654 | ||
672639de | 655 | void iwl5000_init_alive_start(struct iwl_priv *priv) |
99da1b48 RR |
656 | { |
657 | int ret = 0; | |
658 | ||
659 | /* Check alive response for "valid" sign from uCode */ | |
660 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
661 | /* We had an error bringing up the hardware, so take it | |
662 | * all the way back down so we can try again */ | |
e1623446 | 663 | IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); |
99da1b48 RR |
664 | goto restart; |
665 | } | |
666 | ||
667 | /* initialize uCode was loaded... verify inst image. | |
668 | * This is a paranoid check, because we would not have gotten the | |
669 | * "initialize" alive if code weren't properly loaded. */ | |
670 | if (iwl_verify_ucode(priv)) { | |
671 | /* Runtime instruction load was bad; | |
672 | * take it all the way back down so we can try again */ | |
e1623446 | 673 | IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); |
99da1b48 RR |
674 | goto restart; |
675 | } | |
676 | ||
c587de0b | 677 | iwl_clear_stations_table(priv); |
99da1b48 RR |
678 | ret = priv->cfg->ops->lib->alive_notify(priv); |
679 | if (ret) { | |
39aadf8c WT |
680 | IWL_WARN(priv, |
681 | "Could not complete ALIVE transition: %d\n", ret); | |
99da1b48 RR |
682 | goto restart; |
683 | } | |
684 | ||
7c616cba | 685 | iwl5000_send_calib_cfg(priv); |
99da1b48 RR |
686 | return; |
687 | ||
688 | restart: | |
689 | /* real restart (first load init_ucode) */ | |
690 | queue_work(priv->workqueue, &priv->restart); | |
691 | } | |
692 | ||
693 | static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, | |
694 | int txq_id, u32 index) | |
695 | { | |
696 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
697 | (index & 0xff) | (txq_id << 8)); | |
698 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); | |
699 | } | |
700 | ||
701 | static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, | |
702 | struct iwl_tx_queue *txq, | |
703 | int tx_fifo_id, int scd_retry) | |
704 | { | |
705 | int txq_id = txq->q.id; | |
3fd07a1e | 706 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; |
99da1b48 RR |
707 | |
708 | iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
709 | (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
710 | (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | | |
711 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | | |
712 | IWL50_SCD_QUEUE_STTS_REG_MSK); | |
713 | ||
714 | txq->sched_retry = scd_retry; | |
715 | ||
e1623446 | 716 | IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n", |
99da1b48 RR |
717 | active ? "Activate" : "Deactivate", |
718 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); | |
719 | } | |
720 | ||
9636e583 RR |
721 | static int iwl5000_send_wimax_coex(struct iwl_priv *priv) |
722 | { | |
723 | struct iwl_wimax_coex_cmd coex_cmd; | |
724 | ||
725 | memset(&coex_cmd, 0, sizeof(coex_cmd)); | |
726 | ||
727 | return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, | |
728 | sizeof(coex_cmd), &coex_cmd); | |
729 | } | |
730 | ||
672639de | 731 | int iwl5000_alive_notify(struct iwl_priv *priv) |
99da1b48 RR |
732 | { |
733 | u32 a; | |
99da1b48 | 734 | unsigned long flags; |
31a73fe4 | 735 | int i, chan; |
40fc95d5 | 736 | u32 reg_val; |
99da1b48 RR |
737 | |
738 | spin_lock_irqsave(&priv->lock, flags); | |
739 | ||
99da1b48 RR |
740 | priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); |
741 | a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; | |
742 | for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; | |
743 | a += 4) | |
744 | iwl_write_targ_mem(priv, a, 0); | |
745 | for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; | |
746 | a += 4) | |
747 | iwl_write_targ_mem(priv, a, 0); | |
748 | for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) | |
749 | iwl_write_targ_mem(priv, a, 0); | |
750 | ||
751 | iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, | |
4ddbb7d0 | 752 | priv->scd_bc_tbls.dma >> 10); |
31a73fe4 WT |
753 | |
754 | /* Enable DMA channel */ | |
755 | for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++) | |
756 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
757 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
758 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
759 | ||
40fc95d5 WT |
760 | /* Update FH chicken bits */ |
761 | reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); | |
762 | iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, | |
763 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
764 | ||
99da1b48 | 765 | iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, |
4ddbb7d0 | 766 | IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); |
99da1b48 RR |
767 | iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); |
768 | ||
769 | /* initiate the queues */ | |
770 | for (i = 0; i < priv->hw_params.max_txq_num; i++) { | |
771 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); | |
772 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
773 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
774 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); | |
775 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
776 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + | |
777 | sizeof(u32), | |
778 | ((SCD_WIN_SIZE << | |
779 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
780 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
781 | ((SCD_FRAME_LIMIT << | |
782 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
783 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
784 | } | |
785 | ||
786 | iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, | |
da1bc453 | 787 | IWL_MASK(0, priv->hw_params.max_txq_num)); |
99da1b48 | 788 | |
da1bc453 TW |
789 | /* Activate all Tx DMA/FIFO channels */ |
790 | priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); | |
99da1b48 RR |
791 | |
792 | iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); | |
9c80c502 | 793 | |
99da1b48 RR |
794 | /* map qos queues to fifos one-to-one */ |
795 | for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { | |
796 | int ac = iwl5000_default_queue_to_tx_fifo[i]; | |
797 | iwl_txq_ctx_activate(priv, i); | |
798 | iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); | |
799 | } | |
800 | /* TODO - need to initialize those FIFOs inside the loop above, | |
801 | * not only mark them as active */ | |
802 | iwl_txq_ctx_activate(priv, 4); | |
803 | iwl_txq_ctx_activate(priv, 7); | |
804 | iwl_txq_ctx_activate(priv, 8); | |
805 | iwl_txq_ctx_activate(priv, 9); | |
806 | ||
99da1b48 RR |
807 | spin_unlock_irqrestore(&priv->lock, flags); |
808 | ||
7c616cba | 809 | |
9636e583 RR |
810 | iwl5000_send_wimax_coex(priv); |
811 | ||
be5d56ed TW |
812 | iwl5000_set_Xtal_calib(priv); |
813 | iwl_send_calib_results(priv); | |
7c616cba | 814 | |
99da1b48 RR |
815 | return 0; |
816 | } | |
817 | ||
672639de | 818 | int iwl5000_hw_set_hw_params(struct iwl_priv *priv) |
fdd3e8a4 TW |
819 | { |
820 | if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || | |
821 | (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { | |
15b1687c WT |
822 | IWL_ERR(priv, |
823 | "invalid queues_num, should be between %d and %d\n", | |
824 | IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); | |
fdd3e8a4 TW |
825 | return -EINVAL; |
826 | } | |
25ae3986 | 827 | |
fdd3e8a4 | 828 | priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; |
f3f911d1 | 829 | priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; |
4ddbb7d0 TW |
830 | priv->hw_params.scd_bc_tbls_size = |
831 | IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl); | |
a8e74e27 | 832 | priv->hw_params.tfd_size = sizeof(struct iwl_tfd); |
fdd3e8a4 TW |
833 | priv->hw_params.max_stations = IWL5000_STATION_COUNT; |
834 | priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; | |
c0bac76a JS |
835 | |
836 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
837 | case CSR_HW_REV_TYPE_6x00: | |
838 | case CSR_HW_REV_TYPE_6x50: | |
839 | priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE; | |
840 | priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE; | |
841 | break; | |
842 | default: | |
843 | priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; | |
844 | priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; | |
845 | } | |
846 | ||
da154e30 | 847 | priv->hw_params.max_bsm_size = 0; |
7aafef1c | 848 | priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | |
fdd3e8a4 | 849 | BIT(IEEE80211_BAND_5GHZ); |
141c43a3 WT |
850 | priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR; |
851 | ||
c0bac76a JS |
852 | priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); |
853 | priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant); | |
854 | priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant; | |
855 | priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant; | |
c031bf80 | 856 | |
62161aef WYG |
857 | if (priv->cfg->ops->lib->temp_ops.set_ct_kill) |
858 | priv->cfg->ops->lib->temp_ops.set_ct_kill(priv); | |
c031bf80 | 859 | |
9d67187d | 860 | /* Set initial sensitivity parameters */ |
be5d56ed TW |
861 | /* Set initial calibration set */ |
862 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
c0bac76a | 863 | case CSR_HW_REV_TYPE_5150: |
9d67187d | 864 | priv->hw_params.sens = &iwl5150_sensitivity; |
be5d56ed | 865 | priv->hw_params.calib_init_cfg = |
c0bac76a | 866 | BIT(IWL_CALIB_DC) | |
f69f42a6 | 867 | BIT(IWL_CALIB_LO) | |
201706ac | 868 | BIT(IWL_CALIB_TX_IQ) | |
201706ac | 869 | BIT(IWL_CALIB_BASE_BAND); |
c0bac76a | 870 | |
be5d56ed | 871 | break; |
c0bac76a | 872 | default: |
9d67187d | 873 | priv->hw_params.sens = &iwl5000_sensitivity; |
819500c5 | 874 | priv->hw_params.calib_init_cfg = |
c0bac76a | 875 | BIT(IWL_CALIB_XTAL) | |
7470d7f5 WT |
876 | BIT(IWL_CALIB_LO) | |
877 | BIT(IWL_CALIB_TX_IQ) | | |
c0bac76a | 878 | BIT(IWL_CALIB_TX_IQ_PERD) | |
7470d7f5 | 879 | BIT(IWL_CALIB_BASE_BAND); |
be5d56ed TW |
880 | break; |
881 | } | |
882 | ||
fdd3e8a4 TW |
883 | return 0; |
884 | } | |
d4100dd9 | 885 | |
7839fc03 EG |
886 | /** |
887 | * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
888 | */ | |
672639de | 889 | void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, |
16466903 | 890 | struct iwl_tx_queue *txq, |
7839fc03 EG |
891 | u16 byte_cnt) |
892 | { | |
4ddbb7d0 | 893 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab | 894 | int write_ptr = txq->q.write_ptr; |
7839fc03 EG |
895 | int txq_id = txq->q.id; |
896 | u8 sec_ctl = 0; | |
127901ab TW |
897 | u8 sta_id = 0; |
898 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
899 | __le16 bc_ent; | |
7839fc03 | 900 | |
127901ab | 901 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
7839fc03 EG |
902 | |
903 | if (txq_id != IWL_CMD_QUEUE_NUM) { | |
127901ab | 904 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; |
da99c4b6 | 905 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; |
7839fc03 EG |
906 | |
907 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
908 | case TX_CMD_SEC_CCM: | |
909 | len += CCMP_MIC_LEN; | |
910 | break; | |
911 | case TX_CMD_SEC_TKIP: | |
912 | len += TKIP_ICV_LEN; | |
913 | break; | |
914 | case TX_CMD_SEC_WEP: | |
915 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
916 | break; | |
917 | } | |
918 | } | |
919 | ||
127901ab | 920 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); |
7839fc03 | 921 | |
4ddbb7d0 | 922 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; |
7839fc03 | 923 | |
127901ab | 924 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 925 | scd_bc_tbl[txq_id]. |
127901ab | 926 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; |
7839fc03 EG |
927 | } |
928 | ||
672639de | 929 | void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, |
972cf447 TW |
930 | struct iwl_tx_queue *txq) |
931 | { | |
4ddbb7d0 | 932 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab TW |
933 | int txq_id = txq->q.id; |
934 | int read_ptr = txq->q.read_ptr; | |
935 | u8 sta_id = 0; | |
936 | __le16 bc_ent; | |
937 | ||
938 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
972cf447 TW |
939 | |
940 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
127901ab | 941 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
972cf447 | 942 | |
127901ab | 943 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); |
4ddbb7d0 | 944 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; |
972cf447 | 945 | |
127901ab | 946 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 947 | scd_bc_tbl[txq_id]. |
127901ab | 948 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; |
972cf447 TW |
949 | } |
950 | ||
e26e47d9 TW |
951 | static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, |
952 | u16 txq_id) | |
953 | { | |
954 | u32 tbl_dw_addr; | |
955 | u32 tbl_dw; | |
956 | u16 scd_q2ratid; | |
957 | ||
958 | scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
959 | ||
960 | tbl_dw_addr = priv->scd_base_addr + | |
961 | IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); | |
962 | ||
963 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
964 | ||
965 | if (txq_id & 0x1) | |
966 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
967 | else | |
968 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
969 | ||
970 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
971 | ||
972 | return 0; | |
973 | } | |
974 | static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
975 | { | |
976 | /* Simply stop the queue, but don't change any configuration; | |
977 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
978 | iwl_write_prph(priv, | |
979 | IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
980 | (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
981 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
982 | } | |
983 | ||
672639de | 984 | int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, |
e26e47d9 TW |
985 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) |
986 | { | |
987 | unsigned long flags; | |
e26e47d9 TW |
988 | u16 ra_tid; |
989 | ||
9f17b318 TW |
990 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
991 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
39aadf8c WT |
992 | IWL_WARN(priv, |
993 | "queue number out of range: %d, must be %d to %d\n", | |
9f17b318 TW |
994 | txq_id, IWL50_FIRST_AMPDU_QUEUE, |
995 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
996 | return -EINVAL; | |
997 | } | |
e26e47d9 TW |
998 | |
999 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
1000 | ||
1001 | /* Modify device's station table to Tx this TID */ | |
9f58671e | 1002 | iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); |
e26e47d9 TW |
1003 | |
1004 | spin_lock_irqsave(&priv->lock, flags); | |
e26e47d9 TW |
1005 | |
1006 | /* Stop this Tx queue before configuring it */ | |
1007 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); | |
1008 | ||
1009 | /* Map receiver-address / traffic-ID to this queue */ | |
1010 | iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
1011 | ||
1012 | /* Set this queue as a chain-building queue */ | |
1013 | iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); | |
1014 | ||
1015 | /* enable aggregations for the queue */ | |
1016 | iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); | |
1017 | ||
1018 | /* Place first TFD at index corresponding to start sequence number. | |
1019 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
1020 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
1021 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
1022 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
1023 | ||
1024 | /* Set up Tx window size and frame limit for this queue */ | |
1025 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
1026 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + | |
1027 | sizeof(u32), | |
1028 | ((SCD_WIN_SIZE << | |
1029 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1030 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1031 | ((SCD_FRAME_LIMIT << | |
1032 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1033 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
1034 | ||
1035 | iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
1036 | ||
1037 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
1038 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
1039 | ||
e26e47d9 TW |
1040 | spin_unlock_irqrestore(&priv->lock, flags); |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
672639de | 1045 | int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, |
e26e47d9 TW |
1046 | u16 ssn_idx, u8 tx_fifo) |
1047 | { | |
9f17b318 TW |
1048 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
1049 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
a2f1cbeb | 1050 | IWL_ERR(priv, |
39aadf8c | 1051 | "queue number out of range: %d, must be %d to %d\n", |
9f17b318 TW |
1052 | txq_id, IWL50_FIRST_AMPDU_QUEUE, |
1053 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
e26e47d9 TW |
1054 | return -EINVAL; |
1055 | } | |
1056 | ||
e26e47d9 TW |
1057 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); |
1058 | ||
1059 | iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); | |
1060 | ||
1061 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
1062 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
1063 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
1064 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
1065 | ||
1066 | iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
1067 | iwl_txq_ctx_deactivate(priv, txq_id); | |
1068 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
1069 | ||
e26e47d9 TW |
1070 | return 0; |
1071 | } | |
1072 | ||
e8c00dcb | 1073 | u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) |
2469bf2e TW |
1074 | { |
1075 | u16 size = (u16)sizeof(struct iwl_addsta_cmd); | |
c587de0b TW |
1076 | struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data; |
1077 | memcpy(addsta, cmd, size); | |
1078 | /* resrved in 5000 */ | |
1079 | addsta->rate_n_flags = cpu_to_le16(0); | |
2469bf2e TW |
1080 | return size; |
1081 | } | |
1082 | ||
1083 | ||
da1bc453 | 1084 | /* |
a96a27f9 | 1085 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask |
da1bc453 TW |
1086 | * must be called under priv->lock and mac access |
1087 | */ | |
672639de | 1088 | void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) |
5a676bbe | 1089 | { |
da1bc453 | 1090 | iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); |
5a676bbe RR |
1091 | } |
1092 | ||
e532fa0e RR |
1093 | |
1094 | static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) | |
1095 | { | |
3ac7f146 | 1096 | return le32_to_cpup((__le32 *)&tx_resp->status + |
25a6572c | 1097 | tx_resp->frame_count) & MAX_SN; |
e532fa0e RR |
1098 | } |
1099 | ||
1100 | static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, | |
1101 | struct iwl_ht_agg *agg, | |
1102 | struct iwl5000_tx_resp *tx_resp, | |
25a6572c | 1103 | int txq_id, u16 start_idx) |
e532fa0e RR |
1104 | { |
1105 | u16 status; | |
1106 | struct agg_tx_status *frame_status = &tx_resp->status; | |
1107 | struct ieee80211_tx_info *info = NULL; | |
1108 | struct ieee80211_hdr *hdr = NULL; | |
e7d326ac | 1109 | u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); |
25a6572c | 1110 | int i, sh, idx; |
e532fa0e RR |
1111 | u16 seq; |
1112 | ||
1113 | if (agg->wait_for_ba) | |
e1623446 | 1114 | IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n"); |
e532fa0e RR |
1115 | |
1116 | agg->frame_count = tx_resp->frame_count; | |
1117 | agg->start_idx = start_idx; | |
e7d326ac | 1118 | agg->rate_n_flags = rate_n_flags; |
e532fa0e RR |
1119 | agg->bitmap = 0; |
1120 | ||
1121 | /* # frames attempted by Tx command */ | |
1122 | if (agg->frame_count == 1) { | |
1123 | /* Only one frame was attempted; no block-ack will arrive */ | |
1124 | status = le16_to_cpu(frame_status[0].status); | |
25a6572c | 1125 | idx = start_idx; |
e532fa0e RR |
1126 | |
1127 | /* FIXME: code repetition */ | |
e1623446 | 1128 | IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n", |
e532fa0e RR |
1129 | agg->frame_count, agg->start_idx, idx); |
1130 | ||
1131 | info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); | |
e6a9854b | 1132 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
e532fa0e | 1133 | info->flags &= ~IEEE80211_TX_CTL_AMPDU; |
c3056065 | 1134 | info->flags |= iwl_is_tx_success(status) ? |
3fd07a1e | 1135 | IEEE80211_TX_STAT_ACK : 0; |
e7d326ac TW |
1136 | iwl_hwrate_to_tx_control(priv, rate_n_flags, info); |
1137 | ||
e532fa0e RR |
1138 | /* FIXME: code repetition end */ |
1139 | ||
e1623446 | 1140 | IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n", |
e532fa0e | 1141 | status & 0xff, tx_resp->failure_frame); |
e1623446 | 1142 | IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags); |
e532fa0e RR |
1143 | |
1144 | agg->wait_for_ba = 0; | |
1145 | } else { | |
1146 | /* Two or more frames were attempted; expect block-ack */ | |
1147 | u64 bitmap = 0; | |
1148 | int start = agg->start_idx; | |
1149 | ||
1150 | /* Construct bit-map of pending frames within Tx window */ | |
1151 | for (i = 0; i < agg->frame_count; i++) { | |
1152 | u16 sc; | |
1153 | status = le16_to_cpu(frame_status[i].status); | |
1154 | seq = le16_to_cpu(frame_status[i].sequence); | |
1155 | idx = SEQ_TO_INDEX(seq); | |
1156 | txq_id = SEQ_TO_QUEUE(seq); | |
1157 | ||
1158 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
1159 | AGG_TX_STATE_ABORT_MSK)) | |
1160 | continue; | |
1161 | ||
e1623446 | 1162 | IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n", |
e532fa0e RR |
1163 | agg->frame_count, txq_id, idx); |
1164 | ||
1165 | hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); | |
6c6a22e2 SG |
1166 | if (!hdr) { |
1167 | IWL_ERR(priv, | |
1168 | "BUG_ON idx doesn't point to valid skb" | |
1169 | " idx=%d, txq_id=%d\n", idx, txq_id); | |
1170 | return -1; | |
1171 | } | |
e532fa0e RR |
1172 | |
1173 | sc = le16_to_cpu(hdr->seq_ctrl); | |
1174 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
15b1687c WT |
1175 | IWL_ERR(priv, |
1176 | "BUG_ON idx doesn't match seq control" | |
1177 | " idx=%d, seq_idx=%d, seq=%d\n", | |
e532fa0e RR |
1178 | idx, SEQ_TO_SN(sc), |
1179 | hdr->seq_ctrl); | |
1180 | return -1; | |
1181 | } | |
1182 | ||
e1623446 | 1183 | IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n", |
e532fa0e RR |
1184 | i, idx, SEQ_TO_SN(sc)); |
1185 | ||
1186 | sh = idx - start; | |
1187 | if (sh > 64) { | |
1188 | sh = (start - idx) + 0xff; | |
1189 | bitmap = bitmap << sh; | |
1190 | sh = 0; | |
1191 | start = idx; | |
1192 | } else if (sh < -64) | |
1193 | sh = 0xff - (start - idx); | |
1194 | else if (sh < 0) { | |
1195 | sh = start - idx; | |
1196 | start = idx; | |
1197 | bitmap = bitmap << sh; | |
1198 | sh = 0; | |
1199 | } | |
4aa41f12 | 1200 | bitmap |= 1ULL << sh; |
e1623446 | 1201 | IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n", |
4aa41f12 | 1202 | start, (unsigned long long)bitmap); |
e532fa0e RR |
1203 | } |
1204 | ||
1205 | agg->bitmap = bitmap; | |
1206 | agg->start_idx = start; | |
e1623446 | 1207 | IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n", |
e532fa0e RR |
1208 | agg->frame_count, agg->start_idx, |
1209 | (unsigned long long)agg->bitmap); | |
1210 | ||
1211 | if (bitmap) | |
1212 | agg->wait_for_ba = 1; | |
1213 | } | |
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | static void iwl5000_rx_reply_tx(struct iwl_priv *priv, | |
1218 | struct iwl_rx_mem_buffer *rxb) | |
1219 | { | |
1220 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1221 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
1222 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1223 | int index = SEQ_TO_INDEX(sequence); | |
1224 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1225 | struct ieee80211_tx_info *info; | |
1226 | struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; | |
1227 | u32 status = le16_to_cpu(tx_resp->status.status); | |
3fd07a1e TW |
1228 | int tid; |
1229 | int sta_id; | |
1230 | int freed; | |
e532fa0e RR |
1231 | |
1232 | if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { | |
15b1687c | 1233 | IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " |
e532fa0e RR |
1234 | "is out of range [0-%d] %d %d\n", txq_id, |
1235 | index, txq->q.n_bd, txq->q.write_ptr, | |
1236 | txq->q.read_ptr); | |
1237 | return; | |
1238 | } | |
1239 | ||
1240 | info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); | |
1241 | memset(&info->status, 0, sizeof(info->status)); | |
1242 | ||
3fd07a1e TW |
1243 | tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; |
1244 | sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; | |
e532fa0e RR |
1245 | |
1246 | if (txq->sched_retry) { | |
1247 | const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); | |
1248 | struct iwl_ht_agg *agg = NULL; | |
1249 | ||
e532fa0e RR |
1250 | agg = &priv->stations[sta_id].tid[tid].agg; |
1251 | ||
25a6572c | 1252 | iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); |
e532fa0e | 1253 | |
3235427e RR |
1254 | /* check if BAR is needed */ |
1255 | if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) | |
1256 | info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
e532fa0e RR |
1257 | |
1258 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { | |
e532fa0e | 1259 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); |
e1623446 | 1260 | IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim " |
3fd07a1e TW |
1261 | "scd_ssn=%d idx=%d txq=%d swq=%d\n", |
1262 | scd_ssn , index, txq_id, txq->swq_id); | |
1263 | ||
17b88929 | 1264 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
e532fa0e RR |
1265 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
1266 | ||
3fd07a1e TW |
1267 | if (priv->mac80211_registered && |
1268 | (iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1269 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { | |
e532fa0e | 1270 | if (agg->state == IWL_AGG_OFF) |
e4e72fb4 | 1271 | iwl_wake_queue(priv, txq_id); |
e532fa0e | 1272 | else |
e4e72fb4 | 1273 | iwl_wake_queue(priv, txq->swq_id); |
e532fa0e | 1274 | } |
e532fa0e RR |
1275 | } |
1276 | } else { | |
3fd07a1e TW |
1277 | BUG_ON(txq_id != txq->swq_id); |
1278 | ||
e6a9854b | 1279 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
3fd07a1e TW |
1280 | info->flags |= iwl_is_tx_success(status) ? |
1281 | IEEE80211_TX_STAT_ACK : 0; | |
e7d326ac | 1282 | iwl_hwrate_to_tx_control(priv, |
4f85f5b3 RR |
1283 | le32_to_cpu(tx_resp->rate_n_flags), |
1284 | info); | |
1285 | ||
e1623446 | 1286 | IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags " |
3fd07a1e TW |
1287 | "0x%x retries %d\n", |
1288 | txq_id, | |
1289 | iwl_get_tx_fail_reason(status), status, | |
1290 | le32_to_cpu(tx_resp->rate_n_flags), | |
1291 | tx_resp->failure_frame); | |
4f85f5b3 | 1292 | |
3fd07a1e TW |
1293 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
1294 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) | |
e532fa0e | 1295 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
3fd07a1e TW |
1296 | |
1297 | if (priv->mac80211_registered && | |
1298 | (iwl_queue_space(&txq->q) > txq->q.low_mark)) | |
e4e72fb4 | 1299 | iwl_wake_queue(priv, txq_id); |
e532fa0e | 1300 | } |
e532fa0e | 1301 | |
3fd07a1e TW |
1302 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) |
1303 | iwl_txq_check_empty(priv, sta_id, tid, txq_id); | |
1304 | ||
e532fa0e | 1305 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) |
15b1687c | 1306 | IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n"); |
e532fa0e RR |
1307 | } |
1308 | ||
a96a27f9 | 1309 | /* Currently 5000 is the superset of everything */ |
e8c00dcb | 1310 | u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) |
c1adf9fb GG |
1311 | { |
1312 | return len; | |
1313 | } | |
1314 | ||
672639de | 1315 | void iwl5000_setup_deferred_work(struct iwl_priv *priv) |
203566f3 EG |
1316 | { |
1317 | /* in 5000 the tx power calibration is done in uCode */ | |
1318 | priv->disable_tx_power_cal = 1; | |
1319 | } | |
1320 | ||
672639de | 1321 | void iwl5000_rx_handler_setup(struct iwl_priv *priv) |
b600e4e1 | 1322 | { |
7c616cba TW |
1323 | /* init calibration handlers */ |
1324 | priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = | |
1325 | iwl5000_rx_calib_result; | |
1326 | priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = | |
1327 | iwl5000_rx_calib_complete; | |
e532fa0e | 1328 | priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; |
b600e4e1 RR |
1329 | } |
1330 | ||
7c616cba | 1331 | |
672639de | 1332 | int iwl5000_hw_valid_rtc_data_addr(u32 addr) |
87283cc1 | 1333 | { |
250bdd21 | 1334 | return (addr >= IWL50_RTC_DATA_LOWER_BOUND) && |
87283cc1 RR |
1335 | (addr < IWL50_RTC_DATA_UPPER_BOUND); |
1336 | } | |
1337 | ||
fe7a90c2 RR |
1338 | static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) |
1339 | { | |
1340 | int ret = 0; | |
1341 | struct iwl5000_rxon_assoc_cmd rxon_assoc; | |
1342 | const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; | |
1343 | const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; | |
1344 | ||
1345 | if ((rxon1->flags == rxon2->flags) && | |
1346 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1347 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1348 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
1349 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
1350 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
1351 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
1352 | (rxon1->ofdm_ht_triple_stream_basic_rates == | |
1353 | rxon2->ofdm_ht_triple_stream_basic_rates) && | |
1354 | (rxon1->acquisition_data == rxon2->acquisition_data) && | |
1355 | (rxon1->rx_chain == rxon2->rx_chain) && | |
1356 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
e1623446 | 1357 | IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n"); |
fe7a90c2 RR |
1358 | return 0; |
1359 | } | |
1360 | ||
1361 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1362 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1363 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1364 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1365 | rxon_assoc.reserved1 = 0; | |
1366 | rxon_assoc.reserved2 = 0; | |
1367 | rxon_assoc.reserved3 = 0; | |
1368 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
1369 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
1370 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
1371 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
1372 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
1373 | rxon_assoc.ofdm_ht_triple_stream_basic_rates = | |
1374 | priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; | |
1375 | rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; | |
1376 | ||
1377 | ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, | |
1378 | sizeof(rxon_assoc), &rxon_assoc, NULL); | |
1379 | if (ret) | |
1380 | return ret; | |
1381 | ||
1382 | return ret; | |
1383 | } | |
672639de | 1384 | int iwl5000_send_tx_power(struct iwl_priv *priv) |
630fe9b6 TW |
1385 | { |
1386 | struct iwl5000_tx_power_dbm_cmd tx_power_cmd; | |
76a2407a | 1387 | u8 tx_ant_cfg_cmd; |
630fe9b6 TW |
1388 | |
1389 | /* half dBm need to multiply */ | |
1390 | tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); | |
853554ac | 1391 | tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; |
630fe9b6 | 1392 | tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; |
76a2407a JS |
1393 | |
1394 | if (IWL_UCODE_API(priv->ucode_ver) == 1) | |
1395 | tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1; | |
1396 | else | |
1397 | tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD; | |
1398 | ||
1399 | return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd, | |
630fe9b6 TW |
1400 | sizeof(tx_power_cmd), &tx_power_cmd, |
1401 | NULL); | |
1402 | } | |
1403 | ||
672639de | 1404 | void iwl5000_temperature(struct iwl_priv *priv) |
8f91aecb EG |
1405 | { |
1406 | /* store temperature from statistics (in Celsius) */ | |
5225640b | 1407 | priv->temperature = le32_to_cpu(priv->statistics.general.temperature); |
39b73fb1 | 1408 | iwl_tt_handler(priv); |
8f91aecb | 1409 | } |
fe7a90c2 | 1410 | |
62161aef WYG |
1411 | static void iwl5150_temperature(struct iwl_priv *priv) |
1412 | { | |
1413 | u32 vt = 0; | |
1414 | s32 offset = iwl_temp_calib_to_offset(priv); | |
1415 | ||
1416 | vt = le32_to_cpu(priv->statistics.general.temperature); | |
1417 | vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset; | |
1418 | /* now vt hold the temperature in Kelvin */ | |
1419 | priv->temperature = KELVIN_TO_CELSIUS(vt); | |
15993e08 | 1420 | iwl_tt_handler(priv); |
62161aef WYG |
1421 | } |
1422 | ||
caab8f1a | 1423 | /* Calc max signal level (dBm) among 3 possible receivers */ |
e8c00dcb | 1424 | int iwl5000_calc_rssi(struct iwl_priv *priv, |
caab8f1a TW |
1425 | struct iwl_rx_phy_res *rx_resp) |
1426 | { | |
1427 | /* data from PHY/DSP regarding signal strength, etc., | |
1428 | * contents are always there, not configurable by host | |
1429 | */ | |
1430 | struct iwl5000_non_cfg_phy *ncphy = | |
1431 | (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | |
1432 | u32 val, rssi_a, rssi_b, rssi_c, max_rssi; | |
1433 | u8 agc; | |
1434 | ||
1435 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); | |
1436 | agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; | |
1437 | ||
1438 | /* Find max rssi among 3 possible receivers. | |
1439 | * These values are measured by the digital signal processor (DSP). | |
1440 | * They should stay fairly constant even as the signal strength varies, | |
1441 | * if the radio's automatic gain control (AGC) is working right. | |
1442 | * AGC value (see below) will provide the "interesting" info. | |
1443 | */ | |
1444 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); | |
1445 | rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; | |
1446 | rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; | |
1447 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); | |
1448 | rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; | |
1449 | ||
1450 | max_rssi = max_t(u32, rssi_a, rssi_b); | |
1451 | max_rssi = max_t(u32, max_rssi, rssi_c); | |
1452 | ||
e1623446 | 1453 | IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n", |
caab8f1a TW |
1454 | rssi_a, rssi_b, rssi_c, max_rssi, agc); |
1455 | ||
1456 | /* dBm = max_rssi dB - agc dB - constant. | |
1457 | * Higher AGC (higher radio gain) means lower signal. */ | |
250bdd21 | 1458 | return max_rssi - agc - IWL49_RSSI_OFFSET; |
caab8f1a TW |
1459 | } |
1460 | ||
cc0f555d JS |
1461 | #define IWL5000_UCODE_GET(item) \ |
1462 | static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\ | |
1463 | u32 api_ver) \ | |
1464 | { \ | |
1465 | if (api_ver <= 2) \ | |
1466 | return le32_to_cpu(ucode->u.v1.item); \ | |
1467 | return le32_to_cpu(ucode->u.v2.item); \ | |
1468 | } | |
1469 | ||
1470 | static u32 iwl5000_ucode_get_header_size(u32 api_ver) | |
1471 | { | |
1472 | if (api_ver <= 2) | |
1473 | return UCODE_HEADER_SIZE(1); | |
1474 | return UCODE_HEADER_SIZE(2); | |
1475 | } | |
1476 | ||
1477 | static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode, | |
1478 | u32 api_ver) | |
1479 | { | |
1480 | if (api_ver <= 2) | |
1481 | return 0; | |
1482 | return le32_to_cpu(ucode->u.v2.build); | |
1483 | } | |
1484 | ||
1485 | static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode, | |
1486 | u32 api_ver) | |
1487 | { | |
1488 | if (api_ver <= 2) | |
1489 | return (u8 *) ucode->u.v1.data; | |
1490 | return (u8 *) ucode->u.v2.data; | |
1491 | } | |
1492 | ||
1493 | IWL5000_UCODE_GET(inst_size); | |
1494 | IWL5000_UCODE_GET(data_size); | |
1495 | IWL5000_UCODE_GET(init_size); | |
1496 | IWL5000_UCODE_GET(init_data_size); | |
1497 | IWL5000_UCODE_GET(boot_size); | |
1498 | ||
e8c00dcb | 1499 | struct iwl_hcmd_ops iwl5000_hcmd = { |
fe7a90c2 | 1500 | .rxon_assoc = iwl5000_send_rxon_assoc, |
e0158e61 | 1501 | .commit_rxon = iwl_commit_rxon, |
45823531 | 1502 | .set_rxon_chain = iwl_set_rxon_chain, |
da8dec29 TW |
1503 | }; |
1504 | ||
e8c00dcb | 1505 | struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { |
c1adf9fb | 1506 | .get_hcmd_size = iwl5000_get_hcmd_size, |
2469bf2e | 1507 | .build_addsta_hcmd = iwl5000_build_addsta_hcmd, |
33fd5033 EG |
1508 | .gain_computation = iwl5000_gain_computation, |
1509 | .chain_noise_reset = iwl5000_chain_noise_reset, | |
a326a5d0 | 1510 | .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, |
caab8f1a | 1511 | .calc_rssi = iwl5000_calc_rssi, |
da8dec29 TW |
1512 | }; |
1513 | ||
cc0f555d JS |
1514 | struct iwl_ucode_ops iwl5000_ucode = { |
1515 | .get_header_size = iwl5000_ucode_get_header_size, | |
1516 | .get_build = iwl5000_ucode_get_build, | |
1517 | .get_inst_size = iwl5000_ucode_get_inst_size, | |
1518 | .get_data_size = iwl5000_ucode_get_data_size, | |
1519 | .get_init_size = iwl5000_ucode_get_init_size, | |
1520 | .get_init_data_size = iwl5000_ucode_get_init_data_size, | |
1521 | .get_boot_size = iwl5000_ucode_get_boot_size, | |
1522 | .get_data = iwl5000_ucode_get_data, | |
1523 | }; | |
1524 | ||
e8c00dcb | 1525 | struct iwl_lib_ops iwl5000_lib = { |
fdd3e8a4 | 1526 | .set_hw_params = iwl5000_hw_set_hw_params, |
7839fc03 | 1527 | .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, |
972cf447 | 1528 | .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, |
da1bc453 | 1529 | .txq_set_sched = iwl5000_txq_set_sched, |
e26e47d9 TW |
1530 | .txq_agg_enable = iwl5000_txq_agg_enable, |
1531 | .txq_agg_disable = iwl5000_txq_agg_disable, | |
7aaa1d79 SO |
1532 | .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, |
1533 | .txq_free_tfd = iwl_hw_txq_free_tfd, | |
a8e74e27 | 1534 | .txq_init = iwl_hw_tx_queue_init, |
b600e4e1 | 1535 | .rx_handler_setup = iwl5000_rx_handler_setup, |
203566f3 | 1536 | .setup_deferred_work = iwl5000_setup_deferred_work, |
87283cc1 | 1537 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
b7a79404 RC |
1538 | .dump_nic_event_log = iwl_dump_nic_event_log, |
1539 | .dump_nic_error_log = iwl_dump_nic_error_log, | |
dbb983b7 | 1540 | .load_ucode = iwl5000_load_ucode, |
99da1b48 RR |
1541 | .init_alive_start = iwl5000_init_alive_start, |
1542 | .alive_notify = iwl5000_alive_notify, | |
630fe9b6 | 1543 | .send_tx_power = iwl5000_send_tx_power, |
5b9f8cd3 | 1544 | .update_chain_flags = iwl_update_chain_flags, |
30d59260 TW |
1545 | .apm_ops = { |
1546 | .init = iwl5000_apm_init, | |
7f066108 | 1547 | .reset = iwl5000_apm_reset, |
f118a91d | 1548 | .stop = iwl5000_apm_stop, |
5a835353 | 1549 | .config = iwl5000_nic_config, |
5b9f8cd3 | 1550 | .set_pwr_src = iwl_set_pwr_src, |
30d59260 | 1551 | }, |
da8dec29 | 1552 | .eeprom_ops = { |
25ae3986 TW |
1553 | .regulatory_bands = { |
1554 | EEPROM_5000_REG_BAND_1_CHANNELS, | |
1555 | EEPROM_5000_REG_BAND_2_CHANNELS, | |
1556 | EEPROM_5000_REG_BAND_3_CHANNELS, | |
1557 | EEPROM_5000_REG_BAND_4_CHANNELS, | |
1558 | EEPROM_5000_REG_BAND_5_CHANNELS, | |
7aafef1c WYG |
1559 | EEPROM_5000_REG_BAND_24_HT40_CHANNELS, |
1560 | EEPROM_5000_REG_BAND_52_HT40_CHANNELS | |
25ae3986 | 1561 | }, |
da8dec29 TW |
1562 | .verify_signature = iwlcore_eeprom_verify_signature, |
1563 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
1564 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
0ef2ca67 | 1565 | .calib_version = iwl5000_eeprom_calib_version, |
25ae3986 | 1566 | .query_addr = iwl5000_eeprom_query_addr, |
da8dec29 | 1567 | }, |
5bbe233b | 1568 | .post_associate = iwl_post_associate, |
ef850d7c | 1569 | .isr = iwl_isr_ict, |
60690a6a | 1570 | .config_ap = iwl_config_ap, |
62161aef WYG |
1571 | .temp_ops = { |
1572 | .temperature = iwl5000_temperature, | |
1573 | .set_ct_kill = iwl5000_set_ct_threshold, | |
1574 | }, | |
1575 | }; | |
1576 | ||
1577 | static struct iwl_lib_ops iwl5150_lib = { | |
1578 | .set_hw_params = iwl5000_hw_set_hw_params, | |
1579 | .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, | |
1580 | .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, | |
1581 | .txq_set_sched = iwl5000_txq_set_sched, | |
1582 | .txq_agg_enable = iwl5000_txq_agg_enable, | |
1583 | .txq_agg_disable = iwl5000_txq_agg_disable, | |
1584 | .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, | |
1585 | .txq_free_tfd = iwl_hw_txq_free_tfd, | |
1586 | .txq_init = iwl_hw_tx_queue_init, | |
1587 | .rx_handler_setup = iwl5000_rx_handler_setup, | |
1588 | .setup_deferred_work = iwl5000_setup_deferred_work, | |
1589 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, | |
b7a79404 RC |
1590 | .dump_nic_event_log = iwl_dump_nic_event_log, |
1591 | .dump_nic_error_log = iwl_dump_nic_error_log, | |
62161aef WYG |
1592 | .load_ucode = iwl5000_load_ucode, |
1593 | .init_alive_start = iwl5000_init_alive_start, | |
1594 | .alive_notify = iwl5000_alive_notify, | |
1595 | .send_tx_power = iwl5000_send_tx_power, | |
1596 | .update_chain_flags = iwl_update_chain_flags, | |
1597 | .apm_ops = { | |
1598 | .init = iwl5000_apm_init, | |
1599 | .reset = iwl5000_apm_reset, | |
1600 | .stop = iwl5000_apm_stop, | |
1601 | .config = iwl5000_nic_config, | |
1602 | .set_pwr_src = iwl_set_pwr_src, | |
1603 | }, | |
1604 | .eeprom_ops = { | |
1605 | .regulatory_bands = { | |
1606 | EEPROM_5000_REG_BAND_1_CHANNELS, | |
1607 | EEPROM_5000_REG_BAND_2_CHANNELS, | |
1608 | EEPROM_5000_REG_BAND_3_CHANNELS, | |
1609 | EEPROM_5000_REG_BAND_4_CHANNELS, | |
1610 | EEPROM_5000_REG_BAND_5_CHANNELS, | |
7aafef1c WYG |
1611 | EEPROM_5000_REG_BAND_24_HT40_CHANNELS, |
1612 | EEPROM_5000_REG_BAND_52_HT40_CHANNELS | |
62161aef WYG |
1613 | }, |
1614 | .verify_signature = iwlcore_eeprom_verify_signature, | |
1615 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
1616 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
1617 | .calib_version = iwl5000_eeprom_calib_version, | |
1618 | .query_addr = iwl5000_eeprom_query_addr, | |
1619 | }, | |
1620 | .post_associate = iwl_post_associate, | |
ef850d7c | 1621 | .isr = iwl_isr_ict, |
62161aef WYG |
1622 | .config_ap = iwl_config_ap, |
1623 | .temp_ops = { | |
1624 | .temperature = iwl5150_temperature, | |
1625 | .set_ct_kill = iwl5150_set_ct_threshold, | |
1626 | }, | |
da8dec29 TW |
1627 | }; |
1628 | ||
cec2d3f3 | 1629 | struct iwl_ops iwl5000_ops = { |
cc0f555d | 1630 | .ucode = &iwl5000_ucode, |
da8dec29 TW |
1631 | .lib = &iwl5000_lib, |
1632 | .hcmd = &iwl5000_hcmd, | |
1633 | .utils = &iwl5000_hcmd_utils, | |
1634 | }; | |
1635 | ||
62161aef | 1636 | static struct iwl_ops iwl5150_ops = { |
cc0f555d | 1637 | .ucode = &iwl5000_ucode, |
62161aef WYG |
1638 | .lib = &iwl5150_lib, |
1639 | .hcmd = &iwl5000_hcmd, | |
1640 | .utils = &iwl5000_hcmd_utils, | |
62161aef WYG |
1641 | }; |
1642 | ||
cec2d3f3 | 1643 | struct iwl_mod_params iwl50_mod_params = { |
5a6a256e | 1644 | .num_of_queues = IWL50_NUM_QUEUES, |
9f17b318 | 1645 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, |
5a6a256e | 1646 | .amsdu_size_8K = 1, |
3a1081e8 | 1647 | .restart_fw = 1, |
5a6a256e TW |
1648 | /* the rest are 0 by default */ |
1649 | }; | |
1650 | ||
1651 | ||
1652 | struct iwl_cfg iwl5300_agn_cfg = { | |
1653 | .name = "5300AGN", | |
a0987a8d RC |
1654 | .fw_name_pre = IWL5000_FW_PRE, |
1655 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1656 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1657 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1658 | .ops = &iwl5000_ops, |
25ae3986 | 1659 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1660 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1661 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
5a6a256e | 1662 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1663 | .valid_tx_ant = ANT_ABC, |
1664 | .valid_rx_ant = ANT_ABC, | |
050681b7 | 1665 | .need_pll_cfg = true, |
b261793d | 1666 | .ht_greenfield_support = true, |
5a6a256e TW |
1667 | }; |
1668 | ||
47408639 EK |
1669 | struct iwl_cfg iwl5100_bg_cfg = { |
1670 | .name = "5100BG", | |
a0987a8d RC |
1671 | .fw_name_pre = IWL5000_FW_PRE, |
1672 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1673 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
47408639 EK |
1674 | .sku = IWL_SKU_G, |
1675 | .ops = &iwl5000_ops, | |
1676 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1677 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1678 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
47408639 | 1679 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1680 | .valid_tx_ant = ANT_B, |
1681 | .valid_rx_ant = ANT_AB, | |
050681b7 | 1682 | .need_pll_cfg = true, |
b261793d | 1683 | .ht_greenfield_support = true, |
47408639 EK |
1684 | }; |
1685 | ||
1686 | struct iwl_cfg iwl5100_abg_cfg = { | |
1687 | .name = "5100ABG", | |
a0987a8d RC |
1688 | .fw_name_pre = IWL5000_FW_PRE, |
1689 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1690 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
47408639 EK |
1691 | .sku = IWL_SKU_A|IWL_SKU_G, |
1692 | .ops = &iwl5000_ops, | |
1693 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1694 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1695 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
47408639 | 1696 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1697 | .valid_tx_ant = ANT_B, |
1698 | .valid_rx_ant = ANT_AB, | |
050681b7 | 1699 | .need_pll_cfg = true, |
b261793d | 1700 | .ht_greenfield_support = true, |
47408639 EK |
1701 | }; |
1702 | ||
5a6a256e TW |
1703 | struct iwl_cfg iwl5100_agn_cfg = { |
1704 | .name = "5100AGN", | |
a0987a8d RC |
1705 | .fw_name_pre = IWL5000_FW_PRE, |
1706 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1707 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1708 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1709 | .ops = &iwl5000_ops, |
25ae3986 | 1710 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1711 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1712 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
5a6a256e | 1713 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1714 | .valid_tx_ant = ANT_B, |
1715 | .valid_rx_ant = ANT_AB, | |
050681b7 | 1716 | .need_pll_cfg = true, |
b261793d | 1717 | .ht_greenfield_support = true, |
5a6a256e TW |
1718 | }; |
1719 | ||
1720 | struct iwl_cfg iwl5350_agn_cfg = { | |
1721 | .name = "5350AGN", | |
a0987a8d RC |
1722 | .fw_name_pre = IWL5000_FW_PRE, |
1723 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1724 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1725 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1726 | .ops = &iwl5000_ops, |
25ae3986 | 1727 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1728 | .eeprom_ver = EEPROM_5050_EEPROM_VERSION, |
1729 | .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, | |
5a6a256e | 1730 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1731 | .valid_tx_ant = ANT_ABC, |
1732 | .valid_rx_ant = ANT_ABC, | |
050681b7 | 1733 | .need_pll_cfg = true, |
b261793d | 1734 | .ht_greenfield_support = true, |
5a6a256e TW |
1735 | }; |
1736 | ||
7100e924 TW |
1737 | struct iwl_cfg iwl5150_agn_cfg = { |
1738 | .name = "5150AGN", | |
a0987a8d RC |
1739 | .fw_name_pre = IWL5150_FW_PRE, |
1740 | .ucode_api_max = IWL5150_UCODE_API_MAX, | |
1741 | .ucode_api_min = IWL5150_UCODE_API_MIN, | |
7100e924 | 1742 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
62161aef | 1743 | .ops = &iwl5150_ops, |
7100e924 | 1744 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
fd63edba TW |
1745 | .eeprom_ver = EEPROM_5050_EEPROM_VERSION, |
1746 | .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, | |
7100e924 | 1747 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1748 | .valid_tx_ant = ANT_A, |
1749 | .valid_rx_ant = ANT_AB, | |
050681b7 | 1750 | .need_pll_cfg = true, |
b261793d | 1751 | .ht_greenfield_support = true, |
7100e924 TW |
1752 | }; |
1753 | ||
a0987a8d RC |
1754 | MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX)); |
1755 | MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX)); | |
c9f79ed2 | 1756 | |
5a6a256e TW |
1757 | module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); |
1758 | MODULE_PARM_DESC(swcrypto50, | |
1759 | "using software crypto engine (default 0 [hardware])\n"); | |
5a6a256e TW |
1760 | module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); |
1761 | MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); | |
49779293 RR |
1762 | module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444); |
1763 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); | |
5a6a256e TW |
1764 | module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); |
1765 | MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); | |
3a1081e8 EK |
1766 | module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); |
1767 | MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); |