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5a6a256e TW |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
23 | * | |
24 | *****************************************************************************/ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
5a6a256e TW |
28 | #include <linux/init.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/wireless.h> | |
35 | #include <net/mac80211.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <asm/unaligned.h> | |
38 | ||
39 | #include "iwl-eeprom.h" | |
3e0d4cb1 | 40 | #include "iwl-dev.h" |
5a6a256e TW |
41 | #include "iwl-core.h" |
42 | #include "iwl-io.h" | |
e26e47d9 | 43 | #include "iwl-sta.h" |
5a6a256e TW |
44 | #include "iwl-helpers.h" |
45 | #include "iwl-5000-hw.h" | |
46 | ||
a0987a8d RC |
47 | /* Highest firmware API version supported */ |
48 | #define IWL5000_UCODE_API_MAX 1 | |
49 | #define IWL5150_UCODE_API_MAX 1 | |
5a6a256e | 50 | |
a0987a8d RC |
51 | /* Lowest firmware API version supported */ |
52 | #define IWL5000_UCODE_API_MIN 1 | |
53 | #define IWL5150_UCODE_API_MIN 1 | |
54 | ||
55 | #define IWL5000_FW_PRE "iwlwifi-5000-" | |
56 | #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode" | |
57 | #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api) | |
58 | ||
59 | #define IWL5150_FW_PRE "iwlwifi-5150-" | |
60 | #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode" | |
61 | #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api) | |
4e062f99 | 62 | |
99da1b48 RR |
63 | static const u16 iwl5000_default_queue_to_tx_fifo[] = { |
64 | IWL_TX_FIFO_AC3, | |
65 | IWL_TX_FIFO_AC2, | |
66 | IWL_TX_FIFO_AC1, | |
67 | IWL_TX_FIFO_AC0, | |
68 | IWL50_CMD_FIFO_NUM, | |
69 | IWL_TX_FIFO_HCCA_1, | |
70 | IWL_TX_FIFO_HCCA_2 | |
71 | }; | |
72 | ||
46315e01 TW |
73 | /* FIXME: same implementation as 4965 */ |
74 | static int iwl5000_apm_stop_master(struct iwl_priv *priv) | |
75 | { | |
76 | int ret = 0; | |
77 | unsigned long flags; | |
78 | ||
79 | spin_lock_irqsave(&priv->lock, flags); | |
80 | ||
81 | /* set stop master bit */ | |
82 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
83 | ||
73d7b5ac | 84 | ret = iwl_poll_direct_bit(priv, CSR_RESET, |
46315e01 TW |
85 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); |
86 | if (ret < 0) | |
87 | goto out; | |
88 | ||
89 | out: | |
90 | spin_unlock_irqrestore(&priv->lock, flags); | |
91 | IWL_DEBUG_INFO("stop master\n"); | |
92 | ||
93 | return ret; | |
94 | } | |
95 | ||
96 | ||
30d59260 TW |
97 | static int iwl5000_apm_init(struct iwl_priv *priv) |
98 | { | |
99 | int ret = 0; | |
100 | ||
101 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
102 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
103 | ||
8f061891 TW |
104 | /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ |
105 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
106 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
107 | ||
a96a27f9 | 108 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ |
4c43e0d0 TW |
109 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); |
110 | ||
111 | /* enable HAP INTA to move device L1a -> L0s */ | |
112 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
113 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
114 | ||
30d59260 TW |
115 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); |
116 | ||
117 | /* set "initialization complete" bit to move adapter | |
118 | * D0U* --> D0A* state */ | |
119 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
120 | ||
121 | /* wait for clock stabilization */ | |
73d7b5ac ZY |
122 | ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, |
123 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
30d59260 TW |
124 | if (ret < 0) { |
125 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
126 | return ret; | |
127 | } | |
128 | ||
129 | ret = iwl_grab_nic_access(priv); | |
130 | if (ret) | |
131 | return ret; | |
132 | ||
133 | /* enable DMA */ | |
8f061891 | 134 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
30d59260 TW |
135 | |
136 | udelay(20); | |
137 | ||
8f061891 | 138 | /* disable L1-Active */ |
30d59260 | 139 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
8f061891 | 140 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
30d59260 TW |
141 | |
142 | iwl_release_nic_access(priv); | |
143 | ||
144 | return ret; | |
145 | } | |
146 | ||
a96a27f9 | 147 | /* FIXME: this is identical to 4965 */ |
f118a91d TW |
148 | static void iwl5000_apm_stop(struct iwl_priv *priv) |
149 | { | |
150 | unsigned long flags; | |
151 | ||
46315e01 | 152 | iwl5000_apm_stop_master(priv); |
f118a91d TW |
153 | |
154 | spin_lock_irqsave(&priv->lock, flags); | |
155 | ||
156 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
157 | ||
158 | udelay(10); | |
159 | ||
1d3e6c61 MA |
160 | /* clear "init complete" move adapter D0A* --> D0U state */ |
161 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
f118a91d TW |
162 | |
163 | spin_unlock_irqrestore(&priv->lock, flags); | |
164 | } | |
165 | ||
166 | ||
7f066108 TW |
167 | static int iwl5000_apm_reset(struct iwl_priv *priv) |
168 | { | |
169 | int ret = 0; | |
170 | unsigned long flags; | |
171 | ||
46315e01 | 172 | iwl5000_apm_stop_master(priv); |
7f066108 TW |
173 | |
174 | spin_lock_irqsave(&priv->lock, flags); | |
175 | ||
176 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
177 | ||
178 | udelay(10); | |
179 | ||
180 | ||
181 | /* FIXME: put here L1A -L0S w/a */ | |
182 | ||
183 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); | |
184 | ||
185 | /* set "initialization complete" bit to move adapter | |
186 | * D0U* --> D0A* state */ | |
187 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
188 | ||
189 | /* wait for clock stabilization */ | |
73d7b5ac ZY |
190 | ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL, |
191 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
7f066108 TW |
192 | if (ret < 0) { |
193 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
194 | goto out; | |
195 | } | |
196 | ||
197 | ret = iwl_grab_nic_access(priv); | |
198 | if (ret) | |
199 | goto out; | |
200 | ||
201 | /* enable DMA */ | |
202 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
203 | ||
204 | udelay(20); | |
205 | ||
206 | /* disable L1-Active */ | |
207 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | |
208 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
209 | ||
210 | iwl_release_nic_access(priv); | |
211 | ||
212 | out: | |
213 | spin_unlock_irqrestore(&priv->lock, flags); | |
214 | ||
215 | return ret; | |
216 | } | |
217 | ||
218 | ||
5a835353 | 219 | static void iwl5000_nic_config(struct iwl_priv *priv) |
e86fe9f6 TW |
220 | { |
221 | unsigned long flags; | |
222 | u16 radio_cfg; | |
e7b63581 | 223 | u16 link; |
e86fe9f6 TW |
224 | |
225 | spin_lock_irqsave(&priv->lock, flags); | |
226 | ||
e7b63581 | 227 | pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link); |
e86fe9f6 | 228 | |
8f061891 | 229 | /* L1 is enabled by BIOS */ |
e7b63581 | 230 | if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) |
a96a27f9 | 231 | /* disable L0S disabled L1A enabled */ |
8f061891 TW |
232 | iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
233 | else | |
234 | /* L0S enabled L1A disabled */ | |
235 | iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
e86fe9f6 TW |
236 | |
237 | radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); | |
238 | ||
239 | /* write radio config values to register */ | |
240 | if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) | |
241 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
242 | EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | | |
243 | EEPROM_RF_CFG_STEP_MSK(radio_cfg) | | |
244 | EEPROM_RF_CFG_DASH_MSK(radio_cfg)); | |
245 | ||
246 | /* set CSR_HW_CONFIG_REG for uCode use */ | |
247 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
248 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | | |
249 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
250 | ||
4c43e0d0 TW |
251 | /* W/A : NIC is stuck in a reset state after Early PCIe power off |
252 | * (PCIe power is lost before PERST# is asserted), | |
253 | * causing ME FW to lose ownership and not being able to obtain it back. | |
254 | */ | |
2d3db679 TW |
255 | iwl_grab_nic_access(priv); |
256 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
4c43e0d0 TW |
257 | APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, |
258 | ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); | |
2d3db679 | 259 | iwl_release_nic_access(priv); |
4c43e0d0 | 260 | |
e86fe9f6 TW |
261 | spin_unlock_irqrestore(&priv->lock, flags); |
262 | } | |
263 | ||
264 | ||
265 | ||
25ae3986 TW |
266 | /* |
267 | * EEPROM | |
268 | */ | |
269 | static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) | |
270 | { | |
271 | u16 offset = 0; | |
272 | ||
273 | if ((address & INDIRECT_ADDRESS) == 0) | |
274 | return address; | |
275 | ||
276 | switch (address & INDIRECT_TYPE_MSK) { | |
277 | case INDIRECT_HOST: | |
278 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); | |
279 | break; | |
280 | case INDIRECT_GENERAL: | |
281 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); | |
282 | break; | |
283 | case INDIRECT_REGULATORY: | |
284 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); | |
285 | break; | |
286 | case INDIRECT_CALIBRATION: | |
287 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); | |
288 | break; | |
289 | case INDIRECT_PROCESS_ADJST: | |
290 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); | |
291 | break; | |
292 | case INDIRECT_OTHERS: | |
293 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); | |
294 | break; | |
295 | default: | |
296 | IWL_ERROR("illegal indirect type: 0x%X\n", | |
297 | address & INDIRECT_TYPE_MSK); | |
298 | break; | |
299 | } | |
300 | ||
301 | /* translate the offset from words to byte */ | |
302 | return (address & ADDRESS_MSK) + (offset << 1); | |
303 | } | |
304 | ||
0ef2ca67 | 305 | static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) |
f1f69415 | 306 | { |
f1f69415 TW |
307 | struct iwl_eeprom_calib_hdr { |
308 | u8 version; | |
309 | u8 pa_type; | |
310 | u16 voltage; | |
311 | } *hdr; | |
312 | ||
f1f69415 TW |
313 | hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, |
314 | EEPROM_5000_CALIB_ALL); | |
0ef2ca67 | 315 | return hdr->version; |
f1f69415 TW |
316 | |
317 | } | |
318 | ||
33fd5033 EG |
319 | static void iwl5000_gain_computation(struct iwl_priv *priv, |
320 | u32 average_noise[NUM_RX_CHAINS], | |
321 | u16 min_average_noise_antenna_i, | |
322 | u32 min_average_noise) | |
323 | { | |
324 | int i; | |
325 | s32 delta_g; | |
326 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
327 | ||
328 | /* Find Gain Code for the antennas B and C */ | |
329 | for (i = 1; i < NUM_RX_CHAINS; i++) { | |
330 | if ((data->disconn_array[i])) { | |
331 | data->delta_gain_code[i] = 0; | |
332 | continue; | |
333 | } | |
334 | delta_g = (1000 * ((s32)average_noise[0] - | |
335 | (s32)average_noise[i])) / 1500; | |
336 | /* bound gain by 2 bits value max, 3rd bit is sign */ | |
337 | data->delta_gain_code[i] = | |
338 | min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); | |
339 | ||
340 | if (delta_g < 0) | |
341 | /* set negative sign */ | |
342 | data->delta_gain_code[i] |= (1 << 2); | |
343 | } | |
344 | ||
345 | IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n", | |
346 | data->delta_gain_code[1], data->delta_gain_code[2]); | |
347 | ||
348 | if (!data->radio_write) { | |
f69f42a6 | 349 | struct iwl_calib_chain_noise_gain_cmd cmd; |
0d950d84 | 350 | |
33fd5033 EG |
351 | memset(&cmd, 0, sizeof(cmd)); |
352 | ||
0d950d84 TW |
353 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; |
354 | cmd.hdr.first_group = 0; | |
355 | cmd.hdr.groups_num = 1; | |
356 | cmd.hdr.data_valid = 1; | |
33fd5033 EG |
357 | cmd.delta_gain_1 = data->delta_gain_code[1]; |
358 | cmd.delta_gain_2 = data->delta_gain_code[2]; | |
359 | iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, | |
360 | sizeof(cmd), &cmd, NULL); | |
361 | ||
362 | data->radio_write = 1; | |
363 | data->state = IWL_CHAIN_NOISE_CALIBRATED; | |
364 | } | |
365 | ||
366 | data->chain_noise_a = 0; | |
367 | data->chain_noise_b = 0; | |
368 | data->chain_noise_c = 0; | |
369 | data->chain_signal_a = 0; | |
370 | data->chain_signal_b = 0; | |
371 | data->chain_signal_c = 0; | |
372 | data->beacon_count = 0; | |
373 | } | |
374 | ||
375 | static void iwl5000_chain_noise_reset(struct iwl_priv *priv) | |
376 | { | |
377 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
0d950d84 | 378 | int ret; |
33fd5033 EG |
379 | |
380 | if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { | |
f69f42a6 | 381 | struct iwl_calib_chain_noise_reset_cmd cmd; |
33fd5033 | 382 | memset(&cmd, 0, sizeof(cmd)); |
0d950d84 TW |
383 | |
384 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; | |
385 | cmd.hdr.first_group = 0; | |
386 | cmd.hdr.groups_num = 1; | |
387 | cmd.hdr.data_valid = 1; | |
388 | ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, | |
389 | sizeof(cmd), &cmd); | |
390 | if (ret) | |
33fd5033 EG |
391 | IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); |
392 | data->state = IWL_CHAIN_NOISE_ACCUMULATE; | |
393 | IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); | |
394 | } | |
395 | } | |
396 | ||
a326a5d0 EG |
397 | static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, |
398 | __le32 *tx_flags) | |
399 | { | |
e6a9854b JB |
400 | if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || |
401 | (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) | |
a326a5d0 EG |
402 | *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; |
403 | else | |
404 | *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; | |
405 | } | |
406 | ||
33fd5033 EG |
407 | static struct iwl_sensitivity_ranges iwl5000_sensitivity = { |
408 | .min_nrg_cck = 95, | |
409 | .max_nrg_cck = 0, | |
410 | .auto_corr_min_ofdm = 90, | |
411 | .auto_corr_min_ofdm_mrc = 170, | |
412 | .auto_corr_min_ofdm_x1 = 120, | |
413 | .auto_corr_min_ofdm_mrc_x1 = 240, | |
414 | ||
415 | .auto_corr_max_ofdm = 120, | |
416 | .auto_corr_max_ofdm_mrc = 210, | |
417 | .auto_corr_max_ofdm_x1 = 155, | |
418 | .auto_corr_max_ofdm_mrc_x1 = 290, | |
419 | ||
420 | .auto_corr_min_cck = 125, | |
421 | .auto_corr_max_cck = 200, | |
422 | .auto_corr_min_cck_mrc = 170, | |
423 | .auto_corr_max_cck_mrc = 400, | |
424 | .nrg_th_cck = 95, | |
425 | .nrg_th_ofdm = 95, | |
426 | }; | |
427 | ||
25ae3986 TW |
428 | static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, |
429 | size_t offset) | |
430 | { | |
431 | u32 address = eeprom_indirect_address(priv, offset); | |
432 | BUG_ON(address >= priv->cfg->eeprom_size); | |
433 | return &priv->eeprom[address]; | |
434 | } | |
435 | ||
339afc89 TW |
436 | static s32 iwl5150_get_ct_threshold(struct iwl_priv *priv) |
437 | { | |
438 | const s32 volt2temp_coef = -5; | |
439 | u16 *temp_calib = (u16 *)iwl_eeprom_query_addr(priv, | |
440 | EEPROM_5000_TEMPERATURE); | |
441 | /* offset = temperate - voltage / coef */ | |
442 | s32 offset = temp_calib[0] - temp_calib[1] / volt2temp_coef; | |
443 | s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) - offset; | |
444 | return threshold * volt2temp_coef; | |
445 | } | |
446 | ||
7c616cba TW |
447 | /* |
448 | * Calibration | |
449 | */ | |
be5d56ed | 450 | static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) |
7c616cba | 451 | { |
0d950d84 | 452 | struct iwl_calib_xtal_freq_cmd cmd; |
7c616cba TW |
453 | u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); |
454 | ||
0d950d84 TW |
455 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; |
456 | cmd.hdr.first_group = 0; | |
457 | cmd.hdr.groups_num = 1; | |
458 | cmd.hdr.data_valid = 1; | |
459 | cmd.cap_pin1 = (u8)xtal_calib[0]; | |
460 | cmd.cap_pin2 = (u8)xtal_calib[1]; | |
f69f42a6 | 461 | return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], |
0d950d84 | 462 | (u8 *)&cmd, sizeof(cmd)); |
7c616cba TW |
463 | } |
464 | ||
7c616cba TW |
465 | static int iwl5000_send_calib_cfg(struct iwl_priv *priv) |
466 | { | |
f69f42a6 | 467 | struct iwl_calib_cfg_cmd calib_cfg_cmd; |
7c616cba TW |
468 | struct iwl_host_cmd cmd = { |
469 | .id = CALIBRATION_CFG_CMD, | |
f69f42a6 | 470 | .len = sizeof(struct iwl_calib_cfg_cmd), |
7c616cba TW |
471 | .data = &calib_cfg_cmd, |
472 | }; | |
473 | ||
474 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
475 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
476 | calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; | |
477 | calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; | |
478 | calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; | |
479 | ||
480 | return iwl_send_cmd(priv, &cmd); | |
481 | } | |
482 | ||
483 | static void iwl5000_rx_calib_result(struct iwl_priv *priv, | |
484 | struct iwl_rx_mem_buffer *rxb) | |
485 | { | |
486 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; | |
f69f42a6 | 487 | struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; |
7c616cba | 488 | int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; |
6e21f2c1 | 489 | int index; |
7c616cba TW |
490 | |
491 | /* reduce the size of the length field itself */ | |
492 | len -= 4; | |
493 | ||
6e21f2c1 TW |
494 | /* Define the order in which the results will be sent to the runtime |
495 | * uCode. iwl_send_calib_results sends them in a row according to their | |
496 | * index. We sort them here */ | |
7c616cba | 497 | switch (hdr->op_code) { |
819500c5 TW |
498 | case IWL_PHY_CALIBRATE_DC_CMD: |
499 | index = IWL_CALIB_DC; | |
500 | break; | |
f69f42a6 TW |
501 | case IWL_PHY_CALIBRATE_LO_CMD: |
502 | index = IWL_CALIB_LO; | |
7c616cba | 503 | break; |
f69f42a6 TW |
504 | case IWL_PHY_CALIBRATE_TX_IQ_CMD: |
505 | index = IWL_CALIB_TX_IQ; | |
7c616cba | 506 | break; |
f69f42a6 TW |
507 | case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: |
508 | index = IWL_CALIB_TX_IQ_PERD; | |
7c616cba | 509 | break; |
201706ac TW |
510 | case IWL_PHY_CALIBRATE_BASE_BAND_CMD: |
511 | index = IWL_CALIB_BASE_BAND; | |
512 | break; | |
7c616cba TW |
513 | default: |
514 | IWL_ERROR("Unknown calibration notification %d\n", | |
515 | hdr->op_code); | |
516 | return; | |
517 | } | |
6e21f2c1 | 518 | iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); |
7c616cba TW |
519 | } |
520 | ||
521 | static void iwl5000_rx_calib_complete(struct iwl_priv *priv, | |
522 | struct iwl_rx_mem_buffer *rxb) | |
523 | { | |
524 | IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n"); | |
525 | queue_work(priv->workqueue, &priv->restart); | |
526 | } | |
527 | ||
dbb983b7 RR |
528 | /* |
529 | * ucode | |
530 | */ | |
531 | static int iwl5000_load_section(struct iwl_priv *priv, | |
532 | struct fw_desc *image, | |
533 | u32 dst_addr) | |
534 | { | |
535 | int ret = 0; | |
536 | unsigned long flags; | |
537 | ||
538 | dma_addr_t phy_addr = image->p_addr; | |
539 | u32 byte_cnt = image->len; | |
540 | ||
541 | spin_lock_irqsave(&priv->lock, flags); | |
542 | ret = iwl_grab_nic_access(priv); | |
543 | if (ret) { | |
544 | spin_unlock_irqrestore(&priv->lock, flags); | |
545 | return ret; | |
546 | } | |
547 | ||
548 | iwl_write_direct32(priv, | |
549 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
550 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
551 | ||
552 | iwl_write_direct32(priv, | |
553 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); | |
554 | ||
555 | iwl_write_direct32(priv, | |
556 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
557 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
558 | ||
dbb983b7 | 559 | iwl_write_direct32(priv, |
f0b9f5cb | 560 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
499b1883 | 561 | (iwl_get_dma_hi_addr(phy_addr) |
f0b9f5cb TW |
562 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); |
563 | ||
dbb983b7 RR |
564 | iwl_write_direct32(priv, |
565 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
566 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
567 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
568 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
569 | ||
570 | iwl_write_direct32(priv, | |
571 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
572 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
9c80c502 | 573 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | |
dbb983b7 RR |
574 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); |
575 | ||
576 | iwl_release_nic_access(priv); | |
577 | spin_unlock_irqrestore(&priv->lock, flags); | |
578 | return 0; | |
579 | } | |
580 | ||
581 | static int iwl5000_load_given_ucode(struct iwl_priv *priv, | |
582 | struct fw_desc *inst_image, | |
583 | struct fw_desc *data_image) | |
584 | { | |
585 | int ret = 0; | |
586 | ||
9c80c502 | 587 | ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND); |
dbb983b7 RR |
588 | if (ret) |
589 | return ret; | |
590 | ||
591 | IWL_DEBUG_INFO("INST uCode section being loaded...\n"); | |
592 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
9c80c502 | 593 | priv->ucode_write_complete, 5 * HZ); |
dbb983b7 RR |
594 | if (ret == -ERESTARTSYS) { |
595 | IWL_ERROR("Could not load the INST uCode section due " | |
596 | "to interrupt\n"); | |
597 | return ret; | |
598 | } | |
599 | if (!ret) { | |
600 | IWL_ERROR("Could not load the INST uCode section\n"); | |
601 | return -ETIMEDOUT; | |
602 | } | |
603 | ||
604 | priv->ucode_write_complete = 0; | |
605 | ||
606 | ret = iwl5000_load_section( | |
607 | priv, data_image, RTC_DATA_LOWER_BOUND); | |
608 | if (ret) | |
609 | return ret; | |
610 | ||
611 | IWL_DEBUG_INFO("DATA uCode section being loaded...\n"); | |
612 | ||
613 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
614 | priv->ucode_write_complete, 5 * HZ); | |
615 | if (ret == -ERESTARTSYS) { | |
616 | IWL_ERROR("Could not load the INST uCode section due " | |
617 | "to interrupt\n"); | |
618 | return ret; | |
619 | } else if (!ret) { | |
620 | IWL_ERROR("Could not load the DATA uCode section\n"); | |
621 | return -ETIMEDOUT; | |
622 | } else | |
623 | ret = 0; | |
624 | ||
625 | priv->ucode_write_complete = 0; | |
626 | ||
627 | return ret; | |
628 | } | |
629 | ||
630 | static int iwl5000_load_ucode(struct iwl_priv *priv) | |
631 | { | |
632 | int ret = 0; | |
633 | ||
634 | /* check whether init ucode should be loaded, or rather runtime ucode */ | |
635 | if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { | |
636 | IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n"); | |
637 | ret = iwl5000_load_given_ucode(priv, | |
638 | &priv->ucode_init, &priv->ucode_init_data); | |
639 | if (!ret) { | |
640 | IWL_DEBUG_INFO("Init ucode load complete.\n"); | |
641 | priv->ucode_type = UCODE_INIT; | |
642 | } | |
643 | } else { | |
644 | IWL_DEBUG_INFO("Init ucode not found, or already loaded. " | |
645 | "Loading runtime ucode...\n"); | |
646 | ret = iwl5000_load_given_ucode(priv, | |
647 | &priv->ucode_code, &priv->ucode_data); | |
648 | if (!ret) { | |
649 | IWL_DEBUG_INFO("Runtime ucode load complete.\n"); | |
650 | priv->ucode_type = UCODE_RT; | |
651 | } | |
652 | } | |
653 | ||
654 | return ret; | |
655 | } | |
656 | ||
99da1b48 RR |
657 | static void iwl5000_init_alive_start(struct iwl_priv *priv) |
658 | { | |
659 | int ret = 0; | |
660 | ||
661 | /* Check alive response for "valid" sign from uCode */ | |
662 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
663 | /* We had an error bringing up the hardware, so take it | |
664 | * all the way back down so we can try again */ | |
665 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
666 | goto restart; | |
667 | } | |
668 | ||
669 | /* initialize uCode was loaded... verify inst image. | |
670 | * This is a paranoid check, because we would not have gotten the | |
671 | * "initialize" alive if code weren't properly loaded. */ | |
672 | if (iwl_verify_ucode(priv)) { | |
673 | /* Runtime instruction load was bad; | |
674 | * take it all the way back down so we can try again */ | |
675 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
676 | goto restart; | |
677 | } | |
678 | ||
37deb2a0 | 679 | iwl_clear_stations_table(priv); |
99da1b48 RR |
680 | ret = priv->cfg->ops->lib->alive_notify(priv); |
681 | if (ret) { | |
682 | IWL_WARNING("Could not complete ALIVE transition: %d\n", ret); | |
683 | goto restart; | |
684 | } | |
685 | ||
7c616cba | 686 | iwl5000_send_calib_cfg(priv); |
99da1b48 RR |
687 | return; |
688 | ||
689 | restart: | |
690 | /* real restart (first load init_ucode) */ | |
691 | queue_work(priv->workqueue, &priv->restart); | |
692 | } | |
693 | ||
694 | static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, | |
695 | int txq_id, u32 index) | |
696 | { | |
697 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
698 | (index & 0xff) | (txq_id << 8)); | |
699 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); | |
700 | } | |
701 | ||
702 | static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, | |
703 | struct iwl_tx_queue *txq, | |
704 | int tx_fifo_id, int scd_retry) | |
705 | { | |
706 | int txq_id = txq->q.id; | |
3fd07a1e | 707 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; |
99da1b48 RR |
708 | |
709 | iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
710 | (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
711 | (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | | |
712 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | | |
713 | IWL50_SCD_QUEUE_STTS_REG_MSK); | |
714 | ||
715 | txq->sched_retry = scd_retry; | |
716 | ||
717 | IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", | |
718 | active ? "Activate" : "Deactivate", | |
719 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); | |
720 | } | |
721 | ||
9636e583 RR |
722 | static int iwl5000_send_wimax_coex(struct iwl_priv *priv) |
723 | { | |
724 | struct iwl_wimax_coex_cmd coex_cmd; | |
725 | ||
726 | memset(&coex_cmd, 0, sizeof(coex_cmd)); | |
727 | ||
728 | return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, | |
729 | sizeof(coex_cmd), &coex_cmd); | |
730 | } | |
731 | ||
99da1b48 RR |
732 | static int iwl5000_alive_notify(struct iwl_priv *priv) |
733 | { | |
734 | u32 a; | |
99da1b48 RR |
735 | unsigned long flags; |
736 | int ret; | |
31a73fe4 | 737 | int i, chan; |
40fc95d5 | 738 | u32 reg_val; |
99da1b48 RR |
739 | |
740 | spin_lock_irqsave(&priv->lock, flags); | |
741 | ||
742 | ret = iwl_grab_nic_access(priv); | |
743 | if (ret) { | |
744 | spin_unlock_irqrestore(&priv->lock, flags); | |
745 | return ret; | |
746 | } | |
747 | ||
748 | priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); | |
749 | a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; | |
750 | for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; | |
751 | a += 4) | |
752 | iwl_write_targ_mem(priv, a, 0); | |
753 | for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; | |
754 | a += 4) | |
755 | iwl_write_targ_mem(priv, a, 0); | |
756 | for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) | |
757 | iwl_write_targ_mem(priv, a, 0); | |
758 | ||
759 | iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, | |
4ddbb7d0 | 760 | priv->scd_bc_tbls.dma >> 10); |
31a73fe4 WT |
761 | |
762 | /* Enable DMA channel */ | |
763 | for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++) | |
764 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
765 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
766 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
767 | ||
40fc95d5 WT |
768 | /* Update FH chicken bits */ |
769 | reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); | |
770 | iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, | |
771 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
772 | ||
99da1b48 | 773 | iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, |
4ddbb7d0 | 774 | IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); |
99da1b48 RR |
775 | iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); |
776 | ||
777 | /* initiate the queues */ | |
778 | for (i = 0; i < priv->hw_params.max_txq_num; i++) { | |
779 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); | |
780 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
781 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
782 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); | |
783 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
784 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + | |
785 | sizeof(u32), | |
786 | ((SCD_WIN_SIZE << | |
787 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
788 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
789 | ((SCD_FRAME_LIMIT << | |
790 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
791 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
792 | } | |
793 | ||
794 | iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, | |
da1bc453 | 795 | IWL_MASK(0, priv->hw_params.max_txq_num)); |
99da1b48 | 796 | |
da1bc453 TW |
797 | /* Activate all Tx DMA/FIFO channels */ |
798 | priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); | |
99da1b48 RR |
799 | |
800 | iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); | |
9c80c502 | 801 | |
99da1b48 RR |
802 | /* map qos queues to fifos one-to-one */ |
803 | for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { | |
804 | int ac = iwl5000_default_queue_to_tx_fifo[i]; | |
805 | iwl_txq_ctx_activate(priv, i); | |
806 | iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); | |
807 | } | |
808 | /* TODO - need to initialize those FIFOs inside the loop above, | |
809 | * not only mark them as active */ | |
810 | iwl_txq_ctx_activate(priv, 4); | |
811 | iwl_txq_ctx_activate(priv, 7); | |
812 | iwl_txq_ctx_activate(priv, 8); | |
813 | iwl_txq_ctx_activate(priv, 9); | |
814 | ||
815 | iwl_release_nic_access(priv); | |
816 | spin_unlock_irqrestore(&priv->lock, flags); | |
817 | ||
7c616cba | 818 | |
9636e583 RR |
819 | iwl5000_send_wimax_coex(priv); |
820 | ||
be5d56ed TW |
821 | iwl5000_set_Xtal_calib(priv); |
822 | iwl_send_calib_results(priv); | |
7c616cba | 823 | |
99da1b48 RR |
824 | return 0; |
825 | } | |
826 | ||
fdd3e8a4 TW |
827 | static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) |
828 | { | |
829 | if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || | |
830 | (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { | |
831 | IWL_ERROR("invalid queues_num, should be between %d and %d\n", | |
832 | IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); | |
833 | return -EINVAL; | |
834 | } | |
25ae3986 | 835 | |
fdd3e8a4 | 836 | priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; |
f3f911d1 | 837 | priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; |
4ddbb7d0 TW |
838 | priv->hw_params.scd_bc_tbls_size = |
839 | IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl); | |
fdd3e8a4 TW |
840 | priv->hw_params.max_stations = IWL5000_STATION_COUNT; |
841 | priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; | |
842 | priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; | |
843 | priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; | |
da154e30 | 844 | priv->hw_params.max_bsm_size = 0; |
fdd3e8a4 TW |
845 | priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | |
846 | BIT(IEEE80211_BAND_5GHZ); | |
33fd5033 | 847 | priv->hw_params.sens = &iwl5000_sensitivity; |
fdd3e8a4 TW |
848 | |
849 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
850 | case CSR_HW_REV_TYPE_5100: | |
5d664a41 TW |
851 | priv->hw_params.tx_chains_num = 1; |
852 | priv->hw_params.rx_chains_num = 2; | |
853 | priv->hw_params.valid_tx_ant = ANT_B; | |
854 | priv->hw_params.valid_rx_ant = ANT_AB; | |
855 | break; | |
fdd3e8a4 TW |
856 | case CSR_HW_REV_TYPE_5150: |
857 | priv->hw_params.tx_chains_num = 1; | |
858 | priv->hw_params.rx_chains_num = 2; | |
1179f18d TW |
859 | priv->hw_params.valid_tx_ant = ANT_A; |
860 | priv->hw_params.valid_rx_ant = ANT_AB; | |
fdd3e8a4 TW |
861 | break; |
862 | case CSR_HW_REV_TYPE_5300: | |
863 | case CSR_HW_REV_TYPE_5350: | |
864 | priv->hw_params.tx_chains_num = 3; | |
865 | priv->hw_params.rx_chains_num = 3; | |
1179f18d TW |
866 | priv->hw_params.valid_tx_ant = ANT_ABC; |
867 | priv->hw_params.valid_rx_ant = ANT_ABC; | |
fdd3e8a4 TW |
868 | break; |
869 | } | |
c031bf80 EG |
870 | |
871 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
872 | case CSR_HW_REV_TYPE_5100: | |
873 | case CSR_HW_REV_TYPE_5300: | |
d5d7c584 TW |
874 | case CSR_HW_REV_TYPE_5350: |
875 | /* 5X00 and 5350 wants in Celsius */ | |
c031bf80 EG |
876 | priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; |
877 | break; | |
878 | case CSR_HW_REV_TYPE_5150: | |
d5d7c584 | 879 | /* 5150 wants in Kelvin */ |
c031bf80 | 880 | priv->hw_params.ct_kill_threshold = |
339afc89 | 881 | iwl5150_get_ct_threshold(priv); |
c031bf80 EG |
882 | break; |
883 | } | |
884 | ||
be5d56ed TW |
885 | /* Set initial calibration set */ |
886 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
887 | case CSR_HW_REV_TYPE_5100: | |
888 | case CSR_HW_REV_TYPE_5300: | |
889 | case CSR_HW_REV_TYPE_5350: | |
890 | priv->hw_params.calib_init_cfg = | |
f69f42a6 TW |
891 | BIT(IWL_CALIB_XTAL) | |
892 | BIT(IWL_CALIB_LO) | | |
201706ac TW |
893 | BIT(IWL_CALIB_TX_IQ) | |
894 | BIT(IWL_CALIB_TX_IQ_PERD) | | |
895 | BIT(IWL_CALIB_BASE_BAND); | |
be5d56ed TW |
896 | break; |
897 | case CSR_HW_REV_TYPE_5150: | |
819500c5 | 898 | priv->hw_params.calib_init_cfg = |
7470d7f5 WT |
899 | BIT(IWL_CALIB_DC) | |
900 | BIT(IWL_CALIB_LO) | | |
901 | BIT(IWL_CALIB_TX_IQ) | | |
902 | BIT(IWL_CALIB_BASE_BAND); | |
819500c5 | 903 | |
be5d56ed TW |
904 | break; |
905 | } | |
906 | ||
907 | ||
fdd3e8a4 TW |
908 | return 0; |
909 | } | |
d4100dd9 | 910 | |
7839fc03 EG |
911 | /** |
912 | * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
913 | */ | |
914 | static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, | |
16466903 | 915 | struct iwl_tx_queue *txq, |
7839fc03 EG |
916 | u16 byte_cnt) |
917 | { | |
4ddbb7d0 | 918 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab | 919 | int write_ptr = txq->q.write_ptr; |
7839fc03 EG |
920 | int txq_id = txq->q.id; |
921 | u8 sec_ctl = 0; | |
127901ab TW |
922 | u8 sta_id = 0; |
923 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
924 | __le16 bc_ent; | |
7839fc03 | 925 | |
127901ab | 926 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
7839fc03 EG |
927 | |
928 | if (txq_id != IWL_CMD_QUEUE_NUM) { | |
127901ab | 929 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; |
da99c4b6 | 930 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; |
7839fc03 EG |
931 | |
932 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
933 | case TX_CMD_SEC_CCM: | |
934 | len += CCMP_MIC_LEN; | |
935 | break; | |
936 | case TX_CMD_SEC_TKIP: | |
937 | len += TKIP_ICV_LEN; | |
938 | break; | |
939 | case TX_CMD_SEC_WEP: | |
940 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
941 | break; | |
942 | } | |
943 | } | |
944 | ||
127901ab | 945 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); |
7839fc03 | 946 | |
4ddbb7d0 | 947 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; |
7839fc03 | 948 | |
127901ab | 949 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 950 | scd_bc_tbl[txq_id]. |
127901ab | 951 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; |
7839fc03 EG |
952 | } |
953 | ||
972cf447 TW |
954 | static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, |
955 | struct iwl_tx_queue *txq) | |
956 | { | |
4ddbb7d0 | 957 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab TW |
958 | int txq_id = txq->q.id; |
959 | int read_ptr = txq->q.read_ptr; | |
960 | u8 sta_id = 0; | |
961 | __le16 bc_ent; | |
962 | ||
963 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
972cf447 TW |
964 | |
965 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
127901ab | 966 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
972cf447 | 967 | |
127901ab | 968 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); |
4ddbb7d0 | 969 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; |
972cf447 | 970 | |
127901ab | 971 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 972 | scd_bc_tbl[txq_id]. |
127901ab | 973 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; |
972cf447 TW |
974 | } |
975 | ||
e26e47d9 TW |
976 | static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, |
977 | u16 txq_id) | |
978 | { | |
979 | u32 tbl_dw_addr; | |
980 | u32 tbl_dw; | |
981 | u16 scd_q2ratid; | |
982 | ||
983 | scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
984 | ||
985 | tbl_dw_addr = priv->scd_base_addr + | |
986 | IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); | |
987 | ||
988 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
989 | ||
990 | if (txq_id & 0x1) | |
991 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
992 | else | |
993 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
994 | ||
995 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
996 | ||
997 | return 0; | |
998 | } | |
999 | static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
1000 | { | |
1001 | /* Simply stop the queue, but don't change any configuration; | |
1002 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1003 | iwl_write_prph(priv, | |
1004 | IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
1005 | (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
1006 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
1007 | } | |
1008 | ||
1009 | static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |
1010 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) | |
1011 | { | |
1012 | unsigned long flags; | |
1013 | int ret; | |
1014 | u16 ra_tid; | |
1015 | ||
9f17b318 TW |
1016 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
1017 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
1018 | IWL_WARNING("queue number out of range: %d, must be %d to %d\n", | |
1019 | txq_id, IWL50_FIRST_AMPDU_QUEUE, | |
1020 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
1021 | return -EINVAL; | |
1022 | } | |
e26e47d9 TW |
1023 | |
1024 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
1025 | ||
1026 | /* Modify device's station table to Tx this TID */ | |
9f58671e | 1027 | iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); |
e26e47d9 TW |
1028 | |
1029 | spin_lock_irqsave(&priv->lock, flags); | |
1030 | ret = iwl_grab_nic_access(priv); | |
1031 | if (ret) { | |
1032 | spin_unlock_irqrestore(&priv->lock, flags); | |
1033 | return ret; | |
1034 | } | |
1035 | ||
1036 | /* Stop this Tx queue before configuring it */ | |
1037 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); | |
1038 | ||
1039 | /* Map receiver-address / traffic-ID to this queue */ | |
1040 | iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
1041 | ||
1042 | /* Set this queue as a chain-building queue */ | |
1043 | iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); | |
1044 | ||
1045 | /* enable aggregations for the queue */ | |
1046 | iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); | |
1047 | ||
1048 | /* Place first TFD at index corresponding to start sequence number. | |
1049 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
1050 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
1051 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
1052 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
1053 | ||
1054 | /* Set up Tx window size and frame limit for this queue */ | |
1055 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
1056 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + | |
1057 | sizeof(u32), | |
1058 | ((SCD_WIN_SIZE << | |
1059 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1060 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1061 | ((SCD_FRAME_LIMIT << | |
1062 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1063 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
1064 | ||
1065 | iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
1066 | ||
1067 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
1068 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
1069 | ||
1070 | iwl_release_nic_access(priv); | |
1071 | spin_unlock_irqrestore(&priv->lock, flags); | |
1072 | ||
1073 | return 0; | |
1074 | } | |
1075 | ||
1076 | static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, | |
1077 | u16 ssn_idx, u8 tx_fifo) | |
1078 | { | |
1079 | int ret; | |
1080 | ||
9f17b318 TW |
1081 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
1082 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
1083 | IWL_WARNING("queue number out of range: %d, must be %d to %d\n", | |
1084 | txq_id, IWL50_FIRST_AMPDU_QUEUE, | |
1085 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
e26e47d9 TW |
1086 | return -EINVAL; |
1087 | } | |
1088 | ||
1089 | ret = iwl_grab_nic_access(priv); | |
1090 | if (ret) | |
1091 | return ret; | |
1092 | ||
1093 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); | |
1094 | ||
1095 | iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); | |
1096 | ||
1097 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
1098 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
1099 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
1100 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
1101 | ||
1102 | iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
1103 | iwl_txq_ctx_deactivate(priv, txq_id); | |
1104 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
1105 | ||
1106 | iwl_release_nic_access(priv); | |
1107 | ||
1108 | return 0; | |
1109 | } | |
1110 | ||
2469bf2e TW |
1111 | static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) |
1112 | { | |
1113 | u16 size = (u16)sizeof(struct iwl_addsta_cmd); | |
1114 | memcpy(data, cmd, size); | |
1115 | return size; | |
1116 | } | |
1117 | ||
1118 | ||
da1bc453 | 1119 | /* |
a96a27f9 | 1120 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask |
da1bc453 TW |
1121 | * must be called under priv->lock and mac access |
1122 | */ | |
1123 | static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) | |
5a676bbe | 1124 | { |
da1bc453 | 1125 | iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); |
5a676bbe RR |
1126 | } |
1127 | ||
e532fa0e RR |
1128 | |
1129 | static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) | |
1130 | { | |
3ac7f146 | 1131 | return le32_to_cpup((__le32 *)&tx_resp->status + |
25a6572c | 1132 | tx_resp->frame_count) & MAX_SN; |
e532fa0e RR |
1133 | } |
1134 | ||
1135 | static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, | |
1136 | struct iwl_ht_agg *agg, | |
1137 | struct iwl5000_tx_resp *tx_resp, | |
25a6572c | 1138 | int txq_id, u16 start_idx) |
e532fa0e RR |
1139 | { |
1140 | u16 status; | |
1141 | struct agg_tx_status *frame_status = &tx_resp->status; | |
1142 | struct ieee80211_tx_info *info = NULL; | |
1143 | struct ieee80211_hdr *hdr = NULL; | |
e7d326ac | 1144 | u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); |
25a6572c | 1145 | int i, sh, idx; |
e532fa0e RR |
1146 | u16 seq; |
1147 | ||
1148 | if (agg->wait_for_ba) | |
1149 | IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); | |
1150 | ||
1151 | agg->frame_count = tx_resp->frame_count; | |
1152 | agg->start_idx = start_idx; | |
e7d326ac | 1153 | agg->rate_n_flags = rate_n_flags; |
e532fa0e RR |
1154 | agg->bitmap = 0; |
1155 | ||
1156 | /* # frames attempted by Tx command */ | |
1157 | if (agg->frame_count == 1) { | |
1158 | /* Only one frame was attempted; no block-ack will arrive */ | |
1159 | status = le16_to_cpu(frame_status[0].status); | |
25a6572c | 1160 | idx = start_idx; |
e532fa0e RR |
1161 | |
1162 | /* FIXME: code repetition */ | |
1163 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", | |
1164 | agg->frame_count, agg->start_idx, idx); | |
1165 | ||
1166 | info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); | |
e6a9854b | 1167 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
e532fa0e | 1168 | info->flags &= ~IEEE80211_TX_CTL_AMPDU; |
c3056065 | 1169 | info->flags |= iwl_is_tx_success(status) ? |
3fd07a1e | 1170 | IEEE80211_TX_STAT_ACK : 0; |
e7d326ac TW |
1171 | iwl_hwrate_to_tx_control(priv, rate_n_flags, info); |
1172 | ||
e532fa0e RR |
1173 | /* FIXME: code repetition end */ |
1174 | ||
1175 | IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", | |
1176 | status & 0xff, tx_resp->failure_frame); | |
e7d326ac | 1177 | IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); |
e532fa0e RR |
1178 | |
1179 | agg->wait_for_ba = 0; | |
1180 | } else { | |
1181 | /* Two or more frames were attempted; expect block-ack */ | |
1182 | u64 bitmap = 0; | |
1183 | int start = agg->start_idx; | |
1184 | ||
1185 | /* Construct bit-map of pending frames within Tx window */ | |
1186 | for (i = 0; i < agg->frame_count; i++) { | |
1187 | u16 sc; | |
1188 | status = le16_to_cpu(frame_status[i].status); | |
1189 | seq = le16_to_cpu(frame_status[i].sequence); | |
1190 | idx = SEQ_TO_INDEX(seq); | |
1191 | txq_id = SEQ_TO_QUEUE(seq); | |
1192 | ||
1193 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
1194 | AGG_TX_STATE_ABORT_MSK)) | |
1195 | continue; | |
1196 | ||
1197 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", | |
1198 | agg->frame_count, txq_id, idx); | |
1199 | ||
1200 | hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); | |
1201 | ||
1202 | sc = le16_to_cpu(hdr->seq_ctrl); | |
1203 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
1204 | IWL_ERROR("BUG_ON idx doesn't match seq control" | |
1205 | " idx=%d, seq_idx=%d, seq=%d\n", | |
1206 | idx, SEQ_TO_SN(sc), | |
1207 | hdr->seq_ctrl); | |
1208 | return -1; | |
1209 | } | |
1210 | ||
1211 | IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", | |
1212 | i, idx, SEQ_TO_SN(sc)); | |
1213 | ||
1214 | sh = idx - start; | |
1215 | if (sh > 64) { | |
1216 | sh = (start - idx) + 0xff; | |
1217 | bitmap = bitmap << sh; | |
1218 | sh = 0; | |
1219 | start = idx; | |
1220 | } else if (sh < -64) | |
1221 | sh = 0xff - (start - idx); | |
1222 | else if (sh < 0) { | |
1223 | sh = start - idx; | |
1224 | start = idx; | |
1225 | bitmap = bitmap << sh; | |
1226 | sh = 0; | |
1227 | } | |
4aa41f12 EG |
1228 | bitmap |= 1ULL << sh; |
1229 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", | |
1230 | start, (unsigned long long)bitmap); | |
e532fa0e RR |
1231 | } |
1232 | ||
1233 | agg->bitmap = bitmap; | |
1234 | agg->start_idx = start; | |
e532fa0e RR |
1235 | IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", |
1236 | agg->frame_count, agg->start_idx, | |
1237 | (unsigned long long)agg->bitmap); | |
1238 | ||
1239 | if (bitmap) | |
1240 | agg->wait_for_ba = 1; | |
1241 | } | |
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | static void iwl5000_rx_reply_tx(struct iwl_priv *priv, | |
1246 | struct iwl_rx_mem_buffer *rxb) | |
1247 | { | |
1248 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1249 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
1250 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1251 | int index = SEQ_TO_INDEX(sequence); | |
1252 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1253 | struct ieee80211_tx_info *info; | |
1254 | struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; | |
1255 | u32 status = le16_to_cpu(tx_resp->status.status); | |
3fd07a1e TW |
1256 | int tid; |
1257 | int sta_id; | |
1258 | int freed; | |
e532fa0e RR |
1259 | |
1260 | if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { | |
1261 | IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " | |
1262 | "is out of range [0-%d] %d %d\n", txq_id, | |
1263 | index, txq->q.n_bd, txq->q.write_ptr, | |
1264 | txq->q.read_ptr); | |
1265 | return; | |
1266 | } | |
1267 | ||
1268 | info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); | |
1269 | memset(&info->status, 0, sizeof(info->status)); | |
1270 | ||
3fd07a1e TW |
1271 | tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; |
1272 | sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; | |
e532fa0e RR |
1273 | |
1274 | if (txq->sched_retry) { | |
1275 | const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); | |
1276 | struct iwl_ht_agg *agg = NULL; | |
1277 | ||
e532fa0e RR |
1278 | agg = &priv->stations[sta_id].tid[tid].agg; |
1279 | ||
25a6572c | 1280 | iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); |
e532fa0e | 1281 | |
3235427e RR |
1282 | /* check if BAR is needed */ |
1283 | if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) | |
1284 | info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
e532fa0e RR |
1285 | |
1286 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { | |
e532fa0e | 1287 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); |
3fd07a1e TW |
1288 | IWL_DEBUG_TX_REPLY("Retry scheduler reclaim " |
1289 | "scd_ssn=%d idx=%d txq=%d swq=%d\n", | |
1290 | scd_ssn , index, txq_id, txq->swq_id); | |
1291 | ||
17b88929 | 1292 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
e532fa0e RR |
1293 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
1294 | ||
3fd07a1e TW |
1295 | if (priv->mac80211_registered && |
1296 | (iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1297 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { | |
e532fa0e RR |
1298 | if (agg->state == IWL_AGG_OFF) |
1299 | ieee80211_wake_queue(priv->hw, txq_id); | |
1300 | else | |
3fd07a1e TW |
1301 | ieee80211_wake_queue(priv->hw, |
1302 | txq->swq_id); | |
e532fa0e | 1303 | } |
e532fa0e RR |
1304 | } |
1305 | } else { | |
3fd07a1e TW |
1306 | BUG_ON(txq_id != txq->swq_id); |
1307 | ||
e6a9854b | 1308 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
3fd07a1e TW |
1309 | info->flags |= iwl_is_tx_success(status) ? |
1310 | IEEE80211_TX_STAT_ACK : 0; | |
e7d326ac | 1311 | iwl_hwrate_to_tx_control(priv, |
4f85f5b3 RR |
1312 | le32_to_cpu(tx_resp->rate_n_flags), |
1313 | info); | |
1314 | ||
3fd07a1e TW |
1315 | IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags " |
1316 | "0x%x retries %d\n", | |
1317 | txq_id, | |
1318 | iwl_get_tx_fail_reason(status), status, | |
1319 | le32_to_cpu(tx_resp->rate_n_flags), | |
1320 | tx_resp->failure_frame); | |
4f85f5b3 | 1321 | |
3fd07a1e TW |
1322 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
1323 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) | |
e532fa0e | 1324 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
3fd07a1e TW |
1325 | |
1326 | if (priv->mac80211_registered && | |
1327 | (iwl_queue_space(&txq->q) > txq->q.low_mark)) | |
e532fa0e | 1328 | ieee80211_wake_queue(priv->hw, txq_id); |
e532fa0e | 1329 | } |
e532fa0e | 1330 | |
3fd07a1e TW |
1331 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) |
1332 | iwl_txq_check_empty(priv, sta_id, tid, txq_id); | |
1333 | ||
e532fa0e RR |
1334 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) |
1335 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); | |
1336 | } | |
1337 | ||
a96a27f9 | 1338 | /* Currently 5000 is the superset of everything */ |
c1adf9fb GG |
1339 | static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) |
1340 | { | |
1341 | return len; | |
1342 | } | |
1343 | ||
203566f3 EG |
1344 | static void iwl5000_setup_deferred_work(struct iwl_priv *priv) |
1345 | { | |
1346 | /* in 5000 the tx power calibration is done in uCode */ | |
1347 | priv->disable_tx_power_cal = 1; | |
1348 | } | |
1349 | ||
b600e4e1 RR |
1350 | static void iwl5000_rx_handler_setup(struct iwl_priv *priv) |
1351 | { | |
7c616cba TW |
1352 | /* init calibration handlers */ |
1353 | priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = | |
1354 | iwl5000_rx_calib_result; | |
1355 | priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = | |
1356 | iwl5000_rx_calib_complete; | |
e532fa0e | 1357 | priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; |
b600e4e1 RR |
1358 | } |
1359 | ||
7c616cba | 1360 | |
87283cc1 RR |
1361 | static int iwl5000_hw_valid_rtc_data_addr(u32 addr) |
1362 | { | |
1363 | return (addr >= RTC_DATA_LOWER_BOUND) && | |
1364 | (addr < IWL50_RTC_DATA_UPPER_BOUND); | |
1365 | } | |
1366 | ||
fe7a90c2 RR |
1367 | static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) |
1368 | { | |
1369 | int ret = 0; | |
1370 | struct iwl5000_rxon_assoc_cmd rxon_assoc; | |
1371 | const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; | |
1372 | const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; | |
1373 | ||
1374 | if ((rxon1->flags == rxon2->flags) && | |
1375 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1376 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1377 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
1378 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
1379 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
1380 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
1381 | (rxon1->ofdm_ht_triple_stream_basic_rates == | |
1382 | rxon2->ofdm_ht_triple_stream_basic_rates) && | |
1383 | (rxon1->acquisition_data == rxon2->acquisition_data) && | |
1384 | (rxon1->rx_chain == rxon2->rx_chain) && | |
1385 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
1386 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1391 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1392 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1393 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1394 | rxon_assoc.reserved1 = 0; | |
1395 | rxon_assoc.reserved2 = 0; | |
1396 | rxon_assoc.reserved3 = 0; | |
1397 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
1398 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
1399 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
1400 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
1401 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
1402 | rxon_assoc.ofdm_ht_triple_stream_basic_rates = | |
1403 | priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; | |
1404 | rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; | |
1405 | ||
1406 | ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, | |
1407 | sizeof(rxon_assoc), &rxon_assoc, NULL); | |
1408 | if (ret) | |
1409 | return ret; | |
1410 | ||
1411 | return ret; | |
1412 | } | |
630fe9b6 TW |
1413 | static int iwl5000_send_tx_power(struct iwl_priv *priv) |
1414 | { | |
1415 | struct iwl5000_tx_power_dbm_cmd tx_power_cmd; | |
1416 | ||
1417 | /* half dBm need to multiply */ | |
1418 | tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); | |
853554ac | 1419 | tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; |
630fe9b6 TW |
1420 | tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; |
1421 | return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD, | |
1422 | sizeof(tx_power_cmd), &tx_power_cmd, | |
1423 | NULL); | |
1424 | } | |
1425 | ||
5225640b | 1426 | static void iwl5000_temperature(struct iwl_priv *priv) |
8f91aecb EG |
1427 | { |
1428 | /* store temperature from statistics (in Celsius) */ | |
5225640b | 1429 | priv->temperature = le32_to_cpu(priv->statistics.general.temperature); |
8f91aecb | 1430 | } |
fe7a90c2 | 1431 | |
caab8f1a TW |
1432 | /* Calc max signal level (dBm) among 3 possible receivers */ |
1433 | static int iwl5000_calc_rssi(struct iwl_priv *priv, | |
1434 | struct iwl_rx_phy_res *rx_resp) | |
1435 | { | |
1436 | /* data from PHY/DSP regarding signal strength, etc., | |
1437 | * contents are always there, not configurable by host | |
1438 | */ | |
1439 | struct iwl5000_non_cfg_phy *ncphy = | |
1440 | (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | |
1441 | u32 val, rssi_a, rssi_b, rssi_c, max_rssi; | |
1442 | u8 agc; | |
1443 | ||
1444 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); | |
1445 | agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; | |
1446 | ||
1447 | /* Find max rssi among 3 possible receivers. | |
1448 | * These values are measured by the digital signal processor (DSP). | |
1449 | * They should stay fairly constant even as the signal strength varies, | |
1450 | * if the radio's automatic gain control (AGC) is working right. | |
1451 | * AGC value (see below) will provide the "interesting" info. | |
1452 | */ | |
1453 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); | |
1454 | rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; | |
1455 | rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; | |
1456 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); | |
1457 | rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; | |
1458 | ||
1459 | max_rssi = max_t(u32, rssi_a, rssi_b); | |
1460 | max_rssi = max_t(u32, max_rssi, rssi_c); | |
1461 | ||
1462 | IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", | |
1463 | rssi_a, rssi_b, rssi_c, max_rssi, agc); | |
1464 | ||
1465 | /* dBm = max_rssi dB - agc dB - constant. | |
1466 | * Higher AGC (higher radio gain) means lower signal. */ | |
1467 | return max_rssi - agc - IWL_RSSI_OFFSET; | |
1468 | } | |
1469 | ||
da8dec29 | 1470 | static struct iwl_hcmd_ops iwl5000_hcmd = { |
fe7a90c2 | 1471 | .rxon_assoc = iwl5000_send_rxon_assoc, |
da8dec29 TW |
1472 | }; |
1473 | ||
1474 | static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { | |
c1adf9fb | 1475 | .get_hcmd_size = iwl5000_get_hcmd_size, |
2469bf2e | 1476 | .build_addsta_hcmd = iwl5000_build_addsta_hcmd, |
33fd5033 EG |
1477 | .gain_computation = iwl5000_gain_computation, |
1478 | .chain_noise_reset = iwl5000_chain_noise_reset, | |
a326a5d0 | 1479 | .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, |
caab8f1a | 1480 | .calc_rssi = iwl5000_calc_rssi, |
da8dec29 TW |
1481 | }; |
1482 | ||
1483 | static struct iwl_lib_ops iwl5000_lib = { | |
fdd3e8a4 | 1484 | .set_hw_params = iwl5000_hw_set_hw_params, |
7839fc03 | 1485 | .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, |
972cf447 | 1486 | .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, |
da1bc453 | 1487 | .txq_set_sched = iwl5000_txq_set_sched, |
e26e47d9 TW |
1488 | .txq_agg_enable = iwl5000_txq_agg_enable, |
1489 | .txq_agg_disable = iwl5000_txq_agg_disable, | |
b600e4e1 | 1490 | .rx_handler_setup = iwl5000_rx_handler_setup, |
203566f3 | 1491 | .setup_deferred_work = iwl5000_setup_deferred_work, |
87283cc1 | 1492 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
dbb983b7 | 1493 | .load_ucode = iwl5000_load_ucode, |
99da1b48 RR |
1494 | .init_alive_start = iwl5000_init_alive_start, |
1495 | .alive_notify = iwl5000_alive_notify, | |
630fe9b6 | 1496 | .send_tx_power = iwl5000_send_tx_power, |
8f91aecb | 1497 | .temperature = iwl5000_temperature, |
5b9f8cd3 | 1498 | .update_chain_flags = iwl_update_chain_flags, |
30d59260 TW |
1499 | .apm_ops = { |
1500 | .init = iwl5000_apm_init, | |
7f066108 | 1501 | .reset = iwl5000_apm_reset, |
f118a91d | 1502 | .stop = iwl5000_apm_stop, |
5a835353 | 1503 | .config = iwl5000_nic_config, |
5b9f8cd3 | 1504 | .set_pwr_src = iwl_set_pwr_src, |
30d59260 | 1505 | }, |
da8dec29 | 1506 | .eeprom_ops = { |
25ae3986 TW |
1507 | .regulatory_bands = { |
1508 | EEPROM_5000_REG_BAND_1_CHANNELS, | |
1509 | EEPROM_5000_REG_BAND_2_CHANNELS, | |
1510 | EEPROM_5000_REG_BAND_3_CHANNELS, | |
1511 | EEPROM_5000_REG_BAND_4_CHANNELS, | |
1512 | EEPROM_5000_REG_BAND_5_CHANNELS, | |
1513 | EEPROM_5000_REG_BAND_24_FAT_CHANNELS, | |
1514 | EEPROM_5000_REG_BAND_52_FAT_CHANNELS | |
1515 | }, | |
da8dec29 TW |
1516 | .verify_signature = iwlcore_eeprom_verify_signature, |
1517 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
1518 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
0ef2ca67 | 1519 | .calib_version = iwl5000_eeprom_calib_version, |
25ae3986 | 1520 | .query_addr = iwl5000_eeprom_query_addr, |
da8dec29 TW |
1521 | }, |
1522 | }; | |
1523 | ||
1524 | static struct iwl_ops iwl5000_ops = { | |
1525 | .lib = &iwl5000_lib, | |
1526 | .hcmd = &iwl5000_hcmd, | |
1527 | .utils = &iwl5000_hcmd_utils, | |
1528 | }; | |
1529 | ||
5a6a256e TW |
1530 | static struct iwl_mod_params iwl50_mod_params = { |
1531 | .num_of_queues = IWL50_NUM_QUEUES, | |
9f17b318 | 1532 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, |
5a6a256e | 1533 | .amsdu_size_8K = 1, |
3a1081e8 | 1534 | .restart_fw = 1, |
5a6a256e TW |
1535 | /* the rest are 0 by default */ |
1536 | }; | |
1537 | ||
1538 | ||
1539 | struct iwl_cfg iwl5300_agn_cfg = { | |
1540 | .name = "5300AGN", | |
a0987a8d RC |
1541 | .fw_name_pre = IWL5000_FW_PRE, |
1542 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1543 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1544 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1545 | .ops = &iwl5000_ops, |
25ae3986 | 1546 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1547 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1548 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
5a6a256e TW |
1549 | .mod_params = &iwl50_mod_params, |
1550 | }; | |
1551 | ||
47408639 EK |
1552 | struct iwl_cfg iwl5100_bg_cfg = { |
1553 | .name = "5100BG", | |
a0987a8d RC |
1554 | .fw_name_pre = IWL5000_FW_PRE, |
1555 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1556 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
47408639 EK |
1557 | .sku = IWL_SKU_G, |
1558 | .ops = &iwl5000_ops, | |
1559 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1560 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1561 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
47408639 EK |
1562 | .mod_params = &iwl50_mod_params, |
1563 | }; | |
1564 | ||
1565 | struct iwl_cfg iwl5100_abg_cfg = { | |
1566 | .name = "5100ABG", | |
a0987a8d RC |
1567 | .fw_name_pre = IWL5000_FW_PRE, |
1568 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1569 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
47408639 EK |
1570 | .sku = IWL_SKU_A|IWL_SKU_G, |
1571 | .ops = &iwl5000_ops, | |
1572 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1573 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1574 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
47408639 EK |
1575 | .mod_params = &iwl50_mod_params, |
1576 | }; | |
1577 | ||
5a6a256e TW |
1578 | struct iwl_cfg iwl5100_agn_cfg = { |
1579 | .name = "5100AGN", | |
a0987a8d RC |
1580 | .fw_name_pre = IWL5000_FW_PRE, |
1581 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1582 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1583 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1584 | .ops = &iwl5000_ops, |
25ae3986 | 1585 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1586 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1587 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
5a6a256e TW |
1588 | .mod_params = &iwl50_mod_params, |
1589 | }; | |
1590 | ||
1591 | struct iwl_cfg iwl5350_agn_cfg = { | |
1592 | .name = "5350AGN", | |
a0987a8d RC |
1593 | .fw_name_pre = IWL5000_FW_PRE, |
1594 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1595 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1596 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1597 | .ops = &iwl5000_ops, |
25ae3986 | 1598 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1599 | .eeprom_ver = EEPROM_5050_EEPROM_VERSION, |
1600 | .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, | |
5a6a256e TW |
1601 | .mod_params = &iwl50_mod_params, |
1602 | }; | |
1603 | ||
7100e924 TW |
1604 | struct iwl_cfg iwl5150_agn_cfg = { |
1605 | .name = "5150AGN", | |
a0987a8d RC |
1606 | .fw_name_pre = IWL5150_FW_PRE, |
1607 | .ucode_api_max = IWL5150_UCODE_API_MAX, | |
1608 | .ucode_api_min = IWL5150_UCODE_API_MIN, | |
7100e924 TW |
1609 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
1610 | .ops = &iwl5000_ops, | |
1611 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
fd63edba TW |
1612 | .eeprom_ver = EEPROM_5050_EEPROM_VERSION, |
1613 | .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, | |
7100e924 TW |
1614 | .mod_params = &iwl50_mod_params, |
1615 | }; | |
1616 | ||
a0987a8d RC |
1617 | MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX)); |
1618 | MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX)); | |
c9f79ed2 | 1619 | |
5a6a256e TW |
1620 | module_param_named(disable50, iwl50_mod_params.disable, int, 0444); |
1621 | MODULE_PARM_DESC(disable50, | |
1622 | "manually disable the 50XX radio (default 0 [radio on])"); | |
1623 | module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); | |
1624 | MODULE_PARM_DESC(swcrypto50, | |
1625 | "using software crypto engine (default 0 [hardware])\n"); | |
95aa194a | 1626 | module_param_named(debug50, iwl50_mod_params.debug, uint, 0444); |
5a6a256e TW |
1627 | MODULE_PARM_DESC(debug50, "50XX debug output mask"); |
1628 | module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); | |
1629 | MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); | |
49779293 RR |
1630 | module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444); |
1631 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); | |
5a6a256e TW |
1632 | module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); |
1633 | MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); | |
3a1081e8 EK |
1634 | module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); |
1635 | MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); |