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headers: remove sched.h from interrupt.h
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
5a6a256e
TW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
5a6a256e
TW		 28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
d43c36dc 32#include <linux/sched.h>
5a6a256e
TW		 33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
37#include <linux/etherdevice.h>
38#include <asm/unaligned.h>
39
40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
5a6a256e
TW		 42#include "iwl-core.h"
43#include "iwl-io.h"
e26e47d9 44#include "iwl-sta.h"
5a6a256e
TW		 45#include "iwl-helpers.h"
46#include "iwl-5000-hw.h"
c0bac76a 47#include "iwl-6000-hw.h"
5a6a256e 48
a0987a8d 49/* Highest firmware API version supported */
c9d2fbf3 50#define IWL5000_UCODE_API_MAX 2
39e6d225 51#define IWL5150_UCODE_API_MAX 2
5a6a256e 52
a0987a8d
RC		 53/* Lowest firmware API version supported */
54#define IWL5000_UCODE_API_MIN 1
55#define IWL5150_UCODE_API_MIN 1
56
57#define IWL5000_FW_PRE "iwlwifi-5000-"
58#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
59#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
60
61#define IWL5150_FW_PRE "iwlwifi-5150-"
62#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
63#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
4e062f99 64
99da1b48
RR		 65static const u16 iwl5000_default_queue_to_tx_fifo[] = {
66 IWL_TX_FIFO_AC3,
67 IWL_TX_FIFO_AC2,
68 IWL_TX_FIFO_AC1,
69 IWL_TX_FIFO_AC0,
70 IWL50_CMD_FIFO_NUM,
71 IWL_TX_FIFO_HCCA_1,
72 IWL_TX_FIFO_HCCA_2
73};
74
46315e01
TW		 75/* FIXME: same implementation as 4965 */
76static int iwl5000_apm_stop_master(struct iwl_priv *priv)
77{
46315e01
TW		 78 unsigned long flags;
79
80 spin_lock_irqsave(&priv->lock, flags);
81
82 /* set stop master bit */
83 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
84
febf3370 85 iwl_poll_direct_bit(priv, CSR_RESET,
46315e01 86 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
46315e01 87
46315e01 88 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 89 IWL_DEBUG_INFO(priv, "stop master\n");
46315e01 90
febf3370 91 return 0;
46315e01
TW		 92}
93
94
672639de 95int iwl5000_apm_init(struct iwl_priv *priv)
30d59260
TW		 96{
97 int ret = 0;
98
99 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
100 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
101
8f061891
TW		 102 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
103 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
104 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
105
a96a27f9 106 /* Set FH wait threshold to maximum (HW error during stress W/A) */
4c43e0d0
TW		 107 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
108
109 /* enable HAP INTA to move device L1a -> L0s */
110 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
111 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
112
050681b7
JS		 113 if (priv->cfg->need_pll_cfg)
114 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
30d59260
TW		 115
116 /* set "initialization complete" bit to move adapter
117 * D0U* --> D0A* state */
118 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
119
120 /* wait for clock stabilization */
73d7b5ac
ZY		 121 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
122 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
30d59260 123 if (ret < 0) {
e1623446 124 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
30d59260
TW		 125 return ret;
126 }
127
30d59260 128 /* enable DMA */
8f061891 129 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
30d59260
TW		 130
131 udelay(20);
132
8f061891 133 /* disable L1-Active */
30d59260 134 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
8f061891 135 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
30d59260 136
30d59260
TW		 137 return ret;
138}
139
a96a27f9 140/* FIXME: this is identical to 4965 */
672639de 141void iwl5000_apm_stop(struct iwl_priv *priv)
f118a91d
TW		 142{
143 unsigned long flags;
144
46315e01 145 iwl5000_apm_stop_master(priv);
f118a91d
TW		 146
147 spin_lock_irqsave(&priv->lock, flags);
148
149 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
150
151 udelay(10);
152
1d3e6c61
MA		 153 /* clear "init complete" move adapter D0A* --> D0U state */
154 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d
TW		 155
156 spin_unlock_irqrestore(&priv->lock, flags);
157}
158
159
672639de 160int iwl5000_apm_reset(struct iwl_priv *priv)
7f066108
TW		 161{
162 int ret = 0;
7f066108 163
46315e01 164 iwl5000_apm_stop_master(priv);
7f066108 165
7f066108
TW		 166 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
167
168 udelay(10);
169
170
171 /* FIXME: put here L1A -L0S w/a */
172
050681b7
JS		 173 if (priv->cfg->need_pll_cfg)
174 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
7f066108
TW		 175
176 /* set "initialization complete" bit to move adapter
177 * D0U* --> D0A* state */
178 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
179
180 /* wait for clock stabilization */
73d7b5ac
ZY		 181 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
182 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
7f066108 183 if (ret < 0) {
e1623446 184 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
7f066108
TW		 185 goto out;
186 }
187
7f066108
TW		 188 /* enable DMA */
189 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
190
191 udelay(20);
192
193 /* disable L1-Active */
194 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
195 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
7f066108 196out:
7f066108
TW		 197
198 return ret;
199}
200
201
65b7998a 202/* NIC configuration for 5000 series and up */
672639de 203void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 204{
205 unsigned long flags;
206 u16 radio_cfg;
3fdb68de 207 u16 lctl;
e86fe9f6
TW		 208
209 spin_lock_irqsave(&priv->lock, flags);
210
3fdb68de 211 lctl = iwl_pcie_link_ctl(priv);
e86fe9f6 212
3fdb68de
TW		 213 /* HW bug W/A */
214 /* L1-ASPM is enabled by BIOS */
215 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
216 /* L1-APSM enabled: disable L0S */
8f061891
TW		 217 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
218 else
3fdb68de 219 /* L1-ASPM disabled: enable L0S */
8f061891 220 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
e86fe9f6
TW		 221
222 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
223
224 /* write radio config values to register */
225 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
226 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
227 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
228 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
229 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
230
231 /* set CSR_HW_CONFIG_REG for uCode use */
232 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
233 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
234 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
235
4c43e0d0
TW		 236 /* W/A : NIC is stuck in a reset state after Early PCIe power off
237 * (PCIe power is lost before PERST# is asserted),
238 * causing ME FW to lose ownership and not being able to obtain it back.
239 */
2d3db679 240 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
4c43e0d0
TW		 241 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
242 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
243
02c06e4a 244
e86fe9f6
TW		 245 spin_unlock_irqrestore(&priv->lock, flags);
246}
247
248
25ae3986
TW		 249/*
250 * EEPROM
251 */
252static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
253{
254 u16 offset = 0;
255
256 if ((address & INDIRECT_ADDRESS) == 0)
257 return address;
258
259 switch (address & INDIRECT_TYPE_MSK) {
260 case INDIRECT_HOST:
261 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
262 break;
263 case INDIRECT_GENERAL:
264 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
265 break;
266 case INDIRECT_REGULATORY:
267 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
268 break;
269 case INDIRECT_CALIBRATION:
270 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
271 break;
272 case INDIRECT_PROCESS_ADJST:
273 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
274 break;
275 case INDIRECT_OTHERS:
276 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
277 break;
278 default:
15b1687c 279 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
25ae3986
TW		 280 address & INDIRECT_TYPE_MSK);
281 break;
282 }
283
284 /* translate the offset from words to byte */
285 return (address & ADDRESS_MSK) + (offset << 1);
286}
287
672639de 288u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
f1f69415 289{
f1f69415
TW		 290 struct iwl_eeprom_calib_hdr {
291 u8 version;
292 u8 pa_type;
293 u16 voltage;
294 } *hdr;
295
f1f69415
TW		 296 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
297 EEPROM_5000_CALIB_ALL);
0ef2ca67 298 return hdr->version;
f1f69415
TW		 299
300}
301
33fd5033
EG		 302static void iwl5000_gain_computation(struct iwl_priv *priv,
303 u32 average_noise[NUM_RX_CHAINS],
304 u16 min_average_noise_antenna_i,
305 u32 min_average_noise)
306{
307 int i;
308 s32 delta_g;
309 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
310
311 /* Find Gain Code for the antennas B and C */
312 for (i = 1; i < NUM_RX_CHAINS; i++) {
313 if ((data->disconn_array[i])) {
314 data->delta_gain_code[i] = 0;
315 continue;
316 }
317 delta_g = (1000 * ((s32)average_noise[0] -
318 (s32)average_noise[i])) / 1500;
319 /* bound gain by 2 bits value max, 3rd bit is sign */
320 data->delta_gain_code[i] =
321 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
322
323 if (delta_g < 0)
324 /* set negative sign */
325 data->delta_gain_code[i] |= (1 << 2);
326 }
327
e1623446 328 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
33fd5033
EG		 329 data->delta_gain_code[1], data->delta_gain_code[2]);
330
331 if (!data->radio_write) {
f69f42a6 332 struct iwl_calib_chain_noise_gain_cmd cmd;
0d950d84 333
33fd5033
EG		 334 memset(&cmd, 0, sizeof(cmd));
335
0d950d84
TW		 336 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
337 cmd.hdr.first_group = 0;
338 cmd.hdr.groups_num = 1;
339 cmd.hdr.data_valid = 1;
33fd5033
EG		 340 cmd.delta_gain_1 = data->delta_gain_code[1];
341 cmd.delta_gain_2 = data->delta_gain_code[2];
342 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
343 sizeof(cmd), &cmd, NULL);
344
345 data->radio_write = 1;
346 data->state = IWL_CHAIN_NOISE_CALIBRATED;
347 }
348
349 data->chain_noise_a = 0;
350 data->chain_noise_b = 0;
351 data->chain_noise_c = 0;
352 data->chain_signal_a = 0;
353 data->chain_signal_b = 0;
354 data->chain_signal_c = 0;
355 data->beacon_count = 0;
356}
357
358static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
359{
360 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
0d950d84 361 int ret;
33fd5033
EG		 362
363 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 364 struct iwl_calib_chain_noise_reset_cmd cmd;
33fd5033 365 memset(&cmd, 0, sizeof(cmd));
0d950d84
TW		 366
367 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
368 cmd.hdr.first_group = 0;
369 cmd.hdr.groups_num = 1;
370 cmd.hdr.data_valid = 1;
371 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
372 sizeof(cmd), &cmd);
373 if (ret)
15b1687c
WT		 374 IWL_ERR(priv,
375 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
33fd5033 376 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
e1623446 377 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
33fd5033
EG		 378 }
379}
380
e8c00dcb 381void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
a326a5d0
EG		 382 __le32 *tx_flags)
383{
e6a9854b
JB		 384 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
385 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
a326a5d0
EG		 386 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
387 else
388 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
389}
390
33fd5033
EG		 391static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
392 .min_nrg_cck = 95,
fe6efb4b 393 .max_nrg_cck = 0, /* not used, set to 0 */
33fd5033
EG		 394 .auto_corr_min_ofdm = 90,
395 .auto_corr_min_ofdm_mrc = 170,
396 .auto_corr_min_ofdm_x1 = 120,
397 .auto_corr_min_ofdm_mrc_x1 = 240,
398
399 .auto_corr_max_ofdm = 120,
400 .auto_corr_max_ofdm_mrc = 210,
401 .auto_corr_max_ofdm_x1 = 155,
402 .auto_corr_max_ofdm_mrc_x1 = 290,
403
404 .auto_corr_min_cck = 125,
405 .auto_corr_max_cck = 200,
406 .auto_corr_min_cck_mrc = 170,
407 .auto_corr_max_cck_mrc = 400,
408 .nrg_th_cck = 95,
409 .nrg_th_ofdm = 95,
410};
411
9d67187d
WYG		 412static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
413 .min_nrg_cck = 95,
414 .max_nrg_cck = 0, /* not used, set to 0 */
415 .auto_corr_min_ofdm = 90,
416 .auto_corr_min_ofdm_mrc = 170,
417 .auto_corr_min_ofdm_x1 = 105,
418 .auto_corr_min_ofdm_mrc_x1 = 220,
419
420 .auto_corr_max_ofdm = 120,
421 .auto_corr_max_ofdm_mrc = 210,
422 /* max = min for performance bug in 5150 DSP */
423 .auto_corr_max_ofdm_x1 = 105,
424 .auto_corr_max_ofdm_mrc_x1 = 220,
425
426 .auto_corr_min_cck = 125,
427 .auto_corr_max_cck = 200,
428 .auto_corr_min_cck_mrc = 170,
429 .auto_corr_max_cck_mrc = 400,
430 .nrg_th_cck = 95,
431 .nrg_th_ofdm = 95,
432};
433
672639de 434const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
25ae3986
TW		 435 size_t offset)
436{
437 u32 address = eeprom_indirect_address(priv, offset);
438 BUG_ON(address >= priv->cfg->eeprom_size);
439 return &priv->eeprom[address];
440}
441
62161aef 442static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
339afc89 443{
62161aef 444 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
672639de 445 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
62161aef
WYG		 446 iwl_temp_calib_to_offset(priv);
447
448 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
449}
450
451static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
452{
453 /* want Celsius */
672639de 454 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
339afc89
TW		 455}
456
7c616cba
TW		 457/*
458 * Calibration
459 */
be5d56ed 460static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
7c616cba 461{
0d950d84 462 struct iwl_calib_xtal_freq_cmd cmd;
7c616cba
TW		 463 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
464
0d950d84
TW		 465 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
466 cmd.hdr.first_group = 0;
467 cmd.hdr.groups_num = 1;
468 cmd.hdr.data_valid = 1;
469 cmd.cap_pin1 = (u8)xtal_calib[0];
470 cmd.cap_pin2 = (u8)xtal_calib[1];
f69f42a6 471 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
0d950d84 472 (u8 *)&cmd, sizeof(cmd));
7c616cba
TW		 473}
474
7c616cba
TW		 475static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
476{
f69f42a6 477 struct iwl_calib_cfg_cmd calib_cfg_cmd;
7c616cba
TW		 478 struct iwl_host_cmd cmd = {
479 .id = CALIBRATION_CFG_CMD,
f69f42a6 480 .len = sizeof(struct iwl_calib_cfg_cmd),
7c616cba
TW		 481 .data = &calib_cfg_cmd,
482 };
483
484 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
485 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
486 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
487 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
488 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
489
490 return iwl_send_cmd(priv, &cmd);
491}
492
493static void iwl5000_rx_calib_result(struct iwl_priv *priv,
494 struct iwl_rx_mem_buffer *rxb)
495{
496 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
f69f42a6 497 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
396887a2 498 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
6e21f2c1 499 int index;
7c616cba
TW		 500
501 /* reduce the size of the length field itself */
502 len -= 4;
503
6e21f2c1
TW		 504 /* Define the order in which the results will be sent to the runtime
505 * uCode. iwl_send_calib_results sends them in a row according to their
506 * index. We sort them here */
7c616cba 507 switch (hdr->op_code) {
819500c5
TW		 508 case IWL_PHY_CALIBRATE_DC_CMD:
509 index = IWL_CALIB_DC;
510 break;
f69f42a6
TW		 511 case IWL_PHY_CALIBRATE_LO_CMD:
512 index = IWL_CALIB_LO;
7c616cba 513 break;
f69f42a6
TW		 514 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
515 index = IWL_CALIB_TX_IQ;
7c616cba 516 break;
f69f42a6
TW		 517 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
518 index = IWL_CALIB_TX_IQ_PERD;
7c616cba 519 break;
201706ac
TW		 520 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
521 index = IWL_CALIB_BASE_BAND;
522 break;
7c616cba 523 default:
15b1687c 524 IWL_ERR(priv, "Unknown calibration notification %d\n",
7c616cba
TW		 525 hdr->op_code);
526 return;
527 }
6e21f2c1 528 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
7c616cba
TW		 529}
530
531static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
532 struct iwl_rx_mem_buffer *rxb)
533{
e1623446 534 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
7c616cba
TW		 535 queue_work(priv->workqueue, &priv->restart);
536}
537
dbb983b7
RR		 538/*
539 * ucode
540 */
541static int iwl5000_load_section(struct iwl_priv *priv,
542 struct fw_desc *image,
543 u32 dst_addr)
544{
dbb983b7
RR		 545 dma_addr_t phy_addr = image->p_addr;
546 u32 byte_cnt = image->len;
547
dbb983b7
RR		 548 iwl_write_direct32(priv,
549 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
550 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
551
552 iwl_write_direct32(priv,
553 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
554
555 iwl_write_direct32(priv,
556 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
557 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
558
dbb983b7 559 iwl_write_direct32(priv,
f0b9f5cb 560 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
499b1883 561 (iwl_get_dma_hi_addr(phy_addr)
f0b9f5cb
TW		 562 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
563
dbb983b7
RR		 564 iwl_write_direct32(priv,
565 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
566 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
567 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
568 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
569
570 iwl_write_direct32(priv,
571 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
572 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
9c80c502 573 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
dbb983b7
RR		 574 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
575
dbb983b7
RR		 576 return 0;
577}
578
579static int iwl5000_load_given_ucode(struct iwl_priv *priv,
580 struct fw_desc *inst_image,
581 struct fw_desc *data_image)
582{
583 int ret = 0;
584
250bdd21
SO		 585 ret = iwl5000_load_section(priv, inst_image,
586 IWL50_RTC_INST_LOWER_BOUND);
dbb983b7
RR		 587 if (ret)
588 return ret;
589
e1623446 590 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
dbb983b7 591 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
9c80c502 592 priv->ucode_write_complete, 5 * HZ);
dbb983b7 593 if (ret == -ERESTARTSYS) {
15b1687c 594 IWL_ERR(priv, "Could not load the INST uCode section due "
dbb983b7
RR		 595 "to interrupt\n");
596 return ret;
597 }
598 if (!ret) {
15b1687c 599 IWL_ERR(priv, "Could not load the INST uCode section\n");
dbb983b7
RR		 600 return -ETIMEDOUT;
601 }
602
603 priv->ucode_write_complete = 0;
604
605 ret = iwl5000_load_section(
250bdd21 606 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
dbb983b7
RR		 607 if (ret)
608 return ret;
609
e1623446 610 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
dbb983b7
RR		 611
612 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
613 priv->ucode_write_complete, 5 * HZ);
614 if (ret == -ERESTARTSYS) {
15b1687c 615 IWL_ERR(priv, "Could not load the INST uCode section due "
dbb983b7
RR		 616 "to interrupt\n");
617 return ret;
618 } else if (!ret) {
15b1687c 619 IWL_ERR(priv, "Could not load the DATA uCode section\n");
dbb983b7
RR		 620 return -ETIMEDOUT;
621 } else
622 ret = 0;
623
624 priv->ucode_write_complete = 0;
625
626 return ret;
627}
628
672639de 629int iwl5000_load_ucode(struct iwl_priv *priv)
dbb983b7
RR		 630{
631 int ret = 0;
632
633 /* check whether init ucode should be loaded, or rather runtime ucode */
634 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
e1623446 635 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
dbb983b7
RR		 636 ret = iwl5000_load_given_ucode(priv,
637 &priv->ucode_init, &priv->ucode_init_data);
638 if (!ret) {
e1623446 639 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
dbb983b7
RR		 640 priv->ucode_type = UCODE_INIT;
641 }
642 } else {
e1623446 643 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
dbb983b7
RR		 644 "Loading runtime ucode...\n");
645 ret = iwl5000_load_given_ucode(priv,
646 &priv->ucode_code, &priv->ucode_data);
647 if (!ret) {
e1623446 648 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
dbb983b7
RR		 649 priv->ucode_type = UCODE_RT;
650 }
651 }
652
653 return ret;
654}
655
672639de 656void iwl5000_init_alive_start(struct iwl_priv *priv)
99da1b48
RR		 657{
658 int ret = 0;
659
660 /* Check alive response for "valid" sign from uCode */
661 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
662 /* We had an error bringing up the hardware, so take it
663 * all the way back down so we can try again */
e1623446 664 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
99da1b48
RR		 665 goto restart;
666 }
667
668 /* initialize uCode was loaded... verify inst image.
669 * This is a paranoid check, because we would not have gotten the
670 * "initialize" alive if code weren't properly loaded. */
671 if (iwl_verify_ucode(priv)) {
672 /* Runtime instruction load was bad;
673 * take it all the way back down so we can try again */
e1623446 674 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
99da1b48
RR		 675 goto restart;
676 }
677
c587de0b 678 iwl_clear_stations_table(priv);
99da1b48
RR		 679 ret = priv->cfg->ops->lib->alive_notify(priv);
680 if (ret) {
39aadf8c
WT		 681 IWL_WARN(priv,
682 "Could not complete ALIVE transition: %d\n", ret);
99da1b48
RR		 683 goto restart;
684 }
685
7c616cba 686 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 687 return;
688
689restart:
690 /* real restart (first load init_ucode) */
691 queue_work(priv->workqueue, &priv->restart);
692}
693
694static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
695 int txq_id, u32 index)
696{
697 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
698 (index & 0xff) | (txq_id << 8));
699 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
700}
701
702static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
703 struct iwl_tx_queue *txq,
704 int tx_fifo_id, int scd_retry)
705{
706 int txq_id = txq->q.id;
3fd07a1e 707 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
99da1b48
RR		 708
709 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
710 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
711 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
712 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
713 IWL50_SCD_QUEUE_STTS_REG_MSK);
714
715 txq->sched_retry = scd_retry;
716
e1623446 717 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
99da1b48
RR		 718 active ? "Activate" : "Deactivate",
719 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
720}
721
9636e583
RR		 722static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
723{
724 struct iwl_wimax_coex_cmd coex_cmd;
725
726 memset(&coex_cmd, 0, sizeof(coex_cmd));
727
728 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
729 sizeof(coex_cmd), &coex_cmd);
730}
731
672639de 732int iwl5000_alive_notify(struct iwl_priv *priv)
99da1b48
RR		 733{
734 u32 a;
99da1b48 735 unsigned long flags;
31a73fe4 736 int i, chan;
40fc95d5 737 u32 reg_val;
99da1b48
RR		 738
739 spin_lock_irqsave(&priv->lock, flags);
740
99da1b48
RR		 741 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
742 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
743 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
744 a += 4)
745 iwl_write_targ_mem(priv, a, 0);
746 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
747 a += 4)
748 iwl_write_targ_mem(priv, a, 0);
749 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
750 iwl_write_targ_mem(priv, a, 0);
751
752 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
4ddbb7d0 753 priv->scd_bc_tbls.dma >> 10);
31a73fe4
WT		 754
755 /* Enable DMA channel */
756 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
757 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
758 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
759 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
760
40fc95d5
WT		 761 /* Update FH chicken bits */
762 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
763 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
764 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
765
99da1b48 766 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
4ddbb7d0 767 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
99da1b48
RR		 768 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
769
770 /* initiate the queues */
771 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
772 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
773 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
774 iwl_write_targ_mem(priv, priv->scd_base_addr +
775 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
776 iwl_write_targ_mem(priv, priv->scd_base_addr +
777 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
778 sizeof(u32),
779 ((SCD_WIN_SIZE <<
780 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
781 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
782 ((SCD_FRAME_LIMIT <<
783 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
784 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
785 }
786
787 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 788 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 789
da1bc453
TW		 790 /* Activate all Tx DMA/FIFO channels */
791 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 792
793 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
9c80c502 794
99da1b48
RR		 795 /* map qos queues to fifos one-to-one */
796 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
797 int ac = iwl5000_default_queue_to_tx_fifo[i];
798 iwl_txq_ctx_activate(priv, i);
799 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
800 }
801 /* TODO - need to initialize those FIFOs inside the loop above,
802 * not only mark them as active */
803 iwl_txq_ctx_activate(priv, 4);
804 iwl_txq_ctx_activate(priv, 7);
805 iwl_txq_ctx_activate(priv, 8);
806 iwl_txq_ctx_activate(priv, 9);
807
99da1b48
RR		 808 spin_unlock_irqrestore(&priv->lock, flags);
809
7c616cba 810
9636e583
RR		 811 iwl5000_send_wimax_coex(priv);
812
be5d56ed
TW		 813 iwl5000_set_Xtal_calib(priv);
814 iwl_send_calib_results(priv);
7c616cba 815
99da1b48
RR		 816 return 0;
817}
818
672639de 819int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
fdd3e8a4
TW		 820{
821 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
822 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
15b1687c
WT		 823 IWL_ERR(priv,
824 "invalid queues_num, should be between %d and %d\n",
825 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
fdd3e8a4
TW		 826 return -EINVAL;
827 }
25ae3986 828
fdd3e8a4 829 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
f3f911d1 830 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
4ddbb7d0
TW		 831 priv->hw_params.scd_bc_tbls_size =
832 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
a8e74e27 833 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
fdd3e8a4
TW		 834 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
835 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
c0bac76a
JS		 836
837 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
838 case CSR_HW_REV_TYPE_6x00:
839 case CSR_HW_REV_TYPE_6x50:
840 priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
841 priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
842 break;
843 default:
844 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
845 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
846 }
847
da154e30 848 priv->hw_params.max_bsm_size = 0;
7aafef1c 849 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
fdd3e8a4 850 BIT(IEEE80211_BAND_5GHZ);
141c43a3
WT		 851 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
852
c0bac76a
JS		 853 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
854 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
855 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
856 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
c031bf80 857
62161aef
WYG		 858 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
859 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
c031bf80 860
9d67187d 861 /* Set initial sensitivity parameters */
be5d56ed
TW		 862 /* Set initial calibration set */
863 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
c0bac76a 864 case CSR_HW_REV_TYPE_5150:
9d67187d 865 priv->hw_params.sens = &iwl5150_sensitivity;
be5d56ed 866 priv->hw_params.calib_init_cfg =
c0bac76a 867 BIT(IWL_CALIB_DC) |
f69f42a6 868 BIT(IWL_CALIB_LO) |
201706ac 869 BIT(IWL_CALIB_TX_IQ) |
201706ac 870 BIT(IWL_CALIB_BASE_BAND);
c0bac76a 871
be5d56ed 872 break;
c0bac76a 873 default:
9d67187d 874 priv->hw_params.sens = &iwl5000_sensitivity;
819500c5 875 priv->hw_params.calib_init_cfg =
c0bac76a 876 BIT(IWL_CALIB_XTAL) |
7470d7f5
WT		 877 BIT(IWL_CALIB_LO) |
878 BIT(IWL_CALIB_TX_IQ) |
c0bac76a 879 BIT(IWL_CALIB_TX_IQ_PERD) |
7470d7f5 880 BIT(IWL_CALIB_BASE_BAND);
be5d56ed
TW		 881 break;
882 }
883
fdd3e8a4
TW		 884 return 0;
885}
d4100dd9 886
7839fc03
EG		 887/**
888 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
889 */
672639de 890void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 891 struct iwl_tx_queue *txq,
7839fc03
EG		 892 u16 byte_cnt)
893{
4ddbb7d0 894 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab 895 int write_ptr = txq->q.write_ptr;
7839fc03
EG		 896 int txq_id = txq->q.id;
897 u8 sec_ctl = 0;
127901ab
TW		 898 u8 sta_id = 0;
899 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
900 __le16 bc_ent;
7839fc03 901
127901ab 902 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
7839fc03
EG		 903
904 if (txq_id != IWL_CMD_QUEUE_NUM) {
127901ab 905 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
da99c4b6 906 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 907
908 switch (sec_ctl & TX_CMD_SEC_MSK) {
909 case TX_CMD_SEC_CCM:
910 len += CCMP_MIC_LEN;
911 break;
912 case TX_CMD_SEC_TKIP:
913 len += TKIP_ICV_LEN;
914 break;
915 case TX_CMD_SEC_WEP:
916 len += WEP_IV_LEN + WEP_ICV_LEN;
917 break;
918 }
919 }
920
127901ab 921 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
7839fc03 922
4ddbb7d0 923 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
7839fc03 924
127901ab 925 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 926 scd_bc_tbl[txq_id].
127901ab 927 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
7839fc03
EG		 928}
929
672639de 930void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
972cf447
TW		 931 struct iwl_tx_queue *txq)
932{
4ddbb7d0 933 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 934 int txq_id = txq->q.id;
935 int read_ptr = txq->q.read_ptr;
936 u8 sta_id = 0;
937 __le16 bc_ent;
938
939 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
972cf447
TW		 940
941 if (txq_id != IWL_CMD_QUEUE_NUM)
127901ab 942 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
972cf447 943
127901ab 944 bc_ent = cpu_to_le16(1 | (sta_id << 12));
4ddbb7d0 945 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
972cf447 946
127901ab 947 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 948 scd_bc_tbl[txq_id].
127901ab 949 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
972cf447
TW		 950}
951
e26e47d9
TW		 952static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
953 u16 txq_id)
954{
955 u32 tbl_dw_addr;
956 u32 tbl_dw;
957 u16 scd_q2ratid;
958
959 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
960
961 tbl_dw_addr = priv->scd_base_addr +
962 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
963
964 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
965
966 if (txq_id & 0x1)
967 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
968 else
969 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
970
971 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
972
973 return 0;
974}
975static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
976{
977 /* Simply stop the queue, but don't change any configuration;
978 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
979 iwl_write_prph(priv,
980 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
981 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
982 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
983}
984
672639de 985int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
e26e47d9
TW		 986 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
987{
988 unsigned long flags;
e26e47d9
TW		 989 u16 ra_tid;
990
9f17b318
TW		 991 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
992 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
39aadf8c
WT		 993 IWL_WARN(priv,
994 "queue number out of range: %d, must be %d to %d\n",
9f17b318
TW		 995 txq_id, IWL50_FIRST_AMPDU_QUEUE,
996 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
997 return -EINVAL;
998 }
e26e47d9
TW		 999
1000 ra_tid = BUILD_RAxTID(sta_id, tid);
1001
1002 /* Modify device's station table to Tx this TID */
9f58671e 1003 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
e26e47d9
TW		 1004
1005 spin_lock_irqsave(&priv->lock, flags);
e26e47d9
TW		 1006
1007 /* Stop this Tx queue before configuring it */
1008 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1009
1010 /* Map receiver-address / traffic-ID to this queue */
1011 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1012
1013 /* Set this queue as a chain-building queue */
1014 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1015
1016 /* enable aggregations for the queue */
1017 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1018
1019 /* Place first TFD at index corresponding to start sequence number.
1020 * Assumes that ssn_idx is valid (!= 0xFFF) */
1021 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1022 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1023 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1024
1025 /* Set up Tx window size and frame limit for this queue */
1026 iwl_write_targ_mem(priv, priv->scd_base_addr +
1027 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1028 sizeof(u32),
1029 ((SCD_WIN_SIZE <<
1030 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1031 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1032 ((SCD_FRAME_LIMIT <<
1033 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1034 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1035
1036 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1037
1038 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1039 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1040
e26e47d9
TW		 1041 spin_unlock_irqrestore(&priv->lock, flags);
1042
1043 return 0;
1044}
1045
672639de 1046int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
e26e47d9
TW		 1047 u16 ssn_idx, u8 tx_fifo)
1048{
9f17b318
TW		 1049 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1050 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
a2f1cbeb 1051 IWL_ERR(priv,
39aadf8c 1052 "queue number out of range: %d, must be %d to %d\n",
9f17b318
TW		 1053 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1054 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
e26e47d9
TW		 1055 return -EINVAL;
1056 }
1057
e26e47d9
TW		 1058 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1059
1060 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1061
1062 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1063 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1064 /* supposes that ssn_idx is valid (!= 0xFFF) */
1065 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1066
1067 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1068 iwl_txq_ctx_deactivate(priv, txq_id);
1069 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1070
e26e47d9
TW		 1071 return 0;
1072}
1073
e8c00dcb 1074u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2469bf2e
TW		 1075{
1076 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
c587de0b
TW		 1077 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1078 memcpy(addsta, cmd, size);
1079 /* resrved in 5000 */
1080 addsta->rate_n_flags = cpu_to_le16(0);
2469bf2e
TW		 1081 return size;
1082}
1083
1084
da1bc453 1085/*
a96a27f9 1086 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 1087 * must be called under priv->lock and mac access
1088 */
672639de 1089void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 1090{
da1bc453 1091 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 1092}
1093
e532fa0e
RR		 1094
1095static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1096{
3ac7f146 1097 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 1098 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 1099}
1100
1101static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1102 struct iwl_ht_agg *agg,
1103 struct iwl5000_tx_resp *tx_resp,
25a6572c 1104 int txq_id, u16 start_idx)
e532fa0e
RR		 1105{
1106 u16 status;
1107 struct agg_tx_status *frame_status = &tx_resp->status;
1108 struct ieee80211_tx_info *info = NULL;
1109 struct ieee80211_hdr *hdr = NULL;
e7d326ac 1110 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 1111 int i, sh, idx;
e532fa0e
RR		 1112 u16 seq;
1113
1114 if (agg->wait_for_ba)
e1623446 1115 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
e532fa0e
RR		 1116
1117 agg->frame_count = tx_resp->frame_count;
1118 agg->start_idx = start_idx;
e7d326ac 1119 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 1120 agg->bitmap = 0;
1121
1122 /* # frames attempted by Tx command */
1123 if (agg->frame_count == 1) {
1124 /* Only one frame was attempted; no block-ack will arrive */
1125 status = le16_to_cpu(frame_status[0].status);
25a6572c 1126 idx = start_idx;
e532fa0e
RR		 1127
1128 /* FIXME: code repetition */
e1623446 1129 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
e532fa0e
RR		 1130 agg->frame_count, agg->start_idx, idx);
1131
1132 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 1133 info->status.rates[0].count = tx_resp->failure_frame + 1;
e532fa0e 1134 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c3056065 1135 info->flags |= iwl_is_tx_success(status) ?
3fd07a1e 1136 IEEE80211_TX_STAT_ACK : 0;
e7d326ac
TW		 1137 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1138
e532fa0e
RR		 1139 /* FIXME: code repetition end */
1140
e1623446 1141 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
e532fa0e 1142 status & 0xff, tx_resp->failure_frame);
e1623446 1143 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1144
1145 agg->wait_for_ba = 0;
1146 } else {
1147 /* Two or more frames were attempted; expect block-ack */
1148 u64 bitmap = 0;
1149 int start = agg->start_idx;
1150
1151 /* Construct bit-map of pending frames within Tx window */
1152 for (i = 0; i < agg->frame_count; i++) {
1153 u16 sc;
1154 status = le16_to_cpu(frame_status[i].status);
1155 seq = le16_to_cpu(frame_status[i].sequence);
1156 idx = SEQ_TO_INDEX(seq);
1157 txq_id = SEQ_TO_QUEUE(seq);
1158
1159 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1160 AGG_TX_STATE_ABORT_MSK))
1161 continue;
1162
e1623446 1163 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
e532fa0e
RR		 1164 agg->frame_count, txq_id, idx);
1165
1166 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
6c6a22e2
SG		 1167 if (!hdr) {
1168 IWL_ERR(priv,
1169 "BUG_ON idx doesn't point to valid skb"
1170 " idx=%d, txq_id=%d\n", idx, txq_id);
1171 return -1;
1172 }
e532fa0e
RR		 1173
1174 sc = le16_to_cpu(hdr->seq_ctrl);
1175 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
15b1687c
WT		 1176 IWL_ERR(priv,
1177 "BUG_ON idx doesn't match seq control"
1178 " idx=%d, seq_idx=%d, seq=%d\n",
e532fa0e
RR		 1179 idx, SEQ_TO_SN(sc),
1180 hdr->seq_ctrl);
1181 return -1;
1182 }
1183
e1623446 1184 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
e532fa0e
RR		 1185 i, idx, SEQ_TO_SN(sc));
1186
1187 sh = idx - start;
1188 if (sh > 64) {
1189 sh = (start - idx) + 0xff;
1190 bitmap = bitmap << sh;
1191 sh = 0;
1192 start = idx;
1193 } else if (sh < -64)
1194 sh = 0xff - (start - idx);
1195 else if (sh < 0) {
1196 sh = start - idx;
1197 start = idx;
1198 bitmap = bitmap << sh;
1199 sh = 0;
1200 }
4aa41f12 1201 bitmap |= 1ULL << sh;
e1623446 1202 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
4aa41f12 1203 start, (unsigned long long)bitmap);
e532fa0e
RR		 1204 }
1205
1206 agg->bitmap = bitmap;
1207 agg->start_idx = start;
e1623446 1208 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
e532fa0e
RR		 1209 agg->frame_count, agg->start_idx,
1210 (unsigned long long)agg->bitmap);
1211
1212 if (bitmap)
1213 agg->wait_for_ba = 1;
1214 }
1215 return 0;
1216}
1217
1218static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1219 struct iwl_rx_mem_buffer *rxb)
1220{
1221 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1222 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1223 int txq_id = SEQ_TO_QUEUE(sequence);
1224 int index = SEQ_TO_INDEX(sequence);
1225 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1226 struct ieee80211_tx_info *info;
1227 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1228 u32 status = le16_to_cpu(tx_resp->status.status);
3fd07a1e
TW		 1229 int tid;
1230 int sta_id;
1231 int freed;
e532fa0e
RR		 1232
1233 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 1234 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
e532fa0e
RR		 1235 "is out of range [0-%d] %d %d\n", txq_id,
1236 index, txq->q.n_bd, txq->q.write_ptr,
1237 txq->q.read_ptr);
1238 return;
1239 }
1240
1241 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1242 memset(&info->status, 0, sizeof(info->status));
1243
3fd07a1e
TW		 1244 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1245 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
e532fa0e
RR		 1246
1247 if (txq->sched_retry) {
1248 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1249 struct iwl_ht_agg *agg = NULL;
1250
e532fa0e
RR		 1251 agg = &priv->stations[sta_id].tid[tid].agg;
1252
25a6572c 1253 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1254
3235427e
RR		 1255 /* check if BAR is needed */
1256 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1257 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1258
1259 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
e532fa0e 1260 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
e1623446 1261 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
3fd07a1e
TW		 1262 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1263 scd_ssn , index, txq_id, txq->swq_id);
1264
17b88929 1265 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1266 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1267
3fd07a1e
TW		 1268 if (priv->mac80211_registered &&
1269 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1270 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
e532fa0e 1271 if (agg->state == IWL_AGG_OFF)
e4e72fb4 1272 iwl_wake_queue(priv, txq_id);
e532fa0e 1273 else
e4e72fb4 1274 iwl_wake_queue(priv, txq->swq_id);
e532fa0e 1275 }
e532fa0e
RR		 1276 }
1277 } else {
3fd07a1e
TW		 1278 BUG_ON(txq_id != txq->swq_id);
1279
e6a9854b 1280 info->status.rates[0].count = tx_resp->failure_frame + 1;
3fd07a1e
TW		 1281 info->flags |= iwl_is_tx_success(status) ?
1282 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 1283 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1284 le32_to_cpu(tx_resp->rate_n_flags),
1285 info);
1286
e1623446 1287 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
3fd07a1e
TW		 1288 "0x%x retries %d\n",
1289 txq_id,
1290 iwl_get_tx_fail_reason(status), status,
1291 le32_to_cpu(tx_resp->rate_n_flags),
1292 tx_resp->failure_frame);
4f85f5b3 1293
3fd07a1e
TW		 1294 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1295 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
e532fa0e 1296 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 1297
1298 if (priv->mac80211_registered &&
1299 (iwl_queue_space(&txq->q) > txq->q.low_mark))
e4e72fb4 1300 iwl_wake_queue(priv, txq_id);
e532fa0e 1301 }
e532fa0e 1302
3fd07a1e
TW		 1303 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1304 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1305
e532fa0e 1306 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 1307 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
e532fa0e
RR		 1308}
1309
a96a27f9 1310/* Currently 5000 is the superset of everything */
e8c00dcb 1311u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
c1adf9fb
GG		 1312{
1313 return len;
1314}
1315
672639de 1316void iwl5000_setup_deferred_work(struct iwl_priv *priv)
203566f3
EG		 1317{
1318 /* in 5000 the tx power calibration is done in uCode */
1319 priv->disable_tx_power_cal = 1;
1320}
1321
672639de 1322void iwl5000_rx_handler_setup(struct iwl_priv *priv)
b600e4e1 1323{
7c616cba
TW		 1324 /* init calibration handlers */
1325 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1326 iwl5000_rx_calib_result;
1327 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1328 iwl5000_rx_calib_complete;
e532fa0e 1329 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1330}
1331
7c616cba 1332
672639de 1333int iwl5000_hw_valid_rtc_data_addr(u32 addr)
87283cc1 1334{
250bdd21 1335 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
87283cc1
RR		 1336 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1337}
1338
fe7a90c2
RR		 1339static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1340{
1341 int ret = 0;
1342 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1343 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1344 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1345
1346 if ((rxon1->flags == rxon2->flags) &&
1347 (rxon1->filter_flags == rxon2->filter_flags) &&
1348 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1349 (rxon1->ofdm_ht_single_stream_basic_rates ==
1350 rxon2->ofdm_ht_single_stream_basic_rates) &&
1351 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1352 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1353 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1354 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1355 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1356 (rxon1->rx_chain == rxon2->rx_chain) &&
1357 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
e1623446 1358 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
fe7a90c2
RR		 1359 return 0;
1360 }
1361
1362 rxon_assoc.flags = priv->staging_rxon.flags;
1363 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1364 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1365 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1366 rxon_assoc.reserved1 = 0;
1367 rxon_assoc.reserved2 = 0;
1368 rxon_assoc.reserved3 = 0;
1369 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1370 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1371 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1372 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1373 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1374 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1375 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1376 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1377
1378 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1379 sizeof(rxon_assoc), &rxon_assoc, NULL);
1380 if (ret)
1381 return ret;
1382
1383 return ret;
1384}
672639de 1385int iwl5000_send_tx_power(struct iwl_priv *priv)
630fe9b6
TW		 1386{
1387 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
76a2407a 1388 u8 tx_ant_cfg_cmd;
630fe9b6
TW		 1389
1390 /* half dBm need to multiply */
1391 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
853554ac 1392 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6 1393 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
76a2407a
JS		 1394
1395 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1396 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1397 else
1398 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1399
1400 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
630fe9b6
TW		 1401 sizeof(tx_power_cmd), &tx_power_cmd,
1402 NULL);
1403}
1404
672639de 1405void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1406{
1407 /* store temperature from statistics (in Celsius) */
5225640b 1408 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
39b73fb1 1409 iwl_tt_handler(priv);
8f91aecb 1410}
fe7a90c2 1411
62161aef
WYG		 1412static void iwl5150_temperature(struct iwl_priv *priv)
1413{
1414 u32 vt = 0;
1415 s32 offset = iwl_temp_calib_to_offset(priv);
1416
1417 vt = le32_to_cpu(priv->statistics.general.temperature);
1418 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1419 /* now vt hold the temperature in Kelvin */
1420 priv->temperature = KELVIN_TO_CELSIUS(vt);
15993e08 1421 iwl_tt_handler(priv);
62161aef
WYG		 1422}
1423
caab8f1a 1424/* Calc max signal level (dBm) among 3 possible receivers */
e8c00dcb 1425int iwl5000_calc_rssi(struct iwl_priv *priv,
caab8f1a
TW		 1426 struct iwl_rx_phy_res *rx_resp)
1427{
1428 /* data from PHY/DSP regarding signal strength, etc.,
1429 * contents are always there, not configurable by host
1430 */
1431 struct iwl5000_non_cfg_phy *ncphy =
1432 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1433 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1434 u8 agc;
1435
1436 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1437 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1438
1439 /* Find max rssi among 3 possible receivers.
1440 * These values are measured by the digital signal processor (DSP).
1441 * They should stay fairly constant even as the signal strength varies,
1442 * if the radio's automatic gain control (AGC) is working right.
1443 * AGC value (see below) will provide the "interesting" info.
1444 */
1445 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1446 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1447 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1448 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1449 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1450
1451 max_rssi = max_t(u32, rssi_a, rssi_b);
1452 max_rssi = max_t(u32, max_rssi, rssi_c);
1453
e1623446 1454 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
caab8f1a
TW		 1455 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1456
1457 /* dBm = max_rssi dB - agc dB - constant.
1458 * Higher AGC (higher radio gain) means lower signal. */
250bdd21 1459 return max_rssi - agc - IWL49_RSSI_OFFSET;
caab8f1a
TW		 1460}
1461
cc0f555d
JS		 1462#define IWL5000_UCODE_GET(item) \
1463static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1464 u32 api_ver) \
1465{ \
1466 if (api_ver <= 2) \
1467 return le32_to_cpu(ucode->u.v1.item); \
1468 return le32_to_cpu(ucode->u.v2.item); \
1469}
1470
1471static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1472{
1473 if (api_ver <= 2)
1474 return UCODE_HEADER_SIZE(1);
1475 return UCODE_HEADER_SIZE(2);
1476}
1477
1478static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1479 u32 api_ver)
1480{
1481 if (api_ver <= 2)
1482 return 0;
1483 return le32_to_cpu(ucode->u.v2.build);
1484}
1485
1486static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1487 u32 api_ver)
1488{
1489 if (api_ver <= 2)
1490 return (u8 *) ucode->u.v1.data;
1491 return (u8 *) ucode->u.v2.data;
1492}
1493
1494IWL5000_UCODE_GET(inst_size);
1495IWL5000_UCODE_GET(data_size);
1496IWL5000_UCODE_GET(init_size);
1497IWL5000_UCODE_GET(init_data_size);
1498IWL5000_UCODE_GET(boot_size);
1499
e8c00dcb 1500struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1501 .rxon_assoc = iwl5000_send_rxon_assoc,
e0158e61 1502 .commit_rxon = iwl_commit_rxon,
45823531 1503 .set_rxon_chain = iwl_set_rxon_chain,
da8dec29
TW		 1504};
1505
e8c00dcb 1506struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1507 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1508 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1509 .gain_computation = iwl5000_gain_computation,
1510 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1511 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1512 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1513};
1514
cc0f555d
JS		 1515struct iwl_ucode_ops iwl5000_ucode = {
1516 .get_header_size = iwl5000_ucode_get_header_size,
1517 .get_build = iwl5000_ucode_get_build,
1518 .get_inst_size = iwl5000_ucode_get_inst_size,
1519 .get_data_size = iwl5000_ucode_get_data_size,
1520 .get_init_size = iwl5000_ucode_get_init_size,
1521 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1522 .get_boot_size = iwl5000_ucode_get_boot_size,
1523 .get_data = iwl5000_ucode_get_data,
1524};
1525
e8c00dcb 1526struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1527 .set_hw_params = iwl5000_hw_set_hw_params,
7839fc03 1528 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1529 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1530 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1531 .txq_agg_enable = iwl5000_txq_agg_enable,
1532 .txq_agg_disable = iwl5000_txq_agg_disable,
7aaa1d79
SO		 1533 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1534 .txq_free_tfd = iwl_hw_txq_free_tfd,
a8e74e27 1535 .txq_init = iwl_hw_tx_queue_init,
b600e4e1 1536 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1537 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1538 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
b7a79404
RC		 1539 .dump_nic_event_log = iwl_dump_nic_event_log,
1540 .dump_nic_error_log = iwl_dump_nic_error_log,
dbb983b7 1541 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1542 .init_alive_start = iwl5000_init_alive_start,
1543 .alive_notify = iwl5000_alive_notify,
630fe9b6 1544 .send_tx_power = iwl5000_send_tx_power,
5b9f8cd3 1545 .update_chain_flags = iwl_update_chain_flags,
30d59260
TW		 1546 .apm_ops = {
1547 .init = iwl5000_apm_init,
7f066108 1548 .reset = iwl5000_apm_reset,
f118a91d 1549 .stop = iwl5000_apm_stop,
5a835353 1550 .config = iwl5000_nic_config,
5b9f8cd3 1551 .set_pwr_src = iwl_set_pwr_src,
30d59260 1552 },
da8dec29 1553 .eeprom_ops = {
25ae3986
TW		 1554 .regulatory_bands = {
1555 EEPROM_5000_REG_BAND_1_CHANNELS,
1556 EEPROM_5000_REG_BAND_2_CHANNELS,
1557 EEPROM_5000_REG_BAND_3_CHANNELS,
1558 EEPROM_5000_REG_BAND_4_CHANNELS,
1559 EEPROM_5000_REG_BAND_5_CHANNELS,
7aafef1c
WYG		 1560 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1561 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
25ae3986 1562 },
da8dec29
TW		 1563 .verify_signature = iwlcore_eeprom_verify_signature,
1564 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1565 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 1566 .calib_version = iwl5000_eeprom_calib_version,
25ae3986 1567 .query_addr = iwl5000_eeprom_query_addr,
da8dec29 1568 },
5bbe233b 1569 .post_associate = iwl_post_associate,
ef850d7c 1570 .isr = iwl_isr_ict,
60690a6a 1571 .config_ap = iwl_config_ap,
62161aef
WYG		 1572 .temp_ops = {
1573 .temperature = iwl5000_temperature,
1574 .set_ct_kill = iwl5000_set_ct_threshold,
1575 },
1576};
1577
1578static struct iwl_lib_ops iwl5150_lib = {
1579 .set_hw_params = iwl5000_hw_set_hw_params,
1580 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1581 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1582 .txq_set_sched = iwl5000_txq_set_sched,
1583 .txq_agg_enable = iwl5000_txq_agg_enable,
1584 .txq_agg_disable = iwl5000_txq_agg_disable,
1585 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1586 .txq_free_tfd = iwl_hw_txq_free_tfd,
1587 .txq_init = iwl_hw_tx_queue_init,
1588 .rx_handler_setup = iwl5000_rx_handler_setup,
1589 .setup_deferred_work = iwl5000_setup_deferred_work,
1590 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
b7a79404
RC		 1591 .dump_nic_event_log = iwl_dump_nic_event_log,
1592 .dump_nic_error_log = iwl_dump_nic_error_log,
62161aef
WYG		 1593 .load_ucode = iwl5000_load_ucode,
1594 .init_alive_start = iwl5000_init_alive_start,
1595 .alive_notify = iwl5000_alive_notify,
1596 .send_tx_power = iwl5000_send_tx_power,
1597 .update_chain_flags = iwl_update_chain_flags,
1598 .apm_ops = {
1599 .init = iwl5000_apm_init,
1600 .reset = iwl5000_apm_reset,
1601 .stop = iwl5000_apm_stop,
1602 .config = iwl5000_nic_config,
1603 .set_pwr_src = iwl_set_pwr_src,
1604 },
1605 .eeprom_ops = {
1606 .regulatory_bands = {
1607 EEPROM_5000_REG_BAND_1_CHANNELS,
1608 EEPROM_5000_REG_BAND_2_CHANNELS,
1609 EEPROM_5000_REG_BAND_3_CHANNELS,
1610 EEPROM_5000_REG_BAND_4_CHANNELS,
1611 EEPROM_5000_REG_BAND_5_CHANNELS,
7aafef1c
WYG		 1612 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1613 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
62161aef
WYG		 1614 },
1615 .verify_signature = iwlcore_eeprom_verify_signature,
1616 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1617 .release_semaphore = iwlcore_eeprom_release_semaphore,
1618 .calib_version = iwl5000_eeprom_calib_version,
1619 .query_addr = iwl5000_eeprom_query_addr,
1620 },
1621 .post_associate = iwl_post_associate,
ef850d7c 1622 .isr = iwl_isr_ict,
62161aef
WYG		 1623 .config_ap = iwl_config_ap,
1624 .temp_ops = {
1625 .temperature = iwl5150_temperature,
1626 .set_ct_kill = iwl5150_set_ct_threshold,
1627 },
da8dec29
TW		 1628};
1629
cec2d3f3 1630struct iwl_ops iwl5000_ops = {
cc0f555d 1631 .ucode = &iwl5000_ucode,
da8dec29
TW		 1632 .lib = &iwl5000_lib,
1633 .hcmd = &iwl5000_hcmd,
1634 .utils = &iwl5000_hcmd_utils,
1635};
1636
62161aef 1637static struct iwl_ops iwl5150_ops = {
cc0f555d 1638 .ucode = &iwl5000_ucode,
62161aef
WYG		 1639 .lib = &iwl5150_lib,
1640 .hcmd = &iwl5000_hcmd,
1641 .utils = &iwl5000_hcmd_utils,
62161aef
WYG		 1642};
1643
cec2d3f3 1644struct iwl_mod_params iwl50_mod_params = {
5a6a256e 1645 .num_of_queues = IWL50_NUM_QUEUES,
9f17b318 1646 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1647 .amsdu_size_8K = 1,
3a1081e8 1648 .restart_fw = 1,
5a6a256e
TW		 1649 /* the rest are 0 by default */
1650};
1651
1652
1653struct iwl_cfg iwl5300_agn_cfg = {
1654 .name = "5300AGN",
a0987a8d
RC		 1655 .fw_name_pre = IWL5000_FW_PRE,
1656 .ucode_api_max = IWL5000_UCODE_API_MAX,
1657 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1658 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1659 .ops = &iwl5000_ops,
25ae3986 1660 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1661 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1662 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
5a6a256e 1663 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1664 .valid_tx_ant = ANT_ABC,
1665 .valid_rx_ant = ANT_ABC,
050681b7 1666 .need_pll_cfg = true,
b261793d 1667 .ht_greenfield_support = true,
5a6a256e
TW		 1668};
1669
47408639
EK		 1670struct iwl_cfg iwl5100_bg_cfg = {
1671 .name = "5100BG",
a0987a8d
RC		 1672 .fw_name_pre = IWL5000_FW_PRE,
1673 .ucode_api_max = IWL5000_UCODE_API_MAX,
1674 .ucode_api_min = IWL5000_UCODE_API_MIN,
47408639
EK		 1675 .sku = IWL_SKU_G,
1676 .ops = &iwl5000_ops,
1677 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1678 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1679 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
47408639 1680 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1681 .valid_tx_ant = ANT_B,
1682 .valid_rx_ant = ANT_AB,
050681b7 1683 .need_pll_cfg = true,
b261793d 1684 .ht_greenfield_support = true,
47408639
EK		 1685};
1686
1687struct iwl_cfg iwl5100_abg_cfg = {
1688 .name = "5100ABG",
a0987a8d
RC		 1689 .fw_name_pre = IWL5000_FW_PRE,
1690 .ucode_api_max = IWL5000_UCODE_API_MAX,
1691 .ucode_api_min = IWL5000_UCODE_API_MIN,
47408639
EK		 1692 .sku = IWL_SKU_A|IWL_SKU_G,
1693 .ops = &iwl5000_ops,
1694 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1695 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1696 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
47408639 1697 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1698 .valid_tx_ant = ANT_B,
1699 .valid_rx_ant = ANT_AB,
050681b7 1700 .need_pll_cfg = true,
b261793d 1701 .ht_greenfield_support = true,
47408639
EK		 1702};
1703
5a6a256e
TW		 1704struct iwl_cfg iwl5100_agn_cfg = {
1705 .name = "5100AGN",
a0987a8d
RC		 1706 .fw_name_pre = IWL5000_FW_PRE,
1707 .ucode_api_max = IWL5000_UCODE_API_MAX,
1708 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1709 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1710 .ops = &iwl5000_ops,
25ae3986 1711 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1712 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1713 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
5a6a256e 1714 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1715 .valid_tx_ant = ANT_B,
1716 .valid_rx_ant = ANT_AB,
050681b7 1717 .need_pll_cfg = true,
b261793d 1718 .ht_greenfield_support = true,
5a6a256e
TW		 1719};
1720
1721struct iwl_cfg iwl5350_agn_cfg = {
1722 .name = "5350AGN",
a0987a8d
RC		 1723 .fw_name_pre = IWL5000_FW_PRE,
1724 .ucode_api_max = IWL5000_UCODE_API_MAX,
1725 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1726 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1727 .ops = &iwl5000_ops,
25ae3986 1728 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1729 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1730 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
5a6a256e 1731 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1732 .valid_tx_ant = ANT_ABC,
1733 .valid_rx_ant = ANT_ABC,
050681b7 1734 .need_pll_cfg = true,
b261793d 1735 .ht_greenfield_support = true,
5a6a256e
TW		 1736};
1737
7100e924
TW		 1738struct iwl_cfg iwl5150_agn_cfg = {
1739 .name = "5150AGN",
a0987a8d
RC		 1740 .fw_name_pre = IWL5150_FW_PRE,
1741 .ucode_api_max = IWL5150_UCODE_API_MAX,
1742 .ucode_api_min = IWL5150_UCODE_API_MIN,
7100e924 1743 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
62161aef 1744 .ops = &iwl5150_ops,
7100e924 1745 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
fd63edba
TW		 1746 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1747 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
7100e924 1748 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1749 .valid_tx_ant = ANT_A,
1750 .valid_rx_ant = ANT_AB,
050681b7 1751 .need_pll_cfg = true,
b261793d 1752 .ht_greenfield_support = true,
7100e924
TW		 1753};
1754
a0987a8d
RC		 1755MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1756MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
c9f79ed2 1757
5a6a256e
TW		 1758module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1759MODULE_PARM_DESC(swcrypto50,
1760 "using software crypto engine (default 0 [hardware])\n");
5a6a256e
TW		 1761module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1762MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
49779293
RR		 1763module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1764MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
5a6a256e
TW		 1765module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1766MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
3a1081e8
EK		 1767module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1768MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
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