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ath9k: Replace ath9k_opmode with nl80211_iftype
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
5a6a256e
TW		 28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/skbuff.h>
33#include <linux/netdevice.h>
34#include <linux/wireless.h>
35#include <net/mac80211.h>
36#include <linux/etherdevice.h>
37#include <asm/unaligned.h>
38
39#include "iwl-eeprom.h"
3e0d4cb1 40#include "iwl-dev.h"
5a6a256e
TW		 41#include "iwl-core.h"
42#include "iwl-io.h"
e26e47d9 43#include "iwl-sta.h"
5a6a256e
TW		 44#include "iwl-helpers.h"
45#include "iwl-5000-hw.h"
46
47#define IWL5000_UCODE_API "-1"
48
4e062f99
JS		 49#define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode"
50
99da1b48
RR		 51static const u16 iwl5000_default_queue_to_tx_fifo[] = {
52 IWL_TX_FIFO_AC3,
53 IWL_TX_FIFO_AC2,
54 IWL_TX_FIFO_AC1,
55 IWL_TX_FIFO_AC0,
56 IWL50_CMD_FIFO_NUM,
57 IWL_TX_FIFO_HCCA_1,
58 IWL_TX_FIFO_HCCA_2
59};
60
46315e01
TW		 61/* FIXME: same implementation as 4965 */
62static int iwl5000_apm_stop_master(struct iwl_priv *priv)
63{
64 int ret = 0;
65 unsigned long flags;
66
67 spin_lock_irqsave(&priv->lock, flags);
68
69 /* set stop master bit */
70 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
71
72 ret = iwl_poll_bit(priv, CSR_RESET,
73 CSR_RESET_REG_FLAG_MASTER_DISABLED,
74 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
75 if (ret < 0)
76 goto out;
77
78out:
79 spin_unlock_irqrestore(&priv->lock, flags);
80 IWL_DEBUG_INFO("stop master\n");
81
82 return ret;
83}
84
85
30d59260
TW		 86static int iwl5000_apm_init(struct iwl_priv *priv)
87{
88 int ret = 0;
89
90 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
92
8f061891
TW		 93 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
94 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
95 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
96
a96a27f9 97 /* Set FH wait threshold to maximum (HW error during stress W/A) */
4c43e0d0
TW		 98 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
99
100 /* enable HAP INTA to move device L1a -> L0s */
101 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
102 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
103
30d59260
TW		 104 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
105
106 /* set "initialization complete" bit to move adapter
107 * D0U* --> D0A* state */
108 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
109
110 /* wait for clock stabilization */
111 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
113 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
114 if (ret < 0) {
115 IWL_DEBUG_INFO("Failed to init the card\n");
116 return ret;
117 }
118
119 ret = iwl_grab_nic_access(priv);
120 if (ret)
121 return ret;
122
123 /* enable DMA */
8f061891 124 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
30d59260
TW		 125
126 udelay(20);
127
8f061891 128 /* disable L1-Active */
30d59260 129 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
8f061891 130 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
30d59260
TW		 131
132 iwl_release_nic_access(priv);
133
134 return ret;
135}
136
a96a27f9 137/* FIXME: this is identical to 4965 */
f118a91d
TW		 138static void iwl5000_apm_stop(struct iwl_priv *priv)
139{
140 unsigned long flags;
141
46315e01 142 iwl5000_apm_stop_master(priv);
f118a91d
TW		 143
144 spin_lock_irqsave(&priv->lock, flags);
145
146 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
147
148 udelay(10);
149
1d3e6c61
MA		 150 /* clear "init complete" move adapter D0A* --> D0U state */
151 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d
TW		 152
153 spin_unlock_irqrestore(&priv->lock, flags);
154}
155
156
7f066108
TW		 157static int iwl5000_apm_reset(struct iwl_priv *priv)
158{
159 int ret = 0;
160 unsigned long flags;
161
46315e01 162 iwl5000_apm_stop_master(priv);
7f066108
TW		 163
164 spin_lock_irqsave(&priv->lock, flags);
165
166 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
167
168 udelay(10);
169
170
171 /* FIXME: put here L1A -L0S w/a */
172
173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
174
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
178
179 /* wait for clock stabilization */
180 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
182 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
183 if (ret < 0) {
184 IWL_DEBUG_INFO("Failed to init the card\n");
185 goto out;
186 }
187
188 ret = iwl_grab_nic_access(priv);
189 if (ret)
190 goto out;
191
192 /* enable DMA */
193 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
194
195 udelay(20);
196
197 /* disable L1-Active */
198 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
199 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
200
201 iwl_release_nic_access(priv);
202
203out:
204 spin_unlock_irqrestore(&priv->lock, flags);
205
206 return ret;
207}
208
209
5a835353 210static void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 211{
212 unsigned long flags;
213 u16 radio_cfg;
e7b63581 214 u16 link;
e86fe9f6
TW		 215
216 spin_lock_irqsave(&priv->lock, flags);
217
e7b63581 218 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
e86fe9f6 219
8f061891 220 /* L1 is enabled by BIOS */
e7b63581 221 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
a96a27f9 222 /* disable L0S disabled L1A enabled */
8f061891
TW		 223 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
224 else
225 /* L0S enabled L1A disabled */
226 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
e86fe9f6
TW		 227
228 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
229
230 /* write radio config values to register */
231 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
232 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
233 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
234 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
235 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
236
237 /* set CSR_HW_CONFIG_REG for uCode use */
238 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
239 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
240 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
241
4c43e0d0
TW		 242 /* W/A : NIC is stuck in a reset state after Early PCIe power off
243 * (PCIe power is lost before PERST# is asserted),
244 * causing ME FW to lose ownership and not being able to obtain it back.
245 */
2d3db679
TW		 246 iwl_grab_nic_access(priv);
247 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
4c43e0d0
TW		 248 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
249 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
2d3db679 250 iwl_release_nic_access(priv);
4c43e0d0 251
e86fe9f6
TW		 252 spin_unlock_irqrestore(&priv->lock, flags);
253}
254
255
256
25ae3986
TW		 257/*
258 * EEPROM
259 */
260static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
261{
262 u16 offset = 0;
263
264 if ((address & INDIRECT_ADDRESS) == 0)
265 return address;
266
267 switch (address & INDIRECT_TYPE_MSK) {
268 case INDIRECT_HOST:
269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
270 break;
271 case INDIRECT_GENERAL:
272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
273 break;
274 case INDIRECT_REGULATORY:
275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
276 break;
277 case INDIRECT_CALIBRATION:
278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
279 break;
280 case INDIRECT_PROCESS_ADJST:
281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
282 break;
283 case INDIRECT_OTHERS:
284 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
285 break;
286 default:
287 IWL_ERROR("illegal indirect type: 0x%X\n",
288 address & INDIRECT_TYPE_MSK);
289 break;
290 }
291
292 /* translate the offset from words to byte */
293 return (address & ADDRESS_MSK) + (offset << 1);
294}
295
0ef2ca67 296static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
f1f69415 297{
f1f69415
TW		 298 struct iwl_eeprom_calib_hdr {
299 u8 version;
300 u8 pa_type;
301 u16 voltage;
302 } *hdr;
303
f1f69415
TW		 304 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
305 EEPROM_5000_CALIB_ALL);
0ef2ca67 306 return hdr->version;
f1f69415
TW		 307
308}
309
33fd5033
EG		 310static void iwl5000_gain_computation(struct iwl_priv *priv,
311 u32 average_noise[NUM_RX_CHAINS],
312 u16 min_average_noise_antenna_i,
313 u32 min_average_noise)
314{
315 int i;
316 s32 delta_g;
317 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
318
319 /* Find Gain Code for the antennas B and C */
320 for (i = 1; i < NUM_RX_CHAINS; i++) {
321 if ((data->disconn_array[i])) {
322 data->delta_gain_code[i] = 0;
323 continue;
324 }
325 delta_g = (1000 * ((s32)average_noise[0] -
326 (s32)average_noise[i])) / 1500;
327 /* bound gain by 2 bits value max, 3rd bit is sign */
328 data->delta_gain_code[i] =
329 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
330
331 if (delta_g < 0)
332 /* set negative sign */
333 data->delta_gain_code[i] |= (1 << 2);
334 }
335
336 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
337 data->delta_gain_code[1], data->delta_gain_code[2]);
338
339 if (!data->radio_write) {
f69f42a6 340 struct iwl_calib_chain_noise_gain_cmd cmd;
0d950d84 341
33fd5033
EG		 342 memset(&cmd, 0, sizeof(cmd));
343
0d950d84
TW		 344 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
345 cmd.hdr.first_group = 0;
346 cmd.hdr.groups_num = 1;
347 cmd.hdr.data_valid = 1;
33fd5033
EG		 348 cmd.delta_gain_1 = data->delta_gain_code[1];
349 cmd.delta_gain_2 = data->delta_gain_code[2];
350 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
351 sizeof(cmd), &cmd, NULL);
352
353 data->radio_write = 1;
354 data->state = IWL_CHAIN_NOISE_CALIBRATED;
355 }
356
357 data->chain_noise_a = 0;
358 data->chain_noise_b = 0;
359 data->chain_noise_c = 0;
360 data->chain_signal_a = 0;
361 data->chain_signal_b = 0;
362 data->chain_signal_c = 0;
363 data->beacon_count = 0;
364}
365
366static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
367{
368 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
0d950d84 369 int ret;
33fd5033
EG		 370
371 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 372 struct iwl_calib_chain_noise_reset_cmd cmd;
33fd5033 373 memset(&cmd, 0, sizeof(cmd));
0d950d84
TW		 374
375 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
376 cmd.hdr.first_group = 0;
377 cmd.hdr.groups_num = 1;
378 cmd.hdr.data_valid = 1;
379 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
380 sizeof(cmd), &cmd);
381 if (ret)
33fd5033
EG		 382 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
383 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
384 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
385 }
386}
387
a326a5d0
EG		 388static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
389 __le32 *tx_flags)
390{
e6a9854b
JB		 391 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
392 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
a326a5d0
EG		 393 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
394 else
395 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
396}
397
33fd5033
EG		 398static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
399 .min_nrg_cck = 95,
400 .max_nrg_cck = 0,
401 .auto_corr_min_ofdm = 90,
402 .auto_corr_min_ofdm_mrc = 170,
403 .auto_corr_min_ofdm_x1 = 120,
404 .auto_corr_min_ofdm_mrc_x1 = 240,
405
406 .auto_corr_max_ofdm = 120,
407 .auto_corr_max_ofdm_mrc = 210,
408 .auto_corr_max_ofdm_x1 = 155,
409 .auto_corr_max_ofdm_mrc_x1 = 290,
410
411 .auto_corr_min_cck = 125,
412 .auto_corr_max_cck = 200,
413 .auto_corr_min_cck_mrc = 170,
414 .auto_corr_max_cck_mrc = 400,
415 .nrg_th_cck = 95,
416 .nrg_th_ofdm = 95,
417};
418
25ae3986
TW		 419static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
420 size_t offset)
421{
422 u32 address = eeprom_indirect_address(priv, offset);
423 BUG_ON(address >= priv->cfg->eeprom_size);
424 return &priv->eeprom[address];
425}
426
7c616cba
TW		 427/*
428 * Calibration
429 */
be5d56ed 430static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
7c616cba 431{
0d950d84 432 struct iwl_calib_xtal_freq_cmd cmd;
7c616cba
TW		 433 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
434
0d950d84
TW		 435 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
436 cmd.hdr.first_group = 0;
437 cmd.hdr.groups_num = 1;
438 cmd.hdr.data_valid = 1;
439 cmd.cap_pin1 = (u8)xtal_calib[0];
440 cmd.cap_pin2 = (u8)xtal_calib[1];
f69f42a6 441 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
0d950d84 442 (u8 *)&cmd, sizeof(cmd));
7c616cba
TW		 443}
444
7c616cba
TW		 445static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
446{
f69f42a6 447 struct iwl_calib_cfg_cmd calib_cfg_cmd;
7c616cba
TW		 448 struct iwl_host_cmd cmd = {
449 .id = CALIBRATION_CFG_CMD,
f69f42a6 450 .len = sizeof(struct iwl_calib_cfg_cmd),
7c616cba
TW		 451 .data = &calib_cfg_cmd,
452 };
453
454 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
455 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
456 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
457 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
458 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
459
460 return iwl_send_cmd(priv, &cmd);
461}
462
463static void iwl5000_rx_calib_result(struct iwl_priv *priv,
464 struct iwl_rx_mem_buffer *rxb)
465{
466 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
f69f42a6 467 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
7c616cba 468 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
6e21f2c1 469 int index;
7c616cba
TW		 470
471 /* reduce the size of the length field itself */
472 len -= 4;
473
6e21f2c1
TW		 474 /* Define the order in which the results will be sent to the runtime
475 * uCode. iwl_send_calib_results sends them in a row according to their
476 * index. We sort them here */
7c616cba 477 switch (hdr->op_code) {
f69f42a6
TW		 478 case IWL_PHY_CALIBRATE_LO_CMD:
479 index = IWL_CALIB_LO;
7c616cba 480 break;
f69f42a6
TW		 481 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
482 index = IWL_CALIB_TX_IQ;
7c616cba 483 break;
f69f42a6
TW		 484 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
485 index = IWL_CALIB_TX_IQ_PERD;
7c616cba 486 break;
201706ac
TW		 487 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
488 index = IWL_CALIB_BASE_BAND;
489 break;
7c616cba
TW		 490 default:
491 IWL_ERROR("Unknown calibration notification %d\n",
492 hdr->op_code);
493 return;
494 }
6e21f2c1 495 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
7c616cba
TW		 496}
497
498static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
499 struct iwl_rx_mem_buffer *rxb)
500{
501 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
502 queue_work(priv->workqueue, &priv->restart);
503}
504
dbb983b7
RR		 505/*
506 * ucode
507 */
508static int iwl5000_load_section(struct iwl_priv *priv,
509 struct fw_desc *image,
510 u32 dst_addr)
511{
512 int ret = 0;
513 unsigned long flags;
514
515 dma_addr_t phy_addr = image->p_addr;
516 u32 byte_cnt = image->len;
517
518 spin_lock_irqsave(&priv->lock, flags);
519 ret = iwl_grab_nic_access(priv);
520 if (ret) {
521 spin_unlock_irqrestore(&priv->lock, flags);
522 return ret;
523 }
524
525 iwl_write_direct32(priv,
526 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
527 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
528
529 iwl_write_direct32(priv,
530 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
531
532 iwl_write_direct32(priv,
533 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
534 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
535
dbb983b7 536 iwl_write_direct32(priv,
f0b9f5cb 537 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
499b1883 538 (iwl_get_dma_hi_addr(phy_addr)
f0b9f5cb
TW		 539 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
540
dbb983b7
RR		 541 iwl_write_direct32(priv,
542 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
543 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
544 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
545 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
546
547 iwl_write_direct32(priv,
548 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
549 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
9c80c502 550 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
dbb983b7
RR		 551 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
552
553 iwl_release_nic_access(priv);
554 spin_unlock_irqrestore(&priv->lock, flags);
555 return 0;
556}
557
558static int iwl5000_load_given_ucode(struct iwl_priv *priv,
559 struct fw_desc *inst_image,
560 struct fw_desc *data_image)
561{
562 int ret = 0;
563
9c80c502 564 ret = iwl5000_load_section(priv, inst_image, RTC_INST_LOWER_BOUND);
dbb983b7
RR		 565 if (ret)
566 return ret;
567
568 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
569 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
9c80c502 570 priv->ucode_write_complete, 5 * HZ);
dbb983b7
RR		 571 if (ret == -ERESTARTSYS) {
572 IWL_ERROR("Could not load the INST uCode section due "
573 "to interrupt\n");
574 return ret;
575 }
576 if (!ret) {
577 IWL_ERROR("Could not load the INST uCode section\n");
578 return -ETIMEDOUT;
579 }
580
581 priv->ucode_write_complete = 0;
582
583 ret = iwl5000_load_section(
584 priv, data_image, RTC_DATA_LOWER_BOUND);
585 if (ret)
586 return ret;
587
588 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
589
590 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
591 priv->ucode_write_complete, 5 * HZ);
592 if (ret == -ERESTARTSYS) {
593 IWL_ERROR("Could not load the INST uCode section due "
594 "to interrupt\n");
595 return ret;
596 } else if (!ret) {
597 IWL_ERROR("Could not load the DATA uCode section\n");
598 return -ETIMEDOUT;
599 } else
600 ret = 0;
601
602 priv->ucode_write_complete = 0;
603
604 return ret;
605}
606
607static int iwl5000_load_ucode(struct iwl_priv *priv)
608{
609 int ret = 0;
610
611 /* check whether init ucode should be loaded, or rather runtime ucode */
612 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
613 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
614 ret = iwl5000_load_given_ucode(priv,
615 &priv->ucode_init, &priv->ucode_init_data);
616 if (!ret) {
617 IWL_DEBUG_INFO("Init ucode load complete.\n");
618 priv->ucode_type = UCODE_INIT;
619 }
620 } else {
621 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
622 "Loading runtime ucode...\n");
623 ret = iwl5000_load_given_ucode(priv,
624 &priv->ucode_code, &priv->ucode_data);
625 if (!ret) {
626 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
627 priv->ucode_type = UCODE_RT;
628 }
629 }
630
631 return ret;
632}
633
99da1b48
RR		 634static void iwl5000_init_alive_start(struct iwl_priv *priv)
635{
636 int ret = 0;
637
638 /* Check alive response for "valid" sign from uCode */
639 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
640 /* We had an error bringing up the hardware, so take it
641 * all the way back down so we can try again */
642 IWL_DEBUG_INFO("Initialize Alive failed.\n");
643 goto restart;
644 }
645
646 /* initialize uCode was loaded... verify inst image.
647 * This is a paranoid check, because we would not have gotten the
648 * "initialize" alive if code weren't properly loaded. */
649 if (iwl_verify_ucode(priv)) {
650 /* Runtime instruction load was bad;
651 * take it all the way back down so we can try again */
652 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
653 goto restart;
654 }
655
37deb2a0 656 iwl_clear_stations_table(priv);
99da1b48
RR		 657 ret = priv->cfg->ops->lib->alive_notify(priv);
658 if (ret) {
659 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
660 goto restart;
661 }
662
7c616cba 663 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 664 return;
665
666restart:
667 /* real restart (first load init_ucode) */
668 queue_work(priv->workqueue, &priv->restart);
669}
670
671static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
672 int txq_id, u32 index)
673{
674 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
675 (index & 0xff) | (txq_id << 8));
676 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
677}
678
679static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
680 struct iwl_tx_queue *txq,
681 int tx_fifo_id, int scd_retry)
682{
683 int txq_id = txq->q.id;
3fd07a1e 684 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
99da1b48
RR		 685
686 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
687 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
688 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
689 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
690 IWL50_SCD_QUEUE_STTS_REG_MSK);
691
692 txq->sched_retry = scd_retry;
693
694 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
695 active ? "Activate" : "Deactivate",
696 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
697}
698
9636e583
RR		 699static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
700{
701 struct iwl_wimax_coex_cmd coex_cmd;
702
703 memset(&coex_cmd, 0, sizeof(coex_cmd));
704
705 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
706 sizeof(coex_cmd), &coex_cmd);
707}
708
99da1b48
RR		 709static int iwl5000_alive_notify(struct iwl_priv *priv)
710{
711 u32 a;
99da1b48
RR		 712 unsigned long flags;
713 int ret;
31a73fe4 714 int i, chan;
40fc95d5 715 u32 reg_val;
99da1b48
RR		 716
717 spin_lock_irqsave(&priv->lock, flags);
718
719 ret = iwl_grab_nic_access(priv);
720 if (ret) {
721 spin_unlock_irqrestore(&priv->lock, flags);
722 return ret;
723 }
724
725 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
726 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
727 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
728 a += 4)
729 iwl_write_targ_mem(priv, a, 0);
730 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
731 a += 4)
732 iwl_write_targ_mem(priv, a, 0);
733 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
734 iwl_write_targ_mem(priv, a, 0);
735
736 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
4ddbb7d0 737 priv->scd_bc_tbls.dma >> 10);
31a73fe4
WT		 738
739 /* Enable DMA channel */
740 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
741 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
742 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
743 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
744
40fc95d5
WT		 745 /* Update FH chicken bits */
746 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
747 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
748 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
749
99da1b48 750 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
4ddbb7d0 751 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
99da1b48
RR		 752 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
753
754 /* initiate the queues */
755 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
756 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
757 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
758 iwl_write_targ_mem(priv, priv->scd_base_addr +
759 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
760 iwl_write_targ_mem(priv, priv->scd_base_addr +
761 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
762 sizeof(u32),
763 ((SCD_WIN_SIZE <<
764 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
765 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
766 ((SCD_FRAME_LIMIT <<
767 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
768 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
769 }
770
771 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 772 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 773
da1bc453
TW		 774 /* Activate all Tx DMA/FIFO channels */
775 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 776
777 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
9c80c502 778
99da1b48
RR		 779 /* map qos queues to fifos one-to-one */
780 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
781 int ac = iwl5000_default_queue_to_tx_fifo[i];
782 iwl_txq_ctx_activate(priv, i);
783 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
784 }
785 /* TODO - need to initialize those FIFOs inside the loop above,
786 * not only mark them as active */
787 iwl_txq_ctx_activate(priv, 4);
788 iwl_txq_ctx_activate(priv, 7);
789 iwl_txq_ctx_activate(priv, 8);
790 iwl_txq_ctx_activate(priv, 9);
791
792 iwl_release_nic_access(priv);
793 spin_unlock_irqrestore(&priv->lock, flags);
794
7c616cba 795
9636e583
RR		 796 iwl5000_send_wimax_coex(priv);
797
be5d56ed
TW		 798 iwl5000_set_Xtal_calib(priv);
799 iwl_send_calib_results(priv);
7c616cba 800
99da1b48
RR		 801 return 0;
802}
803
fdd3e8a4
TW		 804static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
805{
806 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
807 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
808 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
809 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
810 return -EINVAL;
811 }
25ae3986 812
fdd3e8a4 813 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
4ddbb7d0
TW		 814 priv->hw_params.scd_bc_tbls_size =
815 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
fdd3e8a4
TW		 816 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
817 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
818 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
819 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
da154e30 820 priv->hw_params.max_bsm_size = 0;
fdd3e8a4
TW		 821 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
822 BIT(IEEE80211_BAND_5GHZ);
33fd5033 823 priv->hw_params.sens = &iwl5000_sensitivity;
fdd3e8a4
TW		 824
825 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
826 case CSR_HW_REV_TYPE_5100:
5d664a41
TW		 827 priv->hw_params.tx_chains_num = 1;
828 priv->hw_params.rx_chains_num = 2;
829 priv->hw_params.valid_tx_ant = ANT_B;
830 priv->hw_params.valid_rx_ant = ANT_AB;
831 break;
fdd3e8a4
TW		 832 case CSR_HW_REV_TYPE_5150:
833 priv->hw_params.tx_chains_num = 1;
834 priv->hw_params.rx_chains_num = 2;
1179f18d
TW		 835 priv->hw_params.valid_tx_ant = ANT_A;
836 priv->hw_params.valid_rx_ant = ANT_AB;
fdd3e8a4
TW		 837 break;
838 case CSR_HW_REV_TYPE_5300:
839 case CSR_HW_REV_TYPE_5350:
840 priv->hw_params.tx_chains_num = 3;
841 priv->hw_params.rx_chains_num = 3;
1179f18d
TW		 842 priv->hw_params.valid_tx_ant = ANT_ABC;
843 priv->hw_params.valid_rx_ant = ANT_ABC;
fdd3e8a4
TW		 844 break;
845 }
c031bf80
EG		 846
847 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
848 case CSR_HW_REV_TYPE_5100:
849 case CSR_HW_REV_TYPE_5300:
d5d7c584
TW		 850 case CSR_HW_REV_TYPE_5350:
851 /* 5X00 and 5350 wants in Celsius */
c031bf80
EG		 852 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
853 break;
854 case CSR_HW_REV_TYPE_5150:
d5d7c584 855 /* 5150 wants in Kelvin */
c031bf80
EG		 856 priv->hw_params.ct_kill_threshold =
857 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
858 break;
859 }
860
be5d56ed
TW		 861 /* Set initial calibration set */
862 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
863 case CSR_HW_REV_TYPE_5100:
864 case CSR_HW_REV_TYPE_5300:
865 case CSR_HW_REV_TYPE_5350:
866 priv->hw_params.calib_init_cfg =
f69f42a6
TW		 867 BIT(IWL_CALIB_XTAL) |
868 BIT(IWL_CALIB_LO) |
201706ac
TW		 869 BIT(IWL_CALIB_TX_IQ) |
870 BIT(IWL_CALIB_TX_IQ_PERD) |
871 BIT(IWL_CALIB_BASE_BAND);
be5d56ed
TW		 872 break;
873 case CSR_HW_REV_TYPE_5150:
874 priv->hw_params.calib_init_cfg = 0;
875 break;
876 }
877
878
fdd3e8a4
TW		 879 return 0;
880}
d4100dd9 881
7839fc03
EG		 882/**
883 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
884 */
885static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 886 struct iwl_tx_queue *txq,
7839fc03
EG		 887 u16 byte_cnt)
888{
4ddbb7d0 889 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab 890 int write_ptr = txq->q.write_ptr;
7839fc03
EG		 891 int txq_id = txq->q.id;
892 u8 sec_ctl = 0;
127901ab
TW		 893 u8 sta_id = 0;
894 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
895 __le16 bc_ent;
7839fc03 896
127901ab 897 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
7839fc03
EG		 898
899 if (txq_id != IWL_CMD_QUEUE_NUM) {
127901ab 900 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
da99c4b6 901 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 902
903 switch (sec_ctl & TX_CMD_SEC_MSK) {
904 case TX_CMD_SEC_CCM:
905 len += CCMP_MIC_LEN;
906 break;
907 case TX_CMD_SEC_TKIP:
908 len += TKIP_ICV_LEN;
909 break;
910 case TX_CMD_SEC_WEP:
911 len += WEP_IV_LEN + WEP_ICV_LEN;
912 break;
913 }
914 }
915
127901ab 916 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
7839fc03 917
4ddbb7d0 918 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
7839fc03 919
127901ab 920 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 921 scd_bc_tbl[txq_id].
127901ab 922 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
7839fc03
EG		 923}
924
972cf447
TW		 925static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
926 struct iwl_tx_queue *txq)
927{
4ddbb7d0 928 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 929 int txq_id = txq->q.id;
930 int read_ptr = txq->q.read_ptr;
931 u8 sta_id = 0;
932 __le16 bc_ent;
933
934 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
972cf447
TW		 935
936 if (txq_id != IWL_CMD_QUEUE_NUM)
127901ab 937 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
972cf447 938
127901ab 939 bc_ent = cpu_to_le16(1 | (sta_id << 12));
4ddbb7d0 940 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
972cf447 941
127901ab 942 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 943 scd_bc_tbl[txq_id].
127901ab 944 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
972cf447
TW		 945}
946
e26e47d9
TW		 947static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
948 u16 txq_id)
949{
950 u32 tbl_dw_addr;
951 u32 tbl_dw;
952 u16 scd_q2ratid;
953
954 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
955
956 tbl_dw_addr = priv->scd_base_addr +
957 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
958
959 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
960
961 if (txq_id & 0x1)
962 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
963 else
964 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
965
966 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
967
968 return 0;
969}
970static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
971{
972 /* Simply stop the queue, but don't change any configuration;
973 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
974 iwl_write_prph(priv,
975 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
976 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
977 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
978}
979
980static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
981 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
982{
983 unsigned long flags;
984 int ret;
985 u16 ra_tid;
986
9f17b318
TW		 987 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
988 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
989 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
990 txq_id, IWL50_FIRST_AMPDU_QUEUE,
991 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
992 return -EINVAL;
993 }
e26e47d9
TW		 994
995 ra_tid = BUILD_RAxTID(sta_id, tid);
996
997 /* Modify device's station table to Tx this TID */
9f58671e 998 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
e26e47d9
TW		 999
1000 spin_lock_irqsave(&priv->lock, flags);
1001 ret = iwl_grab_nic_access(priv);
1002 if (ret) {
1003 spin_unlock_irqrestore(&priv->lock, flags);
1004 return ret;
1005 }
1006
1007 /* Stop this Tx queue before configuring it */
1008 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1009
1010 /* Map receiver-address / traffic-ID to this queue */
1011 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1012
1013 /* Set this queue as a chain-building queue */
1014 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1015
1016 /* enable aggregations for the queue */
1017 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1018
1019 /* Place first TFD at index corresponding to start sequence number.
1020 * Assumes that ssn_idx is valid (!= 0xFFF) */
1021 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1022 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1023 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1024
1025 /* Set up Tx window size and frame limit for this queue */
1026 iwl_write_targ_mem(priv, priv->scd_base_addr +
1027 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1028 sizeof(u32),
1029 ((SCD_WIN_SIZE <<
1030 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1031 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1032 ((SCD_FRAME_LIMIT <<
1033 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1034 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1035
1036 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1037
1038 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1039 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1040
1041 iwl_release_nic_access(priv);
1042 spin_unlock_irqrestore(&priv->lock, flags);
1043
1044 return 0;
1045}
1046
1047static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1048 u16 ssn_idx, u8 tx_fifo)
1049{
1050 int ret;
1051
9f17b318
TW		 1052 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1053 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1054 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1055 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1056 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
e26e47d9
TW		 1057 return -EINVAL;
1058 }
1059
1060 ret = iwl_grab_nic_access(priv);
1061 if (ret)
1062 return ret;
1063
1064 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1065
1066 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1067
1068 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1069 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1070 /* supposes that ssn_idx is valid (!= 0xFFF) */
1071 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1072
1073 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1074 iwl_txq_ctx_deactivate(priv, txq_id);
1075 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1076
1077 iwl_release_nic_access(priv);
1078
1079 return 0;
1080}
1081
2469bf2e
TW		 1082static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1083{
1084 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1085 memcpy(data, cmd, size);
1086 return size;
1087}
1088
1089
da1bc453 1090/*
a96a27f9 1091 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 1092 * must be called under priv->lock and mac access
1093 */
1094static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 1095{
da1bc453 1096 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 1097}
1098
e532fa0e
RR		 1099
1100static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1101{
3ac7f146 1102 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 1103 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 1104}
1105
1106static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1107 struct iwl_ht_agg *agg,
1108 struct iwl5000_tx_resp *tx_resp,
25a6572c 1109 int txq_id, u16 start_idx)
e532fa0e
RR		 1110{
1111 u16 status;
1112 struct agg_tx_status *frame_status = &tx_resp->status;
1113 struct ieee80211_tx_info *info = NULL;
1114 struct ieee80211_hdr *hdr = NULL;
e7d326ac 1115 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 1116 int i, sh, idx;
e532fa0e
RR		 1117 u16 seq;
1118
1119 if (agg->wait_for_ba)
1120 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1121
1122 agg->frame_count = tx_resp->frame_count;
1123 agg->start_idx = start_idx;
e7d326ac 1124 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 1125 agg->bitmap = 0;
1126
1127 /* # frames attempted by Tx command */
1128 if (agg->frame_count == 1) {
1129 /* Only one frame was attempted; no block-ack will arrive */
1130 status = le16_to_cpu(frame_status[0].status);
25a6572c 1131 idx = start_idx;
e532fa0e
RR		 1132
1133 /* FIXME: code repetition */
1134 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1135 agg->frame_count, agg->start_idx, idx);
1136
1137 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 1138 info->status.rates[0].count = tx_resp->failure_frame + 1;
e532fa0e 1139 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c3056065 1140 info->flags |= iwl_is_tx_success(status) ?
3fd07a1e 1141 IEEE80211_TX_STAT_ACK : 0;
e7d326ac
TW		 1142 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1143
e532fa0e
RR		 1144 /* FIXME: code repetition end */
1145
1146 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1147 status & 0xff, tx_resp->failure_frame);
e7d326ac 1148 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1149
1150 agg->wait_for_ba = 0;
1151 } else {
1152 /* Two or more frames were attempted; expect block-ack */
1153 u64 bitmap = 0;
1154 int start = agg->start_idx;
1155
1156 /* Construct bit-map of pending frames within Tx window */
1157 for (i = 0; i < agg->frame_count; i++) {
1158 u16 sc;
1159 status = le16_to_cpu(frame_status[i].status);
1160 seq = le16_to_cpu(frame_status[i].sequence);
1161 idx = SEQ_TO_INDEX(seq);
1162 txq_id = SEQ_TO_QUEUE(seq);
1163
1164 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1165 AGG_TX_STATE_ABORT_MSK))
1166 continue;
1167
1168 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1169 agg->frame_count, txq_id, idx);
1170
1171 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1172
1173 sc = le16_to_cpu(hdr->seq_ctrl);
1174 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1175 IWL_ERROR("BUG_ON idx doesn't match seq control"
1176 " idx=%d, seq_idx=%d, seq=%d\n",
1177 idx, SEQ_TO_SN(sc),
1178 hdr->seq_ctrl);
1179 return -1;
1180 }
1181
1182 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1183 i, idx, SEQ_TO_SN(sc));
1184
1185 sh = idx - start;
1186 if (sh > 64) {
1187 sh = (start - idx) + 0xff;
1188 bitmap = bitmap << sh;
1189 sh = 0;
1190 start = idx;
1191 } else if (sh < -64)
1192 sh = 0xff - (start - idx);
1193 else if (sh < 0) {
1194 sh = start - idx;
1195 start = idx;
1196 bitmap = bitmap << sh;
1197 sh = 0;
1198 }
4aa41f12
EG		 1199 bitmap |= 1ULL << sh;
1200 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1201 start, (unsigned long long)bitmap);
e532fa0e
RR		 1202 }
1203
1204 agg->bitmap = bitmap;
1205 agg->start_idx = start;
e532fa0e
RR		 1206 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1207 agg->frame_count, agg->start_idx,
1208 (unsigned long long)agg->bitmap);
1209
1210 if (bitmap)
1211 agg->wait_for_ba = 1;
1212 }
1213 return 0;
1214}
1215
1216static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1217 struct iwl_rx_mem_buffer *rxb)
1218{
1219 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1220 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1221 int txq_id = SEQ_TO_QUEUE(sequence);
1222 int index = SEQ_TO_INDEX(sequence);
1223 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1224 struct ieee80211_tx_info *info;
1225 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1226 u32 status = le16_to_cpu(tx_resp->status.status);
3fd07a1e
TW		 1227 int tid;
1228 int sta_id;
1229 int freed;
e532fa0e
RR		 1230
1231 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1232 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1233 "is out of range [0-%d] %d %d\n", txq_id,
1234 index, txq->q.n_bd, txq->q.write_ptr,
1235 txq->q.read_ptr);
1236 return;
1237 }
1238
1239 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1240 memset(&info->status, 0, sizeof(info->status));
1241
3fd07a1e
TW		 1242 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1243 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
e532fa0e
RR		 1244
1245 if (txq->sched_retry) {
1246 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1247 struct iwl_ht_agg *agg = NULL;
1248
e532fa0e
RR		 1249 agg = &priv->stations[sta_id].tid[tid].agg;
1250
25a6572c 1251 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1252
3235427e
RR		 1253 /* check if BAR is needed */
1254 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1255 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1256
1257 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
e532fa0e 1258 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
3fd07a1e
TW		 1259 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1260 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1261 scd_ssn , index, txq_id, txq->swq_id);
1262
17b88929 1263 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1264 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1265
3fd07a1e
TW		 1266 if (priv->mac80211_registered &&
1267 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1268 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
e532fa0e
RR		 1269 if (agg->state == IWL_AGG_OFF)
1270 ieee80211_wake_queue(priv->hw, txq_id);
1271 else
3fd07a1e
TW		 1272 ieee80211_wake_queue(priv->hw,
1273 txq->swq_id);
e532fa0e 1274 }
e532fa0e
RR		 1275 }
1276 } else {
3fd07a1e
TW		 1277 BUG_ON(txq_id != txq->swq_id);
1278
e6a9854b 1279 info->status.rates[0].count = tx_resp->failure_frame + 1;
3fd07a1e
TW		 1280 info->flags |= iwl_is_tx_success(status) ?
1281 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 1282 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1283 le32_to_cpu(tx_resp->rate_n_flags),
1284 info);
1285
3fd07a1e
TW		 1286 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1287 "0x%x retries %d\n",
1288 txq_id,
1289 iwl_get_tx_fail_reason(status), status,
1290 le32_to_cpu(tx_resp->rate_n_flags),
1291 tx_resp->failure_frame);
4f85f5b3 1292
3fd07a1e
TW		 1293 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1294 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
e532fa0e 1295 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 1296
1297 if (priv->mac80211_registered &&
1298 (iwl_queue_space(&txq->q) > txq->q.low_mark))
e532fa0e 1299 ieee80211_wake_queue(priv->hw, txq_id);
e532fa0e 1300 }
e532fa0e 1301
3fd07a1e
TW		 1302 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1303 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1304
e532fa0e
RR		 1305 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1306 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1307}
1308
a96a27f9 1309/* Currently 5000 is the superset of everything */
c1adf9fb
GG		 1310static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1311{
1312 return len;
1313}
1314
203566f3
EG		 1315static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1316{
1317 /* in 5000 the tx power calibration is done in uCode */
1318 priv->disable_tx_power_cal = 1;
1319}
1320
b600e4e1
RR		 1321static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1322{
7c616cba
TW		 1323 /* init calibration handlers */
1324 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1325 iwl5000_rx_calib_result;
1326 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1327 iwl5000_rx_calib_complete;
e532fa0e 1328 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1329}
1330
7c616cba 1331
87283cc1
RR		 1332static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1333{
1334 return (addr >= RTC_DATA_LOWER_BOUND) &&
1335 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1336}
1337
fe7a90c2
RR		 1338static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1339{
1340 int ret = 0;
1341 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1342 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1343 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1344
1345 if ((rxon1->flags == rxon2->flags) &&
1346 (rxon1->filter_flags == rxon2->filter_flags) &&
1347 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1348 (rxon1->ofdm_ht_single_stream_basic_rates ==
1349 rxon2->ofdm_ht_single_stream_basic_rates) &&
1350 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1351 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1352 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1353 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1354 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1355 (rxon1->rx_chain == rxon2->rx_chain) &&
1356 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1357 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1358 return 0;
1359 }
1360
1361 rxon_assoc.flags = priv->staging_rxon.flags;
1362 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1363 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1364 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1365 rxon_assoc.reserved1 = 0;
1366 rxon_assoc.reserved2 = 0;
1367 rxon_assoc.reserved3 = 0;
1368 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1369 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1370 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1371 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1372 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1373 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1374 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1375 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1376
1377 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1378 sizeof(rxon_assoc), &rxon_assoc, NULL);
1379 if (ret)
1380 return ret;
1381
1382 return ret;
1383}
630fe9b6
TW		 1384static int iwl5000_send_tx_power(struct iwl_priv *priv)
1385{
1386 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1387
1388 /* half dBm need to multiply */
1389 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
853554ac 1390 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6
TW		 1391 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1392 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1393 sizeof(tx_power_cmd), &tx_power_cmd,
1394 NULL);
1395}
1396
5225640b 1397static void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1398{
1399 /* store temperature from statistics (in Celsius) */
5225640b 1400 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
8f91aecb 1401}
fe7a90c2 1402
caab8f1a
TW		 1403/* Calc max signal level (dBm) among 3 possible receivers */
1404static int iwl5000_calc_rssi(struct iwl_priv *priv,
1405 struct iwl_rx_phy_res *rx_resp)
1406{
1407 /* data from PHY/DSP regarding signal strength, etc.,
1408 * contents are always there, not configurable by host
1409 */
1410 struct iwl5000_non_cfg_phy *ncphy =
1411 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1412 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1413 u8 agc;
1414
1415 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1416 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1417
1418 /* Find max rssi among 3 possible receivers.
1419 * These values are measured by the digital signal processor (DSP).
1420 * They should stay fairly constant even as the signal strength varies,
1421 * if the radio's automatic gain control (AGC) is working right.
1422 * AGC value (see below) will provide the "interesting" info.
1423 */
1424 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1425 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1426 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1427 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1428 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1429
1430 max_rssi = max_t(u32, rssi_a, rssi_b);
1431 max_rssi = max_t(u32, max_rssi, rssi_c);
1432
1433 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1434 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1435
1436 /* dBm = max_rssi dB - agc dB - constant.
1437 * Higher AGC (higher radio gain) means lower signal. */
1438 return max_rssi - agc - IWL_RSSI_OFFSET;
1439}
1440
da8dec29 1441static struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1442 .rxon_assoc = iwl5000_send_rxon_assoc,
da8dec29
TW		 1443};
1444
1445static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1446 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1447 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1448 .gain_computation = iwl5000_gain_computation,
1449 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1450 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1451 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1452};
1453
1454static struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1455 .set_hw_params = iwl5000_hw_set_hw_params,
7839fc03 1456 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1457 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1458 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1459 .txq_agg_enable = iwl5000_txq_agg_enable,
1460 .txq_agg_disable = iwl5000_txq_agg_disable,
b600e4e1 1461 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1462 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1463 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
dbb983b7 1464 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1465 .init_alive_start = iwl5000_init_alive_start,
1466 .alive_notify = iwl5000_alive_notify,
630fe9b6 1467 .send_tx_power = iwl5000_send_tx_power,
8f91aecb 1468 .temperature = iwl5000_temperature,
5b9f8cd3 1469 .update_chain_flags = iwl_update_chain_flags,
30d59260
TW		 1470 .apm_ops = {
1471 .init = iwl5000_apm_init,
7f066108 1472 .reset = iwl5000_apm_reset,
f118a91d 1473 .stop = iwl5000_apm_stop,
5a835353 1474 .config = iwl5000_nic_config,
5b9f8cd3 1475 .set_pwr_src = iwl_set_pwr_src,
30d59260 1476 },
da8dec29 1477 .eeprom_ops = {
25ae3986
TW		 1478 .regulatory_bands = {
1479 EEPROM_5000_REG_BAND_1_CHANNELS,
1480 EEPROM_5000_REG_BAND_2_CHANNELS,
1481 EEPROM_5000_REG_BAND_3_CHANNELS,
1482 EEPROM_5000_REG_BAND_4_CHANNELS,
1483 EEPROM_5000_REG_BAND_5_CHANNELS,
1484 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1485 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1486 },
da8dec29
TW		 1487 .verify_signature = iwlcore_eeprom_verify_signature,
1488 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1489 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 1490 .calib_version = iwl5000_eeprom_calib_version,
25ae3986 1491 .query_addr = iwl5000_eeprom_query_addr,
da8dec29
TW		 1492 },
1493};
1494
1495static struct iwl_ops iwl5000_ops = {
1496 .lib = &iwl5000_lib,
1497 .hcmd = &iwl5000_hcmd,
1498 .utils = &iwl5000_hcmd_utils,
1499};
1500
5a6a256e
TW		 1501static struct iwl_mod_params iwl50_mod_params = {
1502 .num_of_queues = IWL50_NUM_QUEUES,
9f17b318 1503 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e
TW		 1504 .enable_qos = 1,
1505 .amsdu_size_8K = 1,
3a1081e8 1506 .restart_fw = 1,
5a6a256e
TW		 1507 /* the rest are 0 by default */
1508};
1509
1510
1511struct iwl_cfg iwl5300_agn_cfg = {
1512 .name = "5300AGN",
4e062f99 1513 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1514 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1515 .ops = &iwl5000_ops,
25ae3986 1516 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1517 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1518 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
5a6a256e
TW		 1519 .mod_params = &iwl50_mod_params,
1520};
1521
47408639
EK		 1522struct iwl_cfg iwl5100_bg_cfg = {
1523 .name = "5100BG",
4e062f99 1524 .fw_name = IWL5000_MODULE_FIRMWARE,
47408639
EK		 1525 .sku = IWL_SKU_G,
1526 .ops = &iwl5000_ops,
1527 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1528 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1529 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
47408639
EK		 1530 .mod_params = &iwl50_mod_params,
1531};
1532
1533struct iwl_cfg iwl5100_abg_cfg = {
1534 .name = "5100ABG",
4e062f99 1535 .fw_name = IWL5000_MODULE_FIRMWARE,
47408639
EK		 1536 .sku = IWL_SKU_A|IWL_SKU_G,
1537 .ops = &iwl5000_ops,
1538 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1539 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1540 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
47408639
EK		 1541 .mod_params = &iwl50_mod_params,
1542};
1543
5a6a256e
TW		 1544struct iwl_cfg iwl5100_agn_cfg = {
1545 .name = "5100AGN",
4e062f99 1546 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1547 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1548 .ops = &iwl5000_ops,
25ae3986 1549 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1550 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1551 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
5a6a256e
TW		 1552 .mod_params = &iwl50_mod_params,
1553};
1554
1555struct iwl_cfg iwl5350_agn_cfg = {
1556 .name = "5350AGN",
4e062f99 1557 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1558 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1559 .ops = &iwl5000_ops,
25ae3986 1560 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1561 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1562 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
5a6a256e
TW		 1563 .mod_params = &iwl50_mod_params,
1564};
1565
4e062f99 1566MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE);
c9f79ed2 1567
5a6a256e
TW		 1568module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1569MODULE_PARM_DESC(disable50,
1570 "manually disable the 50XX radio (default 0 [radio on])");
1571module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1572MODULE_PARM_DESC(swcrypto50,
1573 "using software crypto engine (default 0 [hardware])\n");
1574module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1575MODULE_PARM_DESC(debug50, "50XX debug output mask");
1576module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1577MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1578module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1579MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
49779293
RR		 1580module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1581MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
5a6a256e
TW		 1582module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1583MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
3a1081e8
EK		 1584module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1585MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Linux kernel - Deliverables
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