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iwlwifi: don't update TFD free counter for invalid station
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
5a6a256e
TW		 28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
32#include <linux/skbuff.h>
33#include <linux/netdevice.h>
34#include <linux/wireless.h>
35#include <net/mac80211.h>
36#include <linux/etherdevice.h>
37#include <asm/unaligned.h>
38
39#include "iwl-eeprom.h"
3e0d4cb1 40#include "iwl-dev.h"
5a6a256e
TW		 41#include "iwl-core.h"
42#include "iwl-io.h"
e26e47d9 43#include "iwl-sta.h"
5a6a256e
TW		 44#include "iwl-helpers.h"
45#include "iwl-5000-hw.h"
46
47#define IWL5000_UCODE_API "-1"
48
4e062f99
JS		 49#define IWL5000_MODULE_FIRMWARE "iwlwifi-5000" IWL5000_UCODE_API ".ucode"
50
99da1b48
RR		 51static const u16 iwl5000_default_queue_to_tx_fifo[] = {
52 IWL_TX_FIFO_AC3,
53 IWL_TX_FIFO_AC2,
54 IWL_TX_FIFO_AC1,
55 IWL_TX_FIFO_AC0,
56 IWL50_CMD_FIFO_NUM,
57 IWL_TX_FIFO_HCCA_1,
58 IWL_TX_FIFO_HCCA_2
59};
60
46315e01
TW		 61/* FIXME: same implementation as 4965 */
62static int iwl5000_apm_stop_master(struct iwl_priv *priv)
63{
64 int ret = 0;
65 unsigned long flags;
66
67 spin_lock_irqsave(&priv->lock, flags);
68
69 /* set stop master bit */
70 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
71
72 ret = iwl_poll_bit(priv, CSR_RESET,
73 CSR_RESET_REG_FLAG_MASTER_DISABLED,
74 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
75 if (ret < 0)
76 goto out;
77
78out:
79 spin_unlock_irqrestore(&priv->lock, flags);
80 IWL_DEBUG_INFO("stop master\n");
81
82 return ret;
83}
84
85
30d59260
TW		 86static int iwl5000_apm_init(struct iwl_priv *priv)
87{
88 int ret = 0;
89
90 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
92
8f061891
TW		 93 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
94 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
95 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
96
4c43e0d0
TW		 97 /* Set FH wait treshold to maximum (HW error during stress W/A) */
98 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
99
100 /* enable HAP INTA to move device L1a -> L0s */
101 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
102 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
103
30d59260
TW		 104 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
105
106 /* set "initialization complete" bit to move adapter
107 * D0U* --> D0A* state */
108 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
109
110 /* wait for clock stabilization */
111 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
112 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
113 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
114 if (ret < 0) {
115 IWL_DEBUG_INFO("Failed to init the card\n");
116 return ret;
117 }
118
119 ret = iwl_grab_nic_access(priv);
120 if (ret)
121 return ret;
122
123 /* enable DMA */
8f061891 124 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
30d59260
TW		 125
126 udelay(20);
127
8f061891 128 /* disable L1-Active */
30d59260 129 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
8f061891 130 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
30d59260
TW		 131
132 iwl_release_nic_access(priv);
133
134 return ret;
135}
136
f118a91d
TW		 137/* FIXME: this is indentical to 4965 */
138static void iwl5000_apm_stop(struct iwl_priv *priv)
139{
140 unsigned long flags;
141
46315e01 142 iwl5000_apm_stop_master(priv);
f118a91d
TW		 143
144 spin_lock_irqsave(&priv->lock, flags);
145
146 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
147
148 udelay(10);
149
1d3e6c61
MA		 150 /* clear "init complete" move adapter D0A* --> D0U state */
151 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d
TW		 152
153 spin_unlock_irqrestore(&priv->lock, flags);
154}
155
156
7f066108
TW		 157static int iwl5000_apm_reset(struct iwl_priv *priv)
158{
159 int ret = 0;
160 unsigned long flags;
161
46315e01 162 iwl5000_apm_stop_master(priv);
7f066108
TW		 163
164 spin_lock_irqsave(&priv->lock, flags);
165
166 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
167
168 udelay(10);
169
170
171 /* FIXME: put here L1A -L0S w/a */
172
173 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
174
175 /* set "initialization complete" bit to move adapter
176 * D0U* --> D0A* state */
177 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
178
179 /* wait for clock stabilization */
180 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
181 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
182 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
183 if (ret < 0) {
184 IWL_DEBUG_INFO("Failed to init the card\n");
185 goto out;
186 }
187
188 ret = iwl_grab_nic_access(priv);
189 if (ret)
190 goto out;
191
192 /* enable DMA */
193 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
194
195 udelay(20);
196
197 /* disable L1-Active */
198 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
199 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
200
201 iwl_release_nic_access(priv);
202
203out:
204 spin_unlock_irqrestore(&priv->lock, flags);
205
206 return ret;
207}
208
209
5a835353 210static void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 211{
212 unsigned long flags;
213 u16 radio_cfg;
e7b63581 214 u16 link;
e86fe9f6
TW		 215
216 spin_lock_irqsave(&priv->lock, flags);
217
e7b63581 218 pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
e86fe9f6 219
8f061891 220 /* L1 is enabled by BIOS */
e7b63581 221 if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
8f061891
TW		 222 /* diable L0S disabled L1A enabled */
223 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
224 else
225 /* L0S enabled L1A disabled */
226 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
e86fe9f6
TW		 227
228 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
229
230 /* write radio config values to register */
231 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
232 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
233 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
234 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
235 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
236
237 /* set CSR_HW_CONFIG_REG for uCode use */
238 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
239 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
240 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
241
4c43e0d0
TW		 242 /* W/A : NIC is stuck in a reset state after Early PCIe power off
243 * (PCIe power is lost before PERST# is asserted),
244 * causing ME FW to lose ownership and not being able to obtain it back.
245 */
2d3db679
TW		 246 iwl_grab_nic_access(priv);
247 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
4c43e0d0
TW		 248 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
249 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
2d3db679 250 iwl_release_nic_access(priv);
4c43e0d0 251
e86fe9f6
TW		 252 spin_unlock_irqrestore(&priv->lock, flags);
253}
254
255
256
25ae3986
TW		 257/*
258 * EEPROM
259 */
260static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
261{
262 u16 offset = 0;
263
264 if ((address & INDIRECT_ADDRESS) == 0)
265 return address;
266
267 switch (address & INDIRECT_TYPE_MSK) {
268 case INDIRECT_HOST:
269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
270 break;
271 case INDIRECT_GENERAL:
272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
273 break;
274 case INDIRECT_REGULATORY:
275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
276 break;
277 case INDIRECT_CALIBRATION:
278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
279 break;
280 case INDIRECT_PROCESS_ADJST:
281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
282 break;
283 case INDIRECT_OTHERS:
284 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
285 break;
286 default:
287 IWL_ERROR("illegal indirect type: 0x%X\n",
288 address & INDIRECT_TYPE_MSK);
289 break;
290 }
291
292 /* translate the offset from words to byte */
293 return (address & ADDRESS_MSK) + (offset << 1);
294}
295
f1f69415
TW		 296static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
297{
298 u16 eeprom_ver;
299 struct iwl_eeprom_calib_hdr {
300 u8 version;
301 u8 pa_type;
302 u16 voltage;
303 } *hdr;
304
305 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
306
307 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
308 EEPROM_5000_CALIB_ALL);
309
310 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
311 hdr->version < EEPROM_5000_TX_POWER_VERSION)
312 goto err;
313
314 return 0;
315err:
316 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
317 eeprom_ver, EEPROM_5000_EEPROM_VERSION,
318 hdr->version, EEPROM_5000_TX_POWER_VERSION);
319 return -EINVAL;
320
321}
322
33fd5033
EG		 323static void iwl5000_gain_computation(struct iwl_priv *priv,
324 u32 average_noise[NUM_RX_CHAINS],
325 u16 min_average_noise_antenna_i,
326 u32 min_average_noise)
327{
328 int i;
329 s32 delta_g;
330 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
331
332 /* Find Gain Code for the antennas B and C */
333 for (i = 1; i < NUM_RX_CHAINS; i++) {
334 if ((data->disconn_array[i])) {
335 data->delta_gain_code[i] = 0;
336 continue;
337 }
338 delta_g = (1000 * ((s32)average_noise[0] -
339 (s32)average_noise[i])) / 1500;
340 /* bound gain by 2 bits value max, 3rd bit is sign */
341 data->delta_gain_code[i] =
342 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
343
344 if (delta_g < 0)
345 /* set negative sign */
346 data->delta_gain_code[i] |= (1 << 2);
347 }
348
349 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
350 data->delta_gain_code[1], data->delta_gain_code[2]);
351
352 if (!data->radio_write) {
353 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
354 memset(&cmd, 0, sizeof(cmd));
355
356 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
357 cmd.delta_gain_1 = data->delta_gain_code[1];
358 cmd.delta_gain_2 = data->delta_gain_code[2];
359 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
360 sizeof(cmd), &cmd, NULL);
361
362 data->radio_write = 1;
363 data->state = IWL_CHAIN_NOISE_CALIBRATED;
364 }
365
366 data->chain_noise_a = 0;
367 data->chain_noise_b = 0;
368 data->chain_noise_c = 0;
369 data->chain_signal_a = 0;
370 data->chain_signal_b = 0;
371 data->chain_signal_c = 0;
372 data->beacon_count = 0;
373}
374
375static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
376{
377 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
378
379 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
380 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
381
382 memset(&cmd, 0, sizeof(cmd));
383 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
384 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
385 sizeof(cmd), &cmd))
386 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
387 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
388 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
389 }
390}
391
a326a5d0
EG		 392static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
393 __le32 *tx_flags)
394{
e6a9854b
JB		 395 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
396 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
a326a5d0
EG		 397 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
398 else
399 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
400}
401
33fd5033
EG		 402static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
403 .min_nrg_cck = 95,
404 .max_nrg_cck = 0,
405 .auto_corr_min_ofdm = 90,
406 .auto_corr_min_ofdm_mrc = 170,
407 .auto_corr_min_ofdm_x1 = 120,
408 .auto_corr_min_ofdm_mrc_x1 = 240,
409
410 .auto_corr_max_ofdm = 120,
411 .auto_corr_max_ofdm_mrc = 210,
412 .auto_corr_max_ofdm_x1 = 155,
413 .auto_corr_max_ofdm_mrc_x1 = 290,
414
415 .auto_corr_min_cck = 125,
416 .auto_corr_max_cck = 200,
417 .auto_corr_min_cck_mrc = 170,
418 .auto_corr_max_cck_mrc = 400,
419 .nrg_th_cck = 95,
420 .nrg_th_ofdm = 95,
421};
422
25ae3986
TW		 423static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
424 size_t offset)
425{
426 u32 address = eeprom_indirect_address(priv, offset);
427 BUG_ON(address >= priv->cfg->eeprom_size);
428 return &priv->eeprom[address];
429}
430
7c616cba
TW		 431/*
432 * Calibration
433 */
be5d56ed 434static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
7c616cba 435{
be5d56ed
TW		 436 u8 data[sizeof(struct iwl5000_calib_hdr) +
437 sizeof(struct iwl_cal_xtal_freq)];
438 struct iwl5000_calib_cmd *cmd = (struct iwl5000_calib_cmd *)data;
439 struct iwl_cal_xtal_freq *xtal = (struct iwl_cal_xtal_freq *)cmd->data;
7c616cba
TW		 440 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
441
be5d56ed
TW		 442 cmd->hdr.op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
443 xtal->cap_pin1 = (u8)xtal_calib[0];
444 xtal->cap_pin2 = (u8)xtal_calib[1];
445 return iwl_calib_set(&priv->calib_results[IWL5000_CALIB_XTAL],
446 data, sizeof(data));
7c616cba
TW		 447}
448
7c616cba
TW		 449static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
450{
451 struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
452 struct iwl_host_cmd cmd = {
453 .id = CALIBRATION_CFG_CMD,
454 .len = sizeof(struct iwl5000_calib_cfg_cmd),
455 .data = &calib_cfg_cmd,
456 };
457
458 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
459 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
460 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
461 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
462 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
463
464 return iwl_send_cmd(priv, &cmd);
465}
466
467static void iwl5000_rx_calib_result(struct iwl_priv *priv,
468 struct iwl_rx_mem_buffer *rxb)
469{
470 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
471 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
472 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
6e21f2c1 473 int index;
7c616cba
TW		 474
475 /* reduce the size of the length field itself */
476 len -= 4;
477
6e21f2c1
TW		 478 /* Define the order in which the results will be sent to the runtime
479 * uCode. iwl_send_calib_results sends them in a row according to their
480 * index. We sort them here */
7c616cba
TW		 481 switch (hdr->op_code) {
482 case IWL5000_PHY_CALIBRATE_LO_CMD:
6e21f2c1 483 index = IWL5000_CALIB_LO;
7c616cba
TW		 484 break;
485 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
6e21f2c1 486 index = IWL5000_CALIB_TX_IQ;
7c616cba
TW		 487 break;
488 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
6e21f2c1 489 index = IWL5000_CALIB_TX_IQ_PERD;
7c616cba
TW		 490 break;
491 default:
492 IWL_ERROR("Unknown calibration notification %d\n",
493 hdr->op_code);
494 return;
495 }
6e21f2c1 496 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
7c616cba
TW		 497}
498
499static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
500 struct iwl_rx_mem_buffer *rxb)
501{
502 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
503 queue_work(priv->workqueue, &priv->restart);
504}
505
dbb983b7
RR		 506/*
507 * ucode
508 */
509static int iwl5000_load_section(struct iwl_priv *priv,
510 struct fw_desc *image,
511 u32 dst_addr)
512{
513 int ret = 0;
514 unsigned long flags;
515
516 dma_addr_t phy_addr = image->p_addr;
517 u32 byte_cnt = image->len;
518
519 spin_lock_irqsave(&priv->lock, flags);
520 ret = iwl_grab_nic_access(priv);
521 if (ret) {
522 spin_unlock_irqrestore(&priv->lock, flags);
523 return ret;
524 }
525
526 iwl_write_direct32(priv,
527 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
528 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
529
530 iwl_write_direct32(priv,
531 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
532
533 iwl_write_direct32(priv,
534 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
535 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
536
dbb983b7 537 iwl_write_direct32(priv,
f0b9f5cb 538 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
499b1883 539 (iwl_get_dma_hi_addr(phy_addr)
f0b9f5cb
TW		 540 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
541
dbb983b7
RR		 542 iwl_write_direct32(priv,
543 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
544 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
545 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
546 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
547
548 iwl_write_direct32(priv,
549 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
550 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
551 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
552 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
553
554 iwl_release_nic_access(priv);
555 spin_unlock_irqrestore(&priv->lock, flags);
556 return 0;
557}
558
559static int iwl5000_load_given_ucode(struct iwl_priv *priv,
560 struct fw_desc *inst_image,
561 struct fw_desc *data_image)
562{
563 int ret = 0;
564
565 ret = iwl5000_load_section(
566 priv, inst_image, RTC_INST_LOWER_BOUND);
567 if (ret)
568 return ret;
569
570 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
571 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
572 priv->ucode_write_complete, 5 * HZ);
573 if (ret == -ERESTARTSYS) {
574 IWL_ERROR("Could not load the INST uCode section due "
575 "to interrupt\n");
576 return ret;
577 }
578 if (!ret) {
579 IWL_ERROR("Could not load the INST uCode section\n");
580 return -ETIMEDOUT;
581 }
582
583 priv->ucode_write_complete = 0;
584
585 ret = iwl5000_load_section(
586 priv, data_image, RTC_DATA_LOWER_BOUND);
587 if (ret)
588 return ret;
589
590 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
591
592 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
593 priv->ucode_write_complete, 5 * HZ);
594 if (ret == -ERESTARTSYS) {
595 IWL_ERROR("Could not load the INST uCode section due "
596 "to interrupt\n");
597 return ret;
598 } else if (!ret) {
599 IWL_ERROR("Could not load the DATA uCode section\n");
600 return -ETIMEDOUT;
601 } else
602 ret = 0;
603
604 priv->ucode_write_complete = 0;
605
606 return ret;
607}
608
609static int iwl5000_load_ucode(struct iwl_priv *priv)
610{
611 int ret = 0;
612
613 /* check whether init ucode should be loaded, or rather runtime ucode */
614 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
615 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
616 ret = iwl5000_load_given_ucode(priv,
617 &priv->ucode_init, &priv->ucode_init_data);
618 if (!ret) {
619 IWL_DEBUG_INFO("Init ucode load complete.\n");
620 priv->ucode_type = UCODE_INIT;
621 }
622 } else {
623 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
624 "Loading runtime ucode...\n");
625 ret = iwl5000_load_given_ucode(priv,
626 &priv->ucode_code, &priv->ucode_data);
627 if (!ret) {
628 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
629 priv->ucode_type = UCODE_RT;
630 }
631 }
632
633 return ret;
634}
635
99da1b48
RR		 636static void iwl5000_init_alive_start(struct iwl_priv *priv)
637{
638 int ret = 0;
639
640 /* Check alive response for "valid" sign from uCode */
641 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
642 /* We had an error bringing up the hardware, so take it
643 * all the way back down so we can try again */
644 IWL_DEBUG_INFO("Initialize Alive failed.\n");
645 goto restart;
646 }
647
648 /* initialize uCode was loaded... verify inst image.
649 * This is a paranoid check, because we would not have gotten the
650 * "initialize" alive if code weren't properly loaded. */
651 if (iwl_verify_ucode(priv)) {
652 /* Runtime instruction load was bad;
653 * take it all the way back down so we can try again */
654 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
655 goto restart;
656 }
657
37deb2a0 658 iwl_clear_stations_table(priv);
99da1b48
RR		 659 ret = priv->cfg->ops->lib->alive_notify(priv);
660 if (ret) {
661 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
662 goto restart;
663 }
664
7c616cba 665 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 666 return;
667
668restart:
669 /* real restart (first load init_ucode) */
670 queue_work(priv->workqueue, &priv->restart);
671}
672
673static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
674 int txq_id, u32 index)
675{
676 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
677 (index & 0xff) | (txq_id << 8));
678 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
679}
680
681static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
682 struct iwl_tx_queue *txq,
683 int tx_fifo_id, int scd_retry)
684{
685 int txq_id = txq->q.id;
3fd07a1e 686 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
99da1b48
RR		 687
688 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
689 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
690 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
691 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
692 IWL50_SCD_QUEUE_STTS_REG_MSK);
693
694 txq->sched_retry = scd_retry;
695
696 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
697 active ? "Activate" : "Deactivate",
698 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
699}
700
9636e583
RR		 701static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
702{
703 struct iwl_wimax_coex_cmd coex_cmd;
704
705 memset(&coex_cmd, 0, sizeof(coex_cmd));
706
707 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
708 sizeof(coex_cmd), &coex_cmd);
709}
710
99da1b48
RR		 711static int iwl5000_alive_notify(struct iwl_priv *priv)
712{
713 u32 a;
714 int i = 0;
715 unsigned long flags;
716 int ret;
717
718 spin_lock_irqsave(&priv->lock, flags);
719
720 ret = iwl_grab_nic_access(priv);
721 if (ret) {
722 spin_unlock_irqrestore(&priv->lock, flags);
723 return ret;
724 }
725
726 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
727 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
728 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
729 a += 4)
730 iwl_write_targ_mem(priv, a, 0);
731 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
732 a += 4)
733 iwl_write_targ_mem(priv, a, 0);
734 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
735 iwl_write_targ_mem(priv, a, 0);
736
737 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
738 (priv->shared_phys +
739 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
740 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
741 IWL50_SCD_QUEUECHAIN_SEL_ALL(
742 priv->hw_params.max_txq_num));
743 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
744
745 /* initiate the queues */
746 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
747 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
748 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
749 iwl_write_targ_mem(priv, priv->scd_base_addr +
750 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
751 iwl_write_targ_mem(priv, priv->scd_base_addr +
752 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
753 sizeof(u32),
754 ((SCD_WIN_SIZE <<
755 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
756 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
757 ((SCD_FRAME_LIMIT <<
758 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
759 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
760 }
761
762 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 763 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 764
da1bc453
TW		 765 /* Activate all Tx DMA/FIFO channels */
766 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 767
768 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
769 /* map qos queues to fifos one-to-one */
770 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
771 int ac = iwl5000_default_queue_to_tx_fifo[i];
772 iwl_txq_ctx_activate(priv, i);
773 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
774 }
775 /* TODO - need to initialize those FIFOs inside the loop above,
776 * not only mark them as active */
777 iwl_txq_ctx_activate(priv, 4);
778 iwl_txq_ctx_activate(priv, 7);
779 iwl_txq_ctx_activate(priv, 8);
780 iwl_txq_ctx_activate(priv, 9);
781
782 iwl_release_nic_access(priv);
783 spin_unlock_irqrestore(&priv->lock, flags);
784
7c616cba 785
9636e583
RR		 786 iwl5000_send_wimax_coex(priv);
787
be5d56ed
TW		 788 iwl5000_set_Xtal_calib(priv);
789 iwl_send_calib_results(priv);
7c616cba 790
99da1b48
RR		 791 return 0;
792}
793
fdd3e8a4
TW		 794static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
795{
796 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
797 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
798 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
799 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
800 return -EINVAL;
801 }
25ae3986 802
fdd3e8a4 803 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
fdd3e8a4
TW		 804 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
805 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
806 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
807 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
da154e30 808 priv->hw_params.max_bsm_size = 0;
fdd3e8a4
TW		 809 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
810 BIT(IEEE80211_BAND_5GHZ);
33fd5033 811 priv->hw_params.sens = &iwl5000_sensitivity;
fdd3e8a4
TW		 812
813 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
814 case CSR_HW_REV_TYPE_5100:
5d664a41
TW		 815 priv->hw_params.tx_chains_num = 1;
816 priv->hw_params.rx_chains_num = 2;
817 priv->hw_params.valid_tx_ant = ANT_B;
818 priv->hw_params.valid_rx_ant = ANT_AB;
819 break;
fdd3e8a4
TW		 820 case CSR_HW_REV_TYPE_5150:
821 priv->hw_params.tx_chains_num = 1;
822 priv->hw_params.rx_chains_num = 2;
1179f18d
TW		 823 priv->hw_params.valid_tx_ant = ANT_A;
824 priv->hw_params.valid_rx_ant = ANT_AB;
fdd3e8a4
TW		 825 break;
826 case CSR_HW_REV_TYPE_5300:
827 case CSR_HW_REV_TYPE_5350:
828 priv->hw_params.tx_chains_num = 3;
829 priv->hw_params.rx_chains_num = 3;
1179f18d
TW		 830 priv->hw_params.valid_tx_ant = ANT_ABC;
831 priv->hw_params.valid_rx_ant = ANT_ABC;
fdd3e8a4
TW		 832 break;
833 }
c031bf80
EG		 834
835 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
836 case CSR_HW_REV_TYPE_5100:
837 case CSR_HW_REV_TYPE_5300:
d5d7c584
TW		 838 case CSR_HW_REV_TYPE_5350:
839 /* 5X00 and 5350 wants in Celsius */
c031bf80
EG		 840 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
841 break;
842 case CSR_HW_REV_TYPE_5150:
d5d7c584 843 /* 5150 wants in Kelvin */
c031bf80
EG		 844 priv->hw_params.ct_kill_threshold =
845 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
846 break;
847 }
848
be5d56ed
TW		 849 /* Set initial calibration set */
850 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
851 case CSR_HW_REV_TYPE_5100:
852 case CSR_HW_REV_TYPE_5300:
853 case CSR_HW_REV_TYPE_5350:
854 priv->hw_params.calib_init_cfg =
855 BIT(IWL5000_CALIB_XTAL) |
856 BIT(IWL5000_CALIB_LO) |
857 BIT(IWL5000_CALIB_TX_IQ) |
858 BIT(IWL5000_CALIB_TX_IQ_PERD);
859 break;
860 case CSR_HW_REV_TYPE_5150:
861 priv->hw_params.calib_init_cfg = 0;
862 break;
863 }
864
865
fdd3e8a4
TW		 866 return 0;
867}
d4100dd9
RR		 868
869static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
870{
871 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
872 sizeof(struct iwl5000_shared),
873 &priv->shared_phys);
874 if (!priv->shared_virt)
875 return -ENOMEM;
876
877 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
878
d67f5489
RR		 879 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
880
d4100dd9
RR		 881 return 0;
882}
883
884static void iwl5000_free_shared_mem(struct iwl_priv *priv)
885{
886 if (priv->shared_virt)
887 pci_free_consistent(priv->pci_dev,
888 sizeof(struct iwl5000_shared),
889 priv->shared_virt,
890 priv->shared_phys);
891}
892
d67f5489
RR		 893static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
894{
895 struct iwl5000_shared *s = priv->shared_virt;
896 return le32_to_cpu(s->rb_closed) & 0xFFF;
897}
898
7839fc03
EG		 899/**
900 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
901 */
902static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 903 struct iwl_tx_queue *txq,
7839fc03
EG		 904 u16 byte_cnt)
905{
906 struct iwl5000_shared *shared_data = priv->shared_virt;
907 int txq_id = txq->q.id;
908 u8 sec_ctl = 0;
909 u8 sta = 0;
910 int len;
911
912 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
913
914 if (txq_id != IWL_CMD_QUEUE_NUM) {
da99c4b6
GG		 915 sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
916 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 917
918 switch (sec_ctl & TX_CMD_SEC_MSK) {
919 case TX_CMD_SEC_CCM:
920 len += CCMP_MIC_LEN;
921 break;
922 case TX_CMD_SEC_TKIP:
923 len += TKIP_ICV_LEN;
924 break;
925 case TX_CMD_SEC_WEP:
926 len += WEP_IV_LEN + WEP_ICV_LEN;
927 break;
928 }
929 }
930
931 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
932 tfd_offset[txq->q.write_ptr], byte_cnt, len);
933
934 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
935 tfd_offset[txq->q.write_ptr], sta_id, sta);
936
937 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
938 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
939 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
940 byte_cnt, len);
941 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
942 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
943 sta_id, sta);
944 }
945}
946
972cf447
TW		 947static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
948 struct iwl_tx_queue *txq)
949{
950 int txq_id = txq->q.id;
951 struct iwl5000_shared *shared_data = priv->shared_virt;
952 u8 sta = 0;
953
954 if (txq_id != IWL_CMD_QUEUE_NUM)
da99c4b6 955 sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id;
972cf447
TW		 956
957 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
958 val = cpu_to_le16(1 | (sta << 12));
959
960 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
961 shared_data->queues_byte_cnt_tbls[txq_id].
962 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
963 val = cpu_to_le16(1 | (sta << 12));
964 }
965}
966
e26e47d9
TW		 967static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
968 u16 txq_id)
969{
970 u32 tbl_dw_addr;
971 u32 tbl_dw;
972 u16 scd_q2ratid;
973
974 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
975
976 tbl_dw_addr = priv->scd_base_addr +
977 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
978
979 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
980
981 if (txq_id & 0x1)
982 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
983 else
984 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
985
986 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
987
988 return 0;
989}
990static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
991{
992 /* Simply stop the queue, but don't change any configuration;
993 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
994 iwl_write_prph(priv,
995 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
996 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
997 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
998}
999
1000static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1001 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1002{
1003 unsigned long flags;
1004 int ret;
1005 u16 ra_tid;
1006
9f17b318
TW		 1007 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1008 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1009 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1010 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1011 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1012 return -EINVAL;
1013 }
e26e47d9
TW		 1014
1015 ra_tid = BUILD_RAxTID(sta_id, tid);
1016
1017 /* Modify device's station table to Tx this TID */
1018 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1019
1020 spin_lock_irqsave(&priv->lock, flags);
1021 ret = iwl_grab_nic_access(priv);
1022 if (ret) {
1023 spin_unlock_irqrestore(&priv->lock, flags);
1024 return ret;
1025 }
1026
1027 /* Stop this Tx queue before configuring it */
1028 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1029
1030 /* Map receiver-address / traffic-ID to this queue */
1031 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1032
1033 /* Set this queue as a chain-building queue */
1034 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1035
1036 /* enable aggregations for the queue */
1037 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1038
1039 /* Place first TFD at index corresponding to start sequence number.
1040 * Assumes that ssn_idx is valid (!= 0xFFF) */
1041 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1042 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1043 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1044
1045 /* Set up Tx window size and frame limit for this queue */
1046 iwl_write_targ_mem(priv, priv->scd_base_addr +
1047 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1048 sizeof(u32),
1049 ((SCD_WIN_SIZE <<
1050 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1051 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1052 ((SCD_FRAME_LIMIT <<
1053 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1054 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1055
1056 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1057
1058 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1059 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1060
1061 iwl_release_nic_access(priv);
1062 spin_unlock_irqrestore(&priv->lock, flags);
1063
1064 return 0;
1065}
1066
1067static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1068 u16 ssn_idx, u8 tx_fifo)
1069{
1070 int ret;
1071
9f17b318
TW		 1072 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1073 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1074 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1075 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1076 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
e26e47d9
TW		 1077 return -EINVAL;
1078 }
1079
1080 ret = iwl_grab_nic_access(priv);
1081 if (ret)
1082 return ret;
1083
1084 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1085
1086 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1087
1088 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1089 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1090 /* supposes that ssn_idx is valid (!= 0xFFF) */
1091 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1092
1093 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1094 iwl_txq_ctx_deactivate(priv, txq_id);
1095 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1096
1097 iwl_release_nic_access(priv);
1098
1099 return 0;
1100}
1101
2469bf2e
TW		 1102static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1103{
1104 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1105 memcpy(data, cmd, size);
1106 return size;
1107}
1108
1109
da1bc453
TW		 1110/*
1111 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
1112 * must be called under priv->lock and mac access
1113 */
1114static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 1115{
da1bc453 1116 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 1117}
1118
e532fa0e
RR		 1119
1120static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1121{
3ac7f146 1122 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 1123 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 1124}
1125
1126static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1127 struct iwl_ht_agg *agg,
1128 struct iwl5000_tx_resp *tx_resp,
25a6572c 1129 int txq_id, u16 start_idx)
e532fa0e
RR		 1130{
1131 u16 status;
1132 struct agg_tx_status *frame_status = &tx_resp->status;
1133 struct ieee80211_tx_info *info = NULL;
1134 struct ieee80211_hdr *hdr = NULL;
e7d326ac 1135 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 1136 int i, sh, idx;
e532fa0e
RR		 1137 u16 seq;
1138
1139 if (agg->wait_for_ba)
1140 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1141
1142 agg->frame_count = tx_resp->frame_count;
1143 agg->start_idx = start_idx;
e7d326ac 1144 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 1145 agg->bitmap = 0;
1146
1147 /* # frames attempted by Tx command */
1148 if (agg->frame_count == 1) {
1149 /* Only one frame was attempted; no block-ack will arrive */
1150 status = le16_to_cpu(frame_status[0].status);
25a6572c 1151 idx = start_idx;
e532fa0e
RR		 1152
1153 /* FIXME: code repetition */
1154 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1155 agg->frame_count, agg->start_idx, idx);
1156
1157 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 1158 info->status.rates[0].count = tx_resp->failure_frame + 1;
e532fa0e
RR		 1159 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1160 info->flags |= iwl_is_tx_success(status)?
3fd07a1e 1161 IEEE80211_TX_STAT_ACK : 0;
e7d326ac
TW		 1162 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1163
e532fa0e
RR		 1164 /* FIXME: code repetition end */
1165
1166 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1167 status & 0xff, tx_resp->failure_frame);
e7d326ac 1168 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1169
1170 agg->wait_for_ba = 0;
1171 } else {
1172 /* Two or more frames were attempted; expect block-ack */
1173 u64 bitmap = 0;
1174 int start = agg->start_idx;
1175
1176 /* Construct bit-map of pending frames within Tx window */
1177 for (i = 0; i < agg->frame_count; i++) {
1178 u16 sc;
1179 status = le16_to_cpu(frame_status[i].status);
1180 seq = le16_to_cpu(frame_status[i].sequence);
1181 idx = SEQ_TO_INDEX(seq);
1182 txq_id = SEQ_TO_QUEUE(seq);
1183
1184 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1185 AGG_TX_STATE_ABORT_MSK))
1186 continue;
1187
1188 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1189 agg->frame_count, txq_id, idx);
1190
1191 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1192
1193 sc = le16_to_cpu(hdr->seq_ctrl);
1194 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1195 IWL_ERROR("BUG_ON idx doesn't match seq control"
1196 " idx=%d, seq_idx=%d, seq=%d\n",
1197 idx, SEQ_TO_SN(sc),
1198 hdr->seq_ctrl);
1199 return -1;
1200 }
1201
1202 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1203 i, idx, SEQ_TO_SN(sc));
1204
1205 sh = idx - start;
1206 if (sh > 64) {
1207 sh = (start - idx) + 0xff;
1208 bitmap = bitmap << sh;
1209 sh = 0;
1210 start = idx;
1211 } else if (sh < -64)
1212 sh = 0xff - (start - idx);
1213 else if (sh < 0) {
1214 sh = start - idx;
1215 start = idx;
1216 bitmap = bitmap << sh;
1217 sh = 0;
1218 }
4aa41f12
EG		 1219 bitmap |= 1ULL << sh;
1220 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1221 start, (unsigned long long)bitmap);
e532fa0e
RR		 1222 }
1223
1224 agg->bitmap = bitmap;
1225 agg->start_idx = start;
e532fa0e
RR		 1226 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1227 agg->frame_count, agg->start_idx,
1228 (unsigned long long)agg->bitmap);
1229
1230 if (bitmap)
1231 agg->wait_for_ba = 1;
1232 }
1233 return 0;
1234}
1235
1236static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1237 struct iwl_rx_mem_buffer *rxb)
1238{
1239 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1240 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1241 int txq_id = SEQ_TO_QUEUE(sequence);
1242 int index = SEQ_TO_INDEX(sequence);
1243 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1244 struct ieee80211_tx_info *info;
1245 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1246 u32 status = le16_to_cpu(tx_resp->status.status);
3fd07a1e
TW		 1247 int tid;
1248 int sta_id;
1249 int freed;
e532fa0e
RR		 1250
1251 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1252 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1253 "is out of range [0-%d] %d %d\n", txq_id,
1254 index, txq->q.n_bd, txq->q.write_ptr,
1255 txq->q.read_ptr);
1256 return;
1257 }
1258
1259 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1260 memset(&info->status, 0, sizeof(info->status));
1261
3fd07a1e
TW		 1262 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1263 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
e532fa0e
RR		 1264
1265 if (txq->sched_retry) {
1266 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1267 struct iwl_ht_agg *agg = NULL;
1268
e532fa0e
RR		 1269 agg = &priv->stations[sta_id].tid[tid].agg;
1270
25a6572c 1271 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1272
3235427e
RR		 1273 /* check if BAR is needed */
1274 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1275 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1276
1277 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
e532fa0e 1278 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
3fd07a1e
TW		 1279 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1280 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1281 scd_ssn , index, txq_id, txq->swq_id);
1282
17b88929 1283 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1284 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1285
3fd07a1e
TW		 1286 if (priv->mac80211_registered &&
1287 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1288 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
e532fa0e
RR		 1289 if (agg->state == IWL_AGG_OFF)
1290 ieee80211_wake_queue(priv->hw, txq_id);
1291 else
3fd07a1e
TW		 1292 ieee80211_wake_queue(priv->hw,
1293 txq->swq_id);
e532fa0e 1294 }
e532fa0e
RR		 1295 }
1296 } else {
3fd07a1e
TW		 1297 BUG_ON(txq_id != txq->swq_id);
1298
e6a9854b 1299 info->status.rates[0].count = tx_resp->failure_frame + 1;
3fd07a1e
TW		 1300 info->flags |= iwl_is_tx_success(status) ?
1301 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 1302 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1303 le32_to_cpu(tx_resp->rate_n_flags),
1304 info);
1305
3fd07a1e
TW		 1306 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1307 "0x%x retries %d\n",
1308 txq_id,
1309 iwl_get_tx_fail_reason(status), status,
1310 le32_to_cpu(tx_resp->rate_n_flags),
1311 tx_resp->failure_frame);
4f85f5b3 1312
3fd07a1e
TW		 1313 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1314 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
e532fa0e 1315 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 1316
1317 if (priv->mac80211_registered &&
1318 (iwl_queue_space(&txq->q) > txq->q.low_mark))
e532fa0e 1319 ieee80211_wake_queue(priv->hw, txq_id);
e532fa0e 1320 }
e532fa0e 1321
3fd07a1e
TW		 1322 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1323 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1324
e532fa0e
RR		 1325 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1326 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1327}
1328
c1adf9fb
GG		 1329/* Currently 5000 is the supperset of everything */
1330static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1331{
1332 return len;
1333}
1334
203566f3
EG		 1335static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1336{
1337 /* in 5000 the tx power calibration is done in uCode */
1338 priv->disable_tx_power_cal = 1;
1339}
1340
b600e4e1
RR		 1341static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1342{
7c616cba
TW		 1343 /* init calibration handlers */
1344 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1345 iwl5000_rx_calib_result;
1346 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1347 iwl5000_rx_calib_complete;
e532fa0e 1348 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1349}
1350
7c616cba 1351
87283cc1
RR		 1352static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1353{
1354 return (addr >= RTC_DATA_LOWER_BOUND) &&
1355 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1356}
1357
fe7a90c2
RR		 1358static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1359{
1360 int ret = 0;
1361 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1362 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1363 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1364
1365 if ((rxon1->flags == rxon2->flags) &&
1366 (rxon1->filter_flags == rxon2->filter_flags) &&
1367 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1368 (rxon1->ofdm_ht_single_stream_basic_rates ==
1369 rxon2->ofdm_ht_single_stream_basic_rates) &&
1370 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1371 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1372 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1373 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1374 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1375 (rxon1->rx_chain == rxon2->rx_chain) &&
1376 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1377 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1378 return 0;
1379 }
1380
1381 rxon_assoc.flags = priv->staging_rxon.flags;
1382 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1383 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1384 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1385 rxon_assoc.reserved1 = 0;
1386 rxon_assoc.reserved2 = 0;
1387 rxon_assoc.reserved3 = 0;
1388 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1389 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1390 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1391 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1392 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1393 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1394 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1395 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1396
1397 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1398 sizeof(rxon_assoc), &rxon_assoc, NULL);
1399 if (ret)
1400 return ret;
1401
1402 return ret;
1403}
630fe9b6
TW		 1404static int iwl5000_send_tx_power(struct iwl_priv *priv)
1405{
1406 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1407
1408 /* half dBm need to multiply */
1409 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
853554ac 1410 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6
TW		 1411 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1412 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1413 sizeof(tx_power_cmd), &tx_power_cmd,
1414 NULL);
1415}
1416
5225640b 1417static void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1418{
1419 /* store temperature from statistics (in Celsius) */
5225640b 1420 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
8f91aecb 1421}
fe7a90c2 1422
caab8f1a
TW		 1423/* Calc max signal level (dBm) among 3 possible receivers */
1424static int iwl5000_calc_rssi(struct iwl_priv *priv,
1425 struct iwl_rx_phy_res *rx_resp)
1426{
1427 /* data from PHY/DSP regarding signal strength, etc.,
1428 * contents are always there, not configurable by host
1429 */
1430 struct iwl5000_non_cfg_phy *ncphy =
1431 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1432 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1433 u8 agc;
1434
1435 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1436 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1437
1438 /* Find max rssi among 3 possible receivers.
1439 * These values are measured by the digital signal processor (DSP).
1440 * They should stay fairly constant even as the signal strength varies,
1441 * if the radio's automatic gain control (AGC) is working right.
1442 * AGC value (see below) will provide the "interesting" info.
1443 */
1444 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1445 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1446 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1447 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1448 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1449
1450 max_rssi = max_t(u32, rssi_a, rssi_b);
1451 max_rssi = max_t(u32, max_rssi, rssi_c);
1452
1453 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1454 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1455
1456 /* dBm = max_rssi dB - agc dB - constant.
1457 * Higher AGC (higher radio gain) means lower signal. */
1458 return max_rssi - agc - IWL_RSSI_OFFSET;
1459}
1460
da8dec29 1461static struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1462 .rxon_assoc = iwl5000_send_rxon_assoc,
da8dec29
TW		 1463};
1464
1465static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1466 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1467 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1468 .gain_computation = iwl5000_gain_computation,
1469 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1470 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1471 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1472};
1473
1474static struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1475 .set_hw_params = iwl5000_hw_set_hw_params,
d4100dd9
RR		 1476 .alloc_shared_mem = iwl5000_alloc_shared_mem,
1477 .free_shared_mem = iwl5000_free_shared_mem,
d67f5489 1478 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
7839fc03 1479 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1480 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1481 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1482 .txq_agg_enable = iwl5000_txq_agg_enable,
1483 .txq_agg_disable = iwl5000_txq_agg_disable,
b600e4e1 1484 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1485 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1486 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
dbb983b7 1487 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1488 .init_alive_start = iwl5000_init_alive_start,
1489 .alive_notify = iwl5000_alive_notify,
630fe9b6 1490 .send_tx_power = iwl5000_send_tx_power,
8f91aecb 1491 .temperature = iwl5000_temperature,
ca579617 1492 .update_chain_flags = iwl4965_update_chain_flags,
30d59260
TW		 1493 .apm_ops = {
1494 .init = iwl5000_apm_init,
7f066108 1495 .reset = iwl5000_apm_reset,
f118a91d 1496 .stop = iwl5000_apm_stop,
5a835353 1497 .config = iwl5000_nic_config,
88acbd3b 1498 .set_pwr_src = iwl4965_set_pwr_src,
30d59260 1499 },
da8dec29 1500 .eeprom_ops = {
25ae3986
TW		 1501 .regulatory_bands = {
1502 EEPROM_5000_REG_BAND_1_CHANNELS,
1503 EEPROM_5000_REG_BAND_2_CHANNELS,
1504 EEPROM_5000_REG_BAND_3_CHANNELS,
1505 EEPROM_5000_REG_BAND_4_CHANNELS,
1506 EEPROM_5000_REG_BAND_5_CHANNELS,
1507 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1508 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1509 },
da8dec29
TW		 1510 .verify_signature = iwlcore_eeprom_verify_signature,
1511 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1512 .release_semaphore = iwlcore_eeprom_release_semaphore,
f1f69415 1513 .check_version = iwl5000_eeprom_check_version,
25ae3986 1514 .query_addr = iwl5000_eeprom_query_addr,
da8dec29
TW		 1515 },
1516};
1517
1518static struct iwl_ops iwl5000_ops = {
1519 .lib = &iwl5000_lib,
1520 .hcmd = &iwl5000_hcmd,
1521 .utils = &iwl5000_hcmd_utils,
1522};
1523
5a6a256e
TW		 1524static struct iwl_mod_params iwl50_mod_params = {
1525 .num_of_queues = IWL50_NUM_QUEUES,
9f17b318 1526 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e
TW		 1527 .enable_qos = 1,
1528 .amsdu_size_8K = 1,
3a1081e8 1529 .restart_fw = 1,
5a6a256e
TW		 1530 /* the rest are 0 by default */
1531};
1532
1533
1534struct iwl_cfg iwl5300_agn_cfg = {
1535 .name = "5300AGN",
4e062f99 1536 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1537 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1538 .ops = &iwl5000_ops,
25ae3986 1539 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e
TW		 1540 .mod_params = &iwl50_mod_params,
1541};
1542
47408639
EK		 1543struct iwl_cfg iwl5100_bg_cfg = {
1544 .name = "5100BG",
4e062f99 1545 .fw_name = IWL5000_MODULE_FIRMWARE,
47408639
EK		 1546 .sku = IWL_SKU_G,
1547 .ops = &iwl5000_ops,
1548 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1549 .mod_params = &iwl50_mod_params,
1550};
1551
1552struct iwl_cfg iwl5100_abg_cfg = {
1553 .name = "5100ABG",
4e062f99 1554 .fw_name = IWL5000_MODULE_FIRMWARE,
47408639
EK		 1555 .sku = IWL_SKU_A|IWL_SKU_G,
1556 .ops = &iwl5000_ops,
1557 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1558 .mod_params = &iwl50_mod_params,
1559};
1560
5a6a256e
TW		 1561struct iwl_cfg iwl5100_agn_cfg = {
1562 .name = "5100AGN",
4e062f99 1563 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1564 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1565 .ops = &iwl5000_ops,
25ae3986 1566 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e
TW		 1567 .mod_params = &iwl50_mod_params,
1568};
1569
1570struct iwl_cfg iwl5350_agn_cfg = {
1571 .name = "5350AGN",
4e062f99 1572 .fw_name = IWL5000_MODULE_FIRMWARE,
5a6a256e 1573 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1574 .ops = &iwl5000_ops,
25ae3986 1575 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e
TW		 1576 .mod_params = &iwl50_mod_params,
1577};
1578
4e062f99 1579MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE);
c9f79ed2 1580
5a6a256e
TW		 1581module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1582MODULE_PARM_DESC(disable50,
1583 "manually disable the 50XX radio (default 0 [radio on])");
1584module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1585MODULE_PARM_DESC(swcrypto50,
1586 "using software crypto engine (default 0 [hardware])\n");
1587module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1588MODULE_PARM_DESC(debug50, "50XX debug output mask");
1589module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1590MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1591module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1592MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
49779293
RR		 1593module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1594MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
5a6a256e
TW		 1595module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1596MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
3a1081e8
EK		 1597module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1598MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Linux kernel - Deliverables
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