[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c

/******************************************************************************
 *
 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/wireless.h>
#include <net/mac80211.h>
#include <linux/etherdevice.h>
#include <asm/unaligned.h>

#include "iwl-eeprom.h"
#include "iwl-4965.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-helpers.h"
#include "iwl-5000-hw.h"

#define IWL5000_UCODE_API  "-1"

static int iwl5000_apm_init(struct iwl_priv *priv)
{
	int ret = 0;

	iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
		    CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);

	iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);

	/* set "initialization complete" bit to move adapter
	 * D0U* --> D0A* state */
	iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);

	/* wait for clock stabilization */
	ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
			  CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
			  CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
	if (ret < 0) {
		IWL_DEBUG_INFO("Failed to init the card\n");
		return ret;
	}

	ret = iwl_grab_nic_access(priv);
	if (ret)
		return ret;

	/* enable DMA */
	iwl_write_prph(priv, APMG_CLK_EN_REG,
			APMG_CLK_VAL_DMA_CLK_RQT);

	udelay(20);

	iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
			APMG_PCIDEV_STT_VAL_L1_ACT_DIS);

	iwl_release_nic_access(priv);

	return ret;
}

/*
 * EEPROM
 */
static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
{
	u16 offset = 0;

	if ((address & INDIRECT_ADDRESS) == 0)
		return address;

	switch (address & INDIRECT_TYPE_MSK) {
	case INDIRECT_HOST:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
		break;
	case INDIRECT_GENERAL:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
		break;
	case INDIRECT_REGULATORY:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
		break;
	case INDIRECT_CALIBRATION:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
		break;
	case INDIRECT_PROCESS_ADJST:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
		break;
	case INDIRECT_OTHERS:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
		break;
	default:
		IWL_ERROR("illegal indirect type: 0x%X\n",
		address & INDIRECT_TYPE_MSK);
		break;
	}

	/* translate the offset from words to byte */
	return (address & ADDRESS_MSK) + (offset << 1);
}

static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
					   size_t offset)
{
	u32 address = eeprom_indirect_address(priv, offset);
	BUG_ON(address >= priv->cfg->eeprom_size);
	return &priv->eeprom[address];
}

static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
{
	if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
	    (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
		IWL_ERROR("invalid queues_num, should be between %d and %d\n",
			  IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
		return -EINVAL;
	}

	priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
	priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
	priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
	priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
	priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
	if (priv->cfg->mod_params->amsdu_size_8K)
		priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
	else
		priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
	priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
	priv->hw_params.max_stations = IWL5000_STATION_COUNT;
	priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
	priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
	priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
	priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
	priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
					BIT(IEEE80211_BAND_5GHZ);

	switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
	case CSR_HW_REV_TYPE_5100:
	case CSR_HW_REV_TYPE_5150:
		priv->hw_params.tx_chains_num = 1;
		priv->hw_params.rx_chains_num = 2;
		/* FIXME: move to ANT_A, ANT_B, ANT_C enum */
		priv->hw_params.valid_tx_ant = IWL_ANTENNA_MAIN;
		priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN |
						IWL_ANTENNA_AUX);
		break;
	case CSR_HW_REV_TYPE_5300:
	case CSR_HW_REV_TYPE_5350:
		priv->hw_params.tx_chains_num = 3;
		priv->hw_params.rx_chains_num = 3;
		/* FIXME: move to ANT_A, ANT_B, ANT_C enum */
		priv->hw_params.valid_tx_ant = (IWL_ANTENNA_MAIN |
						IWL_ANTENNA_AUX | 0x04);
		priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN |
						IWL_ANTENNA_AUX | 0x04);
		break;
	}
	return 0;
}
static struct iwl_hcmd_ops iwl5000_hcmd = {
};

static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
};

static struct iwl_lib_ops iwl5000_lib = {
	.set_hw_params = iwl5000_hw_set_hw_params,
	.apm_ops = {
		.init =	iwl5000_apm_init,
		.set_pwr_src = iwl4965_set_pwr_src,
	},
	.eeprom_ops = {
		.regulatory_bands = {
			EEPROM_5000_REG_BAND_1_CHANNELS,
			EEPROM_5000_REG_BAND_2_CHANNELS,
			EEPROM_5000_REG_BAND_3_CHANNELS,
			EEPROM_5000_REG_BAND_4_CHANNELS,
			EEPROM_5000_REG_BAND_5_CHANNELS,
			EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
			EEPROM_5000_REG_BAND_52_FAT_CHANNELS
		},
		.verify_signature  = iwlcore_eeprom_verify_signature,
		.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
		.release_semaphore = iwlcore_eeprom_release_semaphore,
		.query_addr = iwl5000_eeprom_query_addr,
	},
};

static struct iwl_ops iwl5000_ops = {
	.lib = &iwl5000_lib,
	.hcmd = &iwl5000_hcmd,
	.utils = &iwl5000_hcmd_utils,
};

static struct iwl_mod_params iwl50_mod_params = {
	.num_of_queues = IWL50_NUM_QUEUES,
	.enable_qos = 1,
	.amsdu_size_8K = 1,
	/* the rest are 0 by default */
};


struct iwl_cfg iwl5300_agn_cfg = {
	.name = "5300AGN",
	.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
	.ops = &iwl5000_ops,
	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
	.mod_params = &iwl50_mod_params,
};

struct iwl_cfg iwl5100_agn_cfg = {
	.name = "5100AGN",
	.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
	.ops = &iwl5000_ops,
	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
	.mod_params = &iwl50_mod_params,
};

struct iwl_cfg iwl5350_agn_cfg = {
	.name = "5350AGN",
	.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
	.sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
	.ops = &iwl5000_ops,
	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
	.mod_params = &iwl50_mod_params,
};

module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
MODULE_PARM_DESC(disable50,
		  "manually disable the 50XX radio (default 0 [radio on])");
module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
MODULE_PARM_DESC(swcrypto50,
		  "using software crypto engine (default 0 [hardware])\n");
module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
MODULE_PARM_DESC(debug50, "50XX debug output mask");
module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
Commit	Line	Data
5a6a256e TW	1	/******************************************************************************
	2	*
	3	* Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	23	*
	24	*****************************************************************************/
	25
	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/version.h>
	29	#include <linux/init.h>
	30	#include <linux/pci.h>
	31	#include <linux/dma-mapping.h>
	32	#include <linux/delay.h>
	33	#include <linux/skbuff.h>
	34	#include <linux/netdevice.h>
	35	#include <linux/wireless.h>
	36	#include <net/mac80211.h>
	37	#include <linux/etherdevice.h>
	38	#include <asm/unaligned.h>
	39
	40	#include "iwl-eeprom.h"
	41	#include "iwl-4965.h"
	42	#include "iwl-core.h"
	43	#include "iwl-io.h"
	44	#include "iwl-helpers.h"
	45	#include "iwl-5000-hw.h"
	46
	47	#define IWL5000_UCODE_API "-1"
	48
30d59260 TW	49	static int iwl5000_apm_init(struct iwl_priv *priv)
	50	{
	51	int ret = 0;
	52
	53	iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
	54	CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
	55
	56	iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
	57
	58	/* set "initialization complete" bit to move adapter
	59	* D0U* --> D0A* state */
	60	iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
	61
	62	/* wait for clock stabilization */
	63	ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
	64	CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
	65	CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
	66	if (ret < 0) {
	67	IWL_DEBUG_INFO("Failed to init the card\n");
	68	return ret;
	69	}
	70
	71	ret = iwl_grab_nic_access(priv);
	72	if (ret)
	73	return ret;
	74
	75	/* enable DMA */
	76	iwl_write_prph(priv, APMG_CLK_EN_REG,
	77	APMG_CLK_VAL_DMA_CLK_RQT);
	78
	79	udelay(20);
	80
	81	iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
	82	APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
	83
	84	iwl_release_nic_access(priv);
	85
	86	return ret;
	87	}
	88
25ae3986 TW	89	/*
	90	* EEPROM
	91	*/
	92	static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
	93	{
	94	u16 offset = 0;
	95
	96	if ((address & INDIRECT_ADDRESS) == 0)
	97	return address;
	98
	99	switch (address & INDIRECT_TYPE_MSK) {
	100	case INDIRECT_HOST:
	101	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
	102	break;
	103	case INDIRECT_GENERAL:
	104	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
	105	break;
	106	case INDIRECT_REGULATORY:
	107	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
	108	break;
	109	case INDIRECT_CALIBRATION:
	110	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
	111	break;
	112	case INDIRECT_PROCESS_ADJST:
	113	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
	114	break;
	115	case INDIRECT_OTHERS:
	116	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
	117	break;
	118	default:
	119	IWL_ERROR("illegal indirect type: 0x%X\n",
	120	address & INDIRECT_TYPE_MSK);
	121	break;
	122	}
	123
	124	/* translate the offset from words to byte */
	125	return (address & ADDRESS_MSK) + (offset << 1);
	126	}
	127
	128	static const u8 iwl5000_eeprom_query_addr(const struct iwl_priv priv,
	129	size_t offset)
	130	{
	131	u32 address = eeprom_indirect_address(priv, offset);
	132	BUG_ON(address >= priv->cfg->eeprom_size);
	133	return &priv->eeprom[address];
	134	}
	135
fdd3e8a4 TW	136	static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
	137	{
	138	if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) \|\|
	139	(priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
	140	IWL_ERROR("invalid queues_num, should be between %d and %d\n",
	141	IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
	142	return -EINVAL;
	143	}
25ae3986	144
fdd3e8a4 TW	145	priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
	146	priv->hw_params.sw_crypto = priv->cfg->mod_params->sw_crypto;
	147	priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
	148	priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
	149	priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
	150	if (priv->cfg->mod_params->amsdu_size_8K)
	151	priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
	152	else
	153	priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
	154	priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
	155	priv->hw_params.max_stations = IWL5000_STATION_COUNT;
	156	priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
	157	priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
	158	priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
	159	priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
	160	priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) \|
	161	BIT(IEEE80211_BAND_5GHZ);
	162
	163	switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
	164	case CSR_HW_REV_TYPE_5100:
	165	case CSR_HW_REV_TYPE_5150:
	166	priv->hw_params.tx_chains_num = 1;
	167	priv->hw_params.rx_chains_num = 2;
	168	/* FIXME: move to ANT_A, ANT_B, ANT_C enum */
	169	priv->hw_params.valid_tx_ant = IWL_ANTENNA_MAIN;
	170	priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN \|
	171	IWL_ANTENNA_AUX);
	172	break;
	173	case CSR_HW_REV_TYPE_5300:
	174	case CSR_HW_REV_TYPE_5350:
	175	priv->hw_params.tx_chains_num = 3;
	176	priv->hw_params.rx_chains_num = 3;
	177	/* FIXME: move to ANT_A, ANT_B, ANT_C enum */
	178	priv->hw_params.valid_tx_ant = (IWL_ANTENNA_MAIN \|
	179	IWL_ANTENNA_AUX \| 0x04);
	180	priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN \|
	181	IWL_ANTENNA_AUX \| 0x04);
	182	break;
	183	}
	184	return 0;
	185	}
da8dec29 TW	186	static struct iwl_hcmd_ops iwl5000_hcmd = {
	187	};
	188
	189	static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
	190	};
	191
	192	static struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4	193	.set_hw_params = iwl5000_hw_set_hw_params,
30d59260 TW	194	.apm_ops = {
30d59260 TW	195	.init = iwl5000_apm_init,
88acbd3b	196	.set_pwr_src = iwl4965_set_pwr_src,
30d59260	197	},
da8dec29	198	.eeprom_ops = {
25ae3986 TW	199	.regulatory_bands = {
	200	EEPROM_5000_REG_BAND_1_CHANNELS,
	201	EEPROM_5000_REG_BAND_2_CHANNELS,
	202	EEPROM_5000_REG_BAND_3_CHANNELS,
	203	EEPROM_5000_REG_BAND_4_CHANNELS,
	204	EEPROM_5000_REG_BAND_5_CHANNELS,
	205	EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
	206	EEPROM_5000_REG_BAND_52_FAT_CHANNELS
	207	},
da8dec29 TW	208	.verify_signature = iwlcore_eeprom_verify_signature,
	209	.acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
	210	.release_semaphore = iwlcore_eeprom_release_semaphore,
25ae3986	211	.query_addr = iwl5000_eeprom_query_addr,
da8dec29 TW	212	},
	213	};
	214
	215	static struct iwl_ops iwl5000_ops = {
	216	.lib = &iwl5000_lib,
	217	.hcmd = &iwl5000_hcmd,
	218	.utils = &iwl5000_hcmd_utils,
	219	};
	220
5a6a256e TW	221	static struct iwl_mod_params iwl50_mod_params = {
	222	.num_of_queues = IWL50_NUM_QUEUES,
	223	.enable_qos = 1,
	224	.amsdu_size_8K = 1,
	225	/* the rest are 0 by default */
	226	};
	227
	228
	229	struct iwl_cfg iwl5300_agn_cfg = {
	230	.name = "5300AGN",
	231	.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
	232	.sku = IWL_SKU_A\|IWL_SKU_G\|IWL_SKU_N,
da8dec29	233	.ops = &iwl5000_ops,
25ae3986	234	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e TW	235	.mod_params = &iwl50_mod_params,
	236	};
	237
	238	struct iwl_cfg iwl5100_agn_cfg = {
	239	.name = "5100AGN",
	240	.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
	241	.sku = IWL_SKU_A\|IWL_SKU_G\|IWL_SKU_N,
da8dec29	242	.ops = &iwl5000_ops,
25ae3986	243	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e TW	244	.mod_params = &iwl50_mod_params,
	245	};
	246
	247	struct iwl_cfg iwl5350_agn_cfg = {
	248	.name = "5350AGN",
	249	.fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
	250	.sku = IWL_SKU_A\|IWL_SKU_G\|IWL_SKU_N,
da8dec29	251	.ops = &iwl5000_ops,
25ae3986	252	.eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e TW	253	.mod_params = &iwl50_mod_params,
	254	};
	255
	256	module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
	257	MODULE_PARM_DESC(disable50,
	258	"manually disable the 50XX radio (default 0 [radio on])");
	259	module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
	260	MODULE_PARM_DESC(swcrypto50,
	261	"using software crypto engine (default 0 [hardware])\n");
	262	module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
	263	MODULE_PARM_DESC(debug50, "50XX debug output mask");
	264	module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
	265	MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
	266	module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
	267	MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
	268	module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
	269	MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
	270
	271