[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c

/******************************************************************************
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>

#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-helpers.h"
#include "iwl-agn-hw.h"
#include "iwl-agn.h"

static inline u32 iwlagn_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
{
	return le32_to_cpup((__le32 *)&tx_resp->status +
			    tx_resp->frame_count) & MAX_SN;
}

static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
				      struct iwl_ht_agg *agg,
				      struct iwl5000_tx_resp *tx_resp,
				      int txq_id, u16 start_idx)
{
	u16 status;
	struct agg_tx_status *frame_status = &tx_resp->status;
	struct ieee80211_tx_info *info = NULL;
	struct ieee80211_hdr *hdr = NULL;
	u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
	int i, sh, idx;
	u16 seq;

	if (agg->wait_for_ba)
		IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");

	agg->frame_count = tx_resp->frame_count;
	agg->start_idx = start_idx;
	agg->rate_n_flags = rate_n_flags;
	agg->bitmap = 0;

	/* # frames attempted by Tx command */
	if (agg->frame_count == 1) {
		/* Only one frame was attempted; no block-ack will arrive */
		status = le16_to_cpu(frame_status[0].status);
		idx = start_idx;

		/* FIXME: code repetition */
		IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
				   agg->frame_count, agg->start_idx, idx);

		info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
		info->status.rates[0].count = tx_resp->failure_frame + 1;
		info->flags &= ~IEEE80211_TX_CTL_AMPDU;
		info->flags |= iwl_tx_status_to_mac80211(status);
		iwl_hwrate_to_tx_control(priv, rate_n_flags, info);

		/* FIXME: code repetition end */

		IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
				    status & 0xff, tx_resp->failure_frame);
		IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);

		agg->wait_for_ba = 0;
	} else {
		/* Two or more frames were attempted; expect block-ack */
		u64 bitmap = 0;
		int start = agg->start_idx;

		/* Construct bit-map of pending frames within Tx window */
		for (i = 0; i < agg->frame_count; i++) {
			u16 sc;
			status = le16_to_cpu(frame_status[i].status);
			seq  = le16_to_cpu(frame_status[i].sequence);
			idx = SEQ_TO_INDEX(seq);
			txq_id = SEQ_TO_QUEUE(seq);

			if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
				      AGG_TX_STATE_ABORT_MSK))
				continue;

			IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
					   agg->frame_count, txq_id, idx);

			hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
			if (!hdr) {
				IWL_ERR(priv,
					"BUG_ON idx doesn't point to valid skb"
					" idx=%d, txq_id=%d\n", idx, txq_id);
				return -1;
			}

			sc = le16_to_cpu(hdr->seq_ctrl);
			if (idx != (SEQ_TO_SN(sc) & 0xff)) {
				IWL_ERR(priv,
					"BUG_ON idx doesn't match seq control"
					" idx=%d, seq_idx=%d, seq=%d\n",
					  idx, SEQ_TO_SN(sc),
					  hdr->seq_ctrl);
				return -1;
			}

			IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
					   i, idx, SEQ_TO_SN(sc));

			sh = idx - start;
			if (sh > 64) {
				sh = (start - idx) + 0xff;
				bitmap = bitmap << sh;
				sh = 0;
				start = idx;
			} else if (sh < -64)
				sh  = 0xff - (start - idx);
			else if (sh < 0) {
				sh = start - idx;
				start = idx;
				bitmap = bitmap << sh;
				sh = 0;
			}
			bitmap |= 1ULL << sh;
			IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
					   start, (unsigned long long)bitmap);
		}

		agg->bitmap = bitmap;
		agg->start_idx = start;
		IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
				   agg->frame_count, agg->start_idx,
				   (unsigned long long)agg->bitmap);

		if (bitmap)
			agg->wait_for_ba = 1;
	}
	return 0;
}

static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
				struct iwl_rx_mem_buffer *rxb)
{
	struct iwl_rx_packet *pkt = rxb_addr(rxb);
	u16 sequence = le16_to_cpu(pkt->hdr.sequence);
	int txq_id = SEQ_TO_QUEUE(sequence);
	int index = SEQ_TO_INDEX(sequence);
	struct iwl_tx_queue *txq = &priv->txq[txq_id];
	struct ieee80211_tx_info *info;
	struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
	u32  status = le16_to_cpu(tx_resp->status.status);
	int tid;
	int sta_id;
	int freed;

	if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
		IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
			  "is out of range [0-%d] %d %d\n", txq_id,
			  index, txq->q.n_bd, txq->q.write_ptr,
			  txq->q.read_ptr);
		return;
	}

	info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
	memset(&info->status, 0, sizeof(info->status));

	tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
	sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;

	if (txq->sched_retry) {
		const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
		struct iwl_ht_agg *agg = NULL;

		agg = &priv->stations[sta_id].tid[tid].agg;

		iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);

		/* check if BAR is needed */
		if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
			info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;

		if (txq->q.read_ptr != (scd_ssn & 0xff)) {
			index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
			IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
					"scd_ssn=%d idx=%d txq=%d swq=%d\n",
					scd_ssn , index, txq_id, txq->swq_id);

			freed = iwl_tx_queue_reclaim(priv, txq_id, index);
			iwl_free_tfds_in_queue(priv, sta_id, tid, freed);

			if (priv->mac80211_registered &&
			    (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
			    (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
				if (agg->state == IWL_AGG_OFF)
					iwl_wake_queue(priv, txq_id);
				else
					iwl_wake_queue(priv, txq->swq_id);
			}
		}
	} else {
		BUG_ON(txq_id != txq->swq_id);

		info->status.rates[0].count = tx_resp->failure_frame + 1;
		info->flags |= iwl_tx_status_to_mac80211(status);
		iwl_hwrate_to_tx_control(priv,
					le32_to_cpu(tx_resp->rate_n_flags),
					info);

		IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
				   "0x%x retries %d\n",
				   txq_id,
				   iwl_get_tx_fail_reason(status), status,
				   le32_to_cpu(tx_resp->rate_n_flags),
				   tx_resp->failure_frame);

		freed = iwl_tx_queue_reclaim(priv, txq_id, index);
		iwl_free_tfds_in_queue(priv, sta_id, tid, freed);

		if (priv->mac80211_registered &&
		    (iwl_queue_space(&txq->q) > txq->q.low_mark))
			iwl_wake_queue(priv, txq_id);
	}

	iwl_txq_check_empty(priv, sta_id, tid, txq_id);

	if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
		IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
}

void iwlagn_rx_handler_setup(struct iwl_priv *priv)
{
	/* init calibration handlers */
	priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
					iwlagn_rx_calib_result;
	priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
					iwlagn_rx_calib_complete;
	priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
}

void iwlagn_setup_deferred_work(struct iwl_priv *priv)
{
	/* in agn, the tx power calibration is done in uCode */
	priv->disable_tx_power_cal = 1;
}

int iwlagn_hw_valid_rtc_data_addr(u32 addr)
{
	return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
		(addr < IWLAGN_RTC_DATA_UPPER_BOUND);
}

int iwlagn_send_tx_power(struct iwl_priv *priv)
{
	struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
	u8 tx_ant_cfg_cmd;

	/* half dBm need to multiply */
	tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);

	if (priv->tx_power_lmt_in_half_dbm &&
	    priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
		/*
		 * For the newer devices which using enhanced/extend tx power
		 * table in EEPROM, the format is in half dBm. driver need to
		 * convert to dBm format before report to mac80211.
		 * By doing so, there is a possibility of 1/2 dBm resolution
		 * lost. driver will perform "round-up" operation before
		 * reporting, but it will cause 1/2 dBm tx power over the
		 * regulatory limit. Perform the checking here, if the
		 * "tx_power_user_lmt" is higher than EEPROM value (in
		 * half-dBm format), lower the tx power based on EEPROM
		 */
		tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
	}
	tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
	tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;

	if (IWL_UCODE_API(priv->ucode_ver) == 1)
		tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
	else
		tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;

	return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
				       sizeof(tx_power_cmd), &tx_power_cmd,
				       NULL);
}

void iwlagn_temperature(struct iwl_priv *priv)
{
	/* store temperature from statistics (in Celsius) */
	priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
	iwl_tt_handler(priv);
}

u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
{
	struct iwl_eeprom_calib_hdr {
		u8 version;
		u8 pa_type;
		u16 voltage;
	} *hdr;

	hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
							EEPROM_5000_CALIB_ALL);
	return hdr->version;

}

/*
 * EEPROM
 */
static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
{
	u16 offset = 0;

	if ((address & INDIRECT_ADDRESS) == 0)
		return address;

	switch (address & INDIRECT_TYPE_MSK) {
	case INDIRECT_HOST:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
		break;
	case INDIRECT_GENERAL:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
		break;
	case INDIRECT_REGULATORY:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
		break;
	case INDIRECT_CALIBRATION:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
		break;
	case INDIRECT_PROCESS_ADJST:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
		break;
	case INDIRECT_OTHERS:
		offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
		break;
	default:
		IWL_ERR(priv, "illegal indirect type: 0x%X\n",
		address & INDIRECT_TYPE_MSK);
		break;
	}

	/* translate the offset from words to byte */
	return (address & ADDRESS_MSK) + (offset << 1);
}

const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
					   size_t offset)
{
	u32 address = eeprom_indirect_address(priv, offset);
	BUG_ON(address >= priv->cfg->eeprom_size);
	return &priv->eeprom[address];
}

struct iwl_mod_params iwlagn_mod_params = {
	.amsdu_size_8K = 1,
	.restart_fw = 1,
	/* the rest are 0 by default */
};
Commit	Line	Data
e04ed0a5 WYG	1	/******************************************************************************
	2	*
	3	* GPL LICENSE SUMMARY
	4	*
	5	* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of version 2 of the GNU General Public License as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
	19	* USA
	20	*
	21	* The full GNU General Public License is included in this distribution
	22	* in the file called LICENSE.GPL.
	23	*
	24	* Contact Information:
	25	* Intel Linux Wireless <ilw@linux.intel.com>
	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*
	28	*****************************************************************************/
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
	32	#include <linux/init.h>
	33	#include <linux/sched.h>
	34
	35	#include "iwl-dev.h"
	36	#include "iwl-core.h"
	37	#include "iwl-io.h"
	38	#include "iwl-helpers.h"
	39	#include "iwl-agn-hw.h"
	40	#include "iwl-agn.h"
	41
	42	static inline u32 iwlagn_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
	43	{
	44	return le32_to_cpup((__le32 *)&tx_resp->status +
	45	tx_resp->frame_count) & MAX_SN;
	46	}
	47
	48	static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
	49	struct iwl_ht_agg *agg,
	50	struct iwl5000_tx_resp *tx_resp,
	51	int txq_id, u16 start_idx)
	52	{
	53	u16 status;
	54	struct agg_tx_status *frame_status = &tx_resp->status;
	55	struct ieee80211_tx_info *info = NULL;
	56	struct ieee80211_hdr *hdr = NULL;
	57	u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
	58	int i, sh, idx;
	59	u16 seq;
	60
	61	if (agg->wait_for_ba)
	62	IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
	63
	64	agg->frame_count = tx_resp->frame_count;
65	agg->start_idx = start_idx;
66	agg->rate_n_flags = rate_n_flags;
67	agg->bitmap = 0;
68
69	/* # frames attempted by Tx command */
70	if (agg->frame_count == 1) {
71	/* Only one frame was attempted; no block-ack will arrive */
72	status = le16_to_cpu(frame_status[0].status);
73	idx = start_idx;
74
75	/* FIXME: code repetition */
76	IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
77	agg->frame_count, agg->start_idx, idx);
78
79	info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
80	info->status.rates[0].count = tx_resp->failure_frame + 1;
81	info->flags &= ~IEEE80211_TX_CTL_AMPDU;
82	info->flags \|= iwl_tx_status_to_mac80211(status);
83	iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
84
85	/* FIXME: code repetition end */
86
87	IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
88	status & 0xff, tx_resp->failure_frame);
89	IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
90
91	agg->wait_for_ba = 0;
92	} else {
93	/* Two or more frames were attempted; expect block-ack */
94	u64 bitmap = 0;
95	int start = agg->start_idx;
96
97	/* Construct bit-map of pending frames within Tx window */
98	for (i = 0; i < agg->frame_count; i++) {
99	u16 sc;
100	status = le16_to_cpu(frame_status[i].status);
101	seq = le16_to_cpu(frame_status[i].sequence);
102	idx = SEQ_TO_INDEX(seq);
103	txq_id = SEQ_TO_QUEUE(seq);
104
105	if (status & (AGG_TX_STATE_FEW_BYTES_MSK \|
106	AGG_TX_STATE_ABORT_MSK))
107	continue;
108
109	IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
110	agg->frame_count, txq_id, idx);
111
112	hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
113	if (!hdr) {
114	IWL_ERR(priv,
115	"BUG_ON idx doesn't point to valid skb"
116	" idx=%d, txq_id=%d\n", idx, txq_id);
117	return -1;
118	}
119
120	sc = le16_to_cpu(hdr->seq_ctrl);
121	if (idx != (SEQ_TO_SN(sc) & 0xff)) {
122	IWL_ERR(priv,
123	"BUG_ON idx doesn't match seq control"
124	" idx=%d, seq_idx=%d, seq=%d\n",
125	idx, SEQ_TO_SN(sc),
126	hdr->seq_ctrl);
127	return -1;
128	}
129
130	IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
131	i, idx, SEQ_TO_SN(sc));
132
133	sh = idx - start;
134	if (sh > 64) {
135	sh = (start - idx) + 0xff;
136	bitmap = bitmap << sh;
137	sh = 0;
138	start = idx;
139	} else if (sh < -64)
140	sh = 0xff - (start - idx);
141	else if (sh < 0) {
142	sh = start - idx;
143	start = idx;
144	bitmap = bitmap << sh;
145	sh = 0;
146	}
147	bitmap \|= 1ULL << sh;
148	IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
149	start, (unsigned long long)bitmap);
150	}
151
152	agg->bitmap = bitmap;
153	agg->start_idx = start;
154	IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
155	agg->frame_count, agg->start_idx,
156	(unsigned long long)agg->bitmap);
157
158	if (bitmap)
159	agg->wait_for_ba = 1;
160	}
161	return 0;
162	}
163
164	static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
165	struct iwl_rx_mem_buffer *rxb)
166	{
167	struct iwl_rx_packet *pkt = rxb_addr(rxb);
168	u16 sequence = le16_to_cpu(pkt->hdr.sequence);
169	int txq_id = SEQ_TO_QUEUE(sequence);
170	int index = SEQ_TO_INDEX(sequence);
171	struct iwl_tx_queue *txq = &priv->txq[txq_id];
172	struct ieee80211_tx_info *info;
173	struct iwl5000_tx_resp tx_resp = (void )&pkt->u.raw[0];
174	u32 status = le16_to_cpu(tx_resp->status.status);
175	int tid;
176	int sta_id;
177	int freed;
178
179	if ((index >= txq->q.n_bd) \|\| (iwl_queue_used(&txq->q, index) == 0)) {
180	IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
181	"is out of range [0-%d] %d %d\n", txq_id,
182	index, txq->q.n_bd, txq->q.write_ptr,
183	txq->q.read_ptr);
184	return;
185	}
186
187	info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
188	memset(&info->status, 0, sizeof(info->status));
189
190	tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
191	sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
192
193	if (txq->sched_retry) {
194	const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
195	struct iwl_ht_agg *agg = NULL;
196
197	agg = &priv->stations[sta_id].tid[tid].agg;
198
199	iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
200
201	/* check if BAR is needed */
202	if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
203	info->flags \|= IEEE80211_TX_STAT_AMPDU_NO_BACK;
204
205	if (txq->q.read_ptr != (scd_ssn & 0xff)) {
206	index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
207	IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
208	"scd_ssn=%d idx=%d txq=%d swq=%d\n",
209	scd_ssn , index, txq_id, txq->swq_id);
210
211	freed = iwl_tx_queue_reclaim(priv, txq_id, index);
212	iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
213
214	if (priv->mac80211_registered &&
215	(iwl_queue_space(&txq->q) > txq->q.low_mark) &&
216	(agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
217	if (agg->state == IWL_AGG_OFF)
218	iwl_wake_queue(priv, txq_id);
219	else
220	iwl_wake_queue(priv, txq->swq_id);
221	}
222	}
223	} else {
224	BUG_ON(txq_id != txq->swq_id);
225
226	info->status.rates[0].count = tx_resp->failure_frame + 1;
227	info->flags \|= iwl_tx_status_to_mac80211(status);
228	iwl_hwrate_to_tx_control(priv,
229	le32_to_cpu(tx_resp->rate_n_flags),
230	info);
231
232	IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
233	"0x%x retries %d\n",
234	txq_id,
235	iwl_get_tx_fail_reason(status), status,
236	le32_to_cpu(tx_resp->rate_n_flags),
237	tx_resp->failure_frame);
238
239	freed = iwl_tx_queue_reclaim(priv, txq_id, index);
240	iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
241
242	if (priv->mac80211_registered &&
243	(iwl_queue_space(&txq->q) > txq->q.low_mark))
244	iwl_wake_queue(priv, txq_id);
245	}
246
247	iwl_txq_check_empty(priv, sta_id, tid, txq_id);
248
249	if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
250	IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
251	}
252
253	void iwlagn_rx_handler_setup(struct iwl_priv *priv)
254	{
255	/* init calibration handlers */
256	priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
257	iwlagn_rx_calib_result;
258	priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
259	iwlagn_rx_calib_complete;
260	priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
261	}
262
263	void iwlagn_setup_deferred_work(struct iwl_priv *priv)
264	{
265	/* in agn, the tx power calibration is done in uCode */
266	priv->disable_tx_power_cal = 1;
267	}
268
269	int iwlagn_hw_valid_rtc_data_addr(u32 addr)
270	{
271	return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
272	(addr < IWLAGN_RTC_DATA_UPPER_BOUND);
273	}
274
275	int iwlagn_send_tx_power(struct iwl_priv *priv)
276	{
277	struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
278	u8 tx_ant_cfg_cmd;
279
280	/* half dBm need to multiply */
281	tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
282
283	if (priv->tx_power_lmt_in_half_dbm &&
284	priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
285	/*
286	* For the newer devices which using enhanced/extend tx power
287	* table in EEPROM, the format is in half dBm. driver need to
288	* convert to dBm format before report to mac80211.
289	* By doing so, there is a possibility of 1/2 dBm resolution
290	* lost. driver will perform "round-up" operation before
291	* reporting, but it will cause 1/2 dBm tx power over the
292	* regulatory limit. Perform the checking here, if the
293	* "tx_power_user_lmt" is higher than EEPROM value (in
294	* half-dBm format), lower the tx power based on EEPROM
295	*/
296	tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
297	}
298	tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
299	tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
300
301	if (IWL_UCODE_API(priv->ucode_ver) == 1)
302	tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
303	else
304	tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
305
306	return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
307	sizeof(tx_power_cmd), &tx_power_cmd,
308	NULL);
309	}
310
311	void iwlagn_temperature(struct iwl_priv *priv)
312	{
313	/* store temperature from statistics (in Celsius) */
314	priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
315	iwl_tt_handler(priv);
316	}
317
318	u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
319	{
320	struct iwl_eeprom_calib_hdr {
321	u8 version;
322	u8 pa_type;
323	u16 voltage;
324	} *hdr;
325
326	hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
327	EEPROM_5000_CALIB_ALL);
328	return hdr->version;
329
330	}
331
332	/*
333	* EEPROM
334	*/
335	static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
336	{
337	u16 offset = 0;
338
339	if ((address & INDIRECT_ADDRESS) == 0)
340	return address;
341
342	switch (address & INDIRECT_TYPE_MSK) {
343	case INDIRECT_HOST:
344	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
345	break;
346	case INDIRECT_GENERAL:
347	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
348	break;
349	case INDIRECT_REGULATORY:
350	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
351	break;
352	case INDIRECT_CALIBRATION:
353	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
354	break;
355	case INDIRECT_PROCESS_ADJST:
356	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
357	break;
358	case INDIRECT_OTHERS:
359	offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
360	break;
361	default:
362	IWL_ERR(priv, "illegal indirect type: 0x%X\n",
363	address & INDIRECT_TYPE_MSK);
364	break;
365	}
366
367	/* translate the offset from words to byte */
368	return (address & ADDRESS_MSK) + (offset << 1);
369	}
370
371	const u8 iwlagn_eeprom_query_addr(const struct iwl_priv priv,
372	size_t offset)
373	{
374	u32 address = eeprom_indirect_address(priv, offset);
375	BUG_ON(address >= priv->cfg->eeprom_size);
376	return &priv->eeprom[address];
377	}
348ee7cd WYG	378
	379	struct iwl_mod_params iwlagn_mod_params = {
	380	.amsdu_size_8K = 1,
	381	.restart_fw = 1,
	382	/* the rest are 0 by default */
	383	};