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iwlwifi: remove debug frame dumping
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
CommitLineData
e04ed0a5
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
8d801080 29#include <linux/etherdevice.h>
e04ed0a5
WYG		 30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
33#include <linux/sched.h>
34
35#include "iwl-dev.h"
36#include "iwl-core.h"
37#include "iwl-io.h"
38#include "iwl-helpers.h"
39#include "iwl-agn-hw.h"
40#include "iwl-agn.h"
1fa61b2e 41#include "iwl-sta.h"
e04ed0a5
WYG		 42
43static inline u32 iwlagn_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
44{
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47}
48
49static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
50 struct iwl_ht_agg *agg,
51 struct iwl5000_tx_resp *tx_resp,
52 int txq_id, u16 start_idx)
53{
54 u16 status;
55 struct agg_tx_status *frame_status = &tx_resp->status;
56 struct ieee80211_tx_info *info = NULL;
57 struct ieee80211_hdr *hdr = NULL;
58 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
59 int i, sh, idx;
60 u16 seq;
61
62 if (agg->wait_for_ba)
63 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
64
65 agg->frame_count = tx_resp->frame_count;
66 agg->start_idx = start_idx;
67 agg->rate_n_flags = rate_n_flags;
68 agg->bitmap = 0;
69
70 /* # frames attempted by Tx command */
71 if (agg->frame_count == 1) {
72 /* Only one frame was attempted; no block-ack will arrive */
73 status = le16_to_cpu(frame_status[0].status);
74 idx = start_idx;
75
76 /* FIXME: code repetition */
77 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
78 agg->frame_count, agg->start_idx, idx);
79
80 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
81 info->status.rates[0].count = tx_resp->failure_frame + 1;
82 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
83 info->flags |= iwl_tx_status_to_mac80211(status);
8d801080 84 iwlagn_hwrate_to_tx_control(priv, rate_n_flags, info);
e04ed0a5
WYG		 85
86 /* FIXME: code repetition end */
87
88 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
89 status & 0xff, tx_resp->failure_frame);
90 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
91
92 agg->wait_for_ba = 0;
93 } else {
94 /* Two or more frames were attempted; expect block-ack */
95 u64 bitmap = 0;
96 int start = agg->start_idx;
97
98 /* Construct bit-map of pending frames within Tx window */
99 for (i = 0; i < agg->frame_count; i++) {
100 u16 sc;
101 status = le16_to_cpu(frame_status[i].status);
102 seq = le16_to_cpu(frame_status[i].sequence);
103 idx = SEQ_TO_INDEX(seq);
104 txq_id = SEQ_TO_QUEUE(seq);
105
106 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
107 AGG_TX_STATE_ABORT_MSK))
108 continue;
109
110 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
111 agg->frame_count, txq_id, idx);
112
113 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
114 if (!hdr) {
115 IWL_ERR(priv,
116 "BUG_ON idx doesn't point to valid skb"
117 " idx=%d, txq_id=%d\n", idx, txq_id);
118 return -1;
119 }
120
121 sc = le16_to_cpu(hdr->seq_ctrl);
122 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
123 IWL_ERR(priv,
124 "BUG_ON idx doesn't match seq control"
125 " idx=%d, seq_idx=%d, seq=%d\n",
126 idx, SEQ_TO_SN(sc),
127 hdr->seq_ctrl);
128 return -1;
129 }
130
131 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
132 i, idx, SEQ_TO_SN(sc));
133
134 sh = idx - start;
135 if (sh > 64) {
136 sh = (start - idx) + 0xff;
137 bitmap = bitmap << sh;
138 sh = 0;
139 start = idx;
140 } else if (sh < -64)
141 sh = 0xff - (start - idx);
142 else if (sh < 0) {
143 sh = start - idx;
144 start = idx;
145 bitmap = bitmap << sh;
146 sh = 0;
147 }
148 bitmap |= 1ULL << sh;
149 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
150 start, (unsigned long long)bitmap);
151 }
152
153 agg->bitmap = bitmap;
154 agg->start_idx = start;
155 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
156 agg->frame_count, agg->start_idx,
157 (unsigned long long)agg->bitmap);
158
159 if (bitmap)
160 agg->wait_for_ba = 1;
161 }
162 return 0;
163}
164
04569cbe
WYG		 165void iwl_check_abort_status(struct iwl_priv *priv,
166 u8 frame_count, u32 status)
167{
168 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
169 IWL_ERR(priv, "TODO: Implement Tx flush command!!!\n");
170 }
171}
172
e04ed0a5
WYG		 173static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
174 struct iwl_rx_mem_buffer *rxb)
175{
176 struct iwl_rx_packet *pkt = rxb_addr(rxb);
177 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
178 int txq_id = SEQ_TO_QUEUE(sequence);
179 int index = SEQ_TO_INDEX(sequence);
180 struct iwl_tx_queue *txq = &priv->txq[txq_id];
181 struct ieee80211_tx_info *info;
182 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
183 u32 status = le16_to_cpu(tx_resp->status.status);
184 int tid;
185 int sta_id;
186 int freed;
9c5ac091 187 unsigned long flags;
e04ed0a5
WYG		 188
189 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
190 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
191 "is out of range [0-%d] %d %d\n", txq_id,
192 index, txq->q.n_bd, txq->q.write_ptr,
193 txq->q.read_ptr);
194 return;
195 }
196
197 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
198 memset(&info->status, 0, sizeof(info->status));
199
200 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
201 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
202
9c5ac091 203 spin_lock_irqsave(&priv->sta_lock, flags);
e04ed0a5
WYG		 204 if (txq->sched_retry) {
205 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
9c5ac091 206 struct iwl_ht_agg *agg;
e04ed0a5
WYG		 207
208 agg = &priv->stations[sta_id].tid[tid].agg;
209
210 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
211
212 /* check if BAR is needed */
213 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
214 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
215
216 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
217 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
218 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
219 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
220 scd_ssn , index, txq_id, txq->swq_id);
221
74bcdb33 222 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
e04ed0a5
WYG		 223 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
224
225 if (priv->mac80211_registered &&
226 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
227 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
228 if (agg->state == IWL_AGG_OFF)
229 iwl_wake_queue(priv, txq_id);
230 else
231 iwl_wake_queue(priv, txq->swq_id);
232 }
233 }
234 } else {
235 BUG_ON(txq_id != txq->swq_id);
236
237 info->status.rates[0].count = tx_resp->failure_frame + 1;
238 info->flags |= iwl_tx_status_to_mac80211(status);
8d801080 239 iwlagn_hwrate_to_tx_control(priv,
e04ed0a5
WYG		 240 le32_to_cpu(tx_resp->rate_n_flags),
241 info);
242
243 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
244 "0x%x retries %d\n",
245 txq_id,
246 iwl_get_tx_fail_reason(status), status,
247 le32_to_cpu(tx_resp->rate_n_flags),
248 tx_resp->failure_frame);
249
74bcdb33 250 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
e04ed0a5
WYG		 251 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
252
253 if (priv->mac80211_registered &&
254 (iwl_queue_space(&txq->q) > txq->q.low_mark))
255 iwl_wake_queue(priv, txq_id);
256 }
257
74bcdb33 258 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
e04ed0a5 259
04569cbe 260 iwl_check_abort_status(priv, tx_resp->frame_count, status);
9c5ac091 261 spin_unlock_irqrestore(&priv->sta_lock, flags);
e04ed0a5
WYG		 262}
263
264void iwlagn_rx_handler_setup(struct iwl_priv *priv)
265{
266 /* init calibration handlers */
267 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
268 iwlagn_rx_calib_result;
269 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
270 iwlagn_rx_calib_complete;
271 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
272}
273
274void iwlagn_setup_deferred_work(struct iwl_priv *priv)
275{
276 /* in agn, the tx power calibration is done in uCode */
277 priv->disable_tx_power_cal = 1;
278}
279
280int iwlagn_hw_valid_rtc_data_addr(u32 addr)
281{
282 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
283 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
284}
285
286int iwlagn_send_tx_power(struct iwl_priv *priv)
287{
288 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
289 u8 tx_ant_cfg_cmd;
290
291 /* half dBm need to multiply */
292 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
293
294 if (priv->tx_power_lmt_in_half_dbm &&
295 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
296 /*
297 * For the newer devices which using enhanced/extend tx power
298 * table in EEPROM, the format is in half dBm. driver need to
299 * convert to dBm format before report to mac80211.
300 * By doing so, there is a possibility of 1/2 dBm resolution
301 * lost. driver will perform "round-up" operation before
302 * reporting, but it will cause 1/2 dBm tx power over the
303 * regulatory limit. Perform the checking here, if the
304 * "tx_power_user_lmt" is higher than EEPROM value (in
305 * half-dBm format), lower the tx power based on EEPROM
306 */
307 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
308 }
309 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
310 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
311
312 if (IWL_UCODE_API(priv->ucode_ver) == 1)
313 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
314 else
315 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
316
317 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
318 sizeof(tx_power_cmd), &tx_power_cmd,
319 NULL);
320}
321
322void iwlagn_temperature(struct iwl_priv *priv)
323{
324 /* store temperature from statistics (in Celsius) */
2daf6c15 325 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
e04ed0a5
WYG		 326 iwl_tt_handler(priv);
327}
328
329u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
330{
331 struct iwl_eeprom_calib_hdr {
332 u8 version;
333 u8 pa_type;
334 u16 voltage;
335 } *hdr;
336
337 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
7944f8e4 338 EEPROM_CALIB_ALL);
e04ed0a5
WYG		 339 return hdr->version;
340
341}
342
343/*
344 * EEPROM
345 */
346static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
347{
348 u16 offset = 0;
349
350 if ((address & INDIRECT_ADDRESS) == 0)
351 return address;
352
353 switch (address & INDIRECT_TYPE_MSK) {
354 case INDIRECT_HOST:
7944f8e4 355 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
e04ed0a5
WYG		 356 break;
357 case INDIRECT_GENERAL:
7944f8e4 358 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
e04ed0a5
WYG		 359 break;
360 case INDIRECT_REGULATORY:
7944f8e4 361 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
e04ed0a5
WYG		 362 break;
363 case INDIRECT_CALIBRATION:
7944f8e4 364 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
e04ed0a5
WYG		 365 break;
366 case INDIRECT_PROCESS_ADJST:
7944f8e4 367 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
e04ed0a5
WYG		 368 break;
369 case INDIRECT_OTHERS:
7944f8e4 370 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
e04ed0a5
WYG		 371 break;
372 default:
373 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
374 address & INDIRECT_TYPE_MSK);
375 break;
376 }
377
378 /* translate the offset from words to byte */
379 return (address & ADDRESS_MSK) + (offset << 1);
380}
381
382const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
383 size_t offset)
384{
385 u32 address = eeprom_indirect_address(priv, offset);
386 BUG_ON(address >= priv->cfg->eeprom_size);
387 return &priv->eeprom[address];
388}
348ee7cd
WYG		 389
390struct iwl_mod_params iwlagn_mod_params = {
391 .amsdu_size_8K = 1,
392 .restart_fw = 1,
393 /* the rest are 0 by default */
394};
74bcdb33
WYG		 395
396void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
397{
398 unsigned long flags;
399 int i;
400 spin_lock_irqsave(&rxq->lock, flags);
401 INIT_LIST_HEAD(&rxq->rx_free);
402 INIT_LIST_HEAD(&rxq->rx_used);
403 /* Fill the rx_used queue with _all_ of the Rx buffers */
404 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
405 /* In the reset function, these buffers may have been allocated
406 * to an SKB, so we need to unmap and free potential storage */
407 if (rxq->pool[i].page != NULL) {
408 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
409 PAGE_SIZE << priv->hw_params.rx_page_order,
410 PCI_DMA_FROMDEVICE);
411 __iwl_free_pages(priv, rxq->pool[i].page);
412 rxq->pool[i].page = NULL;
413 }
414 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
415 }
416
6aac74b4
ZY		 417 for (i = 0; i < RX_QUEUE_SIZE; i++)
418 rxq->queue[i] = NULL;
419
74bcdb33
WYG		 420 /* Set us so that we have processed and used all buffers, but have
421 * not restocked the Rx queue with fresh buffers */
422 rxq->read = rxq->write = 0;
423 rxq->write_actual = 0;
424 rxq->free_count = 0;
425 spin_unlock_irqrestore(&rxq->lock, flags);
426}
427
428int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
429{
430 u32 rb_size;
431 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
432 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
433
434 if (!priv->cfg->use_isr_legacy)
435 rb_timeout = RX_RB_TIMEOUT;
436
437 if (priv->cfg->mod_params->amsdu_size_8K)
438 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
439 else
440 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
441
442 /* Stop Rx DMA */
443 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
444
445 /* Reset driver's Rx queue write index */
446 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
447
448 /* Tell device where to find RBD circular buffer in DRAM */
449 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
450 (u32)(rxq->dma_addr >> 8));
451
452 /* Tell device where in DRAM to update its Rx status */
453 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
454 rxq->rb_stts_dma >> 4);
455
456 /* Enable Rx DMA
457 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
458 * the credit mechanism in 5000 HW RX FIFO
459 * Direct rx interrupts to hosts
460 * Rx buffer size 4 or 8k
461 * RB timeout 0x10
462 * 256 RBDs
463 */
464 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
465 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
466 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
467 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
468 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
469 rb_size|
470 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
471 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
472
473 /* Set interrupt coalescing timer to default (2048 usecs) */
474 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
475
476 return 0;
477}
478
479int iwlagn_hw_nic_init(struct iwl_priv *priv)
480{
481 unsigned long flags;
482 struct iwl_rx_queue *rxq = &priv->rxq;
483 int ret;
484
485 /* nic_init */
486 spin_lock_irqsave(&priv->lock, flags);
487 priv->cfg->ops->lib->apm_ops.init(priv);
488
489 /* Set interrupt coalescing calibration timer to default (512 usecs) */
490 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
491
492 spin_unlock_irqrestore(&priv->lock, flags);
493
494 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
495
496 priv->cfg->ops->lib->apm_ops.config(priv);
497
498 /* Allocate the RX queue, or reset if it is already allocated */
499 if (!rxq->bd) {
500 ret = iwl_rx_queue_alloc(priv);
501 if (ret) {
502 IWL_ERR(priv, "Unable to initialize Rx queue\n");
503 return -ENOMEM;
504 }
505 } else
506 iwlagn_rx_queue_reset(priv, rxq);
507
54b81550 508 iwlagn_rx_replenish(priv);
74bcdb33
WYG		 509
510 iwlagn_rx_init(priv, rxq);
511
512 spin_lock_irqsave(&priv->lock, flags);
513
514 rxq->need_update = 1;
515 iwl_rx_queue_update_write_ptr(priv, rxq);
516
517 spin_unlock_irqrestore(&priv->lock, flags);
518
470058e0
ZY		 519 /* Allocate or reset and init all Tx and Command queues */
520 if (!priv->txq) {
521 ret = iwlagn_txq_ctx_alloc(priv);
522 if (ret)
523 return ret;
524 } else
525 iwlagn_txq_ctx_reset(priv);
74bcdb33
WYG		 526
527 set_bit(STATUS_INIT, &priv->status);
528
529 return 0;
530}
54b81550
WYG		 531
532/**
533 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
534 */
535static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
536 dma_addr_t dma_addr)
537{
538 return cpu_to_le32((u32)(dma_addr >> 8));
539}
540
541/**
542 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
543 *
544 * If there are slots in the RX queue that need to be restocked,
545 * and we have free pre-allocated buffers, fill the ranks as much
546 * as we can, pulling from rx_free.
547 *
548 * This moves the 'write' index forward to catch up with 'processed', and
549 * also updates the memory address in the firmware to reference the new
550 * target buffer.
551 */
552void iwlagn_rx_queue_restock(struct iwl_priv *priv)
553{
554 struct iwl_rx_queue *rxq = &priv->rxq;
555 struct list_head *element;
556 struct iwl_rx_mem_buffer *rxb;
557 unsigned long flags;
54b81550
WYG		 558
559 spin_lock_irqsave(&rxq->lock, flags);
54b81550 560 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
6aac74b4
ZY		 561 /* The overwritten rxb must be a used one */
562 rxb = rxq->queue[rxq->write];
563 BUG_ON(rxb && rxb->page);
564
54b81550
WYG		 565 /* Get next free Rx buffer, remove from free list */
566 element = rxq->rx_free.next;
567 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
568 list_del(element);
569
570 /* Point to Rx buffer via next RBD in circular buffer */
571 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
572 rxb->page_dma);
573 rxq->queue[rxq->write] = rxb;
574 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
575 rxq->free_count--;
576 }
577 spin_unlock_irqrestore(&rxq->lock, flags);
578 /* If the pre-allocated buffer pool is dropping low, schedule to
579 * refill it */
580 if (rxq->free_count <= RX_LOW_WATERMARK)
581 queue_work(priv->workqueue, &priv->rx_replenish);
582
583
584 /* If we've added more space for the firmware to place data, tell it.
585 * Increment device's write pointer in multiples of 8. */
586 if (rxq->write_actual != (rxq->write & ~0x7)) {
587 spin_lock_irqsave(&rxq->lock, flags);
588 rxq->need_update = 1;
589 spin_unlock_irqrestore(&rxq->lock, flags);
590 iwl_rx_queue_update_write_ptr(priv, rxq);
591 }
592}
593
594/**
595 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
596 *
597 * When moving to rx_free an SKB is allocated for the slot.
598 *
599 * Also restock the Rx queue via iwl_rx_queue_restock.
600 * This is called as a scheduled work item (except for during initialization)
601 */
602void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
603{
604 struct iwl_rx_queue *rxq = &priv->rxq;
605 struct list_head *element;
606 struct iwl_rx_mem_buffer *rxb;
607 struct page *page;
608 unsigned long flags;
609 gfp_t gfp_mask = priority;
610
611 while (1) {
612 spin_lock_irqsave(&rxq->lock, flags);
613 if (list_empty(&rxq->rx_used)) {
614 spin_unlock_irqrestore(&rxq->lock, flags);
615 return;
616 }
617 spin_unlock_irqrestore(&rxq->lock, flags);
618
619 if (rxq->free_count > RX_LOW_WATERMARK)
620 gfp_mask |= __GFP_NOWARN;
621
622 if (priv->hw_params.rx_page_order > 0)
623 gfp_mask |= __GFP_COMP;
624
625 /* Alloc a new receive buffer */
626 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
627 if (!page) {
628 if (net_ratelimit())
629 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
630 "order: %d\n",
631 priv->hw_params.rx_page_order);
632
633 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
634 net_ratelimit())
635 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
636 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
637 rxq->free_count);
638 /* We don't reschedule replenish work here -- we will
639 * call the restock method and if it still needs
640 * more buffers it will schedule replenish */
641 return;
642 }
643
644 spin_lock_irqsave(&rxq->lock, flags);
645
646 if (list_empty(&rxq->rx_used)) {
647 spin_unlock_irqrestore(&rxq->lock, flags);
648 __free_pages(page, priv->hw_params.rx_page_order);
649 return;
650 }
651 element = rxq->rx_used.next;
652 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
653 list_del(element);
654
655 spin_unlock_irqrestore(&rxq->lock, flags);
656
6aac74b4 657 BUG_ON(rxb->page);
54b81550
WYG		 658 rxb->page = page;
659 /* Get physical address of the RB */
660 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
661 PAGE_SIZE << priv->hw_params.rx_page_order,
662 PCI_DMA_FROMDEVICE);
663 /* dma address must be no more than 36 bits */
664 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
665 /* and also 256 byte aligned! */
666 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
667
668 spin_lock_irqsave(&rxq->lock, flags);
669
670 list_add_tail(&rxb->list, &rxq->rx_free);
671 rxq->free_count++;
672 priv->alloc_rxb_page++;
673
674 spin_unlock_irqrestore(&rxq->lock, flags);
675 }
676}
677
678void iwlagn_rx_replenish(struct iwl_priv *priv)
679{
680 unsigned long flags;
681
682 iwlagn_rx_allocate(priv, GFP_KERNEL);
683
684 spin_lock_irqsave(&priv->lock, flags);
685 iwlagn_rx_queue_restock(priv);
686 spin_unlock_irqrestore(&priv->lock, flags);
687}
688
689void iwlagn_rx_replenish_now(struct iwl_priv *priv)
690{
691 iwlagn_rx_allocate(priv, GFP_ATOMIC);
692
693 iwlagn_rx_queue_restock(priv);
694}
695
696/* Assumes that the skb field of the buffers in 'pool' is kept accurate.
697 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
698 * This free routine walks the list of POOL entries and if SKB is set to
699 * non NULL it is unmapped and freed
700 */
701void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
702{
703 int i;
704 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
705 if (rxq->pool[i].page != NULL) {
706 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
707 PAGE_SIZE << priv->hw_params.rx_page_order,
708 PCI_DMA_FROMDEVICE);
709 __iwl_free_pages(priv, rxq->pool[i].page);
710 rxq->pool[i].page = NULL;
711 }
712 }
713
714 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
715 rxq->dma_addr);
716 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
717 rxq->rb_stts, rxq->rb_stts_dma);
718 rxq->bd = NULL;
719 rxq->rb_stts = NULL;
720}
721
722int iwlagn_rxq_stop(struct iwl_priv *priv)
723{
724
725 /* stop Rx DMA */
726 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
727 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
728 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
729
730 return 0;
731}
8d801080
WYG		 732
733int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
734{
735 int idx = 0;
736 int band_offset = 0;
737
738 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
739 if (rate_n_flags & RATE_MCS_HT_MSK) {
740 idx = (rate_n_flags & 0xff);
741 return idx;
742 /* Legacy rate format, search for match in table */
743 } else {
744 if (band == IEEE80211_BAND_5GHZ)
745 band_offset = IWL_FIRST_OFDM_RATE;
746 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
747 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
748 return idx - band_offset;
749 }
750
751 return -1;
752}
753
754/* Calc max signal level (dBm) among 3 possible receivers */
755static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
756 struct iwl_rx_phy_res *rx_resp)
757{
758 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
759}
760
8d801080
WYG		 761static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
762{
763 u32 decrypt_out = 0;
764
765 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
766 RX_RES_STATUS_STATION_FOUND)
767 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
768 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
769
770 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
771
772 /* packet was not encrypted */
773 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
774 RX_RES_STATUS_SEC_TYPE_NONE)
775 return decrypt_out;
776
777 /* packet was encrypted with unknown alg */
778 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
779 RX_RES_STATUS_SEC_TYPE_ERR)
780 return decrypt_out;
781
782 /* decryption was not done in HW */
783 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
784 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
785 return decrypt_out;
786
787 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
788
789 case RX_RES_STATUS_SEC_TYPE_CCMP:
790 /* alg is CCM: check MIC only */
791 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
792 /* Bad MIC */
793 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
794 else
795 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
796
797 break;
798
799 case RX_RES_STATUS_SEC_TYPE_TKIP:
800 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
801 /* Bad TTAK */
802 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
803 break;
804 }
805 /* fall through if TTAK OK */
806 default:
807 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
808 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
809 else
810 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
811 break;
ee289b64 812 }
8d801080
WYG		 813
814 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
815 decrypt_in, decrypt_out);
816
817 return decrypt_out;
818}
819
820static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
821 struct ieee80211_hdr *hdr,
822 u16 len,
823 u32 ampdu_status,
824 struct iwl_rx_mem_buffer *rxb,
825 struct ieee80211_rx_status *stats)
826{
827 struct sk_buff *skb;
8d801080
WYG		 828 __le16 fc = hdr->frame_control;
829
830 /* We only process data packets if the interface is open */
831 if (unlikely(!priv->is_open)) {
832 IWL_DEBUG_DROP_LIMIT(priv,
833 "Dropping packet while interface is not open.\n");
834 return;
835 }
836
837 /* In case of HW accelerated crypto and bad decryption, drop */
838 if (!priv->cfg->mod_params->sw_crypto &&
839 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
840 return;
841
ecdf94b8 842 skb = dev_alloc_skb(128);
8d801080 843 if (!skb) {
ecdf94b8 844 IWL_ERR(priv, "dev_alloc_skb failed\n");
8d801080
WYG		 845 return;
846 }
847
8d801080
WYG		 848 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
849
8d801080
WYG		 850 iwl_update_stats(priv, false, fc, len);
851 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
852
853 ieee80211_rx(priv->hw, skb);
8d801080
WYG		 854 priv->alloc_rxb_page--;
855 rxb->page = NULL;
856}
857
858/* Called for REPLY_RX (legacy ABG frames), or
859 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
860void iwlagn_rx_reply_rx(struct iwl_priv *priv,
861 struct iwl_rx_mem_buffer *rxb)
862{
863 struct ieee80211_hdr *header;
864 struct ieee80211_rx_status rx_status;
865 struct iwl_rx_packet *pkt = rxb_addr(rxb);
866 struct iwl_rx_phy_res *phy_res;
867 __le32 rx_pkt_status;
868 struct iwl4965_rx_mpdu_res_start *amsdu;
869 u32 len;
870 u32 ampdu_status;
871 u32 rate_n_flags;
872
873 /**
874 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
875 * REPLY_RX: physical layer info is in this buffer
876 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
877 * command and cached in priv->last_phy_res
878 *
879 * Here we set up local variables depending on which command is
880 * received.
881 */
882 if (pkt->hdr.cmd == REPLY_RX) {
883 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
884 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
885 + phy_res->cfg_phy_cnt);
886
887 len = le16_to_cpu(phy_res->byte_count);
888 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
889 phy_res->cfg_phy_cnt + len);
890 ampdu_status = le32_to_cpu(rx_pkt_status);
891 } else {
05d57520 892 if (!priv->_agn.last_phy_res_valid) {
8d801080
WYG		 893 IWL_ERR(priv, "MPDU frame without cached PHY data\n");
894 return;
895 }
05d57520 896 phy_res = &priv->_agn.last_phy_res;
8d801080
WYG		 897 amsdu = (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
898 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
899 len = le16_to_cpu(amsdu->byte_count);
900 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
901 ampdu_status = iwlagn_translate_rx_status(priv,
902 le32_to_cpu(rx_pkt_status));
903 }
904
905 if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
906 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
907 phy_res->cfg_phy_cnt);
908 return;
909 }
910
911 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
912 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
913 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
914 le32_to_cpu(rx_pkt_status));
915 return;
916 }
917
918 /* This will be used in several places later */
919 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
920
921 /* rx_status carries information about the packet to mac80211 */
922 rx_status.mactime = le64_to_cpu(phy_res->timestamp);
923 rx_status.freq =
924 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
925 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
926 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
927 rx_status.rate_idx =
928 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
929 rx_status.flag = 0;
930
931 /* TSF isn't reliable. In order to allow smooth user experience,
932 * this W/A doesn't propagate it to the mac80211 */
933 /*rx_status.flag |= RX_FLAG_TSFT;*/
934
935 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
936
937 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
938 rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
939
8d801080 940 iwl_dbg_log_rx_data_frame(priv, len, header);
ed1b6e99
JB		 941 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
942 rx_status.signal, (unsigned long long)rx_status.mactime);
8d801080
WYG		 943
944 /*
945 * "antenna number"
946 *
947 * It seems that the antenna field in the phy flags value
948 * is actually a bit field. This is undefined by radiotap,
949 * it wants an actual antenna number but I always get "7"
950 * for most legacy frames I receive indicating that the
951 * same frame was received on all three RX chains.
952 *
953 * I think this field should be removed in favor of a
954 * new 802.11n radiotap field "RX chains" that is defined
955 * as a bitmask.
956 */
957 rx_status.antenna =
958 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
959 >> RX_RES_PHY_FLAGS_ANTENNA_POS;
960
961 /* set the preamble flag if appropriate */
962 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
963 rx_status.flag |= RX_FLAG_SHORTPRE;
964
965 /* Set up the HT phy flags */
966 if (rate_n_flags & RATE_MCS_HT_MSK)
967 rx_status.flag |= RX_FLAG_HT;
968 if (rate_n_flags & RATE_MCS_HT40_MSK)
969 rx_status.flag |= RX_FLAG_40MHZ;
970 if (rate_n_flags & RATE_MCS_SGI_MSK)
971 rx_status.flag |= RX_FLAG_SHORT_GI;
972
973 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
974 rxb, &rx_status);
975}
976
977/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
978 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
979void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
05d57520 980 struct iwl_rx_mem_buffer *rxb)
8d801080
WYG		 981{
982 struct iwl_rx_packet *pkt = rxb_addr(rxb);
05d57520
JB		 983 priv->_agn.last_phy_res_valid = true;
984 memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
8d801080
WYG		 985 sizeof(struct iwl_rx_phy_res));
986}
b6e4c55a
JB		 987
988static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
1dda6d28
JB		 989 struct ieee80211_vif *vif,
990 enum ieee80211_band band,
991 struct iwl_scan_channel *scan_ch)
b6e4c55a
JB		 992{
993 const struct ieee80211_supported_band *sband;
994 const struct iwl_channel_info *ch_info;
995 u16 passive_dwell = 0;
996 u16 active_dwell = 0;
997 int i, added = 0;
998 u16 channel = 0;
999
1000 sband = iwl_get_hw_mode(priv, band);
1001 if (!sband) {
1002 IWL_ERR(priv, "invalid band\n");
1003 return added;
1004 }
1005
1006 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1dda6d28 1007 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
b6e4c55a
JB		 1008
1009 if (passive_dwell <= active_dwell)
1010 passive_dwell = active_dwell + 1;
1011
1012 /* only scan single channel, good enough to reset the RF */
1013 /* pick the first valid not in-use channel */
1014 if (band == IEEE80211_BAND_5GHZ) {
1015 for (i = 14; i < priv->channel_count; i++) {
1016 if (priv->channel_info[i].channel !=
1017 le16_to_cpu(priv->staging_rxon.channel)) {
1018 channel = priv->channel_info[i].channel;
1019 ch_info = iwl_get_channel_info(priv,
1020 band, channel);
1021 if (is_channel_valid(ch_info))
1022 break;
1023 }
1024 }
1025 } else {
1026 for (i = 0; i < 14; i++) {
1027 if (priv->channel_info[i].channel !=
1028 le16_to_cpu(priv->staging_rxon.channel)) {
1029 channel =
1030 priv->channel_info[i].channel;
1031 ch_info = iwl_get_channel_info(priv,
1032 band, channel);
1033 if (is_channel_valid(ch_info))
1034 break;
1035 }
1036 }
1037 }
1038 if (channel) {
1039 scan_ch->channel = cpu_to_le16(channel);
1040 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1041 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1042 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1043 /* Set txpower levels to defaults */
1044 scan_ch->dsp_atten = 110;
1045 if (band == IEEE80211_BAND_5GHZ)
1046 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1047 else
1048 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1049 added++;
1050 } else
1051 IWL_ERR(priv, "no valid channel found\n");
1052 return added;
1053}
1054
1055static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1dda6d28 1056 struct ieee80211_vif *vif,
b6e4c55a
JB		 1057 enum ieee80211_band band,
1058 u8 is_active, u8 n_probes,
1059 struct iwl_scan_channel *scan_ch)
1060{
1061 struct ieee80211_channel *chan;
1062 const struct ieee80211_supported_band *sband;
1063 const struct iwl_channel_info *ch_info;
1064 u16 passive_dwell = 0;
1065 u16 active_dwell = 0;
1066 int added, i;
1067 u16 channel;
1068
1069 sband = iwl_get_hw_mode(priv, band);
1070 if (!sband)
1071 return 0;
1072
1073 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1dda6d28 1074 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
b6e4c55a
JB		 1075
1076 if (passive_dwell <= active_dwell)
1077 passive_dwell = active_dwell + 1;
1078
1079 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1080 chan = priv->scan_request->channels[i];
1081
1082 if (chan->band != band)
1083 continue;
1084
1085 channel = ieee80211_frequency_to_channel(chan->center_freq);
1086 scan_ch->channel = cpu_to_le16(channel);
1087
1088 ch_info = iwl_get_channel_info(priv, band, channel);
1089 if (!is_channel_valid(ch_info)) {
1090 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1091 channel);
1092 continue;
1093 }
1094
1095 if (!is_active || is_channel_passive(ch_info) ||
1096 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1097 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1098 else
1099 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1100
1101 if (n_probes)
1102 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1103
1104 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1105 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1106
1107 /* Set txpower levels to defaults */
1108 scan_ch->dsp_atten = 110;
1109
1110 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1111 * power level:
1112 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1113 */
1114 if (band == IEEE80211_BAND_5GHZ)
1115 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1116 else
1117 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1118
1119 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1120 channel, le32_to_cpu(scan_ch->type),
1121 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1122 "ACTIVE" : "PASSIVE",
1123 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1124 active_dwell : passive_dwell);
1125
1126 scan_ch++;
1127 added++;
1128 }
1129
1130 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1131 return added;
1132}
1133
1dda6d28 1134void iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
b6e4c55a
JB		 1135{
1136 struct iwl_host_cmd cmd = {
1137 .id = REPLY_SCAN_CMD,
1138 .len = sizeof(struct iwl_scan_cmd),
1139 .flags = CMD_SIZE_HUGE,
1140 };
1141 struct iwl_scan_cmd *scan;
1142 struct ieee80211_conf *conf = NULL;
1143 u32 rate_flags = 0;
1144 u16 cmd_len;
1145 u16 rx_chain = 0;
1146 enum ieee80211_band band;
1147 u8 n_probes = 0;
1148 u8 rx_ant = priv->hw_params.valid_rx_ant;
1149 u8 rate;
1150 bool is_active = false;
1151 int chan_mod;
1152 u8 active_chains;
1153
1154 conf = ieee80211_get_hw_conf(priv->hw);
1155
1156 cancel_delayed_work(&priv->scan_check);
1157
1158 if (!iwl_is_ready(priv)) {
1159 IWL_WARN(priv, "request scan called when driver not ready.\n");
1160 goto done;
1161 }
1162
1163 /* Make sure the scan wasn't canceled before this queued work
1164 * was given the chance to run... */
1165 if (!test_bit(STATUS_SCANNING, &priv->status))
1166 goto done;
1167
1168 /* This should never be called or scheduled if there is currently
1169 * a scan active in the hardware. */
1170 if (test_bit(STATUS_SCAN_HW, &priv->status)) {
1171 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests in parallel. "
1172 "Ignoring second request.\n");
1173 goto done;
1174 }
1175
1176 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
1177 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
1178 goto done;
1179 }
1180
1181 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
1182 IWL_DEBUG_HC(priv, "Scan request while abort pending. Queuing.\n");
1183 goto done;
1184 }
1185
1186 if (iwl_is_rfkill(priv)) {
1187 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
1188 goto done;
1189 }
1190
1191 if (!test_bit(STATUS_READY, &priv->status)) {
1192 IWL_DEBUG_HC(priv, "Scan request while uninitialized. Queuing.\n");
1193 goto done;
1194 }
1195
1196 if (!priv->scan_cmd) {
1197 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1198 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1199 if (!priv->scan_cmd) {
1200 IWL_DEBUG_SCAN(priv,
1201 "fail to allocate memory for scan\n");
1202 goto done;
1203 }
1204 }
1205 scan = priv->scan_cmd;
1206 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1207
1208 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1209 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1210
1211 if (iwl_is_associated(priv)) {
1212 u16 interval = 0;
1213 u32 extra;
1214 u32 suspend_time = 100;
1215 u32 scan_suspend_time = 100;
1216 unsigned long flags;
1217
1218 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1219 spin_lock_irqsave(&priv->lock, flags);
1dda6d28 1220 interval = vif ? vif->bss_conf.beacon_int : 0;
b6e4c55a
JB		 1221 spin_unlock_irqrestore(&priv->lock, flags);
1222
1223 scan->suspend_time = 0;
1224 scan->max_out_time = cpu_to_le32(200 * 1024);
1225 if (!interval)
1226 interval = suspend_time;
1227
1228 extra = (suspend_time / interval) << 22;
1229 scan_suspend_time = (extra |
1230 ((suspend_time % interval) * 1024));
1231 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1232 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1233 scan_suspend_time, interval);
1234 }
1235
1236 if (priv->is_internal_short_scan) {
1237 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1238 } else if (priv->scan_request->n_ssids) {
1239 int i, p = 0;
1240 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1241 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1242 /* always does wildcard anyway */
1243 if (!priv->scan_request->ssids[i].ssid_len)
1244 continue;
1245 scan->direct_scan[p].id = WLAN_EID_SSID;
1246 scan->direct_scan[p].len =
1247 priv->scan_request->ssids[i].ssid_len;
1248 memcpy(scan->direct_scan[p].ssid,
1249 priv->scan_request->ssids[i].ssid,
1250 priv->scan_request->ssids[i].ssid_len);
1251 n_probes++;
1252 p++;
1253 }
1254 is_active = true;
1255 } else
1256 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1257
1258 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1259 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
1260 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1261
1262 switch (priv->scan_band) {
1263 case IEEE80211_BAND_2GHZ:
1264 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1265 chan_mod = le32_to_cpu(priv->active_rxon.flags & RXON_FLG_CHANNEL_MODE_MSK)
1266 >> RXON_FLG_CHANNEL_MODE_POS;
1267 if (chan_mod == CHANNEL_MODE_PURE_40) {
1268 rate = IWL_RATE_6M_PLCP;
1269 } else {
1270 rate = IWL_RATE_1M_PLCP;
1271 rate_flags = RATE_MCS_CCK_MSK;
1272 }
ad41ee3a 1273 scan->good_CRC_th = IWL_GOOD_CRC_TH_DISABLED;
b6e4c55a
JB		 1274 break;
1275 case IEEE80211_BAND_5GHZ:
1276 rate = IWL_RATE_6M_PLCP;
1277 /*
ad41ee3a
RC		 1278 * If active scanning is requested but a certain channel is
1279 * marked passive, we can do active scanning if we detect
1280 * transmissions.
1281 *
1282 * There is an issue with some firmware versions that triggers
1283 * a sysassert on a "good CRC threshold" of zero (== disabled),
1284 * on a radar channel even though this means that we should NOT
1285 * send probes.
1286 *
1287 * The "good CRC threshold" is the number of frames that we
1288 * need to receive during our dwell time on a channel before
1289 * sending out probes -- setting this to a huge value will
1290 * mean we never reach it, but at the same time work around
1291 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1292 * here instead of IWL_GOOD_CRC_TH_DISABLED.
b6e4c55a 1293 */
ad41ee3a
RC		 1294 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1295 IWL_GOOD_CRC_TH_NEVER;
b6e4c55a
JB		 1296 break;
1297 default:
1298 IWL_WARN(priv, "Invalid scan band count\n");
1299 goto done;
1300 }
1301
1302 band = priv->scan_band;
1303
e7cb4955
JB		 1304 if (priv->cfg->scan_antennas[band])
1305 rx_ant = priv->cfg->scan_antennas[band];
1306
b6e4c55a
JB		 1307 priv->scan_tx_ant[band] =
1308 iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band]);
1309 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1310 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1311
1312 /* In power save mode use one chain, otherwise use all chains */
1313 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1314 /* rx_ant has been set to all valid chains previously */
1315 active_chains = rx_ant &
1316 ((u8)(priv->chain_noise_data.active_chains));
1317 if (!active_chains)
1318 active_chains = rx_ant;
1319
1320 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1321 priv->chain_noise_data.active_chains);
1322
1323 rx_ant = first_antenna(active_chains);
1324 }
1325 /* MIMO is not used here, but value is required */
1326 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1327 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1328 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1329 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1330 scan->rx_chain = cpu_to_le16(rx_chain);
1331 if (!priv->is_internal_short_scan) {
1332 cmd_len = iwl_fill_probe_req(priv,
1333 (struct ieee80211_mgmt *)scan->data,
3a0b9aad 1334 vif->addr,
b6e4c55a
JB		 1335 priv->scan_request->ie,
1336 priv->scan_request->ie_len,
1337 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1338 } else {
3a0b9aad 1339 /* use bcast addr, will not be transmitted but must be valid */
b6e4c55a
JB		 1340 cmd_len = iwl_fill_probe_req(priv,
1341 (struct ieee80211_mgmt *)scan->data,
3a0b9aad 1342 iwl_bcast_addr, NULL, 0,
b6e4c55a
JB		 1343 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1344
1345 }
1346 scan->tx_cmd.len = cpu_to_le16(cmd_len);
b6e4c55a
JB		 1347
1348 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1349 RXON_FILTER_BCON_AWARE_MSK);
1350
1351 if (priv->is_internal_short_scan) {
1352 scan->channel_count =
1dda6d28 1353 iwl_get_single_channel_for_scan(priv, vif, band,
b6e4c55a
JB		 1354 (void *)&scan->data[le16_to_cpu(
1355 scan->tx_cmd.len)]);
1356 } else {
1357 scan->channel_count =
1dda6d28 1358 iwl_get_channels_for_scan(priv, vif, band,
b6e4c55a
JB		 1359 is_active, n_probes,
1360 (void *)&scan->data[le16_to_cpu(
1361 scan->tx_cmd.len)]);
1362 }
1363 if (scan->channel_count == 0) {
1364 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1365 goto done;
1366 }
1367
1368 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1369 scan->channel_count * sizeof(struct iwl_scan_channel);
1370 cmd.data = scan;
1371 scan->len = cpu_to_le16(cmd.len);
1372
1373 set_bit(STATUS_SCAN_HW, &priv->status);
1374 if (iwl_send_cmd_sync(priv, &cmd))
1375 goto done;
1376
1377 queue_delayed_work(priv->workqueue, &priv->scan_check,
1378 IWL_SCAN_CHECK_WATCHDOG);
1379
1380 return;
1381
1382 done:
1383 /* Cannot perform scan. Make sure we clear scanning
1384 * bits from status so next scan request can be performed.
1385 * If we don't clear scanning status bit here all next scan
1386 * will fail
1387 */
1388 clear_bit(STATUS_SCAN_HW, &priv->status);
1389 clear_bit(STATUS_SCANNING, &priv->status);
1390 /* inform mac80211 scan aborted */
1391 queue_work(priv->workqueue, &priv->scan_completed);
1392}
1fa61b2e
JB		 1393
1394int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1395 struct ieee80211_vif *vif, bool add)
1396{
fd1af15d
JB		 1397 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1398
1fa61b2e 1399 if (add)
57f8db89 1400 return iwl_add_bssid_station(priv, vif->bss_conf.bssid, true,
fd1af15d
JB		 1401 &vif_priv->ibss_bssid_sta_id);
1402 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1403 vif->bss_conf.bssid);
1fa61b2e 1404}
1ff504e0
JB		 1405
1406void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1407 int sta_id, int tid, int freed)
1408{
9c5ac091
RC		 1409 WARN_ON(!spin_is_locked(&priv->sta_lock));
1410
1ff504e0
JB		 1411 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1412 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1413 else {
1414 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1415 priv->stations[sta_id].tid[tid].tfds_in_queue,
1416 freed);
1417 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1418 }
1419}
Linux kernel - Deliverables
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