[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-ucode.c

/******************************************************************************
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>

#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-helpers.h"
#include "iwl-agn-hw.h"
#include "iwl-agn.h"
#include "iwl-agn-calib.h"
#include "iwl-trans.h"

static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
	{COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
	 0, COEX_UNASSOC_IDLE_FLAGS},
	{COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
	 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
	{COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
	 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
	{COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
	 0, COEX_CALIBRATION_FLAGS},
	{COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
	 0, COEX_PERIODIC_CALIBRATION_FLAGS},
	{COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
	 0, COEX_CONNECTION_ESTAB_FLAGS},
	{COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
	 0, COEX_ASSOCIATED_IDLE_FLAGS},
	{COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
	 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
	{COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
	 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
	{COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
	 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
	{COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
	{COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
	{COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
	 0, COEX_STAND_ALONE_DEBUG_FLAGS},
	{COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
	 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
	{COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
	{COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
};

/*
 * ucode
 */
static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
				struct fw_desc *image, u32 dst_addr)
{
	dma_addr_t phy_addr = image->p_addr;
	u32 byte_cnt = image->len;
	int ret;

	priv->ucode_write_complete = 0;

	iwl_write_direct32(priv,
		FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);

	iwl_write_direct32(priv,
		FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);

	iwl_write_direct32(priv,
		FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
		phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);

	iwl_write_direct32(priv,
		FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
		(iwl_get_dma_hi_addr(phy_addr)
			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);

	iwl_write_direct32(priv,
		FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
		1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
		1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
		FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);

	iwl_write_direct32(priv,
		FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE	|
		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE	|
		FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);

	IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
	ret = wait_event_interruptible_timeout(priv->wait_command_queue,
					priv->ucode_write_complete, 5 * HZ);
	if (ret == -ERESTARTSYS) {
		IWL_ERR(priv, "Could not load the %s uCode section due "
			"to interrupt\n", name);
		return ret;
	}
	if (!ret) {
		IWL_ERR(priv, "Could not load the %s uCode section\n",
			name);
		return -ETIMEDOUT;
	}

	return 0;
}

static int iwlagn_load_given_ucode(struct iwl_priv *priv,
				   struct fw_img *image)
{
	int ret = 0;

	ret = iwlagn_load_section(priv, "INST", &image->code,
				   IWLAGN_RTC_INST_LOWER_BOUND);
	if (ret)
		return ret;

	return iwlagn_load_section(priv, "DATA", &image->data,
				    IWLAGN_RTC_DATA_LOWER_BOUND);
}

/*
 *  Calibration
 */
static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
{
	struct iwl_calib_xtal_freq_cmd cmd;
	__le16 *xtal_calib =
		(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);

	iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
	cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
	cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
	return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
			     (u8 *)&cmd, sizeof(cmd));
}

static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
{
	struct iwl_calib_temperature_offset_cmd cmd;
	__le16 *offset_calib =
		(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);

	memset(&cmd, 0, sizeof(cmd));
	iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
	cmd.radio_sensor_offset = le16_to_cpu(offset_calib[1]);
	if (!(cmd.radio_sensor_offset))
		cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;

	IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
			cmd.radio_sensor_offset);
	return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
			     (u8 *)&cmd, sizeof(cmd));
}

static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
{
	struct iwl_calib_cfg_cmd calib_cfg_cmd;
	struct iwl_host_cmd cmd = {
		.id = CALIBRATION_CFG_CMD,
		.len = { sizeof(struct iwl_calib_cfg_cmd), },
		.data = { &calib_cfg_cmd, },
	};

	memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
	calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
	calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
	calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
	calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;

	return trans_send_cmd(priv, &cmd);
}

void iwlagn_rx_calib_result(struct iwl_priv *priv,
			     struct iwl_rx_mem_buffer *rxb)
{
	struct iwl_rx_packet *pkt = rxb_addr(rxb);
	struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
	int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
	int index;

	/* reduce the size of the length field itself */
	len -= 4;

	/* Define the order in which the results will be sent to the runtime
	 * uCode. iwl_send_calib_results sends them in a row according to
	 * their index. We sort them here
	 */
	switch (hdr->op_code) {
	case IWL_PHY_CALIBRATE_DC_CMD:
		index = IWL_CALIB_DC;
		break;
	case IWL_PHY_CALIBRATE_LO_CMD:
		index = IWL_CALIB_LO;
		break;
	case IWL_PHY_CALIBRATE_TX_IQ_CMD:
		index = IWL_CALIB_TX_IQ;
		break;
	case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
		index = IWL_CALIB_TX_IQ_PERD;
		break;
	case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
		index = IWL_CALIB_BASE_BAND;
		break;
	default:
		IWL_ERR(priv, "Unknown calibration notification %d\n",
			  hdr->op_code);
		return;
	}
	iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
}

int iwlagn_init_alive_start(struct iwl_priv *priv)
{
	int ret;

	if (priv->cfg->bt_params &&
	    priv->cfg->bt_params->advanced_bt_coexist) {
		/*
		 * Tell uCode we are ready to perform calibration
		 * need to perform this before any calibration
		 * no need to close the envlope since we are going
		 * to load the runtime uCode later.
		 */
		ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
			BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
		if (ret)
			return ret;

	}

	ret = iwlagn_send_calib_cfg(priv);
	if (ret)
		return ret;

	/**
	 * temperature offset calibration is only needed for runtime ucode,
	 * so prepare the value now.
	 */
	if (priv->cfg->need_temp_offset_calib)
		return iwlagn_set_temperature_offset_calib(priv);

	return 0;
}

static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
{
	struct iwl_wimax_coex_cmd coex_cmd;

	if (priv->cfg->base_params->support_wimax_coexist) {
		/* UnMask wake up src at associated sleep */
		coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;

		/* UnMask wake up src at unassociated sleep */
		coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
		memcpy(coex_cmd.sta_prio, cu_priorities,
			sizeof(struct iwl_wimax_coex_event_entry) *
			 COEX_NUM_OF_EVENTS);

		/* enabling the coexistence feature */
		coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;

		/* enabling the priorities tables */
		coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
	} else {
		/* coexistence is disabled */
		memset(&coex_cmd, 0, sizeof(coex_cmd));
	}
	return trans_send_cmd_pdu(priv,
				COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
				sizeof(coex_cmd), &coex_cmd);
}

static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	0, 0, 0, 0, 0, 0, 0
};

void iwlagn_send_prio_tbl(struct iwl_priv *priv)
{
	struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;

	memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
		sizeof(iwlagn_bt_prio_tbl));
	if (trans_send_cmd_pdu(priv,
				REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
				sizeof(prio_tbl_cmd), &prio_tbl_cmd))
		IWL_ERR(priv, "failed to send BT prio tbl command\n");
}

int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
{
	struct iwl_bt_coex_prot_env_cmd env_cmd;
	int ret;

	env_cmd.action = action;
	env_cmd.type = type;
	ret = trans_send_cmd_pdu(priv,
			       REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
			       sizeof(env_cmd), &env_cmd);
	if (ret)
		IWL_ERR(priv, "failed to send BT env command\n");
	return ret;
}


static int iwlagn_alive_notify(struct iwl_priv *priv)
{
	int ret;

	trans_tx_start(priv);

	ret = iwlagn_send_wimax_coex(priv);
	if (ret)
		return ret;

	ret = iwlagn_set_Xtal_calib(priv);
	if (ret)
		return ret;

	return iwl_send_calib_results(priv);
}


/**
 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
 *   using sample data 100 bytes apart.  If these sample points are good,
 *   it's a pretty good bet that everything between them is good, too.
 */
static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
				      struct fw_desc *fw_desc)
{
	__le32 *image = (__le32 *)fw_desc->v_addr;
	u32 len = fw_desc->len;
	u32 val;
	u32 i;

	IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);

	for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
		/* read data comes through single port, auto-incr addr */
		/* NOTE: Use the debugless read so we don't flood kernel log
		 * if IWL_DL_IO is set */
		iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
			i + IWLAGN_RTC_INST_LOWER_BOUND);
		val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
		if (val != le32_to_cpu(*image))
			return -EIO;
	}

	return 0;
}

static void iwl_print_mismatch_inst(struct iwl_priv *priv,
				    struct fw_desc *fw_desc)
{
	__le32 *image = (__le32 *)fw_desc->v_addr;
	u32 len = fw_desc->len;
	u32 val;
	u32 offs;
	int errors = 0;

	IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);

	iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
			   IWLAGN_RTC_INST_LOWER_BOUND);

	for (offs = 0;
	     offs < len && errors < 20;
	     offs += sizeof(u32), image++) {
		/* read data comes through single port, auto-incr addr */
		val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
		if (val != le32_to_cpu(*image)) {
			IWL_ERR(priv, "uCode INST section at "
				"offset 0x%x, is 0x%x, s/b 0x%x\n",
				offs, val, le32_to_cpu(*image));
			errors++;
		}
	}
}

/**
 * iwl_verify_ucode - determine which instruction image is in SRAM,
 *    and verify its contents
 */
static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
{
	if (!iwlcore_verify_inst_sparse(priv, &img->code)) {
		IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
		return 0;
	}

	IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");

	iwl_print_mismatch_inst(priv, &img->code);
	return -EIO;
}

struct iwlagn_alive_data {
	bool valid;
	u8 subtype;
};

static void iwlagn_alive_fn(struct iwl_priv *priv,
			    struct iwl_rx_packet *pkt,
			    void *data)
{
	struct iwlagn_alive_data *alive_data = data;
	struct iwl_alive_resp *palive;

	palive = &pkt->u.alive_frame;

	IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
		       "0x%01X 0x%01X\n",
		       palive->is_valid, palive->ver_type,
		       palive->ver_subtype);

	priv->device_pointers.error_event_table =
		le32_to_cpu(palive->error_event_table_ptr);
	priv->device_pointers.log_event_table =
		le32_to_cpu(palive->log_event_table_ptr);

	alive_data->subtype = palive->ver_subtype;
	alive_data->valid = palive->is_valid == UCODE_VALID_OK;
}

#define UCODE_ALIVE_TIMEOUT	HZ
#define UCODE_CALIB_TIMEOUT	(2*HZ)

int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
				 struct fw_img *image,
				 enum iwlagn_ucode_type ucode_type)
{
	struct iwl_notification_wait alive_wait;
	struct iwlagn_alive_data alive_data;
	int ret;
	enum iwlagn_ucode_type old_type;

	ret = iwlagn_start_device(priv);
	if (ret)
		return ret;

	iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
				      iwlagn_alive_fn, &alive_data);

	old_type = priv->ucode_type;
	priv->ucode_type = ucode_type;

	ret = iwlagn_load_given_ucode(priv, image);
	if (ret) {
		priv->ucode_type = old_type;
		iwlagn_remove_notification(priv, &alive_wait);
		return ret;
	}

	trans_kick_nic(priv);

	/*
	 * Some things may run in the background now, but we
	 * just wait for the ALIVE notification here.
	 */
	ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
	if (ret) {
		priv->ucode_type = old_type;
		return ret;
	}

	if (!alive_data.valid) {
		IWL_ERR(priv, "Loaded ucode is not valid!\n");
		priv->ucode_type = old_type;
		return -EIO;
	}

	ret = iwl_verify_ucode(priv, image);
	if (ret) {
		priv->ucode_type = old_type;
		return ret;
	}

	/* delay a bit to give rfkill time to run */
	msleep(5);

	ret = iwlagn_alive_notify(priv);
	if (ret) {
		IWL_WARN(priv,
			"Could not complete ALIVE transition: %d\n", ret);
		priv->ucode_type = old_type;
		return ret;
	}

	return 0;
}

int iwlagn_run_init_ucode(struct iwl_priv *priv)
{
	struct iwl_notification_wait calib_wait;
	int ret;

	lockdep_assert_held(&priv->mutex);

	/* No init ucode required? Curious, but maybe ok */
	if (!priv->ucode_init.code.len)
		return 0;

	if (priv->ucode_type != IWL_UCODE_NONE)
		return 0;

	iwlagn_init_notification_wait(priv, &calib_wait,
				      CALIBRATION_COMPLETE_NOTIFICATION,
				      NULL, NULL);

	/* Will also start the device */
	ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
					   IWL_UCODE_INIT);
	if (ret)
		goto error;

	ret = iwlagn_init_alive_start(priv);
	if (ret)
		goto error;

	/*
	 * Some things may run in the background now, but we
	 * just wait for the calibration complete notification.
	 */
	ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);

	goto out;

 error:
	iwlagn_remove_notification(priv, &calib_wait);
 out:
	/* Whatever happened, stop the device */
	trans_stop_device(priv);
	return ret;
}
Commit	Line	Data
792bc3cb WYG	1	/******************************************************************************
	2	*
	3	* GPL LICENSE SUMMARY
	4	*
901069c7	5	* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
792bc3cb WYG	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of version 2 of the GNU General Public License as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
	19	* USA
	20	*
	21	* The full GNU General Public License is included in this distribution
	22	* in the file called LICENSE.GPL.
	23	*
	24	* Contact Information:
	25	* Intel Linux Wireless <ilw@linux.intel.com>
	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*
	28	*****************************************************************************/
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
	32	#include <linux/init.h>
81b8176e	33	#include <linux/sched.h>
792bc3cb WYG	34
	35	#include "iwl-dev.h"
	36	#include "iwl-core.h"
81b8176e	37	#include "iwl-io.h"
741a6266	38	#include "iwl-helpers.h"
19e6cda0	39	#include "iwl-agn-hw.h"
741a6266	40	#include "iwl-agn.h"
0de76736	41	#include "iwl-agn-calib.h"
bdfbf092	42	#include "iwl-trans.h"
741a6266	43
f4012413 WYG	44	static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
	45	{COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
	46	0, COEX_UNASSOC_IDLE_FLAGS},
	47	{COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
	48	0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
	49	{COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
	50	0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
	51	{COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
	52	0, COEX_CALIBRATION_FLAGS},
	53	{COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
	54	0, COEX_PERIODIC_CALIBRATION_FLAGS},
	55	{COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
	56	0, COEX_CONNECTION_ESTAB_FLAGS},
	57	{COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
	58	0, COEX_ASSOCIATED_IDLE_FLAGS},
	59	{COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
	60	0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
	61	{COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
	62	0, COEX_ASSOC_AUTO_SCAN_FLAGS},
	63	{COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
	64	0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
	65	{COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
	66	{COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
	67	{COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
	68	0, COEX_STAND_ALONE_DEBUG_FLAGS},
	69	{COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
	70	0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
	71	{COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
	72	{COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
	73	};
	74
81b8176e WYG	75	/*
	76	* ucode
	77	*/
	78	static int iwlagn_load_section(struct iwl_priv priv, const char name,
	79	struct fw_desc *image, u32 dst_addr)
	80	{
	81	dma_addr_t phy_addr = image->p_addr;
	82	u32 byte_cnt = image->len;
	83	int ret;
	84
	85	priv->ucode_write_complete = 0;
	86
	87	iwl_write_direct32(priv,
	88	FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
	89	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
	90
	91	iwl_write_direct32(priv,
	92	FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
	93
	94	iwl_write_direct32(priv,
	95	FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
	96	phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
	97
	98	iwl_write_direct32(priv,
	99	FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
	100	(iwl_get_dma_hi_addr(phy_addr)
	101	<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) \| byte_cnt);
	102
	103	iwl_write_direct32(priv,
	104	FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
	105	1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM \|
	106	1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX \|
	107	FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
	108
	109	iwl_write_direct32(priv,
	110	FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
	111	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \|
	112	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE \|
	113	FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
	114
06bb8358	115	IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
81b8176e WYG	116	ret = wait_event_interruptible_timeout(priv->wait_command_queue,
	117	priv->ucode_write_complete, 5 * HZ);
	118	if (ret == -ERESTARTSYS) {
	119	IWL_ERR(priv, "Could not load the %s uCode section due "
	120	"to interrupt\n", name);
	121	return ret;
	122	}
	123	if (!ret) {
	124	IWL_ERR(priv, "Could not load the %s uCode section\n",
	125	name);
	126	return -ETIMEDOUT;
	127	}
	128
	129	return 0;
	130	}
	131
	132	static int iwlagn_load_given_ucode(struct iwl_priv *priv,
dbf28e21	133	struct fw_img *image)
81b8176e WYG	134	{
	135	int ret = 0;
	136
dbf28e21	137	ret = iwlagn_load_section(priv, "INST", &image->code,
19e6cda0	138	IWLAGN_RTC_INST_LOWER_BOUND);
81b8176e WYG	139	if (ret)
	140	return ret;
	141
dbf28e21	142	return iwlagn_load_section(priv, "DATA", &image->data,
19e6cda0	143	IWLAGN_RTC_DATA_LOWER_BOUND);
81b8176e WYG	144	}
81b8176e WYG	145
741a6266 WYG	146	/*
	147	* Calibration
	148	*/
	149	static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
	150	{
	151	struct iwl_calib_xtal_freq_cmd cmd;
	152	__le16 *xtal_calib =
7944f8e4	153	(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
741a6266	154
1f8bf039	155	iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
741a6266 WYG	156	cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
	157	cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
	158	return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
	159	(u8 *)&cmd, sizeof(cmd));
	160	}
	161
bf53f939 SZ	162	static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
	163	{
	164	struct iwl_calib_temperature_offset_cmd cmd;
	165	__le16 *offset_calib =
8d8854d9	166	(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);
1f8bf039 WYG	167
	168	memset(&cmd, 0, sizeof(cmd));
	169	iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
bf53f939 SZ	170	cmd.radio_sensor_offset = le16_to_cpu(offset_calib[1]);
	171	if (!(cmd.radio_sensor_offset))
	172	cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
1f8bf039	173
bf53f939 SZ	174	IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
	175	cmd.radio_sensor_offset);
	176	return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
	177	(u8 *)&cmd, sizeof(cmd));
	178	}
	179
741a6266 WYG	180	static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
	181	{
	182	struct iwl_calib_cfg_cmd calib_cfg_cmd;
	183	struct iwl_host_cmd cmd = {
	184	.id = CALIBRATION_CFG_CMD,
3fa50738 JB	185	.len = { sizeof(struct iwl_calib_cfg_cmd), },
3fa50738 JB	186	.data = { &calib_cfg_cmd, },
741a6266 WYG	187	};
	188
	189	memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
	190	calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
	191	calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
	192	calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
	193	calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
	194
bdfbf092	195	return trans_send_cmd(priv, &cmd);
741a6266 WYG	196	}
	197
	198	void iwlagn_rx_calib_result(struct iwl_priv *priv,
	199	struct iwl_rx_mem_buffer *rxb)
	200	{
	201	struct iwl_rx_packet *pkt = rxb_addr(rxb);
	202	struct iwl_calib_hdr hdr = (struct iwl_calib_hdr )pkt->u.raw;
	203	int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
	204	int index;
	205
	206	/* reduce the size of the length field itself */
	207	len -= 4;
	208
	209	/* Define the order in which the results will be sent to the runtime
	210	* uCode. iwl_send_calib_results sends them in a row according to
	211	* their index. We sort them here
	212	*/
	213	switch (hdr->op_code) {
	214	case IWL_PHY_CALIBRATE_DC_CMD:
	215	index = IWL_CALIB_DC;
	216	break;
	217	case IWL_PHY_CALIBRATE_LO_CMD:
	218	index = IWL_CALIB_LO;
	219	break;
	220	case IWL_PHY_CALIBRATE_TX_IQ_CMD:
	221	index = IWL_CALIB_TX_IQ;
	222	break;
	223	case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
	224	index = IWL_CALIB_TX_IQ_PERD;
	225	break;
	226	case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
	227	index = IWL_CALIB_BASE_BAND;
	228	break;
	229	default:
	230	IWL_ERR(priv, "Unknown calibration notification %d\n",
	231	hdr->op_code);
	232	return;
	233	}
	234	iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
	235	}
	236
4613e72d	237	int iwlagn_init_alive_start(struct iwl_priv *priv)
741a6266	238	{
ca7966c8	239	int ret;
741a6266	240
7cb1b088 WYG	241	if (priv->cfg->bt_params &&
7cb1b088 WYG	242	priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f WYG	243	/*
	244	* Tell uCode we are ready to perform calibration
	245	* need to perform this before any calibration
	246	* no need to close the envlope since we are going
	247	* to load the runtime uCode later.
	248	*/
ca7966c8	249	ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
f7322f8f	250	BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
ca7966c8 JB	251	if (ret)
ca7966c8 JB	252	return ret;
f7322f8f WYG	253
f7322f8f WYG	254	}
ca7966c8 JB	255
	256	ret = iwlagn_send_calib_cfg(priv);
	257	if (ret)
	258	return ret;
bf53f939 SZ	259
	260	/**
	261	* temperature offset calibration is only needed for runtime ucode,
	262	* so prepare the value now.
	263	*/
	264	if (priv->cfg->need_temp_offset_calib)
ca7966c8	265	return iwlagn_set_temperature_offset_calib(priv);
741a6266	266
ca7966c8	267	return 0;
741a6266 WYG	268	}
741a6266 WYG	269
f4012413 WYG	270	static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
	271	{
	272	struct iwl_wimax_coex_cmd coex_cmd;
	273
7cb1b088	274	if (priv->cfg->base_params->support_wimax_coexist) {
f4012413 WYG	275	/* UnMask wake up src at associated sleep */
	276	coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
	277
	278	/* UnMask wake up src at unassociated sleep */
	279	coex_cmd.flags \|= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
	280	memcpy(coex_cmd.sta_prio, cu_priorities,
	281	sizeof(struct iwl_wimax_coex_event_entry) *
	282	COEX_NUM_OF_EVENTS);
	283
	284	/* enabling the coexistence feature */
	285	coex_cmd.flags \|= COEX_FLAGS_COEX_ENABLE_MSK;
	286
	287	/* enabling the priorities tables */
	288	coex_cmd.flags \|= COEX_FLAGS_STA_TABLE_VALID_MSK;
	289	} else {
	290	/* coexistence is disabled */
	291	memset(&coex_cmd, 0, sizeof(coex_cmd));
	292	}
bdfbf092	293	return trans_send_cmd_pdu(priv,
e419d62d	294	COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
f4012413 WYG	295	sizeof(coex_cmd), &coex_cmd);
	296	}
	297
aeb4a2ee WYG	298	static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
	299	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	300	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	301	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	302	(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	303	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	304	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	305	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	306	(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	307	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	308	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	309	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	310	(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	311	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	312	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	313	((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	314	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	315	((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	316	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	317	0, 0, 0, 0, 0, 0, 0
	318	};
	319
f7322f8f	320	void iwlagn_send_prio_tbl(struct iwl_priv *priv)
aeb4a2ee WYG	321	{
	322	struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
	323
	324	memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
	325	sizeof(iwlagn_bt_prio_tbl));
bdfbf092	326	if (trans_send_cmd_pdu(priv,
e419d62d	327	REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
aeb4a2ee WYG	328	sizeof(prio_tbl_cmd), &prio_tbl_cmd))
	329	IWL_ERR(priv, "failed to send BT prio tbl command\n");
	330	}
	331
ca7966c8	332	int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
aeb4a2ee WYG	333	{
aeb4a2ee WYG	334	struct iwl_bt_coex_prot_env_cmd env_cmd;
ca7966c8	335	int ret;
aeb4a2ee WYG	336
	337	env_cmd.action = action;
	338	env_cmd.type = type;
bdfbf092	339	ret = trans_send_cmd_pdu(priv,
e419d62d	340	REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
ca7966c8 JB	341	sizeof(env_cmd), &env_cmd);
ca7966c8 JB	342	if (ret)
aeb4a2ee	343	IWL_ERR(priv, "failed to send BT env command\n");
ca7966c8	344	return ret;
aeb4a2ee WYG	345	}
	346
	347
ca7966c8	348	static int iwlagn_alive_notify(struct iwl_priv *priv)
741a6266	349	{
7415952f	350	int ret;
741a6266	351
b3c2ce13	352	trans_tx_start(priv);
e7cad69c	353
7415952f WYG	354	ret = iwlagn_send_wimax_coex(priv);
	355	if (ret)
	356	return ret;
	357
	358	ret = iwlagn_set_Xtal_calib(priv);
	359	if (ret)
	360	return ret;
741a6266	361
36127db0	362	return iwl_send_calib_results(priv);
741a6266	363	}
db41dd27 WYG	364
	365
	366	/**
	367	* iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
	368	* using sample data 100 bytes apart. If these sample points are good,
	369	* it's a pretty good bet that everything between them is good, too.
	370	*/
35b1d92d JB	371	static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
35b1d92d JB	372	struct fw_desc *fw_desc)
db41dd27	373	{
35b1d92d JB	374	__le32 image = (__le32 )fw_desc->v_addr;
35b1d92d JB	375	u32 len = fw_desc->len;
db41dd27	376	u32 val;
db41dd27 WYG	377	u32 i;
db41dd27 WYG	378
06bb8358	379	IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
db41dd27 WYG	380
	381	for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
	382	/* read data comes through single port, auto-incr addr */
	383	/* NOTE: Use the debugless read so we don't flood kernel log
	384	* if IWL_DL_IO is set */
	385	iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
	386	i + IWLAGN_RTC_INST_LOWER_BOUND);
02a7fa00	387	val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
fb66216f JB	388	if (val != le32_to_cpu(*image))
fb66216f JB	389	return -EIO;
db41dd27 WYG	390	}
db41dd27 WYG	391
fb66216f	392	return 0;
db41dd27 WYG	393	}
db41dd27 WYG	394
fb66216f	395	static void iwl_print_mismatch_inst(struct iwl_priv *priv,
35b1d92d	396	struct fw_desc *fw_desc)
db41dd27	397	{
35b1d92d JB	398	__le32 image = (__le32 )fw_desc->v_addr;
35b1d92d JB	399	u32 len = fw_desc->len;
db41dd27	400	u32 val;
fb66216f JB	401	u32 offs;
fb66216f JB	402	int errors = 0;
db41dd27	403
06bb8358	404	IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
db41dd27 WYG	405
	406	iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
	407	IWLAGN_RTC_INST_LOWER_BOUND);
	408
fb66216f JB	409	for (offs = 0;
	410	offs < len && errors < 20;
	411	offs += sizeof(u32), image++) {
db41dd27	412	/* read data comes through single port, auto-incr addr */
02a7fa00	413	val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
db41dd27	414	if (val != le32_to_cpu(*image)) {
fb66216f JB	415	IWL_ERR(priv, "uCode INST section at "
	416	"offset 0x%x, is 0x%x, s/b 0x%x\n",
	417	offs, val, le32_to_cpu(*image));
	418	errors++;
db41dd27 WYG	419	}
db41dd27 WYG	420	}
db41dd27 WYG	421	}
	422
	423	/**
	424	* iwl_verify_ucode - determine which instruction image is in SRAM,
	425	* and verify its contents
	426	*/
dbf28e21	427	static int iwl_verify_ucode(struct iwl_priv priv, struct fw_img img)
db41dd27	428	{
dbf28e21	429	if (!iwlcore_verify_inst_sparse(priv, &img->code)) {
06bb8358	430	IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
db41dd27 WYG	431	return 0;
	432	}
	433
35b1d92d	434	IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
fb66216f	435
dbf28e21	436	iwl_print_mismatch_inst(priv, &img->code);
fb66216f	437	return -EIO;
db41dd27	438	}
ca7966c8 JB	439
	440	struct iwlagn_alive_data {
	441	bool valid;
	442	u8 subtype;
	443	};
	444
	445	static void iwlagn_alive_fn(struct iwl_priv *priv,
	446	struct iwl_rx_packet *pkt,
	447	void *data)
	448	{
	449	struct iwlagn_alive_data *alive_data = data;
	450	struct iwl_alive_resp *palive;
	451
	452	palive = &pkt->u.alive_frame;
	453
06bb8358	454	IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
ca7966c8 JB	455	"0x%01X 0x%01X\n",
	456	palive->is_valid, palive->ver_type,
	457	palive->ver_subtype);
	458
	459	priv->device_pointers.error_event_table =
	460	le32_to_cpu(palive->error_event_table_ptr);
	461	priv->device_pointers.log_event_table =
	462	le32_to_cpu(palive->log_event_table_ptr);
	463
	464	alive_data->subtype = palive->ver_subtype;
	465	alive_data->valid = palive->is_valid == UCODE_VALID_OK;
	466	}
	467
	468	#define UCODE_ALIVE_TIMEOUT HZ
	469	#define UCODE_CALIB_TIMEOUT (2*HZ)
	470
	471	int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
dbf28e21	472	struct fw_img *image,
872907bb	473	enum iwlagn_ucode_type ucode_type)
ca7966c8 JB	474	{
	475	struct iwl_notification_wait alive_wait;
	476	struct iwlagn_alive_data alive_data;
	477	int ret;
872907bb	478	enum iwlagn_ucode_type old_type;
ca7966c8 JB	479
	480	ret = iwlagn_start_device(priv);
	481	if (ret)
	482	return ret;
	483
	484	iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
	485	iwlagn_alive_fn, &alive_data);
	486
	487	old_type = priv->ucode_type;
872907bb	488	priv->ucode_type = ucode_type;
ca7966c8	489
dbf28e21	490	ret = iwlagn_load_given_ucode(priv, image);
ca7966c8 JB	491	if (ret) {
	492	priv->ucode_type = old_type;
	493	iwlagn_remove_notification(priv, &alive_wait);
	494	return ret;
	495	}
	496
56d90f4c	497	trans_kick_nic(priv);
ca7966c8 JB	498
	499	/*
	500	* Some things may run in the background now, but we
	501	* just wait for the ALIVE notification here.
	502	*/
	503	ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
	504	if (ret) {
	505	priv->ucode_type = old_type;
	506	return ret;
	507	}
	508
	509	if (!alive_data.valid) {
	510	IWL_ERR(priv, "Loaded ucode is not valid!\n");
	511	priv->ucode_type = old_type;
	512	return -EIO;
	513	}
	514
dbf28e21	515	ret = iwl_verify_ucode(priv, image);
ca7966c8 JB	516	if (ret) {
	517	priv->ucode_type = old_type;
	518	return ret;
	519	}
	520
	521	/* delay a bit to give rfkill time to run */
	522	msleep(5);
	523
	524	ret = iwlagn_alive_notify(priv);
	525	if (ret) {
	526	IWL_WARN(priv,
	527	"Could not complete ALIVE transition: %d\n", ret);
	528	priv->ucode_type = old_type;
	529	return ret;
	530	}
	531
	532	return 0;
	533	}
	534
	535	int iwlagn_run_init_ucode(struct iwl_priv *priv)
	536	{
	537	struct iwl_notification_wait calib_wait;
	538	int ret;
	539
	540	lockdep_assert_held(&priv->mutex);
	541
	542	/* No init ucode required? Curious, but maybe ok */
dbf28e21	543	if (!priv->ucode_init.code.len)
ca7966c8 JB	544	return 0;
ca7966c8 JB	545
872907bb	546	if (priv->ucode_type != IWL_UCODE_NONE)
ca7966c8 JB	547	return 0;
	548
	549	iwlagn_init_notification_wait(priv, &calib_wait,
	550	CALIBRATION_COMPLETE_NOTIFICATION,
	551	NULL, NULL);
	552
	553	/* Will also start the device */
	554	ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
872907bb	555	IWL_UCODE_INIT);
ca7966c8 JB	556	if (ret)
	557	goto error;
	558
	559	ret = iwlagn_init_alive_start(priv);
	560	if (ret)
	561	goto error;
	562
	563	/*
	564	* Some things may run in the background now, but we
	565	* just wait for the calibration complete notification.
	566	*/
	567	ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
	568
	569	goto out;
	570
	571	error:
	572	iwlagn_remove_notification(priv, &calib_wait);
	573	out:
	574	/* Whatever happened, stop the device */
ab6cf8e8	575	trans_stop_device(priv);
ca7966c8 JB	576	return ret;
ca7966c8 JB	577	}