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iwlagn: remove code duplication
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-ucode.c
CommitLineData
792bc3cb
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
901069c7 5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
792bc3cb
WYG		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/init.h>
81b8176e 33#include <linux/sched.h>
792bc3cb
WYG		 34
35#include "iwl-dev.h"
36#include "iwl-core.h"
81b8176e 37#include "iwl-io.h"
741a6266 38#include "iwl-helpers.h"
19e6cda0 39#include "iwl-agn-hw.h"
741a6266 40#include "iwl-agn.h"
0de76736 41#include "iwl-agn-calib.h"
741a6266 42
cfa1da7e
JB		 43#define IWL_AC_UNSET -1
44
45struct queue_to_fifo_ac {
46 s8 fifo, ac;
47};
48
49static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
0c4ac342
JB		 50 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
51 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
52 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
53 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
cfa1da7e
JB		 54 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
55 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
56 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
57 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
58 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
59 { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
741a6266 60};
81b8176e 61
cfa1da7e 62static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
0c4ac342
JB		 63 { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
64 { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
65 { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
66 { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
67 { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
68 { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
69 { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
70 { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
cfa1da7e
JB		 71 { IWL_TX_FIFO_BE_IPAN, 2, },
72 { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
13bb9483
JB		 73};
74
f4012413
WYG		 75static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
76 {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
77 0, COEX_UNASSOC_IDLE_FLAGS},
78 {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
79 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
80 {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
81 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
82 {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
83 0, COEX_CALIBRATION_FLAGS},
84 {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
85 0, COEX_PERIODIC_CALIBRATION_FLAGS},
86 {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
87 0, COEX_CONNECTION_ESTAB_FLAGS},
88 {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
89 0, COEX_ASSOCIATED_IDLE_FLAGS},
90 {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
91 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
92 {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
93 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
94 {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
95 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
96 {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
97 {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
98 {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
99 0, COEX_STAND_ALONE_DEBUG_FLAGS},
100 {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
101 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
102 {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
103 {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
104};
105
81b8176e
WYG		 106/*
107 * ucode
108 */
109static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
110 struct fw_desc *image, u32 dst_addr)
111{
112 dma_addr_t phy_addr = image->p_addr;
113 u32 byte_cnt = image->len;
114 int ret;
115
116 priv->ucode_write_complete = 0;
117
118 iwl_write_direct32(priv,
119 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
120 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
121
122 iwl_write_direct32(priv,
123 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
124
125 iwl_write_direct32(priv,
126 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
127 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
128
129 iwl_write_direct32(priv,
130 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
131 (iwl_get_dma_hi_addr(phy_addr)
132 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
133
134 iwl_write_direct32(priv,
135 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
136 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
137 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
138 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
139
140 iwl_write_direct32(priv,
141 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
142 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
143 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
144 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
145
06bb8358 146 IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
81b8176e
WYG		 147 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
148 priv->ucode_write_complete, 5 * HZ);
149 if (ret == -ERESTARTSYS) {
150 IWL_ERR(priv, "Could not load the %s uCode section due "
151 "to interrupt\n", name);
152 return ret;
153 }
154 if (!ret) {
155 IWL_ERR(priv, "Could not load the %s uCode section\n",
156 name);
157 return -ETIMEDOUT;
158 }
159
160 return 0;
161}
162
163static int iwlagn_load_given_ucode(struct iwl_priv *priv,
dbf28e21 164 struct fw_img *image)
81b8176e
WYG		 165{
166 int ret = 0;
167
dbf28e21 168 ret = iwlagn_load_section(priv, "INST", &image->code,
19e6cda0 169 IWLAGN_RTC_INST_LOWER_BOUND);
81b8176e
WYG		 170 if (ret)
171 return ret;
172
dbf28e21 173 return iwlagn_load_section(priv, "DATA", &image->data,
19e6cda0 174 IWLAGN_RTC_DATA_LOWER_BOUND);
81b8176e
WYG		 175}
176
741a6266
WYG		 177/*
178 * Calibration
179 */
180static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
181{
182 struct iwl_calib_xtal_freq_cmd cmd;
183 __le16 *xtal_calib =
7944f8e4 184 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
741a6266 185
1f8bf039 186 iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
741a6266
WYG		 187 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
188 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
189 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
190 (u8 *)&cmd, sizeof(cmd));
191}
192
bf53f939
SZ		 193static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
194{
195 struct iwl_calib_temperature_offset_cmd cmd;
196 __le16 *offset_calib =
8d8854d9 197 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);
1f8bf039
WYG		 198
199 memset(&cmd, 0, sizeof(cmd));
200 iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
bf53f939
SZ		 201 cmd.radio_sensor_offset = le16_to_cpu(offset_calib[1]);
202 if (!(cmd.radio_sensor_offset))
203 cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
1f8bf039 204
bf53f939
SZ		 205 IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
206 cmd.radio_sensor_offset);
207 return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
208 (u8 *)&cmd, sizeof(cmd));
209}
210
741a6266
WYG		 211static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
212{
213 struct iwl_calib_cfg_cmd calib_cfg_cmd;
214 struct iwl_host_cmd cmd = {
215 .id = CALIBRATION_CFG_CMD,
3fa50738
JB		 216 .len = { sizeof(struct iwl_calib_cfg_cmd), },
217 .data = { &calib_cfg_cmd, },
741a6266
WYG		 218 };
219
220 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
221 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
222 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
223 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
224 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
225
226 return iwl_send_cmd(priv, &cmd);
227}
228
229void iwlagn_rx_calib_result(struct iwl_priv *priv,
230 struct iwl_rx_mem_buffer *rxb)
231{
232 struct iwl_rx_packet *pkt = rxb_addr(rxb);
233 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
234 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
235 int index;
236
237 /* reduce the size of the length field itself */
238 len -= 4;
239
240 /* Define the order in which the results will be sent to the runtime
241 * uCode. iwl_send_calib_results sends them in a row according to
242 * their index. We sort them here
243 */
244 switch (hdr->op_code) {
245 case IWL_PHY_CALIBRATE_DC_CMD:
246 index = IWL_CALIB_DC;
247 break;
248 case IWL_PHY_CALIBRATE_LO_CMD:
249 index = IWL_CALIB_LO;
250 break;
251 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
252 index = IWL_CALIB_TX_IQ;
253 break;
254 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
255 index = IWL_CALIB_TX_IQ_PERD;
256 break;
257 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
258 index = IWL_CALIB_BASE_BAND;
259 break;
260 default:
261 IWL_ERR(priv, "Unknown calibration notification %d\n",
262 hdr->op_code);
263 return;
264 }
265 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
266}
267
4613e72d 268int iwlagn_init_alive_start(struct iwl_priv *priv)
741a6266 269{
ca7966c8 270 int ret;
741a6266 271
7cb1b088
WYG		 272 if (priv->cfg->bt_params &&
273 priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f
WYG		 274 /*
275 * Tell uCode we are ready to perform calibration
276 * need to perform this before any calibration
277 * no need to close the envlope since we are going
278 * to load the runtime uCode later.
279 */
ca7966c8 280 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
f7322f8f 281 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
ca7966c8
JB		 282 if (ret)
283 return ret;
f7322f8f
WYG		 284
285 }
ca7966c8
JB		 286
287 ret = iwlagn_send_calib_cfg(priv);
288 if (ret)
289 return ret;
bf53f939
SZ		 290
291 /**
292 * temperature offset calibration is only needed for runtime ucode,
293 * so prepare the value now.
294 */
295 if (priv->cfg->need_temp_offset_calib)
ca7966c8 296 return iwlagn_set_temperature_offset_calib(priv);
741a6266 297
ca7966c8 298 return 0;
741a6266
WYG		 299}
300
f4012413
WYG		 301static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
302{
303 struct iwl_wimax_coex_cmd coex_cmd;
304
7cb1b088 305 if (priv->cfg->base_params->support_wimax_coexist) {
f4012413
WYG		 306 /* UnMask wake up src at associated sleep */
307 coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
308
309 /* UnMask wake up src at unassociated sleep */
310 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
311 memcpy(coex_cmd.sta_prio, cu_priorities,
312 sizeof(struct iwl_wimax_coex_event_entry) *
313 COEX_NUM_OF_EVENTS);
314
315 /* enabling the coexistence feature */
316 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
317
318 /* enabling the priorities tables */
319 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
320 } else {
321 /* coexistence is disabled */
322 memset(&coex_cmd, 0, sizeof(coex_cmd));
323 }
324 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
325 sizeof(coex_cmd), &coex_cmd);
326}
327
aeb4a2ee
WYG		 328static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
329 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
330 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
331 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
332 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
333 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
334 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
335 ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
336 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
337 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
338 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
339 ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
340 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
341 ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
342 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
343 ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
344 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
345 ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
346 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
347 0, 0, 0, 0, 0, 0, 0
348};
349
f7322f8f 350void iwlagn_send_prio_tbl(struct iwl_priv *priv)
aeb4a2ee
WYG		 351{
352 struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
353
354 memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
355 sizeof(iwlagn_bt_prio_tbl));
356 if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PRIO_TABLE,
357 sizeof(prio_tbl_cmd), &prio_tbl_cmd))
358 IWL_ERR(priv, "failed to send BT prio tbl command\n");
359}
360
ca7966c8 361int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
aeb4a2ee
WYG		 362{
363 struct iwl_bt_coex_prot_env_cmd env_cmd;
ca7966c8 364 int ret;
aeb4a2ee
WYG		 365
366 env_cmd.action = action;
367 env_cmd.type = type;
ca7966c8
JB		 368 ret = iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PROT_ENV,
369 sizeof(env_cmd), &env_cmd);
370 if (ret)
aeb4a2ee 371 IWL_ERR(priv, "failed to send BT env command\n");
ca7966c8 372 return ret;
aeb4a2ee
WYG		 373}
374
375
ca7966c8 376static int iwlagn_alive_notify(struct iwl_priv *priv)
741a6266 377{
cfa1da7e 378 const struct queue_to_fifo_ac *queue_to_fifo;
68b99311 379 struct iwl_rxon_context *ctx;
741a6266
WYG		 380 u32 a;
381 unsigned long flags;
382 int i, chan;
383 u32 reg_val;
7415952f 384 int ret;
741a6266
WYG		 385
386 spin_lock_irqsave(&priv->lock, flags);
387
f4388adc 388 priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
f86af7ba
WYG		 389 a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_MEM_LOWER_BOUND;
390 /* reset conext data memory */
391 for (; a < priv->scd_base_addr + IWLAGN_SCD_CONTEXT_MEM_UPPER_BOUND;
741a6266
WYG		 392 a += 4)
393 iwl_write_targ_mem(priv, a, 0);
f86af7ba
WYG		 394 /* reset tx status memory */
395 for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_MEM_UPPER_BOUND;
741a6266
WYG		 396 a += 4)
397 iwl_write_targ_mem(priv, a, 0);
398 for (; a < priv->scd_base_addr +
f4388adc 399 IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
741a6266
WYG		 400 iwl_write_targ_mem(priv, a, 0);
401
f4388adc 402 iwl_write_prph(priv, IWLAGN_SCD_DRAM_BASE_ADDR,
741a6266
WYG		 403 priv->scd_bc_tbls.dma >> 10);
404
405 /* Enable DMA channel */
406 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
407 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
408 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
409 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
410
411 /* Update FH chicken bits */
412 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
413 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
414 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
415
f4388adc 416 iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
13bb9483 417 IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv));
f4388adc 418 iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);
741a6266
WYG		 419
420 /* initiate the queues */
421 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
f4388adc 422 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(i), 0);
741a6266
WYG		 423 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
424 iwl_write_targ_mem(priv, priv->scd_base_addr +
f4388adc 425 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
741a6266 426 iwl_write_targ_mem(priv, priv->scd_base_addr +
f4388adc 427 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i) +
741a6266
WYG		 428 sizeof(u32),
429 ((SCD_WIN_SIZE <<
f4388adc
WYG		 430 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
431 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
741a6266 432 ((SCD_FRAME_LIMIT <<
f4388adc
WYG		 433 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
434 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
741a6266
WYG		 435 }
436
f4388adc 437 iwl_write_prph(priv, IWLAGN_SCD_INTERRUPT_MASK,
741a6266
WYG		 438 IWL_MASK(0, priv->hw_params.max_txq_num));
439
440 /* Activate all Tx DMA/FIFO channels */
214d14d4 441 iwlagn_txq_set_sched(priv, IWL_MASK(0, 7));
741a6266 442
13bb9483
JB		 443 /* map queues to FIFOs */
444 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
76f379ce 445 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
13bb9483 446 else
76f379ce 447 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
13bb9483
JB		 448
449 iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);
741a6266
WYG		 450
451 /* make sure all queue are not stopped */
452 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
453 for (i = 0; i < 4; i++)
454 atomic_set(&priv->queue_stop_count[i], 0);
68b99311
GT		 455 for_each_context(priv, ctx)
456 ctx->last_tx_rejected = false;
741a6266
WYG		 457
458 /* reset to 0 to enable all the queue first */
459 priv->txq_ctx_active_msk = 0;
13bb9483 460
741a6266 461 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
13bb9483 462 BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
741a6266 463
13bb9483 464 for (i = 0; i < 10; i++) {
cfa1da7e
JB		 465 int fifo = queue_to_fifo[i].fifo;
466 int ac = queue_to_fifo[i].ac;
741a6266
WYG		 467
468 iwl_txq_ctx_activate(priv, i);
469
76f379ce 470 if (fifo == IWL_TX_FIFO_UNUSED)
741a6266
WYG		 471 continue;
472
cfa1da7e
JB		 473 if (ac != IWL_AC_UNSET)
474 iwl_set_swq_id(&priv->txq[i], ac, i);
76f379ce 475 iwlagn_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
741a6266
WYG		 476 }
477
478 spin_unlock_irqrestore(&priv->lock, flags);
479
e7cad69c
GE		 480 /* Enable L1-Active */
481 iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
482 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
483
7415952f
WYG		 484 ret = iwlagn_send_wimax_coex(priv);
485 if (ret)
486 return ret;
487
488 ret = iwlagn_set_Xtal_calib(priv);
489 if (ret)
490 return ret;
741a6266 491
36127db0 492 return iwl_send_calib_results(priv);
741a6266 493}
db41dd27
WYG		 494
495
496/**
497 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
498 * using sample data 100 bytes apart. If these sample points are good,
499 * it's a pretty good bet that everything between them is good, too.
500 */
35b1d92d
JB		 501static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
502 struct fw_desc *fw_desc)
db41dd27 503{
35b1d92d
JB		 504 __le32 *image = (__le32 *)fw_desc->v_addr;
505 u32 len = fw_desc->len;
db41dd27 506 u32 val;
db41dd27
WYG		 507 u32 i;
508
06bb8358 509 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
db41dd27
WYG		 510
511 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
512 /* read data comes through single port, auto-incr addr */
513 /* NOTE: Use the debugless read so we don't flood kernel log
514 * if IWL_DL_IO is set */
515 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
516 i + IWLAGN_RTC_INST_LOWER_BOUND);
02a7fa00 517 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
fb66216f
JB		 518 if (val != le32_to_cpu(*image))
519 return -EIO;
db41dd27
WYG		 520 }
521
fb66216f 522 return 0;
db41dd27
WYG		 523}
524
fb66216f 525static void iwl_print_mismatch_inst(struct iwl_priv *priv,
35b1d92d 526 struct fw_desc *fw_desc)
db41dd27 527{
35b1d92d
JB		 528 __le32 *image = (__le32 *)fw_desc->v_addr;
529 u32 len = fw_desc->len;
db41dd27 530 u32 val;
fb66216f
JB		 531 u32 offs;
532 int errors = 0;
db41dd27 533
06bb8358 534 IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
db41dd27
WYG		 535
536 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
537 IWLAGN_RTC_INST_LOWER_BOUND);
538
fb66216f
JB		 539 for (offs = 0;
540 offs < len && errors < 20;
541 offs += sizeof(u32), image++) {
db41dd27 542 /* read data comes through single port, auto-incr addr */
02a7fa00 543 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
db41dd27 544 if (val != le32_to_cpu(*image)) {
fb66216f
JB		 545 IWL_ERR(priv, "uCode INST section at "
546 "offset 0x%x, is 0x%x, s/b 0x%x\n",
547 offs, val, le32_to_cpu(*image));
548 errors++;
db41dd27
WYG		 549 }
550 }
db41dd27
WYG		 551}
552
553/**
554 * iwl_verify_ucode - determine which instruction image is in SRAM,
555 * and verify its contents
556 */
dbf28e21 557static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
db41dd27 558{
dbf28e21 559 if (!iwlcore_verify_inst_sparse(priv, &img->code)) {
06bb8358 560 IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
db41dd27
WYG		 561 return 0;
562 }
563
35b1d92d 564 IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
fb66216f 565
dbf28e21 566 iwl_print_mismatch_inst(priv, &img->code);
fb66216f 567 return -EIO;
db41dd27 568}
ca7966c8
JB		 569
570struct iwlagn_alive_data {
571 bool valid;
572 u8 subtype;
573};
574
575static void iwlagn_alive_fn(struct iwl_priv *priv,
576 struct iwl_rx_packet *pkt,
577 void *data)
578{
579 struct iwlagn_alive_data *alive_data = data;
580 struct iwl_alive_resp *palive;
581
582 palive = &pkt->u.alive_frame;
583
06bb8358 584 IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
ca7966c8
JB		 585 "0x%01X 0x%01X\n",
586 palive->is_valid, palive->ver_type,
587 palive->ver_subtype);
588
589 priv->device_pointers.error_event_table =
590 le32_to_cpu(palive->error_event_table_ptr);
591 priv->device_pointers.log_event_table =
592 le32_to_cpu(palive->log_event_table_ptr);
593
594 alive_data->subtype = palive->ver_subtype;
595 alive_data->valid = palive->is_valid == UCODE_VALID_OK;
596}
597
598#define UCODE_ALIVE_TIMEOUT HZ
599#define UCODE_CALIB_TIMEOUT (2*HZ)
600
601int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
dbf28e21 602 struct fw_img *image,
872907bb 603 enum iwlagn_ucode_type ucode_type)
ca7966c8
JB		 604{
605 struct iwl_notification_wait alive_wait;
606 struct iwlagn_alive_data alive_data;
607 int ret;
872907bb 608 enum iwlagn_ucode_type old_type;
ca7966c8
JB		 609
610 ret = iwlagn_start_device(priv);
611 if (ret)
612 return ret;
613
614 iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
615 iwlagn_alive_fn, &alive_data);
616
617 old_type = priv->ucode_type;
872907bb 618 priv->ucode_type = ucode_type;
ca7966c8 619
dbf28e21 620 ret = iwlagn_load_given_ucode(priv, image);
ca7966c8
JB		 621 if (ret) {
622 priv->ucode_type = old_type;
623 iwlagn_remove_notification(priv, &alive_wait);
624 return ret;
625 }
626
627 /* Remove all resets to allow NIC to operate */
628 iwl_write32(priv, CSR_RESET, 0);
629
630 /*
631 * Some things may run in the background now, but we
632 * just wait for the ALIVE notification here.
633 */
634 ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
635 if (ret) {
636 priv->ucode_type = old_type;
637 return ret;
638 }
639
640 if (!alive_data.valid) {
641 IWL_ERR(priv, "Loaded ucode is not valid!\n");
642 priv->ucode_type = old_type;
643 return -EIO;
644 }
645
dbf28e21 646 ret = iwl_verify_ucode(priv, image);
ca7966c8
JB		 647 if (ret) {
648 priv->ucode_type = old_type;
649 return ret;
650 }
651
652 /* delay a bit to give rfkill time to run */
653 msleep(5);
654
655 ret = iwlagn_alive_notify(priv);
656 if (ret) {
657 IWL_WARN(priv,
658 "Could not complete ALIVE transition: %d\n", ret);
659 priv->ucode_type = old_type;
660 return ret;
661 }
662
663 return 0;
664}
665
666int iwlagn_run_init_ucode(struct iwl_priv *priv)
667{
668 struct iwl_notification_wait calib_wait;
669 int ret;
670
671 lockdep_assert_held(&priv->mutex);
672
673 /* No init ucode required? Curious, but maybe ok */
dbf28e21 674 if (!priv->ucode_init.code.len)
ca7966c8
JB		 675 return 0;
676
872907bb 677 if (priv->ucode_type != IWL_UCODE_NONE)
ca7966c8
JB		 678 return 0;
679
680 iwlagn_init_notification_wait(priv, &calib_wait,
681 CALIBRATION_COMPLETE_NOTIFICATION,
682 NULL, NULL);
683
684 /* Will also start the device */
685 ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
872907bb 686 IWL_UCODE_INIT);
ca7966c8
JB		 687 if (ret)
688 goto error;
689
690 ret = iwlagn_init_alive_start(priv);
691 if (ret)
692 goto error;
693
694 /*
695 * Some things may run in the background now, but we
696 * just wait for the calibration complete notification.
697 */
698 ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
699
700 goto out;
701
702 error:
703 iwlagn_remove_notification(priv, &calib_wait);
704 out:
705 /* Whatever happened, stop the device */
706 iwlagn_stop_device(priv);
707 return ret;
708}
Linux kernel - Deliverables
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