[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-ucode.c

/******************************************************************************
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>

#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-helpers.h"
#include "iwl-agn-hw.h"
#include "iwl-agn.h"

static const s8 iwlagn_default_queue_to_tx_fifo[] = {
	IWL_TX_FIFO_VO,
	IWL_TX_FIFO_VI,
	IWL_TX_FIFO_BE,
	IWL_TX_FIFO_BK,
	IWLAGN_CMD_FIFO_NUM,
	IWL_TX_FIFO_UNUSED,
	IWL_TX_FIFO_UNUSED,
	IWL_TX_FIFO_UNUSED,
	IWL_TX_FIFO_UNUSED,
	IWL_TX_FIFO_UNUSED,
};

static const s8 iwlagn_ipan_queue_to_tx_fifo[] = {
	IWL_TX_FIFO_VO,
	IWL_TX_FIFO_VI,
	IWL_TX_FIFO_BE,
	IWL_TX_FIFO_BK,
	IWL_TX_FIFO_BK_IPAN,
	IWL_TX_FIFO_BE_IPAN,
	IWL_TX_FIFO_VI_IPAN,
	IWL_TX_FIFO_VO_IPAN,
	IWL_TX_FIFO_BE_IPAN,
	IWLAGN_CMD_FIFO_NUM,
};

static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
	{COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
	 0, COEX_UNASSOC_IDLE_FLAGS},
	{COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
	 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
	{COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
	 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
	{COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
	 0, COEX_CALIBRATION_FLAGS},
	{COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
	 0, COEX_PERIODIC_CALIBRATION_FLAGS},
	{COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
	 0, COEX_CONNECTION_ESTAB_FLAGS},
	{COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
	 0, COEX_ASSOCIATED_IDLE_FLAGS},
	{COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
	 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
	{COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
	 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
	{COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
	 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
	{COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
	{COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
	{COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
	 0, COEX_STAND_ALONE_DEBUG_FLAGS},
	{COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
	 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
	{COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
	{COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
};

/*
 * ucode
 */
static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
				struct fw_desc *image, u32 dst_addr)
{
	dma_addr_t phy_addr = image->p_addr;
	u32 byte_cnt = image->len;
	int ret;

	priv->ucode_write_complete = 0;

	iwl_write_direct32(priv,
		FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);

	iwl_write_direct32(priv,
		FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);

	iwl_write_direct32(priv,
		FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
		phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);

	iwl_write_direct32(priv,
		FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
		(iwl_get_dma_hi_addr(phy_addr)
			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);

	iwl_write_direct32(priv,
		FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
		1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
		1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
		FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);

	iwl_write_direct32(priv,
		FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE	|
		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE	|
		FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);

	IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
	ret = wait_event_interruptible_timeout(priv->wait_command_queue,
					priv->ucode_write_complete, 5 * HZ);
	if (ret == -ERESTARTSYS) {
		IWL_ERR(priv, "Could not load the %s uCode section due "
			"to interrupt\n", name);
		return ret;
	}
	if (!ret) {
		IWL_ERR(priv, "Could not load the %s uCode section\n",
			name);
		return -ETIMEDOUT;
	}

	return 0;
}

static int iwlagn_load_given_ucode(struct iwl_priv *priv,
		struct fw_desc *inst_image,
		struct fw_desc *data_image)
{
	int ret = 0;

	ret = iwlagn_load_section(priv, "INST", inst_image,
				   IWLAGN_RTC_INST_LOWER_BOUND);
	if (ret)
		return ret;

	return iwlagn_load_section(priv, "DATA", data_image,
				    IWLAGN_RTC_DATA_LOWER_BOUND);
}

int iwlagn_load_ucode(struct iwl_priv *priv)
{
	int ret = 0;

	/* check whether init ucode should be loaded, or rather runtime ucode */
	if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
		IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
		ret = iwlagn_load_given_ucode(priv,
			&priv->ucode_init, &priv->ucode_init_data);
		if (!ret) {
			IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
			priv->ucode_type = UCODE_INIT;
		}
	} else {
		IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
			"Loading runtime ucode...\n");
		ret = iwlagn_load_given_ucode(priv,
			&priv->ucode_code, &priv->ucode_data);
		if (!ret) {
			IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
			priv->ucode_type = UCODE_RT;
		}
	}

	return ret;
}

/*
 *  Calibration
 */
static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
{
	struct iwl_calib_xtal_freq_cmd cmd;
	__le16 *xtal_calib =
		(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);

	cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
	cmd.hdr.first_group = 0;
	cmd.hdr.groups_num = 1;
	cmd.hdr.data_valid = 1;
	cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
	cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
	return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
			     (u8 *)&cmd, sizeof(cmd));
}

static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
{
	struct iwl_calib_cfg_cmd calib_cfg_cmd;
	struct iwl_host_cmd cmd = {
		.id = CALIBRATION_CFG_CMD,
		.len = sizeof(struct iwl_calib_cfg_cmd),
		.data = &calib_cfg_cmd,
	};

	memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
	calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
	calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
	calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
	calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;

	return iwl_send_cmd(priv, &cmd);
}

void iwlagn_rx_calib_result(struct iwl_priv *priv,
			     struct iwl_rx_mem_buffer *rxb)
{
	struct iwl_rx_packet *pkt = rxb_addr(rxb);
	struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
	int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
	int index;

	/* reduce the size of the length field itself */
	len -= 4;

	/* Define the order in which the results will be sent to the runtime
	 * uCode. iwl_send_calib_results sends them in a row according to
	 * their index. We sort them here
	 */
	switch (hdr->op_code) {
	case IWL_PHY_CALIBRATE_DC_CMD:
		index = IWL_CALIB_DC;
		break;
	case IWL_PHY_CALIBRATE_LO_CMD:
		index = IWL_CALIB_LO;
		break;
	case IWL_PHY_CALIBRATE_TX_IQ_CMD:
		index = IWL_CALIB_TX_IQ;
		break;
	case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
		index = IWL_CALIB_TX_IQ_PERD;
		break;
	case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
		index = IWL_CALIB_BASE_BAND;
		break;
	default:
		IWL_ERR(priv, "Unknown calibration notification %d\n",
			  hdr->op_code);
		return;
	}
	iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
}

void iwlagn_rx_calib_complete(struct iwl_priv *priv,
			       struct iwl_rx_mem_buffer *rxb)
{
	IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
	queue_work(priv->workqueue, &priv->restart);
}

void iwlagn_init_alive_start(struct iwl_priv *priv)
{
	int ret = 0;

	/* Check alive response for "valid" sign from uCode */
	if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
		/* We had an error bringing up the hardware, so take it
		 * all the way back down so we can try again */
		IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
		goto restart;
	}

	/* initialize uCode was loaded... verify inst image.
	 * This is a paranoid check, because we would not have gotten the
	 * "initialize" alive if code weren't properly loaded.  */
	if (iwl_verify_ucode(priv)) {
		/* Runtime instruction load was bad;
		 * take it all the way back down so we can try again */
		IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
		goto restart;
	}

	ret = priv->cfg->ops->lib->alive_notify(priv);
	if (ret) {
		IWL_WARN(priv,
			"Could not complete ALIVE transition: %d\n", ret);
		goto restart;
	}

	if (priv->cfg->advanced_bt_coexist) {
		/*
		 * Tell uCode we are ready to perform calibration
		 * need to perform this before any calibration
		 * no need to close the envlope since we are going
		 * to load the runtime uCode later.
		 */
		iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
			BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);

	}
	iwlagn_send_calib_cfg(priv);
	return;

restart:
	/* real restart (first load init_ucode) */
	queue_work(priv->workqueue, &priv->restart);
}

static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
{
	struct iwl_wimax_coex_cmd coex_cmd;

	if (priv->cfg->support_wimax_coexist) {
		/* UnMask wake up src at associated sleep */
		coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;

		/* UnMask wake up src at unassociated sleep */
		coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
		memcpy(coex_cmd.sta_prio, cu_priorities,
			sizeof(struct iwl_wimax_coex_event_entry) *
			 COEX_NUM_OF_EVENTS);

		/* enabling the coexistence feature */
		coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;

		/* enabling the priorities tables */
		coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
	} else {
		/* coexistence is disabled */
		memset(&coex_cmd, 0, sizeof(coex_cmd));
	}
	return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
				sizeof(coex_cmd), &coex_cmd);
}

static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	0, 0, 0, 0, 0, 0, 0
};

void iwlagn_send_prio_tbl(struct iwl_priv *priv)
{
	struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;

	memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
		sizeof(iwlagn_bt_prio_tbl));
	if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PRIO_TABLE,
				sizeof(prio_tbl_cmd), &prio_tbl_cmd))
		IWL_ERR(priv, "failed to send BT prio tbl command\n");
}

void iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
{
	struct iwl_bt_coex_prot_env_cmd env_cmd;

	env_cmd.action = action;
	env_cmd.type = type;
	if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PROT_ENV,
			     sizeof(env_cmd), &env_cmd))
		IWL_ERR(priv, "failed to send BT env command\n");
}


int iwlagn_alive_notify(struct iwl_priv *priv)
{
	const s8 *queues;
	u32 a;
	unsigned long flags;
	int i, chan;
	u32 reg_val;

	spin_lock_irqsave(&priv->lock, flags);

	priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
	a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_DATA_OFFSET;
	for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_BITMAP_OFFSET;
		a += 4)
		iwl_write_targ_mem(priv, a, 0);
	for (; a < priv->scd_base_addr + IWLAGN_SCD_TRANSLATE_TBL_OFFSET;
		a += 4)
		iwl_write_targ_mem(priv, a, 0);
	for (; a < priv->scd_base_addr +
	       IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
		iwl_write_targ_mem(priv, a, 0);

	iwl_write_prph(priv, IWLAGN_SCD_DRAM_BASE_ADDR,
		       priv->scd_bc_tbls.dma >> 10);

	/* Enable DMA channel */
	for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
		iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
				FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
				FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);

	/* Update FH chicken bits */
	reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
	iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
			   reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);

	iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
		IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv));
	iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);

	/* initiate the queues */
	for (i = 0; i < priv->hw_params.max_txq_num; i++) {
		iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(i), 0);
		iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
		iwl_write_targ_mem(priv, priv->scd_base_addr +
				IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
		iwl_write_targ_mem(priv, priv->scd_base_addr +
				IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i) +
				sizeof(u32),
				((SCD_WIN_SIZE <<
				IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
				IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
				((SCD_FRAME_LIMIT <<
				IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
				IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
	}

	iwl_write_prph(priv, IWLAGN_SCD_INTERRUPT_MASK,
			IWL_MASK(0, priv->hw_params.max_txq_num));

	/* Activate all Tx DMA/FIFO channels */
	priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));

	/* map queues to FIFOs */
	if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
		queues = iwlagn_ipan_queue_to_tx_fifo;
	else
		queues = iwlagn_default_queue_to_tx_fifo;

	iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);

	/* make sure all queue are not stopped */
	memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
	for (i = 0; i < 4; i++)
		atomic_set(&priv->queue_stop_count[i], 0);

	/* reset to 0 to enable all the queue first */
	priv->txq_ctx_active_msk = 0;

	BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
	BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);

	for (i = 0; i < 10; i++) {
		int ac = queues[i];

		iwl_txq_ctx_activate(priv, i);

		if (ac == IWL_TX_FIFO_UNUSED)
			continue;

		iwlagn_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
	}

	spin_unlock_irqrestore(&priv->lock, flags);

	iwlagn_send_wimax_coex(priv);

	iwlagn_set_Xtal_calib(priv);
	iwl_send_calib_results(priv);

	return 0;
}


/**
 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
 *   using sample data 100 bytes apart.  If these sample points are good,
 *   it's a pretty good bet that everything between them is good, too.
 */
static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
{
	u32 val;
	int ret = 0;
	u32 errcnt = 0;
	u32 i;

	IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);

	for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
		/* read data comes through single port, auto-incr addr */
		/* NOTE: Use the debugless read so we don't flood kernel log
		 * if IWL_DL_IO is set */
		iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
			i + IWLAGN_RTC_INST_LOWER_BOUND);
		val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
		if (val != le32_to_cpu(*image)) {
			ret = -EIO;
			errcnt++;
			if (errcnt >= 3)
				break;
		}
	}

	return ret;
}

/**
 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
 *     looking at all data.
 */
static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
				 u32 len)
{
	u32 val;
	u32 save_len = len;
	int ret = 0;
	u32 errcnt;

	IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);

	iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
			   IWLAGN_RTC_INST_LOWER_BOUND);

	errcnt = 0;
	for (; len > 0; len -= sizeof(u32), image++) {
		/* read data comes through single port, auto-incr addr */
		/* NOTE: Use the debugless read so we don't flood kernel log
		 * if IWL_DL_IO is set */
		val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
		if (val != le32_to_cpu(*image)) {
			IWL_ERR(priv, "uCode INST section is invalid at "
				  "offset 0x%x, is 0x%x, s/b 0x%x\n",
				  save_len - len, val, le32_to_cpu(*image));
			ret = -EIO;
			errcnt++;
			if (errcnt >= 20)
				break;
		}
	}

	if (!errcnt)
		IWL_DEBUG_INFO(priv,
		    "ucode image in INSTRUCTION memory is good\n");

	return ret;
}

/**
 * iwl_verify_ucode - determine which instruction image is in SRAM,
 *    and verify its contents
 */
int iwl_verify_ucode(struct iwl_priv *priv)
{
	__le32 *image;
	u32 len;
	int ret;

	/* Try bootstrap */
	image = (__le32 *)priv->ucode_boot.v_addr;
	len = priv->ucode_boot.len;
	ret = iwlcore_verify_inst_sparse(priv, image, len);
	if (!ret) {
		IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
		return 0;
	}

	/* Try initialize */
	image = (__le32 *)priv->ucode_init.v_addr;
	len = priv->ucode_init.len;
	ret = iwlcore_verify_inst_sparse(priv, image, len);
	if (!ret) {
		IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
		return 0;
	}

	/* Try runtime/protocol */
	image = (__le32 *)priv->ucode_code.v_addr;
	len = priv->ucode_code.len;
	ret = iwlcore_verify_inst_sparse(priv, image, len);
	if (!ret) {
		IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
		return 0;
	}

	IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");

	/* Since nothing seems to match, show first several data entries in
	 * instruction SRAM, so maybe visual inspection will give a clue.
	 * Selection of bootstrap image (vs. other images) is arbitrary. */
	image = (__le32 *)priv->ucode_boot.v_addr;
	len = priv->ucode_boot.len;
	ret = iwl_verify_inst_full(priv, image, len);

	return ret;
}
Commit	Line	Data
792bc3cb WYG	1	/******************************************************************************
	2	*
	3	* GPL LICENSE SUMMARY
	4	*
	5	* Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of version 2 of the GNU General Public License as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
	19	* USA
	20	*
	21	* The full GNU General Public License is included in this distribution
	22	* in the file called LICENSE.GPL.
	23	*
	24	* Contact Information:
	25	* Intel Linux Wireless <ilw@linux.intel.com>
	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*
	28	*****************************************************************************/
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
	32	#include <linux/init.h>
81b8176e	33	#include <linux/sched.h>
792bc3cb WYG	34
	35	#include "iwl-dev.h"
	36	#include "iwl-core.h"
81b8176e	37	#include "iwl-io.h"
741a6266	38	#include "iwl-helpers.h"
19e6cda0	39	#include "iwl-agn-hw.h"
741a6266 WYG	40	#include "iwl-agn.h"
	41
	42	static const s8 iwlagn_default_queue_to_tx_fifo[] = {
	43	IWL_TX_FIFO_VO,
	44	IWL_TX_FIFO_VI,
	45	IWL_TX_FIFO_BE,
	46	IWL_TX_FIFO_BK,
	47	IWLAGN_CMD_FIFO_NUM,
	48	IWL_TX_FIFO_UNUSED,
	49	IWL_TX_FIFO_UNUSED,
	50	IWL_TX_FIFO_UNUSED,
	51	IWL_TX_FIFO_UNUSED,
	52	IWL_TX_FIFO_UNUSED,
	53	};
81b8176e	54
13bb9483 JB	55	static const s8 iwlagn_ipan_queue_to_tx_fifo[] = {
	56	IWL_TX_FIFO_VO,
	57	IWL_TX_FIFO_VI,
	58	IWL_TX_FIFO_BE,
	59	IWL_TX_FIFO_BK,
751ca305 JB	60	IWL_TX_FIFO_BK_IPAN,
	61	IWL_TX_FIFO_BE_IPAN,
	62	IWL_TX_FIFO_VI_IPAN,
	63	IWL_TX_FIFO_VO_IPAN,
	64	IWL_TX_FIFO_BE_IPAN,
13bb9483 JB	65	IWLAGN_CMD_FIFO_NUM,
	66	};
	67
f4012413 WYG	68	static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
	69	{COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
	70	0, COEX_UNASSOC_IDLE_FLAGS},
	71	{COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
	72	0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
	73	{COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
	74	0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
	75	{COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
	76	0, COEX_CALIBRATION_FLAGS},
	77	{COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
	78	0, COEX_PERIODIC_CALIBRATION_FLAGS},
	79	{COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
	80	0, COEX_CONNECTION_ESTAB_FLAGS},
	81	{COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
	82	0, COEX_ASSOCIATED_IDLE_FLAGS},
	83	{COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
	84	0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
	85	{COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
	86	0, COEX_ASSOC_AUTO_SCAN_FLAGS},
	87	{COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
	88	0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
	89	{COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
	90	{COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
	91	{COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
	92	0, COEX_STAND_ALONE_DEBUG_FLAGS},
	93	{COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
	94	0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
	95	{COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
	96	{COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
	97	};
	98
81b8176e WYG	99	/*
	100	* ucode
	101	*/
	102	static int iwlagn_load_section(struct iwl_priv priv, const char name,
	103	struct fw_desc *image, u32 dst_addr)
	104	{
	105	dma_addr_t phy_addr = image->p_addr;
	106	u32 byte_cnt = image->len;
	107	int ret;
	108
	109	priv->ucode_write_complete = 0;
	110
	111	iwl_write_direct32(priv,
	112	FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
	113	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
	114
	115	iwl_write_direct32(priv,
	116	FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
	117
	118	iwl_write_direct32(priv,
	119	FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
	120	phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
	121
	122	iwl_write_direct32(priv,
	123	FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
	124	(iwl_get_dma_hi_addr(phy_addr)
	125	<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) \| byte_cnt);
	126
	127	iwl_write_direct32(priv,
	128	FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
	129	1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM \|
	130	1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX \|
	131	FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
	132
	133	iwl_write_direct32(priv,
	134	FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
	135	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \|
	136	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE \|
	137	FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
	138
	139	IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
	140	ret = wait_event_interruptible_timeout(priv->wait_command_queue,
	141	priv->ucode_write_complete, 5 * HZ);
	142	if (ret == -ERESTARTSYS) {
	143	IWL_ERR(priv, "Could not load the %s uCode section due "
	144	"to interrupt\n", name);
	145	return ret;
	146	}
	147	if (!ret) {
	148	IWL_ERR(priv, "Could not load the %s uCode section\n",
	149	name);
	150	return -ETIMEDOUT;
	151	}
	152
	153	return 0;
	154	}
	155
	156	static int iwlagn_load_given_ucode(struct iwl_priv *priv,
	157	struct fw_desc *inst_image,
	158	struct fw_desc *data_image)
	159	{
	160	int ret = 0;
	161
	162	ret = iwlagn_load_section(priv, "INST", inst_image,
19e6cda0	163	IWLAGN_RTC_INST_LOWER_BOUND);
81b8176e WYG	164	if (ret)
	165	return ret;
	166
	167	return iwlagn_load_section(priv, "DATA", data_image,
19e6cda0	168	IWLAGN_RTC_DATA_LOWER_BOUND);
81b8176e WYG	169	}
	170
	171	int iwlagn_load_ucode(struct iwl_priv *priv)
	172	{
	173	int ret = 0;
	174
	175	/* check whether init ucode should be loaded, or rather runtime ucode */
	176	if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
	177	IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
	178	ret = iwlagn_load_given_ucode(priv,
	179	&priv->ucode_init, &priv->ucode_init_data);
	180	if (!ret) {
	181	IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
	182	priv->ucode_type = UCODE_INIT;
	183	}
	184	} else {
	185	IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
	186	"Loading runtime ucode...\n");
	187	ret = iwlagn_load_given_ucode(priv,
	188	&priv->ucode_code, &priv->ucode_data);
	189	if (!ret) {
	190	IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
	191	priv->ucode_type = UCODE_RT;
	192	}
	193	}
	194
	195	return ret;
	196	}
792bc3cb	197
741a6266 WYG	198	/*
	199	* Calibration
	200	*/
	201	static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
	202	{
	203	struct iwl_calib_xtal_freq_cmd cmd;
	204	__le16 *xtal_calib =
7944f8e4	205	(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
741a6266 WYG	206
	207	cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
	208	cmd.hdr.first_group = 0;
	209	cmd.hdr.groups_num = 1;
	210	cmd.hdr.data_valid = 1;
	211	cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
	212	cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
	213	return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
	214	(u8 *)&cmd, sizeof(cmd));
	215	}
	216
	217	static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
	218	{
	219	struct iwl_calib_cfg_cmd calib_cfg_cmd;
	220	struct iwl_host_cmd cmd = {
	221	.id = CALIBRATION_CFG_CMD,
	222	.len = sizeof(struct iwl_calib_cfg_cmd),
	223	.data = &calib_cfg_cmd,
	224	};
	225
	226	memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
	227	calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
	228	calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
	229	calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
	230	calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
	231
	232	return iwl_send_cmd(priv, &cmd);
	233	}
	234
	235	void iwlagn_rx_calib_result(struct iwl_priv *priv,
	236	struct iwl_rx_mem_buffer *rxb)
	237	{
	238	struct iwl_rx_packet *pkt = rxb_addr(rxb);
	239	struct iwl_calib_hdr hdr = (struct iwl_calib_hdr )pkt->u.raw;
	240	int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
	241	int index;
	242
	243	/* reduce the size of the length field itself */
	244	len -= 4;
	245
	246	/* Define the order in which the results will be sent to the runtime
	247	* uCode. iwl_send_calib_results sends them in a row according to
	248	* their index. We sort them here
	249	*/
	250	switch (hdr->op_code) {
	251	case IWL_PHY_CALIBRATE_DC_CMD:
	252	index = IWL_CALIB_DC;
	253	break;
	254	case IWL_PHY_CALIBRATE_LO_CMD:
	255	index = IWL_CALIB_LO;
	256	break;
	257	case IWL_PHY_CALIBRATE_TX_IQ_CMD:
	258	index = IWL_CALIB_TX_IQ;
	259	break;
	260	case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
	261	index = IWL_CALIB_TX_IQ_PERD;
	262	break;
	263	case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
	264	index = IWL_CALIB_BASE_BAND;
	265	break;
	266	default:
	267	IWL_ERR(priv, "Unknown calibration notification %d\n",
	268	hdr->op_code);
	269	return;
270	}
271	iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
272	}
273
274	void iwlagn_rx_calib_complete(struct iwl_priv *priv,
275	struct iwl_rx_mem_buffer *rxb)
276	{
277	IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
278	queue_work(priv->workqueue, &priv->restart);
279	}
280
281	void iwlagn_init_alive_start(struct iwl_priv *priv)
282	{
283	int ret = 0;
284
285	/* Check alive response for "valid" sign from uCode */
286	if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
287	/* We had an error bringing up the hardware, so take it
288	* all the way back down so we can try again */
289	IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
290	goto restart;
291	}
292
293	/* initialize uCode was loaded... verify inst image.
294	* This is a paranoid check, because we would not have gotten the
295	* "initialize" alive if code weren't properly loaded. */
296	if (iwl_verify_ucode(priv)) {
297	/* Runtime instruction load was bad;
298	* take it all the way back down so we can try again */
299	IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
300	goto restart;
301	}
302
303	ret = priv->cfg->ops->lib->alive_notify(priv);
304	if (ret) {
305	IWL_WARN(priv,
306	"Could not complete ALIVE transition: %d\n", ret);
307	goto restart;
308	}
309
f7322f8f WYG	310	if (priv->cfg->advanced_bt_coexist) {
	311	/*
	312	* Tell uCode we are ready to perform calibration
	313	* need to perform this before any calibration
	314	* no need to close the envlope since we are going
	315	* to load the runtime uCode later.
	316	*/
	317	iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
	318	BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
	319
	320	}
741a6266 WYG	321	iwlagn_send_calib_cfg(priv);
	322	return;
	323
	324	restart:
	325	/* real restart (first load init_ucode) */
	326	queue_work(priv->workqueue, &priv->restart);
	327	}
	328
f4012413 WYG	329	static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
	330	{
	331	struct iwl_wimax_coex_cmd coex_cmd;
	332
	333	if (priv->cfg->support_wimax_coexist) {
	334	/* UnMask wake up src at associated sleep */
	335	coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
	336
	337	/* UnMask wake up src at unassociated sleep */
	338	coex_cmd.flags \|= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
	339	memcpy(coex_cmd.sta_prio, cu_priorities,
	340	sizeof(struct iwl_wimax_coex_event_entry) *
	341	COEX_NUM_OF_EVENTS);
	342
	343	/* enabling the coexistence feature */
	344	coex_cmd.flags \|= COEX_FLAGS_COEX_ENABLE_MSK;
	345
	346	/* enabling the priorities tables */
	347	coex_cmd.flags \|= COEX_FLAGS_STA_TABLE_VALID_MSK;
	348	} else {
	349	/* coexistence is disabled */
	350	memset(&coex_cmd, 0, sizeof(coex_cmd));
	351	}
	352	return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
	353	sizeof(coex_cmd), &coex_cmd);
	354	}
	355
aeb4a2ee WYG	356	static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
	357	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	358	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	359	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	360	(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	361	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	362	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	363	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	364	(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	365	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	366	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	367	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	368	(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	369	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	370	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	371	((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	372	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	373	((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	374	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	375	0, 0, 0, 0, 0, 0, 0
	376	};
	377
f7322f8f	378	void iwlagn_send_prio_tbl(struct iwl_priv *priv)
aeb4a2ee WYG	379	{
	380	struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
	381
	382	memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
	383	sizeof(iwlagn_bt_prio_tbl));
	384	if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PRIO_TABLE,
	385	sizeof(prio_tbl_cmd), &prio_tbl_cmd))
	386	IWL_ERR(priv, "failed to send BT prio tbl command\n");
	387	}
	388
f7322f8f	389	void iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
aeb4a2ee WYG	390	{
	391	struct iwl_bt_coex_prot_env_cmd env_cmd;
	392
	393	env_cmd.action = action;
	394	env_cmd.type = type;
	395	if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PROT_ENV,
	396	sizeof(env_cmd), &env_cmd))
	397	IWL_ERR(priv, "failed to send BT env command\n");
	398	}
	399
	400
741a6266 WYG	401	int iwlagn_alive_notify(struct iwl_priv *priv)
741a6266 WYG	402	{
13bb9483	403	const s8 *queues;
741a6266 WYG	404	u32 a;
	405	unsigned long flags;
	406	int i, chan;
	407	u32 reg_val;
	408
	409	spin_lock_irqsave(&priv->lock, flags);
	410
f4388adc WYG	411	priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
	412	a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_DATA_OFFSET;
	413	for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_BITMAP_OFFSET;
741a6266 WYG	414	a += 4)
741a6266 WYG	415	iwl_write_targ_mem(priv, a, 0);
f4388adc	416	for (; a < priv->scd_base_addr + IWLAGN_SCD_TRANSLATE_TBL_OFFSET;
741a6266 WYG	417	a += 4)
	418	iwl_write_targ_mem(priv, a, 0);
	419	for (; a < priv->scd_base_addr +
f4388adc	420	IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
741a6266 WYG	421	iwl_write_targ_mem(priv, a, 0);
741a6266 WYG	422
f4388adc	423	iwl_write_prph(priv, IWLAGN_SCD_DRAM_BASE_ADDR,
741a6266 WYG	424	priv->scd_bc_tbls.dma >> 10);
	425
	426	/* Enable DMA channel */
	427	for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
	428	iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
	429	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \|
	430	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
	431
	432	/* Update FH chicken bits */
	433	reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
	434	iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
	435	reg_val \| FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
	436
f4388adc	437	iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
13bb9483	438	IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv));
f4388adc	439	iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);
741a6266 WYG	440
	441	/* initiate the queues */
	442	for (i = 0; i < priv->hw_params.max_txq_num; i++) {
f4388adc	443	iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(i), 0);
741a6266 WYG	444	iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 \| (i << 8));
741a6266 WYG	445	iwl_write_targ_mem(priv, priv->scd_base_addr +
f4388adc	446	IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
741a6266	447	iwl_write_targ_mem(priv, priv->scd_base_addr +
f4388adc	448	IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i) +
741a6266 WYG	449	sizeof(u32),
741a6266 WYG	450	((SCD_WIN_SIZE <<
f4388adc WYG	451	IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
f4388adc WYG	452	IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) \|
741a6266	453	((SCD_FRAME_LIMIT <<
f4388adc WYG	454	IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
f4388adc WYG	455	IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
741a6266 WYG	456	}
741a6266 WYG	457
f4388adc	458	iwl_write_prph(priv, IWLAGN_SCD_INTERRUPT_MASK,
741a6266 WYG	459	IWL_MASK(0, priv->hw_params.max_txq_num));
	460
	461	/* Activate all Tx DMA/FIFO channels */
	462	priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
	463
13bb9483 JB	464	/* map queues to FIFOs */
	465	if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
	466	queues = iwlagn_ipan_queue_to_tx_fifo;
	467	else
	468	queues = iwlagn_default_queue_to_tx_fifo;
	469
	470	iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);
741a6266 WYG	471
	472	/* make sure all queue are not stopped */
	473	memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
	474	for (i = 0; i < 4; i++)
	475	atomic_set(&priv->queue_stop_count[i], 0);
	476
	477	/* reset to 0 to enable all the queue first */
	478	priv->txq_ctx_active_msk = 0;
13bb9483	479
741a6266	480	BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
13bb9483	481	BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
741a6266	482
13bb9483 JB	483	for (i = 0; i < 10; i++) {
13bb9483 JB	484	int ac = queues[i];
741a6266 WYG	485
	486	iwl_txq_ctx_activate(priv, i);
	487
	488	if (ac == IWL_TX_FIFO_UNUSED)
	489	continue;
	490
	491	iwlagn_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
	492	}
	493
	494	spin_unlock_irqrestore(&priv->lock, flags);
	495
f4012413	496	iwlagn_send_wimax_coex(priv);
741a6266 WYG	497
	498	iwlagn_set_Xtal_calib(priv);
	499	iwl_send_calib_results(priv);
	500
	501	return 0;
	502	}
db41dd27 WYG	503
	504
	505	/**
	506	* iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
	507	* using sample data 100 bytes apart. If these sample points are good,
	508	* it's a pretty good bet that everything between them is good, too.
	509	*/
	510	static int iwlcore_verify_inst_sparse(struct iwl_priv priv, __le32 image, u32 len)
	511	{
	512	u32 val;
	513	int ret = 0;
	514	u32 errcnt = 0;
	515	u32 i;
	516
	517	IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
	518
	519	for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
	520	/* read data comes through single port, auto-incr addr */
	521	/* NOTE: Use the debugless read so we don't flood kernel log
	522	* if IWL_DL_IO is set */
	523	iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
	524	i + IWLAGN_RTC_INST_LOWER_BOUND);
	525	val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
	526	if (val != le32_to_cpu(*image)) {
	527	ret = -EIO;
	528	errcnt++;
	529	if (errcnt >= 3)
	530	break;
	531	}
	532	}
	533
	534	return ret;
	535	}
	536
	537	/**
	538	* iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
	539	* looking at all data.
	540	*/
	541	static int iwl_verify_inst_full(struct iwl_priv priv, __le32 image,
	542	u32 len)
	543	{
	544	u32 val;
	545	u32 save_len = len;
	546	int ret = 0;
	547	u32 errcnt;
	548
	549	IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
	550
	551	iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
	552	IWLAGN_RTC_INST_LOWER_BOUND);
	553
	554	errcnt = 0;
	555	for (; len > 0; len -= sizeof(u32), image++) {
	556	/* read data comes through single port, auto-incr addr */
	557	/* NOTE: Use the debugless read so we don't flood kernel log
	558	* if IWL_DL_IO is set */
	559	val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
	560	if (val != le32_to_cpu(*image)) {
	561	IWL_ERR(priv, "uCode INST section is invalid at "
	562	"offset 0x%x, is 0x%x, s/b 0x%x\n",
	563	save_len - len, val, le32_to_cpu(*image));
	564	ret = -EIO;
	565	errcnt++;
	566	if (errcnt >= 20)
567	break;
568	}
569	}
570
571	if (!errcnt)
572	IWL_DEBUG_INFO(priv,
573	"ucode image in INSTRUCTION memory is good\n");
574
575	return ret;
576	}
577
578	/**
579	* iwl_verify_ucode - determine which instruction image is in SRAM,
580	* and verify its contents
581	*/
582	int iwl_verify_ucode(struct iwl_priv *priv)
583	{
584	__le32 *image;
585	u32 len;
586	int ret;
587
588	/* Try bootstrap */
589	image = (__le32 *)priv->ucode_boot.v_addr;
590	len = priv->ucode_boot.len;
591	ret = iwlcore_verify_inst_sparse(priv, image, len);
592	if (!ret) {
593	IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
594	return 0;
595	}
596
597	/* Try initialize */
598	image = (__le32 *)priv->ucode_init.v_addr;
599	len = priv->ucode_init.len;
600	ret = iwlcore_verify_inst_sparse(priv, image, len);
601	if (!ret) {
602	IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
603	return 0;
604	}
605
606	/* Try runtime/protocol */
607	image = (__le32 *)priv->ucode_code.v_addr;
608	len = priv->ucode_code.len;
609	ret = iwlcore_verify_inst_sparse(priv, image, len);
610	if (!ret) {
611	IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
612	return 0;
613	}
614
615	IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
616
617	/* Since nothing seems to match, show first several data entries in
618	* instruction SRAM, so maybe visual inspection will give a clue.
619	* Selection of bootstrap image (vs. other images) is arbitrary. */
620	image = (__le32 *)priv->ucode_boot.v_addr;
621	len = priv->ucode_boot.len;
622	ret = iwl_verify_inst_full(priv, image, len);
623
624	return ret;
625	}