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iwlwifi: define structures and functions externally for customization
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
b481de9c
ZY		 40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
b481de9c
ZY		 43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO		 47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
b481de9c
ZY		 58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
b481de9c
ZY		 64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 70#define VD "d"
71#else
72#define VD
73#endif
74
4fc22b21 75#ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT
b481de9c
ZY		 76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
b481de9c
ZY		 83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
b481de9c
ZY		 92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
5b9f8cd3 105static int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY		 106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG		 109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
b481de9c
ZY		 115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
a326a5d0
EG		 118 /* allow CTS-to-self if possible. this is relevant only for
119 * 5000, but will not damage 4965 */
120 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
b481de9c 121
8ccde88a 122 ret = iwl_check_rxon_cmd(priv);
43d59b32 123 if (ret) {
15b1687c 124 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 125 return -EINVAL;
126 }
127
128 /* If we don't need to send a full RXON, we can use
5b9f8cd3 129 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 130 * and other flags for the current radio configuration. */
54559703 131 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG		 132 ret = iwl_send_rxon_assoc(priv);
133 if (ret) {
15b1687c 134 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 135 return ret;
b481de9c
ZY		 136 }
137
138 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
ZY		 139 return 0;
140 }
141
142 /* station table will be cleared */
143 priv->assoc_station_added = 0;
144
b481de9c
ZY		 145 /* If we are currently associated and the new config requires
146 * an RXON_ASSOC and the new config wants the associated mask enabled,
147 * we must clear the associated from the active configuration
148 * before we apply the new config */
43d59b32 149 if (iwl_is_associated(priv) && new_assoc) {
e1623446 150 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 151 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
152
43d59b32 153 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 154 sizeof(struct iwl_rxon_cmd),
b481de9c
ZY		 155 &priv->active_rxon);
156
157 /* If the mask clearing failed then we set
158 * active_rxon back to what it was previously */
43d59b32 159 if (ret) {
b481de9c 160 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 161 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 162 return ret;
b481de9c 163 }
b481de9c
ZY		 164 }
165
e1623446 166 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 167 "* with%s RXON_FILTER_ASSOC_MSK\n"
168 "* channel = %d\n"
e174961c 169 "* bssid = %pM\n",
43d59b32 170 (new_assoc ? "" : "out"),
b481de9c 171 le16_to_cpu(priv->staging_rxon.channel),
e174961c 172 priv->staging_rxon.bssid_addr);
b481de9c 173
5b9f8cd3 174 iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto);
43d59b32
EG		 175
176 /* Apply the new configuration
177 * RXON unassoc clears the station table in uCode, send it before
178 * we add the bcast station. If assoc bit is set, we will send RXON
179 * after having added the bcast and bssid station.
180 */
181 if (!new_assoc) {
182 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 183 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 184 if (ret) {
15b1687c 185 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 186 return ret;
187 }
188 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
ZY		 189 }
190
37deb2a0 191 iwl_clear_stations_table(priv);
556f8db7 192
b481de9c
ZY		 193 if (!priv->error_recovering)
194 priv->start_calib = 0;
195
b481de9c 196 /* Add the broadcast address so we can send broadcast frames */
4f40e4d9 197 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
43d59b32 198 IWL_INVALID_STATION) {
15b1687c 199 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
b481de9c
ZY		 200 return -EIO;
201 }
202
203 /* If we have set the ASSOC_MSK and we are in BSS mode then
204 * add the IWL_AP_ID to the station rate table */
9185159d 205 if (new_assoc) {
05c914fe 206 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW		 207 ret = iwl_rxon_add_station(priv,
208 priv->active_rxon.bssid_addr, 1);
209 if (ret == IWL_INVALID_STATION) {
15b1687c
WT		 210 IWL_ERR(priv,
211 "Error adding AP address for TX.\n");
9185159d
TW		 212 return -EIO;
213 }
214 priv->assoc_station_added = 1;
215 if (priv->default_wep_key &&
216 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT		 217 IWL_ERR(priv,
218 "Could not send WEP static key.\n");
b481de9c 219 }
43d59b32
EG		 220
221 /* Apply the new configuration
222 * RXON assoc doesn't clear the station table in uCode,
223 */
224 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
225 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
226 if (ret) {
15b1687c 227 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 228 return ret;
229 }
230 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
ZY		 231 }
232
36da7d70
ZY		 233 iwl_init_sensitivity(priv);
234
235 /* If we issue a new RXON command which required a tune then we must
236 * send a new TXPOWER command or we won't be able to Tx any frames */
237 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
238 if (ret) {
15b1687c 239 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 240 return ret;
241 }
242
b481de9c
ZY		 243 return 0;
244}
245
5b9f8cd3 246void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA		 247{
248
c7de35cd 249 iwl_set_rxon_chain(priv);
5b9f8cd3 250 iwl_commit_rxon(priv);
5da4b55f
MA		 251}
252
fcab423d 253static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 254{
255 struct list_head *element;
256
e1623446 257 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 258 priv->frames_count);
259
260 while (!list_empty(&priv->free_frames)) {
261 element = priv->free_frames.next;
262 list_del(element);
fcab423d 263 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 264 priv->frames_count--;
265 }
266
267 if (priv->frames_count) {
39aadf8c 268 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 269 priv->frames_count);
270 priv->frames_count = 0;
271 }
272}
273
fcab423d 274static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 275{
fcab423d 276 struct iwl_frame *frame;
b481de9c
ZY		 277 struct list_head *element;
278 if (list_empty(&priv->free_frames)) {
279 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
280 if (!frame) {
15b1687c 281 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 282 return NULL;
283 }
284
285 priv->frames_count++;
286 return frame;
287 }
288
289 element = priv->free_frames.next;
290 list_del(element);
fcab423d 291 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 292}
293
fcab423d 294static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 295{
296 memset(frame, 0, sizeof(*frame));
297 list_add(&frame->list, &priv->free_frames);
298}
299
4bf64efd
TW		 300static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
301 struct ieee80211_hdr *hdr,
73ec1cc2 302 int left)
b481de9c 303{
3109ece1 304 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 305 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
306 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 307 return 0;
308
309 if (priv->ibss_beacon->len > left)
310 return 0;
311
312 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
313
314 return priv->ibss_beacon->len;
315}
316
5b9f8cd3 317static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW		 318 struct iwl_frame *frame, u8 rate)
319{
320 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
321 unsigned int frame_size;
322
323 tx_beacon_cmd = &frame->u.beacon;
324 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
325
326 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
327 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
328
329 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW		 330 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
331
332 BUG_ON(frame_size > MAX_MPDU_SIZE);
333 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
334
335 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
336 tx_beacon_cmd->tx.rate_n_flags =
337 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
338 else
339 tx_beacon_cmd->tx.rate_n_flags =
340 iwl_hw_set_rate_n_flags(rate, 0);
341
342 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
343 TX_CMD_FLG_TSF_MSK |
344 TX_CMD_FLG_STA_RATE_MSK;
345
346 return sizeof(*tx_beacon_cmd) + frame_size;
347}
5b9f8cd3 348static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 349{
fcab423d 350 struct iwl_frame *frame;
b481de9c
ZY		 351 unsigned int frame_size;
352 int rc;
353 u8 rate;
354
fcab423d 355 frame = iwl_get_free_frame(priv);
b481de9c
ZY		 356
357 if (!frame) {
15b1687c 358 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 359 "command.\n");
360 return -ENOMEM;
361 }
362
5b9f8cd3 363 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 364
5b9f8cd3 365 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 366
857485c0 367 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 368 &frame->u.cmd[0]);
369
fcab423d 370 iwl_free_frame(priv, frame);
b481de9c
ZY		 371
372 return rc;
373}
374
7aaa1d79
SO		 375static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
376{
377 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
378
379 dma_addr_t addr = get_unaligned_le32(&tb->lo);
380 if (sizeof(dma_addr_t) > sizeof(u32))
381 addr |=
382 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
383
384 return addr;
385}
386
387static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
388{
389 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
390
391 return le16_to_cpu(tb->hi_n_len) >> 4;
392}
393
394static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
395 dma_addr_t addr, u16 len)
396{
397 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
398 u16 hi_n_len = len << 4;
399
400 put_unaligned_le32(addr, &tb->lo);
401 if (sizeof(dma_addr_t) > sizeof(u32))
402 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
403
404 tb->hi_n_len = cpu_to_le16(hi_n_len);
405
406 tfd->num_tbs = idx + 1;
407}
408
409static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
410{
411 return tfd->num_tbs & 0x1f;
412}
413
414/**
415 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
416 * @priv - driver private data
417 * @txq - tx queue
418 *
419 * Does NOT advance any TFD circular buffer read/write indexes
420 * Does NOT free the TFD itself (which is within circular buffer)
421 */
422void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
423{
59606ffa 424 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 425 struct iwl_tfd *tfd;
426 struct pci_dev *dev = priv->pci_dev;
427 int index = txq->q.read_ptr;
428 int i;
429 int num_tbs;
430
431 tfd = &tfd_tmp[index];
432
433 /* Sanity check on number of chunks */
434 num_tbs = iwl_tfd_get_num_tbs(tfd);
435
436 if (num_tbs >= IWL_NUM_OF_TBS) {
437 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
438 /* @todo issue fatal error, it is quite serious situation */
439 return;
440 }
441
442 /* Unmap tx_cmd */
443 if (num_tbs)
444 pci_unmap_single(dev,
445 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
446 pci_unmap_len(&txq->cmd[index]->meta, len),
447 PCI_DMA_TODEVICE);
448
449 /* Unmap chunks, if any. */
450 for (i = 1; i < num_tbs; i++) {
451 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
452 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
453
454 if (txq->txb) {
455 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
456 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
457 }
458 }
459}
460
461int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
462 struct iwl_tx_queue *txq,
463 dma_addr_t addr, u16 len,
464 u8 reset, u8 pad)
465{
466 struct iwl_queue *q;
59606ffa 467 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 468 u32 num_tbs;
469
470 q = &txq->q;
59606ffa
SO		 471 tfd_tmp = (struct iwl_tfd *)txq->tfds;
472 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 473
474 if (reset)
475 memset(tfd, 0, sizeof(*tfd));
476
477 num_tbs = iwl_tfd_get_num_tbs(tfd);
478
479 /* Each TFD can point to a maximum 20 Tx buffers */
480 if (num_tbs >= IWL_NUM_OF_TBS) {
481 IWL_ERR(priv, "Error can not send more than %d chunks\n",
482 IWL_NUM_OF_TBS);
483 return -EINVAL;
484 }
485
486 BUG_ON(addr & ~DMA_BIT_MASK(36));
487 if (unlikely(addr & ~IWL_TX_DMA_MASK))
488 IWL_ERR(priv, "Unaligned address = %llx\n",
489 (unsigned long long)addr);
490
491 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
492
493 return 0;
494}
495
a8e74e27
SO		 496/*
497 * Tell nic where to find circular buffer of Tx Frame Descriptors for
498 * given Tx queue, and enable the DMA channel used for that queue.
499 *
500 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
501 * channels supported in hardware.
502 */
503int iwl_hw_tx_queue_init(struct iwl_priv *priv,
504 struct iwl_tx_queue *txq)
505{
506 int ret;
507 unsigned long flags;
508 int txq_id = txq->q.id;
509
510 spin_lock_irqsave(&priv->lock, flags);
511 ret = iwl_grab_nic_access(priv);
512 if (ret) {
513 spin_unlock_irqrestore(&priv->lock, flags);
514 return ret;
515 }
516
517 /* Circular buffer (TFD queue in DRAM) physical base address */
518 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
519 txq->q.dma_addr >> 8);
520
521 iwl_release_nic_access(priv);
522 spin_unlock_irqrestore(&priv->lock, flags);
523
524 return 0;
525}
526
527
b481de9c
ZY		 528/******************************************************************************
529 *
530 * Misc. internal state and helper functions
531 *
532 ******************************************************************************/
b481de9c 533
5b9f8cd3 534static void iwl_ht_conf(struct iwl_priv *priv,
d1141dfb
EG		 535 struct ieee80211_bss_conf *bss_conf)
536{
ae5eb026 537 struct ieee80211_sta_ht_cap *ht_conf;
d1141dfb 538 struct iwl_ht_info *iwl_conf = &priv->current_ht_config;
ae5eb026 539 struct ieee80211_sta *sta;
d1141dfb 540
e1623446 541 IWL_DEBUG_MAC80211(priv, "enter: \n");
d1141dfb 542
d1141dfb
EG		 543 if (!iwl_conf->is_ht)
544 return;
545
ae5eb026
JB		 546
547 /*
548 * It is totally wrong to base global information on something
549 * that is valid only when associated, alas, this driver works
550 * that way and I don't know how to fix it.
551 */
552
553 rcu_read_lock();
554 sta = ieee80211_find_sta(priv->hw, priv->bssid);
555 if (!sta) {
556 rcu_read_unlock();
557 return;
558 }
559 ht_conf = &sta->ht_cap;
560
d1141dfb 561 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_20)
a9841013 562 iwl_conf->sgf |= HT_SHORT_GI_20MHZ;
d1141dfb 563 if (ht_conf->cap & IEEE80211_HT_CAP_SGI_40)
a9841013 564 iwl_conf->sgf |= HT_SHORT_GI_40MHZ;
d1141dfb
EG		 565
566 iwl_conf->is_green_field = !!(ht_conf->cap & IEEE80211_HT_CAP_GRN_FLD);
567 iwl_conf->max_amsdu_size =
568 !!(ht_conf->cap & IEEE80211_HT_CAP_MAX_AMSDU);
569
570 iwl_conf->supported_chan_width =
d9fe60de 571 !!(ht_conf->cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40);
ae5eb026 572
094d05dc
S		 573 /*
574 * XXX: The HT configuration needs to be moved into iwl_mac_config()
575 * to be done there correctly.
576 */
577
578 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE;
de27e64e 579 if (conf_is_ht40_minus(&priv->hw->conf))
094d05dc 580 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW;
de27e64e 581 else if (conf_is_ht40_plus(&priv->hw->conf))
094d05dc
S		 582 iwl_conf->extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
583
d1141dfb 584 /* If no above or below channel supplied disable FAT channel */
d9fe60de 585 if (iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_ABOVE &&
094d05dc 586 iwl_conf->extension_chan_offset != IEEE80211_HT_PARAM_CHA_SEC_BELOW)
d1141dfb
EG		 587 iwl_conf->supported_chan_width = 0;
588
12837be1
RR		 589 iwl_conf->sm_ps = (u8)((ht_conf->cap & IEEE80211_HT_CAP_SM_PS) >> 2);
590
d9fe60de 591 memcpy(&iwl_conf->mcs, &ht_conf->mcs, 16);
d1141dfb 592
094d05dc 593 iwl_conf->tx_chan_width = iwl_conf->supported_chan_width != 0;
d1141dfb 594 iwl_conf->ht_protection =
ae5eb026 595 bss_conf->ht.operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
d1141dfb 596 iwl_conf->non_GF_STA_present =
ae5eb026
JB		 597 !!(bss_conf->ht.operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
598
599 rcu_read_unlock();
d1141dfb 600
e1623446 601 IWL_DEBUG_MAC80211(priv, "leave\n");
d1141dfb
EG		 602}
603
b481de9c
ZY		 604/*
605 * QoS support
606*/
1ff50bda 607static void iwl_activate_qos(struct iwl_priv *priv, u8 force)
b481de9c 608{
b481de9c
ZY		 609 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
610 return;
611
b481de9c
ZY		 612 priv->qos_data.def_qos_parm.qos_flags = 0;
613
614 if (priv->qos_data.qos_cap.q_AP.queue_request &&
615 !priv->qos_data.qos_cap.q_AP.txop_request)
616 priv->qos_data.def_qos_parm.qos_flags |=
617 QOS_PARAM_FLG_TXOP_TYPE_MSK;
b481de9c
ZY		 618 if (priv->qos_data.qos_active)
619 priv->qos_data.def_qos_parm.qos_flags |=
620 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
621
fd105e79 622 if (priv->current_ht_config.is_ht)
f1f1f5c7 623 priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
f1f1f5c7 624
3109ece1 625 if (force || iwl_is_associated(priv)) {
e1623446 626 IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
f1f1f5c7
TW		 627 priv->qos_data.qos_active,
628 priv->qos_data.def_qos_parm.qos_flags);
b481de9c 629
1ff50bda
EG		 630 iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
631 sizeof(struct iwl_qosparam_cmd),
632 &priv->qos_data.def_qos_parm, NULL);
b481de9c
ZY		 633 }
634}
635
b481de9c 636#define MAX_UCODE_BEACON_INTERVAL 4096
b481de9c 637
3195c1f3 638static u16 iwl_adjust_beacon_interval(u16 beacon_val)
b481de9c
ZY		 639{
640 u16 new_val = 0;
641 u16 beacon_factor = 0;
642
3195c1f3
TW		 643 beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL)
644 / MAX_UCODE_BEACON_INTERVAL;
b481de9c
ZY		 645 new_val = beacon_val / beacon_factor;
646
3195c1f3 647 return new_val;
b481de9c
ZY		 648}
649
3195c1f3 650static void iwl_setup_rxon_timing(struct iwl_priv *priv)
b481de9c 651{
3195c1f3
TW		 652 u64 tsf;
653 s32 interval_tm, rem;
b481de9c
ZY		 654 unsigned long flags;
655 struct ieee80211_conf *conf = NULL;
656 u16 beacon_int = 0;
657
658 conf = ieee80211_get_hw_conf(priv->hw);
659
660 spin_lock_irqsave(&priv->lock, flags);
3195c1f3 661 priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
b5d7be5e 662 priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
b481de9c 663
05c914fe 664 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
3195c1f3 665 beacon_int = iwl_adjust_beacon_interval(priv->beacon_int);
b481de9c
ZY		 666 priv->rxon_timing.atim_window = 0;
667 } else {
3195c1f3
TW		 668 beacon_int = iwl_adjust_beacon_interval(conf->beacon_int);
669
b481de9c
ZY		 670 /* TODO: we need to get atim_window from upper stack
671 * for now we set to 0 */
672 priv->rxon_timing.atim_window = 0;
673 }
674
3195c1f3 675 priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
b481de9c 676
3195c1f3
TW		 677 tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
678 interval_tm = beacon_int * 1024;
679 rem = do_div(tsf, interval_tm);
680 priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
681
682 spin_unlock_irqrestore(&priv->lock, flags);
e1623446 683 IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n",
3195c1f3
TW		 684 le16_to_cpu(priv->rxon_timing.beacon_interval),
685 le32_to_cpu(priv->rxon_timing.beacon_init_val),
686 le16_to_cpu(priv->rxon_timing.atim_window));
b481de9c
ZY		 687}
688
5b9f8cd3 689static int iwl_set_mode(struct iwl_priv *priv, int mode)
b481de9c 690{
5b9f8cd3 691 iwl_connection_init_rx_config(priv, mode);
8ccde88a 692 iwl_set_rxon_chain(priv);
b481de9c
ZY		 693 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
694
37deb2a0 695 iwl_clear_stations_table(priv);
b481de9c 696
fde3571f 697 /* dont commit rxon if rf-kill is on*/
fee1247a 698 if (!iwl_is_ready_rf(priv))
fde3571f
MA		 699 return -EAGAIN;
700
701 cancel_delayed_work(&priv->scan_check);
2a421b91 702 if (iwl_scan_cancel_timeout(priv, 100)) {
39aadf8c 703 IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
e1623446 704 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
fde3571f
MA		 705 return -EAGAIN;
706 }
707
5b9f8cd3 708 iwl_commit_rxon(priv);
b481de9c
ZY		 709
710 return 0;
711}
712
b481de9c
ZY		 713/******************************************************************************
714 *
715 * Generic RX handler implementations
716 *
717 ******************************************************************************/
885ba202
TW		 718static void iwl_rx_reply_alive(struct iwl_priv *priv,
719 struct iwl_rx_mem_buffer *rxb)
b481de9c 720{
db11d634 721 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
885ba202 722 struct iwl_alive_resp *palive;
b481de9c
ZY		 723 struct delayed_work *pwork;
724
725 palive = &pkt->u.alive_frame;
726
e1623446 727 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 728 "0x%01X 0x%01X\n",
729 palive->is_valid, palive->ver_type,
730 palive->ver_subtype);
731
732 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 733 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 734 memcpy(&priv->card_alive_init,
735 &pkt->u.alive_frame,
885ba202 736 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 737 pwork = &priv->init_alive_start;
738 } else {
e1623446 739 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 740 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 741 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 742 pwork = &priv->alive_start;
743 }
744
745 /* We delay the ALIVE response by 5ms to
746 * give the HW RF Kill time to activate... */
747 if (palive->is_valid == UCODE_VALID_OK)
748 queue_delayed_work(priv->workqueue, pwork,
749 msecs_to_jiffies(5));
750 else
39aadf8c 751 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 752}
753
5b9f8cd3 754static void iwl_rx_reply_error(struct iwl_priv *priv,
a55360e4 755 struct iwl_rx_mem_buffer *rxb)
b481de9c 756{
db11d634 757 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c 758
15b1687c 759 IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
b481de9c
ZY		 760 "seq 0x%04X ser 0x%08X\n",
761 le32_to_cpu(pkt->u.err_resp.error_type),
762 get_cmd_string(pkt->u.err_resp.cmd_id),
763 pkt->u.err_resp.cmd_id,
764 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
765 le32_to_cpu(pkt->u.err_resp.error_info));
766}
767
5b9f8cd3 768static void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
a55360e4 769 struct iwl_rx_mem_buffer *rxb)
b481de9c 770{
0a6857e7 771#ifdef CONFIG_IWLWIFI_DEBUG
db11d634 772 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2aa6ab86 773 struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
e1623446 774 IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
b481de9c
ZY		 775 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
776#endif
777}
778
5b9f8cd3 779static void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
a55360e4 780 struct iwl_rx_mem_buffer *rxb)
b481de9c 781{
db11d634 782 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
e1623446 783 IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
b481de9c
ZY		 784 "notification for %s:\n",
785 le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
bf403db8 786 iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
b481de9c
ZY		 787}
788
5b9f8cd3 789static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 790{
c79dd5b5
TW		 791 struct iwl_priv *priv =
792 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 793 struct sk_buff *beacon;
794
795 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 796 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 797
798 if (!beacon) {
15b1687c 799 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY		 800 return;
801 }
802
803 mutex_lock(&priv->mutex);
804 /* new beacon skb is allocated every time; dispose previous.*/
805 if (priv->ibss_beacon)
806 dev_kfree_skb(priv->ibss_beacon);
807
808 priv->ibss_beacon = beacon;
809 mutex_unlock(&priv->mutex);
810
5b9f8cd3 811 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 812}
813
4e39317d 814/**
5b9f8cd3 815 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 816 *
817 * This callback is provided in order to send a statistics request.
818 *
819 * This timer function is continually reset to execute within
820 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
821 * was received. We need to ensure we receive the statistics in order
822 * to update the temperature used for calibrating the TXPOWER.
823 */
5b9f8cd3 824static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 825{
826 struct iwl_priv *priv = (struct iwl_priv *)data;
827
828 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
829 return;
830
61780ee3
MA		 831 /* dont send host command if rf-kill is on */
832 if (!iwl_is_ready_rf(priv))
833 return;
834
4e39317d
EG		 835 iwl_send_statistics_request(priv, CMD_ASYNC);
836}
837
5b9f8cd3 838static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 839 struct iwl_rx_mem_buffer *rxb)
b481de9c 840{
0a6857e7 841#ifdef CONFIG_IWLWIFI_DEBUG
db11d634 842 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2aa6ab86
TW		 843 struct iwl4965_beacon_notif *beacon =
844 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 845 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 846
e1623446 847 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 848 "tsf %d %d rate %d\n",
25a6572c 849 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 850 beacon->beacon_notify_hdr.failure_frame,
851 le32_to_cpu(beacon->ibss_mgr_status),
852 le32_to_cpu(beacon->high_tsf),
853 le32_to_cpu(beacon->low_tsf), rate);
854#endif
855
05c914fe 856 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 857 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
858 queue_work(priv->workqueue, &priv->beacon_update);
859}
860
b481de9c
ZY		 861/* Handle notification from uCode that card's power state is changing
862 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 863static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 864 struct iwl_rx_mem_buffer *rxb)
b481de9c 865{
db11d634 866 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 867 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
868 unsigned long status = priv->status;
869
e1623446 870 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY		 871 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
872 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
873
874 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
875 RF_CARD_DISABLED)) {
876
3395f6e9 877 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 878 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
879
3395f6e9
TW		 880 if (!iwl_grab_nic_access(priv)) {
881 iwl_write_direct32(
b481de9c
ZY		 882 priv, HBUS_TARG_MBX_C,
883 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
884
3395f6e9 885 iwl_release_nic_access(priv);
b481de9c
ZY		 886 }
887
888 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 889 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 890 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3395f6e9
TW		 891 if (!iwl_grab_nic_access(priv)) {
892 iwl_write_direct32(
b481de9c
ZY		 893 priv, HBUS_TARG_MBX_C,
894 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
895
3395f6e9 896 iwl_release_nic_access(priv);
b481de9c
ZY		 897 }
898 }
899
900 if (flags & RF_CARD_DISABLED) {
3395f6e9 901 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c 902 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
3395f6e9
TW		 903 iwl_read32(priv, CSR_UCODE_DRV_GP1);
904 if (!iwl_grab_nic_access(priv))
905 iwl_release_nic_access(priv);
b481de9c
ZY		 906 }
907 }
908
909 if (flags & HW_CARD_DISABLED)
910 set_bit(STATUS_RF_KILL_HW, &priv->status);
911 else
912 clear_bit(STATUS_RF_KILL_HW, &priv->status);
913
914
915 if (flags & SW_CARD_DISABLED)
916 set_bit(STATUS_RF_KILL_SW, &priv->status);
917 else
918 clear_bit(STATUS_RF_KILL_SW, &priv->status);
919
920 if (!(flags & RXON_CARD_DISABLED))
2a421b91 921 iwl_scan_cancel(priv);
b481de9c
ZY		 922
923 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
924 test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
925 (test_bit(STATUS_RF_KILL_SW, &status) !=
926 test_bit(STATUS_RF_KILL_SW, &priv->status)))
927 queue_work(priv->workqueue, &priv->rf_kill);
928 else
929 wake_up_interruptible(&priv->wait_command_queue);
930}
931
5b9f8cd3 932int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b
TW		 933{
934 int ret;
935 unsigned long flags;
936
937 spin_lock_irqsave(&priv->lock, flags);
938 ret = iwl_grab_nic_access(priv);
939 if (ret)
940 goto err;
941
942 if (src == IWL_PWR_SRC_VAUX) {
943 u32 val;
e7b63581 944 ret = pci_read_config_dword(priv->pci_dev, PCI_CFG_POWER_SOURCE,
e2e3c57b
TW		 945 &val);
946
947 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
948 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
949 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
950 ~APMG_PS_CTRL_MSK_PWR_SRC);
951 } else {
952 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
953 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
954 ~APMG_PS_CTRL_MSK_PWR_SRC);
955 }
956
957 iwl_release_nic_access(priv);
958err:
959 spin_unlock_irqrestore(&priv->lock, flags);
960 return ret;
961}
962
b481de9c 963/**
5b9f8cd3 964 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 965 *
966 * Setup the RX handlers for each of the reply types sent from the uCode
967 * to the host.
968 *
969 * This function chains into the hardware specific files for them to setup
970 * any hardware specific handlers as well.
971 */
653fa4a0 972static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 973{
885ba202 974 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 975 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
976 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 977 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 978 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 979 iwl_rx_pm_debug_statistics_notif;
980 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 981
9fbab516
BC		 982 /*
983 * The same handler is used for both the REPLY to a discrete
984 * statistics request from the host as well as for the periodic
985 * statistics notifications (after received beacons) from the uCode.
b481de9c 986 */
8f91aecb
EG		 987 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
988 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 989
21c339bf 990 iwl_setup_spectrum_handlers(priv);
2a421b91
TW		 991 iwl_setup_rx_scan_handlers(priv);
992
37a44211 993 /* status change handler */
5b9f8cd3 994 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 995
c1354754
TW		 996 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
997 iwl_rx_missed_beacon_notif;
37a44211 998 /* Rx handlers */
1781a07f
EG		 999 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
1000 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG		 1001 /* block ack */
1002 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 1003 /* Set up hardware specific Rx handlers */
d4789efe 1004 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 1005}
1006
b481de9c 1007/**
a55360e4 1008 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 1009 *
1010 * Uses the priv->rx_handlers callback function array to invoke
1011 * the appropriate handlers, including command responses,
1012 * frame-received notifications, and other notifications.
1013 */
a55360e4 1014void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 1015{
a55360e4 1016 struct iwl_rx_mem_buffer *rxb;
db11d634 1017 struct iwl_rx_packet *pkt;
a55360e4 1018 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 1019 u32 r, i;
1020 int reclaim;
1021 unsigned long flags;
5c0eef96 1022 u8 fill_rx = 0;
d68ab680 1023 u32 count = 8;
b481de9c 1024
6440adb5
CB		 1025 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1026 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 1027 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 1028 i = rxq->read;
1029
1030 /* Rx interrupt, but nothing sent from uCode */
1031 if (i == r)
e1623446 1032 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 1033
a55360e4 1034 if (iwl_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 1035 fill_rx = 1;
1036
b481de9c
ZY		 1037 while (i != r) {
1038 rxb = rxq->queue[i];
1039
9fbab516 1040 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 1041 * then a bug has been introduced in the queue refilling
1042 * routines -- catch it here */
1043 BUG_ON(rxb == NULL);
1044
1045 rxq->queue[i] = NULL;
1046
e91af0af
JB		 1047 dma_sync_single_range_for_cpu(
1048 &priv->pci_dev->dev, rxb->real_dma_addr,
1049 rxb->aligned_dma_addr - rxb->real_dma_addr,
1050 priv->hw_params.rx_buf_size,
1051 PCI_DMA_FROMDEVICE);
db11d634 1052 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY		 1053
1054 /* Reclaim a command buffer only if this packet is a response
1055 * to a (driver-originated) command.
1056 * If the packet (e.g. Rx frame) originated from uCode,
1057 * there is no command buffer to reclaim.
1058 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1059 * but apparently a few don't get set; catch them here. */
1060 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1061 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 1062 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 1063 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 1064 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 1065 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1066 (pkt->hdr.cmd != REPLY_TX);
1067
1068 /* Based on type of command response or notification,
1069 * handle those that need handling via function in
5b9f8cd3 1070 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 1071 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1072 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 1073 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
b481de9c
ZY		 1074 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
1075 } else {
1076 /* No handling needed */
e1623446 1077 IWL_DEBUG_RX(priv,
b481de9c
ZY		 1078 "r %d i %d No handler needed for %s, 0x%02x\n",
1079 r, i, get_cmd_string(pkt->hdr.cmd),
1080 pkt->hdr.cmd);
1081 }
1082
1083 if (reclaim) {
9fbab516 1084 /* Invoke any callbacks, transfer the skb to caller, and
857485c0 1085 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY		 1086 * as we reclaim the driver command queue */
1087 if (rxb && rxb->skb)
17b88929 1088 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1089 else
39aadf8c 1090 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1091 }
1092
1093 /* For now we just don't re-use anything. We can tweak this
1094 * later to try and re-use notification packets and SKBs that
1095 * fail to Rx correctly */
1096 if (rxb->skb != NULL) {
1097 priv->alloc_rxb_skb--;
1098 dev_kfree_skb_any(rxb->skb);
1099 rxb->skb = NULL;
1100 }
1101
4018517a
JB		 1102 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
1103 priv->hw_params.rx_buf_size + 256,
9ee1ba47 1104 PCI_DMA_FROMDEVICE);
b481de9c
ZY		 1105 spin_lock_irqsave(&rxq->lock, flags);
1106 list_add_tail(&rxb->list, &priv->rxq.rx_used);
1107 spin_unlock_irqrestore(&rxq->lock, flags);
1108 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1109 /* If there are a lot of unused frames,
1110 * restock the Rx queue so ucode wont assert. */
1111 if (fill_rx) {
1112 count++;
1113 if (count >= 8) {
1114 priv->rxq.read = i;
f1bc4ac6 1115 iwl_rx_queue_restock(priv);
5c0eef96
MA		 1116 count = 0;
1117 }
1118 }
b481de9c
ZY		 1119 }
1120
1121 /* Backtrack one entry */
1122 priv->rxq.read = i;
a55360e4
TW		 1123 iwl_rx_queue_restock(priv);
1124}
a55360e4 1125
0359facc
MA		 1126/* call this function to flush any scheduled tasklet */
1127static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1128{
a96a27f9 1129 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1130 synchronize_irq(priv->pci_dev->irq);
1131 tasklet_kill(&priv->irq_tasklet);
1132}
1133
5b9f8cd3 1134static void iwl_error_recovery(struct iwl_priv *priv)
b481de9c
ZY		 1135{
1136 unsigned long flags;
1137
1138 memcpy(&priv->staging_rxon, &priv->recovery_rxon,
1139 sizeof(priv->staging_rxon));
1140 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5b9f8cd3 1141 iwl_commit_rxon(priv);
b481de9c 1142
4f40e4d9 1143 iwl_rxon_add_station(priv, priv->bssid, 1);
b481de9c
ZY		 1144
1145 spin_lock_irqsave(&priv->lock, flags);
1146 priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
1147 priv->error_recovering = 0;
1148 spin_unlock_irqrestore(&priv->lock, flags);
1149}
1150
5b9f8cd3 1151static void iwl_irq_tasklet(struct iwl_priv *priv)
b481de9c
ZY		 1152{
1153 u32 inta, handled = 0;
1154 u32 inta_fh;
1155 unsigned long flags;
0a6857e7 1156#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1157 u32 inta_mask;
1158#endif
1159
1160 spin_lock_irqsave(&priv->lock, flags);
1161
1162 /* Ack/clear/reset pending uCode interrupts.
1163 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1164 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1165 inta = iwl_read32(priv, CSR_INT);
1166 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1167
1168 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1169 * Any new interrupts that happen after this, either while we're
1170 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1171 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1172 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1173
0a6857e7 1174#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1175 if (priv->debug_level & IWL_DL_ISR) {
9fbab516 1176 /* just for debug */
3395f6e9 1177 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1178 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1179 inta, inta_mask, inta_fh);
1180 }
1181#endif
1182
1183 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1184 * atomic, make sure that inta covers all the interrupts that
1185 * we've discovered, even if FH interrupt came in just after
1186 * reading CSR_INT. */
6f83eaa1 1187 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1188 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1189 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1190 inta |= CSR_INT_BIT_FH_TX;
1191
1192 /* Now service all interrupt bits discovered above. */
1193 if (inta & CSR_INT_BIT_HW_ERR) {
15b1687c 1194 IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
b481de9c
ZY		 1195
1196 /* Tell the device to stop sending interrupts */
5b9f8cd3 1197 iwl_disable_interrupts(priv);
b481de9c 1198
5b9f8cd3 1199 iwl_irq_handle_error(priv);
b481de9c
ZY		 1200
1201 handled |= CSR_INT_BIT_HW_ERR;
1202
1203 spin_unlock_irqrestore(&priv->lock, flags);
1204
1205 return;
1206 }
1207
0a6857e7 1208#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1209 if (priv->debug_level & (IWL_DL_ISR)) {
b481de9c 1210 /* NIC fires this, but we don't use it, redundant with WAKEUP */
25c03d8e 1211 if (inta & CSR_INT_BIT_SCD)
e1623446 1212 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1213 "the frame/frames.\n");
b481de9c
ZY		 1214
1215 /* Alive notification via Rx interrupt will do the real work */
1216 if (inta & CSR_INT_BIT_ALIVE)
e1623446 1217 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
b481de9c
ZY		 1218 }
1219#endif
1220 /* Safely ignore these bits for debug checks below */
25c03d8e 1221 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1222
9fbab516 1223 /* HW RF KILL switch toggled */
b481de9c
ZY		 1224 if (inta & CSR_INT_BIT_RF_KILL) {
1225 int hw_rf_kill = 0;
3395f6e9 1226 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1227 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1228 hw_rf_kill = 1;
1229
e1623446 1230 IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1231 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1232
a9efa652 1233 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1234 * the driver allows loading the ucode even if the radio
1235 * is killed. Hence update the killswitch state here. The
1236 * rfkill handler will care about restarting if needed.
a9efa652 1237 */
6cd0b1cb
HS		 1238 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1239 if (hw_rf_kill)
1240 set_bit(STATUS_RF_KILL_HW, &priv->status);
1241 else
1242 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1243 queue_work(priv->workqueue, &priv->rf_kill);
edb34228 1244 }
b481de9c
ZY		 1245
1246 handled |= CSR_INT_BIT_RF_KILL;
1247 }
1248
9fbab516 1249 /* Chip got too hot and stopped itself */
b481de9c 1250 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1251 IWL_ERR(priv, "Microcode CT kill error detected.\n");
b481de9c
ZY		 1252 handled |= CSR_INT_BIT_CT_KILL;
1253 }
1254
1255 /* Error detected by uCode */
1256 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1257 IWL_ERR(priv, "Microcode SW error detected. "
1258 " Restarting 0x%X.\n", inta);
5b9f8cd3 1259 iwl_irq_handle_error(priv);
b481de9c
ZY		 1260 handled |= CSR_INT_BIT_SW_ERR;
1261 }
1262
1263 /* uCode wakes up after power-down sleep */
1264 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1265 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1266 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
babcebfa
TW		 1267 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1268 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1269 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1270 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1271 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1272 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c
ZY		 1273
1274 handled |= CSR_INT_BIT_WAKEUP;
1275 }
1276
1277 /* All uCode command responses, including Tx command responses,
1278 * Rx "responses" (frame-received notification), and other
1279 * notifications from uCode come through here*/
1280 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1281 iwl_rx_handle(priv);
b481de9c
ZY		 1282 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1283 }
1284
1285 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1286 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
b481de9c 1287 handled |= CSR_INT_BIT_FH_TX;
dbb983b7
RR		 1288 /* FH finished to write, send event */
1289 priv->ucode_write_complete = 1;
1290 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1291 }
1292
1293 if (inta & ~handled)
15b1687c 1294 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
b481de9c
ZY		 1295
1296 if (inta & ~CSR_INI_SET_MASK) {
39aadf8c 1297 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
b481de9c 1298 inta & ~CSR_INI_SET_MASK);
39aadf8c 1299 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1300 }
1301
1302 /* Re-enable all interrupts */
0359facc
MA		 1303 /* only Re-enable if diabled by irq */
1304 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1305 iwl_enable_interrupts(priv);
b481de9c 1306
0a6857e7 1307#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 1308 if (priv->debug_level & (IWL_DL_ISR)) {
3395f6e9
TW		 1309 inta = iwl_read32(priv, CSR_INT);
1310 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1311 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1312 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1313 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1314 }
1315#endif
1316 spin_unlock_irqrestore(&priv->lock, flags);
1317}
1318
5b9f8cd3 1319static irqreturn_t iwl_isr(int irq, void *data)
b481de9c 1320{
c79dd5b5 1321 struct iwl_priv *priv = data;
b481de9c
ZY		 1322 u32 inta, inta_mask;
1323 u32 inta_fh;
1324 if (!priv)
1325 return IRQ_NONE;
1326
1327 spin_lock(&priv->lock);
1328
1329 /* Disable (but don't clear!) interrupts here to avoid
1330 * back-to-back ISRs and sporadic interrupts from our NIC.
1331 * If we have something to service, the tasklet will re-enable ints.
1332 * If we *don't* have something, we'll re-enable before leaving here. */
3395f6e9
TW		 1333 inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
1334 iwl_write32(priv, CSR_INT_MASK, 0x00000000);
b481de9c
ZY		 1335
1336 /* Discover which interrupts are active/pending */
3395f6e9
TW		 1337 inta = iwl_read32(priv, CSR_INT);
1338 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
b481de9c
ZY		 1339
1340 /* Ignore interrupt if there's nothing in NIC to service.
1341 * This may be due to IRQ shared with another device,
1342 * or due to sporadic interrupts thrown from our NIC. */
1343 if (!inta && !inta_fh) {
e1623446 1344 IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
b481de9c
ZY		 1345 goto none;
1346 }
1347
1348 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
66fbb541
ON		 1349 /* Hardware disappeared. It might have already raised
1350 * an interrupt */
39aadf8c 1351 IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
66fbb541 1352 goto unplugged;
b481de9c
ZY		 1353 }
1354
e1623446 1355 IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1356 inta, inta_mask, inta_fh);
1357
25c03d8e
JP		 1358 inta &= ~CSR_INT_BIT_SCD;
1359
5b9f8cd3 1360 /* iwl_irq_tasklet() will service interrupts and re-enable them */
25c03d8e
JP		 1361 if (likely(inta || inta_fh))
1362 tasklet_schedule(&priv->irq_tasklet);
b481de9c 1363
66fbb541
ON		 1364 unplugged:
1365 spin_unlock(&priv->lock);
b481de9c
ZY		 1366 return IRQ_HANDLED;
1367
1368 none:
1369 /* re-enable interrupts here since we don't have anything to service. */
0359facc
MA		 1370 /* only Re-enable if diabled by irq */
1371 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1372 iwl_enable_interrupts(priv);
b481de9c
ZY		 1373 spin_unlock(&priv->lock);
1374 return IRQ_NONE;
1375}
1376
b481de9c
ZY		 1377/******************************************************************************
1378 *
1379 * uCode download functions
1380 *
1381 ******************************************************************************/
1382
5b9f8cd3 1383static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1384{
98c92211
TW		 1385 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1386 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1387 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1388 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1389 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1390 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1391}
1392
5b9f8cd3 1393static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1394{
1395 /* Remove all resets to allow NIC to operate */
1396 iwl_write32(priv, CSR_RESET, 0);
1397}
1398
1399
b481de9c 1400/**
5b9f8cd3 1401 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY		 1402 *
1403 * Copy into buffers for card to fetch via bus-mastering
1404 */
5b9f8cd3 1405static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1406{
14b3d338 1407 struct iwl_ucode *ucode;
a0987a8d 1408 int ret = -EINVAL, index;
b481de9c 1409 const struct firmware *ucode_raw;
a0987a8d
RC		 1410 const char *name_pre = priv->cfg->fw_name_pre;
1411 const unsigned int api_max = priv->cfg->ucode_api_max;
1412 const unsigned int api_min = priv->cfg->ucode_api_min;
1413 char buf[25];
b481de9c
ZY		 1414 u8 *src;
1415 size_t len;
a0987a8d 1416 u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY		 1417
1418 /* Ask kernel firmware_class module to get the boot firmware off disk.
1419 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC		 1420 for (index = api_max; index >= api_min; index--) {
1421 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1422 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1423 if (ret < 0) {
15b1687c 1424 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC		 1425 buf, ret);
1426 if (ret == -ENOENT)
1427 continue;
1428 else
1429 goto error;
1430 } else {
1431 if (index < api_max)
15b1687c
WT		 1432 IWL_ERR(priv, "Loaded firmware %s, "
1433 "which is deprecated. "
1434 "Please use API v%u instead.\n",
a0987a8d 1435 buf, api_max);
15b1687c 1436
e1623446 1437 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC		 1438 buf, ucode_raw->size);
1439 break;
1440 }
b481de9c
ZY		 1441 }
1442
a0987a8d
RC		 1443 if (ret < 0)
1444 goto error;
b481de9c
ZY		 1445
1446 /* Make sure that we got at least our header! */
1447 if (ucode_raw->size < sizeof(*ucode)) {
15b1687c 1448 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1449 ret = -EINVAL;
b481de9c
ZY		 1450 goto err_release;
1451 }
1452
1453 /* Data from ucode file: header followed by uCode images */
1454 ucode = (void *)ucode_raw->data;
1455
c02b3acd 1456 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1457 api_ver = IWL_UCODE_API(priv->ucode_ver);
b481de9c
ZY		 1458 inst_size = le32_to_cpu(ucode->inst_size);
1459 data_size = le32_to_cpu(ucode->data_size);
1460 init_size = le32_to_cpu(ucode->init_size);
1461 init_data_size = le32_to_cpu(ucode->init_data_size);
1462 boot_size = le32_to_cpu(ucode->boot_size);
1463
a0987a8d
RC		 1464 /* api_ver should match the api version forming part of the
1465 * firmware filename ... but we don't check for that and only rely
1466 * on the API version read from firware header from here on forward */
1467
1468 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1469 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 1470 "Driver supports v%u, firmware is v%u.\n",
1471 api_max, api_ver);
1472 priv->ucode_ver = 0;
1473 ret = -EINVAL;
1474 goto err_release;
1475 }
1476 if (api_ver != api_max)
978785a3 1477 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 1478 "got v%u. New firmware can be obtained "
1479 "from http://www.intellinuxwireless.org.\n",
1480 api_max, api_ver);
1481
978785a3
TW		 1482 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1483 IWL_UCODE_MAJOR(priv->ucode_ver),
1484 IWL_UCODE_MINOR(priv->ucode_ver),
1485 IWL_UCODE_API(priv->ucode_ver),
1486 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1487
e1623446 1488 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1489 priv->ucode_ver);
e1623446 1490 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1491 inst_size);
e1623446 1492 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1493 data_size);
e1623446 1494 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1495 init_size);
e1623446 1496 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1497 init_data_size);
e1623446 1498 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY		 1499 boot_size);
1500
1501 /* Verify size of file vs. image size info in file's header */
1502 if (ucode_raw->size < sizeof(*ucode) +
1503 inst_size + data_size + init_size +
1504 init_data_size + boot_size) {
1505
e1623446 1506 IWL_DEBUG_INFO(priv, "uCode file size %d too small\n",
b481de9c 1507 (int)ucode_raw->size);
90e759d1 1508 ret = -EINVAL;
b481de9c
ZY		 1509 goto err_release;
1510 }
1511
1512 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1513 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1514 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW		 1515 inst_size);
1516 ret = -EINVAL;
b481de9c
ZY		 1517 goto err_release;
1518 }
1519
099b40b7 1520 if (data_size > priv->hw_params.max_data_size) {
e1623446 1521 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW		 1522 data_size);
1523 ret = -EINVAL;
b481de9c
ZY		 1524 goto err_release;
1525 }
099b40b7 1526 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW		 1527 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1528 init_size);
90e759d1 1529 ret = -EINVAL;
b481de9c
ZY		 1530 goto err_release;
1531 }
099b40b7 1532 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1533 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW		 1534 init_data_size);
1535 ret = -EINVAL;
b481de9c
ZY		 1536 goto err_release;
1537 }
099b40b7 1538 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW		 1539 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1540 boot_size);
90e759d1 1541 ret = -EINVAL;
b481de9c
ZY		 1542 goto err_release;
1543 }
1544
1545 /* Allocate ucode buffers for card's bus-master loading ... */
1546
1547 /* Runtime instructions and 2 copies of data:
1548 * 1) unmodified from disk
1549 * 2) backup cache for save/restore during power-downs */
1550 priv->ucode_code.len = inst_size;
98c92211 1551 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY		 1552
1553 priv->ucode_data.len = data_size;
98c92211 1554 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY		 1555
1556 priv->ucode_data_backup.len = data_size;
98c92211 1557 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1558
1f304e4e
ZY		 1559 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1560 !priv->ucode_data_backup.v_addr)
1561 goto err_pci_alloc;
1562
b481de9c 1563 /* Initialization instructions and data */
90e759d1
TW		 1564 if (init_size && init_data_size) {
1565 priv->ucode_init.len = init_size;
98c92211 1566 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW		 1567
1568 priv->ucode_init_data.len = init_data_size;
98c92211 1569 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 1570
1571 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1572 goto err_pci_alloc;
1573 }
b481de9c
ZY		 1574
1575 /* Bootstrap (instructions only, no data) */
90e759d1
TW		 1576 if (boot_size) {
1577 priv->ucode_boot.len = boot_size;
98c92211 1578 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1579
90e759d1
TW		 1580 if (!priv->ucode_boot.v_addr)
1581 goto err_pci_alloc;
1582 }
b481de9c
ZY		 1583
1584 /* Copy images into buffers for card's bus-master reads ... */
1585
1586 /* Runtime instructions (first block of data in file) */
1587 src = &ucode->data[0];
1588 len = priv->ucode_code.len;
e1623446 1589 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1590 memcpy(priv->ucode_code.v_addr, src, len);
e1623446 1591 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 1592 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1593
1594 /* Runtime data (2nd block)
5b9f8cd3 1595 * NOTE: Copy into backup buffer will be done in iwl_up() */
b481de9c
ZY		 1596 src = &ucode->data[inst_size];
1597 len = priv->ucode_data.len;
e1623446 1598 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY		 1599 memcpy(priv->ucode_data.v_addr, src, len);
1600 memcpy(priv->ucode_data_backup.v_addr, src, len);
1601
1602 /* Initialization instructions (3rd block) */
1603 if (init_size) {
1604 src = &ucode->data[inst_size + data_size];
1605 len = priv->ucode_init.len;
e1623446 1606 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1607 len);
b481de9c
ZY		 1608 memcpy(priv->ucode_init.v_addr, src, len);
1609 }
1610
1611 /* Initialization data (4th block) */
1612 if (init_data_size) {
1613 src = &ucode->data[inst_size + data_size + init_size];
1614 len = priv->ucode_init_data.len;
e1623446 1615 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1616 len);
b481de9c
ZY		 1617 memcpy(priv->ucode_init_data.v_addr, src, len);
1618 }
1619
1620 /* Bootstrap instructions (5th block) */
1621 src = &ucode->data[inst_size + data_size + init_size + init_data_size];
1622 len = priv->ucode_boot.len;
e1623446 1623 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY		 1624 memcpy(priv->ucode_boot.v_addr, src, len);
1625
1626 /* We have our copies now, allow OS release its copies */
1627 release_firmware(ucode_raw);
1628 return 0;
1629
1630 err_pci_alloc:
15b1687c 1631 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1632 ret = -ENOMEM;
5b9f8cd3 1633 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 1634
1635 err_release:
1636 release_firmware(ucode_raw);
1637
1638 error:
90e759d1 1639 return ret;
b481de9c
ZY		 1640}
1641
ada17513
MA		 1642/* temporary */
1643static int iwl_mac_beacon_update(struct ieee80211_hw *hw,
1644 struct sk_buff *skb);
1645
b481de9c 1646/**
4a4a9e81 1647 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1648 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1649 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1650 */
4a4a9e81 1651static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1652{
57aab75a 1653 int ret = 0;
b481de9c 1654
e1623446 1655 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 1656
1657 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1658 /* We had an error bringing up the hardware, so take it
1659 * all the way back down so we can try again */
e1623446 1660 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 1661 goto restart;
1662 }
1663
1664 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1665 * This is a paranoid check, because we would not have gotten the
1666 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1667 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 1668 /* Runtime instruction load was bad;
1669 * take it all the way back down so we can try again */
e1623446 1670 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 1671 goto restart;
1672 }
1673
37deb2a0 1674 iwl_clear_stations_table(priv);
57aab75a
TW		 1675 ret = priv->cfg->ops->lib->alive_notify(priv);
1676 if (ret) {
39aadf8c
WT		 1677 IWL_WARN(priv,
1678 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 1679 goto restart;
1680 }
1681
5b9f8cd3 1682 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 1683 set_bit(STATUS_ALIVE, &priv->status);
1684
fee1247a 1685 if (iwl_is_rfkill(priv))
b481de9c
ZY		 1686 return;
1687
36d6825b 1688 ieee80211_wake_queues(priv->hw);
b481de9c
ZY		 1689
1690 priv->active_rate = priv->rates_mask;
1691 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1692
3109ece1 1693 if (iwl_is_associated(priv)) {
c1adf9fb
GG		 1694 struct iwl_rxon_cmd *active_rxon =
1695 (struct iwl_rxon_cmd *)&priv->active_rxon;
b481de9c
ZY		 1696
1697 memcpy(&priv->staging_rxon, &priv->active_rxon,
1698 sizeof(priv->staging_rxon));
1699 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1700 } else {
1701 /* Initialize our rx_config data */
5b9f8cd3 1702 iwl_connection_init_rx_config(priv, priv->iw_mode);
8ccde88a 1703 iwl_set_rxon_chain(priv);
b481de9c
ZY		 1704 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1705 }
1706
9fbab516 1707 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1708 iwl_send_bt_config(priv);
b481de9c 1709
4a4a9e81
TW		 1710 iwl_reset_run_time_calib(priv);
1711
b481de9c 1712 /* Configure the adapter for unassociated operation */
5b9f8cd3 1713 iwl_commit_rxon(priv);
b481de9c
ZY		 1714
1715 /* At this point, the NIC is initialized and operational */
47f4a587 1716 iwl_rf_kill_ct_config(priv);
5a66926a 1717
fe00b5a5
RC		 1718 iwl_leds_register(priv);
1719
e1623446 1720 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1721 set_bit(STATUS_READY, &priv->status);
5a66926a 1722 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1723
1724 if (priv->error_recovering)
5b9f8cd3 1725 iwl_error_recovery(priv);
b481de9c 1726
58d0f361 1727 iwl_power_update_mode(priv, 1);
c46fbefa 1728
ada17513
MA		 1729 /* reassociate for ADHOC mode */
1730 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1731 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1732 priv->vif);
1733 if (beacon)
1734 iwl_mac_beacon_update(priv->hw, beacon);
1735 }
1736
1737
c46fbefa 1738 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1739 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1740
b481de9c
ZY		 1741 return;
1742
1743 restart:
1744 queue_work(priv->workqueue, &priv->restart);
1745}
1746
4e39317d 1747static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1748
5b9f8cd3 1749static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 1750{
1751 unsigned long flags;
1752 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1753
e1623446 1754 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1755
b481de9c
ZY		 1756 if (!exit_pending)
1757 set_bit(STATUS_EXIT_PENDING, &priv->status);
1758
ab53d8af
MA		 1759 iwl_leds_unregister(priv);
1760
37deb2a0 1761 iwl_clear_stations_table(priv);
b481de9c
ZY		 1762
1763 /* Unblock any waiting calls */
1764 wake_up_interruptible_all(&priv->wait_command_queue);
1765
b481de9c
ZY		 1766 /* Wipe out the EXIT_PENDING status bit if we are not actually
1767 * exiting the module */
1768 if (!exit_pending)
1769 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1770
1771 /* stop and reset the on-board processor */
3395f6e9 1772 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 1773
1774 /* tell the device to stop sending interrupts */
0359facc 1775 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1776 iwl_disable_interrupts(priv);
0359facc
MA		 1777 spin_unlock_irqrestore(&priv->lock, flags);
1778 iwl_synchronize_irq(priv);
b481de9c
ZY		 1779
1780 if (priv->mac80211_registered)
1781 ieee80211_stop_queues(priv->hw);
1782
5b9f8cd3 1783 /* If we have not previously called iwl_init() then
b481de9c 1784 * clear all bits but the RF Kill and SUSPEND bits and return */
fee1247a 1785 if (!iwl_is_init(priv)) {
b481de9c
ZY		 1786 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1787 STATUS_RF_KILL_HW |
1788 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1789 STATUS_RF_KILL_SW |
9788864e
RC		 1790 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1791 STATUS_GEO_CONFIGURED |
b481de9c 1792 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
052ec3f1
MA		 1793 STATUS_IN_SUSPEND |
1794 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1795 STATUS_EXIT_PENDING;
b481de9c
ZY		 1796 goto exit;
1797 }
1798
1799 /* ...otherwise clear out all the status bits but the RF Kill and
1800 * SUSPEND bits and continue taking the NIC down. */
1801 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1802 STATUS_RF_KILL_HW |
1803 test_bit(STATUS_RF_KILL_SW, &priv->status) <<
1804 STATUS_RF_KILL_SW |
9788864e
RC		 1805 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1806 STATUS_GEO_CONFIGURED |
b481de9c
ZY		 1807 test_bit(STATUS_IN_SUSPEND, &priv->status) <<
1808 STATUS_IN_SUSPEND |
1809 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 1810 STATUS_FW_ERROR |
1811 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1812 STATUS_EXIT_PENDING;
b481de9c
ZY		 1813
1814 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1815 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1816 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY		 1817 spin_unlock_irqrestore(&priv->lock, flags);
1818
da1bc453 1819 iwl_txq_ctx_stop(priv);
b3bbacb7 1820 iwl_rxq_stop(priv);
b481de9c
ZY		 1821
1822 spin_lock_irqsave(&priv->lock, flags);
3395f6e9
TW		 1823 if (!iwl_grab_nic_access(priv)) {
1824 iwl_write_prph(priv, APMG_CLK_DIS_REG,
b481de9c 1825 APMG_CLK_VAL_DMA_CLK_RQT);
3395f6e9 1826 iwl_release_nic_access(priv);
b481de9c
ZY		 1827 }
1828 spin_unlock_irqrestore(&priv->lock, flags);
1829
1830 udelay(5);
1831
7f066108 1832 /* FIXME: apm_ops.suspend(priv) */
d535311e
GG		 1833 if (exit_pending || test_bit(STATUS_IN_SUSPEND, &priv->status))
1834 priv->cfg->ops->lib->apm_ops.stop(priv);
1835 else
1836 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 1837 exit:
885ba202 1838 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 1839
1840 if (priv->ibss_beacon)
1841 dev_kfree_skb(priv->ibss_beacon);
1842 priv->ibss_beacon = NULL;
1843
1844 /* clear out any free frames */
fcab423d 1845 iwl_clear_free_frames(priv);
b481de9c
ZY		 1846}
1847
5b9f8cd3 1848static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 1849{
1850 mutex_lock(&priv->mutex);
5b9f8cd3 1851 __iwl_down(priv);
b481de9c 1852 mutex_unlock(&priv->mutex);
b24d22b1 1853
4e39317d 1854 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 1855}
1856
1857#define MAX_HW_RESTARTS 5
1858
5b9f8cd3 1859static int __iwl_up(struct iwl_priv *priv)
b481de9c 1860{
57aab75a
TW		 1861 int i;
1862 int ret;
b481de9c
ZY		 1863
1864 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 1865 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 1866 return -EIO;
1867 }
1868
e903fbd4 1869 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 1870 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 1871 return -EIO;
1872 }
1873
e655b9f0 1874 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 1875 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 1876 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1877 else
e655b9f0 1878 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1879
c1842d61 1880 if (iwl_is_rfkill(priv)) {
5b9f8cd3 1881 iwl_enable_interrupts(priv);
39aadf8c 1882 IWL_WARN(priv, "Radio disabled by %s RF Kill switch\n",
3bff19c2 1883 test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW");
c1842d61 1884 return 0;
b481de9c
ZY		 1885 }
1886
3395f6e9 1887 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 1888
1053d35f 1889 ret = iwl_hw_nic_init(priv);
57aab75a 1890 if (ret) {
15b1687c 1891 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 1892 return ret;
b481de9c
ZY		 1893 }
1894
1895 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 1896 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1897 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 1898 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1899
1900 /* clear (again), then enable host interrupts */
3395f6e9 1901 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 1902 iwl_enable_interrupts(priv);
b481de9c
ZY		 1903
1904 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 1905 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1906 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 1907
1908 /* Copy original ucode data image from disk into backup cache.
1909 * This will be used to initialize the on-board processor's
1910 * data SRAM for a clean start when the runtime program first loads. */
1911 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 1912 priv->ucode_data.len);
b481de9c 1913
b481de9c
ZY		 1914 for (i = 0; i < MAX_HW_RESTARTS; i++) {
1915
37deb2a0 1916 iwl_clear_stations_table(priv);
b481de9c
ZY		 1917
1918 /* load bootstrap state machine,
1919 * load bootstrap program into processor's memory,
1920 * prepare to load the "initialize" uCode */
57aab75a 1921 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 1922
57aab75a 1923 if (ret) {
15b1687c
WT		 1924 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
1925 ret);
b481de9c
ZY		 1926 continue;
1927 }
1928
f3d5b45b
EG		 1929 /* Clear out the uCode error bit if it is set */
1930 clear_bit(STATUS_FW_ERROR, &priv->status);
1931
b481de9c 1932 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 1933 iwl_nic_start(priv);
b481de9c 1934
e1623446 1935 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 1936
1937 return 0;
1938 }
1939
1940 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 1941 __iwl_down(priv);
64e72c3e 1942 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 1943
1944 /* tried to restart and config the device for as long as our
1945 * patience could withstand */
15b1687c 1946 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 1947 return -EIO;
1948}
1949
1950
1951/*****************************************************************************
1952 *
1953 * Workqueue callbacks
1954 *
1955 *****************************************************************************/
1956
4a4a9e81 1957static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 1958{
c79dd5b5
TW		 1959 struct iwl_priv *priv =
1960 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 1961
1962 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1963 return;
1964
1965 mutex_lock(&priv->mutex);
f3ccc08c 1966 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 1967 mutex_unlock(&priv->mutex);
1968}
1969
4a4a9e81 1970static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 1971{
c79dd5b5
TW		 1972 struct iwl_priv *priv =
1973 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 1974
1975 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1976 return;
1977
1978 mutex_lock(&priv->mutex);
4a4a9e81 1979 iwl_alive_start(priv);
b481de9c
ZY		 1980 mutex_unlock(&priv->mutex);
1981}
1982
16e727e8
EG		 1983static void iwl_bg_run_time_calib_work(struct work_struct *work)
1984{
1985 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1986 run_time_calib_work);
1987
1988 mutex_lock(&priv->mutex);
1989
1990 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1991 test_bit(STATUS_SCANNING, &priv->status)) {
1992 mutex_unlock(&priv->mutex);
1993 return;
1994 }
1995
1996 if (priv->start_calib) {
1997 iwl_chain_noise_calibration(priv, &priv->statistics);
1998
1999 iwl_sensitivity_calibration(priv, &priv->statistics);
2000 }
2001
2002 mutex_unlock(&priv->mutex);
2003 return;
2004}
2005
5b9f8cd3 2006static void iwl_bg_up(struct work_struct *data)
b481de9c 2007{
c79dd5b5 2008 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY		 2009
2010 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2011 return;
2012
2013 mutex_lock(&priv->mutex);
5b9f8cd3 2014 __iwl_up(priv);
b481de9c 2015 mutex_unlock(&priv->mutex);
80fcc9e2 2016 iwl_rfkill_set_hw_state(priv);
b481de9c
ZY		 2017}
2018
5b9f8cd3 2019static void iwl_bg_restart(struct work_struct *data)
b481de9c 2020{
c79dd5b5 2021 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 2022
2023 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2024 return;
2025
5b9f8cd3 2026 iwl_down(priv);
b481de9c
ZY		 2027 queue_work(priv->workqueue, &priv->up);
2028}
2029
5b9f8cd3 2030static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2031{
c79dd5b5
TW		 2032 struct iwl_priv *priv =
2033 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 2034
2035 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2036 return;
2037
2038 mutex_lock(&priv->mutex);
a55360e4 2039 iwl_rx_replenish(priv);
b481de9c
ZY		 2040 mutex_unlock(&priv->mutex);
2041}
2042
7878a5a4
MA		 2043#define IWL_DELAY_NEXT_SCAN (HZ*2)
2044
5b9f8cd3 2045static void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2046{
b481de9c 2047 struct ieee80211_conf *conf = NULL;
857485c0 2048 int ret = 0;
1ff50bda 2049 unsigned long flags;
b481de9c 2050
05c914fe 2051 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2052 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 2053 return;
2054 }
2055
e1623446 2056 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2057 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY		 2058
2059
2060 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2061 return;
2062
b481de9c 2063
508e32e1 2064 if (!priv->vif || !priv->is_open)
948c171c 2065 return;
508e32e1 2066
c90a74ba 2067 iwl_power_cancel_timeout(priv);
2a421b91 2068 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2069
b481de9c
ZY		 2070 conf = ieee80211_get_hw_conf(priv->hw);
2071
2072 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5b9f8cd3 2073 iwl_commit_rxon(priv);
b481de9c 2074
3195c1f3 2075 iwl_setup_rxon_timing(priv);
857485c0 2076 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2077 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2078 if (ret)
39aadf8c 2079 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 2080 "Attempting to continue.\n");
2081
2082 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2083
42eb7c64 2084 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2085
c7de35cd 2086 iwl_set_rxon_chain(priv);
b481de9c
ZY		 2087 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2088
e1623446 2089 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY		 2090 priv->assoc_id, priv->beacon_int);
2091
2092 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2093 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2094 else
2095 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2096
2097 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2098 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2099 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2100 else
2101 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2102
05c914fe 2103 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 2104 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2105
2106 }
2107
5b9f8cd3 2108 iwl_commit_rxon(priv);
b481de9c
ZY		 2109
2110 switch (priv->iw_mode) {
05c914fe 2111 case NL80211_IFTYPE_STATION:
b481de9c
ZY		 2112 break;
2113
05c914fe 2114 case NL80211_IFTYPE_ADHOC:
b481de9c 2115
c46fbefa
AK		 2116 /* assume default assoc id */
2117 priv->assoc_id = 1;
b481de9c 2118
4f40e4d9 2119 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2120 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 2121
2122 break;
2123
2124 default:
15b1687c 2125 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2126 __func__, priv->iw_mode);
b481de9c
ZY		 2127 break;
2128 }
2129
05c914fe 2130 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 2131 priv->assoc_station_added = 1;
2132
1ff50bda
EG		 2133 spin_lock_irqsave(&priv->lock, flags);
2134 iwl_activate_qos(priv, 0);
2135 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2136
04816448
GE		 2137 /* the chain noise calibration will enabled PM upon completion
2138 * If chain noise has already been run, then we need to enable
2139 * power management here */
2140 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
2141 iwl_power_enable_management(priv);
c90a74ba
EG		 2142
2143 /* Enable Rx differential gain and sensitivity calibrations */
2144 iwl_chain_noise_reset(priv);
2145 priv->start_calib = 1;
2146
508e32e1
RC		 2147}
2148
b481de9c
ZY		 2149/*****************************************************************************
2150 *
2151 * mac80211 entry point functions
2152 *
2153 *****************************************************************************/
2154
154b25ce 2155#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2156
5b9f8cd3 2157static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2158{
c79dd5b5 2159 struct iwl_priv *priv = hw->priv;
5a66926a 2160 int ret;
b481de9c 2161
e1623446 2162 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 2163
2164 /* we should be verifying the device is ready to be opened */
2165 mutex_lock(&priv->mutex);
2166
c1adf9fb 2167 memset(&priv->staging_rxon, 0, sizeof(struct iwl_rxon_cmd));
5a66926a
ZY		 2168 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2169 * ucode filename and max sizes are card-specific. */
b481de9c 2170
5a66926a 2171 if (!priv->ucode_code.len) {
5b9f8cd3 2172 ret = iwl_read_ucode(priv);
5a66926a 2173 if (ret) {
15b1687c 2174 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2175 mutex_unlock(&priv->mutex);
6cd0b1cb 2176 return ret;
5a66926a
ZY		 2177 }
2178 }
b481de9c 2179
5b9f8cd3 2180 ret = __iwl_up(priv);
5a66926a 2181
b481de9c 2182 mutex_unlock(&priv->mutex);
5a66926a 2183
80fcc9e2
AG		 2184 iwl_rfkill_set_hw_state(priv);
2185
e655b9f0 2186 if (ret)
6cd0b1cb 2187 return ret;
e655b9f0 2188
c1842d61
TW		 2189 if (iwl_is_rfkill(priv))
2190 goto out;
2191
e1623446 2192 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0
ZY		 2193
2194 if (test_bit(STATUS_IN_SUSPEND, &priv->status))
2195 return 0;
2196
fe9b6b72 2197 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2198 * mac80211 will not be run successfully. */
154b25ce
EG		 2199 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2200 test_bit(STATUS_READY, &priv->status),
2201 UCODE_READY_TIMEOUT);
2202 if (!ret) {
2203 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2204 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2205 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2206 return -ETIMEDOUT;
5a66926a 2207 }
fe9b6b72 2208 }
0a078ffa 2209
c1842d61 2210out:
0a078ffa 2211 priv->is_open = 1;
e1623446 2212 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2213 return 0;
2214}
2215
5b9f8cd3 2216static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2217{
c79dd5b5 2218 struct iwl_priv *priv = hw->priv;
b481de9c 2219
e1623446 2220 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2221
e655b9f0 2222 if (!priv->is_open) {
e1623446 2223 IWL_DEBUG_MAC80211(priv, "leave - skip\n");
e655b9f0
ZY		 2224 return;
2225 }
2226
b481de9c 2227 priv->is_open = 0;
5a66926a 2228
fee1247a 2229 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY		 2230 /* stop mac, cancel any scan request and clear
2231 * RXON_FILTER_ASSOC_MSK BIT
2232 */
5a66926a 2233 mutex_lock(&priv->mutex);
2a421b91 2234 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2235 mutex_unlock(&priv->mutex);
fde3571f
MA		 2236 }
2237
5b9f8cd3 2238 iwl_down(priv);
5a66926a
ZY		 2239
2240 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 2241
2242 /* enable interrupts again in order to receive rfkill changes */
2243 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2244 iwl_enable_interrupts(priv);
948c171c 2245
e1623446 2246 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2247}
2248
5b9f8cd3 2249static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2250{
c79dd5b5 2251 struct iwl_priv *priv = hw->priv;
b481de9c 2252
e1623446 2253 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2254
e1623446 2255 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2256 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2257
e039fa4a 2258 if (iwl_tx_skb(priv, skb))
b481de9c
ZY		 2259 dev_kfree_skb_any(skb);
2260
e1623446 2261 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2262 return NETDEV_TX_OK;
b481de9c
ZY		 2263}
2264
5b9f8cd3 2265static int iwl_mac_add_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 2266 struct ieee80211_if_init_conf *conf)
2267{
c79dd5b5 2268 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 2269 unsigned long flags;
2270
e1623446 2271 IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
b481de9c 2272
32bfd35d 2273 if (priv->vif) {
e1623446 2274 IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
75849d28 2275 return -EOPNOTSUPP;
b481de9c
ZY		 2276 }
2277
2278 spin_lock_irqsave(&priv->lock, flags);
32bfd35d 2279 priv->vif = conf->vif;
60294de3 2280 priv->iw_mode = conf->type;
b481de9c
ZY		 2281
2282 spin_unlock_irqrestore(&priv->lock, flags);
2283
2284 mutex_lock(&priv->mutex);
864792e3
TW		 2285
2286 if (conf->mac_addr) {
e1623446 2287 IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
864792e3
TW		 2288 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
2289 }
b481de9c 2290
5b9f8cd3 2291 if (iwl_set_mode(priv, conf->type) == -EAGAIN)
c46fbefa
AK		 2292 /* we are not ready, will run again when ready */
2293 set_bit(STATUS_MODE_PENDING, &priv->status);
5a66926a 2294
b481de9c
ZY		 2295 mutex_unlock(&priv->mutex);
2296
e1623446 2297 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2298 return 0;
2299}
2300
2301/**
5b9f8cd3 2302 * iwl_mac_config - mac80211 config callback
b481de9c
ZY		 2303 *
2304 * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
2305 * be set inappropriately and the driver currently sets the hardware up to
2306 * use it whenever needed.
2307 */
5b9f8cd3 2308static int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
b481de9c 2309{
c79dd5b5 2310 struct iwl_priv *priv = hw->priv;
bf85ea4f 2311 const struct iwl_channel_info *ch_info;
e8975581 2312 struct ieee80211_conf *conf = &hw->conf;
b481de9c 2313 unsigned long flags;
76bb77e0 2314 int ret = 0;
82a66bbb 2315 u16 channel;
b481de9c
ZY		 2316
2317 mutex_lock(&priv->mutex);
e1623446 2318 IWL_DEBUG_MAC80211(priv, "enter to channel %d\n", conf->channel->hw_value);
b481de9c 2319
de27e64e 2320 priv->current_ht_config.is_ht = conf_is_ht(conf);
ae5eb026 2321
14a08a7f 2322 if (conf->radio_enabled && iwl_radio_kill_sw_enable_radio(priv)) {
e1623446 2323 IWL_DEBUG_MAC80211(priv, "leave - RF-KILL - waiting for uCode\n");
14a08a7f 2324 goto out;
64e72c3e
MA		 2325 }
2326
14a08a7f
EG		 2327 if (!conf->radio_enabled)
2328 iwl_radio_kill_sw_disable_radio(priv);
2329
fee1247a 2330 if (!iwl_is_ready(priv)) {
e1623446 2331 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
76bb77e0
ZY		 2332 ret = -EIO;
2333 goto out;
b481de9c
ZY		 2334 }
2335
1ea87396 2336 if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
b481de9c 2337 test_bit(STATUS_SCANNING, &priv->status))) {
e1623446 2338 IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
b481de9c 2339 mutex_unlock(&priv->mutex);
a0646470 2340 return 0;
b481de9c
ZY		 2341 }
2342
82a66bbb
TW		 2343 channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
2344 ch_info = iwl_get_channel_info(priv, conf->channel->band, channel);
b481de9c 2345 if (!is_channel_valid(ch_info)) {
e1623446 2346 IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
76bb77e0
ZY		 2347 ret = -EINVAL;
2348 goto out;
b481de9c
ZY		 2349 }
2350
05c914fe 2351 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
398f9e76 2352 !is_channel_ibss(ch_info)) {
15b1687c 2353 IWL_ERR(priv, "channel %d in band %d not IBSS channel\n",
398f9e76
AK		 2354 conf->channel->hw_value, conf->channel->band);
2355 ret = -EINVAL;
2356 goto out;
2357 }
2358
82a66bbb
TW		 2359 spin_lock_irqsave(&priv->lock, flags);
2360
b5d7be5e 2361
78330fdd 2362 /* if we are switching from ht to 2.4 clear flags
b481de9c
ZY		 2363 * from any ht related info since 2.4 does not
2364 * support ht */
82a66bbb 2365 if ((le16_to_cpu(priv->staging_rxon.channel) != channel)
b481de9c
ZY		 2366#ifdef IEEE80211_CONF_CHANNEL_SWITCH
2367 && !(conf->flags & IEEE80211_CONF_CHANNEL_SWITCH)
2368#endif
2369 )
2370 priv->staging_rxon.flags = 0;
b481de9c 2371
17e72782 2372 iwl_set_rxon_channel(priv, conf->channel);
b481de9c 2373
82a66bbb 2374 iwl_set_flags_for_band(priv, conf->channel->band);
b481de9c
ZY		 2375
2376 /* The list of supported rates and rate mask can be different
8318d78a 2377 * for each band; since the band may have changed, reset
b481de9c 2378 * the rate mask to what mac80211 lists */
5b9f8cd3 2379 iwl_set_rate(priv);
b481de9c
ZY		 2380
2381 spin_unlock_irqrestore(&priv->lock, flags);
2382
2383#ifdef IEEE80211_CONF_CHANNEL_SWITCH
2384 if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
5b9f8cd3 2385 iwl_hw_channel_switch(priv, conf->channel);
76bb77e0 2386 goto out;
b481de9c
ZY		 2387 }
2388#endif
2389
b481de9c 2390 if (!conf->radio_enabled) {
e1623446 2391 IWL_DEBUG_MAC80211(priv, "leave - radio disabled\n");
76bb77e0 2392 goto out;
b481de9c
ZY		 2393 }
2394
fee1247a 2395 if (iwl_is_rfkill(priv)) {
e1623446 2396 IWL_DEBUG_MAC80211(priv, "leave - RF kill\n");
76bb77e0
ZY		 2397 ret = -EIO;
2398 goto out;
b481de9c
ZY		 2399 }
2400
e602cb18
EK		 2401 if (conf->flags & IEEE80211_CONF_PS)
2402 ret = iwl_power_set_user_mode(priv, IWL_POWER_INDEX_3);
2403 else
2404 ret = iwl_power_set_user_mode(priv, IWL_POWER_MODE_CAM);
2405 if (ret)
e1623446 2406 IWL_DEBUG_MAC80211(priv, "Error setting power level\n");
e602cb18 2407
e1623446 2408 IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
630fe9b6
TW		 2409 priv->tx_power_user_lmt, conf->power_level);
2410
2411 iwl_set_tx_power(priv, conf->power_level, false);
2412
5b9f8cd3 2413 iwl_set_rate(priv);
b481de9c 2414
7b841727
RF		 2415 /* call to ensure that 4965 rx_chain is set properly in monitor mode */
2416 iwl_set_rxon_chain(priv);
2417
b481de9c
ZY		 2418 if (memcmp(&priv->active_rxon,
2419 &priv->staging_rxon, sizeof(priv->staging_rxon)))
5b9f8cd3 2420 iwl_commit_rxon(priv);
b481de9c 2421 else
e1623446 2422 IWL_DEBUG_INFO(priv, "No re-sending same RXON configuration.\n");
b481de9c 2423
e1623446 2424 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2425
a0646470 2426out:
5a66926a 2427 mutex_unlock(&priv->mutex);
76bb77e0 2428 return ret;
b481de9c
ZY		 2429}
2430
5b9f8cd3 2431static void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2432{
857485c0 2433 int ret = 0;
1ff50bda 2434 unsigned long flags;
b481de9c 2435
d986bcd1 2436 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 2437 return;
2438
2439 /* The following should be done only at AP bring up */
3195c1f3 2440 if (!iwl_is_associated(priv)) {
b481de9c
ZY		 2441
2442 /* RXON - unassoc (to set timing command) */
2443 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5b9f8cd3 2444 iwl_commit_rxon(priv);
b481de9c
ZY		 2445
2446 /* RXON Timing */
3195c1f3 2447 iwl_setup_rxon_timing(priv);
857485c0 2448 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2449 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2450 if (ret)
39aadf8c 2451 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 2452 "Attempting to continue.\n");
2453
c7de35cd 2454 iwl_set_rxon_chain(priv);
b481de9c
ZY		 2455
2456 /* FIXME: what should be the assoc_id for AP? */
2457 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2458 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2459 priv->staging_rxon.flags |=
2460 RXON_FLG_SHORT_PREAMBLE_MSK;
2461 else
2462 priv->staging_rxon.flags &=
2463 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2464
2465 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2466 if (priv->assoc_capability &
2467 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2468 priv->staging_rxon.flags |=
2469 RXON_FLG_SHORT_SLOT_MSK;
2470 else
2471 priv->staging_rxon.flags &=
2472 ~RXON_FLG_SHORT_SLOT_MSK;
2473
05c914fe 2474 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY		 2475 priv->staging_rxon.flags &=
2476 ~RXON_FLG_SHORT_SLOT_MSK;
2477 }
2478 /* restore RXON assoc */
2479 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
5b9f8cd3 2480 iwl_commit_rxon(priv);
1ff50bda
EG		 2481 spin_lock_irqsave(&priv->lock, flags);
2482 iwl_activate_qos(priv, 1);
2483 spin_unlock_irqrestore(&priv->lock, flags);
4f40e4d9 2484 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
e1493deb 2485 }
5b9f8cd3 2486 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 2487
2488 /* FIXME - we need to add code here to detect a totally new
2489 * configuration, reset the AP, unassoc, rxon timing, assoc,
2490 * clear sta table, add BCAST sta... */
2491}
2492
9d139c81 2493
5b9f8cd3 2494static int iwl_mac_config_interface(struct ieee80211_hw *hw,
32bfd35d 2495 struct ieee80211_vif *vif,
b481de9c
ZY		 2496 struct ieee80211_if_conf *conf)
2497{
c79dd5b5 2498 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 2499 int rc;
2500
2501 if (conf == NULL)
2502 return -EIO;
2503
b716bb91 2504 if (priv->vif != vif) {
e1623446 2505 IWL_DEBUG_MAC80211(priv, "leave - priv->vif != vif\n");
b716bb91
EG		 2506 return 0;
2507 }
2508
05c914fe 2509 if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
9d139c81
JB		 2510 conf->changed & IEEE80211_IFCC_BEACON) {
2511 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2512 if (!beacon)
2513 return -ENOMEM;
ada17513 2514 mutex_lock(&priv->mutex);
5b9f8cd3 2515 rc = iwl_mac_beacon_update(hw, beacon);
ada17513 2516 mutex_unlock(&priv->mutex);
9d139c81
JB		 2517 if (rc)
2518 return rc;
2519 }
2520
fee1247a 2521 if (!iwl_is_alive(priv))
5a66926a
ZY		 2522 return -EAGAIN;
2523
b481de9c
ZY		 2524 mutex_lock(&priv->mutex);
2525
b481de9c 2526 if (conf->bssid)
e1623446 2527 IWL_DEBUG_MAC80211(priv, "bssid: %pM\n", conf->bssid);
b481de9c 2528
4150c572
JB		 2529/*
2530 * very dubious code was here; the probe filtering flag is never set:
2531 *
b481de9c
ZY		 2532 if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
2533 !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
4150c572 2534 */
b481de9c 2535
05c914fe 2536 if (priv->iw_mode == NL80211_IFTYPE_AP) {
b481de9c
ZY		 2537 if (!conf->bssid) {
2538 conf->bssid = priv->mac_addr;
2539 memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
e1623446 2540 IWL_DEBUG_MAC80211(priv, "bssid was set to: %pM\n",
e174961c 2541 conf->bssid);
b481de9c
ZY		 2542 }
2543 if (priv->ibss_beacon)
2544 dev_kfree_skb(priv->ibss_beacon);
2545
9d139c81 2546 priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
b481de9c
ZY		 2547 }
2548
fee1247a 2549 if (iwl_is_rfkill(priv))
fde3571f
MA		 2550 goto done;
2551
b481de9c
ZY		 2552 if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
2553 !is_multicast_ether_addr(conf->bssid)) {
2554 /* If there is currently a HW scan going on in the background
2555 * then we need to cancel it else the RXON below will fail. */
2a421b91 2556 if (iwl_scan_cancel_timeout(priv, 100)) {
39aadf8c 2557 IWL_WARN(priv, "Aborted scan still in progress "
b481de9c 2558 "after 100ms\n");
e1623446 2559 IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
b481de9c
ZY		 2560 mutex_unlock(&priv->mutex);
2561 return -EAGAIN;
2562 }
2563 memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
2564
2565 /* TODO: Audit driver for usage of these members and see
2566 * if mac80211 deprecates them (priv->bssid looks like it
2567 * shouldn't be there, but I haven't scanned the IBSS code
2568 * to verify) - jpk */
2569 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
2570
05c914fe 2571 if (priv->iw_mode == NL80211_IFTYPE_AP)
5b9f8cd3 2572 iwl_config_ap(priv);
b481de9c 2573 else {
5b9f8cd3 2574 rc = iwl_commit_rxon(priv);
05c914fe 2575 if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
4f40e4d9 2576 iwl_rxon_add_station(
b481de9c
ZY		 2577 priv, priv->active_rxon.bssid_addr, 1);
2578 }
2579
2580 } else {
2a421b91 2581 iwl_scan_cancel_timeout(priv, 100);
b481de9c 2582 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5b9f8cd3 2583 iwl_commit_rxon(priv);
b481de9c
ZY		 2584 }
2585
fde3571f 2586 done:
e1623446 2587 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2588 mutex_unlock(&priv->mutex);
2589
2590 return 0;
2591}
2592
5b9f8cd3 2593static void iwl_mac_remove_interface(struct ieee80211_hw *hw,
b481de9c
ZY		 2594 struct ieee80211_if_init_conf *conf)
2595{
c79dd5b5 2596 struct iwl_priv *priv = hw->priv;
b481de9c 2597
e1623446 2598 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 2599
2600 mutex_lock(&priv->mutex);
948c171c 2601
fee1247a 2602 if (iwl_is_ready_rf(priv)) {
2a421b91 2603 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2604 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5b9f8cd3 2605 iwl_commit_rxon(priv);
fde3571f 2606 }
32bfd35d
JB		 2607 if (priv->vif == conf->vif) {
2608 priv->vif = NULL;
b481de9c 2609 memset(priv->bssid, 0, ETH_ALEN);
b481de9c
ZY		 2610 }
2611 mutex_unlock(&priv->mutex);
2612
e1623446 2613 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2614
2615}
471b3efd 2616
3109ece1 2617#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
5b9f8cd3 2618static void iwl_bss_info_changed(struct ieee80211_hw *hw,
471b3efd
JB		 2619 struct ieee80211_vif *vif,
2620 struct ieee80211_bss_conf *bss_conf,
2621 u32 changes)
220173b0 2622{
c79dd5b5 2623 struct iwl_priv *priv = hw->priv;
220173b0 2624
e1623446 2625 IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
3109ece1 2626
471b3efd 2627 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
e1623446 2628 IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
3109ece1 2629 bss_conf->use_short_preamble);
471b3efd 2630 if (bss_conf->use_short_preamble)
220173b0
TW		 2631 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2632 else
2633 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2634 }
2635
471b3efd 2636 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
e1623446 2637 IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
8318d78a 2638 if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
220173b0
TW		 2639 priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
2640 else
2641 priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
2642 }
2643
98952d5d 2644 if (changes & BSS_CHANGED_HT) {
5b9f8cd3 2645 iwl_ht_conf(priv, bss_conf);
c7de35cd 2646 iwl_set_rxon_chain(priv);
98952d5d
TW		 2647 }
2648
471b3efd 2649 if (changes & BSS_CHANGED_ASSOC) {
e1623446 2650 IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
508e32e1
RC		 2651 /* This should never happen as this function should
2652 * never be called from interrupt context. */
2653 if (WARN_ON_ONCE(in_interrupt()))
2654 return;
3109ece1
TW		 2655 if (bss_conf->assoc) {
2656 priv->assoc_id = bss_conf->aid;
2657 priv->beacon_int = bss_conf->beacon_int;
b5d7be5e 2658 priv->power_data.dtim_period = bss_conf->dtim_period;
3109ece1
TW		 2659 priv->timestamp = bss_conf->timestamp;
2660 priv->assoc_capability = bss_conf->assoc_capability;
9ccacb86
TW		 2661
2662 /* we have just associated, don't start scan too early
2663 * leave time for EAPOL exchange to complete
2664 */
3109ece1
TW		 2665 priv->next_scan_jiffies = jiffies +
2666 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
508e32e1 2667 mutex_lock(&priv->mutex);
5b9f8cd3 2668 iwl_post_associate(priv);
508e32e1 2669 mutex_unlock(&priv->mutex);
3109ece1
TW		 2670 } else {
2671 priv->assoc_id = 0;
e1623446 2672 IWL_DEBUG_MAC80211(priv, "DISASSOC %d\n", bss_conf->assoc);
3109ece1
TW		 2673 }
2674 } else if (changes && iwl_is_associated(priv) && priv->assoc_id) {
e1623446 2675 IWL_DEBUG_MAC80211(priv, "Associated Changes %d\n", changes);
7e8c519e 2676 iwl_send_rxon_assoc(priv);
471b3efd
JB		 2677 }
2678
220173b0 2679}
b481de9c 2680
cb43dc25 2681static int iwl_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t ssid_len)
b481de9c 2682{
b481de9c 2683 unsigned long flags;
c79dd5b5 2684 struct iwl_priv *priv = hw->priv;
8d09a5e1 2685 int ret;
b481de9c 2686
e1623446 2687 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2688
052c4b9f 2689 mutex_lock(&priv->mutex);
b481de9c
ZY		 2690 spin_lock_irqsave(&priv->lock, flags);
2691
fee1247a 2692 if (!iwl_is_ready_rf(priv)) {
cb43dc25 2693 ret = -EIO;
e1623446 2694 IWL_DEBUG_MAC80211(priv, "leave - not ready or exit pending\n");
b481de9c
ZY		 2695 goto out_unlock;
2696 }
2697
8d09a5e1
TW		 2698 /* We don't schedule scan within next_scan_jiffies period.
2699 * Avoid scanning during possible EAPOL exchange, return
2700 * success immediately.
2701 */
7878a5a4 2702 if (priv->next_scan_jiffies &&
cb43dc25 2703 time_after(priv->next_scan_jiffies, jiffies)) {
e1623446 2704 IWL_DEBUG_SCAN(priv, "scan rejected: within next scan period\n");
8d09a5e1
TW		 2705 queue_work(priv->workqueue, &priv->scan_completed);
2706 ret = 0;
7878a5a4
MA		 2707 goto out_unlock;
2708 }
8d09a5e1 2709
b481de9c 2710 /* if we just finished scan ask for delay */
681c0050 2711 if (iwl_is_associated(priv) && priv->last_scan_jiffies &&
cb43dc25 2712 time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN, jiffies)) {
e1623446 2713 IWL_DEBUG_SCAN(priv, "scan rejected: within previous scan period\n");
8d09a5e1
TW		 2714 queue_work(priv->workqueue, &priv->scan_completed);
2715 ret = 0;
b481de9c
ZY		 2716 goto out_unlock;
2717 }
8d09a5e1 2718
cb43dc25 2719 if (ssid_len) {
b481de9c 2720 priv->one_direct_scan = 1;
cb43dc25 2721 priv->direct_ssid_len = min_t(u8, ssid_len, IW_ESSID_MAX_SIZE);
b481de9c 2722 memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
cb43dc25 2723 } else {
948c171c 2724 priv->one_direct_scan = 0;
cb43dc25 2725 }
b481de9c 2726
cb43dc25 2727 ret = iwl_scan_initiate(priv);
b481de9c 2728
e1623446 2729 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2730
2731out_unlock:
2732 spin_unlock_irqrestore(&priv->lock, flags);
052c4b9f 2733 mutex_unlock(&priv->mutex);
b481de9c 2734
cb43dc25 2735 return ret;
b481de9c
ZY		 2736}
2737
5b9f8cd3 2738static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG		 2739 struct ieee80211_key_conf *keyconf, const u8 *addr,
2740 u32 iv32, u16 *phase1key)
2741{
ab885f8c 2742
9f58671e 2743 struct iwl_priv *priv = hw->priv;
e1623446 2744 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2745
9f58671e 2746 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2747
e1623446 2748 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 2749}
2750
5b9f8cd3 2751static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2752 struct ieee80211_vif *vif,
2753 struct ieee80211_sta *sta,
b481de9c
ZY		 2754 struct ieee80211_key_conf *key)
2755{
c79dd5b5 2756 struct iwl_priv *priv = hw->priv;
42986796
WT		 2757 const u8 *addr;
2758 int ret;
2759 u8 sta_id;
2760 bool is_default_wep_key = false;
b481de9c 2761
e1623446 2762 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2763
099b40b7 2764 if (priv->hw_params.sw_crypto) {
e1623446 2765 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 2766 return -EOPNOTSUPP;
2767 }
42986796 2768 addr = sta ? sta->addr : iwl_bcast_addr;
947b13a7 2769 sta_id = iwl_find_station(priv, addr);
6974e363 2770 if (sta_id == IWL_INVALID_STATION) {
e1623446 2771 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2772 addr);
6974e363 2773 return -EINVAL;
b481de9c 2774
deb09c43 2775 }
b481de9c 2776
6974e363 2777 mutex_lock(&priv->mutex);
2a421b91 2778 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG		 2779 mutex_unlock(&priv->mutex);
2780
2781 /* If we are getting WEP group key and we didn't receive any key mapping
2782 * so far, we are in legacy wep mode (group key only), otherwise we are
2783 * in 1X mode.
2784 * In legacy wep mode, we use another host command to the uCode */
5425e490 2785 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2786 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG		 2787 if (cmd == SET_KEY)
2788 is_default_wep_key = !priv->key_mapping_key;
2789 else
ccc038ab
EG		 2790 is_default_wep_key =
2791 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2792 }
052c4b9f 2793
b481de9c 2794 switch (cmd) {
deb09c43 2795 case SET_KEY:
6974e363
EG		 2796 if (is_default_wep_key)
2797 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2798 else
7480513f 2799 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2800
e1623446 2801 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 2802 break;
2803 case DISABLE_KEY:
6974e363
EG		 2804 if (is_default_wep_key)
2805 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2806 else
3ec47732 2807 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2808
e1623446 2809 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 2810 break;
2811 default:
deb09c43 2812 ret = -EINVAL;
b481de9c
ZY		 2813 }
2814
e1623446 2815 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2816
deb09c43 2817 return ret;
b481de9c
ZY		 2818}
2819
5b9f8cd3 2820static int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
b481de9c
ZY		 2821 const struct ieee80211_tx_queue_params *params)
2822{
c79dd5b5 2823 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 2824 unsigned long flags;
2825 int q;
b481de9c 2826
e1623446 2827 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2828
fee1247a 2829 if (!iwl_is_ready_rf(priv)) {
e1623446 2830 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
b481de9c
ZY		 2831 return -EIO;
2832 }
2833
2834 if (queue >= AC_NUM) {
e1623446 2835 IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
b481de9c
ZY		 2836 return 0;
2837 }
2838
b481de9c
ZY		 2839 q = AC_NUM - 1 - queue;
2840
2841 spin_lock_irqsave(&priv->lock, flags);
2842
2843 priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
2844 priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
2845 priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
2846 priv->qos_data.def_qos_parm.ac[q].edca_txop =
3330d7be 2847 cpu_to_le16((params->txop * 32));
b481de9c
ZY		 2848
2849 priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
2850 priv->qos_data.qos_active = 1;
2851
05c914fe 2852 if (priv->iw_mode == NL80211_IFTYPE_AP)
1ff50bda 2853 iwl_activate_qos(priv, 1);
3109ece1 2854 else if (priv->assoc_id && iwl_is_associated(priv))
1ff50bda 2855 iwl_activate_qos(priv, 0);
b481de9c 2856
1ff50bda 2857 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c 2858
e1623446 2859 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2860 return 0;
2861}
2862
5b9f8cd3 2863static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2864 enum ieee80211_ampdu_mlme_action action,
17741cdc 2865 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 2866{
2867 struct iwl_priv *priv = hw->priv;
d783b061 2868
e1623446 2869 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2870 sta->addr, tid);
d783b061
TW		 2871
2872 if (!(priv->cfg->sku & IWL_SKU_N))
2873 return -EACCES;
2874
2875 switch (action) {
2876 case IEEE80211_AMPDU_RX_START:
e1623446 2877 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2878 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2879 case IEEE80211_AMPDU_RX_STOP:
e1623446 2880 IWL_DEBUG_HT(priv, "stop Rx\n");
9f58671e 2881 return iwl_sta_rx_agg_stop(priv, sta->addr, tid);
d783b061 2882 case IEEE80211_AMPDU_TX_START:
e1623446 2883 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2884 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2885 case IEEE80211_AMPDU_TX_STOP:
e1623446 2886 IWL_DEBUG_HT(priv, "stop Tx\n");
17741cdc 2887 return iwl_tx_agg_stop(priv, sta->addr, tid);
d783b061 2888 default:
e1623446 2889 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW		 2890 return -EINVAL;
2891 break;
2892 }
2893 return 0;
2894}
9f58671e 2895
5b9f8cd3 2896static int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 2897 struct ieee80211_tx_queue_stats *stats)
2898{
c79dd5b5 2899 struct iwl_priv *priv = hw->priv;
b481de9c 2900 int i, avail;
16466903 2901 struct iwl_tx_queue *txq;
443cfd45 2902 struct iwl_queue *q;
b481de9c
ZY		 2903 unsigned long flags;
2904
e1623446 2905 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2906
fee1247a 2907 if (!iwl_is_ready_rf(priv)) {
e1623446 2908 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
b481de9c
ZY		 2909 return -EIO;
2910 }
2911
2912 spin_lock_irqsave(&priv->lock, flags);
2913
2914 for (i = 0; i < AC_NUM; i++) {
2915 txq = &priv->txq[i];
2916 q = &txq->q;
443cfd45 2917 avail = iwl_queue_space(q);
b481de9c 2918
57ffc589
JB		 2919 stats[i].len = q->n_window - avail;
2920 stats[i].limit = q->n_window - q->high_mark;
2921 stats[i].count = q->n_window;
b481de9c
ZY		 2922
2923 }
2924 spin_unlock_irqrestore(&priv->lock, flags);
2925
e1623446 2926 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2927
2928 return 0;
2929}
2930
5b9f8cd3 2931static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY		 2932 struct ieee80211_low_level_stats *stats)
2933{
bf403db8
EK		 2934 struct iwl_priv *priv = hw->priv;
2935
2936 priv = hw->priv;
e1623446
TW		 2937 IWL_DEBUG_MAC80211(priv, "enter\n");
2938 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2939
2940 return 0;
2941}
2942
5b9f8cd3 2943static void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
b481de9c 2944{
c79dd5b5 2945 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 2946 unsigned long flags;
2947
2948 mutex_lock(&priv->mutex);
e1623446 2949 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2950
b481de9c 2951 spin_lock_irqsave(&priv->lock, flags);
fd105e79 2952 memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_info));
b481de9c 2953 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c 2954
c7de35cd 2955 iwl_reset_qos(priv);
b481de9c 2956
b481de9c
ZY		 2957 spin_lock_irqsave(&priv->lock, flags);
2958 priv->assoc_id = 0;
2959 priv->assoc_capability = 0;
b481de9c
ZY		 2960 priv->assoc_station_added = 0;
2961
2962 /* new association get rid of ibss beacon skb */
2963 if (priv->ibss_beacon)
2964 dev_kfree_skb(priv->ibss_beacon);
2965
2966 priv->ibss_beacon = NULL;
2967
2968 priv->beacon_int = priv->hw->conf.beacon_int;
3109ece1 2969 priv->timestamp = 0;
05c914fe 2970 if ((priv->iw_mode == NL80211_IFTYPE_STATION))
b481de9c
ZY		 2971 priv->beacon_int = 0;
2972
2973 spin_unlock_irqrestore(&priv->lock, flags);
2974
fee1247a 2975 if (!iwl_is_ready_rf(priv)) {
e1623446 2976 IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
fde3571f
MA		 2977 mutex_unlock(&priv->mutex);
2978 return;
2979 }
2980
052c4b9f 2981 /* we are restarting association process
2982 * clear RXON_FILTER_ASSOC_MSK bit
2983 */
05c914fe 2984 if (priv->iw_mode != NL80211_IFTYPE_AP) {
2a421b91 2985 iwl_scan_cancel_timeout(priv, 100);
052c4b9f 2986 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5b9f8cd3 2987 iwl_commit_rxon(priv);
052c4b9f 2988 }
2989
5da4b55f
MA		 2990 iwl_power_update_mode(priv, 0);
2991
b481de9c 2992 /* Per mac80211.h: This is only used in IBSS mode... */
05c914fe 2993 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
052c4b9f 2994
c90a74ba
EG		 2995 /* switch to CAM during association period.
2996 * the ucode will block any association/authentication
2997 * frome during assiciation period if it can not hear
2998 * the AP because of PM. the timer enable PM back is
2999 * association do not complete
3000 */
3001 if (priv->hw->conf.channel->flags & (IEEE80211_CHAN_PASSIVE_SCAN |
3002 IEEE80211_CHAN_RADAR))
3003 iwl_power_disable_management(priv, 3000);
3004
e1623446 3005 IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
b481de9c
ZY		 3006 mutex_unlock(&priv->mutex);
3007 return;
3008 }
3009
5b9f8cd3 3010 iwl_set_rate(priv);
b481de9c
ZY		 3011
3012 mutex_unlock(&priv->mutex);
3013
e1623446 3014 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3015}
3016
5b9f8cd3 3017static int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3018{
c79dd5b5 3019 struct iwl_priv *priv = hw->priv;
b481de9c 3020 unsigned long flags;
2ff75b78 3021 __le64 timestamp;
b481de9c 3022
e1623446 3023 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3024
fee1247a 3025 if (!iwl_is_ready_rf(priv)) {
e1623446 3026 IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
b481de9c
ZY		 3027 return -EIO;
3028 }
3029
05c914fe 3030 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
e1623446 3031 IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
b481de9c
ZY		 3032 return -EIO;
3033 }
3034
3035 spin_lock_irqsave(&priv->lock, flags);
3036
3037 if (priv->ibss_beacon)
3038 dev_kfree_skb(priv->ibss_beacon);
3039
3040 priv->ibss_beacon = skb;
3041
3042 priv->assoc_id = 0;
2ff75b78 3043 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
b94d8eea 3044 priv->timestamp = le64_to_cpu(timestamp);
b481de9c 3045
e1623446 3046 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3047 spin_unlock_irqrestore(&priv->lock, flags);
3048
c7de35cd 3049 iwl_reset_qos(priv);
b481de9c 3050
5b9f8cd3 3051 iwl_post_associate(priv);
b481de9c 3052
b481de9c
ZY		 3053
3054 return 0;
3055}
3056
b481de9c
ZY		 3057/*****************************************************************************
3058 *
3059 * sysfs attributes
3060 *
3061 *****************************************************************************/
3062
0a6857e7 3063#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 3064
3065/*
3066 * The following adds a new attribute to the sysfs representation
c3a739fa 3067 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY		 3068 * used for controlling the debug level.
3069 *
3070 * See the level definitions in iwl for details.
3071 */
3072
8cf769c6
EK		 3073static ssize_t show_debug_level(struct device *d,
3074 struct device_attribute *attr, char *buf)
b481de9c 3075{
8cf769c6
EK		 3076 struct iwl_priv *priv = d->driver_data;
3077
3078 return sprintf(buf, "0x%08X\n", priv->debug_level);
b481de9c 3079}
8cf769c6
EK		 3080static ssize_t store_debug_level(struct device *d,
3081 struct device_attribute *attr,
b481de9c
ZY		 3082 const char *buf, size_t count)
3083{
8cf769c6 3084 struct iwl_priv *priv = d->driver_data;
9257746f
TW		 3085 unsigned long val;
3086 int ret;
b481de9c 3087
9257746f
TW		 3088 ret = strict_strtoul(buf, 0, &val);
3089 if (ret)
978785a3 3090 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 3091 else
8cf769c6 3092 priv->debug_level = val;
b481de9c
ZY		 3093
3094 return strnlen(buf, count);
3095}
3096
8cf769c6
EK		 3097static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
3098 show_debug_level, store_debug_level);
3099
b481de9c 3100
0a6857e7 3101#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 3102
b481de9c 3103
bc6f59bc
TW		 3104static ssize_t show_version(struct device *d,
3105 struct device_attribute *attr, char *buf)
3106{
3107 struct iwl_priv *priv = d->driver_data;
885ba202 3108 struct iwl_alive_resp *palive = &priv->card_alive;
f236a265
TW		 3109 ssize_t pos = 0;
3110 u16 eeprom_ver;
bc6f59bc
TW		 3111
3112 if (palive->is_valid)
f236a265
TW		 3113 pos += sprintf(buf + pos,
3114 "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
3115 "fw type: 0x%01X 0x%01X\n",
bc6f59bc
TW		 3116 palive->ucode_major, palive->ucode_minor,
3117 palive->sw_rev[0], palive->sw_rev[1],
3118 palive->ver_type, palive->ver_subtype);
bc6f59bc 3119 else
f236a265
TW		 3120 pos += sprintf(buf + pos, "fw not loaded\n");
3121
3122 if (priv->eeprom) {
3123 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
3124 pos += sprintf(buf + pos, "EEPROM version: 0x%x\n",
3125 eeprom_ver);
3126 } else {
3127 pos += sprintf(buf + pos, "EEPROM not initialzed\n");
3128 }
3129
3130 return pos;
bc6f59bc
TW		 3131}
3132
3133static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
3134
b481de9c
ZY		 3135static ssize_t show_temperature(struct device *d,
3136 struct device_attribute *attr, char *buf)
3137{
c79dd5b5 3138 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c 3139
fee1247a 3140 if (!iwl_is_alive(priv))
b481de9c
ZY		 3141 return -EAGAIN;
3142
91dbc5bd 3143 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY		 3144}
3145
3146static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
3147
b481de9c
ZY		 3148static ssize_t show_tx_power(struct device *d,
3149 struct device_attribute *attr, char *buf)
3150{
c79dd5b5 3151 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
91f39e8e
JS		 3152
3153 if (!iwl_is_ready_rf(priv))
3154 return sprintf(buf, "off\n");
3155 else
3156 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY		 3157}
3158
3159static ssize_t store_tx_power(struct device *d,
3160 struct device_attribute *attr,
3161 const char *buf, size_t count)
3162{
c79dd5b5 3163 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
9257746f
TW		 3164 unsigned long val;
3165 int ret;
b481de9c 3166
9257746f
TW		 3167 ret = strict_strtoul(buf, 10, &val);
3168 if (ret)
978785a3 3169 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
b481de9c 3170 else
630fe9b6 3171 iwl_set_tx_power(priv, val, false);
b481de9c
ZY		 3172
3173 return count;
3174}
3175
3176static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
3177
3178static ssize_t show_flags(struct device *d,
3179 struct device_attribute *attr, char *buf)
3180{
c79dd5b5 3181 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 3182
3183 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
3184}
3185
3186static ssize_t store_flags(struct device *d,
3187 struct device_attribute *attr,
3188 const char *buf, size_t count)
3189{
c79dd5b5 3190 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
9257746f
TW		 3191 unsigned long val;
3192 u32 flags;
3193 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 3194 if (ret)
9257746f
TW		 3195 return ret;
3196 flags = (u32)val;
b481de9c
ZY		 3197
3198 mutex_lock(&priv->mutex);
3199 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
3200 /* Cancel any currently running scans... */
2a421b91 3201 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3202 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3203 else {
e1623446 3204 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 3205 priv->staging_rxon.flags = cpu_to_le32(flags);
5b9f8cd3 3206 iwl_commit_rxon(priv);
b481de9c
ZY		 3207 }
3208 }
3209 mutex_unlock(&priv->mutex);
3210
3211 return count;
3212}
3213
3214static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
3215
3216static ssize_t show_filter_flags(struct device *d,
3217 struct device_attribute *attr, char *buf)
3218{
c79dd5b5 3219 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
b481de9c
ZY		 3220
3221 return sprintf(buf, "0x%04X\n",
3222 le32_to_cpu(priv->active_rxon.filter_flags));
3223}
3224
3225static ssize_t store_filter_flags(struct device *d,
3226 struct device_attribute *attr,
3227 const char *buf, size_t count)
3228{
c79dd5b5 3229 struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
9257746f
TW		 3230 unsigned long val;
3231 u32 filter_flags;
3232 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 3233 if (ret)
9257746f
TW		 3234 return ret;
3235 filter_flags = (u32)val;
b481de9c
ZY		 3236
3237 mutex_lock(&priv->mutex);
3238 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
3239 /* Cancel any currently running scans... */
2a421b91 3240 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 3241 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 3242 else {
e1623446 3243 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY		 3244 "0x%04X\n", filter_flags);
3245 priv->staging_rxon.filter_flags =
3246 cpu_to_le32(filter_flags);
5b9f8cd3 3247 iwl_commit_rxon(priv);
b481de9c
ZY		 3248 }
3249 }
3250 mutex_unlock(&priv->mutex);
3251
3252 return count;
3253}
3254
3255static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
3256 store_filter_flags);
3257
b481de9c
ZY		 3258static ssize_t store_power_level(struct device *d,
3259 struct device_attribute *attr,
3260 const char *buf, size_t count)
3261{
c79dd5b5 3262 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6 3263 int ret;
9257746f
TW		 3264 unsigned long mode;
3265
b481de9c 3266
b481de9c
ZY		 3267 mutex_lock(&priv->mutex);
3268
fee1247a 3269 if (!iwl_is_ready(priv)) {
298df1f6 3270 ret = -EAGAIN;
b481de9c
ZY		 3271 goto out;
3272 }
3273
9257746f 3274 ret = strict_strtoul(buf, 10, &mode);
926f0b2e 3275 if (ret)
9257746f
TW		 3276 goto out;
3277
298df1f6
EK		 3278 ret = iwl_power_set_user_mode(priv, mode);
3279 if (ret) {
e1623446 3280 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
5da4b55f 3281 goto out;
b481de9c 3282 }
298df1f6 3283 ret = count;
b481de9c
ZY		 3284
3285 out:
3286 mutex_unlock(&priv->mutex);
298df1f6 3287 return ret;
b481de9c
ZY		 3288}
3289
b481de9c
ZY		 3290static ssize_t show_power_level(struct device *d,
3291 struct device_attribute *attr, char *buf)
3292{
c79dd5b5 3293 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6
EK		 3294 int mode = priv->power_data.user_power_setting;
3295 int system = priv->power_data.system_power_setting;
5da4b55f 3296 int level = priv->power_data.power_mode;
b481de9c
ZY		 3297 char *p = buf;
3298
298df1f6
EK		 3299 switch (system) {
3300 case IWL_POWER_SYS_AUTO:
3301 p += sprintf(p, "SYSTEM:auto");
b481de9c 3302 break;
298df1f6
EK		 3303 case IWL_POWER_SYS_AC:
3304 p += sprintf(p, "SYSTEM:ac");
3305 break;
3306 case IWL_POWER_SYS_BATTERY:
3307 p += sprintf(p, "SYSTEM:battery");
b481de9c 3308 break;
b481de9c 3309 }
298df1f6 3310
c3056065
AK		 3311 p += sprintf(p, "\tMODE:%s", (mode < IWL_POWER_AUTO) ?
3312 "fixed" : "auto");
298df1f6
EK		 3313 p += sprintf(p, "\tINDEX:%d", level);
3314 p += sprintf(p, "\n");
3ac7f146 3315 return p - buf + 1;
b481de9c
ZY		 3316}
3317
3318static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
3319 store_power_level);
3320
b481de9c
ZY		 3321
3322static ssize_t show_statistics(struct device *d,
3323 struct device_attribute *attr, char *buf)
3324{
c79dd5b5 3325 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 3326 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 3327 u32 len = 0, ofs = 0;
3ac7f146 3328 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY		 3329 int rc = 0;
3330
fee1247a 3331 if (!iwl_is_alive(priv))
b481de9c
ZY		 3332 return -EAGAIN;
3333
3334 mutex_lock(&priv->mutex);
49ea8596 3335 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY		 3336 mutex_unlock(&priv->mutex);
3337
3338 if (rc) {
3339 len = sprintf(buf,
3340 "Error sending statistics request: 0x%08X\n", rc);
3341 return len;
3342 }
3343
3344 while (size && (PAGE_SIZE - len)) {
3345 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
3346 PAGE_SIZE - len, 1);
3347 len = strlen(buf);
3348 if (PAGE_SIZE - len)
3349 buf[len++] = '\n';
3350
3351 ofs += 16;
3352 size -= min(size, 16U);
3353 }
3354
3355 return len;
3356}
3357
3358static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
3359
b481de9c 3360
b481de9c
ZY		 3361/*****************************************************************************
3362 *
3363 * driver setup and teardown
3364 *
3365 *****************************************************************************/
3366
4e39317d 3367static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 3368{
3369 priv->workqueue = create_workqueue(DRV_NAME);
3370
3371 init_waitqueue_head(&priv->wait_command_queue);
3372
5b9f8cd3
EG		 3373 INIT_WORK(&priv->up, iwl_bg_up);
3374 INIT_WORK(&priv->restart, iwl_bg_restart);
3375 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3376 INIT_WORK(&priv->rf_kill, iwl_bg_rf_kill);
3377 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3378 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW		 3379 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3380 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3381
2a421b91 3382 iwl_setup_scan_deferred_work(priv);
c90a74ba 3383 iwl_setup_power_deferred_work(priv);
bb8c093b 3384
4e39317d
EG		 3385 if (priv->cfg->ops->lib->setup_deferred_work)
3386 priv->cfg->ops->lib->setup_deferred_work(priv);
3387
3388 init_timer(&priv->statistics_periodic);
3389 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3390 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c
ZY		 3391
3392 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
5b9f8cd3 3393 iwl_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 3394}
3395
4e39317d 3396static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3397{
4e39317d
EG		 3398 if (priv->cfg->ops->lib->cancel_deferred_work)
3399 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3400
3ae6a054 3401 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3402 cancel_delayed_work(&priv->scan_check);
c90a74ba 3403 cancel_delayed_work_sync(&priv->set_power_save);
b481de9c 3404 cancel_delayed_work(&priv->alive_start);
b481de9c 3405 cancel_work_sync(&priv->beacon_update);
4e39317d 3406 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY		 3407}
3408
5b9f8cd3 3409static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY		 3410 &dev_attr_flags.attr,
3411 &dev_attr_filter_flags.attr,
b481de9c 3412 &dev_attr_power_level.attr,
b481de9c 3413 &dev_attr_statistics.attr,
b481de9c 3414 &dev_attr_temperature.attr,
b481de9c 3415 &dev_attr_tx_power.attr,
8cf769c6
EK		 3416#ifdef CONFIG_IWLWIFI_DEBUG
3417 &dev_attr_debug_level.attr,
3418#endif
bc6f59bc 3419 &dev_attr_version.attr,
b481de9c
ZY		 3420
3421 NULL
3422};
3423
5b9f8cd3 3424static struct attribute_group iwl_attribute_group = {
b481de9c 3425 .name = NULL, /* put in device directory */
5b9f8cd3 3426 .attrs = iwl_sysfs_entries,
b481de9c
ZY		 3427};
3428
5b9f8cd3
EG		 3429static struct ieee80211_ops iwl_hw_ops = {
3430 .tx = iwl_mac_tx,
3431 .start = iwl_mac_start,
3432 .stop = iwl_mac_stop,
3433 .add_interface = iwl_mac_add_interface,
3434 .remove_interface = iwl_mac_remove_interface,
3435 .config = iwl_mac_config,
3436 .config_interface = iwl_mac_config_interface,
3437 .configure_filter = iwl_configure_filter,
3438 .set_key = iwl_mac_set_key,
3439 .update_tkip_key = iwl_mac_update_tkip_key,
3440 .get_stats = iwl_mac_get_stats,
3441 .get_tx_stats = iwl_mac_get_tx_stats,
3442 .conf_tx = iwl_mac_conf_tx,
3443 .reset_tsf = iwl_mac_reset_tsf,
3444 .bss_info_changed = iwl_bss_info_changed,
3445 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 3446 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY		 3447};
3448
5b9f8cd3 3449static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 3450{
3451 int err = 0;
c79dd5b5 3452 struct iwl_priv *priv;
b481de9c 3453 struct ieee80211_hw *hw;
82b9a121 3454 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3455 unsigned long flags;
6cd0b1cb 3456 u16 pci_cmd;
b481de9c 3457
316c30d9
AK		 3458 /************************
3459 * 1. Allocating HW data
3460 ************************/
3461
6440adb5
CB		 3462 /* Disabling hardware scan means that mac80211 will perform scans
3463 * "the hard way", rather than using device's scan. */
1ea87396 3464 if (cfg->mod_params->disable_hw_scan) {
bf403db8
EK		 3465 if (cfg->mod_params->debug & IWL_DL_INFO)
3466 dev_printk(KERN_DEBUG, &(pdev->dev),
3467 "Disabling hw_scan\n");
5b9f8cd3 3468 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 3469 }
3470
5b9f8cd3 3471 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3472 if (!hw) {
b481de9c
ZY		 3473 err = -ENOMEM;
3474 goto out;
3475 }
1d0a082d
AK		 3476 priv = hw->priv;
3477 /* At this point both hw and priv are allocated. */
3478
b481de9c
ZY		 3479 SET_IEEE80211_DEV(hw, &pdev->dev);
3480
e1623446 3481 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3482 priv->cfg = cfg;
b481de9c 3483 priv->pci_dev = pdev;
316c30d9 3484
0a6857e7 3485#ifdef CONFIG_IWLWIFI_DEBUG
bf403db8 3486 priv->debug_level = priv->cfg->mod_params->debug;
b481de9c
ZY		 3487 atomic_set(&priv->restrict_refcnt, 0);
3488#endif
b481de9c 3489
316c30d9
AK		 3490 /**************************
3491 * 2. Initializing PCI bus
3492 **************************/
3493 if (pci_enable_device(pdev)) {
3494 err = -ENODEV;
3495 goto out_ieee80211_free_hw;
3496 }
3497
3498 pci_set_master(pdev);
3499
093d874c 3500 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3501 if (!err)
093d874c 3502 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3503 if (err) {
093d874c 3504 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3505 if (!err)
093d874c 3506 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3507 /* both attempts failed: */
316c30d9 3508 if (err) {
978785a3 3509 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3510 goto out_pci_disable_device;
cc2a8ea8 3511 }
316c30d9
AK		 3512 }
3513
3514 err = pci_request_regions(pdev, DRV_NAME);
3515 if (err)
3516 goto out_pci_disable_device;
3517
3518 pci_set_drvdata(pdev, priv);
3519
316c30d9
AK		 3520
3521 /***********************
3522 * 3. Read REV register
3523 ***********************/
3524 priv->hw_base = pci_iomap(pdev, 0, 0);
3525 if (!priv->hw_base) {
3526 err = -ENODEV;
3527 goto out_pci_release_regions;
3528 }
3529
e1623446 3530 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3531 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3532 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3533
b661c819 3534 iwl_hw_detect(priv);
978785a3 3535 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3536 priv->cfg->name, priv->hw_rev);
316c30d9 3537
e7b63581
TW		 3538 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3539 * PCI Tx retries from interfering with C3 CPU state */
3540 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3541
91238714
TW		 3542 /* amp init */
3543 err = priv->cfg->ops->lib->apm_ops.init(priv);
316c30d9 3544 if (err < 0) {
e1623446 3545 IWL_DEBUG_INFO(priv, "Failed to init APMG\n");
316c30d9
AK		 3546 goto out_iounmap;
3547 }
91238714
TW		 3548 /*****************
3549 * 4. Read EEPROM
3550 *****************/
316c30d9
AK		 3551 /* Read the EEPROM */
3552 err = iwl_eeprom_init(priv);
3553 if (err) {
15b1687c 3554 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 3555 goto out_iounmap;
3556 }
8614f360
TW		 3557 err = iwl_eeprom_check_version(priv);
3558 if (err)
3559 goto out_iounmap;
3560
02883017 3561 /* extract MAC Address */
316c30d9 3562 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3563 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK		 3564 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3565
3566 /************************
3567 * 5. Setup HW constants
3568 ************************/
da154e30 3569 if (iwl_set_hw_params(priv)) {
15b1687c 3570 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3571 goto out_free_eeprom;
316c30d9
AK		 3572 }
3573
3574 /*******************
6ba87956 3575 * 6. Setup priv
316c30d9 3576 *******************/
b481de9c 3577
6ba87956 3578 err = iwl_init_drv(priv);
bf85ea4f 3579 if (err)
399f4900 3580 goto out_free_eeprom;
bf85ea4f 3581 /* At this point both hw and priv are initialized. */
316c30d9
AK		 3582
3583 /**********************************
3584 * 7. Initialize module parameters
3585 **********************************/
3586
3587 /* Disable radio (SW RF KILL) via parameter when loading driver */
1ea87396 3588 if (priv->cfg->mod_params->disable) {
316c30d9 3589 set_bit(STATUS_RF_KILL_SW, &priv->status);
e1623446 3590 IWL_DEBUG_INFO(priv, "Radio disabled.\n");
316c30d9
AK		 3591 }
3592
316c30d9
AK		 3593 /********************
3594 * 8. Setup services
3595 ********************/
0359facc 3596 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3597 iwl_disable_interrupts(priv);
0359facc 3598 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3599
6cd0b1cb
HS		 3600 pci_enable_msi(priv->pci_dev);
3601
3602 err = request_irq(priv->pci_dev->irq, iwl_isr, IRQF_SHARED,
3603 DRV_NAME, priv);
3604 if (err) {
3605 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3606 goto out_disable_msi;
3607 }
5b9f8cd3 3608 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3609 if (err) {
15b1687c 3610 IWL_ERR(priv, "failed to create sysfs device attributes\n");
6ba87956 3611 goto out_uninit_drv;
316c30d9
AK		 3612 }
3613
4e39317d 3614 iwl_setup_deferred_work(priv);
653fa4a0 3615 iwl_setup_rx_handlers(priv);
316c30d9 3616
6ba87956 3617 /**********************************
6cd0b1cb 3618 * 9. Setup and register mac80211
6ba87956
TW		 3619 **********************************/
3620
6cd0b1cb
HS		 3621 /* enable interrupts if needed: hw bug w/a */
3622 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3623 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3624 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3625 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3626 }
3627
3628 iwl_enable_interrupts(priv);
3629
6ba87956
TW		 3630 err = iwl_setup_mac(priv);
3631 if (err)
3632 goto out_remove_sysfs;
3633
3634 err = iwl_dbgfs_register(priv, DRV_NAME);
3635 if (err)
15b1687c 3636 IWL_ERR(priv, "failed to create debugfs files\n");
6ba87956 3637
6cd0b1cb
HS		 3638 /* If platform's RF_KILL switch is NOT set to KILL */
3639 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3640 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3641 else
3642 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3643
58d0f361
EG		 3644 err = iwl_rfkill_init(priv);
3645 if (err)
15b1687c 3646 IWL_ERR(priv, "Unable to initialize RFKILL system. "
58d0f361 3647 "Ignoring error: %d\n", err);
6cd0b1cb
HS		 3648 else
3649 iwl_rfkill_set_hw_state(priv);
3650
58d0f361 3651 iwl_power_initialize(priv);
b481de9c
ZY		 3652 return 0;
3653
316c30d9 3654 out_remove_sysfs:
5b9f8cd3 3655 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
6cd0b1cb
HS		 3656 out_disable_msi:
3657 pci_disable_msi(priv->pci_dev);
3658 pci_disable_device(priv->pci_dev);
6ba87956
TW		 3659 out_uninit_drv:
3660 iwl_uninit_drv(priv);
073d3f5f
TW		 3661 out_free_eeprom:
3662 iwl_eeprom_free(priv);
b481de9c
ZY		 3663 out_iounmap:
3664 pci_iounmap(pdev, priv->hw_base);
3665 out_pci_release_regions:
3666 pci_release_regions(pdev);
316c30d9 3667 pci_set_drvdata(pdev, NULL);
b481de9c
ZY		 3668 out_pci_disable_device:
3669 pci_disable_device(pdev);
b481de9c
ZY		 3670 out_ieee80211_free_hw:
3671 ieee80211_free_hw(priv->hw);
3672 out:
3673 return err;
3674}
3675
5b9f8cd3 3676static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3677{
c79dd5b5 3678 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3679 unsigned long flags;
b481de9c
ZY		 3680
3681 if (!priv)
3682 return;
3683
e1623446 3684 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3685
67249625 3686 iwl_dbgfs_unregister(priv);
5b9f8cd3 3687 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3688
5b9f8cd3
EG		 3689 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3690 * to be called and iwl_down since we are removing the device
0b124c31
GG		 3691 * we need to set STATUS_EXIT_PENDING bit.
3692 */
3693 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 3694 if (priv->mac80211_registered) {
3695 ieee80211_unregister_hw(priv->hw);
3696 priv->mac80211_registered = 0;
0b124c31 3697 } else {
5b9f8cd3 3698 iwl_down(priv);
c4f55232
RR		 3699 }
3700
0359facc
MA		 3701 /* make sure we flush any pending irq or
3702 * tasklet for the driver
3703 */
3704 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3705 iwl_disable_interrupts(priv);
0359facc
MA		 3706 spin_unlock_irqrestore(&priv->lock, flags);
3707
3708 iwl_synchronize_irq(priv);
3709
58d0f361 3710 iwl_rfkill_unregister(priv);
5b9f8cd3 3711 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 3712
3713 if (priv->rxq.bd)
a55360e4 3714 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3715 iwl_hw_txq_ctx_free(priv);
b481de9c 3716
37deb2a0 3717 iwl_clear_stations_table(priv);
073d3f5f 3718 iwl_eeprom_free(priv);
b481de9c 3719
b481de9c 3720
948c171c
MA		 3721 /*netif_stop_queue(dev); */
3722 flush_workqueue(priv->workqueue);
3723
5b9f8cd3 3724 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 3725 * priv->workqueue... so we can't take down the workqueue
3726 * until now... */
3727 destroy_workqueue(priv->workqueue);
3728 priv->workqueue = NULL;
3729
6cd0b1cb
HS		 3730 free_irq(priv->pci_dev->irq, priv);
3731 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 3732 pci_iounmap(pdev, priv->hw_base);
3733 pci_release_regions(pdev);
3734 pci_disable_device(pdev);
3735 pci_set_drvdata(pdev, NULL);
3736
6ba87956 3737 iwl_uninit_drv(priv);
b481de9c
ZY		 3738
3739 if (priv->ibss_beacon)
3740 dev_kfree_skb(priv->ibss_beacon);
3741
3742 ieee80211_free_hw(priv->hw);
3743}
3744
3745#ifdef CONFIG_PM
3746
5b9f8cd3 3747static int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
b481de9c 3748{
c79dd5b5 3749 struct iwl_priv *priv = pci_get_drvdata(pdev);
b481de9c 3750
e655b9f0
ZY		 3751 if (priv->is_open) {
3752 set_bit(STATUS_IN_SUSPEND, &priv->status);
5b9f8cd3 3753 iwl_mac_stop(priv->hw);
e655b9f0
ZY		 3754 priv->is_open = 1;
3755 }
b481de9c 3756
6cd0b1cb
HS		 3757 pci_save_state(pdev);
3758 pci_disable_device(pdev);
b481de9c
ZY		 3759 pci_set_power_state(pdev, PCI_D3hot);
3760
b481de9c
ZY		 3761 return 0;
3762}
3763
5b9f8cd3 3764static int iwl_pci_resume(struct pci_dev *pdev)
b481de9c 3765{
c79dd5b5 3766 struct iwl_priv *priv = pci_get_drvdata(pdev);
450154e4 3767 int ret;
b481de9c 3768
b481de9c 3769 pci_set_power_state(pdev, PCI_D0);
450154e4
WT		 3770 ret = pci_enable_device(pdev);
3771 if (ret)
3772 return ret;
6cd0b1cb
HS		 3773 pci_restore_state(pdev);
3774 iwl_enable_interrupts(priv);
b481de9c 3775
e655b9f0 3776 if (priv->is_open)
5b9f8cd3 3777 iwl_mac_start(priv->hw);
b481de9c 3778
e655b9f0 3779 clear_bit(STATUS_IN_SUSPEND, &priv->status);
b481de9c
ZY		 3780 return 0;
3781}
3782
3783#endif /* CONFIG_PM */
3784
3785/*****************************************************************************
3786 *
3787 * driver and module entry point
3788 *
3789 *****************************************************************************/
3790
fed9017e
RR		 3791/* Hardware specific file defines the PCI IDs table for that hardware module */
3792static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3793#ifdef CONFIG_IWL4965
fed9017e
RR		 3794 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3795 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3796#endif /* CONFIG_IWL4965 */
5a6a256e 3797#ifdef CONFIG_IWL5000
47408639
EK		 3798 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3799 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3800 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3801 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3802 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3803 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3804 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK		 3805 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3806 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3807 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW		 3808/* 5350 WiFi/WiMax */
3809 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3810 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3811 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW		 3812/* 5150 Wifi/WiMax */
3813 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3814 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
e1228374
JS		 3815/* 6000/6050 Series */
3816 {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
3817 {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
3818 {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
3819 {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
3820 {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
3821 {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
3822 {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
3823 {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
3824 {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
3825 {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
3826 {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
c5d05698
JS		 3827/* 100 Series WiFi */
3828 {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl100_bgn_cfg)},
3829 {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl100_bgn_cfg)},
5a6a256e 3830#endif /* CONFIG_IWL5000 */
7100e924 3831
fed9017e
RR		 3832 {0}
3833};
3834MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3835
3836static struct pci_driver iwl_driver = {
b481de9c 3837 .name = DRV_NAME,
fed9017e 3838 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 3839 .probe = iwl_pci_probe,
3840 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3841#ifdef CONFIG_PM
5b9f8cd3
EG		 3842 .suspend = iwl_pci_suspend,
3843 .resume = iwl_pci_resume,
b481de9c
ZY		 3844#endif
3845};
3846
5b9f8cd3 3847static int __init iwl_init(void)
b481de9c
ZY		 3848{
3849
3850 int ret;
3851 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3852 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3853
e227ceac 3854 ret = iwlagn_rate_control_register();
897e1cf2 3855 if (ret) {
a3139c59
SO		 3856 printk(KERN_ERR DRV_NAME
3857 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 3858 return ret;
3859 }
3860
fed9017e 3861 ret = pci_register_driver(&iwl_driver);
b481de9c 3862 if (ret) {
a3139c59 3863 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3864 goto error_register;
b481de9c 3865 }
b481de9c
ZY		 3866
3867 return ret;
897e1cf2 3868
897e1cf2 3869error_register:
e227ceac 3870 iwlagn_rate_control_unregister();
897e1cf2 3871 return ret;
b481de9c
ZY		 3872}
3873
5b9f8cd3 3874static void __exit iwl_exit(void)
b481de9c 3875{
fed9017e 3876 pci_unregister_driver(&iwl_driver);
e227ceac 3877 iwlagn_rate_control_unregister();
b481de9c
ZY		 3878}
3879
5b9f8cd3
EG		 3880module_exit(iwl_exit);
3881module_init(iwl_init);
Linux kernel - Deliverables
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