Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
c96c31e4 JP |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
b481de9c ZY |
32 | #include <linux/kernel.h> |
33 | #include <linux/module.h> | |
b481de9c | 34 | #include <linux/init.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
b481de9c ZY |
36 | #include <linux/dma-mapping.h> |
37 | #include <linux/delay.h> | |
d43c36dc | 38 | #include <linux/sched.h> |
b481de9c ZY |
39 | #include <linux/skbuff.h> |
40 | #include <linux/netdevice.h> | |
41 | #include <linux/wireless.h> | |
42 | #include <linux/firmware.h> | |
b481de9c ZY |
43 | #include <linux/etherdevice.h> |
44 | #include <linux/if_arp.h> | |
45 | ||
b481de9c ZY |
46 | #include <net/mac80211.h> |
47 | ||
48 | #include <asm/div64.h> | |
49 | ||
6bc913bd | 50 | #include "iwl-eeprom.h" |
3e0d4cb1 | 51 | #include "iwl-dev.h" |
fee1247a | 52 | #include "iwl-core.h" |
3395f6e9 | 53 | #include "iwl-io.h" |
b481de9c | 54 | #include "iwl-helpers.h" |
6974e363 | 55 | #include "iwl-sta.h" |
0de76736 | 56 | #include "iwl-agn-calib.h" |
a1175124 | 57 | #include "iwl-agn.h" |
48d1a211 | 58 | #include "iwl-pci.h" |
b481de9c | 59 | |
416e1438 | 60 | |
b481de9c ZY |
61 | /****************************************************************************** |
62 | * | |
63 | * module boiler plate | |
64 | * | |
65 | ******************************************************************************/ | |
66 | ||
b481de9c ZY |
67 | /* |
68 | * module name, copyright, version, etc. | |
b481de9c | 69 | */ |
d783b061 | 70 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 71 | |
0a6857e7 | 72 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
73 | #define VD "d" |
74 | #else | |
75 | #define VD | |
76 | #endif | |
77 | ||
81963d68 | 78 | #define DRV_VERSION IWLWIFI_VERSION VD |
b481de9c | 79 | |
b481de9c ZY |
80 | |
81 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
82 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 83 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
84 | MODULE_LICENSE("GPL"); |
85 | ||
bee008b7 | 86 | static int iwlagn_ant_coupling; |
f37837c9 | 87 | static bool iwlagn_bt_ch_announce = 1; |
bee008b7 | 88 | |
5b9f8cd3 | 89 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f | 90 | { |
246ed355 | 91 | struct iwl_rxon_context *ctx; |
5da4b55f | 92 | |
246ed355 JB |
93 | if (priv->cfg->ops->hcmd->set_rxon_chain) { |
94 | for_each_context(priv, ctx) { | |
95 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
6163a373 | 96 | if (ctx->active.rx_chain != ctx->staging.rx_chain) |
805a3b81 | 97 | iwlagn_commit_rxon(priv, ctx); |
246ed355 JB |
98 | } |
99 | } | |
5da4b55f MA |
100 | } |
101 | ||
47ff65c4 DH |
102 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ |
103 | static void iwl_set_beacon_tim(struct iwl_priv *priv, | |
77834543 JB |
104 | struct iwl_tx_beacon_cmd *tx_beacon_cmd, |
105 | u8 *beacon, u32 frame_size) | |
47ff65c4 DH |
106 | { |
107 | u16 tim_idx; | |
108 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
109 | ||
110 | /* | |
111 | * The index is relative to frame start but we start looking at the | |
112 | * variable-length part of the beacon. | |
113 | */ | |
114 | tim_idx = mgmt->u.beacon.variable - beacon; | |
115 | ||
116 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
117 | while ((tim_idx < (frame_size - 2)) && | |
118 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
119 | tim_idx += beacon[tim_idx+1] + 2; | |
120 | ||
121 | /* If TIM field was found, set variables */ | |
122 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
123 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
124 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
125 | } else | |
126 | IWL_WARN(priv, "Unable to find TIM Element in beacon\n"); | |
127 | } | |
128 | ||
8a98d49e | 129 | int iwlagn_send_beacon_cmd(struct iwl_priv *priv) |
4bf64efd TW |
130 | { |
131 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
8a98d49e JB |
132 | struct iwl_host_cmd cmd = { |
133 | .id = REPLY_TX_BEACON, | |
8a98d49e | 134 | }; |
47ff65c4 DH |
135 | u32 frame_size; |
136 | u32 rate_flags; | |
137 | u32 rate; | |
8a98d49e | 138 | |
47ff65c4 DH |
139 | /* |
140 | * We have to set up the TX command, the TX Beacon command, and the | |
141 | * beacon contents. | |
142 | */ | |
4bf64efd | 143 | |
76d04815 JB |
144 | lockdep_assert_held(&priv->mutex); |
145 | ||
146 | if (!priv->beacon_ctx) { | |
147 | IWL_ERR(priv, "trying to build beacon w/o beacon context!\n"); | |
950094cb | 148 | return 0; |
76d04815 JB |
149 | } |
150 | ||
8a98d49e JB |
151 | if (WARN_ON(!priv->beacon_skb)) |
152 | return -EINVAL; | |
153 | ||
4ce7cc2b JB |
154 | /* Allocate beacon command */ |
155 | if (!priv->beacon_cmd) | |
156 | priv->beacon_cmd = kzalloc(sizeof(*tx_beacon_cmd), GFP_KERNEL); | |
157 | tx_beacon_cmd = priv->beacon_cmd; | |
8a98d49e JB |
158 | if (!tx_beacon_cmd) |
159 | return -ENOMEM; | |
160 | ||
161 | frame_size = priv->beacon_skb->len; | |
4bf64efd | 162 | |
47ff65c4 | 163 | /* Set up TX command fields */ |
4bf64efd | 164 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); |
76d04815 | 165 | tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id; |
47ff65c4 DH |
166 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
167 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
168 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
4bf64efd | 169 | |
47ff65c4 | 170 | /* Set up TX beacon command fields */ |
4ce7cc2b | 171 | iwl_set_beacon_tim(priv, tx_beacon_cmd, priv->beacon_skb->data, |
77834543 | 172 | frame_size); |
4bf64efd | 173 | |
47ff65c4 | 174 | /* Set up packet rate and flags */ |
76d04815 | 175 | rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx); |
0e1654fa JB |
176 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, |
177 | priv->hw_params.valid_tx_ant); | |
47ff65c4 DH |
178 | rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); |
179 | if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) | |
180 | rate_flags |= RATE_MCS_CCK_MSK; | |
181 | tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, | |
182 | rate_flags); | |
4bf64efd | 183 | |
8a98d49e | 184 | /* Submit command */ |
4ce7cc2b | 185 | cmd.len[0] = sizeof(*tx_beacon_cmd); |
3fa50738 | 186 | cmd.data[0] = tx_beacon_cmd; |
4ce7cc2b JB |
187 | cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY; |
188 | cmd.len[1] = frame_size; | |
189 | cmd.data[1] = priv->beacon_skb->data; | |
190 | cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY; | |
7aaa1d79 | 191 | |
4ce7cc2b | 192 | return iwl_send_cmd_sync(priv, &cmd); |
a8e74e27 SO |
193 | } |
194 | ||
5b9f8cd3 | 195 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 196 | { |
c79dd5b5 TW |
197 | struct iwl_priv *priv = |
198 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
199 | struct sk_buff *beacon; |
200 | ||
76d04815 JB |
201 | mutex_lock(&priv->mutex); |
202 | if (!priv->beacon_ctx) { | |
203 | IWL_ERR(priv, "updating beacon w/o beacon context!\n"); | |
204 | goto out; | |
205 | } | |
b481de9c | 206 | |
60744f62 JB |
207 | if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) { |
208 | /* | |
209 | * The ucode will send beacon notifications even in | |
210 | * IBSS mode, but we don't want to process them. But | |
211 | * we need to defer the type check to here due to | |
212 | * requiring locking around the beacon_ctx access. | |
213 | */ | |
214 | goto out; | |
215 | } | |
216 | ||
76d04815 JB |
217 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ |
218 | beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif); | |
b481de9c | 219 | if (!beacon) { |
77834543 | 220 | IWL_ERR(priv, "update beacon failed -- keeping old\n"); |
76d04815 | 221 | goto out; |
b481de9c ZY |
222 | } |
223 | ||
b481de9c | 224 | /* new beacon skb is allocated every time; dispose previous.*/ |
77834543 | 225 | dev_kfree_skb(priv->beacon_skb); |
b481de9c | 226 | |
12e934dc | 227 | priv->beacon_skb = beacon; |
b481de9c | 228 | |
2295c66b | 229 | iwlagn_send_beacon_cmd(priv); |
76d04815 JB |
230 | out: |
231 | mutex_unlock(&priv->mutex); | |
b481de9c ZY |
232 | } |
233 | ||
fbba9410 WYG |
234 | static void iwl_bg_bt_runtime_config(struct work_struct *work) |
235 | { | |
236 | struct iwl_priv *priv = | |
237 | container_of(work, struct iwl_priv, bt_runtime_config); | |
238 | ||
239 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
240 | return; | |
241 | ||
242 | /* dont send host command if rf-kill is on */ | |
243 | if (!iwl_is_ready_rf(priv)) | |
244 | return; | |
245 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
246 | } | |
247 | ||
bee008b7 WYG |
248 | static void iwl_bg_bt_full_concurrency(struct work_struct *work) |
249 | { | |
250 | struct iwl_priv *priv = | |
251 | container_of(work, struct iwl_priv, bt_full_concurrency); | |
246ed355 | 252 | struct iwl_rxon_context *ctx; |
bee008b7 | 253 | |
dc1a4068 SG |
254 | mutex_lock(&priv->mutex); |
255 | ||
bee008b7 | 256 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
dc1a4068 | 257 | goto out; |
bee008b7 WYG |
258 | |
259 | /* dont send host command if rf-kill is on */ | |
260 | if (!iwl_is_ready_rf(priv)) | |
dc1a4068 | 261 | goto out; |
bee008b7 WYG |
262 | |
263 | IWL_DEBUG_INFO(priv, "BT coex in %s mode\n", | |
264 | priv->bt_full_concurrent ? | |
265 | "full concurrency" : "3-wire"); | |
266 | ||
267 | /* | |
268 | * LQ & RXON updated cmds must be sent before BT Config cmd | |
269 | * to avoid 3-wire collisions | |
270 | */ | |
246ed355 JB |
271 | for_each_context(priv, ctx) { |
272 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
273 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
805a3b81 | 274 | iwlagn_commit_rxon(priv, ctx); |
246ed355 | 275 | } |
bee008b7 WYG |
276 | |
277 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
dc1a4068 SG |
278 | out: |
279 | mutex_unlock(&priv->mutex); | |
bee008b7 WYG |
280 | } |
281 | ||
4e39317d | 282 | /** |
5b9f8cd3 | 283 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
284 | * |
285 | * This callback is provided in order to send a statistics request. | |
286 | * | |
287 | * This timer function is continually reset to execute within | |
288 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
289 | * was received. We need to ensure we receive the statistics in order | |
290 | * to update the temperature used for calibrating the TXPOWER. | |
291 | */ | |
5b9f8cd3 | 292 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
293 | { |
294 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
295 | ||
296 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
297 | return; | |
298 | ||
61780ee3 MA |
299 | /* dont send host command if rf-kill is on */ |
300 | if (!iwl_is_ready_rf(priv)) | |
301 | return; | |
302 | ||
ef8d5529 | 303 | iwl_send_statistics_request(priv, CMD_ASYNC, false); |
4e39317d EG |
304 | } |
305 | ||
a9e1cb6a WYG |
306 | |
307 | static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |
308 | u32 start_idx, u32 num_events, | |
309 | u32 mode) | |
310 | { | |
311 | u32 i; | |
312 | u32 ptr; /* SRAM byte address of log data */ | |
313 | u32 ev, time, data; /* event log data */ | |
314 | unsigned long reg_flags; | |
315 | ||
316 | if (mode == 0) | |
317 | ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); | |
318 | else | |
319 | ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); | |
320 | ||
321 | /* Make sure device is powered up for SRAM reads */ | |
322 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
323 | if (iwl_grab_nic_access(priv)) { | |
324 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
325 | return; | |
326 | } | |
327 | ||
328 | /* Set starting address; reads will auto-increment */ | |
02a7fa00 | 329 | iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr); |
a9e1cb6a WYG |
330 | rmb(); |
331 | ||
332 | /* | |
333 | * "time" is actually "data" for mode 0 (no timestamp). | |
334 | * place event id # at far right for easier visual parsing. | |
335 | */ | |
336 | for (i = 0; i < num_events; i++) { | |
02a7fa00 JB |
337 | ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
338 | time = iwl_read32(priv, HBUS_TARG_MEM_RDAT); | |
a9e1cb6a WYG |
339 | if (mode == 0) { |
340 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
341 | 0, time, ev); | |
342 | } else { | |
02a7fa00 | 343 | data = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
a9e1cb6a WYG |
344 | trace_iwlwifi_dev_ucode_cont_event(priv, |
345 | time, data, ev); | |
346 | } | |
347 | } | |
348 | /* Allow device to power down */ | |
349 | iwl_release_nic_access(priv); | |
350 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
351 | } | |
352 | ||
875295f1 | 353 | static void iwl_continuous_event_trace(struct iwl_priv *priv) |
a9e1cb6a WYG |
354 | { |
355 | u32 capacity; /* event log capacity in # entries */ | |
356 | u32 base; /* SRAM byte address of event log header */ | |
357 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
358 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
359 | u32 next_entry; /* index of next entry to be written by uCode */ | |
360 | ||
d7d5783c | 361 | base = priv->device_pointers.error_event_table; |
a9e1cb6a WYG |
362 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
363 | capacity = iwl_read_targ_mem(priv, base); | |
364 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
365 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
366 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
367 | } else | |
368 | return; | |
369 | ||
370 | if (num_wraps == priv->event_log.num_wraps) { | |
371 | iwl_print_cont_event_trace(priv, | |
372 | base, priv->event_log.next_entry, | |
373 | next_entry - priv->event_log.next_entry, | |
374 | mode); | |
375 | priv->event_log.non_wraps_count++; | |
376 | } else { | |
377 | if ((num_wraps - priv->event_log.num_wraps) > 1) | |
378 | priv->event_log.wraps_more_count++; | |
379 | else | |
380 | priv->event_log.wraps_once_count++; | |
381 | trace_iwlwifi_dev_ucode_wrap_event(priv, | |
382 | num_wraps - priv->event_log.num_wraps, | |
383 | next_entry, priv->event_log.next_entry); | |
384 | if (next_entry < priv->event_log.next_entry) { | |
385 | iwl_print_cont_event_trace(priv, base, | |
386 | priv->event_log.next_entry, | |
387 | capacity - priv->event_log.next_entry, | |
388 | mode); | |
389 | ||
390 | iwl_print_cont_event_trace(priv, base, 0, | |
391 | next_entry, mode); | |
392 | } else { | |
393 | iwl_print_cont_event_trace(priv, base, | |
394 | next_entry, capacity - next_entry, | |
395 | mode); | |
396 | ||
397 | iwl_print_cont_event_trace(priv, base, 0, | |
398 | next_entry, mode); | |
399 | } | |
400 | } | |
401 | priv->event_log.num_wraps = num_wraps; | |
402 | priv->event_log.next_entry = next_entry; | |
403 | } | |
404 | ||
405 | /** | |
406 | * iwl_bg_ucode_trace - Timer callback to log ucode event | |
407 | * | |
408 | * The timer is continually set to execute every | |
409 | * UCODE_TRACE_PERIOD milliseconds after the last timer expired | |
410 | * this function is to perform continuous uCode event logging operation | |
411 | * if enabled | |
412 | */ | |
413 | static void iwl_bg_ucode_trace(unsigned long data) | |
414 | { | |
415 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
416 | ||
417 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
418 | return; | |
419 | ||
420 | if (priv->event_log.ucode_trace) { | |
421 | iwl_continuous_event_trace(priv); | |
422 | /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */ | |
423 | mod_timer(&priv->ucode_trace, | |
424 | jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD)); | |
425 | } | |
426 | } | |
427 | ||
65550636 WYG |
428 | static void iwl_bg_tx_flush(struct work_struct *work) |
429 | { | |
430 | struct iwl_priv *priv = | |
431 | container_of(work, struct iwl_priv, tx_flush); | |
432 | ||
433 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
434 | return; | |
435 | ||
436 | /* do nothing if rf-kill is on */ | |
437 | if (!iwl_is_ready_rf(priv)) | |
438 | return; | |
439 | ||
c68744fb WYG |
440 | IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n"); |
441 | iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL); | |
65550636 WYG |
442 | } |
443 | ||
b481de9c | 444 | /** |
a55360e4 | 445 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
446 | * |
447 | * Uses the priv->rx_handlers callback function array to invoke | |
448 | * the appropriate handlers, including command responses, | |
449 | * frame-received notifications, and other notifications. | |
450 | */ | |
f945f108 | 451 | static void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 452 | { |
a55360e4 | 453 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 454 | struct iwl_rx_packet *pkt; |
a55360e4 | 455 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
456 | u32 r, i; |
457 | int reclaim; | |
458 | unsigned long flags; | |
5c0eef96 | 459 | u8 fill_rx = 0; |
d68ab680 | 460 | u32 count = 8; |
4752c93c | 461 | int total_empty; |
b481de9c | 462 | |
6440adb5 CB |
463 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
464 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 465 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
466 | i = rxq->read; |
467 | ||
468 | /* Rx interrupt, but nothing sent from uCode */ | |
469 | if (i == r) | |
e1623446 | 470 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 471 | |
4752c93c | 472 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 473 | total_empty = r - rxq->write_actual; |
4752c93c MA |
474 | if (total_empty < 0) |
475 | total_empty += RX_QUEUE_SIZE; | |
476 | ||
477 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
478 | fill_rx = 1; |
479 | ||
b481de9c | 480 | while (i != r) { |
f4989d9b JB |
481 | int len; |
482 | ||
b481de9c ZY |
483 | rxb = rxq->queue[i]; |
484 | ||
9fbab516 | 485 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
486 | * then a bug has been introduced in the queue refilling |
487 | * routines -- catch it here */ | |
3e41ace5 JB |
488 | if (WARN_ON(rxb == NULL)) { |
489 | i = (i + 1) & RX_QUEUE_MASK; | |
490 | continue; | |
491 | } | |
b481de9c ZY |
492 | |
493 | rxq->queue[i] = NULL; | |
494 | ||
795414db | 495 | dma_unmap_page(priv->bus.dev, rxb->page_dma, |
2f301227 | 496 | PAGE_SIZE << priv->hw_params.rx_page_order, |
795414db | 497 | DMA_FROM_DEVICE); |
2f301227 | 498 | pkt = rxb_addr(rxb); |
b481de9c | 499 | |
f4989d9b JB |
500 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
501 | len += sizeof(u32); /* account for status word */ | |
502 | trace_iwlwifi_dev_rx(priv, pkt, len); | |
be1a71a1 | 503 | |
b481de9c ZY |
504 | /* Reclaim a command buffer only if this packet is a response |
505 | * to a (driver-originated) command. | |
506 | * If the packet (e.g. Rx frame) originated from uCode, | |
507 | * there is no command buffer to reclaim. | |
508 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
509 | * but apparently a few don't get set; catch them here. */ | |
510 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
511 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 512 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 513 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 514 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
515 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
516 | (pkt->hdr.cmd != REPLY_TX); | |
517 | ||
7194207c JB |
518 | /* |
519 | * Do the notification wait before RX handlers so | |
520 | * even if the RX handler consumes the RXB we have | |
521 | * access to it in the notification wait entry. | |
522 | */ | |
523 | if (!list_empty(&priv->_agn.notif_waits)) { | |
524 | struct iwl_notification_wait *w; | |
525 | ||
526 | spin_lock(&priv->_agn.notif_wait_lock); | |
527 | list_for_each_entry(w, &priv->_agn.notif_waits, list) { | |
528 | if (w->cmd == pkt->hdr.cmd) { | |
529 | w->triggered = true; | |
530 | if (w->fn) | |
09f18afe | 531 | w->fn(priv, pkt, w->fn_data); |
7194207c JB |
532 | } |
533 | } | |
534 | spin_unlock(&priv->_agn.notif_wait_lock); | |
535 | ||
536 | wake_up_all(&priv->_agn.notif_waitq); | |
537 | } | |
4613e72d CK |
538 | if (priv->pre_rx_handler) |
539 | priv->pre_rx_handler(priv, rxb); | |
7194207c | 540 | |
b481de9c ZY |
541 | /* Based on type of command response or notification, |
542 | * handle those that need handling via function in | |
5b9f8cd3 | 543 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 544 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 545 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 546 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
a83b9141 | 547 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 548 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
549 | } else { |
550 | /* No handling needed */ | |
e1623446 | 551 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
552 | "r %d i %d No handler needed for %s, 0x%02x\n", |
553 | r, i, get_cmd_string(pkt->hdr.cmd), | |
554 | pkt->hdr.cmd); | |
555 | } | |
556 | ||
29b1b268 ZY |
557 | /* |
558 | * XXX: After here, we should always check rxb->page | |
559 | * against NULL before touching it or its virtual | |
560 | * memory (pkt). Because some rx_handler might have | |
561 | * already taken or freed the pages. | |
562 | */ | |
563 | ||
b481de9c | 564 | if (reclaim) { |
2f301227 ZY |
565 | /* Invoke any callbacks, transfer the buffer to caller, |
566 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 567 | * as we reclaim the driver command queue */ |
29b1b268 | 568 | if (rxb->page) |
17b88929 | 569 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 570 | else |
39aadf8c | 571 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
572 | } |
573 | ||
7300515d ZY |
574 | /* Reuse the page if possible. For notification packets and |
575 | * SKBs that fail to Rx correctly, add them back into the | |
576 | * rx_free list for reuse later. */ | |
577 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 578 | if (rxb->page != NULL) { |
795414db | 579 | rxb->page_dma = dma_map_page(priv->bus.dev, rxb->page, |
7300515d | 580 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, |
795414db | 581 | DMA_FROM_DEVICE); |
7300515d ZY |
582 | list_add_tail(&rxb->list, &rxq->rx_free); |
583 | rxq->free_count++; | |
584 | } else | |
585 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 586 | |
b481de9c | 587 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 588 | |
b481de9c | 589 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
590 | /* If there are a lot of unused frames, |
591 | * restock the Rx queue so ucode wont assert. */ | |
592 | if (fill_rx) { | |
593 | count++; | |
594 | if (count >= 8) { | |
7300515d | 595 | rxq->read = i; |
54b81550 | 596 | iwlagn_rx_replenish_now(priv); |
5c0eef96 MA |
597 | count = 0; |
598 | } | |
599 | } | |
b481de9c ZY |
600 | } |
601 | ||
602 | /* Backtrack one entry */ | |
7300515d | 603 | rxq->read = i; |
4752c93c | 604 | if (fill_rx) |
54b81550 | 605 | iwlagn_rx_replenish_now(priv); |
4752c93c | 606 | else |
54b81550 | 607 | iwlagn_rx_queue_restock(priv); |
a55360e4 | 608 | } |
a55360e4 | 609 | |
ef850d7c MA |
610 | /* tasklet for iwlagn interrupt */ |
611 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
612 | { | |
613 | u32 inta = 0; | |
614 | u32 handled = 0; | |
615 | unsigned long flags; | |
8756990f | 616 | u32 i; |
ef850d7c MA |
617 | #ifdef CONFIG_IWLWIFI_DEBUG |
618 | u32 inta_mask; | |
619 | #endif | |
620 | ||
621 | spin_lock_irqsave(&priv->lock, flags); | |
622 | ||
623 | /* Ack/clear/reset pending uCode interrupts. | |
624 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
625 | */ | |
48a6be6a SZ |
626 | /* There is a hardware bug in the interrupt mask function that some |
627 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
628 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
629 | * ICT interrupt handling mechanism has another bug that might cause | |
630 | * these unmasked interrupts fail to be detected. We workaround the | |
631 | * hardware bugs here by ACKing all the possible interrupts so that | |
632 | * interrupt coalescing can still be achieved. | |
633 | */ | |
4a35ecf8 | 634 | iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask); |
ef850d7c | 635 | |
a4c8b2a6 | 636 | inta = priv->_agn.inta; |
ef850d7c MA |
637 | |
638 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 639 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
640 | /* just for debug */ |
641 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
642 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
643 | inta, inta_mask); | |
644 | } | |
645 | #endif | |
2f301227 ZY |
646 | |
647 | spin_unlock_irqrestore(&priv->lock, flags); | |
648 | ||
a4c8b2a6 JB |
649 | /* saved interrupt in inta variable now we can reset priv->_agn.inta */ |
650 | priv->_agn.inta = 0; | |
ef850d7c MA |
651 | |
652 | /* Now service all interrupt bits discovered above. */ | |
653 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 654 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
655 | |
656 | /* Tell the device to stop sending interrupts */ | |
657 | iwl_disable_interrupts(priv); | |
658 | ||
659 | priv->isr_stats.hw++; | |
660 | iwl_irq_handle_error(priv); | |
661 | ||
662 | handled |= CSR_INT_BIT_HW_ERR; | |
663 | ||
ef850d7c MA |
664 | return; |
665 | } | |
666 | ||
667 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 668 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
669 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
670 | if (inta & CSR_INT_BIT_SCD) { | |
671 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
672 | "the frame/frames.\n"); | |
673 | priv->isr_stats.sch++; | |
674 | } | |
675 | ||
676 | /* Alive notification via Rx interrupt will do the real work */ | |
677 | if (inta & CSR_INT_BIT_ALIVE) { | |
678 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
679 | priv->isr_stats.alive++; | |
680 | } | |
681 | } | |
682 | #endif | |
683 | /* Safely ignore these bits for debug checks below */ | |
684 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
685 | ||
686 | /* HW RF KILL switch toggled */ | |
687 | if (inta & CSR_INT_BIT_RF_KILL) { | |
688 | int hw_rf_kill = 0; | |
689 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
690 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
691 | hw_rf_kill = 1; | |
692 | ||
4c423a2b | 693 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
694 | hw_rf_kill ? "disable radio" : "enable radio"); |
695 | ||
696 | priv->isr_stats.rfkill++; | |
697 | ||
698 | /* driver only loads ucode once setting the interface up. | |
699 | * the driver allows loading the ucode even if the radio | |
700 | * is killed. Hence update the killswitch state here. The | |
701 | * rfkill handler will care about restarting if needed. | |
702 | */ | |
703 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
704 | if (hw_rf_kill) | |
705 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
706 | else | |
707 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 708 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
709 | } |
710 | ||
711 | handled |= CSR_INT_BIT_RF_KILL; | |
712 | } | |
713 | ||
714 | /* Chip got too hot and stopped itself */ | |
715 | if (inta & CSR_INT_BIT_CT_KILL) { | |
716 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
717 | priv->isr_stats.ctkill++; | |
718 | handled |= CSR_INT_BIT_CT_KILL; | |
719 | } | |
720 | ||
721 | /* Error detected by uCode */ | |
722 | if (inta & CSR_INT_BIT_SW_ERR) { | |
723 | IWL_ERR(priv, "Microcode SW error detected. " | |
724 | " Restarting 0x%X.\n", inta); | |
725 | priv->isr_stats.sw++; | |
ef850d7c MA |
726 | iwl_irq_handle_error(priv); |
727 | handled |= CSR_INT_BIT_SW_ERR; | |
728 | } | |
729 | ||
730 | /* uCode wakes up after power-down sleep */ | |
731 | if (inta & CSR_INT_BIT_WAKEUP) { | |
732 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
733 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
8756990f BC |
734 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
735 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
ef850d7c MA |
736 | |
737 | priv->isr_stats.wakeup++; | |
738 | ||
739 | handled |= CSR_INT_BIT_WAKEUP; | |
740 | } | |
741 | ||
742 | /* All uCode command responses, including Tx command responses, | |
743 | * Rx "responses" (frame-received notification), and other | |
744 | * notifications from uCode come through here*/ | |
40cefda9 MA |
745 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
746 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 747 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
748 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
749 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
750 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
f7d046f9 | 751 | CSR_FH_INT_RX_MASK); |
40cefda9 MA |
752 | } |
753 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
754 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
755 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
756 | } | |
757 | /* Sending RX interrupt require many steps to be done in the | |
758 | * the device: | |
759 | * 1- write interrupt to current index in ICT table. | |
760 | * 2- dma RX frame. | |
761 | * 3- update RX shared data to indicate last write index. | |
762 | * 4- send interrupt. | |
763 | * This could lead to RX race, driver could receive RX interrupt | |
74ba67ed BC |
764 | * but the shared data changes does not reflect this; |
765 | * periodic interrupt will detect any dangling Rx activity. | |
40cefda9 | 766 | */ |
74ba67ed BC |
767 | |
768 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
769 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
40cefda9 | 770 | CSR_INT_PERIODIC_DIS); |
ef850d7c | 771 | iwl_rx_handle(priv); |
74ba67ed BC |
772 | |
773 | /* | |
774 | * Enable periodic interrupt in 8 msec only if we received | |
775 | * real RX interrupt (instead of just periodic int), to catch | |
776 | * any dangling Rx interrupt. If it was just the periodic | |
777 | * interrupt, there was no dangling Rx activity, and no need | |
778 | * to extend the periodic interrupt; one-shot is enough. | |
779 | */ | |
40cefda9 | 780 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) |
74ba67ed | 781 | iwl_write8(priv, CSR_INT_PERIODIC_REG, |
40cefda9 MA |
782 | CSR_INT_PERIODIC_ENA); |
783 | ||
ef850d7c | 784 | priv->isr_stats.rx++; |
ef850d7c MA |
785 | } |
786 | ||
c72cd19f | 787 | /* This "Tx" DMA channel is used only for loading uCode */ |
ef850d7c | 788 | if (inta & CSR_INT_BIT_FH_TX) { |
f7d046f9 | 789 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
c72cd19f | 790 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
ef850d7c MA |
791 | priv->isr_stats.tx++; |
792 | handled |= CSR_INT_BIT_FH_TX; | |
c72cd19f | 793 | /* Wake up uCode load routine, now that load is complete */ |
ef850d7c MA |
794 | priv->ucode_write_complete = 1; |
795 | wake_up_interruptible(&priv->wait_command_queue); | |
796 | } | |
797 | ||
798 | if (inta & ~handled) { | |
799 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
800 | priv->isr_stats.unhandled++; | |
801 | } | |
802 | ||
40cefda9 | 803 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 804 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 805 | inta & ~priv->inta_mask); |
ef850d7c MA |
806 | } |
807 | ||
ef850d7c | 808 | /* Re-enable all interrupts */ |
62e45c14 | 809 | /* only Re-enable if disabled by irq */ |
ef850d7c MA |
810 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) |
811 | iwl_enable_interrupts(priv); | |
3dd823e6 DF |
812 | /* Re-enable RF_KILL if it occurred */ |
813 | else if (handled & CSR_INT_BIT_RF_KILL) | |
814 | iwl_enable_rfkill_int(priv); | |
ef850d7c MA |
815 | } |
816 | ||
7d47618a EG |
817 | /***************************************************************************** |
818 | * | |
819 | * sysfs attributes | |
820 | * | |
821 | *****************************************************************************/ | |
822 | ||
823 | #ifdef CONFIG_IWLWIFI_DEBUG | |
824 | ||
825 | /* | |
826 | * The following adds a new attribute to the sysfs representation | |
827 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) | |
828 | * used for controlling the debug level. | |
829 | * | |
830 | * See the level definitions in iwl for details. | |
831 | * | |
832 | * The debug_level being managed using sysfs below is a per device debug | |
833 | * level that is used instead of the global debug level if it (the per | |
834 | * device debug level) is set. | |
835 | */ | |
836 | static ssize_t show_debug_level(struct device *d, | |
837 | struct device_attribute *attr, char *buf) | |
838 | { | |
839 | struct iwl_priv *priv = dev_get_drvdata(d); | |
840 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
841 | } | |
842 | static ssize_t store_debug_level(struct device *d, | |
843 | struct device_attribute *attr, | |
844 | const char *buf, size_t count) | |
845 | { | |
846 | struct iwl_priv *priv = dev_get_drvdata(d); | |
847 | unsigned long val; | |
848 | int ret; | |
849 | ||
850 | ret = strict_strtoul(buf, 0, &val); | |
851 | if (ret) | |
852 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); | |
853 | else { | |
854 | priv->debug_level = val; | |
855 | if (iwl_alloc_traffic_mem(priv)) | |
856 | IWL_ERR(priv, | |
857 | "Not enough memory to generate traffic log\n"); | |
858 | } | |
859 | return strnlen(buf, count); | |
860 | } | |
861 | ||
862 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
863 | show_debug_level, store_debug_level); | |
864 | ||
865 | ||
866 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
867 | ||
868 | ||
869 | static ssize_t show_temperature(struct device *d, | |
870 | struct device_attribute *attr, char *buf) | |
871 | { | |
872 | struct iwl_priv *priv = dev_get_drvdata(d); | |
873 | ||
874 | if (!iwl_is_alive(priv)) | |
875 | return -EAGAIN; | |
876 | ||
877 | return sprintf(buf, "%d\n", priv->temperature); | |
878 | } | |
879 | ||
880 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
881 | ||
882 | static ssize_t show_tx_power(struct device *d, | |
883 | struct device_attribute *attr, char *buf) | |
884 | { | |
885 | struct iwl_priv *priv = dev_get_drvdata(d); | |
886 | ||
887 | if (!iwl_is_ready_rf(priv)) | |
888 | return sprintf(buf, "off\n"); | |
889 | else | |
890 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
891 | } | |
892 | ||
893 | static ssize_t store_tx_power(struct device *d, | |
894 | struct device_attribute *attr, | |
895 | const char *buf, size_t count) | |
896 | { | |
897 | struct iwl_priv *priv = dev_get_drvdata(d); | |
898 | unsigned long val; | |
899 | int ret; | |
900 | ||
901 | ret = strict_strtoul(buf, 10, &val); | |
902 | if (ret) | |
903 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); | |
904 | else { | |
905 | ret = iwl_set_tx_power(priv, val, false); | |
906 | if (ret) | |
907 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
908 | ret); | |
909 | else | |
910 | ret = count; | |
911 | } | |
912 | return ret; | |
913 | } | |
914 | ||
915 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
916 | ||
7d47618a EG |
917 | static struct attribute *iwl_sysfs_entries[] = { |
918 | &dev_attr_temperature.attr, | |
919 | &dev_attr_tx_power.attr, | |
7d47618a EG |
920 | #ifdef CONFIG_IWLWIFI_DEBUG |
921 | &dev_attr_debug_level.attr, | |
922 | #endif | |
923 | NULL | |
924 | }; | |
925 | ||
926 | static struct attribute_group iwl_attribute_group = { | |
927 | .name = NULL, /* put in device directory */ | |
928 | .attrs = iwl_sysfs_entries, | |
929 | }; | |
930 | ||
b481de9c ZY |
931 | /****************************************************************************** |
932 | * | |
933 | * uCode download functions | |
934 | * | |
935 | ******************************************************************************/ | |
936 | ||
3599d39a | 937 | static void iwl_free_fw_desc(struct iwl_priv *priv, struct fw_desc *desc) |
dbf28e21 JB |
938 | { |
939 | if (desc->v_addr) | |
3599d39a | 940 | dma_free_coherent(priv->bus.dev, desc->len, |
dbf28e21 JB |
941 | desc->v_addr, desc->p_addr); |
942 | desc->v_addr = NULL; | |
943 | desc->len = 0; | |
944 | } | |
945 | ||
3599d39a | 946 | static void iwl_free_fw_img(struct iwl_priv *priv, struct fw_img *img) |
dbf28e21 | 947 | { |
3599d39a EG |
948 | iwl_free_fw_desc(priv, &img->code); |
949 | iwl_free_fw_desc(priv, &img->data); | |
dbf28e21 JB |
950 | } |
951 | ||
3599d39a EG |
952 | static void iwl_dealloc_ucode(struct iwl_priv *priv) |
953 | { | |
954 | iwl_free_fw_img(priv, &priv->ucode_rt); | |
955 | iwl_free_fw_img(priv, &priv->ucode_init); | |
956 | } | |
957 | ||
958 | static int iwl_alloc_fw_desc(struct iwl_priv *priv, struct fw_desc *desc, | |
dbf28e21 JB |
959 | const void *data, size_t len) |
960 | { | |
961 | if (!len) { | |
962 | desc->v_addr = NULL; | |
963 | return -EINVAL; | |
964 | } | |
965 | ||
3599d39a | 966 | desc->v_addr = dma_alloc_coherent(priv->bus.dev, len, |
dbf28e21 JB |
967 | &desc->p_addr, GFP_KERNEL); |
968 | if (!desc->v_addr) | |
969 | return -ENOMEM; | |
3599d39a | 970 | |
dbf28e21 JB |
971 | desc->len = len; |
972 | memcpy(desc->v_addr, data, len); | |
973 | return 0; | |
974 | } | |
975 | ||
dd7a2509 JB |
976 | struct iwlagn_ucode_capabilities { |
977 | u32 max_probe_length; | |
6a822d06 | 978 | u32 standard_phy_calibration_size; |
3997ff39 | 979 | u32 flags; |
dd7a2509 | 980 | }; |
edcdf8b2 | 981 | |
b08dfd04 | 982 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
dd7a2509 JB |
983 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
984 | struct iwlagn_ucode_capabilities *capa); | |
b08dfd04 | 985 | |
39396085 JS |
986 | #define UCODE_EXPERIMENTAL_INDEX 100 |
987 | #define UCODE_EXPERIMENTAL_TAG "exp" | |
988 | ||
b08dfd04 JB |
989 | static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) |
990 | { | |
991 | const char *name_pre = priv->cfg->fw_name_pre; | |
39396085 | 992 | char tag[8]; |
b08dfd04 | 993 | |
39396085 JS |
994 | if (first) { |
995 | #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE | |
996 | priv->fw_index = UCODE_EXPERIMENTAL_INDEX; | |
997 | strcpy(tag, UCODE_EXPERIMENTAL_TAG); | |
998 | } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) { | |
999 | #endif | |
b08dfd04 | 1000 | priv->fw_index = priv->cfg->ucode_api_max; |
39396085 JS |
1001 | sprintf(tag, "%d", priv->fw_index); |
1002 | } else { | |
b08dfd04 | 1003 | priv->fw_index--; |
39396085 JS |
1004 | sprintf(tag, "%d", priv->fw_index); |
1005 | } | |
b08dfd04 JB |
1006 | |
1007 | if (priv->fw_index < priv->cfg->ucode_api_min) { | |
1008 | IWL_ERR(priv, "no suitable firmware found!\n"); | |
1009 | return -ENOENT; | |
1010 | } | |
1011 | ||
39396085 | 1012 | sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); |
b08dfd04 | 1013 | |
39396085 JS |
1014 | IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n", |
1015 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
1016 | ? "EXPERIMENTAL " : "", | |
b08dfd04 JB |
1017 | priv->firmware_name); |
1018 | ||
1019 | return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, | |
3599d39a EG |
1020 | priv->bus.dev, |
1021 | GFP_KERNEL, priv, iwl_ucode_callback); | |
b08dfd04 JB |
1022 | } |
1023 | ||
0e9a44dc | 1024 | struct iwlagn_firmware_pieces { |
1fc35276 JB |
1025 | const void *inst, *data, *init, *init_data; |
1026 | size_t inst_size, data_size, init_size, init_data_size; | |
0e9a44dc JB |
1027 | |
1028 | u32 build; | |
b2e640d4 JB |
1029 | |
1030 | u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; | |
1031 | u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; | |
0e9a44dc JB |
1032 | }; |
1033 | ||
1034 | static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |
1035 | const struct firmware *ucode_raw, | |
1036 | struct iwlagn_firmware_pieces *pieces) | |
1037 | { | |
1038 | struct iwl_ucode_header *ucode = (void *)ucode_raw->data; | |
1039 | u32 api_ver, hdr_size; | |
1040 | const u8 *src; | |
1041 | ||
1042 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1043 | api_ver = IWL_UCODE_API(priv->ucode_ver); | |
1044 | ||
1045 | switch (api_ver) { | |
1046 | default: | |
f7d046f9 WYG |
1047 | hdr_size = 28; |
1048 | if (ucode_raw->size < hdr_size) { | |
1049 | IWL_ERR(priv, "File size too small!\n"); | |
1050 | return -EINVAL; | |
0e9a44dc | 1051 | } |
f7d046f9 WYG |
1052 | pieces->build = le32_to_cpu(ucode->u.v2.build); |
1053 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | |
1054 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | |
1055 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | |
1056 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | |
f7d046f9 WYG |
1057 | src = ucode->u.v2.data; |
1058 | break; | |
0e9a44dc JB |
1059 | case 0: |
1060 | case 1: | |
1061 | case 2: | |
1062 | hdr_size = 24; | |
1063 | if (ucode_raw->size < hdr_size) { | |
1064 | IWL_ERR(priv, "File size too small!\n"); | |
1065 | return -EINVAL; | |
1066 | } | |
1067 | pieces->build = 0; | |
1068 | pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size); | |
1069 | pieces->data_size = le32_to_cpu(ucode->u.v1.data_size); | |
1070 | pieces->init_size = le32_to_cpu(ucode->u.v1.init_size); | |
1071 | pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size); | |
0e9a44dc JB |
1072 | src = ucode->u.v1.data; |
1073 | break; | |
1074 | } | |
1075 | ||
1076 | /* Verify size of file vs. image size info in file's header */ | |
1077 | if (ucode_raw->size != hdr_size + pieces->inst_size + | |
1078 | pieces->data_size + pieces->init_size + | |
1fc35276 | 1079 | pieces->init_data_size) { |
0e9a44dc JB |
1080 | |
1081 | IWL_ERR(priv, | |
1082 | "uCode file size %d does not match expected size\n", | |
1083 | (int)ucode_raw->size); | |
1084 | return -EINVAL; | |
1085 | } | |
1086 | ||
1087 | pieces->inst = src; | |
1088 | src += pieces->inst_size; | |
1089 | pieces->data = src; | |
1090 | src += pieces->data_size; | |
1091 | pieces->init = src; | |
1092 | src += pieces->init_size; | |
1093 | pieces->init_data = src; | |
1094 | src += pieces->init_data_size; | |
0e9a44dc JB |
1095 | |
1096 | return 0; | |
1097 | } | |
1098 | ||
dd7a2509 JB |
1099 | static int iwlagn_wanted_ucode_alternative = 1; |
1100 | ||
1101 | static int iwlagn_load_firmware(struct iwl_priv *priv, | |
1102 | const struct firmware *ucode_raw, | |
1103 | struct iwlagn_firmware_pieces *pieces, | |
1104 | struct iwlagn_ucode_capabilities *capa) | |
1105 | { | |
1106 | struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data; | |
1107 | struct iwl_ucode_tlv *tlv; | |
1108 | size_t len = ucode_raw->size; | |
1109 | const u8 *data; | |
1110 | int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp; | |
1111 | u64 alternatives; | |
ad8d8333 WYG |
1112 | u32 tlv_len; |
1113 | enum iwl_ucode_tlv_type tlv_type; | |
1114 | const u8 *tlv_data; | |
dd7a2509 | 1115 | |
ad8d8333 WYG |
1116 | if (len < sizeof(*ucode)) { |
1117 | IWL_ERR(priv, "uCode has invalid length: %zd\n", len); | |
dd7a2509 | 1118 | return -EINVAL; |
ad8d8333 | 1119 | } |
dd7a2509 | 1120 | |
ad8d8333 WYG |
1121 | if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) { |
1122 | IWL_ERR(priv, "invalid uCode magic: 0X%x\n", | |
1123 | le32_to_cpu(ucode->magic)); | |
dd7a2509 | 1124 | return -EINVAL; |
ad8d8333 | 1125 | } |
dd7a2509 JB |
1126 | |
1127 | /* | |
1128 | * Check which alternatives are present, and "downgrade" | |
1129 | * when the chosen alternative is not present, warning | |
1130 | * the user when that happens. Some files may not have | |
1131 | * any alternatives, so don't warn in that case. | |
1132 | */ | |
1133 | alternatives = le64_to_cpu(ucode->alternatives); | |
1134 | tmp = wanted_alternative; | |
1135 | if (wanted_alternative > 63) | |
1136 | wanted_alternative = 63; | |
1137 | while (wanted_alternative && !(alternatives & BIT(wanted_alternative))) | |
1138 | wanted_alternative--; | |
1139 | if (wanted_alternative && wanted_alternative != tmp) | |
1140 | IWL_WARN(priv, | |
1141 | "uCode alternative %d not available, choosing %d\n", | |
1142 | tmp, wanted_alternative); | |
1143 | ||
1144 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1145 | pieces->build = le32_to_cpu(ucode->build); | |
1146 | data = ucode->data; | |
1147 | ||
1148 | len -= sizeof(*ucode); | |
1149 | ||
704da534 | 1150 | while (len >= sizeof(*tlv)) { |
dd7a2509 | 1151 | u16 tlv_alt; |
dd7a2509 JB |
1152 | |
1153 | len -= sizeof(*tlv); | |
1154 | tlv = (void *)data; | |
1155 | ||
1156 | tlv_len = le32_to_cpu(tlv->length); | |
1157 | tlv_type = le16_to_cpu(tlv->type); | |
1158 | tlv_alt = le16_to_cpu(tlv->alternative); | |
1159 | tlv_data = tlv->data; | |
1160 | ||
ad8d8333 WYG |
1161 | if (len < tlv_len) { |
1162 | IWL_ERR(priv, "invalid TLV len: %zd/%u\n", | |
1163 | len, tlv_len); | |
dd7a2509 | 1164 | return -EINVAL; |
ad8d8333 | 1165 | } |
dd7a2509 JB |
1166 | len -= ALIGN(tlv_len, 4); |
1167 | data += sizeof(*tlv) + ALIGN(tlv_len, 4); | |
1168 | ||
1169 | /* | |
1170 | * Alternative 0 is always valid. | |
1171 | * | |
1172 | * Skip alternative TLVs that are not selected. | |
1173 | */ | |
1174 | if (tlv_alt != 0 && tlv_alt != wanted_alternative) | |
1175 | continue; | |
1176 | ||
1177 | switch (tlv_type) { | |
1178 | case IWL_UCODE_TLV_INST: | |
1179 | pieces->inst = tlv_data; | |
1180 | pieces->inst_size = tlv_len; | |
1181 | break; | |
1182 | case IWL_UCODE_TLV_DATA: | |
1183 | pieces->data = tlv_data; | |
1184 | pieces->data_size = tlv_len; | |
1185 | break; | |
1186 | case IWL_UCODE_TLV_INIT: | |
1187 | pieces->init = tlv_data; | |
1188 | pieces->init_size = tlv_len; | |
1189 | break; | |
1190 | case IWL_UCODE_TLV_INIT_DATA: | |
1191 | pieces->init_data = tlv_data; | |
1192 | pieces->init_data_size = tlv_len; | |
1193 | break; | |
1194 | case IWL_UCODE_TLV_BOOT: | |
1fc35276 | 1195 | IWL_ERR(priv, "Found unexpected BOOT ucode\n"); |
dd7a2509 JB |
1196 | break; |
1197 | case IWL_UCODE_TLV_PROBE_MAX_LEN: | |
704da534 JB |
1198 | if (tlv_len != sizeof(u32)) |
1199 | goto invalid_tlv_len; | |
1200 | capa->max_probe_length = | |
ad8d8333 | 1201 | le32_to_cpup((__le32 *)tlv_data); |
dd7a2509 | 1202 | break; |
ece9c4ee JB |
1203 | case IWL_UCODE_TLV_PAN: |
1204 | if (tlv_len) | |
1205 | goto invalid_tlv_len; | |
3997ff39 JB |
1206 | capa->flags |= IWL_UCODE_TLV_FLAGS_PAN; |
1207 | break; | |
1208 | case IWL_UCODE_TLV_FLAGS: | |
1209 | /* must be at least one u32 */ | |
1210 | if (tlv_len < sizeof(u32)) | |
1211 | goto invalid_tlv_len; | |
1212 | /* and a proper number of u32s */ | |
1213 | if (tlv_len % sizeof(u32)) | |
1214 | goto invalid_tlv_len; | |
1215 | /* | |
1216 | * This driver only reads the first u32 as | |
1217 | * right now no more features are defined, | |
1218 | * if that changes then either the driver | |
1219 | * will not work with the new firmware, or | |
1220 | * it'll not take advantage of new features. | |
1221 | */ | |
1222 | capa->flags = le32_to_cpup((__le32 *)tlv_data); | |
ece9c4ee | 1223 | break; |
b2e640d4 | 1224 | case IWL_UCODE_TLV_INIT_EVTLOG_PTR: |
704da534 JB |
1225 | if (tlv_len != sizeof(u32)) |
1226 | goto invalid_tlv_len; | |
1227 | pieces->init_evtlog_ptr = | |
ad8d8333 | 1228 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1229 | break; |
1230 | case IWL_UCODE_TLV_INIT_EVTLOG_SIZE: | |
704da534 JB |
1231 | if (tlv_len != sizeof(u32)) |
1232 | goto invalid_tlv_len; | |
1233 | pieces->init_evtlog_size = | |
ad8d8333 | 1234 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1235 | break; |
1236 | case IWL_UCODE_TLV_INIT_ERRLOG_PTR: | |
704da534 JB |
1237 | if (tlv_len != sizeof(u32)) |
1238 | goto invalid_tlv_len; | |
1239 | pieces->init_errlog_ptr = | |
ad8d8333 | 1240 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1241 | break; |
1242 | case IWL_UCODE_TLV_RUNT_EVTLOG_PTR: | |
704da534 JB |
1243 | if (tlv_len != sizeof(u32)) |
1244 | goto invalid_tlv_len; | |
1245 | pieces->inst_evtlog_ptr = | |
ad8d8333 | 1246 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1247 | break; |
1248 | case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE: | |
704da534 JB |
1249 | if (tlv_len != sizeof(u32)) |
1250 | goto invalid_tlv_len; | |
1251 | pieces->inst_evtlog_size = | |
ad8d8333 | 1252 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1253 | break; |
1254 | case IWL_UCODE_TLV_RUNT_ERRLOG_PTR: | |
704da534 JB |
1255 | if (tlv_len != sizeof(u32)) |
1256 | goto invalid_tlv_len; | |
1257 | pieces->inst_errlog_ptr = | |
ad8d8333 | 1258 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 | 1259 | break; |
c8312fac WYG |
1260 | case IWL_UCODE_TLV_ENHANCE_SENS_TBL: |
1261 | if (tlv_len) | |
704da534 JB |
1262 | goto invalid_tlv_len; |
1263 | priv->enhance_sensitivity_table = true; | |
c8312fac | 1264 | break; |
6a822d06 | 1265 | case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE: |
704da534 JB |
1266 | if (tlv_len != sizeof(u32)) |
1267 | goto invalid_tlv_len; | |
1268 | capa->standard_phy_calibration_size = | |
6a822d06 WYG |
1269 | le32_to_cpup((__le32 *)tlv_data); |
1270 | break; | |
dd7a2509 | 1271 | default: |
6fc3ba99 | 1272 | IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type); |
dd7a2509 JB |
1273 | break; |
1274 | } | |
1275 | } | |
1276 | ||
ad8d8333 WYG |
1277 | if (len) { |
1278 | IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len); | |
1279 | iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len); | |
704da534 | 1280 | return -EINVAL; |
ad8d8333 | 1281 | } |
dd7a2509 | 1282 | |
704da534 JB |
1283 | return 0; |
1284 | ||
1285 | invalid_tlv_len: | |
1286 | IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len); | |
1287 | iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len); | |
1288 | ||
1289 | return -EINVAL; | |
dd7a2509 JB |
1290 | } |
1291 | ||
b481de9c | 1292 | /** |
b08dfd04 | 1293 | * iwl_ucode_callback - callback when firmware was loaded |
b481de9c | 1294 | * |
b08dfd04 JB |
1295 | * If loaded successfully, copies the firmware into buffers |
1296 | * for the card to fetch (via DMA). | |
b481de9c | 1297 | */ |
b08dfd04 | 1298 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) |
b481de9c | 1299 | { |
b08dfd04 | 1300 | struct iwl_priv *priv = context; |
cc0f555d | 1301 | struct iwl_ucode_header *ucode; |
0e9a44dc JB |
1302 | int err; |
1303 | struct iwlagn_firmware_pieces pieces; | |
a0987a8d RC |
1304 | const unsigned int api_max = priv->cfg->ucode_api_max; |
1305 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
0e9a44dc | 1306 | u32 api_ver; |
3e4de761 | 1307 | char buildstr[25]; |
0e9a44dc | 1308 | u32 build; |
dd7a2509 JB |
1309 | struct iwlagn_ucode_capabilities ucode_capa = { |
1310 | .max_probe_length = 200, | |
6a822d06 | 1311 | .standard_phy_calibration_size = |
642454cc | 1312 | IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE, |
dd7a2509 | 1313 | }; |
0e9a44dc JB |
1314 | |
1315 | memset(&pieces, 0, sizeof(pieces)); | |
b481de9c | 1316 | |
b08dfd04 | 1317 | if (!ucode_raw) { |
39396085 JS |
1318 | if (priv->fw_index <= priv->cfg->ucode_api_max) |
1319 | IWL_ERR(priv, | |
1320 | "request for firmware file '%s' failed.\n", | |
1321 | priv->firmware_name); | |
b08dfd04 | 1322 | goto try_again; |
b481de9c ZY |
1323 | } |
1324 | ||
b08dfd04 JB |
1325 | IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", |
1326 | priv->firmware_name, ucode_raw->size); | |
b481de9c | 1327 | |
22adba2a JB |
1328 | /* Make sure that we got at least the API version number */ |
1329 | if (ucode_raw->size < 4) { | |
15b1687c | 1330 | IWL_ERR(priv, "File size way too small!\n"); |
b08dfd04 | 1331 | goto try_again; |
b481de9c ZY |
1332 | } |
1333 | ||
1334 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1335 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1336 | |
0e9a44dc JB |
1337 | if (ucode->ver) |
1338 | err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces); | |
1339 | else | |
dd7a2509 JB |
1340 | err = iwlagn_load_firmware(priv, ucode_raw, &pieces, |
1341 | &ucode_capa); | |
22adba2a | 1342 | |
0e9a44dc JB |
1343 | if (err) |
1344 | goto try_again; | |
b481de9c | 1345 | |
a0987a8d | 1346 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
0e9a44dc | 1347 | build = pieces.build; |
a0987a8d | 1348 | |
0e9a44dc JB |
1349 | /* |
1350 | * api_ver should match the api version forming part of the | |
1351 | * firmware filename ... but we don't check for that and only rely | |
1352 | * on the API version read from firmware header from here on forward | |
1353 | */ | |
65cccfb0 WYG |
1354 | /* no api version check required for experimental uCode */ |
1355 | if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) { | |
1356 | if (api_ver < api_min || api_ver > api_max) { | |
1357 | IWL_ERR(priv, | |
1358 | "Driver unable to support your firmware API. " | |
1359 | "Driver supports v%u, firmware is v%u.\n", | |
1360 | api_max, api_ver); | |
1361 | goto try_again; | |
1362 | } | |
b08dfd04 | 1363 | |
65cccfb0 WYG |
1364 | if (api_ver != api_max) |
1365 | IWL_ERR(priv, | |
1366 | "Firmware has old API version. Expected v%u, " | |
1367 | "got v%u. New firmware can be obtained " | |
1368 | "from http://www.intellinuxwireless.org.\n", | |
1369 | api_max, api_ver); | |
1370 | } | |
a0987a8d | 1371 | |
3e4de761 | 1372 | if (build) |
39396085 JS |
1373 | sprintf(buildstr, " build %u%s", build, |
1374 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
1375 | ? " (EXP)" : ""); | |
3e4de761 JB |
1376 | else |
1377 | buildstr[0] = '\0'; | |
1378 | ||
1379 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n", | |
1380 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1381 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1382 | IWL_UCODE_API(priv->ucode_ver), | |
1383 | IWL_UCODE_SERIAL(priv->ucode_ver), | |
1384 | buildstr); | |
a0987a8d | 1385 | |
5ebeb5a6 RC |
1386 | snprintf(priv->hw->wiphy->fw_version, |
1387 | sizeof(priv->hw->wiphy->fw_version), | |
3e4de761 | 1388 | "%u.%u.%u.%u%s", |
5ebeb5a6 RC |
1389 | IWL_UCODE_MAJOR(priv->ucode_ver), |
1390 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1391 | IWL_UCODE_API(priv->ucode_ver), | |
3e4de761 JB |
1392 | IWL_UCODE_SERIAL(priv->ucode_ver), |
1393 | buildstr); | |
b481de9c | 1394 | |
b08dfd04 JB |
1395 | /* |
1396 | * For any of the failures below (before allocating pci memory) | |
1397 | * we will try to load a version with a smaller API -- maybe the | |
1398 | * user just got a corrupted version of the latest API. | |
1399 | */ | |
1400 | ||
0e9a44dc JB |
1401 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
1402 | priv->ucode_ver); | |
1403 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n", | |
1404 | pieces.inst_size); | |
1405 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n", | |
1406 | pieces.data_size); | |
1407 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n", | |
1408 | pieces.init_size); | |
1409 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n", | |
1410 | pieces.init_data_size); | |
b481de9c ZY |
1411 | |
1412 | /* Verify that uCode images will fit in card's SRAM */ | |
0e9a44dc JB |
1413 | if (pieces.inst_size > priv->hw_params.max_inst_size) { |
1414 | IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n", | |
1415 | pieces.inst_size); | |
b08dfd04 | 1416 | goto try_again; |
b481de9c ZY |
1417 | } |
1418 | ||
0e9a44dc JB |
1419 | if (pieces.data_size > priv->hw_params.max_data_size) { |
1420 | IWL_ERR(priv, "uCode data len %Zd too large to fit in\n", | |
1421 | pieces.data_size); | |
b08dfd04 | 1422 | goto try_again; |
b481de9c | 1423 | } |
0e9a44dc JB |
1424 | |
1425 | if (pieces.init_size > priv->hw_params.max_inst_size) { | |
1426 | IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n", | |
1427 | pieces.init_size); | |
b08dfd04 | 1428 | goto try_again; |
b481de9c | 1429 | } |
0e9a44dc JB |
1430 | |
1431 | if (pieces.init_data_size > priv->hw_params.max_data_size) { | |
1432 | IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n", | |
1433 | pieces.init_data_size); | |
b08dfd04 | 1434 | goto try_again; |
b481de9c | 1435 | } |
0e9a44dc | 1436 | |
b481de9c ZY |
1437 | /* Allocate ucode buffers for card's bus-master loading ... */ |
1438 | ||
1439 | /* Runtime instructions and 2 copies of data: | |
1440 | * 1) unmodified from disk | |
1441 | * 2) backup cache for save/restore during power-downs */ | |
3599d39a | 1442 | if (iwl_alloc_fw_desc(priv, &priv->ucode_rt.code, |
dbf28e21 JB |
1443 | pieces.inst, pieces.inst_size)) |
1444 | goto err_pci_alloc; | |
3599d39a | 1445 | if (iwl_alloc_fw_desc(priv, &priv->ucode_rt.data, |
dbf28e21 | 1446 | pieces.data, pieces.data_size)) |
1f304e4e ZY |
1447 | goto err_pci_alloc; |
1448 | ||
b481de9c | 1449 | /* Initialization instructions and data */ |
0e9a44dc | 1450 | if (pieces.init_size && pieces.init_data_size) { |
3599d39a | 1451 | if (iwl_alloc_fw_desc(priv, &priv->ucode_init.code, |
dbf28e21 JB |
1452 | pieces.init, pieces.init_size)) |
1453 | goto err_pci_alloc; | |
3599d39a | 1454 | if (iwl_alloc_fw_desc(priv, &priv->ucode_init.data, |
dbf28e21 | 1455 | pieces.init_data, pieces.init_data_size)) |
90e759d1 TW |
1456 | goto err_pci_alloc; |
1457 | } | |
b481de9c | 1458 | |
b2e640d4 JB |
1459 | /* Now that we can no longer fail, copy information */ |
1460 | ||
1461 | /* | |
1462 | * The (size - 16) / 12 formula is based on the information recorded | |
1463 | * for each event, which is of mode 1 (including timestamp) for all | |
1464 | * new microcodes that include this information. | |
1465 | */ | |
1466 | priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr; | |
1467 | if (pieces.init_evtlog_size) | |
1468 | priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12; | |
1469 | else | |
7cb1b088 WYG |
1470 | priv->_agn.init_evtlog_size = |
1471 | priv->cfg->base_params->max_event_log_size; | |
b2e640d4 JB |
1472 | priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr; |
1473 | priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr; | |
1474 | if (pieces.inst_evtlog_size) | |
1475 | priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12; | |
1476 | else | |
7cb1b088 WYG |
1477 | priv->_agn.inst_evtlog_size = |
1478 | priv->cfg->base_params->max_event_log_size; | |
b2e640d4 JB |
1479 | priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; |
1480 | ||
d2690c0d JB |
1481 | priv->new_scan_threshold_behaviour = |
1482 | !!(ucode_capa.flags & IWL_UCODE_TLV_FLAGS_NEWSCAN); | |
1483 | ||
b2ea345e WYG |
1484 | if ((priv->cfg->sku & EEPROM_SKU_CAP_IPAN_ENABLE) && |
1485 | (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN)) { | |
ece9c4ee | 1486 | priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN); |
c10afb6e | 1487 | priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN; |
ece9c4ee JB |
1488 | } else |
1489 | priv->sta_key_max_num = STA_KEY_MAX_NUM; | |
c10afb6e | 1490 | |
17445b8c JB |
1491 | if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
1492 | priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM; | |
1493 | else | |
1494 | priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM; | |
1495 | ||
6a822d06 WYG |
1496 | /* |
1497 | * figure out the offset of chain noise reset and gain commands | |
1498 | * base on the size of standard phy calibration commands table size | |
1499 | */ | |
1500 | if (ucode_capa.standard_phy_calibration_size > | |
1501 | IWL_MAX_PHY_CALIBRATE_TBL_SIZE) | |
1502 | ucode_capa.standard_phy_calibration_size = | |
1503 | IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE; | |
1504 | ||
1505 | priv->_agn.phy_calib_chain_noise_reset_cmd = | |
1506 | ucode_capa.standard_phy_calibration_size; | |
1507 | priv->_agn.phy_calib_chain_noise_gain_cmd = | |
1508 | ucode_capa.standard_phy_calibration_size + 1; | |
1509 | ||
b08dfd04 JB |
1510 | /************************************************** |
1511 | * This is still part of probe() in a sense... | |
1512 | * | |
1513 | * 9. Setup and register with mac80211 and debugfs | |
1514 | **************************************************/ | |
dd7a2509 | 1515 | err = iwl_mac_setup_register(priv, &ucode_capa); |
b08dfd04 JB |
1516 | if (err) |
1517 | goto out_unbind; | |
1518 | ||
1519 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
1520 | if (err) | |
1521 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
1522 | ||
3599d39a | 1523 | err = sysfs_create_group(&(priv->bus.dev->kobj), |
7d47618a EG |
1524 | &iwl_attribute_group); |
1525 | if (err) { | |
1526 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); | |
1527 | goto out_unbind; | |
1528 | } | |
1529 | ||
b481de9c ZY |
1530 | /* We have our copies now, allow OS release its copies */ |
1531 | release_firmware(ucode_raw); | |
a15707d8 | 1532 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 JB |
1533 | return; |
1534 | ||
1535 | try_again: | |
1536 | /* try next, if any */ | |
1537 | if (iwl_request_firmware(priv, false)) | |
1538 | goto out_unbind; | |
1539 | release_firmware(ucode_raw); | |
1540 | return; | |
b481de9c ZY |
1541 | |
1542 | err_pci_alloc: | |
15b1687c | 1543 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
3599d39a | 1544 | iwl_dealloc_ucode(priv); |
b08dfd04 | 1545 | out_unbind: |
a15707d8 | 1546 | complete(&priv->_agn.firmware_loading_complete); |
3599d39a | 1547 | device_release_driver(priv->bus.dev); |
b481de9c | 1548 | release_firmware(ucode_raw); |
b481de9c ZY |
1549 | } |
1550 | ||
b7a79404 RC |
1551 | static const char *desc_lookup_text[] = { |
1552 | "OK", | |
1553 | "FAIL", | |
1554 | "BAD_PARAM", | |
1555 | "BAD_CHECKSUM", | |
1556 | "NMI_INTERRUPT_WDG", | |
1557 | "SYSASSERT", | |
1558 | "FATAL_ERROR", | |
1559 | "BAD_COMMAND", | |
1560 | "HW_ERROR_TUNE_LOCK", | |
1561 | "HW_ERROR_TEMPERATURE", | |
1562 | "ILLEGAL_CHAN_FREQ", | |
1563 | "VCC_NOT_STABLE", | |
1564 | "FH_ERROR", | |
1565 | "NMI_INTERRUPT_HOST", | |
1566 | "NMI_INTERRUPT_ACTION_PT", | |
1567 | "NMI_INTERRUPT_UNKNOWN", | |
1568 | "UCODE_VERSION_MISMATCH", | |
1569 | "HW_ERROR_ABS_LOCK", | |
1570 | "HW_ERROR_CAL_LOCK_FAIL", | |
1571 | "NMI_INTERRUPT_INST_ACTION_PT", | |
1572 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
1573 | "NMI_TRM_HW_ER", | |
1574 | "NMI_INTERRUPT_TRM", | |
1575 | "NMI_INTERRUPT_BREAK_POINT" | |
1576 | "DEBUG_0", | |
1577 | "DEBUG_1", | |
1578 | "DEBUG_2", | |
1579 | "DEBUG_3", | |
b7a79404 RC |
1580 | }; |
1581 | ||
4b58645c JS |
1582 | static struct { char *name; u8 num; } advanced_lookup[] = { |
1583 | { "NMI_INTERRUPT_WDG", 0x34 }, | |
1584 | { "SYSASSERT", 0x35 }, | |
1585 | { "UCODE_VERSION_MISMATCH", 0x37 }, | |
1586 | { "BAD_COMMAND", 0x38 }, | |
1587 | { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, | |
1588 | { "FATAL_ERROR", 0x3D }, | |
1589 | { "NMI_TRM_HW_ERR", 0x46 }, | |
1590 | { "NMI_INTERRUPT_TRM", 0x4C }, | |
1591 | { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, | |
1592 | { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, | |
1593 | { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, | |
1594 | { "NMI_INTERRUPT_HOST", 0x66 }, | |
1595 | { "NMI_INTERRUPT_ACTION_PT", 0x7C }, | |
1596 | { "NMI_INTERRUPT_UNKNOWN", 0x84 }, | |
1597 | { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, | |
1598 | { "ADVANCED_SYSASSERT", 0 }, | |
1599 | }; | |
1600 | ||
1601 | static const char *desc_lookup(u32 num) | |
b7a79404 | 1602 | { |
4b58645c JS |
1603 | int i; |
1604 | int max = ARRAY_SIZE(desc_lookup_text); | |
b7a79404 | 1605 | |
4b58645c JS |
1606 | if (num < max) |
1607 | return desc_lookup_text[num]; | |
b7a79404 | 1608 | |
4b58645c JS |
1609 | max = ARRAY_SIZE(advanced_lookup) - 1; |
1610 | for (i = 0; i < max; i++) { | |
1611 | if (advanced_lookup[i].num == num) | |
6eab04a8 | 1612 | break; |
4b58645c JS |
1613 | } |
1614 | return advanced_lookup[i].name; | |
b7a79404 RC |
1615 | } |
1616 | ||
1617 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1618 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1619 | ||
1620 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
1621 | { | |
50650547 | 1622 | u32 base; |
e46f6538 | 1623 | struct iwl_error_event_table table; |
b7a79404 | 1624 | |
d7d5783c | 1625 | base = priv->device_pointers.error_event_table; |
872907bb | 1626 | if (priv->ucode_type == IWL_UCODE_INIT) { |
b2e640d4 JB |
1627 | if (!base) |
1628 | base = priv->_agn.init_errlog_ptr; | |
1629 | } else { | |
b2e640d4 JB |
1630 | if (!base) |
1631 | base = priv->_agn.inst_errlog_ptr; | |
1632 | } | |
b7a79404 RC |
1633 | |
1634 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
1635 | IWL_ERR(priv, |
1636 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
ca7966c8 | 1637 | base, |
872907bb | 1638 | (priv->ucode_type == IWL_UCODE_INIT) |
ca7966c8 | 1639 | ? "Init" : "RT"); |
b7a79404 RC |
1640 | return; |
1641 | } | |
1642 | ||
e46f6538 JB |
1643 | iwl_read_targ_mem_words(priv, base, &table, sizeof(table)); |
1644 | ||
50650547 | 1645 | if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { |
b7a79404 RC |
1646 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); |
1647 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
50650547 | 1648 | priv->status, table.valid); |
b7a79404 RC |
1649 | } |
1650 | ||
50650547 WYG |
1651 | priv->isr_stats.err_code = table.error_id; |
1652 | ||
1653 | trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low, | |
1654 | table.data1, table.data2, table.line, | |
1655 | table.blink1, table.blink2, table.ilink1, | |
1656 | table.ilink2, table.bcon_time, table.gp1, | |
1657 | table.gp2, table.gp3, table.ucode_ver, | |
1658 | table.hw_ver, table.brd_ver); | |
1659 | IWL_ERR(priv, "0x%08X | %-28s\n", table.error_id, | |
1660 | desc_lookup(table.error_id)); | |
1661 | IWL_ERR(priv, "0x%08X | uPc\n", table.pc); | |
1662 | IWL_ERR(priv, "0x%08X | branchlink1\n", table.blink1); | |
1663 | IWL_ERR(priv, "0x%08X | branchlink2\n", table.blink2); | |
1664 | IWL_ERR(priv, "0x%08X | interruptlink1\n", table.ilink1); | |
1665 | IWL_ERR(priv, "0x%08X | interruptlink2\n", table.ilink2); | |
1666 | IWL_ERR(priv, "0x%08X | data1\n", table.data1); | |
1667 | IWL_ERR(priv, "0x%08X | data2\n", table.data2); | |
1668 | IWL_ERR(priv, "0x%08X | line\n", table.line); | |
1669 | IWL_ERR(priv, "0x%08X | beacon time\n", table.bcon_time); | |
1670 | IWL_ERR(priv, "0x%08X | tsf low\n", table.tsf_low); | |
1671 | IWL_ERR(priv, "0x%08X | tsf hi\n", table.tsf_hi); | |
1672 | IWL_ERR(priv, "0x%08X | time gp1\n", table.gp1); | |
1673 | IWL_ERR(priv, "0x%08X | time gp2\n", table.gp2); | |
1674 | IWL_ERR(priv, "0x%08X | time gp3\n", table.gp3); | |
1675 | IWL_ERR(priv, "0x%08X | uCode version\n", table.ucode_ver); | |
1676 | IWL_ERR(priv, "0x%08X | hw version\n", table.hw_ver); | |
1677 | IWL_ERR(priv, "0x%08X | board version\n", table.brd_ver); | |
1678 | IWL_ERR(priv, "0x%08X | hcmd\n", table.hcmd); | |
b7a79404 RC |
1679 | } |
1680 | ||
1681 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
1682 | ||
1683 | /** | |
1684 | * iwl_print_event_log - Dump error event log to syslog | |
1685 | * | |
1686 | */ | |
b03d7d0f WYG |
1687 | static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
1688 | u32 num_events, u32 mode, | |
1689 | int pos, char **buf, size_t bufsz) | |
b7a79404 RC |
1690 | { |
1691 | u32 i; | |
1692 | u32 base; /* SRAM byte address of event log header */ | |
1693 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1694 | u32 ptr; /* SRAM byte address of log data */ | |
1695 | u32 ev, time, data; /* event log data */ | |
e5854471 | 1696 | unsigned long reg_flags; |
b7a79404 RC |
1697 | |
1698 | if (num_events == 0) | |
b03d7d0f | 1699 | return pos; |
b2e640d4 | 1700 | |
d7d5783c | 1701 | base = priv->device_pointers.log_event_table; |
872907bb | 1702 | if (priv->ucode_type == IWL_UCODE_INIT) { |
b2e640d4 JB |
1703 | if (!base) |
1704 | base = priv->_agn.init_evtlog_ptr; | |
1705 | } else { | |
b2e640d4 JB |
1706 | if (!base) |
1707 | base = priv->_agn.inst_evtlog_ptr; | |
1708 | } | |
b7a79404 RC |
1709 | |
1710 | if (mode == 0) | |
1711 | event_size = 2 * sizeof(u32); | |
1712 | else | |
1713 | event_size = 3 * sizeof(u32); | |
1714 | ||
1715 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1716 | ||
e5854471 BC |
1717 | /* Make sure device is powered up for SRAM reads */ |
1718 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
1719 | iwl_grab_nic_access(priv); | |
1720 | ||
1721 | /* Set starting address; reads will auto-increment */ | |
02a7fa00 | 1722 | iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr); |
e5854471 BC |
1723 | rmb(); |
1724 | ||
b7a79404 RC |
1725 | /* "time" is actually "data" for mode 0 (no timestamp). |
1726 | * place event id # at far right for easier visual parsing. */ | |
1727 | for (i = 0; i < num_events; i++) { | |
02a7fa00 JB |
1728 | ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
1729 | time = iwl_read32(priv, HBUS_TARG_MEM_RDAT); | |
b7a79404 RC |
1730 | if (mode == 0) { |
1731 | /* data, ev */ | |
b03d7d0f WYG |
1732 | if (bufsz) { |
1733 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1734 | "EVT_LOG:0x%08x:%04u\n", | |
1735 | time, ev); | |
1736 | } else { | |
1737 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
1738 | time, ev); | |
1739 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", | |
1740 | time, ev); | |
1741 | } | |
b7a79404 | 1742 | } else { |
02a7fa00 | 1743 | data = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
1744 | if (bufsz) { |
1745 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1746 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
1747 | time, data, ev); | |
1748 | } else { | |
1749 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
b7a79404 | 1750 | time, data, ev); |
b03d7d0f WYG |
1751 | trace_iwlwifi_dev_ucode_event(priv, time, |
1752 | data, ev); | |
1753 | } | |
b7a79404 RC |
1754 | } |
1755 | } | |
e5854471 BC |
1756 | |
1757 | /* Allow device to power down */ | |
1758 | iwl_release_nic_access(priv); | |
1759 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 1760 | return pos; |
b7a79404 RC |
1761 | } |
1762 | ||
c341ddb2 WYG |
1763 | /** |
1764 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
1765 | */ | |
b03d7d0f WYG |
1766 | static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
1767 | u32 num_wraps, u32 next_entry, | |
1768 | u32 size, u32 mode, | |
1769 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
1770 | { |
1771 | /* | |
1772 | * display the newest DEFAULT_LOG_ENTRIES entries | |
1773 | * i.e the entries just before the next ont that uCode would fill. | |
1774 | */ | |
1775 | if (num_wraps) { | |
1776 | if (next_entry < size) { | |
b03d7d0f WYG |
1777 | pos = iwl_print_event_log(priv, |
1778 | capacity - (size - next_entry), | |
1779 | size - next_entry, mode, | |
1780 | pos, buf, bufsz); | |
1781 | pos = iwl_print_event_log(priv, 0, | |
1782 | next_entry, mode, | |
1783 | pos, buf, bufsz); | |
c341ddb2 | 1784 | } else |
b03d7d0f WYG |
1785 | pos = iwl_print_event_log(priv, next_entry - size, |
1786 | size, mode, pos, buf, bufsz); | |
c341ddb2 | 1787 | } else { |
b03d7d0f WYG |
1788 | if (next_entry < size) { |
1789 | pos = iwl_print_event_log(priv, 0, next_entry, | |
1790 | mode, pos, buf, bufsz); | |
1791 | } else { | |
1792 | pos = iwl_print_event_log(priv, next_entry - size, | |
1793 | size, mode, pos, buf, bufsz); | |
1794 | } | |
c341ddb2 | 1795 | } |
b03d7d0f | 1796 | return pos; |
c341ddb2 WYG |
1797 | } |
1798 | ||
c341ddb2 WYG |
1799 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) |
1800 | ||
b03d7d0f WYG |
1801 | int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
1802 | char **buf, bool display) | |
b7a79404 RC |
1803 | { |
1804 | u32 base; /* SRAM byte address of event log header */ | |
1805 | u32 capacity; /* event log capacity in # entries */ | |
1806 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
1807 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
1808 | u32 next_entry; /* index of next entry to be written by uCode */ | |
1809 | u32 size; /* # entries that we'll print */ | |
b2e640d4 | 1810 | u32 logsize; |
b03d7d0f WYG |
1811 | int pos = 0; |
1812 | size_t bufsz = 0; | |
b7a79404 | 1813 | |
d7d5783c | 1814 | base = priv->device_pointers.log_event_table; |
872907bb | 1815 | if (priv->ucode_type == IWL_UCODE_INIT) { |
b2e640d4 JB |
1816 | logsize = priv->_agn.init_evtlog_size; |
1817 | if (!base) | |
1818 | base = priv->_agn.init_evtlog_ptr; | |
1819 | } else { | |
b2e640d4 JB |
1820 | logsize = priv->_agn.inst_evtlog_size; |
1821 | if (!base) | |
1822 | base = priv->_agn.inst_evtlog_ptr; | |
1823 | } | |
b7a79404 RC |
1824 | |
1825 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
1826 | IWL_ERR(priv, |
1827 | "Invalid event log pointer 0x%08X for %s uCode\n", | |
ca7966c8 | 1828 | base, |
872907bb | 1829 | (priv->ucode_type == IWL_UCODE_INIT) |
ca7966c8 | 1830 | ? "Init" : "RT"); |
937c397e | 1831 | return -EINVAL; |
b7a79404 RC |
1832 | } |
1833 | ||
1834 | /* event log header */ | |
1835 | capacity = iwl_read_targ_mem(priv, base); | |
1836 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
1837 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
1838 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
1839 | ||
b2e640d4 | 1840 | if (capacity > logsize) { |
84c40692 | 1841 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", |
b2e640d4 JB |
1842 | capacity, logsize); |
1843 | capacity = logsize; | |
84c40692 BC |
1844 | } |
1845 | ||
b2e640d4 | 1846 | if (next_entry > logsize) { |
84c40692 | 1847 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", |
b2e640d4 JB |
1848 | next_entry, logsize); |
1849 | next_entry = logsize; | |
84c40692 BC |
1850 | } |
1851 | ||
b7a79404 RC |
1852 | size = num_wraps ? capacity : next_entry; |
1853 | ||
1854 | /* bail out if nothing in log */ | |
1855 | if (size == 0) { | |
1856 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
b03d7d0f | 1857 | return pos; |
b7a79404 RC |
1858 | } |
1859 | ||
9f28ebc3 | 1860 | /* enable/disable bt channel inhibition */ |
f37837c9 WYG |
1861 | priv->bt_ch_announce = iwlagn_bt_ch_announce; |
1862 | ||
c341ddb2 | 1863 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 1864 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
1865 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
1866 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
1867 | #else | |
1868 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
1869 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
1870 | #endif | |
1871 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n", | |
1872 | size); | |
b7a79404 | 1873 | |
c341ddb2 | 1874 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
1875 | if (display) { |
1876 | if (full_log) | |
1877 | bufsz = capacity * 48; | |
1878 | else | |
1879 | bufsz = size * 48; | |
1880 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1881 | if (!*buf) | |
937c397e | 1882 | return -ENOMEM; |
b03d7d0f | 1883 | } |
c341ddb2 WYG |
1884 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
1885 | /* | |
1886 | * if uCode has wrapped back to top of log, | |
1887 | * start at the oldest entry, | |
1888 | * i.e the next one that uCode would fill. | |
1889 | */ | |
1890 | if (num_wraps) | |
b03d7d0f WYG |
1891 | pos = iwl_print_event_log(priv, next_entry, |
1892 | capacity - next_entry, mode, | |
1893 | pos, buf, bufsz); | |
c341ddb2 | 1894 | /* (then/else) start at top of log */ |
b03d7d0f WYG |
1895 | pos = iwl_print_event_log(priv, 0, |
1896 | next_entry, mode, pos, buf, bufsz); | |
c341ddb2 | 1897 | } else |
b03d7d0f WYG |
1898 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
1899 | next_entry, size, mode, | |
1900 | pos, buf, bufsz); | |
c341ddb2 | 1901 | #else |
b03d7d0f WYG |
1902 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
1903 | next_entry, size, mode, | |
1904 | pos, buf, bufsz); | |
b7a79404 | 1905 | #endif |
b03d7d0f | 1906 | return pos; |
c341ddb2 | 1907 | } |
b7a79404 | 1908 | |
0975cc8f WYG |
1909 | static void iwl_rf_kill_ct_config(struct iwl_priv *priv) |
1910 | { | |
1911 | struct iwl_ct_kill_config cmd; | |
1912 | struct iwl_ct_kill_throttling_config adv_cmd; | |
1913 | unsigned long flags; | |
1914 | int ret = 0; | |
1915 | ||
1916 | spin_lock_irqsave(&priv->lock, flags); | |
1917 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
1918 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | |
1919 | spin_unlock_irqrestore(&priv->lock, flags); | |
1920 | priv->thermal_throttle.ct_kill_toggle = false; | |
1921 | ||
7cb1b088 | 1922 | if (priv->cfg->base_params->support_ct_kill_exit) { |
0975cc8f WYG |
1923 | adv_cmd.critical_temperature_enter = |
1924 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
1925 | adv_cmd.critical_temperature_exit = | |
1926 | cpu_to_le32(priv->hw_params.ct_kill_exit_threshold); | |
1927 | ||
1928 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
1929 | sizeof(adv_cmd), &adv_cmd); | |
1930 | if (ret) | |
1931 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
1932 | else | |
1933 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
1934 | "succeeded, " | |
1935 | "critical temperature enter is %d," | |
1936 | "exit is %d\n", | |
1937 | priv->hw_params.ct_kill_threshold, | |
1938 | priv->hw_params.ct_kill_exit_threshold); | |
1939 | } else { | |
1940 | cmd.critical_temperature_R = | |
1941 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
1942 | ||
1943 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
1944 | sizeof(cmd), &cmd); | |
1945 | if (ret) | |
1946 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
1947 | else | |
1948 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
1949 | "succeeded, " | |
1950 | "critical temperature is %d\n", | |
1951 | priv->hw_params.ct_kill_threshold); | |
1952 | } | |
1953 | } | |
1954 | ||
6d6a1afd SZ |
1955 | static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg) |
1956 | { | |
1957 | struct iwl_calib_cfg_cmd calib_cfg_cmd; | |
1958 | struct iwl_host_cmd cmd = { | |
1959 | .id = CALIBRATION_CFG_CMD, | |
3fa50738 JB |
1960 | .len = { sizeof(struct iwl_calib_cfg_cmd), }, |
1961 | .data = { &calib_cfg_cmd, }, | |
6d6a1afd SZ |
1962 | }; |
1963 | ||
1964 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
1965 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
7cb1b088 | 1966 | calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg); |
6d6a1afd SZ |
1967 | |
1968 | return iwl_send_cmd(priv, &cmd); | |
1969 | } | |
1970 | ||
1971 | ||
b481de9c | 1972 | /** |
4a4a9e81 | 1973 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 1974 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 1975 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 1976 | */ |
4613e72d | 1977 | int iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 1978 | { |
57aab75a | 1979 | int ret = 0; |
246ed355 | 1980 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 1981 | |
ca7966c8 | 1982 | iwl_reset_ict(priv); |
b481de9c | 1983 | |
ca7966c8 | 1984 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
6d6a1afd | 1985 | |
5b9f8cd3 | 1986 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
1987 | set_bit(STATUS_ALIVE, &priv->status); |
1988 | ||
22de94de SG |
1989 | /* Enable watchdog to monitor the driver tx queues */ |
1990 | iwl_setup_watchdog(priv); | |
b74e31a9 | 1991 | |
fee1247a | 1992 | if (iwl_is_rfkill(priv)) |
ca7966c8 | 1993 | return -ERFKILL; |
b481de9c | 1994 | |
bc795df1 | 1995 | /* download priority table before any calibration request */ |
7cb1b088 WYG |
1996 | if (priv->cfg->bt_params && |
1997 | priv->cfg->bt_params->advanced_bt_coexist) { | |
f7322f8f WYG |
1998 | /* Configure Bluetooth device coexistence support */ |
1999 | priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; | |
2000 | priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; | |
2001 | priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; | |
2002 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
2003 | priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS; | |
a5901cbb | 2004 | iwlagn_send_prio_tbl(priv); |
f7322f8f WYG |
2005 | |
2006 | /* FIXME: w/a to force change uCode BT state machine */ | |
ca7966c8 JB |
2007 | ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN, |
2008 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); | |
2009 | if (ret) | |
2010 | return ret; | |
2011 | ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE, | |
2012 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); | |
2013 | if (ret) | |
2014 | return ret; | |
f7322f8f | 2015 | } |
bc795df1 WYG |
2016 | if (priv->hw_params.calib_rt_cfg) |
2017 | iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg); | |
2018 | ||
36d6825b | 2019 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2020 | |
470ab2dd | 2021 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2022 | |
2f748dec WYG |
2023 | /* Configure Tx antenna selection based on H/W config */ |
2024 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
2025 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
2026 | ||
246ed355 | 2027 | if (iwl_is_associated_ctx(ctx)) { |
c1adf9fb | 2028 | struct iwl_rxon_cmd *active_rxon = |
246ed355 | 2029 | (struct iwl_rxon_cmd *)&ctx->active; |
019fb97d | 2030 | /* apply any changes in staging */ |
246ed355 | 2031 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2032 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2033 | } else { | |
d0fe478c | 2034 | struct iwl_rxon_context *tmp; |
b481de9c | 2035 | /* Initialize our rx_config data */ |
d0fe478c JB |
2036 | for_each_context(priv, tmp) |
2037 | iwl_connection_init_rx_config(priv, tmp); | |
45823531 AK |
2038 | |
2039 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 | 2040 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); |
b481de9c ZY |
2041 | } |
2042 | ||
73b78a22 WYG |
2043 | if (!priv->cfg->bt_params || (priv->cfg->bt_params && |
2044 | !priv->cfg->bt_params->advanced_bt_coexist)) { | |
2045 | /* | |
2046 | * default is 2-wire BT coexexistence support | |
2047 | */ | |
aeb4a2ee WYG |
2048 | priv->cfg->ops->hcmd->send_bt_config(priv); |
2049 | } | |
b481de9c | 2050 | |
4a4a9e81 TW |
2051 | iwl_reset_run_time_calib(priv); |
2052 | ||
9e2e7422 WYG |
2053 | set_bit(STATUS_READY, &priv->status); |
2054 | ||
b481de9c | 2055 | /* Configure the adapter for unassociated operation */ |
805a3b81 | 2056 | ret = iwlagn_commit_rxon(priv, ctx); |
ca7966c8 JB |
2057 | if (ret) |
2058 | return ret; | |
b481de9c ZY |
2059 | |
2060 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 2061 | iwl_rf_kill_ct_config(priv); |
5a66926a | 2062 | |
e1623446 | 2063 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
c46fbefa | 2064 | |
ca7966c8 | 2065 | return iwl_power_update_mode(priv, true); |
b481de9c ZY |
2066 | } |
2067 | ||
4e39317d | 2068 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2069 | |
5b9f8cd3 | 2070 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c | 2071 | { |
22dd2fd2 | 2072 | int exit_pending; |
b481de9c | 2073 | |
e1623446 | 2074 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2075 | |
d745d472 SG |
2076 | iwl_scan_cancel_timeout(priv, 200); |
2077 | ||
2078 | exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2079 | |
b62177a0 SG |
2080 | /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set |
2081 | * to prevent rearm timer */ | |
22de94de | 2082 | del_timer_sync(&priv->watchdog); |
b62177a0 | 2083 | |
dcef732c | 2084 | iwl_clear_ucode_stations(priv, NULL); |
a194e324 | 2085 | iwl_dealloc_bcast_stations(priv); |
db125c78 | 2086 | iwl_clear_driver_stations(priv); |
b481de9c | 2087 | |
a1174138 | 2088 | /* reset BT coex data */ |
da5dbb97 | 2089 | priv->bt_status = 0; |
7cb1b088 WYG |
2090 | if (priv->cfg->bt_params) |
2091 | priv->bt_traffic_load = | |
2092 | priv->cfg->bt_params->bt_init_traffic_load; | |
2093 | else | |
2094 | priv->bt_traffic_load = 0; | |
bee008b7 WYG |
2095 | priv->bt_full_concurrent = false; |
2096 | priv->bt_ci_compliance = 0; | |
a1174138 | 2097 | |
b481de9c ZY |
2098 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2099 | * exiting the module */ | |
2100 | if (!exit_pending) | |
2101 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2102 | ||
b481de9c ZY |
2103 | if (priv->mac80211_registered) |
2104 | ieee80211_stop_queues(priv->hw); | |
2105 | ||
1a10f433 | 2106 | /* Clear out all status bits but a few that are stable across reset */ |
b481de9c ZY |
2107 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2108 | STATUS_RF_KILL_HW | | |
9788864e RC |
2109 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2110 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2111 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
2112 | STATUS_FW_ERROR | |
2113 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2114 | STATUS_EXIT_PENDING; | |
b481de9c | 2115 | |
bc4f8ada | 2116 | iwlagn_stop_device(priv); |
4d2ccdb9 | 2117 | |
77834543 | 2118 | dev_kfree_skb(priv->beacon_skb); |
12e934dc | 2119 | priv->beacon_skb = NULL; |
b481de9c ZY |
2120 | } |
2121 | ||
5b9f8cd3 | 2122 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2123 | { |
2124 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2125 | __iwl_down(priv); |
b481de9c | 2126 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2127 | |
4e39317d | 2128 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
2129 | } |
2130 | ||
086ed117 MA |
2131 | #define HW_READY_TIMEOUT (50) |
2132 | ||
4cd2bf76 | 2133 | /* Note: returns poll_bit return value, which is >= 0 if success */ |
086ed117 MA |
2134 | static int iwl_set_hw_ready(struct iwl_priv *priv) |
2135 | { | |
4cd2bf76 | 2136 | int ret; |
086ed117 MA |
2137 | |
2138 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2139 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
2140 | ||
2141 | /* See if we got it */ | |
2142 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2143 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2144 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2145 | HW_READY_TIMEOUT); | |
086ed117 | 2146 | |
4cd2bf76 | 2147 | IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : ""); |
086ed117 MA |
2148 | return ret; |
2149 | } | |
2150 | ||
4cd2bf76 | 2151 | /* Note: returns standard 0/-ERROR code */ |
3e14c1fd | 2152 | int iwl_prepare_card_hw(struct iwl_priv *priv) |
086ed117 | 2153 | { |
4cd2bf76 | 2154 | int ret; |
086ed117 | 2155 | |
91dd6c27 | 2156 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n"); |
086ed117 | 2157 | |
3354a0f6 | 2158 | ret = iwl_set_hw_ready(priv); |
4cd2bf76 JB |
2159 | if (ret >= 0) |
2160 | return 0; | |
3354a0f6 MA |
2161 | |
2162 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
2163 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
2164 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
2165 | ||
2166 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2167 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
2168 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
2169 | ||
4cd2bf76 JB |
2170 | if (ret < 0) |
2171 | return ret; | |
086ed117 | 2172 | |
4cd2bf76 JB |
2173 | /* HW should be ready by now, check again. */ |
2174 | ret = iwl_set_hw_ready(priv); | |
2175 | if (ret >= 0) | |
2176 | return 0; | |
086ed117 MA |
2177 | return ret; |
2178 | } | |
2179 | ||
b481de9c ZY |
2180 | #define MAX_HW_RESTARTS 5 |
2181 | ||
5b9f8cd3 | 2182 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 2183 | { |
a194e324 | 2184 | struct iwl_rxon_context *ctx; |
57aab75a | 2185 | int ret; |
b481de9c | 2186 | |
ca7966c8 JB |
2187 | lockdep_assert_held(&priv->mutex); |
2188 | ||
b481de9c | 2189 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { |
39aadf8c | 2190 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2191 | return -EIO; |
2192 | } | |
2193 | ||
a194e324 | 2194 | for_each_context(priv, ctx) { |
a30e3112 | 2195 | ret = iwlagn_alloc_bcast_station(priv, ctx); |
a194e324 JB |
2196 | if (ret) { |
2197 | iwl_dealloc_bcast_stations(priv); | |
2198 | return ret; | |
2199 | } | |
2200 | } | |
2c810ccd | 2201 | |
ca7966c8 JB |
2202 | ret = iwlagn_run_init_ucode(priv); |
2203 | if (ret) { | |
2204 | IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret); | |
2205 | goto error; | |
2206 | } | |
b481de9c | 2207 | |
ca7966c8 | 2208 | ret = iwlagn_load_ucode_wait_alive(priv, |
dbf28e21 | 2209 | &priv->ucode_rt, |
872907bb | 2210 | IWL_UCODE_REGULAR); |
ca7966c8 JB |
2211 | if (ret) { |
2212 | IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret); | |
2213 | goto error; | |
b481de9c ZY |
2214 | } |
2215 | ||
ca7966c8 JB |
2216 | ret = iwl_alive_start(priv); |
2217 | if (ret) | |
2218 | goto error; | |
2219 | return 0; | |
2220 | ||
2221 | error: | |
b481de9c | 2222 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
5b9f8cd3 | 2223 | __iwl_down(priv); |
64e72c3e | 2224 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c | 2225 | |
ca7966c8 JB |
2226 | IWL_ERR(priv, "Unable to initialize device.\n"); |
2227 | return ret; | |
b481de9c ZY |
2228 | } |
2229 | ||
2230 | ||
2231 | /***************************************************************************** | |
2232 | * | |
2233 | * Workqueue callbacks | |
2234 | * | |
2235 | *****************************************************************************/ | |
2236 | ||
16e727e8 EG |
2237 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
2238 | { | |
2239 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
2240 | run_time_calib_work); | |
2241 | ||
2242 | mutex_lock(&priv->mutex); | |
2243 | ||
2244 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
2245 | test_bit(STATUS_SCANNING, &priv->status)) { | |
2246 | mutex_unlock(&priv->mutex); | |
2247 | return; | |
2248 | } | |
2249 | ||
2250 | if (priv->start_calib) { | |
0da0e5bf JB |
2251 | iwl_chain_noise_calibration(priv); |
2252 | iwl_sensitivity_calibration(priv); | |
16e727e8 EG |
2253 | } |
2254 | ||
2255 | mutex_unlock(&priv->mutex); | |
16e727e8 EG |
2256 | } |
2257 | ||
e43e85c4 JB |
2258 | static void iwlagn_prepare_restart(struct iwl_priv *priv) |
2259 | { | |
2260 | struct iwl_rxon_context *ctx; | |
2261 | bool bt_full_concurrent; | |
2262 | u8 bt_ci_compliance; | |
2263 | u8 bt_load; | |
2264 | u8 bt_status; | |
2265 | ||
2266 | lockdep_assert_held(&priv->mutex); | |
2267 | ||
2268 | for_each_context(priv, ctx) | |
2269 | ctx->vif = NULL; | |
2270 | priv->is_open = 0; | |
2271 | ||
2272 | /* | |
2273 | * __iwl_down() will clear the BT status variables, | |
2274 | * which is correct, but when we restart we really | |
2275 | * want to keep them so restore them afterwards. | |
2276 | * | |
2277 | * The restart process will later pick them up and | |
2278 | * re-configure the hw when we reconfigure the BT | |
2279 | * command. | |
2280 | */ | |
2281 | bt_full_concurrent = priv->bt_full_concurrent; | |
2282 | bt_ci_compliance = priv->bt_ci_compliance; | |
2283 | bt_load = priv->bt_traffic_load; | |
2284 | bt_status = priv->bt_status; | |
2285 | ||
2286 | __iwl_down(priv); | |
2287 | ||
2288 | priv->bt_full_concurrent = bt_full_concurrent; | |
2289 | priv->bt_ci_compliance = bt_ci_compliance; | |
2290 | priv->bt_traffic_load = bt_load; | |
2291 | priv->bt_status = bt_status; | |
2292 | } | |
2293 | ||
5b9f8cd3 | 2294 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2295 | { |
c79dd5b5 | 2296 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2297 | |
2298 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2299 | return; | |
2300 | ||
19cc1087 JB |
2301 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
2302 | mutex_lock(&priv->mutex); | |
e43e85c4 | 2303 | iwlagn_prepare_restart(priv); |
19cc1087 | 2304 | mutex_unlock(&priv->mutex); |
a1174138 | 2305 | iwl_cancel_deferred_work(priv); |
19cc1087 JB |
2306 | ieee80211_restart_hw(priv->hw); |
2307 | } else { | |
ca7966c8 | 2308 | WARN_ON(1); |
19cc1087 | 2309 | } |
b481de9c ZY |
2310 | } |
2311 | ||
5b9f8cd3 | 2312 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2313 | { |
c79dd5b5 TW |
2314 | struct iwl_priv *priv = |
2315 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2316 | |
2317 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2318 | return; | |
2319 | ||
2320 | mutex_lock(&priv->mutex); | |
54b81550 | 2321 | iwlagn_rx_replenish(priv); |
b481de9c ZY |
2322 | mutex_unlock(&priv->mutex); |
2323 | } | |
2324 | ||
266af4c7 JB |
2325 | static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb, |
2326 | struct ieee80211_channel *chan, | |
2327 | enum nl80211_channel_type channel_type, | |
2328 | unsigned int wait) | |
2329 | { | |
2330 | struct iwl_priv *priv = hw->priv; | |
2331 | int ret; | |
2332 | ||
2333 | /* Not supported if we don't have PAN */ | |
2334 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) { | |
2335 | ret = -EOPNOTSUPP; | |
2336 | goto free; | |
2337 | } | |
2338 | ||
2339 | /* Not supported on pre-P2P firmware */ | |
2340 | if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes & | |
2341 | BIT(NL80211_IFTYPE_P2P_CLIENT))) { | |
2342 | ret = -EOPNOTSUPP; | |
2343 | goto free; | |
2344 | } | |
2345 | ||
2346 | mutex_lock(&priv->mutex); | |
2347 | ||
2348 | if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) { | |
2349 | /* | |
2350 | * If the PAN context is free, use the normal | |
2351 | * way of doing remain-on-channel offload + TX. | |
2352 | */ | |
2353 | ret = 1; | |
2354 | goto out; | |
2355 | } | |
2356 | ||
2357 | /* TODO: queue up if scanning? */ | |
2358 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
2359 | priv->_agn.offchan_tx_skb) { | |
2360 | ret = -EBUSY; | |
2361 | goto out; | |
2362 | } | |
2363 | ||
2364 | /* | |
2365 | * max_scan_ie_len doesn't include the blank SSID or the header, | |
2366 | * so need to add that again here. | |
2367 | */ | |
2368 | if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) { | |
2369 | ret = -ENOBUFS; | |
2370 | goto out; | |
2371 | } | |
2372 | ||
2373 | priv->_agn.offchan_tx_skb = skb; | |
2374 | priv->_agn.offchan_tx_timeout = wait; | |
2375 | priv->_agn.offchan_tx_chan = chan; | |
2376 | ||
2377 | ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif, | |
2378 | IWL_SCAN_OFFCH_TX, chan->band); | |
2379 | if (ret) | |
2380 | priv->_agn.offchan_tx_skb = NULL; | |
2381 | out: | |
2382 | mutex_unlock(&priv->mutex); | |
2383 | free: | |
2384 | if (ret < 0) | |
2385 | kfree_skb(skb); | |
2386 | ||
2387 | return ret; | |
2388 | } | |
2389 | ||
2390 | static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw) | |
2391 | { | |
2392 | struct iwl_priv *priv = hw->priv; | |
2393 | int ret; | |
2394 | ||
2395 | mutex_lock(&priv->mutex); | |
2396 | ||
f8a22a2b DC |
2397 | if (!priv->_agn.offchan_tx_skb) { |
2398 | ret = -EINVAL; | |
2399 | goto unlock; | |
2400 | } | |
266af4c7 JB |
2401 | |
2402 | priv->_agn.offchan_tx_skb = NULL; | |
2403 | ||
2404 | ret = iwl_scan_cancel_timeout(priv, 200); | |
2405 | if (ret) | |
2406 | ret = -EIO; | |
f8a22a2b | 2407 | unlock: |
266af4c7 JB |
2408 | mutex_unlock(&priv->mutex); |
2409 | ||
2410 | return ret; | |
2411 | } | |
2412 | ||
b481de9c ZY |
2413 | /***************************************************************************** |
2414 | * | |
2415 | * mac80211 entry point functions | |
2416 | * | |
2417 | *****************************************************************************/ | |
2418 | ||
0fd09502 JB |
2419 | static const struct ieee80211_iface_limit iwlagn_sta_ap_limits[] = { |
2420 | { | |
2421 | .max = 1, | |
2422 | .types = BIT(NL80211_IFTYPE_STATION), | |
2423 | }, | |
2424 | { | |
2425 | .max = 1, | |
2426 | .types = BIT(NL80211_IFTYPE_AP), | |
2427 | }, | |
2428 | }; | |
2429 | ||
2430 | static const struct ieee80211_iface_limit iwlagn_2sta_limits[] = { | |
2431 | { | |
2432 | .max = 2, | |
2433 | .types = BIT(NL80211_IFTYPE_STATION), | |
2434 | }, | |
2435 | }; | |
2436 | ||
2437 | static const struct ieee80211_iface_limit iwlagn_p2p_sta_go_limits[] = { | |
2438 | { | |
2439 | .max = 1, | |
2440 | .types = BIT(NL80211_IFTYPE_STATION), | |
2441 | }, | |
2442 | { | |
2443 | .max = 1, | |
2444 | .types = BIT(NL80211_IFTYPE_P2P_GO) | | |
2445 | BIT(NL80211_IFTYPE_AP), | |
2446 | }, | |
2447 | }; | |
2448 | ||
2449 | static const struct ieee80211_iface_limit iwlagn_p2p_2sta_limits[] = { | |
2450 | { | |
2451 | .max = 2, | |
2452 | .types = BIT(NL80211_IFTYPE_STATION), | |
2453 | }, | |
2454 | { | |
2455 | .max = 1, | |
2456 | .types = BIT(NL80211_IFTYPE_P2P_CLIENT), | |
2457 | }, | |
2458 | }; | |
2459 | ||
2460 | static const struct ieee80211_iface_combination | |
2461 | iwlagn_iface_combinations_dualmode[] = { | |
2462 | { .num_different_channels = 1, | |
2463 | .max_interfaces = 2, | |
2464 | .beacon_int_infra_match = true, | |
2465 | .limits = iwlagn_sta_ap_limits, | |
2466 | .n_limits = ARRAY_SIZE(iwlagn_sta_ap_limits), | |
2467 | }, | |
2468 | { .num_different_channels = 1, | |
2469 | .max_interfaces = 2, | |
2470 | .limits = iwlagn_2sta_limits, | |
2471 | .n_limits = ARRAY_SIZE(iwlagn_2sta_limits), | |
2472 | }, | |
2473 | }; | |
2474 | ||
2475 | static const struct ieee80211_iface_combination | |
2476 | iwlagn_iface_combinations_p2p[] = { | |
2477 | { .num_different_channels = 1, | |
2478 | .max_interfaces = 2, | |
2479 | .beacon_int_infra_match = true, | |
2480 | .limits = iwlagn_p2p_sta_go_limits, | |
2481 | .n_limits = ARRAY_SIZE(iwlagn_p2p_sta_go_limits), | |
2482 | }, | |
2483 | { .num_different_channels = 1, | |
2484 | .max_interfaces = 2, | |
2485 | .limits = iwlagn_p2p_2sta_limits, | |
2486 | .n_limits = ARRAY_SIZE(iwlagn_p2p_2sta_limits), | |
2487 | }, | |
2488 | }; | |
2489 | ||
f0b6e2e8 RC |
2490 | /* |
2491 | * Not a mac80211 entry point function, but it fits in with all the | |
2492 | * other mac80211 functions grouped here. | |
2493 | */ | |
dd7a2509 JB |
2494 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
2495 | struct iwlagn_ucode_capabilities *capa) | |
f0b6e2e8 RC |
2496 | { |
2497 | int ret; | |
2498 | struct ieee80211_hw *hw = priv->hw; | |
d0fe478c JB |
2499 | struct iwl_rxon_context *ctx; |
2500 | ||
f0b6e2e8 RC |
2501 | hw->rate_control_algorithm = "iwl-agn-rs"; |
2502 | ||
2503 | /* Tell mac80211 our characteristics */ | |
2504 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
f0b6e2e8 | 2505 | IEEE80211_HW_AMPDU_AGGREGATION | |
2491fa42 | 2506 | IEEE80211_HW_NEED_DTIM_PERIOD | |
6fb5511a JB |
2507 | IEEE80211_HW_SPECTRUM_MGMT | |
2508 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
f0b6e2e8 | 2509 | |
9b768832 JB |
2510 | hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF; |
2511 | ||
23c0fcc6 WYG |
2512 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | |
2513 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
f0b6e2e8 | 2514 | |
88950758 | 2515 | if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE) |
ba37a3d0 JB |
2516 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | |
2517 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
2518 | ||
3997ff39 JB |
2519 | if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP) |
2520 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; | |
2521 | ||
8d9698b3 | 2522 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
fd1af15d JB |
2523 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
2524 | ||
d0fe478c JB |
2525 | for_each_context(priv, ctx) { |
2526 | hw->wiphy->interface_modes |= ctx->interface_modes; | |
2527 | hw->wiphy->interface_modes |= ctx->exclusive_interface_modes; | |
2528 | } | |
f0b6e2e8 | 2529 | |
0fd09502 JB |
2530 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); |
2531 | ||
f35490f9 | 2532 | if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_P2P_CLIENT)) { |
0fd09502 JB |
2533 | hw->wiphy->iface_combinations = iwlagn_iface_combinations_p2p; |
2534 | hw->wiphy->n_iface_combinations = | |
2535 | ARRAY_SIZE(iwlagn_iface_combinations_p2p); | |
f35490f9 | 2536 | } else if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_AP)) { |
0fd09502 JB |
2537 | hw->wiphy->iface_combinations = iwlagn_iface_combinations_dualmode; |
2538 | hw->wiphy->n_iface_combinations = | |
2539 | ARRAY_SIZE(iwlagn_iface_combinations_dualmode); | |
2540 | } | |
2541 | ||
9b9190d9 JB |
2542 | hw->wiphy->max_remain_on_channel_duration = 1000; |
2543 | ||
f6c8f152 | 2544 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | |
274102a8 JB |
2545 | WIPHY_FLAG_DISABLE_BEACON_HINTS | |
2546 | WIPHY_FLAG_IBSS_RSN; | |
f0b6e2e8 | 2547 | |
0172b029 WYG |
2548 | if (iwlagn_mod_params.power_save) |
2549 | hw->wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
2550 | else | |
2551 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
f0b6e2e8 | 2552 | |
1382c71c | 2553 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; |
f0b6e2e8 | 2554 | /* we create the 802.11 header and a zero-length SSID element */ |
dd7a2509 | 2555 | hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2; |
f0b6e2e8 RC |
2556 | |
2557 | /* Default value; 4 EDCA QOS priorities */ | |
2558 | hw->queues = 4; | |
2559 | ||
2560 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | |
2561 | ||
2562 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
2563 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
2564 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2565 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
2566 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
2567 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
2568 | ||
5ed540ae WYG |
2569 | iwl_leds_init(priv); |
2570 | ||
f0b6e2e8 RC |
2571 | ret = ieee80211_register_hw(priv->hw); |
2572 | if (ret) { | |
2573 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
2574 | return ret; | |
2575 | } | |
2576 | priv->mac80211_registered = 1; | |
2577 | ||
2578 | return 0; | |
2579 | } | |
2580 | ||
2581 | ||
2dedbf58 | 2582 | static int iwlagn_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2583 | { |
c79dd5b5 | 2584 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2585 | int ret; |
b481de9c | 2586 | |
e1623446 | 2587 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2588 | |
2589 | /* we should be verifying the device is ready to be opened */ | |
2590 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2591 | ret = __iwl_up(priv); |
b481de9c | 2592 | mutex_unlock(&priv->mutex); |
e655b9f0 | 2593 | if (ret) |
6cd0b1cb | 2594 | return ret; |
e655b9f0 | 2595 | |
e1623446 | 2596 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2597 | |
ca7966c8 JB |
2598 | /* Now we should be done, and the READY bit should be set. */ |
2599 | if (WARN_ON(!test_bit(STATUS_READY, &priv->status))) | |
2600 | ret = -EIO; | |
0a078ffa | 2601 | |
5ed540ae | 2602 | iwlagn_led_enable(priv); |
e932a609 | 2603 | |
0a078ffa | 2604 | priv->is_open = 1; |
e1623446 | 2605 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2606 | return 0; |
2607 | } | |
2608 | ||
2dedbf58 | 2609 | static void iwlagn_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2610 | { |
c79dd5b5 | 2611 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2612 | |
e1623446 | 2613 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2614 | |
19cc1087 | 2615 | if (!priv->is_open) |
e655b9f0 | 2616 | return; |
e655b9f0 | 2617 | |
b481de9c | 2618 | priv->is_open = 0; |
5a66926a | 2619 | |
5b9f8cd3 | 2620 | iwl_down(priv); |
5a66926a ZY |
2621 | |
2622 | flush_workqueue(priv->workqueue); | |
6cd0b1cb | 2623 | |
554d1d02 SG |
2624 | /* User space software may expect getting rfkill changes |
2625 | * even if interface is down */ | |
6cd0b1cb | 2626 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
554d1d02 | 2627 | iwl_enable_rfkill_int(priv); |
948c171c | 2628 | |
e1623446 | 2629 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2630 | } |
2631 | ||
2dedbf58 | 2632 | static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2633 | { |
c79dd5b5 | 2634 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2635 | |
e1623446 | 2636 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2637 | |
e1623446 | 2638 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2639 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2640 | |
74bcdb33 | 2641 | if (iwlagn_tx_skb(priv, skb)) |
b481de9c ZY |
2642 | dev_kfree_skb_any(skb); |
2643 | ||
e1623446 | 2644 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
b481de9c ZY |
2645 | } |
2646 | ||
2dedbf58 JB |
2647 | static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw, |
2648 | struct ieee80211_vif *vif, | |
2649 | struct ieee80211_key_conf *keyconf, | |
2650 | struct ieee80211_sta *sta, | |
2651 | u32 iv32, u16 *phase1key) | |
ab885f8c | 2652 | { |
9f58671e | 2653 | struct iwl_priv *priv = hw->priv; |
a194e324 JB |
2654 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
2655 | ||
e1623446 | 2656 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2657 | |
a194e324 | 2658 | iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta, |
b3fbdcf4 | 2659 | iv32, phase1key); |
ab885f8c | 2660 | |
e1623446 | 2661 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2662 | } |
2663 | ||
2dedbf58 JB |
2664 | static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
2665 | struct ieee80211_vif *vif, | |
2666 | struct ieee80211_sta *sta, | |
2667 | struct ieee80211_key_conf *key) | |
b481de9c | 2668 | { |
c79dd5b5 | 2669 | struct iwl_priv *priv = hw->priv; |
a194e324 | 2670 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
c10afb6e | 2671 | struct iwl_rxon_context *ctx = vif_priv->ctx; |
42986796 WT |
2672 | int ret; |
2673 | u8 sta_id; | |
2674 | bool is_default_wep_key = false; | |
b481de9c | 2675 | |
e1623446 | 2676 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 2677 | |
9d143e9a | 2678 | if (iwlagn_mod_params.sw_crypto) { |
e1623446 | 2679 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
2680 | return -EOPNOTSUPP; |
2681 | } | |
b481de9c | 2682 | |
274102a8 JB |
2683 | /* |
2684 | * To support IBSS RSN, don't program group keys in IBSS, the | |
2685 | * hardware will then not attempt to decrypt the frames. | |
2686 | */ | |
2687 | if (vif->type == NL80211_IFTYPE_ADHOC && | |
2688 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) | |
2689 | return -EOPNOTSUPP; | |
2690 | ||
a194e324 | 2691 | sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta); |
0af8bcae JB |
2692 | if (sta_id == IWL_INVALID_STATION) |
2693 | return -EINVAL; | |
b481de9c | 2694 | |
6974e363 | 2695 | mutex_lock(&priv->mutex); |
2a421b91 | 2696 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 | 2697 | |
a90178fa JB |
2698 | /* |
2699 | * If we are getting WEP group key and we didn't receive any key mapping | |
6974e363 EG |
2700 | * so far, we are in legacy wep mode (group key only), otherwise we are |
2701 | * in 1X mode. | |
a90178fa JB |
2702 | * In legacy wep mode, we use another host command to the uCode. |
2703 | */ | |
97359d12 JB |
2704 | if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || |
2705 | key->cipher == WLAN_CIPHER_SUITE_WEP104) && | |
54c8067a | 2706 | !sta) { |
6974e363 | 2707 | if (cmd == SET_KEY) |
c10afb6e | 2708 | is_default_wep_key = !ctx->key_mapping_keys; |
6974e363 | 2709 | else |
ccc038ab EG |
2710 | is_default_wep_key = |
2711 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2712 | } |
052c4b9f | 2713 | |
b481de9c | 2714 | switch (cmd) { |
deb09c43 | 2715 | case SET_KEY: |
6974e363 | 2716 | if (is_default_wep_key) |
2995bafa | 2717 | ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key); |
deb09c43 | 2718 | else |
a194e324 JB |
2719 | ret = iwl_set_dynamic_key(priv, vif_priv->ctx, |
2720 | key, sta_id); | |
deb09c43 | 2721 | |
e1623446 | 2722 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
2723 | break; |
2724 | case DISABLE_KEY: | |
6974e363 | 2725 | if (is_default_wep_key) |
c10afb6e | 2726 | ret = iwl_remove_default_wep_key(priv, ctx, key); |
deb09c43 | 2727 | else |
c10afb6e | 2728 | ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id); |
deb09c43 | 2729 | |
e1623446 | 2730 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
2731 | break; |
2732 | default: | |
deb09c43 | 2733 | ret = -EINVAL; |
b481de9c ZY |
2734 | } |
2735 | ||
72e15d71 | 2736 | mutex_unlock(&priv->mutex); |
e1623446 | 2737 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 2738 | |
deb09c43 | 2739 | return ret; |
b481de9c ZY |
2740 | } |
2741 | ||
2dedbf58 JB |
2742 | static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw, |
2743 | struct ieee80211_vif *vif, | |
2744 | enum ieee80211_ampdu_mlme_action action, | |
2745 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, | |
2746 | u8 buf_size) | |
d783b061 TW |
2747 | { |
2748 | struct iwl_priv *priv = hw->priv; | |
4620fefa | 2749 | int ret = -EINVAL; |
7b090687 | 2750 | struct iwl_station_priv *sta_priv = (void *) sta->drv_priv; |
d783b061 | 2751 | |
e1623446 | 2752 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 2753 | sta->addr, tid); |
d783b061 | 2754 | |
88950758 | 2755 | if (!(priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)) |
d783b061 TW |
2756 | return -EACCES; |
2757 | ||
4620fefa JB |
2758 | mutex_lock(&priv->mutex); |
2759 | ||
d783b061 TW |
2760 | switch (action) { |
2761 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 2762 | IWL_DEBUG_HT(priv, "start Rx\n"); |
4620fefa JB |
2763 | ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn); |
2764 | break; | |
d783b061 | 2765 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 2766 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
619753ff | 2767 | ret = iwl_sta_rx_agg_stop(priv, sta, tid); |
5c2207c6 | 2768 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa JB |
2769 | ret = 0; |
2770 | break; | |
d783b061 | 2771 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 2772 | IWL_DEBUG_HT(priv, "start Tx\n"); |
619753ff | 2773 | ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn); |
d5a0ffa3 WYG |
2774 | if (ret == 0) { |
2775 | priv->_agn.agg_tids_count++; | |
2776 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
2777 | priv->_agn.agg_tids_count); | |
2778 | } | |
4620fefa | 2779 | break; |
d783b061 | 2780 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 2781 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
619753ff | 2782 | ret = iwlagn_tx_agg_stop(priv, vif, sta, tid); |
d5a0ffa3 WYG |
2783 | if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) { |
2784 | priv->_agn.agg_tids_count--; | |
2785 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
2786 | priv->_agn.agg_tids_count); | |
2787 | } | |
5c2207c6 | 2788 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa | 2789 | ret = 0; |
7cb1b088 WYG |
2790 | if (priv->cfg->ht_params && |
2791 | priv->cfg->ht_params->use_rts_for_aggregation) { | |
94597ab2 JB |
2792 | /* |
2793 | * switch off RTS/CTS if it was previously enabled | |
2794 | */ | |
94597ab2 JB |
2795 | sta_priv->lq_sta.lq.general_params.flags &= |
2796 | ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
7e6a5886 JB |
2797 | iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), |
2798 | &sta_priv->lq_sta.lq, CMD_ASYNC, false); | |
94597ab2 | 2799 | } |
4620fefa | 2800 | break; |
f0527971 | 2801 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
c8823ec1 JB |
2802 | buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF); |
2803 | ||
2804 | iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size); | |
2805 | ||
7b090687 JB |
2806 | /* |
2807 | * If the limit is 0, then it wasn't initialised yet, | |
2808 | * use the default. We can do that since we take the | |
2809 | * minimum below, and we don't want to go above our | |
2810 | * default due to hardware restrictions. | |
2811 | */ | |
2812 | if (sta_priv->max_agg_bufsize == 0) | |
2813 | sta_priv->max_agg_bufsize = | |
2814 | LINK_QUAL_AGG_FRAME_LIMIT_DEF; | |
2815 | ||
2816 | /* | |
2817 | * Even though in theory the peer could have different | |
2818 | * aggregation reorder buffer sizes for different sessions, | |
2819 | * our ucode doesn't allow for that and has a global limit | |
2820 | * for each station. Therefore, use the minimum of all the | |
2821 | * aggregation sessions and our default value. | |
2822 | */ | |
2823 | sta_priv->max_agg_bufsize = | |
2824 | min(sta_priv->max_agg_bufsize, buf_size); | |
2825 | ||
7cb1b088 WYG |
2826 | if (priv->cfg->ht_params && |
2827 | priv->cfg->ht_params->use_rts_for_aggregation) { | |
cfecc6b4 WYG |
2828 | /* |
2829 | * switch to RTS/CTS if it is the prefer protection | |
2830 | * method for HT traffic | |
2831 | */ | |
94597ab2 JB |
2832 | |
2833 | sta_priv->lq_sta.lq.general_params.flags |= | |
2834 | LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
cfecc6b4 | 2835 | } |
7b090687 JB |
2836 | |
2837 | sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit = | |
2838 | sta_priv->max_agg_bufsize; | |
2839 | ||
2840 | iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), | |
2841 | &sta_priv->lq_sta.lq, CMD_ASYNC, false); | |
5bc9890f WYG |
2842 | |
2843 | IWL_INFO(priv, "Tx aggregation enabled on ra = %pM tid = %d\n", | |
2844 | sta->addr, tid); | |
cfecc6b4 | 2845 | ret = 0; |
d783b061 TW |
2846 | break; |
2847 | } | |
4620fefa JB |
2848 | mutex_unlock(&priv->mutex); |
2849 | ||
2850 | return ret; | |
d783b061 | 2851 | } |
9f58671e | 2852 | |
2dedbf58 JB |
2853 | static int iwlagn_mac_sta_add(struct ieee80211_hw *hw, |
2854 | struct ieee80211_vif *vif, | |
2855 | struct ieee80211_sta *sta) | |
fe6b23dd RC |
2856 | { |
2857 | struct iwl_priv *priv = hw->priv; | |
2858 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
a194e324 | 2859 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
eafdfbd3 | 2860 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
fe6b23dd RC |
2861 | int ret; |
2862 | u8 sta_id; | |
2863 | ||
2864 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", | |
2865 | sta->addr); | |
da5ae1cf RC |
2866 | mutex_lock(&priv->mutex); |
2867 | IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n", | |
2868 | sta->addr); | |
2869 | sta_priv->common.sta_id = IWL_INVALID_STATION; | |
fe6b23dd RC |
2870 | |
2871 | atomic_set(&sta_priv->pending_frames, 0); | |
2872 | if (vif->type == NL80211_IFTYPE_AP) | |
2873 | sta_priv->client = true; | |
2874 | ||
a194e324 | 2875 | ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr, |
238d781d | 2876 | is_ap, sta, &sta_id); |
fe6b23dd RC |
2877 | if (ret) { |
2878 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
2879 | sta->addr, ret); | |
2880 | /* Should we return success if return code is EEXIST ? */ | |
da5ae1cf | 2881 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
2882 | return ret; |
2883 | } | |
2884 | ||
fd1af15d JB |
2885 | sta_priv->common.sta_id = sta_id; |
2886 | ||
fe6b23dd | 2887 | /* Initialize rate scaling */ |
91dd6c27 | 2888 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n", |
fe6b23dd RC |
2889 | sta->addr); |
2890 | iwl_rs_rate_init(priv, sta, sta_id); | |
da5ae1cf | 2891 | mutex_unlock(&priv->mutex); |
fe6b23dd | 2892 | |
fd1af15d | 2893 | return 0; |
fe6b23dd RC |
2894 | } |
2895 | ||
2dedbf58 JB |
2896 | static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw, |
2897 | struct ieee80211_channel_switch *ch_switch) | |
79d07325 WYG |
2898 | { |
2899 | struct iwl_priv *priv = hw->priv; | |
2900 | const struct iwl_channel_info *ch_info; | |
2901 | struct ieee80211_conf *conf = &hw->conf; | |
aa2dc6b5 | 2902 | struct ieee80211_channel *channel = ch_switch->channel; |
79d07325 | 2903 | struct iwl_ht_config *ht_conf = &priv->current_ht_config; |
246ed355 JB |
2904 | /* |
2905 | * MULTI-FIXME | |
2906 | * When we add support for multiple interfaces, we need to | |
2907 | * revisit this. The channel switch command in the device | |
2908 | * only affects the BSS context, but what does that really | |
2909 | * mean? And what if we get a CSA on the second interface? | |
2910 | * This needs a lot of work. | |
2911 | */ | |
2912 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
79d07325 | 2913 | u16 ch; |
79d07325 WYG |
2914 | |
2915 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
2916 | ||
dc1a4068 SG |
2917 | mutex_lock(&priv->mutex); |
2918 | ||
79d07325 | 2919 | if (iwl_is_rfkill(priv)) |
dc1a4068 | 2920 | goto out; |
79d07325 WYG |
2921 | |
2922 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
6f213ff1 SG |
2923 | test_bit(STATUS_SCANNING, &priv->status) || |
2924 | test_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status)) | |
dc1a4068 | 2925 | goto out; |
79d07325 | 2926 | |
246ed355 | 2927 | if (!iwl_is_associated_ctx(ctx)) |
dc1a4068 | 2928 | goto out; |
79d07325 | 2929 | |
f973f87e SG |
2930 | if (!priv->cfg->ops->lib->set_channel_switch) |
2931 | goto out; | |
79d07325 | 2932 | |
f973f87e SG |
2933 | ch = channel->hw_value; |
2934 | if (le16_to_cpu(ctx->active.channel) == ch) | |
2935 | goto out; | |
2936 | ||
2937 | ch_info = iwl_get_channel_info(priv, channel->band, ch); | |
2938 | if (!is_channel_valid(ch_info)) { | |
2939 | IWL_DEBUG_MAC80211(priv, "invalid channel\n"); | |
2940 | goto out; | |
2941 | } | |
79d07325 | 2942 | |
f973f87e | 2943 | spin_lock_irq(&priv->lock); |
79d07325 | 2944 | |
f973f87e | 2945 | priv->current_ht_config.smps = conf->smps_mode; |
79d07325 | 2946 | |
f973f87e SG |
2947 | /* Configure HT40 channels */ |
2948 | ctx->ht.enabled = conf_is_ht(conf); | |
2949 | if (ctx->ht.enabled) { | |
2950 | if (conf_is_ht40_minus(conf)) { | |
2951 | ctx->ht.extension_chan_offset = | |
2952 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; | |
2953 | ctx->ht.is_40mhz = true; | |
2954 | } else if (conf_is_ht40_plus(conf)) { | |
2955 | ctx->ht.extension_chan_offset = | |
2956 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; | |
2957 | ctx->ht.is_40mhz = true; | |
2958 | } else { | |
2959 | ctx->ht.extension_chan_offset = | |
2960 | IEEE80211_HT_PARAM_CHA_SEC_NONE; | |
2961 | ctx->ht.is_40mhz = false; | |
79d07325 | 2962 | } |
f973f87e SG |
2963 | } else |
2964 | ctx->ht.is_40mhz = false; | |
2965 | ||
2966 | if ((le16_to_cpu(ctx->staging.channel) != ch)) | |
2967 | ctx->staging.flags = 0; | |
2968 | ||
2969 | iwl_set_rxon_channel(priv, channel, ctx); | |
2970 | iwl_set_rxon_ht(priv, ht_conf); | |
2971 | iwl_set_flags_for_band(priv, ctx, channel->band, ctx->vif); | |
2972 | ||
2973 | spin_unlock_irq(&priv->lock); | |
2974 | ||
2975 | iwl_set_rate(priv); | |
2976 | /* | |
2977 | * at this point, staging_rxon has the | |
2978 | * configuration for channel switch | |
2979 | */ | |
2980 | set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status); | |
2981 | priv->switch_channel = cpu_to_le16(ch); | |
2982 | if (priv->cfg->ops->lib->set_channel_switch(priv, ch_switch)) { | |
2983 | clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status); | |
2984 | priv->switch_channel = 0; | |
2985 | ieee80211_chswitch_done(ctx->vif, false); | |
79d07325 | 2986 | } |
f973f87e | 2987 | |
79d07325 WYG |
2988 | out: |
2989 | mutex_unlock(&priv->mutex); | |
79d07325 WYG |
2990 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
2991 | } | |
2992 | ||
2dedbf58 JB |
2993 | static void iwlagn_configure_filter(struct ieee80211_hw *hw, |
2994 | unsigned int changed_flags, | |
2995 | unsigned int *total_flags, | |
2996 | u64 multicast) | |
8b8ab9d5 JB |
2997 | { |
2998 | struct iwl_priv *priv = hw->priv; | |
2999 | __le32 filter_or = 0, filter_nand = 0; | |
246ed355 | 3000 | struct iwl_rxon_context *ctx; |
8b8ab9d5 JB |
3001 | |
3002 | #define CHK(test, flag) do { \ | |
3003 | if (*total_flags & (test)) \ | |
3004 | filter_or |= (flag); \ | |
3005 | else \ | |
3006 | filter_nand |= (flag); \ | |
3007 | } while (0) | |
3008 | ||
3009 | IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n", | |
3010 | changed_flags, *total_flags); | |
3011 | ||
3012 | CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); | |
bdb84fec JB |
3013 | /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */ |
3014 | CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); | |
8b8ab9d5 JB |
3015 | CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); |
3016 | ||
3017 | #undef CHK | |
3018 | ||
3019 | mutex_lock(&priv->mutex); | |
3020 | ||
246ed355 JB |
3021 | for_each_context(priv, ctx) { |
3022 | ctx->staging.filter_flags &= ~filter_nand; | |
3023 | ctx->staging.filter_flags |= filter_or; | |
749ff4ef SG |
3024 | |
3025 | /* | |
3026 | * Not committing directly because hardware can perform a scan, | |
3027 | * but we'll eventually commit the filter flags change anyway. | |
3028 | */ | |
246ed355 | 3029 | } |
8b8ab9d5 JB |
3030 | |
3031 | mutex_unlock(&priv->mutex); | |
3032 | ||
3033 | /* | |
3034 | * Receiving all multicast frames is always enabled by the | |
3035 | * default flags setup in iwl_connection_init_rx_config() | |
3036 | * since we currently do not support programming multicast | |
3037 | * filters into the device. | |
3038 | */ | |
3039 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
3040 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
3041 | } | |
3042 | ||
2dedbf58 | 3043 | static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop) |
716c74b0 WYG |
3044 | { |
3045 | struct iwl_priv *priv = hw->priv; | |
3046 | ||
3047 | mutex_lock(&priv->mutex); | |
3048 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3049 | ||
716c74b0 WYG |
3050 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { |
3051 | IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n"); | |
3052 | goto done; | |
3053 | } | |
3054 | if (iwl_is_rfkill(priv)) { | |
3055 | IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n"); | |
3056 | goto done; | |
3057 | } | |
3058 | ||
3059 | /* | |
3060 | * mac80211 will not push any more frames for transmit | |
3061 | * until the flush is completed | |
3062 | */ | |
3063 | if (drop) { | |
3064 | IWL_DEBUG_MAC80211(priv, "send flush command\n"); | |
c68744fb | 3065 | if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) { |
716c74b0 WYG |
3066 | IWL_ERR(priv, "flush request fail\n"); |
3067 | goto done; | |
3068 | } | |
3069 | } | |
3070 | IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n"); | |
3071 | iwlagn_wait_tx_queue_empty(priv); | |
3072 | done: | |
3073 | mutex_unlock(&priv->mutex); | |
3074 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
3075 | } | |
3076 | ||
9b9190d9 JB |
3077 | static void iwlagn_disable_roc(struct iwl_priv *priv) |
3078 | { | |
3079 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN]; | |
3080 | struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel); | |
3081 | ||
3082 | lockdep_assert_held(&priv->mutex); | |
3083 | ||
3084 | if (!ctx->is_active) | |
3085 | return; | |
3086 | ||
3087 | ctx->staging.dev_type = RXON_DEV_TYPE_2STA; | |
3088 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
3089 | iwl_set_rxon_channel(priv, chan, ctx); | |
3090 | iwl_set_flags_for_band(priv, ctx, chan->band, NULL); | |
3091 | ||
3092 | priv->_agn.hw_roc_channel = NULL; | |
3093 | ||
805a3b81 | 3094 | iwlagn_commit_rxon(priv, ctx); |
9b9190d9 JB |
3095 | |
3096 | ctx->is_active = false; | |
3097 | } | |
3098 | ||
3099 | static void iwlagn_bg_roc_done(struct work_struct *work) | |
3100 | { | |
3101 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
3102 | _agn.hw_roc_work.work); | |
3103 | ||
3104 | mutex_lock(&priv->mutex); | |
3105 | ieee80211_remain_on_channel_expired(priv->hw); | |
3106 | iwlagn_disable_roc(priv); | |
3107 | mutex_unlock(&priv->mutex); | |
3108 | } | |
3109 | ||
3110 | static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw, | |
3111 | struct ieee80211_channel *channel, | |
3112 | enum nl80211_channel_type channel_type, | |
3113 | int duration) | |
3114 | { | |
3115 | struct iwl_priv *priv = hw->priv; | |
3116 | int err = 0; | |
3117 | ||
3118 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | |
3119 | return -EOPNOTSUPP; | |
3120 | ||
3121 | if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes & | |
3122 | BIT(NL80211_IFTYPE_P2P_CLIENT))) | |
3123 | return -EOPNOTSUPP; | |
3124 | ||
3125 | mutex_lock(&priv->mutex); | |
3126 | ||
3127 | if (priv->contexts[IWL_RXON_CTX_PAN].is_active || | |
3128 | test_bit(STATUS_SCAN_HW, &priv->status)) { | |
3129 | err = -EBUSY; | |
3130 | goto out; | |
3131 | } | |
3132 | ||
3133 | priv->contexts[IWL_RXON_CTX_PAN].is_active = true; | |
3134 | priv->_agn.hw_roc_channel = channel; | |
3135 | priv->_agn.hw_roc_chantype = channel_type; | |
3136 | priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024); | |
805a3b81 | 3137 | iwlagn_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]); |
9b9190d9 JB |
3138 | queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work, |
3139 | msecs_to_jiffies(duration + 20)); | |
3140 | ||
94073919 | 3141 | msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */ |
9b9190d9 JB |
3142 | ieee80211_ready_on_channel(priv->hw); |
3143 | ||
3144 | out: | |
3145 | mutex_unlock(&priv->mutex); | |
3146 | ||
3147 | return err; | |
3148 | } | |
3149 | ||
3150 | static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw) | |
3151 | { | |
3152 | struct iwl_priv *priv = hw->priv; | |
3153 | ||
3154 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | |
3155 | return -EOPNOTSUPP; | |
3156 | ||
3157 | cancel_delayed_work_sync(&priv->_agn.hw_roc_work); | |
3158 | ||
3159 | mutex_lock(&priv->mutex); | |
3160 | iwlagn_disable_roc(priv); | |
3161 | mutex_unlock(&priv->mutex); | |
3162 | ||
3163 | return 0; | |
3164 | } | |
3165 | ||
b481de9c ZY |
3166 | /***************************************************************************** |
3167 | * | |
3168 | * driver setup and teardown | |
3169 | * | |
3170 | *****************************************************************************/ | |
3171 | ||
4e39317d | 3172 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3173 | { |
d21050c7 | 3174 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3175 | |
3176 | init_waitqueue_head(&priv->wait_command_queue); | |
3177 | ||
5b9f8cd3 EG |
3178 | INIT_WORK(&priv->restart, iwl_bg_restart); |
3179 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 3180 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 3181 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
65550636 | 3182 | INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush); |
bee008b7 | 3183 | INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency); |
fbba9410 | 3184 | INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config); |
9b9190d9 | 3185 | INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done); |
2a421b91 | 3186 | |
2a421b91 | 3187 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 3188 | |
4e39317d EG |
3189 | if (priv->cfg->ops->lib->setup_deferred_work) |
3190 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3191 | ||
3192 | init_timer(&priv->statistics_periodic); | |
3193 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3194 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 3195 | |
a9e1cb6a WYG |
3196 | init_timer(&priv->ucode_trace); |
3197 | priv->ucode_trace.data = (unsigned long)priv; | |
3198 | priv->ucode_trace.function = iwl_bg_ucode_trace; | |
3199 | ||
22de94de SG |
3200 | init_timer(&priv->watchdog); |
3201 | priv->watchdog.data = (unsigned long)priv; | |
3202 | priv->watchdog.function = iwl_bg_watchdog; | |
b74e31a9 | 3203 | |
d6b80618 WYG |
3204 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) |
3205 | iwl_irq_tasklet, (unsigned long)priv); | |
b481de9c ZY |
3206 | } |
3207 | ||
4e39317d | 3208 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3209 | { |
4e39317d EG |
3210 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3211 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3212 | |
815e629b | 3213 | cancel_work_sync(&priv->run_time_calib_work); |
b481de9c | 3214 | cancel_work_sync(&priv->beacon_update); |
e7e16b90 SG |
3215 | |
3216 | iwl_cancel_scan_deferred_work(priv); | |
3217 | ||
bee008b7 | 3218 | cancel_work_sync(&priv->bt_full_concurrency); |
fbba9410 | 3219 | cancel_work_sync(&priv->bt_runtime_config); |
e7e16b90 | 3220 | |
4e39317d | 3221 | del_timer_sync(&priv->statistics_periodic); |
a9e1cb6a | 3222 | del_timer_sync(&priv->ucode_trace); |
b481de9c ZY |
3223 | } |
3224 | ||
89f186a8 RC |
3225 | static void iwl_init_hw_rates(struct iwl_priv *priv, |
3226 | struct ieee80211_rate *rates) | |
3227 | { | |
3228 | int i; | |
3229 | ||
3230 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { | |
3231 | rates[i].bitrate = iwl_rates[i].ieee * 5; | |
3232 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
3233 | rates[i].hw_value_short = i; | |
3234 | rates[i].flags = 0; | |
3235 | if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) { | |
3236 | /* | |
3237 | * If CCK != 1M then set short preamble rate flag. | |
3238 | */ | |
3239 | rates[i].flags |= | |
3240 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
3241 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
3242 | } | |
3243 | } | |
3244 | } | |
3245 | ||
3246 | static int iwl_init_drv(struct iwl_priv *priv) | |
3247 | { | |
3248 | int ret; | |
3249 | ||
89f186a8 RC |
3250 | spin_lock_init(&priv->sta_lock); |
3251 | spin_lock_init(&priv->hcmd_lock); | |
3252 | ||
89f186a8 RC |
3253 | mutex_init(&priv->mutex); |
3254 | ||
89f186a8 RC |
3255 | priv->ieee_channels = NULL; |
3256 | priv->ieee_rates = NULL; | |
3257 | priv->band = IEEE80211_BAND_2GHZ; | |
3258 | ||
3259 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
ba37a3d0 | 3260 | priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; |
a13d276f | 3261 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
d5a0ffa3 | 3262 | priv->_agn.agg_tids_count = 0; |
89f186a8 | 3263 | |
8a472da4 WYG |
3264 | /* initialize force reset */ |
3265 | priv->force_reset[IWL_RF_RESET].reset_duration = | |
3266 | IWL_DELAY_NEXT_FORCE_RF_RESET; | |
3267 | priv->force_reset[IWL_FW_RESET].reset_duration = | |
3268 | IWL_DELAY_NEXT_FORCE_FW_RELOAD; | |
89f186a8 | 3269 | |
410f2bb3 SG |
3270 | priv->rx_statistics_jiffies = jiffies; |
3271 | ||
89f186a8 RC |
3272 | /* Choose which receivers/antennas to use */ |
3273 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 JB |
3274 | priv->cfg->ops->hcmd->set_rxon_chain(priv, |
3275 | &priv->contexts[IWL_RXON_CTX_BSS]); | |
89f186a8 RC |
3276 | |
3277 | iwl_init_scan_params(priv); | |
3278 | ||
22bf59a0 | 3279 | /* init bt coex */ |
7cb1b088 WYG |
3280 | if (priv->cfg->bt_params && |
3281 | priv->cfg->bt_params->advanced_bt_coexist) { | |
b6e116e8 WYG |
3282 | priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; |
3283 | priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; | |
3284 | priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; | |
22bf59a0 WYG |
3285 | priv->bt_on_thresh = BT_ON_THRESHOLD_DEF; |
3286 | priv->bt_duration = BT_DURATION_LIMIT_DEF; | |
3287 | priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF; | |
22bf59a0 WYG |
3288 | } |
3289 | ||
89f186a8 RC |
3290 | ret = iwl_init_channel_map(priv); |
3291 | if (ret) { | |
3292 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3293 | goto err; | |
3294 | } | |
3295 | ||
3296 | ret = iwlcore_init_geos(priv); | |
3297 | if (ret) { | |
3298 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3299 | goto err_free_channel_map; | |
3300 | } | |
3301 | iwl_init_hw_rates(priv, priv->ieee_rates); | |
3302 | ||
3303 | return 0; | |
3304 | ||
3305 | err_free_channel_map: | |
3306 | iwl_free_channel_map(priv); | |
3307 | err: | |
3308 | return ret; | |
3309 | } | |
3310 | ||
3311 | static void iwl_uninit_drv(struct iwl_priv *priv) | |
3312 | { | |
3313 | iwl_calib_free_results(priv); | |
3314 | iwlcore_free_geos(priv); | |
3315 | iwl_free_channel_map(priv); | |
811ecc99 | 3316 | kfree(priv->scan_cmd); |
4ce7cc2b | 3317 | kfree(priv->beacon_cmd); |
89f186a8 RC |
3318 | } |
3319 | ||
dc21b545 | 3320 | struct ieee80211_ops iwlagn_hw_ops = { |
2295c66b JB |
3321 | .tx = iwlagn_mac_tx, |
3322 | .start = iwlagn_mac_start, | |
3323 | .stop = iwlagn_mac_stop, | |
5b9f8cd3 EG |
3324 | .add_interface = iwl_mac_add_interface, |
3325 | .remove_interface = iwl_mac_remove_interface, | |
d4daaea6 | 3326 | .change_interface = iwl_mac_change_interface, |
2295c66b | 3327 | .config = iwlagn_mac_config, |
8b8ab9d5 | 3328 | .configure_filter = iwlagn_configure_filter, |
2295c66b JB |
3329 | .set_key = iwlagn_mac_set_key, |
3330 | .update_tkip_key = iwlagn_mac_update_tkip_key, | |
5b9f8cd3 | 3331 | .conf_tx = iwl_mac_conf_tx, |
2295c66b JB |
3332 | .bss_info_changed = iwlagn_bss_info_changed, |
3333 | .ampdu_action = iwlagn_mac_ampdu_action, | |
6ab10ff8 | 3334 | .hw_scan = iwl_mac_hw_scan, |
2295c66b | 3335 | .sta_notify = iwlagn_mac_sta_notify, |
fe6b23dd RC |
3336 | .sta_add = iwlagn_mac_sta_add, |
3337 | .sta_remove = iwl_mac_sta_remove, | |
2295c66b JB |
3338 | .channel_switch = iwlagn_mac_channel_switch, |
3339 | .flush = iwlagn_mac_flush, | |
a85d7cca | 3340 | .tx_last_beacon = iwl_mac_tx_last_beacon, |
9b9190d9 JB |
3341 | .remain_on_channel = iwl_mac_remain_on_channel, |
3342 | .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel, | |
266af4c7 JB |
3343 | .offchannel_tx = iwl_mac_offchannel_tx, |
3344 | .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait, | |
4613e72d | 3345 | CFG80211_TESTMODE_CMD(iwl_testmode_cmd) |
eb64dca0 | 3346 | CFG80211_TESTMODE_DUMP(iwl_testmode_dump) |
b481de9c ZY |
3347 | }; |
3348 | ||
e98a1302 | 3349 | static u32 iwl_hw_detect(struct iwl_priv *priv) |
3867fe04 | 3350 | { |
02a7fa00 | 3351 | return iwl_read32(priv, CSR_HW_REV); |
3867fe04 WYG |
3352 | } |
3353 | ||
07d4f1ad WYG |
3354 | static int iwl_set_hw_params(struct iwl_priv *priv) |
3355 | { | |
3356 | priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; | |
3357 | priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
9d143e9a | 3358 | if (iwlagn_mod_params.amsdu_size_8K) |
07d4f1ad WYG |
3359 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K); |
3360 | else | |
3361 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K); | |
3362 | ||
3363 | priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL; | |
3364 | ||
9d143e9a | 3365 | if (iwlagn_mod_params.disable_11n) |
88950758 | 3366 | priv->cfg->sku &= ~EEPROM_SKU_CAP_11N_ENABLE; |
07d4f1ad WYG |
3367 | |
3368 | /* Device-specific setup */ | |
3369 | return priv->cfg->ops->lib->set_hw_params(priv); | |
3370 | } | |
3371 | ||
e72f368b JB |
3372 | static const u8 iwlagn_bss_ac_to_fifo[] = { |
3373 | IWL_TX_FIFO_VO, | |
3374 | IWL_TX_FIFO_VI, | |
3375 | IWL_TX_FIFO_BE, | |
3376 | IWL_TX_FIFO_BK, | |
3377 | }; | |
3378 | ||
3379 | static const u8 iwlagn_bss_ac_to_queue[] = { | |
3380 | 0, 1, 2, 3, | |
3381 | }; | |
3382 | ||
3383 | static const u8 iwlagn_pan_ac_to_fifo[] = { | |
3384 | IWL_TX_FIFO_VO_IPAN, | |
3385 | IWL_TX_FIFO_VI_IPAN, | |
3386 | IWL_TX_FIFO_BE_IPAN, | |
3387 | IWL_TX_FIFO_BK_IPAN, | |
3388 | }; | |
3389 | ||
3390 | static const u8 iwlagn_pan_ac_to_queue[] = { | |
3391 | 7, 6, 5, 4, | |
3392 | }; | |
3393 | ||
119ea186 WYG |
3394 | /* This function both allocates and initializes hw and priv. */ |
3395 | static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg) | |
3396 | { | |
3397 | struct iwl_priv *priv; | |
3398 | /* mac80211 allocates memory for this device instance, including | |
3399 | * space for this driver's private structure */ | |
3400 | struct ieee80211_hw *hw; | |
3401 | ||
3402 | hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops); | |
3403 | if (hw == NULL) { | |
3404 | pr_err("%s: Can not allocate network device\n", | |
3405 | cfg->name); | |
3406 | goto out; | |
3407 | } | |
3408 | ||
3409 | priv = hw->priv; | |
3410 | priv->hw = hw; | |
3411 | ||
3412 | out: | |
3413 | return hw; | |
3414 | } | |
3415 | ||
b2ea345e | 3416 | static void iwl_init_context(struct iwl_priv *priv) |
b481de9c | 3417 | { |
b2ea345e | 3418 | int i; |
1d0a082d | 3419 | |
246ed355 JB |
3420 | /* |
3421 | * The default context is always valid, | |
3422 | * more may be discovered when firmware | |
3423 | * is loaded. | |
3424 | */ | |
3425 | priv->valid_contexts = BIT(IWL_RXON_CTX_BSS); | |
3426 | ||
3427 | for (i = 0; i < NUM_IWL_RXON_CTX; i++) | |
3428 | priv->contexts[i].ctxid = i; | |
3429 | ||
763cc3bf JB |
3430 | priv->contexts[IWL_RXON_CTX_BSS].always_active = true; |
3431 | priv->contexts[IWL_RXON_CTX_BSS].is_active = true; | |
8f2d3d2a JB |
3432 | priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON; |
3433 | priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING; | |
3434 | priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC; | |
8dfdb9d5 | 3435 | priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM; |
2995bafa | 3436 | priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID; |
c10afb6e | 3437 | priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY; |
e72f368b JB |
3438 | priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo; |
3439 | priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue; | |
d0fe478c JB |
3440 | priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes = |
3441 | BIT(NL80211_IFTYPE_ADHOC); | |
3442 | priv->contexts[IWL_RXON_CTX_BSS].interface_modes = | |
3443 | BIT(NL80211_IFTYPE_STATION); | |
2295c66b | 3444 | priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP; |
d0fe478c JB |
3445 | priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS; |
3446 | priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS; | |
3447 | priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS; | |
ece9c4ee JB |
3448 | |
3449 | priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON; | |
b2ea345e WYG |
3450 | priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = |
3451 | REPLY_WIPAN_RXON_TIMING; | |
3452 | priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = | |
3453 | REPLY_WIPAN_RXON_ASSOC; | |
ece9c4ee JB |
3454 | priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM; |
3455 | priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN; | |
3456 | priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY; | |
3457 | priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID; | |
3458 | priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION; | |
e72f368b JB |
3459 | priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo; |
3460 | priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue; | |
3461 | priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE; | |
d0fe478c JB |
3462 | priv->contexts[IWL_RXON_CTX_PAN].interface_modes = |
3463 | BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP); | |
f35c0c56 WYG |
3464 | #ifdef CONFIG_IWL_P2P |
3465 | priv->contexts[IWL_RXON_CTX_PAN].interface_modes |= | |
3466 | BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO); | |
3467 | #endif | |
d0fe478c JB |
3468 | priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP; |
3469 | priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA; | |
3470 | priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P; | |
ece9c4ee JB |
3471 | |
3472 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); | |
b2ea345e WYG |
3473 | } |
3474 | ||
a48709c5 EG |
3475 | int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops, |
3476 | struct iwl_cfg *cfg) | |
b2ea345e WYG |
3477 | { |
3478 | int err = 0; | |
3479 | struct iwl_priv *priv; | |
3480 | struct ieee80211_hw *hw; | |
084dd791 | 3481 | u16 num_mac; |
b2ea345e WYG |
3482 | u32 hw_rev; |
3483 | ||
3484 | /************************ | |
3485 | * 1. Allocating HW data | |
3486 | ************************/ | |
b2ea345e WYG |
3487 | hw = iwl_alloc_all(cfg); |
3488 | if (!hw) { | |
3489 | err = -ENOMEM; | |
807caf26 EG |
3490 | goto out; |
3491 | } | |
3492 | ||
b2ea345e | 3493 | priv = hw->priv; |
a48709c5 EG |
3494 | |
3495 | priv->bus.priv = priv; | |
3496 | priv->bus.bus_specific = bus_specific; | |
3497 | priv->bus.ops = bus_ops; | |
705cd451 | 3498 | priv->bus.irq = priv->bus.ops->get_irq(&priv->bus); |
a48709c5 | 3499 | priv->bus.ops->set_drv_data(&priv->bus, priv); |
3599d39a | 3500 | priv->bus.dev = priv->bus.ops->get_dev(&priv->bus); |
a48709c5 | 3501 | |
b2ea345e | 3502 | /* At this point both hw and priv are allocated. */ |
8f2d3d2a | 3503 | |
3599d39a | 3504 | SET_IEEE80211_DEV(hw, priv->bus.dev); |
b481de9c | 3505 | |
e1623446 | 3506 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 3507 | priv->cfg = cfg; |
40cefda9 | 3508 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 3509 | |
bee008b7 WYG |
3510 | /* is antenna coupling more than 35dB ? */ |
3511 | priv->bt_ant_couple_ok = | |
3512 | (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ? | |
3513 | true : false; | |
3514 | ||
9f28ebc3 | 3515 | /* enable/disable bt channel inhibition */ |
f37837c9 | 3516 | priv->bt_ch_announce = iwlagn_bt_ch_announce; |
9f28ebc3 WYG |
3517 | IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n", |
3518 | (priv->bt_ch_announce) ? "On" : "Off"); | |
f37837c9 | 3519 | |
20594eb0 WYG |
3520 | if (iwl_alloc_traffic_mem(priv)) |
3521 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 3522 | |
316c30d9 | 3523 | |
731a29b7 | 3524 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
3525 | * we should init now |
3526 | */ | |
3527 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 3528 | spin_lock_init(&priv->lock); |
4843b5a7 RC |
3529 | |
3530 | /* | |
3531 | * stop and reset the on-board processor just in case it is in a | |
3532 | * strange state ... like being left stranded by a primary kernel | |
3533 | * and this is now the kdump kernel trying to start up | |
3534 | */ | |
3535 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
3536 | ||
084dd791 EG |
3537 | /*********************** |
3538 | * 3. Read REV register | |
3539 | ***********************/ | |
e98a1302 | 3540 | hw_rev = iwl_hw_detect(priv); |
c11362c0 | 3541 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", |
e98a1302 | 3542 | priv->cfg->name, hw_rev); |
316c30d9 | 3543 | |
4cd2bf76 | 3544 | if (iwl_prepare_card_hw(priv)) { |
bcd4fe2f | 3545 | err = -EIO; |
086ed117 | 3546 | IWL_WARN(priv, "Failed, HW not ready\n"); |
084dd791 | 3547 | goto out_free_traffic_mem; |
086ed117 MA |
3548 | } |
3549 | ||
91238714 TW |
3550 | /***************** |
3551 | * 4. Read EEPROM | |
3552 | *****************/ | |
316c30d9 | 3553 | /* Read the EEPROM */ |
e98a1302 | 3554 | err = iwl_eeprom_init(priv, hw_rev); |
316c30d9 | 3555 | if (err) { |
15b1687c | 3556 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
084dd791 | 3557 | goto out_free_traffic_mem; |
316c30d9 | 3558 | } |
8614f360 TW |
3559 | err = iwl_eeprom_check_version(priv); |
3560 | if (err) | |
c8f16138 | 3561 | goto out_free_eeprom; |
8614f360 | 3562 | |
21a5b3c6 WYG |
3563 | err = iwl_eeprom_check_sku(priv); |
3564 | if (err) | |
3565 | goto out_free_eeprom; | |
3566 | ||
02883017 | 3567 | /* extract MAC Address */ |
c6fa17ed WYG |
3568 | iwl_eeprom_get_mac(priv, priv->addresses[0].addr); |
3569 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr); | |
3570 | priv->hw->wiphy->addresses = priv->addresses; | |
3571 | priv->hw->wiphy->n_addresses = 1; | |
3572 | num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS); | |
3573 | if (num_mac > 1) { | |
3574 | memcpy(priv->addresses[1].addr, priv->addresses[0].addr, | |
3575 | ETH_ALEN); | |
3576 | priv->addresses[1].addr[5]++; | |
3577 | priv->hw->wiphy->n_addresses++; | |
3578 | } | |
316c30d9 | 3579 | |
b2ea345e WYG |
3580 | /* initialize all valid contexts */ |
3581 | iwl_init_context(priv); | |
3582 | ||
316c30d9 AK |
3583 | /************************ |
3584 | * 5. Setup HW constants | |
3585 | ************************/ | |
da154e30 | 3586 | if (iwl_set_hw_params(priv)) { |
084dd791 | 3587 | err = -ENOENT; |
15b1687c | 3588 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 3589 | goto out_free_eeprom; |
316c30d9 AK |
3590 | } |
3591 | ||
3592 | /******************* | |
6ba87956 | 3593 | * 6. Setup priv |
316c30d9 | 3594 | *******************/ |
b481de9c | 3595 | |
6ba87956 | 3596 | err = iwl_init_drv(priv); |
bf85ea4f | 3597 | if (err) |
399f4900 | 3598 | goto out_free_eeprom; |
bf85ea4f | 3599 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 3600 | |
316c30d9 | 3601 | /******************** |
09f9bf79 | 3602 | * 7. Setup services |
316c30d9 | 3603 | ********************/ |
519d8abd | 3604 | iwl_alloc_isr_ict(priv); |
e39fdee1 | 3605 | |
705cd451 EG |
3606 | err = request_irq(priv->bus.irq, iwl_isr_ict, IRQF_SHARED, |
3607 | DRV_NAME, priv); | |
6cd0b1cb | 3608 | if (err) { |
705cd451 | 3609 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->bus.irq); |
084dd791 | 3610 | goto out_uninit_drv; |
6cd0b1cb | 3611 | } |
316c30d9 | 3612 | |
4e39317d | 3613 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3614 | iwl_setup_rx_handlers(priv); |
4613e72d | 3615 | iwl_testmode_init(priv); |
316c30d9 | 3616 | |
158bea07 | 3617 | /********************************************* |
084dd791 | 3618 | * 8. Enable interrupts |
158bea07 | 3619 | *********************************************/ |
6ba87956 | 3620 | |
554d1d02 | 3621 | iwl_enable_rfkill_int(priv); |
6cd0b1cb | 3622 | |
6cd0b1cb HS |
3623 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3624 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3625 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3626 | else | |
3627 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3628 | |
a60e77e5 JB |
3629 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
3630 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 3631 | |
58d0f361 | 3632 | iwl_power_initialize(priv); |
39b73fb1 | 3633 | iwl_tt_initialize(priv); |
158bea07 | 3634 | |
a15707d8 | 3635 | init_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 3636 | |
b08dfd04 | 3637 | err = iwl_request_firmware(priv, true); |
158bea07 | 3638 | if (err) |
7d47618a | 3639 | goto out_destroy_workqueue; |
158bea07 | 3640 | |
b481de9c ZY |
3641 | return 0; |
3642 | ||
7d47618a | 3643 | out_destroy_workqueue: |
c8f16138 RC |
3644 | destroy_workqueue(priv->workqueue); |
3645 | priv->workqueue = NULL; | |
705cd451 | 3646 | free_irq(priv->bus.irq, priv); |
93cce6f0 | 3647 | iwl_free_isr_ict(priv); |
084dd791 | 3648 | out_uninit_drv: |
6ba87956 | 3649 | iwl_uninit_drv(priv); |
073d3f5f TW |
3650 | out_free_eeprom: |
3651 | iwl_eeprom_free(priv); | |
084dd791 | 3652 | out_free_traffic_mem: |
20594eb0 | 3653 | iwl_free_traffic_mem(priv); |
d7c76f4c | 3654 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
3655 | out: |
3656 | return err; | |
3657 | } | |
3658 | ||
a48709c5 | 3659 | void __devexit iwl_remove(struct iwl_priv * priv) |
b481de9c | 3660 | { |
0359facc | 3661 | unsigned long flags; |
b481de9c | 3662 | |
a15707d8 | 3663 | wait_for_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 3664 | |
e1623446 | 3665 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 3666 | |
67249625 | 3667 | iwl_dbgfs_unregister(priv); |
3599d39a EG |
3668 | sysfs_remove_group(&priv->bus.dev->kobj, |
3669 | &iwl_attribute_group); | |
67249625 | 3670 | |
5b9f8cd3 EG |
3671 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
3672 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
3673 | * we need to set STATUS_EXIT_PENDING bit. |
3674 | */ | |
3675 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5ed540ae | 3676 | |
7a4e5281 | 3677 | iwl_testmode_cleanup(priv); |
5ed540ae WYG |
3678 | iwl_leds_exit(priv); |
3679 | ||
c4f55232 RR |
3680 | if (priv->mac80211_registered) { |
3681 | ieee80211_unregister_hw(priv->hw); | |
3682 | priv->mac80211_registered = 0; | |
3683 | } | |
3684 | ||
1a10f433 | 3685 | /* Reset to low power before unloading driver. */ |
14e8e4af | 3686 | iwl_apm_stop(priv); |
c166b25a | 3687 | |
39b73fb1 WYG |
3688 | iwl_tt_exit(priv); |
3689 | ||
0359facc MA |
3690 | /* make sure we flush any pending irq or |
3691 | * tasklet for the driver | |
3692 | */ | |
3693 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 3694 | iwl_disable_interrupts(priv); |
0359facc MA |
3695 | spin_unlock_irqrestore(&priv->lock, flags); |
3696 | ||
3697 | iwl_synchronize_irq(priv); | |
3698 | ||
3599d39a | 3699 | iwl_dealloc_ucode(priv); |
b481de9c ZY |
3700 | |
3701 | if (priv->rxq.bd) | |
54b81550 | 3702 | iwlagn_rx_queue_free(priv, &priv->rxq); |
74bcdb33 | 3703 | iwlagn_hw_txq_ctx_free(priv); |
b481de9c | 3704 | |
073d3f5f | 3705 | iwl_eeprom_free(priv); |
b481de9c | 3706 | |
b481de9c | 3707 | |
948c171c MA |
3708 | /*netif_stop_queue(dev); */ |
3709 | flush_workqueue(priv->workqueue); | |
3710 | ||
5b9f8cd3 | 3711 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3712 | * priv->workqueue... so we can't take down the workqueue |
3713 | * until now... */ | |
3714 | destroy_workqueue(priv->workqueue); | |
3715 | priv->workqueue = NULL; | |
20594eb0 | 3716 | iwl_free_traffic_mem(priv); |
b481de9c | 3717 | |
705cd451 | 3718 | free_irq(priv->bus.irq, priv); |
a48709c5 | 3719 | priv->bus.ops->set_drv_data(&priv->bus, NULL); |
b481de9c | 3720 | |
6ba87956 | 3721 | iwl_uninit_drv(priv); |
b481de9c | 3722 | |
519d8abd | 3723 | iwl_free_isr_ict(priv); |
ef850d7c | 3724 | |
77834543 | 3725 | dev_kfree_skb(priv->beacon_skb); |
b481de9c ZY |
3726 | |
3727 | ieee80211_free_hw(priv->hw); | |
3728 | } | |
3729 | ||
b481de9c ZY |
3730 | |
3731 | /***************************************************************************** | |
3732 | * | |
3733 | * driver and module entry point | |
3734 | * | |
3735 | *****************************************************************************/ | |
5b9f8cd3 | 3736 | static int __init iwl_init(void) |
b481de9c ZY |
3737 | { |
3738 | ||
3739 | int ret; | |
c96c31e4 JP |
3740 | pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); |
3741 | pr_info(DRV_COPYRIGHT "\n"); | |
897e1cf2 | 3742 | |
e227ceac | 3743 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 3744 | if (ret) { |
c96c31e4 | 3745 | pr_err("Unable to register rate control algorithm: %d\n", ret); |
897e1cf2 RC |
3746 | return ret; |
3747 | } | |
3748 | ||
48d1a211 | 3749 | ret = iwl_pci_register_driver(); |
b481de9c | 3750 | |
48d1a211 EG |
3751 | if (ret) |
3752 | goto error_register; | |
b481de9c | 3753 | return ret; |
897e1cf2 | 3754 | |
897e1cf2 | 3755 | error_register: |
e227ceac | 3756 | iwlagn_rate_control_unregister(); |
897e1cf2 | 3757 | return ret; |
b481de9c ZY |
3758 | } |
3759 | ||
5b9f8cd3 | 3760 | static void __exit iwl_exit(void) |
b481de9c | 3761 | { |
48d1a211 | 3762 | iwl_pci_unregister_driver(); |
e227ceac | 3763 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
3764 | } |
3765 | ||
5b9f8cd3 EG |
3766 | module_exit(iwl_exit); |
3767 | module_init(iwl_init); | |
a562a9dd RC |
3768 | |
3769 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 3770 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
3771 | MODULE_PARM_DESC(debug, "debug output mask"); |
3772 | #endif | |
3773 | ||
2b068618 WYG |
3774 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); |
3775 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | |
2b068618 WYG |
3776 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); |
3777 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | |
2b068618 WYG |
3778 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); |
3779 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | |
2b068618 WYG |
3780 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, |
3781 | int, S_IRUGO); | |
3782 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
2b068618 WYG |
3783 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); |
3784 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | |
dd7a2509 JB |
3785 | |
3786 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, | |
3787 | S_IRUGO); | |
3788 | MODULE_PARM_DESC(ucode_alternative, | |
3789 | "specify ucode alternative to use from ucode file"); | |
bee008b7 WYG |
3790 | |
3791 | module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO); | |
3792 | MODULE_PARM_DESC(antenna_coupling, | |
3793 | "specify antenna coupling in dB (defualt: 0 dB)"); | |
f37837c9 | 3794 | |
9f28ebc3 WYG |
3795 | module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO); |
3796 | MODULE_PARM_DESC(bt_ch_inhibition, | |
3797 | "Disable BT channel inhibition (default: enable)"); | |
b7977ffa SG |
3798 | |
3799 | module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO); | |
3800 | MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])"); | |
3801 | ||
3802 | module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO); | |
3803 | MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])"); | |
b60eec9b WYG |
3804 | |
3805 | /* | |
3806 | * set bt_coex_active to true, uCode will do kill/defer | |
3807 | * every time the priority line is asserted (BT is sending signals on the | |
3808 | * priority line in the PCIx). | |
3809 | * set bt_coex_active to false, uCode will ignore the BT activity and | |
3810 | * perform the normal operation | |
3811 | * | |
3812 | * User might experience transmit issue on some platform due to WiFi/BT | |
3813 | * co-exist problem. The possible behaviors are: | |
3814 | * Able to scan and finding all the available AP | |
3815 | * Not able to associate with any AP | |
3816 | * On those platforms, WiFi communication can be restored by set | |
3817 | * "bt_coex_active" module parameter to "false" | |
3818 | * | |
3819 | * default: bt_coex_active = true (BT_COEX_ENABLE) | |
3820 | */ | |
3821 | module_param_named(bt_coex_active, iwlagn_mod_params.bt_coex_active, | |
3822 | bool, S_IRUGO); | |
3823 | MODULE_PARM_DESC(bt_coex_active, "enable wifi/bt co-exist (default: enable)"); | |
6b0184c4 WYG |
3824 | |
3825 | module_param_named(led_mode, iwlagn_mod_params.led_mode, int, S_IRUGO); | |
3826 | MODULE_PARM_DESC(led_mode, "0=system default, " | |
3827 | "1=On(RF On)/Off(RF Off), 2=blinking (default: 0)"); | |
3f1e5f4a | 3828 | |
0172b029 WYG |
3829 | module_param_named(power_save, iwlagn_mod_params.power_save, |
3830 | bool, S_IRUGO); | |
3831 | MODULE_PARM_DESC(power_save, | |
3832 | "enable WiFi power management (default: disable)"); | |
3833 | ||
3f1e5f4a WYG |
3834 | /* |
3835 | * For now, keep using power level 1 instead of automatically | |
3836 | * adjusting ... | |
3837 | */ | |
3838 | module_param_named(no_sleep_autoadjust, iwlagn_mod_params.no_sleep_autoadjust, | |
3839 | bool, S_IRUGO); | |
3840 | MODULE_PARM_DESC(no_sleep_autoadjust, | |
3841 | "don't automatically adjust sleep level " | |
3842 | "according to maximum network latency (default: true)"); |