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iwlagn: send beacon before committing associated RXON
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY		 34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY		 38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY		 41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY		 45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY		 48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO		 52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
f0832f13 60#include "iwl-calib.h"
a1175124 61#include "iwl-agn.h"
b481de9c 62
416e1438 63
b481de9c
ZY		 64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
b481de9c
ZY		 70/*
71 * module name, copyright, version, etc.
b481de9c 72 */
d783b061 73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 74
0a6857e7 75#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 76#define VD "d"
77#else
78#define VD
79#endif
80
81963d68 81#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 82
b481de9c
ZY		 83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
bee008b7 90static int iwlagn_ant_coupling;
f37837c9 91static bool iwlagn_bt_ch_announce = 1;
bee008b7 92
b481de9c 93/**
5b9f8cd3 94 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 95 *
01ebd063 96 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 97 * the active_rxon structure is updated with the new data. This
98 * function correctly transitions out of the RXON_ASSOC_MSK state if
99 * a HW tune is required based on the RXON structure changes.
100 */
246ed355 101int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
b481de9c
ZY		 102{
103 /* cast away the const for active_rxon in this function */
246ed355 104 struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
43d59b32
EG		 105 int ret;
106 bool new_assoc =
246ed355 107 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 108
fee1247a 109 if (!iwl_is_alive(priv))
43d59b32 110 return -EBUSY;
b481de9c
ZY		 111
112 /* always get timestamp with Rx frame */
246ed355 113 ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
b481de9c 114
246ed355 115 ret = iwl_check_rxon_cmd(priv, ctx);
43d59b32 116 if (ret) {
15b1687c 117 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 118 return -EINVAL;
119 }
120
0924e519
WYG		 121 /*
122 * receive commit_rxon request
123 * abort any previous channel switch if still in process
124 */
125 if (priv->switch_rxon.switch_in_progress &&
246ed355 126 (priv->switch_rxon.channel != ctx->staging.channel)) {
0924e519
WYG		 127 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
128 le16_to_cpu(priv->switch_rxon.channel));
79d07325 129 iwl_chswitch_done(priv, false);
0924e519
WYG		 130 }
131
b481de9c 132 /* If we don't need to send a full RXON, we can use
5b9f8cd3 133 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 134 * and other flags for the current radio configuration. */
246ed355
JB		 135 if (!iwl_full_rxon_required(priv, ctx)) {
136 ret = iwl_send_rxon_assoc(priv, ctx);
43d59b32 137 if (ret) {
15b1687c 138 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 139 return ret;
b481de9c
ZY		 140 }
141
246ed355
JB		 142 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
143 iwl_print_rx_config_cmd(priv, ctx);
b481de9c
ZY		 144 return 0;
145 }
146
b481de9c
ZY		 147 /* If we are currently associated and the new config requires
148 * an RXON_ASSOC and the new config wants the associated mask enabled,
149 * we must clear the associated from the active configuration
150 * before we apply the new config */
246ed355 151 if (iwl_is_associated_ctx(ctx) && new_assoc) {
e1623446 152 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 153 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
154
8f2d3d2a 155 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355
JB		 156 sizeof(struct iwl_rxon_cmd),
157 active_rxon);
b481de9c
ZY		 158
159 /* If the mask clearing failed then we set
160 * active_rxon back to what it was previously */
43d59b32 161 if (ret) {
b481de9c 162 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 163 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 164 return ret;
b481de9c 165 }
dcef732c
JB		 166 iwl_clear_ucode_stations(priv, ctx);
167 iwl_restore_stations(priv, ctx);
c10afb6e 168 ret = iwl_restore_default_wep_keys(priv, ctx);
335348b1
JB		 169 if (ret) {
170 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
171 return ret;
172 }
b481de9c
ZY		 173 }
174
e1623446 175 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 176 "* with%s RXON_FILTER_ASSOC_MSK\n"
177 "* channel = %d\n"
e174961c 178 "* bssid = %pM\n",
43d59b32 179 (new_assoc ? "" : "out"),
246ed355
JB		 180 le16_to_cpu(ctx->staging.channel),
181 ctx->staging.bssid_addr);
b481de9c 182
246ed355 183 iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
43d59b32 184
2491fa42
JB		 185 if (new_assoc) {
186 if (WARN_ON(!ctx->vif))
187 return -EINVAL;
188 /*
189 * First of all, before setting associated, we need to
190 * send RXON timing so the device knows about the DTIM
191 * period and other timing values
192 */
193 ret = iwl_send_rxon_timing(priv, ctx->vif);
194 if (ret) {
195 IWL_ERR(priv, "Error setting RXON timing!\n");
196 return ret;
197 }
198 }
199
43d59b32 200 /* Apply the new configuration
7e246191
RC		 201 * RXON unassoc clears the station table in uCode so restoration of
202 * stations is needed after it (the RXON command) completes
43d59b32
EG		 203 */
204 if (!new_assoc) {
8f2d3d2a 205 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 206 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 207 if (ret) {
15b1687c 208 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 209 return ret;
210 }
91dd6c27 211 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
246ed355 212 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
dcef732c
JB		 213 iwl_clear_ucode_stations(priv, ctx);
214 iwl_restore_stations(priv, ctx);
c10afb6e 215 ret = iwl_restore_default_wep_keys(priv, ctx);
335348b1
JB		 216 if (ret) {
217 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
218 return ret;
219 }
b481de9c
ZY		 220 }
221
19cc1087 222 priv->start_calib = 0;
9185159d 223 if (new_assoc) {
43d59b32
EG		 224 /* Apply the new configuration
225 * RXON assoc doesn't clear the station table in uCode,
226 */
8f2d3d2a 227 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 228 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 229 if (ret) {
15b1687c 230 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 231 return ret;
232 }
246ed355 233 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
b481de9c 234 }
246ed355 235 iwl_print_rx_config_cmd(priv, ctx);
b481de9c 236
36da7d70
ZY		 237 iwl_init_sensitivity(priv);
238
239 /* If we issue a new RXON command which required a tune then we must
240 * send a new TXPOWER command or we won't be able to Tx any frames */
241 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
242 if (ret) {
15b1687c 243 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 244 return ret;
245 }
246
b481de9c
ZY		 247 return 0;
248}
249
5b9f8cd3 250void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f 251{
246ed355 252 struct iwl_rxon_context *ctx;
5da4b55f 253
246ed355
JB		 254 if (priv->cfg->ops->hcmd->set_rxon_chain) {
255 for_each_context(priv, ctx) {
256 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
257 iwlcore_commit_rxon(priv, ctx);
258 }
259 }
5da4b55f
MA		 260}
261
fcab423d 262static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 263{
264 struct list_head *element;
265
e1623446 266 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 267 priv->frames_count);
268
269 while (!list_empty(&priv->free_frames)) {
270 element = priv->free_frames.next;
271 list_del(element);
fcab423d 272 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 273 priv->frames_count--;
274 }
275
276 if (priv->frames_count) {
39aadf8c 277 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 278 priv->frames_count);
279 priv->frames_count = 0;
280 }
281}
282
fcab423d 283static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 284{
fcab423d 285 struct iwl_frame *frame;
b481de9c
ZY		 286 struct list_head *element;
287 if (list_empty(&priv->free_frames)) {
288 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
289 if (!frame) {
15b1687c 290 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 291 return NULL;
292 }
293
294 priv->frames_count++;
295 return frame;
296 }
297
298 element = priv->free_frames.next;
299 list_del(element);
fcab423d 300 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 301}
302
fcab423d 303static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 304{
305 memset(frame, 0, sizeof(*frame));
306 list_add(&frame->list, &priv->free_frames);
307}
308
47ff65c4 309static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 310 struct ieee80211_hdr *hdr,
73ec1cc2 311 int left)
b481de9c 312{
6abbe554 313 if (!priv->ibss_beacon)
b481de9c
ZY		 314 return 0;
315
316 if (priv->ibss_beacon->len > left)
317 return 0;
318
319 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
320
321 return priv->ibss_beacon->len;
322}
323
47ff65c4
DH		 324/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
325static void iwl_set_beacon_tim(struct iwl_priv *priv,
326 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
327 u8 *beacon, u32 frame_size)
328{
329 u16 tim_idx;
330 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
331
332 /*
333 * The index is relative to frame start but we start looking at the
334 * variable-length part of the beacon.
335 */
336 tim_idx = mgmt->u.beacon.variable - beacon;
337
338 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
339 while ((tim_idx < (frame_size - 2)) &&
340 (beacon[tim_idx] != WLAN_EID_TIM))
341 tim_idx += beacon[tim_idx+1] + 2;
342
343 /* If TIM field was found, set variables */
344 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
345 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
346 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
347 } else
348 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
349}
350
5b9f8cd3 351static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 352 struct iwl_frame *frame)
4bf64efd
TW		 353{
354 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 355 u32 frame_size;
356 u32 rate_flags;
357 u32 rate;
358 /*
359 * We have to set up the TX command, the TX Beacon command, and the
360 * beacon contents.
361 */
4bf64efd 362
76d04815
JB		 363 lockdep_assert_held(&priv->mutex);
364
365 if (!priv->beacon_ctx) {
366 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
367 return -EINVAL;
368 }
369
47ff65c4 370 /* Initialize memory */
4bf64efd
TW		 371 tx_beacon_cmd = &frame->u.beacon;
372 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
373
47ff65c4 374 /* Set up TX beacon contents */
4bf64efd 375 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 376 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 377 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
378 return 0;
4bf64efd 379
47ff65c4 380 /* Set up TX command fields */
4bf64efd 381 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
76d04815 382 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
47ff65c4
DH		 383 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
384 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
385 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 386
47ff65c4
DH		 387 /* Set up TX beacon command fields */
388 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
389 frame_size);
4bf64efd 390
47ff65c4 391 /* Set up packet rate and flags */
76d04815 392 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
0e1654fa
JB		 393 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
394 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 395 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
396 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
397 rate_flags |= RATE_MCS_CCK_MSK;
398 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
399 rate_flags);
4bf64efd
TW		 400
401 return sizeof(*tx_beacon_cmd) + frame_size;
402}
5b9f8cd3 403static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 404{
fcab423d 405 struct iwl_frame *frame;
b481de9c
ZY		 406 unsigned int frame_size;
407 int rc;
b481de9c 408
fcab423d 409 frame = iwl_get_free_frame(priv);
b481de9c 410 if (!frame) {
15b1687c 411 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 412 "command.\n");
413 return -ENOMEM;
414 }
415
47ff65c4
DH		 416 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
417 if (!frame_size) {
418 IWL_ERR(priv, "Error configuring the beacon command\n");
419 iwl_free_frame(priv, frame);
420 return -EINVAL;
421 }
b481de9c 422
857485c0 423 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 424 &frame->u.cmd[0]);
425
fcab423d 426 iwl_free_frame(priv, frame);
b481de9c
ZY		 427
428 return rc;
429}
430
7aaa1d79
SO		 431static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
432{
433 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
434
435 dma_addr_t addr = get_unaligned_le32(&tb->lo);
436 if (sizeof(dma_addr_t) > sizeof(u32))
437 addr |=
438 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
439
440 return addr;
441}
442
443static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
444{
445 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
446
447 return le16_to_cpu(tb->hi_n_len) >> 4;
448}
449
450static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
451 dma_addr_t addr, u16 len)
452{
453 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
454 u16 hi_n_len = len << 4;
455
456 put_unaligned_le32(addr, &tb->lo);
457 if (sizeof(dma_addr_t) > sizeof(u32))
458 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
459
460 tb->hi_n_len = cpu_to_le16(hi_n_len);
461
462 tfd->num_tbs = idx + 1;
463}
464
465static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
466{
467 return tfd->num_tbs & 0x1f;
468}
469
470/**
471 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
472 * @priv - driver private data
473 * @txq - tx queue
474 *
475 * Does NOT advance any TFD circular buffer read/write indexes
476 * Does NOT free the TFD itself (which is within circular buffer)
477 */
478void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
479{
59606ffa 480 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 481 struct iwl_tfd *tfd;
482 struct pci_dev *dev = priv->pci_dev;
483 int index = txq->q.read_ptr;
484 int i;
485 int num_tbs;
486
487 tfd = &tfd_tmp[index];
488
489 /* Sanity check on number of chunks */
490 num_tbs = iwl_tfd_get_num_tbs(tfd);
491
492 if (num_tbs >= IWL_NUM_OF_TBS) {
493 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
494 /* @todo issue fatal error, it is quite serious situation */
495 return;
496 }
497
498 /* Unmap tx_cmd */
499 if (num_tbs)
500 pci_unmap_single(dev,
2e724443
FT		 501 dma_unmap_addr(&txq->meta[index], mapping),
502 dma_unmap_len(&txq->meta[index], len),
96891cee 503 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 504
505 /* Unmap chunks, if any. */
ff0d91c3 506 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 507 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
508 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
509
ff0d91c3
JB		 510 /* free SKB */
511 if (txq->txb) {
512 struct sk_buff *skb;
6f80240e 513
ff0d91c3 514 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 515
ff0d91c3
JB		 516 /* can be called from irqs-disabled context */
517 if (skb) {
518 dev_kfree_skb_any(skb);
519 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 520 }
521 }
522}
523
524int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
525 struct iwl_tx_queue *txq,
526 dma_addr_t addr, u16 len,
527 u8 reset, u8 pad)
528{
529 struct iwl_queue *q;
59606ffa 530 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 531 u32 num_tbs;
532
533 q = &txq->q;
59606ffa
SO		 534 tfd_tmp = (struct iwl_tfd *)txq->tfds;
535 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 536
537 if (reset)
538 memset(tfd, 0, sizeof(*tfd));
539
540 num_tbs = iwl_tfd_get_num_tbs(tfd);
541
542 /* Each TFD can point to a maximum 20 Tx buffers */
543 if (num_tbs >= IWL_NUM_OF_TBS) {
544 IWL_ERR(priv, "Error can not send more than %d chunks\n",
545 IWL_NUM_OF_TBS);
546 return -EINVAL;
547 }
548
549 BUG_ON(addr & ~DMA_BIT_MASK(36));
550 if (unlikely(addr & ~IWL_TX_DMA_MASK))
551 IWL_ERR(priv, "Unaligned address = %llx\n",
552 (unsigned long long)addr);
553
554 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
555
556 return 0;
557}
558
a8e74e27
SO		 559/*
560 * Tell nic where to find circular buffer of Tx Frame Descriptors for
561 * given Tx queue, and enable the DMA channel used for that queue.
562 *
563 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
564 * channels supported in hardware.
565 */
566int iwl_hw_tx_queue_init(struct iwl_priv *priv,
567 struct iwl_tx_queue *txq)
568{
a8e74e27
SO		 569 int txq_id = txq->q.id;
570
a8e74e27
SO		 571 /* Circular buffer (TFD queue in DRAM) physical base address */
572 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
573 txq->q.dma_addr >> 8);
574
a8e74e27
SO		 575 return 0;
576}
577
b481de9c
ZY		 578/******************************************************************************
579 *
580 * Generic RX handler implementations
581 *
582 ******************************************************************************/
885ba202
TW		 583static void iwl_rx_reply_alive(struct iwl_priv *priv,
584 struct iwl_rx_mem_buffer *rxb)
b481de9c 585{
2f301227 586 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 587 struct iwl_alive_resp *palive;
b481de9c
ZY		 588 struct delayed_work *pwork;
589
590 palive = &pkt->u.alive_frame;
591
e1623446 592 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 593 "0x%01X 0x%01X\n",
594 palive->is_valid, palive->ver_type,
595 palive->ver_subtype);
596
597 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 598 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 599 memcpy(&priv->card_alive_init,
600 &pkt->u.alive_frame,
885ba202 601 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 602 pwork = &priv->init_alive_start;
603 } else {
e1623446 604 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 605 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 606 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 607 pwork = &priv->alive_start;
608 }
609
610 /* We delay the ALIVE response by 5ms to
611 * give the HW RF Kill time to activate... */
612 if (palive->is_valid == UCODE_VALID_OK)
613 queue_delayed_work(priv->workqueue, pwork,
614 msecs_to_jiffies(5));
615 else
39aadf8c 616 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 617}
618
5b9f8cd3 619static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 620{
c79dd5b5
TW		 621 struct iwl_priv *priv =
622 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 623 struct sk_buff *beacon;
624
76d04815
JB		 625 mutex_lock(&priv->mutex);
626 if (!priv->beacon_ctx) {
627 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
628 goto out;
629 }
b481de9c 630
60744f62
JB		 631 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
632 /*
633 * The ucode will send beacon notifications even in
634 * IBSS mode, but we don't want to process them. But
635 * we need to defer the type check to here due to
636 * requiring locking around the beacon_ctx access.
637 */
638 goto out;
639 }
640
76d04815
JB		 641 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
642 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
b481de9c 643 if (!beacon) {
15b1687c 644 IWL_ERR(priv, "update beacon failed\n");
76d04815 645 goto out;
b481de9c
ZY		 646 }
647
b481de9c
ZY		 648 /* new beacon skb is allocated every time; dispose previous.*/
649 if (priv->ibss_beacon)
650 dev_kfree_skb(priv->ibss_beacon);
651
652 priv->ibss_beacon = beacon;
b481de9c 653
5b9f8cd3 654 iwl_send_beacon_cmd(priv);
76d04815
JB		 655 out:
656 mutex_unlock(&priv->mutex);
b481de9c
ZY		 657}
658
fbba9410
WYG		 659static void iwl_bg_bt_runtime_config(struct work_struct *work)
660{
661 struct iwl_priv *priv =
662 container_of(work, struct iwl_priv, bt_runtime_config);
663
664 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
665 return;
666
667 /* dont send host command if rf-kill is on */
668 if (!iwl_is_ready_rf(priv))
669 return;
670 priv->cfg->ops->hcmd->send_bt_config(priv);
671}
672
bee008b7
WYG		 673static void iwl_bg_bt_full_concurrency(struct work_struct *work)
674{
675 struct iwl_priv *priv =
676 container_of(work, struct iwl_priv, bt_full_concurrency);
246ed355 677 struct iwl_rxon_context *ctx;
bee008b7
WYG		 678
679 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
680 return;
681
682 /* dont send host command if rf-kill is on */
683 if (!iwl_is_ready_rf(priv))
684 return;
685
686 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
687 priv->bt_full_concurrent ?
688 "full concurrency" : "3-wire");
689
690 /*
691 * LQ & RXON updated cmds must be sent before BT Config cmd
692 * to avoid 3-wire collisions
693 */
246ed355
JB		 694 mutex_lock(&priv->mutex);
695 for_each_context(priv, ctx) {
696 if (priv->cfg->ops->hcmd->set_rxon_chain)
697 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
698 iwlcore_commit_rxon(priv, ctx);
699 }
700 mutex_unlock(&priv->mutex);
bee008b7
WYG		 701
702 priv->cfg->ops->hcmd->send_bt_config(priv);
703}
704
4e39317d 705/**
5b9f8cd3 706 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 707 *
708 * This callback is provided in order to send a statistics request.
709 *
710 * This timer function is continually reset to execute within
711 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
712 * was received. We need to ensure we receive the statistics in order
713 * to update the temperature used for calibrating the TXPOWER.
714 */
5b9f8cd3 715static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 716{
717 struct iwl_priv *priv = (struct iwl_priv *)data;
718
719 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
720 return;
721
61780ee3
MA		 722 /* dont send host command if rf-kill is on */
723 if (!iwl_is_ready_rf(priv))
724 return;
725
ef8d5529 726 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 727}
728
a9e1cb6a
WYG		 729
730static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
731 u32 start_idx, u32 num_events,
732 u32 mode)
733{
734 u32 i;
735 u32 ptr; /* SRAM byte address of log data */
736 u32 ev, time, data; /* event log data */
737 unsigned long reg_flags;
738
739 if (mode == 0)
740 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
741 else
742 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
743
744 /* Make sure device is powered up for SRAM reads */
745 spin_lock_irqsave(&priv->reg_lock, reg_flags);
746 if (iwl_grab_nic_access(priv)) {
747 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
748 return;
749 }
750
751 /* Set starting address; reads will auto-increment */
752 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
753 rmb();
754
755 /*
756 * "time" is actually "data" for mode 0 (no timestamp).
757 * place event id # at far right for easier visual parsing.
758 */
759 for (i = 0; i < num_events; i++) {
760 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
761 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
762 if (mode == 0) {
763 trace_iwlwifi_dev_ucode_cont_event(priv,
764 0, time, ev);
765 } else {
766 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
767 trace_iwlwifi_dev_ucode_cont_event(priv,
768 time, data, ev);
769 }
770 }
771 /* Allow device to power down */
772 iwl_release_nic_access(priv);
773 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
774}
775
875295f1 776static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 777{
778 u32 capacity; /* event log capacity in # entries */
779 u32 base; /* SRAM byte address of event log header */
780 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
781 u32 num_wraps; /* # times uCode wrapped to top of log */
782 u32 next_entry; /* index of next entry to be written by uCode */
783
784 if (priv->ucode_type == UCODE_INIT)
785 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
786 else
787 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
788 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
789 capacity = iwl_read_targ_mem(priv, base);
790 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
791 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
792 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
793 } else
794 return;
795
796 if (num_wraps == priv->event_log.num_wraps) {
797 iwl_print_cont_event_trace(priv,
798 base, priv->event_log.next_entry,
799 next_entry - priv->event_log.next_entry,
800 mode);
801 priv->event_log.non_wraps_count++;
802 } else {
803 if ((num_wraps - priv->event_log.num_wraps) > 1)
804 priv->event_log.wraps_more_count++;
805 else
806 priv->event_log.wraps_once_count++;
807 trace_iwlwifi_dev_ucode_wrap_event(priv,
808 num_wraps - priv->event_log.num_wraps,
809 next_entry, priv->event_log.next_entry);
810 if (next_entry < priv->event_log.next_entry) {
811 iwl_print_cont_event_trace(priv, base,
812 priv->event_log.next_entry,
813 capacity - priv->event_log.next_entry,
814 mode);
815
816 iwl_print_cont_event_trace(priv, base, 0,
817 next_entry, mode);
818 } else {
819 iwl_print_cont_event_trace(priv, base,
820 next_entry, capacity - next_entry,
821 mode);
822
823 iwl_print_cont_event_trace(priv, base, 0,
824 next_entry, mode);
825 }
826 }
827 priv->event_log.num_wraps = num_wraps;
828 priv->event_log.next_entry = next_entry;
829}
830
831/**
832 * iwl_bg_ucode_trace - Timer callback to log ucode event
833 *
834 * The timer is continually set to execute every
835 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
836 * this function is to perform continuous uCode event logging operation
837 * if enabled
838 */
839static void iwl_bg_ucode_trace(unsigned long data)
840{
841 struct iwl_priv *priv = (struct iwl_priv *)data;
842
843 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
844 return;
845
846 if (priv->event_log.ucode_trace) {
847 iwl_continuous_event_trace(priv);
848 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
849 mod_timer(&priv->ucode_trace,
850 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
851 }
852}
853
5b9f8cd3 854static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 855 struct iwl_rx_mem_buffer *rxb)
b481de9c 856{
2f301227 857 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 858 struct iwl4965_beacon_notif *beacon =
859 (struct iwl4965_beacon_notif *)pkt->u.raw;
a85d7cca 860#ifdef CONFIG_IWLWIFI_DEBUG
e7d326ac 861 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 862
e1623446 863 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 864 "tsf %d %d rate %d\n",
25a6572c 865 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 866 beacon->beacon_notify_hdr.failure_frame,
867 le32_to_cpu(beacon->ibss_mgr_status),
868 le32_to_cpu(beacon->high_tsf),
869 le32_to_cpu(beacon->low_tsf), rate);
870#endif
871
a85d7cca
JB		 872 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
873
60744f62 874 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 875 queue_work(priv->workqueue, &priv->beacon_update);
876}
877
b481de9c
ZY		 878/* Handle notification from uCode that card's power state is changing
879 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 880static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 881 struct iwl_rx_mem_buffer *rxb)
b481de9c 882{
2f301227 883 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 884 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
885 unsigned long status = priv->status;
886
3a41bbd5 887 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 888 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 889 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
890 (flags & CT_CARD_DISABLED) ?
891 "Reached" : "Not reached");
b481de9c
ZY		 892
893 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 894 CT_CARD_DISABLED)) {
b481de9c 895
3395f6e9 896 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 897 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
898
a8b50a0a
MA		 899 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
900 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 901
902 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 903 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 904 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 905 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 906 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 907 }
3a41bbd5 908 if (flags & CT_CARD_DISABLED)
39b73fb1 909 iwl_tt_enter_ct_kill(priv);
b481de9c 910 }
3a41bbd5 911 if (!(flags & CT_CARD_DISABLED))
39b73fb1 912 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 913
914 if (flags & HW_CARD_DISABLED)
915 set_bit(STATUS_RF_KILL_HW, &priv->status);
916 else
917 clear_bit(STATUS_RF_KILL_HW, &priv->status);
918
919
b481de9c 920 if (!(flags & RXON_CARD_DISABLED))
2a421b91 921 iwl_scan_cancel(priv);
b481de9c
ZY		 922
923 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 924 test_bit(STATUS_RF_KILL_HW, &priv->status)))
925 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
926 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 927 else
928 wake_up_interruptible(&priv->wait_command_queue);
929}
930
5b9f8cd3 931int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 932{
e2e3c57b 933 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 934 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW		 935 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
936 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
937 ~APMG_PS_CTRL_MSK_PWR_SRC);
938 } else {
939 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
940 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
941 ~APMG_PS_CTRL_MSK_PWR_SRC);
942 }
943
a8b50a0a 944 return 0;
e2e3c57b
TW		 945}
946
65550636
WYG		 947static void iwl_bg_tx_flush(struct work_struct *work)
948{
949 struct iwl_priv *priv =
950 container_of(work, struct iwl_priv, tx_flush);
951
952 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
953 return;
954
955 /* do nothing if rf-kill is on */
956 if (!iwl_is_ready_rf(priv))
957 return;
958
959 if (priv->cfg->ops->lib->txfifo_flush) {
960 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
961 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
962 }
963}
964
b481de9c 965/**
5b9f8cd3 966 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 967 *
968 * Setup the RX handlers for each of the reply types sent from the uCode
969 * to the host.
970 *
971 * This function chains into the hardware specific files for them to setup
972 * any hardware specific handlers as well.
973 */
653fa4a0 974static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 975{
885ba202 976 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 977 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
978 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 979 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
980 iwl_rx_spectrum_measure_notif;
5b9f8cd3 981 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 982 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 983 iwl_rx_pm_debug_statistics_notif;
984 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 985
9fbab516
BC		 986 /*
987 * The same handler is used for both the REPLY to a discrete
988 * statistics request from the host as well as for the periodic
989 * statistics notifications (after received beacons) from the uCode.
b481de9c 990 */
ef8d5529 991 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 992 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 993
994 iwl_setup_rx_scan_handlers(priv);
995
37a44211 996 /* status change handler */
5b9f8cd3 997 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 998
c1354754
TW		 999 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
1000 iwl_rx_missed_beacon_notif;
37a44211 1001 /* Rx handlers */
8d801080
WYG		 1002 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
1003 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 1004 /* block ack */
74bcdb33 1005 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 1006 /* Set up hardware specific Rx handlers */
d4789efe 1007 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 1008}
1009
b481de9c 1010/**
a55360e4 1011 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 1012 *
1013 * Uses the priv->rx_handlers callback function array to invoke
1014 * the appropriate handlers, including command responses,
1015 * frame-received notifications, and other notifications.
1016 */
a55360e4 1017void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 1018{
a55360e4 1019 struct iwl_rx_mem_buffer *rxb;
db11d634 1020 struct iwl_rx_packet *pkt;
a55360e4 1021 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 1022 u32 r, i;
1023 int reclaim;
1024 unsigned long flags;
5c0eef96 1025 u8 fill_rx = 0;
d68ab680 1026 u32 count = 8;
4752c93c 1027 int total_empty;
b481de9c 1028
6440adb5
CB		 1029 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1030 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 1031 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 1032 i = rxq->read;
1033
1034 /* Rx interrupt, but nothing sent from uCode */
1035 if (i == r)
e1623446 1036 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 1037
4752c93c 1038 /* calculate total frames need to be restock after handling RX */
7300515d 1039 total_empty = r - rxq->write_actual;
4752c93c
MA		 1040 if (total_empty < 0)
1041 total_empty += RX_QUEUE_SIZE;
1042
1043 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 1044 fill_rx = 1;
1045
b481de9c 1046 while (i != r) {
f4989d9b
JB		 1047 int len;
1048
b481de9c
ZY		 1049 rxb = rxq->queue[i];
1050
9fbab516 1051 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 1052 * then a bug has been introduced in the queue refilling
1053 * routines -- catch it here */
1054 BUG_ON(rxb == NULL);
1055
1056 rxq->queue[i] = NULL;
1057
2f301227
ZY		 1058 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1059 PAGE_SIZE << priv->hw_params.rx_page_order,
1060 PCI_DMA_FROMDEVICE);
1061 pkt = rxb_addr(rxb);
b481de9c 1062
f4989d9b
JB		 1063 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1064 len += sizeof(u32); /* account for status word */
1065 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 1066
b481de9c
ZY		 1067 /* Reclaim a command buffer only if this packet is a response
1068 * to a (driver-originated) command.
1069 * If the packet (e.g. Rx frame) originated from uCode,
1070 * there is no command buffer to reclaim.
1071 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1072 * but apparently a few don't get set; catch them here. */
1073 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1074 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 1075 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 1076 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 1077 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 1078 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1079 (pkt->hdr.cmd != REPLY_TX);
1080
1081 /* Based on type of command response or notification,
1082 * handle those that need handling via function in
5b9f8cd3 1083 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 1084 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1085 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 1086 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 1087 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1088 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 1089 } else {
1090 /* No handling needed */
e1623446 1091 IWL_DEBUG_RX(priv,
b481de9c
ZY		 1092 "r %d i %d No handler needed for %s, 0x%02x\n",
1093 r, i, get_cmd_string(pkt->hdr.cmd),
1094 pkt->hdr.cmd);
1095 }
1096
29b1b268
ZY		 1097 /*
1098 * XXX: After here, we should always check rxb->page
1099 * against NULL before touching it or its virtual
1100 * memory (pkt). Because some rx_handler might have
1101 * already taken or freed the pages.
1102 */
1103
b481de9c 1104 if (reclaim) {
2f301227
ZY		 1105 /* Invoke any callbacks, transfer the buffer to caller,
1106 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1107 * as we reclaim the driver command queue */
29b1b268 1108 if (rxb->page)
17b88929 1109 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1110 else
39aadf8c 1111 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1112 }
1113
7300515d
ZY		 1114 /* Reuse the page if possible. For notification packets and
1115 * SKBs that fail to Rx correctly, add them back into the
1116 * rx_free list for reuse later. */
1117 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1118 if (rxb->page != NULL) {
7300515d
ZY		 1119 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1120 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1121 PCI_DMA_FROMDEVICE);
1122 list_add_tail(&rxb->list, &rxq->rx_free);
1123 rxq->free_count++;
1124 } else
1125 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1126
b481de9c 1127 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1128
b481de9c 1129 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1130 /* If there are a lot of unused frames,
1131 * restock the Rx queue so ucode wont assert. */
1132 if (fill_rx) {
1133 count++;
1134 if (count >= 8) {
7300515d 1135 rxq->read = i;
54b81550 1136 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1137 count = 0;
1138 }
1139 }
b481de9c
ZY		 1140 }
1141
1142 /* Backtrack one entry */
7300515d 1143 rxq->read = i;
4752c93c 1144 if (fill_rx)
54b81550 1145 iwlagn_rx_replenish_now(priv);
4752c93c 1146 else
54b81550 1147 iwlagn_rx_queue_restock(priv);
a55360e4 1148}
a55360e4 1149
0359facc
MA		 1150/* call this function to flush any scheduled tasklet */
1151static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1152{
a96a27f9 1153 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1154 synchronize_irq(priv->pci_dev->irq);
1155 tasklet_kill(&priv->irq_tasklet);
1156}
1157
ef850d7c 1158static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1159{
1160 u32 inta, handled = 0;
1161 u32 inta_fh;
1162 unsigned long flags;
c2e61da2 1163 u32 i;
0a6857e7 1164#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1165 u32 inta_mask;
1166#endif
1167
1168 spin_lock_irqsave(&priv->lock, flags);
1169
1170 /* Ack/clear/reset pending uCode interrupts.
1171 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1172 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1173 inta = iwl_read32(priv, CSR_INT);
1174 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1175
1176 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1177 * Any new interrupts that happen after this, either while we're
1178 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1179 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1180 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1181
0a6857e7 1182#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1183 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1184 /* just for debug */
3395f6e9 1185 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1186 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1187 inta, inta_mask, inta_fh);
1188 }
1189#endif
1190
2f301227
ZY		 1191 spin_unlock_irqrestore(&priv->lock, flags);
1192
b481de9c
ZY		 1193 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1194 * atomic, make sure that inta covers all the interrupts that
1195 * we've discovered, even if FH interrupt came in just after
1196 * reading CSR_INT. */
6f83eaa1 1197 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1198 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1199 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1200 inta |= CSR_INT_BIT_FH_TX;
1201
1202 /* Now service all interrupt bits discovered above. */
1203 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1204 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1205
1206 /* Tell the device to stop sending interrupts */
5b9f8cd3 1207 iwl_disable_interrupts(priv);
b481de9c 1208
a83b9141 1209 priv->isr_stats.hw++;
5b9f8cd3 1210 iwl_irq_handle_error(priv);
b481de9c
ZY		 1211
1212 handled |= CSR_INT_BIT_HW_ERR;
1213
b481de9c
ZY		 1214 return;
1215 }
1216
0a6857e7 1217#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1218 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1219 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1220 if (inta & CSR_INT_BIT_SCD) {
e1623446 1221 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1222 "the frame/frames.\n");
a83b9141
WYG		 1223 priv->isr_stats.sch++;
1224 }
b481de9c
ZY		 1225
1226 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1227 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1228 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1229 priv->isr_stats.alive++;
1230 }
b481de9c
ZY		 1231 }
1232#endif
1233 /* Safely ignore these bits for debug checks below */
25c03d8e 1234 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1235
9fbab516 1236 /* HW RF KILL switch toggled */
b481de9c
ZY		 1237 if (inta & CSR_INT_BIT_RF_KILL) {
1238 int hw_rf_kill = 0;
3395f6e9 1239 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1240 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1241 hw_rf_kill = 1;
1242
4c423a2b 1243 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1244 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1245
a83b9141
WYG		 1246 priv->isr_stats.rfkill++;
1247
a9efa652 1248 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1249 * the driver allows loading the ucode even if the radio
1250 * is killed. Hence update the killswitch state here. The
1251 * rfkill handler will care about restarting if needed.
a9efa652 1252 */
6cd0b1cb
HS		 1253 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1254 if (hw_rf_kill)
1255 set_bit(STATUS_RF_KILL_HW, &priv->status);
1256 else
1257 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1258 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1259 }
b481de9c
ZY		 1260
1261 handled |= CSR_INT_BIT_RF_KILL;
1262 }
1263
9fbab516 1264 /* Chip got too hot and stopped itself */
b481de9c 1265 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1266 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1267 priv->isr_stats.ctkill++;
b481de9c
ZY		 1268 handled |= CSR_INT_BIT_CT_KILL;
1269 }
1270
1271 /* Error detected by uCode */
1272 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1273 IWL_ERR(priv, "Microcode SW error detected. "
1274 " Restarting 0x%X.\n", inta);
a83b9141
WYG		 1275 priv->isr_stats.sw++;
1276 priv->isr_stats.sw_err = inta;
5b9f8cd3 1277 iwl_irq_handle_error(priv);
b481de9c
ZY		 1278 handled |= CSR_INT_BIT_SW_ERR;
1279 }
1280
c2e61da2
BC		 1281 /*
1282 * uCode wakes up after power-down sleep.
1283 * Tell device about any new tx or host commands enqueued,
1284 * and about any Rx buffers made available while asleep.
1285 */
b481de9c 1286 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1287 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1288 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1289 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1290 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1291 priv->isr_stats.wakeup++;
b481de9c
ZY		 1292 handled |= CSR_INT_BIT_WAKEUP;
1293 }
1294
1295 /* All uCode command responses, including Tx command responses,
1296 * Rx "responses" (frame-received notification), and other
1297 * notifications from uCode come through here*/
1298 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1299 iwl_rx_handle(priv);
a83b9141 1300 priv->isr_stats.rx++;
b481de9c
ZY		 1301 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1302 }
1303
c72cd19f 1304 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1305 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1306 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1307 priv->isr_stats.tx++;
b481de9c 1308 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1309 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1310 priv->ucode_write_complete = 1;
1311 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1312 }
1313
a83b9141 1314 if (inta & ~handled) {
15b1687c 1315 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1316 priv->isr_stats.unhandled++;
1317 }
b481de9c 1318
40cefda9 1319 if (inta & ~(priv->inta_mask)) {
39aadf8c 1320 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1321 inta & ~priv->inta_mask);
39aadf8c 1322 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1323 }
1324
1325 /* Re-enable all interrupts */
0359facc
MA		 1326 /* only Re-enable if diabled by irq */
1327 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1328 iwl_enable_interrupts(priv);
b481de9c 1329
0a6857e7 1330#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1331 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1332 inta = iwl_read32(priv, CSR_INT);
1333 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1334 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1335 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1336 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1337 }
1338#endif
b481de9c
ZY		 1339}
1340
ef850d7c
MA		 1341/* tasklet for iwlagn interrupt */
1342static void iwl_irq_tasklet(struct iwl_priv *priv)
1343{
1344 u32 inta = 0;
1345 u32 handled = 0;
1346 unsigned long flags;
8756990f 1347 u32 i;
ef850d7c
MA		 1348#ifdef CONFIG_IWLWIFI_DEBUG
1349 u32 inta_mask;
1350#endif
1351
1352 spin_lock_irqsave(&priv->lock, flags);
1353
1354 /* Ack/clear/reset pending uCode interrupts.
1355 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1356 */
48a6be6a
SZ		 1357 /* There is a hardware bug in the interrupt mask function that some
1358 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1359 * they are disabled in the CSR_INT_MASK register. Furthermore the
1360 * ICT interrupt handling mechanism has another bug that might cause
1361 * these unmasked interrupts fail to be detected. We workaround the
1362 * hardware bugs here by ACKing all the possible interrupts so that
1363 * interrupt coalescing can still be achieved.
1364 */
4a35ecf8 1365 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1366
a4c8b2a6 1367 inta = priv->_agn.inta;
ef850d7c
MA		 1368
1369#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1370 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1371 /* just for debug */
1372 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1373 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1374 inta, inta_mask);
1375 }
1376#endif
2f301227
ZY		 1377
1378 spin_unlock_irqrestore(&priv->lock, flags);
1379
a4c8b2a6
JB		 1380 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1381 priv->_agn.inta = 0;
ef850d7c
MA		 1382
1383 /* Now service all interrupt bits discovered above. */
1384 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1385 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1386
1387 /* Tell the device to stop sending interrupts */
1388 iwl_disable_interrupts(priv);
1389
1390 priv->isr_stats.hw++;
1391 iwl_irq_handle_error(priv);
1392
1393 handled |= CSR_INT_BIT_HW_ERR;
1394
ef850d7c
MA		 1395 return;
1396 }
1397
1398#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1399 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1400 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1401 if (inta & CSR_INT_BIT_SCD) {
1402 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1403 "the frame/frames.\n");
1404 priv->isr_stats.sch++;
1405 }
1406
1407 /* Alive notification via Rx interrupt will do the real work */
1408 if (inta & CSR_INT_BIT_ALIVE) {
1409 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1410 priv->isr_stats.alive++;
1411 }
1412 }
1413#endif
1414 /* Safely ignore these bits for debug checks below */
1415 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1416
1417 /* HW RF KILL switch toggled */
1418 if (inta & CSR_INT_BIT_RF_KILL) {
1419 int hw_rf_kill = 0;
1420 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1421 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1422 hw_rf_kill = 1;
1423
4c423a2b 1424 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1425 hw_rf_kill ? "disable radio" : "enable radio");
1426
1427 priv->isr_stats.rfkill++;
1428
1429 /* driver only loads ucode once setting the interface up.
1430 * the driver allows loading the ucode even if the radio
1431 * is killed. Hence update the killswitch state here. The
1432 * rfkill handler will care about restarting if needed.
1433 */
1434 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1435 if (hw_rf_kill)
1436 set_bit(STATUS_RF_KILL_HW, &priv->status);
1437 else
1438 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1439 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1440 }
1441
1442 handled |= CSR_INT_BIT_RF_KILL;
1443 }
1444
1445 /* Chip got too hot and stopped itself */
1446 if (inta & CSR_INT_BIT_CT_KILL) {
1447 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1448 priv->isr_stats.ctkill++;
1449 handled |= CSR_INT_BIT_CT_KILL;
1450 }
1451
1452 /* Error detected by uCode */
1453 if (inta & CSR_INT_BIT_SW_ERR) {
1454 IWL_ERR(priv, "Microcode SW error detected. "
1455 " Restarting 0x%X.\n", inta);
1456 priv->isr_stats.sw++;
1457 priv->isr_stats.sw_err = inta;
1458 iwl_irq_handle_error(priv);
1459 handled |= CSR_INT_BIT_SW_ERR;
1460 }
1461
1462 /* uCode wakes up after power-down sleep */
1463 if (inta & CSR_INT_BIT_WAKEUP) {
1464 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1465 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1466 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1467 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1468
1469 priv->isr_stats.wakeup++;
1470
1471 handled |= CSR_INT_BIT_WAKEUP;
1472 }
1473
1474 /* All uCode command responses, including Tx command responses,
1475 * Rx "responses" (frame-received notification), and other
1476 * notifications from uCode come through here*/
40cefda9
MA		 1477 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1478 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1479 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1480 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1481 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1482 iwl_write32(priv, CSR_FH_INT_STATUS,
1483 CSR49_FH_INT_RX_MASK);
1484 }
1485 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1486 handled |= CSR_INT_BIT_RX_PERIODIC;
1487 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1488 }
1489 /* Sending RX interrupt require many steps to be done in the
1490 * the device:
1491 * 1- write interrupt to current index in ICT table.
1492 * 2- dma RX frame.
1493 * 3- update RX shared data to indicate last write index.
1494 * 4- send interrupt.
1495 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1496 * but the shared data changes does not reflect this;
1497 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1498 */
74ba67ed
BC		 1499
1500 /* Disable periodic interrupt; we use it as just a one-shot. */
1501 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1502 CSR_INT_PERIODIC_DIS);
ef850d7c 1503 iwl_rx_handle(priv);
74ba67ed
BC		 1504
1505 /*
1506 * Enable periodic interrupt in 8 msec only if we received
1507 * real RX interrupt (instead of just periodic int), to catch
1508 * any dangling Rx interrupt. If it was just the periodic
1509 * interrupt, there was no dangling Rx activity, and no need
1510 * to extend the periodic interrupt; one-shot is enough.
1511 */
40cefda9 1512 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1513 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1514 CSR_INT_PERIODIC_ENA);
1515
ef850d7c 1516 priv->isr_stats.rx++;
ef850d7c
MA		 1517 }
1518
c72cd19f 1519 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1520 if (inta & CSR_INT_BIT_FH_TX) {
1521 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1522 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1523 priv->isr_stats.tx++;
1524 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1525 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1526 priv->ucode_write_complete = 1;
1527 wake_up_interruptible(&priv->wait_command_queue);
1528 }
1529
1530 if (inta & ~handled) {
1531 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1532 priv->isr_stats.unhandled++;
1533 }
1534
40cefda9 1535 if (inta & ~(priv->inta_mask)) {
ef850d7c 1536 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1537 inta & ~priv->inta_mask);
ef850d7c
MA		 1538 }
1539
ef850d7c
MA		 1540 /* Re-enable all interrupts */
1541 /* only Re-enable if diabled by irq */
1542 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1543 iwl_enable_interrupts(priv);
ef850d7c
MA		 1544}
1545
872c8ddc
WYG		 1546/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1547#define ACK_CNT_RATIO (50)
1548#define BA_TIMEOUT_CNT (5)
1549#define BA_TIMEOUT_MAX (16)
1550
1551/**
1552 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1553 *
1554 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1555 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1556 * operation state.
1557 */
1558bool iwl_good_ack_health(struct iwl_priv *priv,
1559 struct iwl_rx_packet *pkt)
1560{
1561 bool rc = true;
1562 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1563 int ba_timeout_delta;
1564
1565 actual_ack_cnt_delta =
1566 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
f3aebeee 1567 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1568 expected_ack_cnt_delta =
1569 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
f3aebeee 1570 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1571 ba_timeout_delta =
1572 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
f3aebeee 1573 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1574 if ((priv->_agn.agg_tids_count > 0) &&
1575 (expected_ack_cnt_delta > 0) &&
1576 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1577 < ACK_CNT_RATIO) &&
1578 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1579 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1580 " expected_ack_cnt = %d\n",
1581 actual_ack_cnt_delta, expected_ack_cnt_delta);
1582
d73e4923
JB		 1583#ifdef CONFIG_IWLWIFI_DEBUGFS
1584 /*
1585 * This is ifdef'ed on DEBUGFS because otherwise the
1586 * statistics aren't available. If DEBUGFS is set but
1587 * DEBUG is not, these will just compile out.
1588 */
872c8ddc 1589 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
f3aebeee 1590 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1591 IWL_DEBUG_RADIO(priv,
1592 "ack_or_ba_timeout_collision delta = %d\n",
f3aebeee 1593 priv->_agn.delta_statistics.tx.
872c8ddc
WYG		 1594 ack_or_ba_timeout_collision);
1595#endif
1596 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1597 ba_timeout_delta);
1598 if (!actual_ack_cnt_delta &&
1599 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1600 rc = false;
1601 }
1602 return rc;
1603}
1604
a83b9141 1605
7d47618a
EG		 1606/*****************************************************************************
1607 *
1608 * sysfs attributes
1609 *
1610 *****************************************************************************/
1611
1612#ifdef CONFIG_IWLWIFI_DEBUG
1613
1614/*
1615 * The following adds a new attribute to the sysfs representation
1616 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1617 * used for controlling the debug level.
1618 *
1619 * See the level definitions in iwl for details.
1620 *
1621 * The debug_level being managed using sysfs below is a per device debug
1622 * level that is used instead of the global debug level if it (the per
1623 * device debug level) is set.
1624 */
1625static ssize_t show_debug_level(struct device *d,
1626 struct device_attribute *attr, char *buf)
1627{
1628 struct iwl_priv *priv = dev_get_drvdata(d);
1629 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1630}
1631static ssize_t store_debug_level(struct device *d,
1632 struct device_attribute *attr,
1633 const char *buf, size_t count)
1634{
1635 struct iwl_priv *priv = dev_get_drvdata(d);
1636 unsigned long val;
1637 int ret;
1638
1639 ret = strict_strtoul(buf, 0, &val);
1640 if (ret)
1641 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1642 else {
1643 priv->debug_level = val;
1644 if (iwl_alloc_traffic_mem(priv))
1645 IWL_ERR(priv,
1646 "Not enough memory to generate traffic log\n");
1647 }
1648 return strnlen(buf, count);
1649}
1650
1651static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1652 show_debug_level, store_debug_level);
1653
1654
1655#endif /* CONFIG_IWLWIFI_DEBUG */
1656
1657
1658static ssize_t show_temperature(struct device *d,
1659 struct device_attribute *attr, char *buf)
1660{
1661 struct iwl_priv *priv = dev_get_drvdata(d);
1662
1663 if (!iwl_is_alive(priv))
1664 return -EAGAIN;
1665
1666 return sprintf(buf, "%d\n", priv->temperature);
1667}
1668
1669static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1670
1671static ssize_t show_tx_power(struct device *d,
1672 struct device_attribute *attr, char *buf)
1673{
1674 struct iwl_priv *priv = dev_get_drvdata(d);
1675
1676 if (!iwl_is_ready_rf(priv))
1677 return sprintf(buf, "off\n");
1678 else
1679 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1680}
1681
1682static ssize_t store_tx_power(struct device *d,
1683 struct device_attribute *attr,
1684 const char *buf, size_t count)
1685{
1686 struct iwl_priv *priv = dev_get_drvdata(d);
1687 unsigned long val;
1688 int ret;
1689
1690 ret = strict_strtoul(buf, 10, &val);
1691 if (ret)
1692 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1693 else {
1694 ret = iwl_set_tx_power(priv, val, false);
1695 if (ret)
1696 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1697 ret);
1698 else
1699 ret = count;
1700 }
1701 return ret;
1702}
1703
1704static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1705
7d47618a
EG		 1706static struct attribute *iwl_sysfs_entries[] = {
1707 &dev_attr_temperature.attr,
1708 &dev_attr_tx_power.attr,
7d47618a
EG		 1709#ifdef CONFIG_IWLWIFI_DEBUG
1710 &dev_attr_debug_level.attr,
1711#endif
1712 NULL
1713};
1714
1715static struct attribute_group iwl_attribute_group = {
1716 .name = NULL, /* put in device directory */
1717 .attrs = iwl_sysfs_entries,
1718};
1719
b481de9c
ZY		 1720/******************************************************************************
1721 *
1722 * uCode download functions
1723 *
1724 ******************************************************************************/
1725
5b9f8cd3 1726static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1727{
98c92211
TW		 1728 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1729 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1730 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1731 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1732 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1733 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1734}
1735
5b9f8cd3 1736static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1737{
1738 /* Remove all resets to allow NIC to operate */
1739 iwl_write32(priv, CSR_RESET, 0);
1740}
1741
dd7a2509
JB		 1742struct iwlagn_ucode_capabilities {
1743 u32 max_probe_length;
6a822d06 1744 u32 standard_phy_calibration_size;
ece9c4ee 1745 bool pan;
dd7a2509 1746};
edcdf8b2 1747
b08dfd04 1748static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1749static int iwl_mac_setup_register(struct iwl_priv *priv,
1750 struct iwlagn_ucode_capabilities *capa);
b08dfd04 1751
39396085
JS		 1752#define UCODE_EXPERIMENTAL_INDEX 100
1753#define UCODE_EXPERIMENTAL_TAG "exp"
1754
b08dfd04
JB		 1755static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1756{
1757 const char *name_pre = priv->cfg->fw_name_pre;
39396085 1758 char tag[8];
b08dfd04 1759
39396085
JS		 1760 if (first) {
1761#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1762 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1763 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1764 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1765#endif
b08dfd04 1766 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS		 1767 sprintf(tag, "%d", priv->fw_index);
1768 } else {
b08dfd04 1769 priv->fw_index--;
39396085
JS		 1770 sprintf(tag, "%d", priv->fw_index);
1771 }
b08dfd04
JB		 1772
1773 if (priv->fw_index < priv->cfg->ucode_api_min) {
1774 IWL_ERR(priv, "no suitable firmware found!\n");
1775 return -ENOENT;
1776 }
1777
39396085 1778 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1779
39396085
JS		 1780 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1781 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1782 ? "EXPERIMENTAL " : "",
b08dfd04
JB		 1783 priv->firmware_name);
1784
1785 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1786 &priv->pci_dev->dev, GFP_KERNEL, priv,
1787 iwl_ucode_callback);
1788}
1789
0e9a44dc
JB		 1790struct iwlagn_firmware_pieces {
1791 const void *inst, *data, *init, *init_data, *boot;
1792 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1793
1794 u32 build;
b2e640d4
JB		 1795
1796 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1797 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1798};
1799
1800static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1801 const struct firmware *ucode_raw,
1802 struct iwlagn_firmware_pieces *pieces)
1803{
1804 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1805 u32 api_ver, hdr_size;
1806 const u8 *src;
1807
1808 priv->ucode_ver = le32_to_cpu(ucode->ver);
1809 api_ver = IWL_UCODE_API(priv->ucode_ver);
1810
1811 switch (api_ver) {
1812 default:
1813 /*
1814 * 4965 doesn't revision the firmware file format
1815 * along with the API version, it always uses v1
1816 * file format.
1817 */
1818 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1819 CSR_HW_REV_TYPE_4965) {
1820 hdr_size = 28;
1821 if (ucode_raw->size < hdr_size) {
1822 IWL_ERR(priv, "File size too small!\n");
1823 return -EINVAL;
1824 }
1825 pieces->build = le32_to_cpu(ucode->u.v2.build);
1826 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1827 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1828 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1829 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1830 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1831 src = ucode->u.v2.data;
1832 break;
1833 }
1834 /* fall through for 4965 */
1835 case 0:
1836 case 1:
1837 case 2:
1838 hdr_size = 24;
1839 if (ucode_raw->size < hdr_size) {
1840 IWL_ERR(priv, "File size too small!\n");
1841 return -EINVAL;
1842 }
1843 pieces->build = 0;
1844 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1845 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1846 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1847 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1848 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1849 src = ucode->u.v1.data;
1850 break;
1851 }
1852
1853 /* Verify size of file vs. image size info in file's header */
1854 if (ucode_raw->size != hdr_size + pieces->inst_size +
1855 pieces->data_size + pieces->init_size +
1856 pieces->init_data_size + pieces->boot_size) {
1857
1858 IWL_ERR(priv,
1859 "uCode file size %d does not match expected size\n",
1860 (int)ucode_raw->size);
1861 return -EINVAL;
1862 }
1863
1864 pieces->inst = src;
1865 src += pieces->inst_size;
1866 pieces->data = src;
1867 src += pieces->data_size;
1868 pieces->init = src;
1869 src += pieces->init_size;
1870 pieces->init_data = src;
1871 src += pieces->init_data_size;
1872 pieces->boot = src;
1873 src += pieces->boot_size;
1874
1875 return 0;
1876}
1877
dd7a2509
JB		 1878static int iwlagn_wanted_ucode_alternative = 1;
1879
1880static int iwlagn_load_firmware(struct iwl_priv *priv,
1881 const struct firmware *ucode_raw,
1882 struct iwlagn_firmware_pieces *pieces,
1883 struct iwlagn_ucode_capabilities *capa)
1884{
1885 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1886 struct iwl_ucode_tlv *tlv;
1887 size_t len = ucode_raw->size;
1888 const u8 *data;
1889 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1890 u64 alternatives;
ad8d8333
WYG		 1891 u32 tlv_len;
1892 enum iwl_ucode_tlv_type tlv_type;
1893 const u8 *tlv_data;
dd7a2509 1894
ad8d8333
WYG		 1895 if (len < sizeof(*ucode)) {
1896 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1897 return -EINVAL;
ad8d8333 1898 }
dd7a2509 1899
ad8d8333
WYG		 1900 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1901 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1902 le32_to_cpu(ucode->magic));
dd7a2509 1903 return -EINVAL;
ad8d8333 1904 }
dd7a2509
JB		 1905
1906 /*
1907 * Check which alternatives are present, and "downgrade"
1908 * when the chosen alternative is not present, warning
1909 * the user when that happens. Some files may not have
1910 * any alternatives, so don't warn in that case.
1911 */
1912 alternatives = le64_to_cpu(ucode->alternatives);
1913 tmp = wanted_alternative;
1914 if (wanted_alternative > 63)
1915 wanted_alternative = 63;
1916 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1917 wanted_alternative--;
1918 if (wanted_alternative && wanted_alternative != tmp)
1919 IWL_WARN(priv,
1920 "uCode alternative %d not available, choosing %d\n",
1921 tmp, wanted_alternative);
1922
1923 priv->ucode_ver = le32_to_cpu(ucode->ver);
1924 pieces->build = le32_to_cpu(ucode->build);
1925 data = ucode->data;
1926
1927 len -= sizeof(*ucode);
1928
704da534 1929 while (len >= sizeof(*tlv)) {
dd7a2509 1930 u16 tlv_alt;
dd7a2509
JB		 1931
1932 len -= sizeof(*tlv);
1933 tlv = (void *)data;
1934
1935 tlv_len = le32_to_cpu(tlv->length);
1936 tlv_type = le16_to_cpu(tlv->type);
1937 tlv_alt = le16_to_cpu(tlv->alternative);
1938 tlv_data = tlv->data;
1939
ad8d8333
WYG		 1940 if (len < tlv_len) {
1941 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1942 len, tlv_len);
dd7a2509 1943 return -EINVAL;
ad8d8333 1944 }
dd7a2509
JB		 1945 len -= ALIGN(tlv_len, 4);
1946 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1947
1948 /*
1949 * Alternative 0 is always valid.
1950 *
1951 * Skip alternative TLVs that are not selected.
1952 */
1953 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1954 continue;
1955
1956 switch (tlv_type) {
1957 case IWL_UCODE_TLV_INST:
1958 pieces->inst = tlv_data;
1959 pieces->inst_size = tlv_len;
1960 break;
1961 case IWL_UCODE_TLV_DATA:
1962 pieces->data = tlv_data;
1963 pieces->data_size = tlv_len;
1964 break;
1965 case IWL_UCODE_TLV_INIT:
1966 pieces->init = tlv_data;
1967 pieces->init_size = tlv_len;
1968 break;
1969 case IWL_UCODE_TLV_INIT_DATA:
1970 pieces->init_data = tlv_data;
1971 pieces->init_data_size = tlv_len;
1972 break;
1973 case IWL_UCODE_TLV_BOOT:
1974 pieces->boot = tlv_data;
1975 pieces->boot_size = tlv_len;
1976 break;
1977 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1978 if (tlv_len != sizeof(u32))
1979 goto invalid_tlv_len;
1980 capa->max_probe_length =
ad8d8333 1981 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1982 break;
ece9c4ee
JB		 1983 case IWL_UCODE_TLV_PAN:
1984 if (tlv_len)
1985 goto invalid_tlv_len;
1986 capa->pan = true;
1987 break;
b2e640d4 1988 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1989 if (tlv_len != sizeof(u32))
1990 goto invalid_tlv_len;
1991 pieces->init_evtlog_ptr =
ad8d8333 1992 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1993 break;
1994 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 1995 if (tlv_len != sizeof(u32))
1996 goto invalid_tlv_len;
1997 pieces->init_evtlog_size =
ad8d8333 1998 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1999 break;
2000 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 2001 if (tlv_len != sizeof(u32))
2002 goto invalid_tlv_len;
2003 pieces->init_errlog_ptr =
ad8d8333 2004 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2005 break;
2006 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 2007 if (tlv_len != sizeof(u32))
2008 goto invalid_tlv_len;
2009 pieces->inst_evtlog_ptr =
ad8d8333 2010 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2011 break;
2012 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 2013 if (tlv_len != sizeof(u32))
2014 goto invalid_tlv_len;
2015 pieces->inst_evtlog_size =
ad8d8333 2016 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2017 break;
2018 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 2019 if (tlv_len != sizeof(u32))
2020 goto invalid_tlv_len;
2021 pieces->inst_errlog_ptr =
ad8d8333 2022 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 2023 break;
c8312fac
WYG		 2024 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
2025 if (tlv_len)
704da534
JB		 2026 goto invalid_tlv_len;
2027 priv->enhance_sensitivity_table = true;
c8312fac 2028 break;
6a822d06 2029 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 2030 if (tlv_len != sizeof(u32))
2031 goto invalid_tlv_len;
2032 capa->standard_phy_calibration_size =
6a822d06
WYG		 2033 le32_to_cpup((__le32 *)tlv_data);
2034 break;
dd7a2509 2035 default:
ad8d8333 2036 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 2037 break;
2038 }
2039 }
2040
ad8d8333
WYG		 2041 if (len) {
2042 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2043 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 2044 return -EINVAL;
ad8d8333 2045 }
dd7a2509 2046
704da534
JB		 2047 return 0;
2048
2049 invalid_tlv_len:
2050 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2051 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2052
2053 return -EINVAL;
dd7a2509
JB		 2054}
2055
b481de9c 2056/**
b08dfd04 2057 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 2058 *
b08dfd04
JB		 2059 * If loaded successfully, copies the firmware into buffers
2060 * for the card to fetch (via DMA).
b481de9c 2061 */
b08dfd04 2062static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 2063{
b08dfd04 2064 struct iwl_priv *priv = context;
cc0f555d 2065 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 2066 int err;
2067 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 2068 const unsigned int api_max = priv->cfg->ucode_api_max;
2069 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 2070 u32 api_ver;
3e4de761 2071 char buildstr[25];
0e9a44dc 2072 u32 build;
dd7a2509
JB		 2073 struct iwlagn_ucode_capabilities ucode_capa = {
2074 .max_probe_length = 200,
6a822d06
WYG		 2075 .standard_phy_calibration_size =
2076 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 2077 };
0e9a44dc
JB		 2078
2079 memset(&pieces, 0, sizeof(pieces));
b481de9c 2080
b08dfd04 2081 if (!ucode_raw) {
39396085
JS		 2082 if (priv->fw_index <= priv->cfg->ucode_api_max)
2083 IWL_ERR(priv,
2084 "request for firmware file '%s' failed.\n",
2085 priv->firmware_name);
b08dfd04 2086 goto try_again;
b481de9c
ZY		 2087 }
2088
b08dfd04
JB		 2089 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2090 priv->firmware_name, ucode_raw->size);
b481de9c 2091
22adba2a
JB		 2092 /* Make sure that we got at least the API version number */
2093 if (ucode_raw->size < 4) {
15b1687c 2094 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 2095 goto try_again;
b481de9c
ZY		 2096 }
2097
2098 /* Data from ucode file: header followed by uCode images */
cc0f555d 2099 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2100
0e9a44dc
JB		 2101 if (ucode->ver)
2102 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2103 else
dd7a2509
JB		 2104 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2105 &ucode_capa);
22adba2a 2106
0e9a44dc
JB		 2107 if (err)
2108 goto try_again;
b481de9c 2109
a0987a8d 2110 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 2111 build = pieces.build;
a0987a8d 2112
0e9a44dc
JB		 2113 /*
2114 * api_ver should match the api version forming part of the
2115 * firmware filename ... but we don't check for that and only rely
2116 * on the API version read from firmware header from here on forward
2117 */
a0987a8d 2118 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2119 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 2120 "Driver supports v%u, firmware is v%u.\n",
2121 api_max, api_ver);
b08dfd04 2122 goto try_again;
a0987a8d 2123 }
b08dfd04 2124
a0987a8d 2125 if (api_ver != api_max)
978785a3 2126 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 2127 "got v%u. New firmware can be obtained "
2128 "from http://www.intellinuxwireless.org.\n",
2129 api_max, api_ver);
2130
3e4de761 2131 if (build)
39396085
JS		 2132 sprintf(buildstr, " build %u%s", build,
2133 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2134 ? " (EXP)" : "");
3e4de761
JB		 2135 else
2136 buildstr[0] = '\0';
2137
2138 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2139 IWL_UCODE_MAJOR(priv->ucode_ver),
2140 IWL_UCODE_MINOR(priv->ucode_ver),
2141 IWL_UCODE_API(priv->ucode_ver),
2142 IWL_UCODE_SERIAL(priv->ucode_ver),
2143 buildstr);
a0987a8d 2144
5ebeb5a6
RC		 2145 snprintf(priv->hw->wiphy->fw_version,
2146 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2147 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2148 IWL_UCODE_MAJOR(priv->ucode_ver),
2149 IWL_UCODE_MINOR(priv->ucode_ver),
2150 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2151 IWL_UCODE_SERIAL(priv->ucode_ver),
2152 buildstr);
b481de9c 2153
b08dfd04
JB		 2154 /*
2155 * For any of the failures below (before allocating pci memory)
2156 * we will try to load a version with a smaller API -- maybe the
2157 * user just got a corrupted version of the latest API.
2158 */
2159
0e9a44dc
JB		 2160 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2161 priv->ucode_ver);
2162 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2163 pieces.inst_size);
2164 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2165 pieces.data_size);
2166 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2167 pieces.init_size);
2168 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2169 pieces.init_data_size);
2170 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2171 pieces.boot_size);
b481de9c
ZY		 2172
2173 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2174 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2175 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2176 pieces.inst_size);
b08dfd04 2177 goto try_again;
b481de9c
ZY		 2178 }
2179
0e9a44dc
JB		 2180 if (pieces.data_size > priv->hw_params.max_data_size) {
2181 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2182 pieces.data_size);
b08dfd04 2183 goto try_again;
b481de9c 2184 }
0e9a44dc
JB		 2185
2186 if (pieces.init_size > priv->hw_params.max_inst_size) {
2187 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2188 pieces.init_size);
b08dfd04 2189 goto try_again;
b481de9c 2190 }
0e9a44dc
JB		 2191
2192 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2193 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2194 pieces.init_data_size);
b08dfd04 2195 goto try_again;
b481de9c 2196 }
0e9a44dc
JB		 2197
2198 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2199 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2200 pieces.boot_size);
b08dfd04 2201 goto try_again;
b481de9c
ZY		 2202 }
2203
2204 /* Allocate ucode buffers for card's bus-master loading ... */
2205
2206 /* Runtime instructions and 2 copies of data:
2207 * 1) unmodified from disk
2208 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2209 priv->ucode_code.len = pieces.inst_size;
98c92211 2210 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2211
0e9a44dc 2212 priv->ucode_data.len = pieces.data_size;
98c92211 2213 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2214
0e9a44dc 2215 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2216 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2217
1f304e4e
ZY		 2218 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2219 !priv->ucode_data_backup.v_addr)
2220 goto err_pci_alloc;
2221
b481de9c 2222 /* Initialization instructions and data */
0e9a44dc
JB		 2223 if (pieces.init_size && pieces.init_data_size) {
2224 priv->ucode_init.len = pieces.init_size;
98c92211 2225 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2226
0e9a44dc 2227 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2228 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2229
2230 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2231 goto err_pci_alloc;
2232 }
b481de9c
ZY		 2233
2234 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2235 if (pieces.boot_size) {
2236 priv->ucode_boot.len = pieces.boot_size;
98c92211 2237 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2238
90e759d1
TW		 2239 if (!priv->ucode_boot.v_addr)
2240 goto err_pci_alloc;
2241 }
b481de9c 2242
b2e640d4
JB		 2243 /* Now that we can no longer fail, copy information */
2244
2245 /*
2246 * The (size - 16) / 12 formula is based on the information recorded
2247 * for each event, which is of mode 1 (including timestamp) for all
2248 * new microcodes that include this information.
2249 */
2250 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2251 if (pieces.init_evtlog_size)
2252 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2253 else
2254 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2255 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2256 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2257 if (pieces.inst_evtlog_size)
2258 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2259 else
2260 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2261 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2262
ece9c4ee
JB		 2263 if (ucode_capa.pan) {
2264 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
c10afb6e 2265 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
ece9c4ee
JB		 2266 } else
2267 priv->sta_key_max_num = STA_KEY_MAX_NUM;
c10afb6e 2268
b481de9c
ZY		 2269 /* Copy images into buffers for card's bus-master reads ... */
2270
2271 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2272 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2273 pieces.inst_size);
2274 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2275
e1623446 2276 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2277 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2278
0e9a44dc
JB		 2279 /*
2280 * Runtime data
2281 * NOTE: Copy into backup buffer will be done in iwl_up()
2282 */
2283 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2284 pieces.data_size);
2285 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2286 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2287
2288 /* Initialization instructions */
2289 if (pieces.init_size) {
e1623446 2290 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2291 pieces.init_size);
2292 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2293 }
2294
0e9a44dc
JB		 2295 /* Initialization data */
2296 if (pieces.init_data_size) {
e1623446 2297 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2298 pieces.init_data_size);
2299 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2300 pieces.init_data_size);
b481de9c
ZY		 2301 }
2302
0e9a44dc
JB		 2303 /* Bootstrap instructions */
2304 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2305 pieces.boot_size);
2306 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2307
6a822d06
WYG		 2308 /*
2309 * figure out the offset of chain noise reset and gain commands
2310 * base on the size of standard phy calibration commands table size
2311 */
2312 if (ucode_capa.standard_phy_calibration_size >
2313 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2314 ucode_capa.standard_phy_calibration_size =
2315 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2316
2317 priv->_agn.phy_calib_chain_noise_reset_cmd =
2318 ucode_capa.standard_phy_calibration_size;
2319 priv->_agn.phy_calib_chain_noise_gain_cmd =
2320 ucode_capa.standard_phy_calibration_size + 1;
2321
b08dfd04
JB		 2322 /**************************************************
2323 * This is still part of probe() in a sense...
2324 *
2325 * 9. Setup and register with mac80211 and debugfs
2326 **************************************************/
dd7a2509 2327 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2328 if (err)
2329 goto out_unbind;
2330
2331 err = iwl_dbgfs_register(priv, DRV_NAME);
2332 if (err)
2333 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2334
7d47618a
EG		 2335 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2336 &iwl_attribute_group);
2337 if (err) {
2338 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2339 goto out_unbind;
2340 }
2341
b481de9c
ZY		 2342 /* We have our copies now, allow OS release its copies */
2343 release_firmware(ucode_raw);
a15707d8 2344 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2345 return;
2346
2347 try_again:
2348 /* try next, if any */
2349 if (iwl_request_firmware(priv, false))
2350 goto out_unbind;
2351 release_firmware(ucode_raw);
2352 return;
b481de9c
ZY		 2353
2354 err_pci_alloc:
15b1687c 2355 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2356 iwl_dealloc_ucode_pci(priv);
b08dfd04 2357 out_unbind:
a15707d8 2358 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2359 device_release_driver(&priv->pci_dev->dev);
b481de9c 2360 release_firmware(ucode_raw);
b481de9c
ZY		 2361}
2362
b7a79404
RC		 2363static const char *desc_lookup_text[] = {
2364 "OK",
2365 "FAIL",
2366 "BAD_PARAM",
2367 "BAD_CHECKSUM",
2368 "NMI_INTERRUPT_WDG",
2369 "SYSASSERT",
2370 "FATAL_ERROR",
2371 "BAD_COMMAND",
2372 "HW_ERROR_TUNE_LOCK",
2373 "HW_ERROR_TEMPERATURE",
2374 "ILLEGAL_CHAN_FREQ",
2375 "VCC_NOT_STABLE",
2376 "FH_ERROR",
2377 "NMI_INTERRUPT_HOST",
2378 "NMI_INTERRUPT_ACTION_PT",
2379 "NMI_INTERRUPT_UNKNOWN",
2380 "UCODE_VERSION_MISMATCH",
2381 "HW_ERROR_ABS_LOCK",
2382 "HW_ERROR_CAL_LOCK_FAIL",
2383 "NMI_INTERRUPT_INST_ACTION_PT",
2384 "NMI_INTERRUPT_DATA_ACTION_PT",
2385 "NMI_TRM_HW_ER",
2386 "NMI_INTERRUPT_TRM",
2387 "NMI_INTERRUPT_BREAK_POINT"
2388 "DEBUG_0",
2389 "DEBUG_1",
2390 "DEBUG_2",
2391 "DEBUG_3",
b7a79404
RC		 2392};
2393
4b58645c
JS		 2394static struct { char *name; u8 num; } advanced_lookup[] = {
2395 { "NMI_INTERRUPT_WDG", 0x34 },
2396 { "SYSASSERT", 0x35 },
2397 { "UCODE_VERSION_MISMATCH", 0x37 },
2398 { "BAD_COMMAND", 0x38 },
2399 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2400 { "FATAL_ERROR", 0x3D },
2401 { "NMI_TRM_HW_ERR", 0x46 },
2402 { "NMI_INTERRUPT_TRM", 0x4C },
2403 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2404 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2405 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2406 { "NMI_INTERRUPT_HOST", 0x66 },
2407 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2408 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2409 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2410 { "ADVANCED_SYSASSERT", 0 },
2411};
2412
2413static const char *desc_lookup(u32 num)
b7a79404 2414{
4b58645c
JS		 2415 int i;
2416 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 2417
4b58645c
JS		 2418 if (num < max)
2419 return desc_lookup_text[num];
b7a79404 2420
4b58645c
JS		 2421 max = ARRAY_SIZE(advanced_lookup) - 1;
2422 for (i = 0; i < max; i++) {
2423 if (advanced_lookup[i].num == num)
2424 break;;
2425 }
2426 return advanced_lookup[i].name;
b7a79404
RC		 2427}
2428
2429#define ERROR_START_OFFSET (1 * sizeof(u32))
2430#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2431
2432void iwl_dump_nic_error_log(struct iwl_priv *priv)
2433{
2434 u32 data2, line;
2435 u32 desc, time, count, base, data1;
2436 u32 blink1, blink2, ilink1, ilink2;
461ef382 2437 u32 pc, hcmd;
b7a79404 2438
b2e640d4 2439 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2440 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2441 if (!base)
2442 base = priv->_agn.init_errlog_ptr;
2443 } else {
b7a79404 2444 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2445 if (!base)
2446 base = priv->_agn.inst_errlog_ptr;
2447 }
b7a79404
RC		 2448
2449 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2450 IWL_ERR(priv,
2451 "Not valid error log pointer 0x%08X for %s uCode\n",
2452 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2453 return;
2454 }
2455
2456 count = iwl_read_targ_mem(priv, base);
2457
2458 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2459 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2460 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2461 priv->status, count);
2462 }
2463
2464 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
461ef382 2465 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2466 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2467 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2468 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2469 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2470 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2471 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2472 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2473 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2474 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2475
be1a71a1
JB		 2476 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2477 blink1, blink2, ilink1, ilink2);
2478
87563715 2479 IWL_ERR(priv, "Desc Time "
b7a79404 2480 "data1 data2 line\n");
87563715 2481 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2482 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2483 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2484 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2485 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2486}
2487
2488#define EVENT_START_OFFSET (4 * sizeof(u32))
2489
2490/**
2491 * iwl_print_event_log - Dump error event log to syslog
2492 *
2493 */
b03d7d0f
WYG		 2494static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2495 u32 num_events, u32 mode,
2496 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2497{
2498 u32 i;
2499 u32 base; /* SRAM byte address of event log header */
2500 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2501 u32 ptr; /* SRAM byte address of log data */
2502 u32 ev, time, data; /* event log data */
e5854471 2503 unsigned long reg_flags;
b7a79404
RC		 2504
2505 if (num_events == 0)
b03d7d0f 2506 return pos;
b2e640d4
JB		 2507
2508 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2509 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2510 if (!base)
2511 base = priv->_agn.init_evtlog_ptr;
2512 } else {
b7a79404 2513 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2514 if (!base)
2515 base = priv->_agn.inst_evtlog_ptr;
2516 }
b7a79404
RC		 2517
2518 if (mode == 0)
2519 event_size = 2 * sizeof(u32);
2520 else
2521 event_size = 3 * sizeof(u32);
2522
2523 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2524
e5854471
BC		 2525 /* Make sure device is powered up for SRAM reads */
2526 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2527 iwl_grab_nic_access(priv);
2528
2529 /* Set starting address; reads will auto-increment */
2530 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2531 rmb();
2532
b7a79404
RC		 2533 /* "time" is actually "data" for mode 0 (no timestamp).
2534 * place event id # at far right for easier visual parsing. */
2535 for (i = 0; i < num_events; i++) {
e5854471
BC		 2536 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2537 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2538 if (mode == 0) {
2539 /* data, ev */
b03d7d0f
WYG		 2540 if (bufsz) {
2541 pos += scnprintf(*buf + pos, bufsz - pos,
2542 "EVT_LOG:0x%08x:%04u\n",
2543 time, ev);
2544 } else {
2545 trace_iwlwifi_dev_ucode_event(priv, 0,
2546 time, ev);
2547 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2548 time, ev);
2549 }
b7a79404 2550 } else {
e5854471 2551 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2552 if (bufsz) {
2553 pos += scnprintf(*buf + pos, bufsz - pos,
2554 "EVT_LOGT:%010u:0x%08x:%04u\n",
2555 time, data, ev);
2556 } else {
2557 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2558 time, data, ev);
b03d7d0f
WYG		 2559 trace_iwlwifi_dev_ucode_event(priv, time,
2560 data, ev);
2561 }
b7a79404
RC		 2562 }
2563 }
e5854471
BC		 2564
2565 /* Allow device to power down */
2566 iwl_release_nic_access(priv);
2567 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2568 return pos;
b7a79404
RC		 2569}
2570
c341ddb2
WYG		 2571/**
2572 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2573 */
b03d7d0f
WYG		 2574static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2575 u32 num_wraps, u32 next_entry,
2576 u32 size, u32 mode,
2577 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2578{
2579 /*
2580 * display the newest DEFAULT_LOG_ENTRIES entries
2581 * i.e the entries just before the next ont that uCode would fill.
2582 */
2583 if (num_wraps) {
2584 if (next_entry < size) {
b03d7d0f
WYG		 2585 pos = iwl_print_event_log(priv,
2586 capacity - (size - next_entry),
2587 size - next_entry, mode,
2588 pos, buf, bufsz);
2589 pos = iwl_print_event_log(priv, 0,
2590 next_entry, mode,
2591 pos, buf, bufsz);
c341ddb2 2592 } else
b03d7d0f
WYG		 2593 pos = iwl_print_event_log(priv, next_entry - size,
2594 size, mode, pos, buf, bufsz);
c341ddb2 2595 } else {
b03d7d0f
WYG		 2596 if (next_entry < size) {
2597 pos = iwl_print_event_log(priv, 0, next_entry,
2598 mode, pos, buf, bufsz);
2599 } else {
2600 pos = iwl_print_event_log(priv, next_entry - size,
2601 size, mode, pos, buf, bufsz);
2602 }
c341ddb2 2603 }
b03d7d0f 2604 return pos;
c341ddb2
WYG		 2605}
2606
c341ddb2
WYG		 2607#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2608
b03d7d0f
WYG		 2609int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2610 char **buf, bool display)
b7a79404
RC		 2611{
2612 u32 base; /* SRAM byte address of event log header */
2613 u32 capacity; /* event log capacity in # entries */
2614 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2615 u32 num_wraps; /* # times uCode wrapped to top of log */
2616 u32 next_entry; /* index of next entry to be written by uCode */
2617 u32 size; /* # entries that we'll print */
b2e640d4 2618 u32 logsize;
b03d7d0f
WYG		 2619 int pos = 0;
2620 size_t bufsz = 0;
b7a79404 2621
b2e640d4 2622 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2623 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2624 logsize = priv->_agn.init_evtlog_size;
2625 if (!base)
2626 base = priv->_agn.init_evtlog_ptr;
2627 } else {
b7a79404 2628 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2629 logsize = priv->_agn.inst_evtlog_size;
2630 if (!base)
2631 base = priv->_agn.inst_evtlog_ptr;
2632 }
b7a79404
RC		 2633
2634 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2635 IWL_ERR(priv,
2636 "Invalid event log pointer 0x%08X for %s uCode\n",
2637 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2638 return -EINVAL;
b7a79404
RC		 2639 }
2640
2641 /* event log header */
2642 capacity = iwl_read_targ_mem(priv, base);
2643 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2644 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2645 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2646
b2e640d4 2647 if (capacity > logsize) {
84c40692 2648 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2649 capacity, logsize);
2650 capacity = logsize;
84c40692
BC		 2651 }
2652
b2e640d4 2653 if (next_entry > logsize) {
84c40692 2654 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2655 next_entry, logsize);
2656 next_entry = logsize;
84c40692
BC		 2657 }
2658
b7a79404
RC		 2659 size = num_wraps ? capacity : next_entry;
2660
2661 /* bail out if nothing in log */
2662 if (size == 0) {
2663 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2664 return pos;
b7a79404
RC		 2665 }
2666
f37837c9
WYG		 2667 /* enable/disable bt channel announcement */
2668 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2669
c341ddb2 2670#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2671 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2672 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2673 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2674#else
2675 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2676 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2677#endif
2678 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2679 size);
b7a79404 2680
c341ddb2 2681#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2682 if (display) {
2683 if (full_log)
2684 bufsz = capacity * 48;
2685 else
2686 bufsz = size * 48;
2687 *buf = kmalloc(bufsz, GFP_KERNEL);
2688 if (!*buf)
937c397e 2689 return -ENOMEM;
b03d7d0f 2690 }
c341ddb2
WYG		 2691 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2692 /*
2693 * if uCode has wrapped back to top of log,
2694 * start at the oldest entry,
2695 * i.e the next one that uCode would fill.
2696 */
2697 if (num_wraps)
b03d7d0f
WYG		 2698 pos = iwl_print_event_log(priv, next_entry,
2699 capacity - next_entry, mode,
2700 pos, buf, bufsz);
c341ddb2 2701 /* (then/else) start at top of log */
b03d7d0f
WYG		 2702 pos = iwl_print_event_log(priv, 0,
2703 next_entry, mode, pos, buf, bufsz);
c341ddb2 2704 } else
b03d7d0f
WYG		 2705 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2706 next_entry, size, mode,
2707 pos, buf, bufsz);
c341ddb2 2708#else
b03d7d0f
WYG		 2709 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2710 next_entry, size, mode,
2711 pos, buf, bufsz);
b7a79404 2712#endif
b03d7d0f 2713 return pos;
c341ddb2 2714}
b7a79404 2715
0975cc8f
WYG		 2716static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2717{
2718 struct iwl_ct_kill_config cmd;
2719 struct iwl_ct_kill_throttling_config adv_cmd;
2720 unsigned long flags;
2721 int ret = 0;
2722
2723 spin_lock_irqsave(&priv->lock, flags);
2724 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2725 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2726 spin_unlock_irqrestore(&priv->lock, flags);
2727 priv->thermal_throttle.ct_kill_toggle = false;
2728
2729 if (priv->cfg->support_ct_kill_exit) {
2730 adv_cmd.critical_temperature_enter =
2731 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2732 adv_cmd.critical_temperature_exit =
2733 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2734
2735 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2736 sizeof(adv_cmd), &adv_cmd);
2737 if (ret)
2738 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2739 else
2740 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2741 "succeeded, "
2742 "critical temperature enter is %d,"
2743 "exit is %d\n",
2744 priv->hw_params.ct_kill_threshold,
2745 priv->hw_params.ct_kill_exit_threshold);
2746 } else {
2747 cmd.critical_temperature_R =
2748 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2749
2750 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2751 sizeof(cmd), &cmd);
2752 if (ret)
2753 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2754 else
2755 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2756 "succeeded, "
2757 "critical temperature is %d\n",
2758 priv->hw_params.ct_kill_threshold);
2759 }
2760}
2761
b481de9c 2762/**
4a4a9e81 2763 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2764 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2765 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2766 */
4a4a9e81 2767static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2768{
57aab75a 2769 int ret = 0;
246ed355 2770 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 2771
e1623446 2772 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2773
2774 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2775 /* We had an error bringing up the hardware, so take it
2776 * all the way back down so we can try again */
e1623446 2777 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2778 goto restart;
2779 }
2780
2781 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2782 * This is a paranoid check, because we would not have gotten the
2783 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2784 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2785 /* Runtime instruction load was bad;
2786 * take it all the way back down so we can try again */
e1623446 2787 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2788 goto restart;
2789 }
2790
57aab75a
TW		 2791 ret = priv->cfg->ops->lib->alive_notify(priv);
2792 if (ret) {
39aadf8c
WT		 2793 IWL_WARN(priv,
2794 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2795 goto restart;
2796 }
2797
5b9f8cd3 2798 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2799 set_bit(STATUS_ALIVE, &priv->status);
2800
b74e31a9
WYG		 2801 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2802 /* Enable timer to monitor the driver queues */
2803 mod_timer(&priv->monitor_recover,
2804 jiffies +
2805 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2806 }
2807
fee1247a 2808 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2809 return;
2810
36d6825b 2811 ieee80211_wake_queues(priv->hw);
b481de9c 2812
470ab2dd 2813 priv->active_rate = IWL_RATES_MASK;
b481de9c 2814
2f748dec
WYG		 2815 /* Configure Tx antenna selection based on H/W config */
2816 if (priv->cfg->ops->hcmd->set_tx_ant)
2817 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2818
246ed355 2819 if (iwl_is_associated_ctx(ctx)) {
c1adf9fb 2820 struct iwl_rxon_cmd *active_rxon =
246ed355 2821 (struct iwl_rxon_cmd *)&ctx->active;
019fb97d 2822 /* apply any changes in staging */
246ed355 2823 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2824 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2825 } else {
2826 /* Initialize our rx_config data */
1dda6d28 2827 iwl_connection_init_rx_config(priv, NULL);
45823531
AK		 2828
2829 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 2830 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c
ZY		 2831 }
2832
aeb4a2ee
WYG		 2833 if (!priv->cfg->advanced_bt_coexist) {
2834 /* Configure Bluetooth device coexistence support */
2835 priv->cfg->ops->hcmd->send_bt_config(priv);
2836 }
b481de9c 2837
4a4a9e81
TW		 2838 iwl_reset_run_time_calib(priv);
2839
b481de9c 2840 /* Configure the adapter for unassociated operation */
246ed355 2841 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 2842
2843 /* At this point, the NIC is initialized and operational */
47f4a587 2844 iwl_rf_kill_ct_config(priv);
5a66926a 2845
e932a609 2846 iwl_leds_init(priv);
fe00b5a5 2847
e1623446 2848 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2849 set_bit(STATUS_READY, &priv->status);
5a66926a 2850 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2851
e312c24c 2852 iwl_power_update_mode(priv, true);
7e246191
RC		 2853 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2854
c46fbefa 2855
b481de9c
ZY		 2856 return;
2857
2858 restart:
2859 queue_work(priv->workqueue, &priv->restart);
2860}
2861
4e39317d 2862static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2863
5b9f8cd3 2864static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2865{
2866 unsigned long flags;
2867 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2868
e1623446 2869 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2870
b481de9c
ZY		 2871 if (!exit_pending)
2872 set_bit(STATUS_EXIT_PENDING, &priv->status);
2873
b62177a0
SG		 2874 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2875 * to prevent rearm timer */
2876 if (priv->cfg->ops->lib->recover_from_tx_stall)
2877 del_timer_sync(&priv->monitor_recover);
2878
dcef732c 2879 iwl_clear_ucode_stations(priv, NULL);
a194e324 2880 iwl_dealloc_bcast_stations(priv);
db125c78 2881 iwl_clear_driver_stations(priv);
b481de9c 2882
a1174138 2883 /* reset BT coex data */
da5dbb97 2884 priv->bt_status = 0;
a4b96cc4 2885 priv->bt_traffic_load = priv->cfg->bt_init_traffic_load;
a1174138 2886 priv->bt_sco_active = false;
bee008b7
WYG		 2887 priv->bt_full_concurrent = false;
2888 priv->bt_ci_compliance = 0;
a1174138 2889
b481de9c
ZY		 2890 /* Unblock any waiting calls */
2891 wake_up_interruptible_all(&priv->wait_command_queue);
2892
b481de9c
ZY		 2893 /* Wipe out the EXIT_PENDING status bit if we are not actually
2894 * exiting the module */
2895 if (!exit_pending)
2896 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2897
2898 /* stop and reset the on-board processor */
3395f6e9 2899 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2900
2901 /* tell the device to stop sending interrupts */
0359facc 2902 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2903 iwl_disable_interrupts(priv);
0359facc
MA		 2904 spin_unlock_irqrestore(&priv->lock, flags);
2905 iwl_synchronize_irq(priv);
b481de9c
ZY		 2906
2907 if (priv->mac80211_registered)
2908 ieee80211_stop_queues(priv->hw);
2909
5b9f8cd3 2910 /* If we have not previously called iwl_init() then
a60e77e5 2911 * clear all bits but the RF Kill bit and return */
fee1247a 2912 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2913 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2914 STATUS_RF_KILL_HW |
9788864e
RC		 2915 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2916 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2917 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2918 STATUS_EXIT_PENDING;
b481de9c
ZY		 2919 goto exit;
2920 }
2921
6da3a13e 2922 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2923 * bit and continue taking the NIC down. */
b481de9c
ZY		 2924 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2925 STATUS_RF_KILL_HW |
9788864e
RC		 2926 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2927 STATUS_GEO_CONFIGURED |
b481de9c 2928 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2929 STATUS_FW_ERROR |
2930 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2931 STATUS_EXIT_PENDING;
b481de9c 2932
ef850d7c
MA		 2933 /* device going down, Stop using ICT table */
2934 iwl_disable_ict(priv);
b481de9c 2935
74bcdb33 2936 iwlagn_txq_ctx_stop(priv);
54b81550 2937 iwlagn_rxq_stop(priv);
b481de9c 2938
309e731a
BC		 2939 /* Power-down device's busmaster DMA clocks */
2940 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2941 udelay(5);
2942
309e731a
BC		 2943 /* Make sure (redundant) we've released our request to stay awake */
2944 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2945
4d2ccdb9
BC		 2946 /* Stop the device, and put it in low power state */
2947 priv->cfg->ops->lib->apm_ops.stop(priv);
2948
b481de9c 2949 exit:
885ba202 2950 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 2951
2952 if (priv->ibss_beacon)
2953 dev_kfree_skb(priv->ibss_beacon);
2954 priv->ibss_beacon = NULL;
2955
2956 /* clear out any free frames */
fcab423d 2957 iwl_clear_free_frames(priv);
b481de9c
ZY		 2958}
2959
5b9f8cd3 2960static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2961{
2962 mutex_lock(&priv->mutex);
5b9f8cd3 2963 __iwl_down(priv);
b481de9c 2964 mutex_unlock(&priv->mutex);
b24d22b1 2965
4e39317d 2966 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2967}
2968
086ed117
MA		 2969#define HW_READY_TIMEOUT (50)
2970
2971static int iwl_set_hw_ready(struct iwl_priv *priv)
2972{
2973 int ret = 0;
2974
2975 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2976 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2977
2978 /* See if we got it */
2979 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2980 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2981 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2982 HW_READY_TIMEOUT);
2983 if (ret != -ETIMEDOUT)
2984 priv->hw_ready = true;
2985 else
2986 priv->hw_ready = false;
2987
2988 IWL_DEBUG_INFO(priv, "hardware %s\n",
2989 (priv->hw_ready == 1) ? "ready" : "not ready");
2990 return ret;
2991}
2992
2993static int iwl_prepare_card_hw(struct iwl_priv *priv)
2994{
2995 int ret = 0;
2996
91dd6c27 2997 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2998
3354a0f6
MA		 2999 ret = iwl_set_hw_ready(priv);
3000 if (priv->hw_ready)
3001 return ret;
3002
3003 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 3004 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3005 CSR_HW_IF_CONFIG_REG_PREPARE);
3006
3007 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3008 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
3009 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
3010
3354a0f6 3011 /* HW should be ready by now, check again. */
086ed117
MA		 3012 if (ret != -ETIMEDOUT)
3013 iwl_set_hw_ready(priv);
3014
3015 return ret;
3016}
3017
b481de9c
ZY		 3018#define MAX_HW_RESTARTS 5
3019
5b9f8cd3 3020static int __iwl_up(struct iwl_priv *priv)
b481de9c 3021{
a194e324 3022 struct iwl_rxon_context *ctx;
57aab75a
TW		 3023 int i;
3024 int ret;
b481de9c
ZY		 3025
3026 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 3027 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 3028 return -EIO;
3029 }
3030
e903fbd4 3031 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 3032 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 3033 return -EIO;
3034 }
3035
a194e324
JB		 3036 for_each_context(priv, ctx) {
3037 ret = iwl_alloc_bcast_station(priv, ctx, true);
3038 if (ret) {
3039 iwl_dealloc_bcast_stations(priv);
3040 return ret;
3041 }
3042 }
2c810ccd 3043
086ed117
MA		 3044 iwl_prepare_card_hw(priv);
3045
3046 if (!priv->hw_ready) {
3047 IWL_WARN(priv, "Exit HW not ready\n");
3048 return -EIO;
3049 }
3050
e655b9f0 3051 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 3052 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 3053 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3054 else
e655b9f0 3055 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3056
c1842d61 3057 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 3058 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3059
5b9f8cd3 3060 iwl_enable_interrupts(priv);
a60e77e5 3061 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 3062 return 0;
b481de9c
ZY		 3063 }
3064
3395f6e9 3065 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 3066
13bb9483 3067 /* must be initialised before iwl_hw_nic_init */
751ca305
JB		 3068 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3069 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3070 else
3071 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
13bb9483 3072
74bcdb33 3073 ret = iwlagn_hw_nic_init(priv);
57aab75a 3074 if (ret) {
15b1687c 3075 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 3076 return ret;
b481de9c
ZY		 3077 }
3078
3079 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3080 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3081 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 3082 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3083
3084 /* clear (again), then enable host interrupts */
3395f6e9 3085 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 3086 iwl_enable_interrupts(priv);
b481de9c
ZY		 3087
3088 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3089 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3090 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3091
3092 /* Copy original ucode data image from disk into backup cache.
3093 * This will be used to initialize the on-board processor's
3094 * data SRAM for a clean start when the runtime program first loads. */
3095 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 3096 priv->ucode_data.len);
b481de9c 3097
b481de9c
ZY		 3098 for (i = 0; i < MAX_HW_RESTARTS; i++) {
3099
b481de9c
ZY		 3100 /* load bootstrap state machine,
3101 * load bootstrap program into processor's memory,
3102 * prepare to load the "initialize" uCode */
57aab75a 3103 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 3104
57aab75a 3105 if (ret) {
15b1687c
WT		 3106 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3107 ret);
b481de9c
ZY		 3108 continue;
3109 }
3110
3111 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 3112 iwl_nic_start(priv);
b481de9c 3113
e1623446 3114 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 3115
3116 return 0;
3117 }
3118
3119 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 3120 __iwl_down(priv);
64e72c3e 3121 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 3122
3123 /* tried to restart and config the device for as long as our
3124 * patience could withstand */
15b1687c 3125 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 3126 return -EIO;
3127}
3128
3129
3130/*****************************************************************************
3131 *
3132 * Workqueue callbacks
3133 *
3134 *****************************************************************************/
3135
4a4a9e81 3136static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 3137{
c79dd5b5
TW		 3138 struct iwl_priv *priv =
3139 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 3140
3141 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3142 return;
3143
3144 mutex_lock(&priv->mutex);
f3ccc08c 3145 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 3146 mutex_unlock(&priv->mutex);
3147}
3148
4a4a9e81 3149static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 3150{
c79dd5b5
TW		 3151 struct iwl_priv *priv =
3152 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 3153
3154 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3155 return;
3156
258c44a0
MA		 3157 /* enable dram interrupt */
3158 iwl_reset_ict(priv);
3159
b481de9c 3160 mutex_lock(&priv->mutex);
4a4a9e81 3161 iwl_alive_start(priv);
b481de9c
ZY		 3162 mutex_unlock(&priv->mutex);
3163}
3164
16e727e8
EG		 3165static void iwl_bg_run_time_calib_work(struct work_struct *work)
3166{
3167 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3168 run_time_calib_work);
3169
3170 mutex_lock(&priv->mutex);
3171
3172 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3173 test_bit(STATUS_SCANNING, &priv->status)) {
3174 mutex_unlock(&priv->mutex);
3175 return;
3176 }
3177
3178 if (priv->start_calib) {
7980fba5
WYG		 3179 if (priv->cfg->bt_statistics) {
3180 iwl_chain_noise_calibration(priv,
3181 (void *)&priv->_agn.statistics_bt);
3182 iwl_sensitivity_calibration(priv,
3183 (void *)&priv->_agn.statistics_bt);
3184 } else {
3185 iwl_chain_noise_calibration(priv,
3186 (void *)&priv->_agn.statistics);
3187 iwl_sensitivity_calibration(priv,
3188 (void *)&priv->_agn.statistics);
3189 }
16e727e8
EG		 3190 }
3191
3192 mutex_unlock(&priv->mutex);
16e727e8
EG		 3193}
3194
5b9f8cd3 3195static void iwl_bg_restart(struct work_struct *data)
b481de9c 3196{
c79dd5b5 3197 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 3198
3199 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3200 return;
3201
19cc1087 3202 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
8bd413e6 3203 struct iwl_rxon_context *ctx;
bee008b7
WYG		 3204 bool bt_sco, bt_full_concurrent;
3205 u8 bt_ci_compliance;
511b082d 3206 u8 bt_load;
da5dbb97 3207 u8 bt_status;
511b082d 3208
19cc1087 3209 mutex_lock(&priv->mutex);
8bd413e6
JB		 3210 for_each_context(priv, ctx)
3211 ctx->vif = NULL;
19cc1087 3212 priv->is_open = 0;
511b082d
JB		 3213
3214 /*
3215 * __iwl_down() will clear the BT status variables,
3216 * which is correct, but when we restart we really
3217 * want to keep them so restore them afterwards.
3218 *
3219 * The restart process will later pick them up and
3220 * re-configure the hw when we reconfigure the BT
3221 * command.
3222 */
3223 bt_sco = priv->bt_sco_active;
bee008b7
WYG		 3224 bt_full_concurrent = priv->bt_full_concurrent;
3225 bt_ci_compliance = priv->bt_ci_compliance;
511b082d 3226 bt_load = priv->bt_traffic_load;
da5dbb97 3227 bt_status = priv->bt_status;
511b082d 3228
a1174138 3229 __iwl_down(priv);
511b082d
JB		 3230
3231 priv->bt_sco_active = bt_sco;
bee008b7
WYG		 3232 priv->bt_full_concurrent = bt_full_concurrent;
3233 priv->bt_ci_compliance = bt_ci_compliance;
511b082d 3234 priv->bt_traffic_load = bt_load;
da5dbb97 3235 priv->bt_status = bt_status;
511b082d 3236
19cc1087 3237 mutex_unlock(&priv->mutex);
a1174138 3238 iwl_cancel_deferred_work(priv);
19cc1087
JB		 3239 ieee80211_restart_hw(priv->hw);
3240 } else {
3241 iwl_down(priv);
80676518
JB		 3242
3243 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3244 return;
3245
3246 mutex_lock(&priv->mutex);
3247 __iwl_up(priv);
3248 mutex_unlock(&priv->mutex);
19cc1087 3249 }
b481de9c
ZY		 3250}
3251
5b9f8cd3 3252static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3253{
c79dd5b5
TW		 3254 struct iwl_priv *priv =
3255 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3256
3257 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3258 return;
3259
3260 mutex_lock(&priv->mutex);
54b81550 3261 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3262 mutex_unlock(&priv->mutex);
3263}
3264
7878a5a4
MA		 3265#define IWL_DELAY_NEXT_SCAN (HZ*2)
3266
1dda6d28 3267void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3268{
246ed355 3269 struct iwl_rxon_context *ctx;
b481de9c 3270 struct ieee80211_conf *conf = NULL;
857485c0 3271 int ret = 0;
b481de9c 3272
1dda6d28
JB		 3273 if (!vif || !priv->is_open)
3274 return;
3275
246ed355
JB		 3276 ctx = iwl_rxon_ctx_from_vif(vif);
3277
1dda6d28 3278 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 3279 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 3280 return;
3281 }
3282
b481de9c
ZY		 3283 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3284 return;
3285
2a421b91 3286 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 3287
b481de9c
ZY		 3288 conf = ieee80211_get_hw_conf(priv->hw);
3289
246ed355
JB		 3290 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3291 iwlcore_commit_rxon(priv, ctx);
b481de9c 3292
948f5a2f 3293 ret = iwl_send_rxon_timing(priv, vif);
857485c0 3294 if (ret)
8f2d3d2a 3295 IWL_WARN(priv, "RXON timing - "
b481de9c
ZY		 3296 "Attempting to continue.\n");
3297
246ed355 3298 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3299
42eb7c64 3300 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 3301
45823531 3302 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3303 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
45823531 3304
246ed355 3305 ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3306
e1623446 3307 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3308 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3309
c213d745 3310 if (vif->bss_conf.use_short_preamble)
246ed355 3311 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3312 else
246ed355 3313 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3314
246ed355 3315 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3316 if (vif->bss_conf.use_short_slot)
246ed355 3317 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3318 else
246ed355 3319 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3320 }
3321
246ed355 3322 iwlcore_commit_rxon(priv, ctx);
b481de9c 3323
fe6b23dd 3324 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
246ed355 3325 vif->bss_conf.aid, ctx->active.bssid_addr);
fe6b23dd 3326
1dda6d28 3327 switch (vif->type) {
05c914fe 3328 case NL80211_IFTYPE_STATION:
b481de9c 3329 break;
05c914fe 3330 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 3331 iwl_send_beacon_cmd(priv);
b481de9c 3332 break;
b481de9c 3333 default:
15b1687c 3334 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 3335 __func__, vif->type);
b481de9c
ZY		 3336 break;
3337 }
3338
04816448
GE		 3339 /* the chain noise calibration will enabled PM upon completion
3340 * If chain noise has already been run, then we need to enable
3341 * power management here */
3342 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 3343 iwl_power_update_mode(priv, false);
c90a74ba
EG		 3344
3345 /* Enable Rx differential gain and sensitivity calibrations */
3346 iwl_chain_noise_reset(priv);
3347 priv->start_calib = 1;
3348
508e32e1
RC		 3349}
3350
b481de9c
ZY		 3351/*****************************************************************************
3352 *
3353 * mac80211 entry point functions
3354 *
3355 *****************************************************************************/
3356
154b25ce 3357#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3358
f0b6e2e8
RC		 3359/*
3360 * Not a mac80211 entry point function, but it fits in with all the
3361 * other mac80211 functions grouped here.
3362 */
dd7a2509
JB		 3363static int iwl_mac_setup_register(struct iwl_priv *priv,
3364 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3365{
3366 int ret;
3367 struct ieee80211_hw *hw = priv->hw;
3368 hw->rate_control_algorithm = "iwl-agn-rs";
3369
3370 /* Tell mac80211 our characteristics */
3371 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8 3372 IEEE80211_HW_AMPDU_AGGREGATION |
2491fa42 3373 IEEE80211_HW_NEED_DTIM_PERIOD |
f0b6e2e8
RC		 3374 IEEE80211_HW_SPECTRUM_MGMT;
3375
3376 if (!priv->cfg->broken_powersave)
3377 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3378 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3379
ba37a3d0
JB		 3380 if (priv->cfg->sku & IWL_SKU_N)
3381 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3382 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3383
8d9698b3 3384 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3385 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3386
f0b6e2e8
RC		 3387 hw->wiphy->interface_modes =
3388 BIT(NL80211_IFTYPE_STATION) |
3389 BIT(NL80211_IFTYPE_ADHOC);
3390
f6c8f152 3391 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3392 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3393
3394 /*
3395 * For now, disable PS by default because it affects
3396 * RX performance significantly.
3397 */
5be83de5 3398 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3399
1382c71c 3400 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3401 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3402 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3403
3404 /* Default value; 4 EDCA QOS priorities */
3405 hw->queues = 4;
3406
3407 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3408
3409 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3410 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3411 &priv->bands[IEEE80211_BAND_2GHZ];
3412 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3413 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3414 &priv->bands[IEEE80211_BAND_5GHZ];
3415
3416 ret = ieee80211_register_hw(priv->hw);
3417 if (ret) {
3418 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3419 return ret;
3420 }
3421 priv->mac80211_registered = 1;
3422
3423 return 0;
3424}
3425
3426
5b9f8cd3 3427static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 3428{
c79dd5b5 3429 struct iwl_priv *priv = hw->priv;
5a66926a 3430 int ret;
b481de9c 3431
e1623446 3432 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3433
3434 /* we should be verifying the device is ready to be opened */
3435 mutex_lock(&priv->mutex);
5b9f8cd3 3436 ret = __iwl_up(priv);
b481de9c 3437 mutex_unlock(&priv->mutex);
5a66926a 3438
e655b9f0 3439 if (ret)
6cd0b1cb 3440 return ret;
e655b9f0 3441
c1842d61
TW		 3442 if (iwl_is_rfkill(priv))
3443 goto out;
3444
e1623446 3445 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3446
fe9b6b72 3447 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3448 * mac80211 will not be run successfully. */
154b25ce
EG		 3449 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3450 test_bit(STATUS_READY, &priv->status),
3451 UCODE_READY_TIMEOUT);
3452 if (!ret) {
3453 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3454 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3455 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3456 return -ETIMEDOUT;
5a66926a 3457 }
fe9b6b72 3458 }
0a078ffa 3459
e932a609
JB		 3460 iwl_led_start(priv);
3461
c1842d61 3462out:
0a078ffa 3463 priv->is_open = 1;
e1623446 3464 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3465 return 0;
3466}
3467
5b9f8cd3 3468static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 3469{
c79dd5b5 3470 struct iwl_priv *priv = hw->priv;
b481de9c 3471
e1623446 3472 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3473
19cc1087 3474 if (!priv->is_open)
e655b9f0 3475 return;
e655b9f0 3476
b481de9c 3477 priv->is_open = 0;
5a66926a 3478
5bddf549 3479 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY		 3480 /* stop mac, cancel any scan request and clear
3481 * RXON_FILTER_ASSOC_MSK BIT
3482 */
5a66926a 3483 mutex_lock(&priv->mutex);
2a421b91 3484 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3485 mutex_unlock(&priv->mutex);
fde3571f
MA		 3486 }
3487
5b9f8cd3 3488 iwl_down(priv);
5a66926a
ZY		 3489
3490 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3491
3492 /* enable interrupts again in order to receive rfkill changes */
3493 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3494 iwl_enable_interrupts(priv);
948c171c 3495
e1623446 3496 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3497}
3498
5b9f8cd3 3499static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3500{
c79dd5b5 3501 struct iwl_priv *priv = hw->priv;
b481de9c 3502
e1623446 3503 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3504
e1623446 3505 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3506 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3507
74bcdb33 3508 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3509 dev_kfree_skb_any(skb);
3510
e1623446 3511 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3512 return NETDEV_TX_OK;
b481de9c
ZY		 3513}
3514
1dda6d28 3515void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3516{
246ed355 3517 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
857485c0 3518 int ret = 0;
b481de9c 3519
76d04815
JB		 3520 lockdep_assert_held(&priv->mutex);
3521
d986bcd1 3522 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 3523 return;
3524
3525 /* The following should be done only at AP bring up */
246ed355 3526 if (!iwl_is_associated_ctx(ctx)) {
b481de9c
ZY		 3527
3528 /* RXON - unassoc (to set timing command) */
246ed355
JB		 3529 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3530 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 3531
3532 /* RXON Timing */
948f5a2f 3533 ret = iwl_send_rxon_timing(priv, vif);
857485c0 3534 if (ret)
8f2d3d2a 3535 IWL_WARN(priv, "RXON timing failed - "
b481de9c
ZY		 3536 "Attempting to continue.\n");
3537
f513dfff
DH		 3538 /* AP has all antennas */
3539 priv->chain_noise_data.active_chains =
3540 priv->hw_params.valid_rx_ant;
3541 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531 3542 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3543 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c 3544
246ed355 3545 ctx->staging.assoc_id = 0;
1dda6d28 3546
c213d745 3547 if (vif->bss_conf.use_short_preamble)
246ed355 3548 ctx->staging.flags |=
b481de9c
ZY		 3549 RXON_FLG_SHORT_PREAMBLE_MSK;
3550 else
246ed355 3551 ctx->staging.flags &=
b481de9c
ZY		 3552 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3553
246ed355 3554 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3555 if (vif->bss_conf.use_short_slot)
246ed355 3556 ctx->staging.flags |=
b481de9c
ZY		 3557 RXON_FLG_SHORT_SLOT_MSK;
3558 else
246ed355 3559 ctx->staging.flags &=
b481de9c 3560 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3561 }
08abc53c
JB		 3562 /* need to send beacon cmd before committing assoc RXON! */
3563 iwl_send_beacon_cmd(priv);
b481de9c 3564 /* restore RXON assoc */
246ed355
JB		 3565 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3566 iwlcore_commit_rxon(priv, ctx);
e1493deb 3567 }
5b9f8cd3 3568 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3569
3570 /* FIXME - we need to add code here to detect a totally new
3571 * configuration, reset the AP, unassoc, rxon timing, assoc,
3572 * clear sta table, add BCAST sta... */
3573}
3574
5b9f8cd3 3575static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3576 struct ieee80211_vif *vif,
3577 struct ieee80211_key_conf *keyconf,
3578 struct ieee80211_sta *sta,
3579 u32 iv32, u16 *phase1key)
ab885f8c 3580{
ab885f8c 3581
9f58671e 3582 struct iwl_priv *priv = hw->priv;
a194e324
JB		 3583 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3584
e1623446 3585 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3586
a194e324 3587 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
b3fbdcf4 3588 iv32, phase1key);
ab885f8c 3589
e1623446 3590 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3591}
3592
5b9f8cd3 3593static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3594 struct ieee80211_vif *vif,
3595 struct ieee80211_sta *sta,
b481de9c
ZY		 3596 struct ieee80211_key_conf *key)
3597{
c79dd5b5 3598 struct iwl_priv *priv = hw->priv;
a194e324 3599 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
c10afb6e 3600 struct iwl_rxon_context *ctx = vif_priv->ctx;
42986796
WT		 3601 int ret;
3602 u8 sta_id;
3603 bool is_default_wep_key = false;
b481de9c 3604
e1623446 3605 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3606
90e8e424 3607 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3608 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3609 return -EOPNOTSUPP;
3610 }
b481de9c 3611
a194e324 3612 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
0af8bcae
JB		 3613 if (sta_id == IWL_INVALID_STATION)
3614 return -EINVAL;
b481de9c 3615
6974e363 3616 mutex_lock(&priv->mutex);
2a421b91 3617 iwl_scan_cancel_timeout(priv, 100);
6974e363 3618
a90178fa
JB		 3619 /*
3620 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3621 * so far, we are in legacy wep mode (group key only), otherwise we are
3622 * in 1X mode.
a90178fa
JB		 3623 * In legacy wep mode, we use another host command to the uCode.
3624 */
97359d12
JB		 3625 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3626 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 3627 !sta) {
6974e363 3628 if (cmd == SET_KEY)
c10afb6e 3629 is_default_wep_key = !ctx->key_mapping_keys;
6974e363 3630 else
ccc038ab
EG		 3631 is_default_wep_key =
3632 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3633 }
052c4b9f 3634
b481de9c 3635 switch (cmd) {
deb09c43 3636 case SET_KEY:
6974e363 3637 if (is_default_wep_key)
2995bafa 3638 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
deb09c43 3639 else
a194e324
JB		 3640 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3641 key, sta_id);
deb09c43 3642
e1623446 3643 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3644 break;
3645 case DISABLE_KEY:
6974e363 3646 if (is_default_wep_key)
c10afb6e 3647 ret = iwl_remove_default_wep_key(priv, ctx, key);
deb09c43 3648 else
c10afb6e 3649 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
deb09c43 3650
e1623446 3651 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3652 break;
3653 default:
deb09c43 3654 ret = -EINVAL;
b481de9c
ZY		 3655 }
3656
72e15d71 3657 mutex_unlock(&priv->mutex);
e1623446 3658 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3659
deb09c43 3660 return ret;
b481de9c
ZY		 3661}
3662
5b9f8cd3 3663static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3664 struct ieee80211_vif *vif,
832f47e3
JB		 3665 enum ieee80211_ampdu_mlme_action action,
3666 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3667{
3668 struct iwl_priv *priv = hw->priv;
4620fefa 3669 int ret = -EINVAL;
d783b061 3670
e1623446 3671 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3672 sta->addr, tid);
d783b061
TW		 3673
3674 if (!(priv->cfg->sku & IWL_SKU_N))
3675 return -EACCES;
3676
4620fefa
JB		 3677 mutex_lock(&priv->mutex);
3678
d783b061
TW		 3679 switch (action) {
3680 case IEEE80211_AMPDU_RX_START:
e1623446 3681 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3682 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3683 break;
d783b061 3684 case IEEE80211_AMPDU_RX_STOP:
e1623446 3685 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3686 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3687 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3688 ret = 0;
3689 break;
d783b061 3690 case IEEE80211_AMPDU_TX_START:
e1623446 3691 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3692 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3693 if (ret == 0) {
3694 priv->_agn.agg_tids_count++;
3695 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3696 priv->_agn.agg_tids_count);
3697 }
4620fefa 3698 break;
d783b061 3699 case IEEE80211_AMPDU_TX_STOP:
e1623446 3700 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3701 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3702 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3703 priv->_agn.agg_tids_count--;
3704 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3705 priv->_agn.agg_tids_count);
3706 }
5c2207c6 3707 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 3708 ret = 0;
94597ab2
JB		 3709 if (priv->cfg->use_rts_for_aggregation) {
3710 struct iwl_station_priv *sta_priv =
3711 (void *) sta->drv_priv;
3712 /*
3713 * switch off RTS/CTS if it was previously enabled
3714 */
3715
3716 sta_priv->lq_sta.lq.general_params.flags &=
3717 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3718 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3719 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
94597ab2 3720 }
4620fefa 3721 break;
f0527971 3722 case IEEE80211_AMPDU_TX_OPERATIONAL:
94597ab2
JB		 3723 if (priv->cfg->use_rts_for_aggregation) {
3724 struct iwl_station_priv *sta_priv =
3725 (void *) sta->drv_priv;
3726
cfecc6b4
WYG		 3727 /*
3728 * switch to RTS/CTS if it is the prefer protection
3729 * method for HT traffic
3730 */
94597ab2
JB		 3731
3732 sta_priv->lq_sta.lq.general_params.flags |=
3733 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3734 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3735 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
cfecc6b4
WYG		 3736 }
3737 ret = 0;
d783b061
TW		 3738 break;
3739 }
4620fefa
JB		 3740 mutex_unlock(&priv->mutex);
3741
3742 return ret;
d783b061 3743}
9f58671e 3744
6ab10ff8
JB		 3745static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3746 struct ieee80211_vif *vif,
3747 enum sta_notify_cmd cmd,
3748 struct ieee80211_sta *sta)
3749{
3750 struct iwl_priv *priv = hw->priv;
3751 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3752 int sta_id;
3753
6ab10ff8 3754 switch (cmd) {
6ab10ff8
JB		 3755 case STA_NOTIFY_SLEEP:
3756 WARN_ON(!sta_priv->client);
3757 sta_priv->asleep = true;
3758 if (atomic_read(&sta_priv->pending_frames) > 0)
3759 ieee80211_sta_block_awake(hw, sta, true);
3760 break;
3761 case STA_NOTIFY_AWAKE:
3762 WARN_ON(!sta_priv->client);
49dcc819
DH		 3763 if (!sta_priv->asleep)
3764 break;
6ab10ff8 3765 sta_priv->asleep = false;
2a87c26b 3766 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3767 if (sta_id != IWL_INVALID_STATION)
3768 iwl_sta_modify_ps_wake(priv, sta_id);
3769 break;
3770 default:
3771 break;
3772 }
3773}
3774
fe6b23dd
RC		 3775static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3776 struct ieee80211_vif *vif,
3777 struct ieee80211_sta *sta)
3778{
3779 struct iwl_priv *priv = hw->priv;
3780 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
a194e324 3781 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
eafdfbd3 3782 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3783 int ret;
3784 u8 sta_id;
3785
3786 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3787 sta->addr);
da5ae1cf
RC		 3788 mutex_lock(&priv->mutex);
3789 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3790 sta->addr);
3791 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3792
3793 atomic_set(&sta_priv->pending_frames, 0);
3794 if (vif->type == NL80211_IFTYPE_AP)
3795 sta_priv->client = true;
3796
a194e324 3797 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
238d781d 3798 is_ap, sta, &sta_id);
fe6b23dd
RC		 3799 if (ret) {
3800 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3801 sta->addr, ret);
3802 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3803 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3804 return ret;
3805 }
3806
fd1af15d
JB		 3807 sta_priv->common.sta_id = sta_id;
3808
fe6b23dd 3809 /* Initialize rate scaling */
91dd6c27 3810 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3811 sta->addr);
3812 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3813 mutex_unlock(&priv->mutex);
fe6b23dd 3814
fd1af15d 3815 return 0;
fe6b23dd
RC		 3816}
3817
79d07325
WYG		 3818static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3819 struct ieee80211_channel_switch *ch_switch)
3820{
3821 struct iwl_priv *priv = hw->priv;
3822 const struct iwl_channel_info *ch_info;
3823 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 3824 struct ieee80211_channel *channel = ch_switch->channel;
79d07325 3825 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
246ed355
JB		 3826 /*
3827 * MULTI-FIXME
3828 * When we add support for multiple interfaces, we need to
3829 * revisit this. The channel switch command in the device
3830 * only affects the BSS context, but what does that really
3831 * mean? And what if we get a CSA on the second interface?
3832 * This needs a lot of work.
3833 */
3834 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
79d07325
WYG		 3835 u16 ch;
3836 unsigned long flags = 0;
3837
3838 IWL_DEBUG_MAC80211(priv, "enter\n");
3839
3840 if (iwl_is_rfkill(priv))
3841 goto out_exit;
3842
3843 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3844 test_bit(STATUS_SCANNING, &priv->status))
3845 goto out_exit;
3846
246ed355 3847 if (!iwl_is_associated_ctx(ctx))
79d07325
WYG		 3848 goto out_exit;
3849
3850 /* channel switch in progress */
3851 if (priv->switch_rxon.switch_in_progress == true)
3852 goto out_exit;
3853
3854 mutex_lock(&priv->mutex);
3855 if (priv->cfg->ops->lib->set_channel_switch) {
3856
aa2dc6b5 3857 ch = channel->hw_value;
246ed355 3858 if (le16_to_cpu(ctx->active.channel) != ch) {
79d07325 3859 ch_info = iwl_get_channel_info(priv,
aa2dc6b5 3860 channel->band,
79d07325
WYG		 3861 ch);
3862 if (!is_channel_valid(ch_info)) {
3863 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3864 goto out;
3865 }
3866 spin_lock_irqsave(&priv->lock, flags);
3867
3868 priv->current_ht_config.smps = conf->smps_mode;
3869
3870 /* Configure HT40 channels */
7e6a5886
JB		 3871 ctx->ht.enabled = conf_is_ht(conf);
3872 if (ctx->ht.enabled) {
79d07325 3873 if (conf_is_ht40_minus(conf)) {
7e6a5886 3874 ctx->ht.extension_chan_offset =
79d07325 3875 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
7e6a5886 3876 ctx->ht.is_40mhz = true;
79d07325 3877 } else if (conf_is_ht40_plus(conf)) {
7e6a5886 3878 ctx->ht.extension_chan_offset =
79d07325 3879 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
7e6a5886 3880 ctx->ht.is_40mhz = true;
79d07325 3881 } else {
7e6a5886 3882 ctx->ht.extension_chan_offset =
79d07325 3883 IEEE80211_HT_PARAM_CHA_SEC_NONE;
7e6a5886 3884 ctx->ht.is_40mhz = false;
79d07325
WYG		 3885 }
3886 } else
7e6a5886 3887 ctx->ht.is_40mhz = false;
79d07325 3888
246ed355
JB		 3889 if ((le16_to_cpu(ctx->staging.channel) != ch))
3890 ctx->staging.flags = 0;
79d07325 3891
246ed355 3892 iwl_set_rxon_channel(priv, channel, ctx);
79d07325 3893 iwl_set_rxon_ht(priv, ht_conf);
246ed355 3894 iwl_set_flags_for_band(priv, ctx, channel->band,
8bd413e6 3895 ctx->vif);
79d07325
WYG		 3896 spin_unlock_irqrestore(&priv->lock, flags);
3897
3898 iwl_set_rate(priv);
3899 /*
3900 * at this point, staging_rxon has the
3901 * configuration for channel switch
3902 */
3903 if (priv->cfg->ops->lib->set_channel_switch(priv,
3904 ch_switch))
3905 priv->switch_rxon.switch_in_progress = false;
3906 }
3907 }
3908out:
3909 mutex_unlock(&priv->mutex);
3910out_exit:
3911 if (!priv->switch_rxon.switch_in_progress)
8bd413e6 3912 ieee80211_chswitch_done(ctx->vif, false);
79d07325
WYG		 3913 IWL_DEBUG_MAC80211(priv, "leave\n");
3914}
3915
8b8ab9d5
JB		 3916static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3917 unsigned int changed_flags,
3918 unsigned int *total_flags,
3919 u64 multicast)
3920{
3921 struct iwl_priv *priv = hw->priv;
3922 __le32 filter_or = 0, filter_nand = 0;
246ed355 3923 struct iwl_rxon_context *ctx;
8b8ab9d5
JB		 3924
3925#define CHK(test, flag) do { \
3926 if (*total_flags & (test)) \
3927 filter_or |= (flag); \
3928 else \
3929 filter_nand |= (flag); \
3930 } while (0)
3931
3932 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3933 changed_flags, *total_flags);
3934
3935 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3936 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3937 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3938
3939#undef CHK
3940
3941 mutex_lock(&priv->mutex);
3942
246ed355
JB		 3943 for_each_context(priv, ctx) {
3944 ctx->staging.filter_flags &= ~filter_nand;
3945 ctx->staging.filter_flags |= filter_or;
3946 iwlcore_commit_rxon(priv, ctx);
3947 }
8b8ab9d5
JB		 3948
3949 mutex_unlock(&priv->mutex);
3950
3951 /*
3952 * Receiving all multicast frames is always enabled by the
3953 * default flags setup in iwl_connection_init_rx_config()
3954 * since we currently do not support programming multicast
3955 * filters into the device.
3956 */
3957 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3958 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3959}
3960
716c74b0
WYG		 3961static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3962{
3963 struct iwl_priv *priv = hw->priv;
3964
3965 mutex_lock(&priv->mutex);
3966 IWL_DEBUG_MAC80211(priv, "enter\n");
3967
3968 /* do not support "flush" */
3969 if (!priv->cfg->ops->lib->txfifo_flush)
3970 goto done;
3971
3972 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3973 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3974 goto done;
3975 }
3976 if (iwl_is_rfkill(priv)) {
3977 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3978 goto done;
3979 }
3980
3981 /*
3982 * mac80211 will not push any more frames for transmit
3983 * until the flush is completed
3984 */
3985 if (drop) {
3986 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3987 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3988 IWL_ERR(priv, "flush request fail\n");
3989 goto done;
3990 }
3991 }
3992 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3993 iwlagn_wait_tx_queue_empty(priv);
3994done:
3995 mutex_unlock(&priv->mutex);
3996 IWL_DEBUG_MAC80211(priv, "leave\n");
3997}
3998
b481de9c
ZY		 3999/*****************************************************************************
4000 *
4001 * driver setup and teardown
4002 *
4003 *****************************************************************************/
4004
4e39317d 4005static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 4006{
d21050c7 4007 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 4008
4009 init_waitqueue_head(&priv->wait_command_queue);
4010
5b9f8cd3
EG		 4011 INIT_WORK(&priv->restart, iwl_bg_restart);
4012 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 4013 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 4014 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 4015 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 4016 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 4017 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4a4a9e81
TW		 4018 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
4019 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 4020
2a421b91 4021 iwl_setup_scan_deferred_work(priv);
bb8c093b 4022
4e39317d
EG		 4023 if (priv->cfg->ops->lib->setup_deferred_work)
4024 priv->cfg->ops->lib->setup_deferred_work(priv);
4025
4026 init_timer(&priv->statistics_periodic);
4027 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 4028 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 4029
a9e1cb6a
WYG		 4030 init_timer(&priv->ucode_trace);
4031 priv->ucode_trace.data = (unsigned long)priv;
4032 priv->ucode_trace.function = iwl_bg_ucode_trace;
4033
b74e31a9
WYG		 4034 if (priv->cfg->ops->lib->recover_from_tx_stall) {
4035 init_timer(&priv->monitor_recover);
4036 priv->monitor_recover.data = (unsigned long)priv;
4037 priv->monitor_recover.function =
4038 priv->cfg->ops->lib->recover_from_tx_stall;
4039 }
4040
ef850d7c
MA		 4041 if (!priv->cfg->use_isr_legacy)
4042 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4043 iwl_irq_tasklet, (unsigned long)priv);
4044 else
4045 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4046 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 4047}
4048
4e39317d 4049static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 4050{
4e39317d
EG		 4051 if (priv->cfg->ops->lib->cancel_deferred_work)
4052 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 4053
3ae6a054 4054 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 4055 cancel_delayed_work(&priv->scan_check);
88be0264 4056 cancel_work_sync(&priv->start_internal_scan);
b481de9c 4057 cancel_delayed_work(&priv->alive_start);
815e629b 4058 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 4059 cancel_work_sync(&priv->beacon_update);
bee008b7 4060 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 4061 cancel_work_sync(&priv->bt_runtime_config);
4e39317d 4062 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 4063 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY		 4064}
4065
89f186a8
RC		 4066static void iwl_init_hw_rates(struct iwl_priv *priv,
4067 struct ieee80211_rate *rates)
4068{
4069 int i;
4070
4071 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4072 rates[i].bitrate = iwl_rates[i].ieee * 5;
4073 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4074 rates[i].hw_value_short = i;
4075 rates[i].flags = 0;
4076 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4077 /*
4078 * If CCK != 1M then set short preamble rate flag.
4079 */
4080 rates[i].flags |=
4081 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4082 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4083 }
4084 }
4085}
4086
4087static int iwl_init_drv(struct iwl_priv *priv)
4088{
4089 int ret;
4090
4091 priv->ibss_beacon = NULL;
4092
89f186a8
RC		 4093 spin_lock_init(&priv->sta_lock);
4094 spin_lock_init(&priv->hcmd_lock);
4095
4096 INIT_LIST_HEAD(&priv->free_frames);
4097
4098 mutex_init(&priv->mutex);
d2dfe6df 4099 mutex_init(&priv->sync_cmd_mutex);
89f186a8 4100
89f186a8
RC		 4101 priv->ieee_channels = NULL;
4102 priv->ieee_rates = NULL;
4103 priv->band = IEEE80211_BAND_2GHZ;
4104
4105 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 4106 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 4107 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 4108 priv->_agn.agg_tids_count = 0;
89f186a8 4109
8a472da4
WYG		 4110 /* initialize force reset */
4111 priv->force_reset[IWL_RF_RESET].reset_duration =
4112 IWL_DELAY_NEXT_FORCE_RF_RESET;
4113 priv->force_reset[IWL_FW_RESET].reset_duration =
4114 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 4115
4116 /* Choose which receivers/antennas to use */
4117 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355
JB		 4118 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4119 &priv->contexts[IWL_RXON_CTX_BSS]);
89f186a8
RC		 4120
4121 iwl_init_scan_params(priv);
4122
22bf59a0
WYG		 4123 /* init bt coex */
4124 if (priv->cfg->advanced_bt_coexist) {
b6e116e8
WYG		 4125 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4126 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4127 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG		 4128 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4129 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4130 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4131 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4132 }
4133
89f186a8
RC		 4134 /* Set the tx_power_user_lmt to the lowest power level
4135 * this value will get overwritten by channel max power avg
4136 * from eeprom */
b744cb79 4137 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 4138
4139 ret = iwl_init_channel_map(priv);
4140 if (ret) {
4141 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4142 goto err;
4143 }
4144
4145 ret = iwlcore_init_geos(priv);
4146 if (ret) {
4147 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4148 goto err_free_channel_map;
4149 }
4150 iwl_init_hw_rates(priv, priv->ieee_rates);
4151
4152 return 0;
4153
4154err_free_channel_map:
4155 iwl_free_channel_map(priv);
4156err:
4157 return ret;
4158}
4159
4160static void iwl_uninit_drv(struct iwl_priv *priv)
4161{
4162 iwl_calib_free_results(priv);
4163 iwlcore_free_geos(priv);
4164 iwl_free_channel_map(priv);
811ecc99 4165 kfree(priv->scan_cmd);
89f186a8
RC		 4166}
4167
5b9f8cd3
EG		 4168static struct ieee80211_ops iwl_hw_ops = {
4169 .tx = iwl_mac_tx,
4170 .start = iwl_mac_start,
4171 .stop = iwl_mac_stop,
4172 .add_interface = iwl_mac_add_interface,
4173 .remove_interface = iwl_mac_remove_interface,
4174 .config = iwl_mac_config,
8b8ab9d5 4175 .configure_filter = iwlagn_configure_filter,
5b9f8cd3
EG		 4176 .set_key = iwl_mac_set_key,
4177 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 4178 .conf_tx = iwl_mac_conf_tx,
4179 .reset_tsf = iwl_mac_reset_tsf,
4180 .bss_info_changed = iwl_bss_info_changed,
4181 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 4182 .hw_scan = iwl_mac_hw_scan,
4183 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 4184 .sta_add = iwlagn_mac_sta_add,
4185 .sta_remove = iwl_mac_sta_remove,
79d07325 4186 .channel_switch = iwl_mac_channel_switch,
716c74b0 4187 .flush = iwl_mac_flush,
a85d7cca 4188 .tx_last_beacon = iwl_mac_tx_last_beacon,
b481de9c
ZY		 4189};
4190
3867fe04
WYG		 4191static void iwl_hw_detect(struct iwl_priv *priv)
4192{
4193 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4194 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4195 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
49ded76b 4196 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3867fe04
WYG		 4197}
4198
07d4f1ad
WYG		 4199static int iwl_set_hw_params(struct iwl_priv *priv)
4200{
4201 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4202 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4203 if (priv->cfg->mod_params->amsdu_size_8K)
4204 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4205 else
4206 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4207
4208 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4209
4210 if (priv->cfg->mod_params->disable_11n)
4211 priv->cfg->sku &= ~IWL_SKU_N;
4212
4213 /* Device-specific setup */
4214 return priv->cfg->ops->lib->set_hw_params(priv);
4215}
4216
e72f368b
JB		 4217static const u8 iwlagn_bss_ac_to_fifo[] = {
4218 IWL_TX_FIFO_VO,
4219 IWL_TX_FIFO_VI,
4220 IWL_TX_FIFO_BE,
4221 IWL_TX_FIFO_BK,
4222};
4223
4224static const u8 iwlagn_bss_ac_to_queue[] = {
4225 0, 1, 2, 3,
4226};
4227
4228static const u8 iwlagn_pan_ac_to_fifo[] = {
4229 IWL_TX_FIFO_VO_IPAN,
4230 IWL_TX_FIFO_VI_IPAN,
4231 IWL_TX_FIFO_BE_IPAN,
4232 IWL_TX_FIFO_BK_IPAN,
4233};
4234
4235static const u8 iwlagn_pan_ac_to_queue[] = {
4236 7, 6, 5, 4,
4237};
4238
5b9f8cd3 4239static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c 4240{
246ed355 4241 int err = 0, i;
c79dd5b5 4242 struct iwl_priv *priv;
b481de9c 4243 struct ieee80211_hw *hw;
82b9a121 4244 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 4245 unsigned long flags;
c6fa17ed 4246 u16 pci_cmd, num_mac;
b481de9c 4247
316c30d9
AK		 4248 /************************
4249 * 1. Allocating HW data
4250 ************************/
4251
6440adb5
CB		 4252 /* Disabling hardware scan means that mac80211 will perform scans
4253 * "the hard way", rather than using device's scan. */
1ea87396 4254 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 4255 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK		 4256 dev_printk(KERN_DEBUG, &(pdev->dev),
4257 "Disabling hw_scan\n");
5b9f8cd3 4258 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 4259 }
4260
5b9f8cd3 4261 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 4262 if (!hw) {
b481de9c
ZY		 4263 err = -ENOMEM;
4264 goto out;
4265 }
1d0a082d
AK		 4266 priv = hw->priv;
4267 /* At this point both hw and priv are allocated. */
4268
246ed355
JB		 4269 /*
4270 * The default context is always valid,
4271 * more may be discovered when firmware
4272 * is loaded.
4273 */
4274 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4275
4276 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4277 priv->contexts[i].ctxid = i;
4278
8f2d3d2a
JB		 4279 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4280 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4281 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 4282 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 4283 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
c10afb6e 4284 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
e72f368b
JB		 4285 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4286 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
ece9c4ee
JB		 4287
4288 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4289 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4290 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4291 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4292 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4293 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4294 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4295 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
e72f368b
JB		 4296 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4297 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4298 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
ece9c4ee
JB		 4299
4300 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
8f2d3d2a 4301
b481de9c
ZY		 4302 SET_IEEE80211_DEV(hw, &pdev->dev);
4303
e1623446 4304 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 4305 priv->cfg = cfg;
b481de9c 4306 priv->pci_dev = pdev;
40cefda9 4307 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 4308
bee008b7
WYG		 4309 /* is antenna coupling more than 35dB ? */
4310 priv->bt_ant_couple_ok =
4311 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4312 true : false;
4313
f37837c9
WYG		 4314 /* enable/disable bt channel announcement */
4315 priv->bt_ch_announce = iwlagn_bt_ch_announce;
4316
20594eb0
WYG		 4317 if (iwl_alloc_traffic_mem(priv))
4318 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4319
316c30d9
AK		 4320 /**************************
4321 * 2. Initializing PCI bus
4322 **************************/
1a7123cd
JL		 4323 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4324 PCIE_LINK_STATE_CLKPM);
4325
316c30d9
AK		 4326 if (pci_enable_device(pdev)) {
4327 err = -ENODEV;
4328 goto out_ieee80211_free_hw;
4329 }
4330
4331 pci_set_master(pdev);
4332
093d874c 4333 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 4334 if (!err)
093d874c 4335 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 4336 if (err) {
093d874c 4337 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4338 if (!err)
093d874c 4339 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4340 /* both attempts failed: */
316c30d9 4341 if (err) {
978785a3 4342 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 4343 goto out_pci_disable_device;
cc2a8ea8 4344 }
316c30d9
AK		 4345 }
4346
4347 err = pci_request_regions(pdev, DRV_NAME);
4348 if (err)
4349 goto out_pci_disable_device;
4350
4351 pci_set_drvdata(pdev, priv);
4352
316c30d9
AK		 4353
4354 /***********************
4355 * 3. Read REV register
4356 ***********************/
4357 priv->hw_base = pci_iomap(pdev, 0, 0);
4358 if (!priv->hw_base) {
4359 err = -ENODEV;
4360 goto out_pci_release_regions;
4361 }
4362
e1623446 4363 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 4364 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4365 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 4366
731a29b7 4367 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 4368 * we should init now
4369 */
4370 spin_lock_init(&priv->reg_lock);
731a29b7 4371 spin_lock_init(&priv->lock);
4843b5a7
RC		 4372
4373 /*
4374 * stop and reset the on-board processor just in case it is in a
4375 * strange state ... like being left stranded by a primary kernel
4376 * and this is now the kdump kernel trying to start up
4377 */
4378 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4379
b661c819 4380 iwl_hw_detect(priv);
c11362c0 4381 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 4382 priv->cfg->name, priv->hw_rev);
316c30d9 4383
e7b63581
TW		 4384 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4385 * PCI Tx retries from interfering with C3 CPU state */
4386 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4387
086ed117
MA		 4388 iwl_prepare_card_hw(priv);
4389 if (!priv->hw_ready) {
4390 IWL_WARN(priv, "Failed, HW not ready\n");
4391 goto out_iounmap;
4392 }
4393
91238714
TW		 4394 /*****************
4395 * 4. Read EEPROM
4396 *****************/
316c30d9
AK		 4397 /* Read the EEPROM */
4398 err = iwl_eeprom_init(priv);
4399 if (err) {
15b1687c 4400 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4401 goto out_iounmap;
4402 }
8614f360
TW		 4403 err = iwl_eeprom_check_version(priv);
4404 if (err)
c8f16138 4405 goto out_free_eeprom;
8614f360 4406
02883017 4407 /* extract MAC Address */
c6fa17ed
WYG		 4408 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4409 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4410 priv->hw->wiphy->addresses = priv->addresses;
4411 priv->hw->wiphy->n_addresses = 1;
4412 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4413 if (num_mac > 1) {
4414 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4415 ETH_ALEN);
4416 priv->addresses[1].addr[5]++;
4417 priv->hw->wiphy->n_addresses++;
4418 }
316c30d9
AK		 4419
4420 /************************
4421 * 5. Setup HW constants
4422 ************************/
da154e30 4423 if (iwl_set_hw_params(priv)) {
15b1687c 4424 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4425 goto out_free_eeprom;
316c30d9
AK		 4426 }
4427
4428 /*******************
6ba87956 4429 * 6. Setup priv
316c30d9 4430 *******************/
b481de9c 4431
6ba87956 4432 err = iwl_init_drv(priv);
bf85ea4f 4433 if (err)
399f4900 4434 goto out_free_eeprom;
bf85ea4f 4435 /* At this point both hw and priv are initialized. */
316c30d9 4436
316c30d9 4437 /********************
09f9bf79 4438 * 7. Setup services
316c30d9 4439 ********************/
0359facc 4440 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4441 iwl_disable_interrupts(priv);
0359facc 4442 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4443
6cd0b1cb
HS		 4444 pci_enable_msi(priv->pci_dev);
4445
ef850d7c
MA		 4446 iwl_alloc_isr_ict(priv);
4447 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4448 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4449 if (err) {
4450 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4451 goto out_disable_msi;
4452 }
316c30d9 4453
4e39317d 4454 iwl_setup_deferred_work(priv);
653fa4a0 4455 iwl_setup_rx_handlers(priv);
316c30d9 4456
158bea07
JB		 4457 /*********************************************
4458 * 8. Enable interrupts and read RFKILL state
4459 *********************************************/
6ba87956 4460
6cd0b1cb
HS		 4461 /* enable interrupts if needed: hw bug w/a */
4462 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4463 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4464 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4465 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4466 }
4467
4468 iwl_enable_interrupts(priv);
4469
6cd0b1cb
HS		 4470 /* If platform's RF_KILL switch is NOT set to KILL */
4471 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4472 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4473 else
4474 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4475
a60e77e5
JB		 4476 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4477 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4478
58d0f361 4479 iwl_power_initialize(priv);
39b73fb1 4480 iwl_tt_initialize(priv);
158bea07 4481
a15707d8 4482 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4483
b08dfd04 4484 err = iwl_request_firmware(priv, true);
158bea07 4485 if (err)
7d47618a 4486 goto out_destroy_workqueue;
158bea07 4487
b481de9c
ZY		 4488 return 0;
4489
7d47618a 4490 out_destroy_workqueue:
c8f16138
RC		 4491 destroy_workqueue(priv->workqueue);
4492 priv->workqueue = NULL;
795cc0ad 4493 free_irq(priv->pci_dev->irq, priv);
ef850d7c 4494 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 4495 out_disable_msi:
4496 pci_disable_msi(priv->pci_dev);
6ba87956 4497 iwl_uninit_drv(priv);
073d3f5f
TW		 4498 out_free_eeprom:
4499 iwl_eeprom_free(priv);
b481de9c
ZY		 4500 out_iounmap:
4501 pci_iounmap(pdev, priv->hw_base);
4502 out_pci_release_regions:
316c30d9 4503 pci_set_drvdata(pdev, NULL);
623d563e 4504 pci_release_regions(pdev);
b481de9c
ZY		 4505 out_pci_disable_device:
4506 pci_disable_device(pdev);
b481de9c 4507 out_ieee80211_free_hw:
20594eb0 4508 iwl_free_traffic_mem(priv);
d7c76f4c 4509 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4510 out:
4511 return err;
4512}
4513
5b9f8cd3 4514static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4515{
c79dd5b5 4516 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4517 unsigned long flags;
b481de9c
ZY		 4518
4519 if (!priv)
4520 return;
4521
a15707d8 4522 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4523
e1623446 4524 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4525
67249625 4526 iwl_dbgfs_unregister(priv);
5b9f8cd3 4527 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4528
5b9f8cd3
EG		 4529 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4530 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4531 * we need to set STATUS_EXIT_PENDING bit.
4532 */
4533 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4534 if (priv->mac80211_registered) {
4535 ieee80211_unregister_hw(priv->hw);
4536 priv->mac80211_registered = 0;
0b124c31 4537 } else {
5b9f8cd3 4538 iwl_down(priv);
c4f55232
RR		 4539 }
4540
c166b25a
BC		 4541 /*
4542 * Make sure device is reset to low power before unloading driver.
4543 * This may be redundant with iwl_down(), but there are paths to
4544 * run iwl_down() without calling apm_ops.stop(), and there are
4545 * paths to avoid running iwl_down() at all before leaving driver.
4546 * This (inexpensive) call *makes sure* device is reset.
4547 */
4548 priv->cfg->ops->lib->apm_ops.stop(priv);
4549
39b73fb1
WYG		 4550 iwl_tt_exit(priv);
4551
0359facc
MA		 4552 /* make sure we flush any pending irq or
4553 * tasklet for the driver
4554 */
4555 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4556 iwl_disable_interrupts(priv);
0359facc
MA		 4557 spin_unlock_irqrestore(&priv->lock, flags);
4558
4559 iwl_synchronize_irq(priv);
4560
5b9f8cd3 4561 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4562
4563 if (priv->rxq.bd)
54b81550 4564 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4565 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4566
073d3f5f 4567 iwl_eeprom_free(priv);
b481de9c 4568
b481de9c 4569
948c171c
MA		 4570 /*netif_stop_queue(dev); */
4571 flush_workqueue(priv->workqueue);
4572
5b9f8cd3 4573 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4574 * priv->workqueue... so we can't take down the workqueue
4575 * until now... */
4576 destroy_workqueue(priv->workqueue);
4577 priv->workqueue = NULL;
20594eb0 4578 iwl_free_traffic_mem(priv);
b481de9c 4579
6cd0b1cb
HS		 4580 free_irq(priv->pci_dev->irq, priv);
4581 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4582 pci_iounmap(pdev, priv->hw_base);
4583 pci_release_regions(pdev);
4584 pci_disable_device(pdev);
4585 pci_set_drvdata(pdev, NULL);
4586
6ba87956 4587 iwl_uninit_drv(priv);
b481de9c 4588
ef850d7c
MA		 4589 iwl_free_isr_ict(priv);
4590
b481de9c
ZY		 4591 if (priv->ibss_beacon)
4592 dev_kfree_skb(priv->ibss_beacon);
4593
4594 ieee80211_free_hw(priv->hw);
4595}
4596
b481de9c
ZY		 4597
4598/*****************************************************************************
4599 *
4600 * driver and module entry point
4601 *
4602 *****************************************************************************/
4603
fed9017e 4604/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4605static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4606#ifdef CONFIG_IWL4965
fed9017e
RR		 4607 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4608 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4609#endif /* CONFIG_IWL4965 */
5a6a256e 4610#ifdef CONFIG_IWL5000
ac592574
WYG		 4611/* 5100 Series WiFi */
4612 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4613 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4614 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4615 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4616 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4617 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4618 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4619 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4620 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4621 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4622 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4623 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4624 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4625 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4626 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4627 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4628 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4629 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4630 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4631 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4632 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4633 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4634 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4635 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4636
4637/* 5300 Series WiFi */
4638 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4639 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4640 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4641 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4642 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4643 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4644 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4645 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4646 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4647 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4648 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4649 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4650
4651/* 5350 Series WiFi/WiMax */
4652 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4653 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4654 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4655
4656/* 5150 Series Wifi/WiMax */
4657 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4658 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4659 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4660 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4661 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4662 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4663
4664 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4665 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4666 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4667 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4668
4669/* 6x00 Series */
5953a62e
WYG		 4670 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4671 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4672 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4673 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4674 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4675 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4676 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4677 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4678 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4679 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4680
95b13014
SZ		 4681/* 6x00 Series Gen2a */
4682 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4683 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4684 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
1808972f
SZ		 4685 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4686 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4687 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4688 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
9f6e1baf
SZ		 4689 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4690 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4691 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4692 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4693 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4694 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4695 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4696
4697/* 6x00 Series Gen2b */
4698 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4699 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4700 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4701 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4702 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4703 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4704 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4705 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4706 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4707 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4708 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
9f6e1baf
SZ		 4709 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4710 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4711 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4712 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4713 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4714 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4715 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4716 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4717 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4718 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4719 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4720 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4721 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4722 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4723 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4724 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4725 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4726
4727/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4728 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4729 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4730 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4731 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4732 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4733 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4734
03264339
SZ		 4735/* 6x50 WiFi/WiMax Series Gen2 */
4736 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4737 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4738 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4739 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4740 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4741 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4742
77dcb6a9 4743/* 1000 Series WiFi */
4bd0914f
WYG		 4744 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4745 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4746 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4747 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4748 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4749 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4750 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4751 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4752 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4753 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4754 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4755 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 4756#endif /* CONFIG_IWL5000 */
7100e924 4757
fed9017e
RR		 4758 {0}
4759};
4760MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4761
4762static struct pci_driver iwl_driver = {
b481de9c 4763 .name = DRV_NAME,
fed9017e 4764 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4765 .probe = iwl_pci_probe,
4766 .remove = __devexit_p(iwl_pci_remove),
b481de9c 4767#ifdef CONFIG_PM
5b9f8cd3
EG		 4768 .suspend = iwl_pci_suspend,
4769 .resume = iwl_pci_resume,
b481de9c
ZY		 4770#endif
4771};
4772
5b9f8cd3 4773static int __init iwl_init(void)
b481de9c
ZY		 4774{
4775
4776 int ret;
c96c31e4
JP		 4777 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4778 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4779
e227ceac 4780 ret = iwlagn_rate_control_register();
897e1cf2 4781 if (ret) {
c96c31e4 4782 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4783 return ret;
4784 }
4785
fed9017e 4786 ret = pci_register_driver(&iwl_driver);
b481de9c 4787 if (ret) {
c96c31e4 4788 pr_err("Unable to initialize PCI module\n");
897e1cf2 4789 goto error_register;
b481de9c 4790 }
b481de9c
ZY		 4791
4792 return ret;
897e1cf2 4793
897e1cf2 4794error_register:
e227ceac 4795 iwlagn_rate_control_unregister();
897e1cf2 4796 return ret;
b481de9c
ZY		 4797}
4798
5b9f8cd3 4799static void __exit iwl_exit(void)
b481de9c 4800{
fed9017e 4801 pci_unregister_driver(&iwl_driver);
e227ceac 4802 iwlagn_rate_control_unregister();
b481de9c
ZY		 4803}
4804
5b9f8cd3
EG		 4805module_exit(iwl_exit);
4806module_init(iwl_init);
a562a9dd
RC		 4807
4808#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4809module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4810MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4811module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4812MODULE_PARM_DESC(debug, "debug output mask");
4813#endif
4814
2b068618
WYG		 4815module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4816MODULE_PARM_DESC(swcrypto50,
4817 "using crypto in software (default 0 [hardware]) (deprecated)");
4818module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4819MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4820module_param_named(queues_num50,
4821 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4822MODULE_PARM_DESC(queues_num50,
4823 "number of hw queues in 50xx series (deprecated)");
4824module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4825MODULE_PARM_DESC(queues_num, "number of hw queues.");
4826module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4827MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4828module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4829MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4830module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4831 int, S_IRUGO);
4832MODULE_PARM_DESC(amsdu_size_8K50,
4833 "enable 8K amsdu size in 50XX series (deprecated)");
4834module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4835 int, S_IRUGO);
4836MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4837module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4838MODULE_PARM_DESC(fw_restart50,
4839 "restart firmware in case of error (deprecated)");
4840module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4841MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4842module_param_named(
4843 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4844MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
dd7a2509
JB		 4845
4846module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4847 S_IRUGO);
4848MODULE_PARM_DESC(ucode_alternative,
4849 "specify ucode alternative to use from ucode file");
bee008b7
WYG		 4850
4851module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4852MODULE_PARM_DESC(antenna_coupling,
4853 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9
WYG		 4854
4855module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4856MODULE_PARM_DESC(bt_ch_announce,
4857 "Enable BT channel announcement mode (default: enable)");
Linux kernel - Deliverables
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