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iwlwifi: disable aspm by default
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY		 34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY		 38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY		 41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY		 45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY		 48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO		 52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
f0832f13 60#include "iwl-calib.h"
a1175124 61#include "iwl-agn.h"
b481de9c 62
416e1438 63
b481de9c
ZY		 64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
b481de9c
ZY		 70/*
71 * module name, copyright, version, etc.
b481de9c 72 */
d783b061 73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 74
0a6857e7 75#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 76#define VD "d"
77#else
78#define VD
79#endif
80
81963d68 81#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 82
b481de9c
ZY		 83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/**
5b9f8cd3 91 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 92 *
01ebd063 93 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 94 * the active_rxon structure is updated with the new data. This
95 * function correctly transitions out of the RXON_ASSOC_MSK state if
96 * a HW tune is required based on the RXON structure changes.
97 */
e0158e61 98int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY		 99{
100 /* cast away the const for active_rxon in this function */
c1adf9fb 101 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG		 102 int ret;
103 bool new_assoc =
104 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 105
fee1247a 106 if (!iwl_is_alive(priv))
43d59b32 107 return -EBUSY;
b481de9c
ZY		 108
109 /* always get timestamp with Rx frame */
110 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
111
8ccde88a 112 ret = iwl_check_rxon_cmd(priv);
43d59b32 113 if (ret) {
15b1687c 114 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 115 return -EINVAL;
116 }
117
0924e519
WYG		 118 /*
119 * receive commit_rxon request
120 * abort any previous channel switch if still in process
121 */
122 if (priv->switch_rxon.switch_in_progress &&
123 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
124 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
125 le16_to_cpu(priv->switch_rxon.channel));
79d07325 126 iwl_chswitch_done(priv, false);
0924e519
WYG		 127 }
128
b481de9c 129 /* If we don't need to send a full RXON, we can use
5b9f8cd3 130 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 131 * and other flags for the current radio configuration. */
54559703 132 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG		 133 ret = iwl_send_rxon_assoc(priv);
134 if (ret) {
15b1687c 135 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 136 return ret;
b481de9c
ZY		 137 }
138
139 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 140 iwl_print_rx_config_cmd(priv);
b481de9c
ZY		 141 return 0;
142 }
143
b481de9c
ZY		 144 /* If we are currently associated and the new config requires
145 * an RXON_ASSOC and the new config wants the associated mask enabled,
146 * we must clear the associated from the active configuration
147 * before we apply the new config */
43d59b32 148 if (iwl_is_associated(priv) && new_assoc) {
e1623446 149 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 150 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
151
43d59b32 152 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 153 sizeof(struct iwl_rxon_cmd),
b481de9c
ZY		 154 &priv->active_rxon);
155
156 /* If the mask clearing failed then we set
157 * active_rxon back to what it was previously */
43d59b32 158 if (ret) {
b481de9c 159 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 160 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 161 return ret;
b481de9c 162 }
2c810ccd 163 iwl_clear_ucode_stations(priv);
7e246191 164 iwl_restore_stations(priv);
335348b1
JB		 165 ret = iwl_restore_default_wep_keys(priv);
166 if (ret) {
167 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
168 return ret;
169 }
b481de9c
ZY		 170 }
171
e1623446 172 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 173 "* with%s RXON_FILTER_ASSOC_MSK\n"
174 "* channel = %d\n"
e174961c 175 "* bssid = %pM\n",
43d59b32 176 (new_assoc ? "" : "out"),
b481de9c 177 le16_to_cpu(priv->staging_rxon.channel),
e174961c 178 priv->staging_rxon.bssid_addr);
b481de9c 179
90e8e424 180 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG		 181
182 /* Apply the new configuration
7e246191
RC		 183 * RXON unassoc clears the station table in uCode so restoration of
184 * stations is needed after it (the RXON command) completes
43d59b32
EG		 185 */
186 if (!new_assoc) {
187 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 188 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 189 if (ret) {
15b1687c 190 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 191 return ret;
192 }
91dd6c27 193 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
43d59b32 194 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
2c810ccd 195 iwl_clear_ucode_stations(priv);
7e246191 196 iwl_restore_stations(priv);
335348b1
JB		 197 ret = iwl_restore_default_wep_keys(priv);
198 if (ret) {
199 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
200 return ret;
201 }
b481de9c
ZY		 202 }
203
19cc1087 204 priv->start_calib = 0;
9185159d 205 if (new_assoc) {
47eef9bd
WYG		 206 /*
207 * allow CTS-to-self if possible for new association.
208 * this is relevant only for 5000 series and up,
209 * but will not damage 4965
210 */
211 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
212
43d59b32
EG		 213 /* Apply the new configuration
214 * RXON assoc doesn't clear the station table in uCode,
215 */
216 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
217 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
218 if (ret) {
15b1687c 219 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 220 return ret;
221 }
222 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 223 }
a643565e 224 iwl_print_rx_config_cmd(priv);
b481de9c 225
36da7d70
ZY		 226 iwl_init_sensitivity(priv);
227
228 /* If we issue a new RXON command which required a tune then we must
229 * send a new TXPOWER command or we won't be able to Tx any frames */
230 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
231 if (ret) {
15b1687c 232 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 233 return ret;
234 }
235
b481de9c
ZY		 236 return 0;
237}
238
5b9f8cd3 239void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA		 240{
241
45823531
AK		 242 if (priv->cfg->ops->hcmd->set_rxon_chain)
243 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 244 iwlcore_commit_rxon(priv);
5da4b55f
MA		 245}
246
fcab423d 247static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 248{
249 struct list_head *element;
250
e1623446 251 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 252 priv->frames_count);
253
254 while (!list_empty(&priv->free_frames)) {
255 element = priv->free_frames.next;
256 list_del(element);
fcab423d 257 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 258 priv->frames_count--;
259 }
260
261 if (priv->frames_count) {
39aadf8c 262 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 263 priv->frames_count);
264 priv->frames_count = 0;
265 }
266}
267
fcab423d 268static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 269{
fcab423d 270 struct iwl_frame *frame;
b481de9c
ZY		 271 struct list_head *element;
272 if (list_empty(&priv->free_frames)) {
273 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
274 if (!frame) {
15b1687c 275 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 276 return NULL;
277 }
278
279 priv->frames_count++;
280 return frame;
281 }
282
283 element = priv->free_frames.next;
284 list_del(element);
fcab423d 285 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 286}
287
fcab423d 288static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 289{
290 memset(frame, 0, sizeof(*frame));
291 list_add(&frame->list, &priv->free_frames);
292}
293
47ff65c4 294static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 295 struct ieee80211_hdr *hdr,
73ec1cc2 296 int left)
b481de9c 297{
6abbe554 298 if (!priv->ibss_beacon)
b481de9c
ZY		 299 return 0;
300
301 if (priv->ibss_beacon->len > left)
302 return 0;
303
304 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
305
306 return priv->ibss_beacon->len;
307}
308
47ff65c4
DH		 309/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
310static void iwl_set_beacon_tim(struct iwl_priv *priv,
311 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
312 u8 *beacon, u32 frame_size)
313{
314 u16 tim_idx;
315 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
316
317 /*
318 * The index is relative to frame start but we start looking at the
319 * variable-length part of the beacon.
320 */
321 tim_idx = mgmt->u.beacon.variable - beacon;
322
323 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
324 while ((tim_idx < (frame_size - 2)) &&
325 (beacon[tim_idx] != WLAN_EID_TIM))
326 tim_idx += beacon[tim_idx+1] + 2;
327
328 /* If TIM field was found, set variables */
329 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
330 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
331 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
332 } else
333 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
334}
335
5b9f8cd3 336static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 337 struct iwl_frame *frame)
4bf64efd
TW		 338{
339 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 340 u32 frame_size;
341 u32 rate_flags;
342 u32 rate;
343 /*
344 * We have to set up the TX command, the TX Beacon command, and the
345 * beacon contents.
346 */
4bf64efd 347
47ff65c4 348 /* Initialize memory */
4bf64efd
TW		 349 tx_beacon_cmd = &frame->u.beacon;
350 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
351
47ff65c4 352 /* Set up TX beacon contents */
4bf64efd 353 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 354 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 355 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
356 return 0;
4bf64efd 357
47ff65c4 358 /* Set up TX command fields */
4bf64efd 359 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH		 360 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
361 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
362 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
363 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 364
47ff65c4
DH		 365 /* Set up TX beacon command fields */
366 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
367 frame_size);
4bf64efd 368
47ff65c4
DH		 369 /* Set up packet rate and flags */
370 rate = iwl_rate_get_lowest_plcp(priv);
0e1654fa
JB		 371 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
372 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 373 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
374 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
375 rate_flags |= RATE_MCS_CCK_MSK;
376 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
377 rate_flags);
4bf64efd
TW		 378
379 return sizeof(*tx_beacon_cmd) + frame_size;
380}
5b9f8cd3 381static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 382{
fcab423d 383 struct iwl_frame *frame;
b481de9c
ZY		 384 unsigned int frame_size;
385 int rc;
b481de9c 386
fcab423d 387 frame = iwl_get_free_frame(priv);
b481de9c 388 if (!frame) {
15b1687c 389 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 390 "command.\n");
391 return -ENOMEM;
392 }
393
47ff65c4
DH		 394 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
395 if (!frame_size) {
396 IWL_ERR(priv, "Error configuring the beacon command\n");
397 iwl_free_frame(priv, frame);
398 return -EINVAL;
399 }
b481de9c 400
857485c0 401 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 402 &frame->u.cmd[0]);
403
fcab423d 404 iwl_free_frame(priv, frame);
b481de9c
ZY		 405
406 return rc;
407}
408
7aaa1d79
SO		 409static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
410{
411 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
412
413 dma_addr_t addr = get_unaligned_le32(&tb->lo);
414 if (sizeof(dma_addr_t) > sizeof(u32))
415 addr |=
416 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
417
418 return addr;
419}
420
421static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
422{
423 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
424
425 return le16_to_cpu(tb->hi_n_len) >> 4;
426}
427
428static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
429 dma_addr_t addr, u16 len)
430{
431 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
432 u16 hi_n_len = len << 4;
433
434 put_unaligned_le32(addr, &tb->lo);
435 if (sizeof(dma_addr_t) > sizeof(u32))
436 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
437
438 tb->hi_n_len = cpu_to_le16(hi_n_len);
439
440 tfd->num_tbs = idx + 1;
441}
442
443static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
444{
445 return tfd->num_tbs & 0x1f;
446}
447
448/**
449 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
450 * @priv - driver private data
451 * @txq - tx queue
452 *
453 * Does NOT advance any TFD circular buffer read/write indexes
454 * Does NOT free the TFD itself (which is within circular buffer)
455 */
456void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
457{
59606ffa 458 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 459 struct iwl_tfd *tfd;
460 struct pci_dev *dev = priv->pci_dev;
461 int index = txq->q.read_ptr;
462 int i;
463 int num_tbs;
464
465 tfd = &tfd_tmp[index];
466
467 /* Sanity check on number of chunks */
468 num_tbs = iwl_tfd_get_num_tbs(tfd);
469
470 if (num_tbs >= IWL_NUM_OF_TBS) {
471 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
472 /* @todo issue fatal error, it is quite serious situation */
473 return;
474 }
475
476 /* Unmap tx_cmd */
477 if (num_tbs)
478 pci_unmap_single(dev,
2e724443
FT		 479 dma_unmap_addr(&txq->meta[index], mapping),
480 dma_unmap_len(&txq->meta[index], len),
96891cee 481 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 482
483 /* Unmap chunks, if any. */
ff0d91c3 484 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 485 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
486 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
487
ff0d91c3
JB		 488 /* free SKB */
489 if (txq->txb) {
490 struct sk_buff *skb;
6f80240e 491
ff0d91c3 492 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 493
ff0d91c3
JB		 494 /* can be called from irqs-disabled context */
495 if (skb) {
496 dev_kfree_skb_any(skb);
497 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 498 }
499 }
500}
501
502int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
503 struct iwl_tx_queue *txq,
504 dma_addr_t addr, u16 len,
505 u8 reset, u8 pad)
506{
507 struct iwl_queue *q;
59606ffa 508 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 509 u32 num_tbs;
510
511 q = &txq->q;
59606ffa
SO		 512 tfd_tmp = (struct iwl_tfd *)txq->tfds;
513 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 514
515 if (reset)
516 memset(tfd, 0, sizeof(*tfd));
517
518 num_tbs = iwl_tfd_get_num_tbs(tfd);
519
520 /* Each TFD can point to a maximum 20 Tx buffers */
521 if (num_tbs >= IWL_NUM_OF_TBS) {
522 IWL_ERR(priv, "Error can not send more than %d chunks\n",
523 IWL_NUM_OF_TBS);
524 return -EINVAL;
525 }
526
527 BUG_ON(addr & ~DMA_BIT_MASK(36));
528 if (unlikely(addr & ~IWL_TX_DMA_MASK))
529 IWL_ERR(priv, "Unaligned address = %llx\n",
530 (unsigned long long)addr);
531
532 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
533
534 return 0;
535}
536
a8e74e27
SO		 537/*
538 * Tell nic where to find circular buffer of Tx Frame Descriptors for
539 * given Tx queue, and enable the DMA channel used for that queue.
540 *
541 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
542 * channels supported in hardware.
543 */
544int iwl_hw_tx_queue_init(struct iwl_priv *priv,
545 struct iwl_tx_queue *txq)
546{
a8e74e27
SO		 547 int txq_id = txq->q.id;
548
a8e74e27
SO		 549 /* Circular buffer (TFD queue in DRAM) physical base address */
550 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
551 txq->q.dma_addr >> 8);
552
a8e74e27
SO		 553 return 0;
554}
555
b481de9c
ZY		 556/******************************************************************************
557 *
558 * Generic RX handler implementations
559 *
560 ******************************************************************************/
885ba202
TW		 561static void iwl_rx_reply_alive(struct iwl_priv *priv,
562 struct iwl_rx_mem_buffer *rxb)
b481de9c 563{
2f301227 564 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 565 struct iwl_alive_resp *palive;
b481de9c
ZY		 566 struct delayed_work *pwork;
567
568 palive = &pkt->u.alive_frame;
569
e1623446 570 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 571 "0x%01X 0x%01X\n",
572 palive->is_valid, palive->ver_type,
573 palive->ver_subtype);
574
575 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 576 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 577 memcpy(&priv->card_alive_init,
578 &pkt->u.alive_frame,
885ba202 579 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 580 pwork = &priv->init_alive_start;
581 } else {
e1623446 582 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 583 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 584 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 585 pwork = &priv->alive_start;
586 }
587
588 /* We delay the ALIVE response by 5ms to
589 * give the HW RF Kill time to activate... */
590 if (palive->is_valid == UCODE_VALID_OK)
591 queue_delayed_work(priv->workqueue, pwork,
592 msecs_to_jiffies(5));
593 else
39aadf8c 594 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 595}
596
5b9f8cd3 597static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 598{
c79dd5b5
TW		 599 struct iwl_priv *priv =
600 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 601 struct sk_buff *beacon;
602
603 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 604 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 605
606 if (!beacon) {
15b1687c 607 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY		 608 return;
609 }
610
611 mutex_lock(&priv->mutex);
612 /* new beacon skb is allocated every time; dispose previous.*/
613 if (priv->ibss_beacon)
614 dev_kfree_skb(priv->ibss_beacon);
615
616 priv->ibss_beacon = beacon;
617 mutex_unlock(&priv->mutex);
618
5b9f8cd3 619 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 620}
621
4e39317d 622/**
5b9f8cd3 623 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 624 *
625 * This callback is provided in order to send a statistics request.
626 *
627 * This timer function is continually reset to execute within
628 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
629 * was received. We need to ensure we receive the statistics in order
630 * to update the temperature used for calibrating the TXPOWER.
631 */
5b9f8cd3 632static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 633{
634 struct iwl_priv *priv = (struct iwl_priv *)data;
635
636 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
637 return;
638
61780ee3
MA		 639 /* dont send host command if rf-kill is on */
640 if (!iwl_is_ready_rf(priv))
641 return;
642
ef8d5529 643 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 644}
645
a9e1cb6a
WYG		 646
647static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
648 u32 start_idx, u32 num_events,
649 u32 mode)
650{
651 u32 i;
652 u32 ptr; /* SRAM byte address of log data */
653 u32 ev, time, data; /* event log data */
654 unsigned long reg_flags;
655
656 if (mode == 0)
657 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
658 else
659 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
660
661 /* Make sure device is powered up for SRAM reads */
662 spin_lock_irqsave(&priv->reg_lock, reg_flags);
663 if (iwl_grab_nic_access(priv)) {
664 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
665 return;
666 }
667
668 /* Set starting address; reads will auto-increment */
669 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
670 rmb();
671
672 /*
673 * "time" is actually "data" for mode 0 (no timestamp).
674 * place event id # at far right for easier visual parsing.
675 */
676 for (i = 0; i < num_events; i++) {
677 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
678 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
679 if (mode == 0) {
680 trace_iwlwifi_dev_ucode_cont_event(priv,
681 0, time, ev);
682 } else {
683 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
684 trace_iwlwifi_dev_ucode_cont_event(priv,
685 time, data, ev);
686 }
687 }
688 /* Allow device to power down */
689 iwl_release_nic_access(priv);
690 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
691}
692
875295f1 693static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 694{
695 u32 capacity; /* event log capacity in # entries */
696 u32 base; /* SRAM byte address of event log header */
697 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
698 u32 num_wraps; /* # times uCode wrapped to top of log */
699 u32 next_entry; /* index of next entry to be written by uCode */
700
701 if (priv->ucode_type == UCODE_INIT)
702 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
703 else
704 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
705 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
706 capacity = iwl_read_targ_mem(priv, base);
707 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
708 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
709 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
710 } else
711 return;
712
713 if (num_wraps == priv->event_log.num_wraps) {
714 iwl_print_cont_event_trace(priv,
715 base, priv->event_log.next_entry,
716 next_entry - priv->event_log.next_entry,
717 mode);
718 priv->event_log.non_wraps_count++;
719 } else {
720 if ((num_wraps - priv->event_log.num_wraps) > 1)
721 priv->event_log.wraps_more_count++;
722 else
723 priv->event_log.wraps_once_count++;
724 trace_iwlwifi_dev_ucode_wrap_event(priv,
725 num_wraps - priv->event_log.num_wraps,
726 next_entry, priv->event_log.next_entry);
727 if (next_entry < priv->event_log.next_entry) {
728 iwl_print_cont_event_trace(priv, base,
729 priv->event_log.next_entry,
730 capacity - priv->event_log.next_entry,
731 mode);
732
733 iwl_print_cont_event_trace(priv, base, 0,
734 next_entry, mode);
735 } else {
736 iwl_print_cont_event_trace(priv, base,
737 next_entry, capacity - next_entry,
738 mode);
739
740 iwl_print_cont_event_trace(priv, base, 0,
741 next_entry, mode);
742 }
743 }
744 priv->event_log.num_wraps = num_wraps;
745 priv->event_log.next_entry = next_entry;
746}
747
748/**
749 * iwl_bg_ucode_trace - Timer callback to log ucode event
750 *
751 * The timer is continually set to execute every
752 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
753 * this function is to perform continuous uCode event logging operation
754 * if enabled
755 */
756static void iwl_bg_ucode_trace(unsigned long data)
757{
758 struct iwl_priv *priv = (struct iwl_priv *)data;
759
760 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
761 return;
762
763 if (priv->event_log.ucode_trace) {
764 iwl_continuous_event_trace(priv);
765 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
766 mod_timer(&priv->ucode_trace,
767 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
768 }
769}
770
5b9f8cd3 771static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 772 struct iwl_rx_mem_buffer *rxb)
b481de9c 773{
0a6857e7 774#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 775 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 776 struct iwl4965_beacon_notif *beacon =
777 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 778 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 779
e1623446 780 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 781 "tsf %d %d rate %d\n",
25a6572c 782 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 783 beacon->beacon_notify_hdr.failure_frame,
784 le32_to_cpu(beacon->ibss_mgr_status),
785 le32_to_cpu(beacon->high_tsf),
786 le32_to_cpu(beacon->low_tsf), rate);
787#endif
788
05c914fe 789 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 790 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
791 queue_work(priv->workqueue, &priv->beacon_update);
792}
793
b481de9c
ZY		 794/* Handle notification from uCode that card's power state is changing
795 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 796static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 797 struct iwl_rx_mem_buffer *rxb)
b481de9c 798{
2f301227 799 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 800 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
801 unsigned long status = priv->status;
802
3a41bbd5 803 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 804 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 805 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
806 (flags & CT_CARD_DISABLED) ?
807 "Reached" : "Not reached");
b481de9c
ZY		 808
809 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 810 CT_CARD_DISABLED)) {
b481de9c 811
3395f6e9 812 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 813 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
814
a8b50a0a
MA		 815 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
816 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 817
818 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 819 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 820 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 821 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 822 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 823 }
3a41bbd5 824 if (flags & CT_CARD_DISABLED)
39b73fb1 825 iwl_tt_enter_ct_kill(priv);
b481de9c 826 }
3a41bbd5 827 if (!(flags & CT_CARD_DISABLED))
39b73fb1 828 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 829
830 if (flags & HW_CARD_DISABLED)
831 set_bit(STATUS_RF_KILL_HW, &priv->status);
832 else
833 clear_bit(STATUS_RF_KILL_HW, &priv->status);
834
835
b481de9c 836 if (!(flags & RXON_CARD_DISABLED))
2a421b91 837 iwl_scan_cancel(priv);
b481de9c
ZY		 838
839 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 840 test_bit(STATUS_RF_KILL_HW, &priv->status)))
841 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
842 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 843 else
844 wake_up_interruptible(&priv->wait_command_queue);
845}
846
5b9f8cd3 847int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 848{
e2e3c57b 849 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 850 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW		 851 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
852 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
853 ~APMG_PS_CTRL_MSK_PWR_SRC);
854 } else {
855 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
856 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
857 ~APMG_PS_CTRL_MSK_PWR_SRC);
858 }
859
a8b50a0a 860 return 0;
e2e3c57b
TW		 861}
862
65550636
WYG		 863static void iwl_bg_tx_flush(struct work_struct *work)
864{
865 struct iwl_priv *priv =
866 container_of(work, struct iwl_priv, tx_flush);
867
868 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
869 return;
870
871 /* do nothing if rf-kill is on */
872 if (!iwl_is_ready_rf(priv))
873 return;
874
875 if (priv->cfg->ops->lib->txfifo_flush) {
876 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
877 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
878 }
879}
880
b481de9c 881/**
5b9f8cd3 882 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 883 *
884 * Setup the RX handlers for each of the reply types sent from the uCode
885 * to the host.
886 *
887 * This function chains into the hardware specific files for them to setup
888 * any hardware specific handlers as well.
889 */
653fa4a0 890static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 891{
885ba202 892 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 893 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
894 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 895 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
896 iwl_rx_spectrum_measure_notif;
5b9f8cd3 897 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 898 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 899 iwl_rx_pm_debug_statistics_notif;
900 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 901
9fbab516
BC		 902 /*
903 * The same handler is used for both the REPLY to a discrete
904 * statistics request from the host as well as for the periodic
905 * statistics notifications (after received beacons) from the uCode.
b481de9c 906 */
ef8d5529 907 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 908 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 909
910 iwl_setup_rx_scan_handlers(priv);
911
37a44211 912 /* status change handler */
5b9f8cd3 913 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 914
c1354754
TW		 915 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
916 iwl_rx_missed_beacon_notif;
37a44211 917 /* Rx handlers */
8d801080
WYG		 918 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
919 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 920 /* block ack */
74bcdb33 921 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 922 /* Set up hardware specific Rx handlers */
d4789efe 923 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 924}
925
b481de9c 926/**
a55360e4 927 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 928 *
929 * Uses the priv->rx_handlers callback function array to invoke
930 * the appropriate handlers, including command responses,
931 * frame-received notifications, and other notifications.
932 */
a55360e4 933void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 934{
a55360e4 935 struct iwl_rx_mem_buffer *rxb;
db11d634 936 struct iwl_rx_packet *pkt;
a55360e4 937 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 938 u32 r, i;
939 int reclaim;
940 unsigned long flags;
5c0eef96 941 u8 fill_rx = 0;
d68ab680 942 u32 count = 8;
4752c93c 943 int total_empty;
b481de9c 944
6440adb5
CB		 945 /* uCode's read index (stored in shared DRAM) indicates the last Rx
946 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 947 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 948 i = rxq->read;
949
950 /* Rx interrupt, but nothing sent from uCode */
951 if (i == r)
e1623446 952 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 953
4752c93c 954 /* calculate total frames need to be restock after handling RX */
7300515d 955 total_empty = r - rxq->write_actual;
4752c93c
MA		 956 if (total_empty < 0)
957 total_empty += RX_QUEUE_SIZE;
958
959 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 960 fill_rx = 1;
961
b481de9c 962 while (i != r) {
f4989d9b
JB		 963 int len;
964
b481de9c
ZY		 965 rxb = rxq->queue[i];
966
9fbab516 967 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 968 * then a bug has been introduced in the queue refilling
969 * routines -- catch it here */
970 BUG_ON(rxb == NULL);
971
972 rxq->queue[i] = NULL;
973
2f301227
ZY		 974 pci_unmap_page(priv->pci_dev, rxb->page_dma,
975 PAGE_SIZE << priv->hw_params.rx_page_order,
976 PCI_DMA_FROMDEVICE);
977 pkt = rxb_addr(rxb);
b481de9c 978
f4989d9b
JB		 979 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
980 len += sizeof(u32); /* account for status word */
981 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 982
b481de9c
ZY		 983 /* Reclaim a command buffer only if this packet is a response
984 * to a (driver-originated) command.
985 * If the packet (e.g. Rx frame) originated from uCode,
986 * there is no command buffer to reclaim.
987 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
988 * but apparently a few don't get set; catch them here. */
989 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
990 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 991 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 992 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 993 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 994 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
995 (pkt->hdr.cmd != REPLY_TX);
996
997 /* Based on type of command response or notification,
998 * handle those that need handling via function in
5b9f8cd3 999 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 1000 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1001 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 1002 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 1003 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1004 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 1005 } else {
1006 /* No handling needed */
e1623446 1007 IWL_DEBUG_RX(priv,
b481de9c
ZY		 1008 "r %d i %d No handler needed for %s, 0x%02x\n",
1009 r, i, get_cmd_string(pkt->hdr.cmd),
1010 pkt->hdr.cmd);
1011 }
1012
29b1b268
ZY		 1013 /*
1014 * XXX: After here, we should always check rxb->page
1015 * against NULL before touching it or its virtual
1016 * memory (pkt). Because some rx_handler might have
1017 * already taken or freed the pages.
1018 */
1019
b481de9c 1020 if (reclaim) {
2f301227
ZY		 1021 /* Invoke any callbacks, transfer the buffer to caller,
1022 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1023 * as we reclaim the driver command queue */
29b1b268 1024 if (rxb->page)
17b88929 1025 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1026 else
39aadf8c 1027 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1028 }
1029
7300515d
ZY		 1030 /* Reuse the page if possible. For notification packets and
1031 * SKBs that fail to Rx correctly, add them back into the
1032 * rx_free list for reuse later. */
1033 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1034 if (rxb->page != NULL) {
7300515d
ZY		 1035 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1036 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1037 PCI_DMA_FROMDEVICE);
1038 list_add_tail(&rxb->list, &rxq->rx_free);
1039 rxq->free_count++;
1040 } else
1041 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1042
b481de9c 1043 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1044
b481de9c 1045 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1046 /* If there are a lot of unused frames,
1047 * restock the Rx queue so ucode wont assert. */
1048 if (fill_rx) {
1049 count++;
1050 if (count >= 8) {
7300515d 1051 rxq->read = i;
54b81550 1052 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1053 count = 0;
1054 }
1055 }
b481de9c
ZY		 1056 }
1057
1058 /* Backtrack one entry */
7300515d 1059 rxq->read = i;
4752c93c 1060 if (fill_rx)
54b81550 1061 iwlagn_rx_replenish_now(priv);
4752c93c 1062 else
54b81550 1063 iwlagn_rx_queue_restock(priv);
a55360e4 1064}
a55360e4 1065
0359facc
MA		 1066/* call this function to flush any scheduled tasklet */
1067static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1068{
a96a27f9 1069 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1070 synchronize_irq(priv->pci_dev->irq);
1071 tasklet_kill(&priv->irq_tasklet);
1072}
1073
ef850d7c 1074static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1075{
1076 u32 inta, handled = 0;
1077 u32 inta_fh;
1078 unsigned long flags;
c2e61da2 1079 u32 i;
0a6857e7 1080#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1081 u32 inta_mask;
1082#endif
1083
1084 spin_lock_irqsave(&priv->lock, flags);
1085
1086 /* Ack/clear/reset pending uCode interrupts.
1087 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1088 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1089 inta = iwl_read32(priv, CSR_INT);
1090 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1091
1092 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1093 * Any new interrupts that happen after this, either while we're
1094 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1095 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1096 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1097
0a6857e7 1098#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1099 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1100 /* just for debug */
3395f6e9 1101 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1102 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1103 inta, inta_mask, inta_fh);
1104 }
1105#endif
1106
2f301227
ZY		 1107 spin_unlock_irqrestore(&priv->lock, flags);
1108
b481de9c
ZY		 1109 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1110 * atomic, make sure that inta covers all the interrupts that
1111 * we've discovered, even if FH interrupt came in just after
1112 * reading CSR_INT. */
6f83eaa1 1113 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1114 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1115 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1116 inta |= CSR_INT_BIT_FH_TX;
1117
1118 /* Now service all interrupt bits discovered above. */
1119 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1120 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1121
1122 /* Tell the device to stop sending interrupts */
5b9f8cd3 1123 iwl_disable_interrupts(priv);
b481de9c 1124
a83b9141 1125 priv->isr_stats.hw++;
5b9f8cd3 1126 iwl_irq_handle_error(priv);
b481de9c
ZY		 1127
1128 handled |= CSR_INT_BIT_HW_ERR;
1129
b481de9c
ZY		 1130 return;
1131 }
1132
0a6857e7 1133#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1134 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1135 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1136 if (inta & CSR_INT_BIT_SCD) {
e1623446 1137 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1138 "the frame/frames.\n");
a83b9141
WYG		 1139 priv->isr_stats.sch++;
1140 }
b481de9c
ZY		 1141
1142 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1143 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1144 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1145 priv->isr_stats.alive++;
1146 }
b481de9c
ZY		 1147 }
1148#endif
1149 /* Safely ignore these bits for debug checks below */
25c03d8e 1150 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1151
9fbab516 1152 /* HW RF KILL switch toggled */
b481de9c
ZY		 1153 if (inta & CSR_INT_BIT_RF_KILL) {
1154 int hw_rf_kill = 0;
3395f6e9 1155 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1156 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1157 hw_rf_kill = 1;
1158
4c423a2b 1159 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1160 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1161
a83b9141
WYG		 1162 priv->isr_stats.rfkill++;
1163
a9efa652 1164 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1165 * the driver allows loading the ucode even if the radio
1166 * is killed. Hence update the killswitch state here. The
1167 * rfkill handler will care about restarting if needed.
a9efa652 1168 */
6cd0b1cb
HS		 1169 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1170 if (hw_rf_kill)
1171 set_bit(STATUS_RF_KILL_HW, &priv->status);
1172 else
1173 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1174 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1175 }
b481de9c
ZY		 1176
1177 handled |= CSR_INT_BIT_RF_KILL;
1178 }
1179
9fbab516 1180 /* Chip got too hot and stopped itself */
b481de9c 1181 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1182 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1183 priv->isr_stats.ctkill++;
b481de9c
ZY		 1184 handled |= CSR_INT_BIT_CT_KILL;
1185 }
1186
1187 /* Error detected by uCode */
1188 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1189 IWL_ERR(priv, "Microcode SW error detected. "
1190 " Restarting 0x%X.\n", inta);
a83b9141
WYG		 1191 priv->isr_stats.sw++;
1192 priv->isr_stats.sw_err = inta;
5b9f8cd3 1193 iwl_irq_handle_error(priv);
b481de9c
ZY		 1194 handled |= CSR_INT_BIT_SW_ERR;
1195 }
1196
c2e61da2
BC		 1197 /*
1198 * uCode wakes up after power-down sleep.
1199 * Tell device about any new tx or host commands enqueued,
1200 * and about any Rx buffers made available while asleep.
1201 */
b481de9c 1202 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1203 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1204 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1205 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1206 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1207 priv->isr_stats.wakeup++;
b481de9c
ZY		 1208 handled |= CSR_INT_BIT_WAKEUP;
1209 }
1210
1211 /* All uCode command responses, including Tx command responses,
1212 * Rx "responses" (frame-received notification), and other
1213 * notifications from uCode come through here*/
1214 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1215 iwl_rx_handle(priv);
a83b9141 1216 priv->isr_stats.rx++;
b481de9c
ZY		 1217 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1218 }
1219
c72cd19f 1220 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1221 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1222 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1223 priv->isr_stats.tx++;
b481de9c 1224 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1225 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1226 priv->ucode_write_complete = 1;
1227 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1228 }
1229
a83b9141 1230 if (inta & ~handled) {
15b1687c 1231 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1232 priv->isr_stats.unhandled++;
1233 }
b481de9c 1234
40cefda9 1235 if (inta & ~(priv->inta_mask)) {
39aadf8c 1236 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1237 inta & ~priv->inta_mask);
39aadf8c 1238 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1239 }
1240
1241 /* Re-enable all interrupts */
0359facc
MA		 1242 /* only Re-enable if diabled by irq */
1243 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1244 iwl_enable_interrupts(priv);
b481de9c 1245
0a6857e7 1246#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1247 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1248 inta = iwl_read32(priv, CSR_INT);
1249 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1250 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1251 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1252 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1253 }
1254#endif
b481de9c
ZY		 1255}
1256
ef850d7c
MA		 1257/* tasklet for iwlagn interrupt */
1258static void iwl_irq_tasklet(struct iwl_priv *priv)
1259{
1260 u32 inta = 0;
1261 u32 handled = 0;
1262 unsigned long flags;
8756990f 1263 u32 i;
ef850d7c
MA		 1264#ifdef CONFIG_IWLWIFI_DEBUG
1265 u32 inta_mask;
1266#endif
1267
1268 spin_lock_irqsave(&priv->lock, flags);
1269
1270 /* Ack/clear/reset pending uCode interrupts.
1271 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1272 */
48a6be6a
SZ		 1273 /* There is a hardware bug in the interrupt mask function that some
1274 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1275 * they are disabled in the CSR_INT_MASK register. Furthermore the
1276 * ICT interrupt handling mechanism has another bug that might cause
1277 * these unmasked interrupts fail to be detected. We workaround the
1278 * hardware bugs here by ACKing all the possible interrupts so that
1279 * interrupt coalescing can still be achieved.
1280 */
4a35ecf8 1281 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1282
a4c8b2a6 1283 inta = priv->_agn.inta;
ef850d7c
MA		 1284
1285#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1286 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1287 /* just for debug */
1288 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1289 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1290 inta, inta_mask);
1291 }
1292#endif
2f301227
ZY		 1293
1294 spin_unlock_irqrestore(&priv->lock, flags);
1295
a4c8b2a6
JB		 1296 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1297 priv->_agn.inta = 0;
ef850d7c
MA		 1298
1299 /* Now service all interrupt bits discovered above. */
1300 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1301 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1302
1303 /* Tell the device to stop sending interrupts */
1304 iwl_disable_interrupts(priv);
1305
1306 priv->isr_stats.hw++;
1307 iwl_irq_handle_error(priv);
1308
1309 handled |= CSR_INT_BIT_HW_ERR;
1310
ef850d7c
MA		 1311 return;
1312 }
1313
1314#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1315 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1316 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1317 if (inta & CSR_INT_BIT_SCD) {
1318 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1319 "the frame/frames.\n");
1320 priv->isr_stats.sch++;
1321 }
1322
1323 /* Alive notification via Rx interrupt will do the real work */
1324 if (inta & CSR_INT_BIT_ALIVE) {
1325 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1326 priv->isr_stats.alive++;
1327 }
1328 }
1329#endif
1330 /* Safely ignore these bits for debug checks below */
1331 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1332
1333 /* HW RF KILL switch toggled */
1334 if (inta & CSR_INT_BIT_RF_KILL) {
1335 int hw_rf_kill = 0;
1336 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1337 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1338 hw_rf_kill = 1;
1339
4c423a2b 1340 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1341 hw_rf_kill ? "disable radio" : "enable radio");
1342
1343 priv->isr_stats.rfkill++;
1344
1345 /* driver only loads ucode once setting the interface up.
1346 * the driver allows loading the ucode even if the radio
1347 * is killed. Hence update the killswitch state here. The
1348 * rfkill handler will care about restarting if needed.
1349 */
1350 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1351 if (hw_rf_kill)
1352 set_bit(STATUS_RF_KILL_HW, &priv->status);
1353 else
1354 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1355 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1356 }
1357
1358 handled |= CSR_INT_BIT_RF_KILL;
1359 }
1360
1361 /* Chip got too hot and stopped itself */
1362 if (inta & CSR_INT_BIT_CT_KILL) {
1363 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1364 priv->isr_stats.ctkill++;
1365 handled |= CSR_INT_BIT_CT_KILL;
1366 }
1367
1368 /* Error detected by uCode */
1369 if (inta & CSR_INT_BIT_SW_ERR) {
1370 IWL_ERR(priv, "Microcode SW error detected. "
1371 " Restarting 0x%X.\n", inta);
1372 priv->isr_stats.sw++;
1373 priv->isr_stats.sw_err = inta;
1374 iwl_irq_handle_error(priv);
1375 handled |= CSR_INT_BIT_SW_ERR;
1376 }
1377
1378 /* uCode wakes up after power-down sleep */
1379 if (inta & CSR_INT_BIT_WAKEUP) {
1380 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1381 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1382 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1383 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1384
1385 priv->isr_stats.wakeup++;
1386
1387 handled |= CSR_INT_BIT_WAKEUP;
1388 }
1389
1390 /* All uCode command responses, including Tx command responses,
1391 * Rx "responses" (frame-received notification), and other
1392 * notifications from uCode come through here*/
40cefda9
MA		 1393 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1394 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1395 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1396 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1397 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1398 iwl_write32(priv, CSR_FH_INT_STATUS,
1399 CSR49_FH_INT_RX_MASK);
1400 }
1401 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1402 handled |= CSR_INT_BIT_RX_PERIODIC;
1403 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1404 }
1405 /* Sending RX interrupt require many steps to be done in the
1406 * the device:
1407 * 1- write interrupt to current index in ICT table.
1408 * 2- dma RX frame.
1409 * 3- update RX shared data to indicate last write index.
1410 * 4- send interrupt.
1411 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1412 * but the shared data changes does not reflect this;
1413 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1414 */
74ba67ed
BC		 1415
1416 /* Disable periodic interrupt; we use it as just a one-shot. */
1417 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1418 CSR_INT_PERIODIC_DIS);
ef850d7c 1419 iwl_rx_handle(priv);
74ba67ed
BC		 1420
1421 /*
1422 * Enable periodic interrupt in 8 msec only if we received
1423 * real RX interrupt (instead of just periodic int), to catch
1424 * any dangling Rx interrupt. If it was just the periodic
1425 * interrupt, there was no dangling Rx activity, and no need
1426 * to extend the periodic interrupt; one-shot is enough.
1427 */
40cefda9 1428 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1429 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1430 CSR_INT_PERIODIC_ENA);
1431
ef850d7c 1432 priv->isr_stats.rx++;
ef850d7c
MA		 1433 }
1434
c72cd19f 1435 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1436 if (inta & CSR_INT_BIT_FH_TX) {
1437 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1438 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1439 priv->isr_stats.tx++;
1440 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1441 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1442 priv->ucode_write_complete = 1;
1443 wake_up_interruptible(&priv->wait_command_queue);
1444 }
1445
1446 if (inta & ~handled) {
1447 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1448 priv->isr_stats.unhandled++;
1449 }
1450
40cefda9 1451 if (inta & ~(priv->inta_mask)) {
ef850d7c 1452 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1453 inta & ~priv->inta_mask);
ef850d7c
MA		 1454 }
1455
ef850d7c
MA		 1456 /* Re-enable all interrupts */
1457 /* only Re-enable if diabled by irq */
1458 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1459 iwl_enable_interrupts(priv);
ef850d7c
MA		 1460}
1461
872c8ddc
WYG		 1462/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1463#define ACK_CNT_RATIO (50)
1464#define BA_TIMEOUT_CNT (5)
1465#define BA_TIMEOUT_MAX (16)
1466
1467/**
1468 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1469 *
1470 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1471 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1472 * operation state.
1473 */
1474bool iwl_good_ack_health(struct iwl_priv *priv,
1475 struct iwl_rx_packet *pkt)
1476{
1477 bool rc = true;
1478 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1479 int ba_timeout_delta;
1480
1481 actual_ack_cnt_delta =
1482 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
f3aebeee 1483 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1484 expected_ack_cnt_delta =
1485 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
f3aebeee 1486 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1487 ba_timeout_delta =
1488 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
f3aebeee 1489 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1490 if ((priv->_agn.agg_tids_count > 0) &&
1491 (expected_ack_cnt_delta > 0) &&
1492 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1493 < ACK_CNT_RATIO) &&
1494 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1495 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1496 " expected_ack_cnt = %d\n",
1497 actual_ack_cnt_delta, expected_ack_cnt_delta);
1498
d73e4923
JB		 1499#ifdef CONFIG_IWLWIFI_DEBUGFS
1500 /*
1501 * This is ifdef'ed on DEBUGFS because otherwise the
1502 * statistics aren't available. If DEBUGFS is set but
1503 * DEBUG is not, these will just compile out.
1504 */
872c8ddc 1505 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
f3aebeee 1506 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1507 IWL_DEBUG_RADIO(priv,
1508 "ack_or_ba_timeout_collision delta = %d\n",
f3aebeee 1509 priv->_agn.delta_statistics.tx.
872c8ddc
WYG		 1510 ack_or_ba_timeout_collision);
1511#endif
1512 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1513 ba_timeout_delta);
1514 if (!actual_ack_cnt_delta &&
1515 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1516 rc = false;
1517 }
1518 return rc;
1519}
1520
a83b9141 1521
7d47618a
EG		 1522/*****************************************************************************
1523 *
1524 * sysfs attributes
1525 *
1526 *****************************************************************************/
1527
1528#ifdef CONFIG_IWLWIFI_DEBUG
1529
1530/*
1531 * The following adds a new attribute to the sysfs representation
1532 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1533 * used for controlling the debug level.
1534 *
1535 * See the level definitions in iwl for details.
1536 *
1537 * The debug_level being managed using sysfs below is a per device debug
1538 * level that is used instead of the global debug level if it (the per
1539 * device debug level) is set.
1540 */
1541static ssize_t show_debug_level(struct device *d,
1542 struct device_attribute *attr, char *buf)
1543{
1544 struct iwl_priv *priv = dev_get_drvdata(d);
1545 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1546}
1547static ssize_t store_debug_level(struct device *d,
1548 struct device_attribute *attr,
1549 const char *buf, size_t count)
1550{
1551 struct iwl_priv *priv = dev_get_drvdata(d);
1552 unsigned long val;
1553 int ret;
1554
1555 ret = strict_strtoul(buf, 0, &val);
1556 if (ret)
1557 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1558 else {
1559 priv->debug_level = val;
1560 if (iwl_alloc_traffic_mem(priv))
1561 IWL_ERR(priv,
1562 "Not enough memory to generate traffic log\n");
1563 }
1564 return strnlen(buf, count);
1565}
1566
1567static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1568 show_debug_level, store_debug_level);
1569
1570
1571#endif /* CONFIG_IWLWIFI_DEBUG */
1572
1573
1574static ssize_t show_temperature(struct device *d,
1575 struct device_attribute *attr, char *buf)
1576{
1577 struct iwl_priv *priv = dev_get_drvdata(d);
1578
1579 if (!iwl_is_alive(priv))
1580 return -EAGAIN;
1581
1582 return sprintf(buf, "%d\n", priv->temperature);
1583}
1584
1585static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1586
1587static ssize_t show_tx_power(struct device *d,
1588 struct device_attribute *attr, char *buf)
1589{
1590 struct iwl_priv *priv = dev_get_drvdata(d);
1591
1592 if (!iwl_is_ready_rf(priv))
1593 return sprintf(buf, "off\n");
1594 else
1595 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1596}
1597
1598static ssize_t store_tx_power(struct device *d,
1599 struct device_attribute *attr,
1600 const char *buf, size_t count)
1601{
1602 struct iwl_priv *priv = dev_get_drvdata(d);
1603 unsigned long val;
1604 int ret;
1605
1606 ret = strict_strtoul(buf, 10, &val);
1607 if (ret)
1608 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1609 else {
1610 ret = iwl_set_tx_power(priv, val, false);
1611 if (ret)
1612 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1613 ret);
1614 else
1615 ret = count;
1616 }
1617 return ret;
1618}
1619
1620static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1621
1622static ssize_t show_rts_ht_protection(struct device *d,
1623 struct device_attribute *attr, char *buf)
1624{
1625 struct iwl_priv *priv = dev_get_drvdata(d);
1626
1627 return sprintf(buf, "%s\n",
1628 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
1629}
1630
1631static ssize_t store_rts_ht_protection(struct device *d,
1632 struct device_attribute *attr,
1633 const char *buf, size_t count)
1634{
1635 struct iwl_priv *priv = dev_get_drvdata(d);
1636 unsigned long val;
1637 int ret;
1638
1639 ret = strict_strtoul(buf, 10, &val);
1640 if (ret)
1641 IWL_INFO(priv, "Input is not in decimal form.\n");
1642 else {
1643 if (!iwl_is_associated(priv))
1644 priv->cfg->use_rts_for_ht = val ? true : false;
1645 else
1646 IWL_ERR(priv, "Sta associated with AP - "
1647 "Change protection mechanism is not allowed\n");
1648 ret = count;
1649 }
1650 return ret;
1651}
1652
1653static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
1654 show_rts_ht_protection, store_rts_ht_protection);
1655
1656
1657static struct attribute *iwl_sysfs_entries[] = {
1658 &dev_attr_temperature.attr,
1659 &dev_attr_tx_power.attr,
1660 &dev_attr_rts_ht_protection.attr,
1661#ifdef CONFIG_IWLWIFI_DEBUG
1662 &dev_attr_debug_level.attr,
1663#endif
1664 NULL
1665};
1666
1667static struct attribute_group iwl_attribute_group = {
1668 .name = NULL, /* put in device directory */
1669 .attrs = iwl_sysfs_entries,
1670};
1671
b481de9c
ZY		 1672/******************************************************************************
1673 *
1674 * uCode download functions
1675 *
1676 ******************************************************************************/
1677
5b9f8cd3 1678static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1679{
98c92211
TW		 1680 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1681 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1682 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1683 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1684 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1685 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1686}
1687
5b9f8cd3 1688static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1689{
1690 /* Remove all resets to allow NIC to operate */
1691 iwl_write32(priv, CSR_RESET, 0);
1692}
1693
dd7a2509
JB		 1694struct iwlagn_ucode_capabilities {
1695 u32 max_probe_length;
6a822d06 1696 u32 standard_phy_calibration_size;
dd7a2509 1697};
edcdf8b2 1698
b08dfd04 1699static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1700static int iwl_mac_setup_register(struct iwl_priv *priv,
1701 struct iwlagn_ucode_capabilities *capa);
b08dfd04
JB		 1702
1703static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1704{
1705 const char *name_pre = priv->cfg->fw_name_pre;
1706
1707 if (first)
1708 priv->fw_index = priv->cfg->ucode_api_max;
1709 else
1710 priv->fw_index--;
1711
1712 if (priv->fw_index < priv->cfg->ucode_api_min) {
1713 IWL_ERR(priv, "no suitable firmware found!\n");
1714 return -ENOENT;
1715 }
1716
1717 sprintf(priv->firmware_name, "%s%d%s",
1718 name_pre, priv->fw_index, ".ucode");
1719
1720 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1721 priv->firmware_name);
1722
1723 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1724 &priv->pci_dev->dev, GFP_KERNEL, priv,
1725 iwl_ucode_callback);
1726}
1727
0e9a44dc
JB		 1728struct iwlagn_firmware_pieces {
1729 const void *inst, *data, *init, *init_data, *boot;
1730 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1731
1732 u32 build;
b2e640d4
JB		 1733
1734 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1735 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1736};
1737
1738static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1739 const struct firmware *ucode_raw,
1740 struct iwlagn_firmware_pieces *pieces)
1741{
1742 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1743 u32 api_ver, hdr_size;
1744 const u8 *src;
1745
1746 priv->ucode_ver = le32_to_cpu(ucode->ver);
1747 api_ver = IWL_UCODE_API(priv->ucode_ver);
1748
1749 switch (api_ver) {
1750 default:
1751 /*
1752 * 4965 doesn't revision the firmware file format
1753 * along with the API version, it always uses v1
1754 * file format.
1755 */
1756 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1757 CSR_HW_REV_TYPE_4965) {
1758 hdr_size = 28;
1759 if (ucode_raw->size < hdr_size) {
1760 IWL_ERR(priv, "File size too small!\n");
1761 return -EINVAL;
1762 }
1763 pieces->build = le32_to_cpu(ucode->u.v2.build);
1764 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1765 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1766 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1767 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1768 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1769 src = ucode->u.v2.data;
1770 break;
1771 }
1772 /* fall through for 4965 */
1773 case 0:
1774 case 1:
1775 case 2:
1776 hdr_size = 24;
1777 if (ucode_raw->size < hdr_size) {
1778 IWL_ERR(priv, "File size too small!\n");
1779 return -EINVAL;
1780 }
1781 pieces->build = 0;
1782 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1783 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1784 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1785 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1786 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1787 src = ucode->u.v1.data;
1788 break;
1789 }
1790
1791 /* Verify size of file vs. image size info in file's header */
1792 if (ucode_raw->size != hdr_size + pieces->inst_size +
1793 pieces->data_size + pieces->init_size +
1794 pieces->init_data_size + pieces->boot_size) {
1795
1796 IWL_ERR(priv,
1797 "uCode file size %d does not match expected size\n",
1798 (int)ucode_raw->size);
1799 return -EINVAL;
1800 }
1801
1802 pieces->inst = src;
1803 src += pieces->inst_size;
1804 pieces->data = src;
1805 src += pieces->data_size;
1806 pieces->init = src;
1807 src += pieces->init_size;
1808 pieces->init_data = src;
1809 src += pieces->init_data_size;
1810 pieces->boot = src;
1811 src += pieces->boot_size;
1812
1813 return 0;
1814}
1815
dd7a2509
JB		 1816static int iwlagn_wanted_ucode_alternative = 1;
1817
1818static int iwlagn_load_firmware(struct iwl_priv *priv,
1819 const struct firmware *ucode_raw,
1820 struct iwlagn_firmware_pieces *pieces,
1821 struct iwlagn_ucode_capabilities *capa)
1822{
1823 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1824 struct iwl_ucode_tlv *tlv;
1825 size_t len = ucode_raw->size;
1826 const u8 *data;
1827 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1828 u64 alternatives;
ad8d8333
WYG		 1829 u32 tlv_len;
1830 enum iwl_ucode_tlv_type tlv_type;
1831 const u8 *tlv_data;
dd7a2509 1832
ad8d8333
WYG		 1833 if (len < sizeof(*ucode)) {
1834 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1835 return -EINVAL;
ad8d8333 1836 }
dd7a2509 1837
ad8d8333
WYG		 1838 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1839 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1840 le32_to_cpu(ucode->magic));
dd7a2509 1841 return -EINVAL;
ad8d8333 1842 }
dd7a2509
JB		 1843
1844 /*
1845 * Check which alternatives are present, and "downgrade"
1846 * when the chosen alternative is not present, warning
1847 * the user when that happens. Some files may not have
1848 * any alternatives, so don't warn in that case.
1849 */
1850 alternatives = le64_to_cpu(ucode->alternatives);
1851 tmp = wanted_alternative;
1852 if (wanted_alternative > 63)
1853 wanted_alternative = 63;
1854 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1855 wanted_alternative--;
1856 if (wanted_alternative && wanted_alternative != tmp)
1857 IWL_WARN(priv,
1858 "uCode alternative %d not available, choosing %d\n",
1859 tmp, wanted_alternative);
1860
1861 priv->ucode_ver = le32_to_cpu(ucode->ver);
1862 pieces->build = le32_to_cpu(ucode->build);
1863 data = ucode->data;
1864
1865 len -= sizeof(*ucode);
1866
704da534 1867 while (len >= sizeof(*tlv)) {
dd7a2509 1868 u16 tlv_alt;
dd7a2509
JB		 1869
1870 len -= sizeof(*tlv);
1871 tlv = (void *)data;
1872
1873 tlv_len = le32_to_cpu(tlv->length);
1874 tlv_type = le16_to_cpu(tlv->type);
1875 tlv_alt = le16_to_cpu(tlv->alternative);
1876 tlv_data = tlv->data;
1877
ad8d8333
WYG		 1878 if (len < tlv_len) {
1879 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1880 len, tlv_len);
dd7a2509 1881 return -EINVAL;
ad8d8333 1882 }
dd7a2509
JB		 1883 len -= ALIGN(tlv_len, 4);
1884 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1885
1886 /*
1887 * Alternative 0 is always valid.
1888 *
1889 * Skip alternative TLVs that are not selected.
1890 */
1891 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1892 continue;
1893
1894 switch (tlv_type) {
1895 case IWL_UCODE_TLV_INST:
1896 pieces->inst = tlv_data;
1897 pieces->inst_size = tlv_len;
1898 break;
1899 case IWL_UCODE_TLV_DATA:
1900 pieces->data = tlv_data;
1901 pieces->data_size = tlv_len;
1902 break;
1903 case IWL_UCODE_TLV_INIT:
1904 pieces->init = tlv_data;
1905 pieces->init_size = tlv_len;
1906 break;
1907 case IWL_UCODE_TLV_INIT_DATA:
1908 pieces->init_data = tlv_data;
1909 pieces->init_data_size = tlv_len;
1910 break;
1911 case IWL_UCODE_TLV_BOOT:
1912 pieces->boot = tlv_data;
1913 pieces->boot_size = tlv_len;
1914 break;
1915 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1916 if (tlv_len != sizeof(u32))
1917 goto invalid_tlv_len;
1918 capa->max_probe_length =
ad8d8333 1919 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1920 break;
b2e640d4 1921 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1922 if (tlv_len != sizeof(u32))
1923 goto invalid_tlv_len;
1924 pieces->init_evtlog_ptr =
ad8d8333 1925 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1926 break;
1927 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 1928 if (tlv_len != sizeof(u32))
1929 goto invalid_tlv_len;
1930 pieces->init_evtlog_size =
ad8d8333 1931 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1932 break;
1933 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 1934 if (tlv_len != sizeof(u32))
1935 goto invalid_tlv_len;
1936 pieces->init_errlog_ptr =
ad8d8333 1937 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1938 break;
1939 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 1940 if (tlv_len != sizeof(u32))
1941 goto invalid_tlv_len;
1942 pieces->inst_evtlog_ptr =
ad8d8333 1943 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1944 break;
1945 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 1946 if (tlv_len != sizeof(u32))
1947 goto invalid_tlv_len;
1948 pieces->inst_evtlog_size =
ad8d8333 1949 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1950 break;
1951 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 1952 if (tlv_len != sizeof(u32))
1953 goto invalid_tlv_len;
1954 pieces->inst_errlog_ptr =
ad8d8333 1955 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 1956 break;
c8312fac
WYG		 1957 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1958 if (tlv_len)
704da534
JB		 1959 goto invalid_tlv_len;
1960 priv->enhance_sensitivity_table = true;
c8312fac 1961 break;
6a822d06 1962 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 1963 if (tlv_len != sizeof(u32))
1964 goto invalid_tlv_len;
1965 capa->standard_phy_calibration_size =
6a822d06
WYG		 1966 le32_to_cpup((__le32 *)tlv_data);
1967 break;
dd7a2509 1968 default:
ad8d8333 1969 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 1970 break;
1971 }
1972 }
1973
ad8d8333
WYG		 1974 if (len) {
1975 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1976 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 1977 return -EINVAL;
ad8d8333 1978 }
dd7a2509 1979
704da534
JB		 1980 return 0;
1981
1982 invalid_tlv_len:
1983 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1984 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1985
1986 return -EINVAL;
dd7a2509
JB		 1987}
1988
b481de9c 1989/**
b08dfd04 1990 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1991 *
b08dfd04
JB		 1992 * If loaded successfully, copies the firmware into buffers
1993 * for the card to fetch (via DMA).
b481de9c 1994 */
b08dfd04 1995static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1996{
b08dfd04 1997 struct iwl_priv *priv = context;
cc0f555d 1998 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 1999 int err;
2000 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 2001 const unsigned int api_max = priv->cfg->ucode_api_max;
2002 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 2003 u32 api_ver;
3e4de761 2004 char buildstr[25];
0e9a44dc 2005 u32 build;
dd7a2509
JB		 2006 struct iwlagn_ucode_capabilities ucode_capa = {
2007 .max_probe_length = 200,
6a822d06
WYG		 2008 .standard_phy_calibration_size =
2009 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 2010 };
0e9a44dc
JB		 2011
2012 memset(&pieces, 0, sizeof(pieces));
b481de9c 2013
b08dfd04
JB		 2014 if (!ucode_raw) {
2015 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
2016 priv->firmware_name);
2017 goto try_again;
b481de9c
ZY		 2018 }
2019
b08dfd04
JB		 2020 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2021 priv->firmware_name, ucode_raw->size);
b481de9c 2022
22adba2a
JB		 2023 /* Make sure that we got at least the API version number */
2024 if (ucode_raw->size < 4) {
15b1687c 2025 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 2026 goto try_again;
b481de9c
ZY		 2027 }
2028
2029 /* Data from ucode file: header followed by uCode images */
cc0f555d 2030 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2031
0e9a44dc
JB		 2032 if (ucode->ver)
2033 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2034 else
dd7a2509
JB		 2035 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2036 &ucode_capa);
22adba2a 2037
0e9a44dc
JB		 2038 if (err)
2039 goto try_again;
b481de9c 2040
a0987a8d 2041 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 2042 build = pieces.build;
a0987a8d 2043
0e9a44dc
JB		 2044 /*
2045 * api_ver should match the api version forming part of the
2046 * firmware filename ... but we don't check for that and only rely
2047 * on the API version read from firmware header from here on forward
2048 */
a0987a8d 2049 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2050 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 2051 "Driver supports v%u, firmware is v%u.\n",
2052 api_max, api_ver);
b08dfd04 2053 goto try_again;
a0987a8d 2054 }
b08dfd04 2055
a0987a8d 2056 if (api_ver != api_max)
978785a3 2057 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 2058 "got v%u. New firmware can be obtained "
2059 "from http://www.intellinuxwireless.org.\n",
2060 api_max, api_ver);
2061
3e4de761
JB		 2062 if (build)
2063 sprintf(buildstr, " build %u", build);
2064 else
2065 buildstr[0] = '\0';
2066
2067 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2068 IWL_UCODE_MAJOR(priv->ucode_ver),
2069 IWL_UCODE_MINOR(priv->ucode_ver),
2070 IWL_UCODE_API(priv->ucode_ver),
2071 IWL_UCODE_SERIAL(priv->ucode_ver),
2072 buildstr);
a0987a8d 2073
5ebeb5a6
RC		 2074 snprintf(priv->hw->wiphy->fw_version,
2075 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2076 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2077 IWL_UCODE_MAJOR(priv->ucode_ver),
2078 IWL_UCODE_MINOR(priv->ucode_ver),
2079 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2080 IWL_UCODE_SERIAL(priv->ucode_ver),
2081 buildstr);
b481de9c 2082
b08dfd04
JB		 2083 /*
2084 * For any of the failures below (before allocating pci memory)
2085 * we will try to load a version with a smaller API -- maybe the
2086 * user just got a corrupted version of the latest API.
2087 */
2088
0e9a44dc
JB		 2089 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2090 priv->ucode_ver);
2091 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2092 pieces.inst_size);
2093 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2094 pieces.data_size);
2095 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2096 pieces.init_size);
2097 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2098 pieces.init_data_size);
2099 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2100 pieces.boot_size);
b481de9c
ZY		 2101
2102 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2103 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2104 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2105 pieces.inst_size);
b08dfd04 2106 goto try_again;
b481de9c
ZY		 2107 }
2108
0e9a44dc
JB		 2109 if (pieces.data_size > priv->hw_params.max_data_size) {
2110 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2111 pieces.data_size);
b08dfd04 2112 goto try_again;
b481de9c 2113 }
0e9a44dc
JB		 2114
2115 if (pieces.init_size > priv->hw_params.max_inst_size) {
2116 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2117 pieces.init_size);
b08dfd04 2118 goto try_again;
b481de9c 2119 }
0e9a44dc
JB		 2120
2121 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2122 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2123 pieces.init_data_size);
b08dfd04 2124 goto try_again;
b481de9c 2125 }
0e9a44dc
JB		 2126
2127 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2128 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2129 pieces.boot_size);
b08dfd04 2130 goto try_again;
b481de9c
ZY		 2131 }
2132
2133 /* Allocate ucode buffers for card's bus-master loading ... */
2134
2135 /* Runtime instructions and 2 copies of data:
2136 * 1) unmodified from disk
2137 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2138 priv->ucode_code.len = pieces.inst_size;
98c92211 2139 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2140
0e9a44dc 2141 priv->ucode_data.len = pieces.data_size;
98c92211 2142 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2143
0e9a44dc 2144 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2145 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2146
1f304e4e
ZY		 2147 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2148 !priv->ucode_data_backup.v_addr)
2149 goto err_pci_alloc;
2150
b481de9c 2151 /* Initialization instructions and data */
0e9a44dc
JB		 2152 if (pieces.init_size && pieces.init_data_size) {
2153 priv->ucode_init.len = pieces.init_size;
98c92211 2154 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2155
0e9a44dc 2156 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2157 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2158
2159 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2160 goto err_pci_alloc;
2161 }
b481de9c
ZY		 2162
2163 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2164 if (pieces.boot_size) {
2165 priv->ucode_boot.len = pieces.boot_size;
98c92211 2166 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2167
90e759d1
TW		 2168 if (!priv->ucode_boot.v_addr)
2169 goto err_pci_alloc;
2170 }
b481de9c 2171
b2e640d4
JB		 2172 /* Now that we can no longer fail, copy information */
2173
2174 /*
2175 * The (size - 16) / 12 formula is based on the information recorded
2176 * for each event, which is of mode 1 (including timestamp) for all
2177 * new microcodes that include this information.
2178 */
2179 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2180 if (pieces.init_evtlog_size)
2181 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2182 else
2183 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2184 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2185 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2186 if (pieces.inst_evtlog_size)
2187 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2188 else
2189 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2190 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2191
b481de9c
ZY		 2192 /* Copy images into buffers for card's bus-master reads ... */
2193
2194 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2195 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2196 pieces.inst_size);
2197 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2198
e1623446 2199 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2200 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2201
0e9a44dc
JB		 2202 /*
2203 * Runtime data
2204 * NOTE: Copy into backup buffer will be done in iwl_up()
2205 */
2206 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2207 pieces.data_size);
2208 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2209 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2210
2211 /* Initialization instructions */
2212 if (pieces.init_size) {
e1623446 2213 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2214 pieces.init_size);
2215 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2216 }
2217
0e9a44dc
JB		 2218 /* Initialization data */
2219 if (pieces.init_data_size) {
e1623446 2220 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2221 pieces.init_data_size);
2222 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2223 pieces.init_data_size);
b481de9c
ZY		 2224 }
2225
0e9a44dc
JB		 2226 /* Bootstrap instructions */
2227 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2228 pieces.boot_size);
2229 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2230
6a822d06
WYG		 2231 /*
2232 * figure out the offset of chain noise reset and gain commands
2233 * base on the size of standard phy calibration commands table size
2234 */
2235 if (ucode_capa.standard_phy_calibration_size >
2236 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2237 ucode_capa.standard_phy_calibration_size =
2238 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2239
2240 priv->_agn.phy_calib_chain_noise_reset_cmd =
2241 ucode_capa.standard_phy_calibration_size;
2242 priv->_agn.phy_calib_chain_noise_gain_cmd =
2243 ucode_capa.standard_phy_calibration_size + 1;
2244
b08dfd04
JB		 2245 /**************************************************
2246 * This is still part of probe() in a sense...
2247 *
2248 * 9. Setup and register with mac80211 and debugfs
2249 **************************************************/
dd7a2509 2250 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2251 if (err)
2252 goto out_unbind;
2253
2254 err = iwl_dbgfs_register(priv, DRV_NAME);
2255 if (err)
2256 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2257
7d47618a
EG		 2258 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2259 &iwl_attribute_group);
2260 if (err) {
2261 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2262 goto out_unbind;
2263 }
2264
b481de9c
ZY		 2265 /* We have our copies now, allow OS release its copies */
2266 release_firmware(ucode_raw);
a15707d8 2267 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2268 return;
2269
2270 try_again:
2271 /* try next, if any */
2272 if (iwl_request_firmware(priv, false))
2273 goto out_unbind;
2274 release_firmware(ucode_raw);
2275 return;
b481de9c
ZY		 2276
2277 err_pci_alloc:
15b1687c 2278 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2279 iwl_dealloc_ucode_pci(priv);
b08dfd04 2280 out_unbind:
a15707d8 2281 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2282 device_release_driver(&priv->pci_dev->dev);
b481de9c 2283 release_firmware(ucode_raw);
b481de9c
ZY		 2284}
2285
b7a79404
RC		 2286static const char *desc_lookup_text[] = {
2287 "OK",
2288 "FAIL",
2289 "BAD_PARAM",
2290 "BAD_CHECKSUM",
2291 "NMI_INTERRUPT_WDG",
2292 "SYSASSERT",
2293 "FATAL_ERROR",
2294 "BAD_COMMAND",
2295 "HW_ERROR_TUNE_LOCK",
2296 "HW_ERROR_TEMPERATURE",
2297 "ILLEGAL_CHAN_FREQ",
2298 "VCC_NOT_STABLE",
2299 "FH_ERROR",
2300 "NMI_INTERRUPT_HOST",
2301 "NMI_INTERRUPT_ACTION_PT",
2302 "NMI_INTERRUPT_UNKNOWN",
2303 "UCODE_VERSION_MISMATCH",
2304 "HW_ERROR_ABS_LOCK",
2305 "HW_ERROR_CAL_LOCK_FAIL",
2306 "NMI_INTERRUPT_INST_ACTION_PT",
2307 "NMI_INTERRUPT_DATA_ACTION_PT",
2308 "NMI_TRM_HW_ER",
2309 "NMI_INTERRUPT_TRM",
2310 "NMI_INTERRUPT_BREAK_POINT"
2311 "DEBUG_0",
2312 "DEBUG_1",
2313 "DEBUG_2",
2314 "DEBUG_3",
b7a79404
RC		 2315};
2316
4b58645c
JS		 2317static struct { char *name; u8 num; } advanced_lookup[] = {
2318 { "NMI_INTERRUPT_WDG", 0x34 },
2319 { "SYSASSERT", 0x35 },
2320 { "UCODE_VERSION_MISMATCH", 0x37 },
2321 { "BAD_COMMAND", 0x38 },
2322 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2323 { "FATAL_ERROR", 0x3D },
2324 { "NMI_TRM_HW_ERR", 0x46 },
2325 { "NMI_INTERRUPT_TRM", 0x4C },
2326 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2327 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2328 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2329 { "NMI_INTERRUPT_HOST", 0x66 },
2330 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2331 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2332 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2333 { "ADVANCED_SYSASSERT", 0 },
2334};
2335
2336static const char *desc_lookup(u32 num)
b7a79404 2337{
4b58645c
JS		 2338 int i;
2339 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 2340
4b58645c
JS		 2341 if (num < max)
2342 return desc_lookup_text[num];
b7a79404 2343
4b58645c
JS		 2344 max = ARRAY_SIZE(advanced_lookup) - 1;
2345 for (i = 0; i < max; i++) {
2346 if (advanced_lookup[i].num == num)
2347 break;;
2348 }
2349 return advanced_lookup[i].name;
b7a79404
RC		 2350}
2351
2352#define ERROR_START_OFFSET (1 * sizeof(u32))
2353#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2354
2355void iwl_dump_nic_error_log(struct iwl_priv *priv)
2356{
2357 u32 data2, line;
2358 u32 desc, time, count, base, data1;
2359 u32 blink1, blink2, ilink1, ilink2;
461ef382 2360 u32 pc, hcmd;
b7a79404 2361
b2e640d4 2362 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2363 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2364 if (!base)
2365 base = priv->_agn.init_errlog_ptr;
2366 } else {
b7a79404 2367 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2368 if (!base)
2369 base = priv->_agn.inst_errlog_ptr;
2370 }
b7a79404
RC		 2371
2372 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2373 IWL_ERR(priv,
2374 "Not valid error log pointer 0x%08X for %s uCode\n",
2375 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2376 return;
2377 }
2378
2379 count = iwl_read_targ_mem(priv, base);
2380
2381 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2382 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2383 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2384 priv->status, count);
2385 }
2386
2387 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
461ef382 2388 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2389 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2390 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2391 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2392 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2393 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2394 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2395 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2396 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2397 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2398
be1a71a1
JB		 2399 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2400 blink1, blink2, ilink1, ilink2);
2401
87563715 2402 IWL_ERR(priv, "Desc Time "
b7a79404 2403 "data1 data2 line\n");
87563715 2404 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2405 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2406 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2407 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2408 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2409}
2410
2411#define EVENT_START_OFFSET (4 * sizeof(u32))
2412
2413/**
2414 * iwl_print_event_log - Dump error event log to syslog
2415 *
2416 */
b03d7d0f
WYG		 2417static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2418 u32 num_events, u32 mode,
2419 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2420{
2421 u32 i;
2422 u32 base; /* SRAM byte address of event log header */
2423 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2424 u32 ptr; /* SRAM byte address of log data */
2425 u32 ev, time, data; /* event log data */
e5854471 2426 unsigned long reg_flags;
b7a79404
RC		 2427
2428 if (num_events == 0)
b03d7d0f 2429 return pos;
b2e640d4
JB		 2430
2431 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2432 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2433 if (!base)
2434 base = priv->_agn.init_evtlog_ptr;
2435 } else {
b7a79404 2436 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2437 if (!base)
2438 base = priv->_agn.inst_evtlog_ptr;
2439 }
b7a79404
RC		 2440
2441 if (mode == 0)
2442 event_size = 2 * sizeof(u32);
2443 else
2444 event_size = 3 * sizeof(u32);
2445
2446 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2447
e5854471
BC		 2448 /* Make sure device is powered up for SRAM reads */
2449 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2450 iwl_grab_nic_access(priv);
2451
2452 /* Set starting address; reads will auto-increment */
2453 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2454 rmb();
2455
b7a79404
RC		 2456 /* "time" is actually "data" for mode 0 (no timestamp).
2457 * place event id # at far right for easier visual parsing. */
2458 for (i = 0; i < num_events; i++) {
e5854471
BC		 2459 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2460 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2461 if (mode == 0) {
2462 /* data, ev */
b03d7d0f
WYG		 2463 if (bufsz) {
2464 pos += scnprintf(*buf + pos, bufsz - pos,
2465 "EVT_LOG:0x%08x:%04u\n",
2466 time, ev);
2467 } else {
2468 trace_iwlwifi_dev_ucode_event(priv, 0,
2469 time, ev);
2470 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2471 time, ev);
2472 }
b7a79404 2473 } else {
e5854471 2474 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2475 if (bufsz) {
2476 pos += scnprintf(*buf + pos, bufsz - pos,
2477 "EVT_LOGT:%010u:0x%08x:%04u\n",
2478 time, data, ev);
2479 } else {
2480 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2481 time, data, ev);
b03d7d0f
WYG		 2482 trace_iwlwifi_dev_ucode_event(priv, time,
2483 data, ev);
2484 }
b7a79404
RC		 2485 }
2486 }
e5854471
BC		 2487
2488 /* Allow device to power down */
2489 iwl_release_nic_access(priv);
2490 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2491 return pos;
b7a79404
RC		 2492}
2493
c341ddb2
WYG		 2494/**
2495 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2496 */
b03d7d0f
WYG		 2497static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2498 u32 num_wraps, u32 next_entry,
2499 u32 size, u32 mode,
2500 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2501{
2502 /*
2503 * display the newest DEFAULT_LOG_ENTRIES entries
2504 * i.e the entries just before the next ont that uCode would fill.
2505 */
2506 if (num_wraps) {
2507 if (next_entry < size) {
b03d7d0f
WYG		 2508 pos = iwl_print_event_log(priv,
2509 capacity - (size - next_entry),
2510 size - next_entry, mode,
2511 pos, buf, bufsz);
2512 pos = iwl_print_event_log(priv, 0,
2513 next_entry, mode,
2514 pos, buf, bufsz);
c341ddb2 2515 } else
b03d7d0f
WYG		 2516 pos = iwl_print_event_log(priv, next_entry - size,
2517 size, mode, pos, buf, bufsz);
c341ddb2 2518 } else {
b03d7d0f
WYG		 2519 if (next_entry < size) {
2520 pos = iwl_print_event_log(priv, 0, next_entry,
2521 mode, pos, buf, bufsz);
2522 } else {
2523 pos = iwl_print_event_log(priv, next_entry - size,
2524 size, mode, pos, buf, bufsz);
2525 }
c341ddb2 2526 }
b03d7d0f 2527 return pos;
c341ddb2
WYG		 2528}
2529
c341ddb2
WYG		 2530#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2531
b03d7d0f
WYG		 2532int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2533 char **buf, bool display)
b7a79404
RC		 2534{
2535 u32 base; /* SRAM byte address of event log header */
2536 u32 capacity; /* event log capacity in # entries */
2537 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2538 u32 num_wraps; /* # times uCode wrapped to top of log */
2539 u32 next_entry; /* index of next entry to be written by uCode */
2540 u32 size; /* # entries that we'll print */
b2e640d4 2541 u32 logsize;
b03d7d0f
WYG		 2542 int pos = 0;
2543 size_t bufsz = 0;
b7a79404 2544
b2e640d4 2545 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2546 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2547 logsize = priv->_agn.init_evtlog_size;
2548 if (!base)
2549 base = priv->_agn.init_evtlog_ptr;
2550 } else {
b7a79404 2551 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2552 logsize = priv->_agn.inst_evtlog_size;
2553 if (!base)
2554 base = priv->_agn.inst_evtlog_ptr;
2555 }
b7a79404
RC		 2556
2557 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2558 IWL_ERR(priv,
2559 "Invalid event log pointer 0x%08X for %s uCode\n",
2560 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2561 return -EINVAL;
b7a79404
RC		 2562 }
2563
2564 /* event log header */
2565 capacity = iwl_read_targ_mem(priv, base);
2566 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2567 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2568 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2569
b2e640d4 2570 if (capacity > logsize) {
84c40692 2571 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2572 capacity, logsize);
2573 capacity = logsize;
84c40692
BC		 2574 }
2575
b2e640d4 2576 if (next_entry > logsize) {
84c40692 2577 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2578 next_entry, logsize);
2579 next_entry = logsize;
84c40692
BC		 2580 }
2581
b7a79404
RC		 2582 size = num_wraps ? capacity : next_entry;
2583
2584 /* bail out if nothing in log */
2585 if (size == 0) {
2586 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2587 return pos;
b7a79404
RC		 2588 }
2589
c341ddb2 2590#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2591 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2592 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2593 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2594#else
2595 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2596 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2597#endif
2598 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2599 size);
b7a79404 2600
c341ddb2 2601#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2602 if (display) {
2603 if (full_log)
2604 bufsz = capacity * 48;
2605 else
2606 bufsz = size * 48;
2607 *buf = kmalloc(bufsz, GFP_KERNEL);
2608 if (!*buf)
937c397e 2609 return -ENOMEM;
b03d7d0f 2610 }
c341ddb2
WYG		 2611 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2612 /*
2613 * if uCode has wrapped back to top of log,
2614 * start at the oldest entry,
2615 * i.e the next one that uCode would fill.
2616 */
2617 if (num_wraps)
b03d7d0f
WYG		 2618 pos = iwl_print_event_log(priv, next_entry,
2619 capacity - next_entry, mode,
2620 pos, buf, bufsz);
c341ddb2 2621 /* (then/else) start at top of log */
b03d7d0f
WYG		 2622 pos = iwl_print_event_log(priv, 0,
2623 next_entry, mode, pos, buf, bufsz);
c341ddb2 2624 } else
b03d7d0f
WYG		 2625 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2626 next_entry, size, mode,
2627 pos, buf, bufsz);
c341ddb2 2628#else
b03d7d0f
WYG		 2629 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2630 next_entry, size, mode,
2631 pos, buf, bufsz);
b7a79404 2632#endif
b03d7d0f 2633 return pos;
c341ddb2 2634}
b7a79404 2635
b481de9c 2636/**
4a4a9e81 2637 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2638 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2639 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2640 */
4a4a9e81 2641static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2642{
57aab75a 2643 int ret = 0;
b481de9c 2644
e1623446 2645 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2646
2647 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2648 /* We had an error bringing up the hardware, so take it
2649 * all the way back down so we can try again */
e1623446 2650 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2651 goto restart;
2652 }
2653
2654 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2655 * This is a paranoid check, because we would not have gotten the
2656 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2657 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2658 /* Runtime instruction load was bad;
2659 * take it all the way back down so we can try again */
e1623446 2660 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2661 goto restart;
2662 }
2663
57aab75a
TW		 2664 ret = priv->cfg->ops->lib->alive_notify(priv);
2665 if (ret) {
39aadf8c
WT		 2666 IWL_WARN(priv,
2667 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2668 goto restart;
2669 }
2670
5b9f8cd3 2671 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2672 set_bit(STATUS_ALIVE, &priv->status);
2673
b74e31a9
WYG		 2674 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2675 /* Enable timer to monitor the driver queues */
2676 mod_timer(&priv->monitor_recover,
2677 jiffies +
2678 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2679 }
2680
fee1247a 2681 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2682 return;
2683
36d6825b 2684 ieee80211_wake_queues(priv->hw);
b481de9c 2685
470ab2dd 2686 priv->active_rate = IWL_RATES_MASK;
b481de9c 2687
2f748dec
WYG		 2688 /* Configure Tx antenna selection based on H/W config */
2689 if (priv->cfg->ops->hcmd->set_tx_ant)
2690 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2691
3109ece1 2692 if (iwl_is_associated(priv)) {
c1adf9fb
GG		 2693 struct iwl_rxon_cmd *active_rxon =
2694 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA		 2695 /* apply any changes in staging */
2696 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2697 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2698 } else {
2699 /* Initialize our rx_config data */
1dda6d28 2700 iwl_connection_init_rx_config(priv, NULL);
45823531
AK		 2701
2702 if (priv->cfg->ops->hcmd->set_rxon_chain)
2703 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY		 2704 }
2705
9fbab516 2706 /* Configure Bluetooth device coexistence support */
65b52bde 2707 priv->cfg->ops->hcmd->send_bt_config(priv);
b481de9c 2708
4a4a9e81
TW		 2709 iwl_reset_run_time_calib(priv);
2710
b481de9c 2711 /* Configure the adapter for unassociated operation */
e0158e61 2712 iwlcore_commit_rxon(priv);
b481de9c
ZY		 2713
2714 /* At this point, the NIC is initialized and operational */
47f4a587 2715 iwl_rf_kill_ct_config(priv);
5a66926a 2716
e932a609 2717 iwl_leds_init(priv);
fe00b5a5 2718
e1623446 2719 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2720 set_bit(STATUS_READY, &priv->status);
5a66926a 2721 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2722
e312c24c 2723 iwl_power_update_mode(priv, true);
7e246191
RC		 2724 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2725
c46fbefa 2726
b481de9c
ZY		 2727 return;
2728
2729 restart:
2730 queue_work(priv->workqueue, &priv->restart);
2731}
2732
4e39317d 2733static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2734
5b9f8cd3 2735static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2736{
2737 unsigned long flags;
2738 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2739
e1623446 2740 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2741
b481de9c
ZY		 2742 if (!exit_pending)
2743 set_bit(STATUS_EXIT_PENDING, &priv->status);
2744
2c810ccd
JB		 2745 iwl_clear_ucode_stations(priv);
2746 iwl_dealloc_bcast_station(priv);
db125c78 2747 iwl_clear_driver_stations(priv);
b481de9c
ZY		 2748
2749 /* Unblock any waiting calls */
2750 wake_up_interruptible_all(&priv->wait_command_queue);
2751
b481de9c
ZY		 2752 /* Wipe out the EXIT_PENDING status bit if we are not actually
2753 * exiting the module */
2754 if (!exit_pending)
2755 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2756
2757 /* stop and reset the on-board processor */
3395f6e9 2758 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2759
2760 /* tell the device to stop sending interrupts */
0359facc 2761 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2762 iwl_disable_interrupts(priv);
0359facc
MA		 2763 spin_unlock_irqrestore(&priv->lock, flags);
2764 iwl_synchronize_irq(priv);
b481de9c
ZY		 2765
2766 if (priv->mac80211_registered)
2767 ieee80211_stop_queues(priv->hw);
2768
5b9f8cd3 2769 /* If we have not previously called iwl_init() then
a60e77e5 2770 * clear all bits but the RF Kill bit and return */
fee1247a 2771 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2772 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2773 STATUS_RF_KILL_HW |
9788864e
RC		 2774 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2775 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2776 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2777 STATUS_EXIT_PENDING;
b481de9c
ZY		 2778 goto exit;
2779 }
2780
6da3a13e 2781 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2782 * bit and continue taking the NIC down. */
b481de9c
ZY		 2783 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2784 STATUS_RF_KILL_HW |
9788864e
RC		 2785 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2786 STATUS_GEO_CONFIGURED |
b481de9c 2787 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2788 STATUS_FW_ERROR |
2789 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2790 STATUS_EXIT_PENDING;
b481de9c 2791
ef850d7c
MA		 2792 /* device going down, Stop using ICT table */
2793 iwl_disable_ict(priv);
b481de9c 2794
74bcdb33 2795 iwlagn_txq_ctx_stop(priv);
54b81550 2796 iwlagn_rxq_stop(priv);
b481de9c 2797
309e731a
BC		 2798 /* Power-down device's busmaster DMA clocks */
2799 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2800 udelay(5);
2801
309e731a
BC		 2802 /* Make sure (redundant) we've released our request to stay awake */
2803 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2804
4d2ccdb9
BC		 2805 /* Stop the device, and put it in low power state */
2806 priv->cfg->ops->lib->apm_ops.stop(priv);
2807
b481de9c 2808 exit:
885ba202 2809 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 2810
2811 if (priv->ibss_beacon)
2812 dev_kfree_skb(priv->ibss_beacon);
2813 priv->ibss_beacon = NULL;
2814
2815 /* clear out any free frames */
fcab423d 2816 iwl_clear_free_frames(priv);
b481de9c
ZY		 2817}
2818
5b9f8cd3 2819static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2820{
2821 mutex_lock(&priv->mutex);
5b9f8cd3 2822 __iwl_down(priv);
b481de9c 2823 mutex_unlock(&priv->mutex);
b24d22b1 2824
4e39317d 2825 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2826}
2827
086ed117
MA		 2828#define HW_READY_TIMEOUT (50)
2829
2830static int iwl_set_hw_ready(struct iwl_priv *priv)
2831{
2832 int ret = 0;
2833
2834 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2835 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2836
2837 /* See if we got it */
2838 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2839 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2840 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2841 HW_READY_TIMEOUT);
2842 if (ret != -ETIMEDOUT)
2843 priv->hw_ready = true;
2844 else
2845 priv->hw_ready = false;
2846
2847 IWL_DEBUG_INFO(priv, "hardware %s\n",
2848 (priv->hw_ready == 1) ? "ready" : "not ready");
2849 return ret;
2850}
2851
2852static int iwl_prepare_card_hw(struct iwl_priv *priv)
2853{
2854 int ret = 0;
2855
91dd6c27 2856 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2857
3354a0f6
MA		 2858 ret = iwl_set_hw_ready(priv);
2859 if (priv->hw_ready)
2860 return ret;
2861
2862 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 2863 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2864 CSR_HW_IF_CONFIG_REG_PREPARE);
2865
2866 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2867 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2868 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2869
3354a0f6 2870 /* HW should be ready by now, check again. */
086ed117
MA		 2871 if (ret != -ETIMEDOUT)
2872 iwl_set_hw_ready(priv);
2873
2874 return ret;
2875}
2876
b481de9c
ZY		 2877#define MAX_HW_RESTARTS 5
2878
5b9f8cd3 2879static int __iwl_up(struct iwl_priv *priv)
b481de9c 2880{
57aab75a
TW		 2881 int i;
2882 int ret;
b481de9c
ZY		 2883
2884 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2885 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 2886 return -EIO;
2887 }
2888
e903fbd4 2889 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2890 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 2891 return -EIO;
2892 }
2893
2c810ccd
JB		 2894 ret = iwl_alloc_bcast_station(priv, true);
2895 if (ret)
2896 return ret;
2897
086ed117
MA		 2898 iwl_prepare_card_hw(priv);
2899
2900 if (!priv->hw_ready) {
2901 IWL_WARN(priv, "Exit HW not ready\n");
2902 return -EIO;
2903 }
2904
e655b9f0 2905 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2906 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2907 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2908 else
e655b9f0 2909 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2910
c1842d61 2911 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 2912 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2913
5b9f8cd3 2914 iwl_enable_interrupts(priv);
a60e77e5 2915 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2916 return 0;
b481de9c
ZY		 2917 }
2918
3395f6e9 2919 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2920
74bcdb33 2921 ret = iwlagn_hw_nic_init(priv);
57aab75a 2922 if (ret) {
15b1687c 2923 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2924 return ret;
b481de9c
ZY		 2925 }
2926
2927 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2928 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2929 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 2930 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2931
2932 /* clear (again), then enable host interrupts */
3395f6e9 2933 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2934 iwl_enable_interrupts(priv);
b481de9c
ZY		 2935
2936 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2937 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2938 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2939
2940 /* Copy original ucode data image from disk into backup cache.
2941 * This will be used to initialize the on-board processor's
2942 * data SRAM for a clean start when the runtime program first loads. */
2943 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2944 priv->ucode_data.len);
b481de9c 2945
b481de9c
ZY		 2946 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2947
b481de9c
ZY		 2948 /* load bootstrap state machine,
2949 * load bootstrap program into processor's memory,
2950 * prepare to load the "initialize" uCode */
57aab75a 2951 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2952
57aab75a 2953 if (ret) {
15b1687c
WT		 2954 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2955 ret);
b481de9c
ZY		 2956 continue;
2957 }
2958
2959 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2960 iwl_nic_start(priv);
b481de9c 2961
e1623446 2962 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 2963
2964 return 0;
2965 }
2966
2967 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2968 __iwl_down(priv);
64e72c3e 2969 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 2970
2971 /* tried to restart and config the device for as long as our
2972 * patience could withstand */
15b1687c 2973 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 2974 return -EIO;
2975}
2976
2977
2978/*****************************************************************************
2979 *
2980 * Workqueue callbacks
2981 *
2982 *****************************************************************************/
2983
4a4a9e81 2984static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2985{
c79dd5b5
TW		 2986 struct iwl_priv *priv =
2987 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 2988
2989 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2990 return;
2991
2992 mutex_lock(&priv->mutex);
f3ccc08c 2993 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 2994 mutex_unlock(&priv->mutex);
2995}
2996
4a4a9e81 2997static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2998{
c79dd5b5
TW		 2999 struct iwl_priv *priv =
3000 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 3001
3002 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3003 return;
3004
258c44a0
MA		 3005 /* enable dram interrupt */
3006 iwl_reset_ict(priv);
3007
b481de9c 3008 mutex_lock(&priv->mutex);
4a4a9e81 3009 iwl_alive_start(priv);
b481de9c
ZY		 3010 mutex_unlock(&priv->mutex);
3011}
3012
16e727e8
EG		 3013static void iwl_bg_run_time_calib_work(struct work_struct *work)
3014{
3015 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3016 run_time_calib_work);
3017
3018 mutex_lock(&priv->mutex);
3019
3020 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3021 test_bit(STATUS_SCANNING, &priv->status)) {
3022 mutex_unlock(&priv->mutex);
3023 return;
3024 }
3025
3026 if (priv->start_calib) {
7980fba5
WYG		 3027 if (priv->cfg->bt_statistics) {
3028 iwl_chain_noise_calibration(priv,
3029 (void *)&priv->_agn.statistics_bt);
3030 iwl_sensitivity_calibration(priv,
3031 (void *)&priv->_agn.statistics_bt);
3032 } else {
3033 iwl_chain_noise_calibration(priv,
3034 (void *)&priv->_agn.statistics);
3035 iwl_sensitivity_calibration(priv,
3036 (void *)&priv->_agn.statistics);
3037 }
16e727e8
EG		 3038 }
3039
3040 mutex_unlock(&priv->mutex);
16e727e8
EG		 3041}
3042
5b9f8cd3 3043static void iwl_bg_restart(struct work_struct *data)
b481de9c 3044{
c79dd5b5 3045 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 3046
3047 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3048 return;
3049
19cc1087
JB		 3050 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3051 mutex_lock(&priv->mutex);
3052 priv->vif = NULL;
3053 priv->is_open = 0;
3054 mutex_unlock(&priv->mutex);
3055 iwl_down(priv);
3056 ieee80211_restart_hw(priv->hw);
3057 } else {
3058 iwl_down(priv);
80676518
JB		 3059
3060 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3061 return;
3062
3063 mutex_lock(&priv->mutex);
3064 __iwl_up(priv);
3065 mutex_unlock(&priv->mutex);
19cc1087 3066 }
b481de9c
ZY		 3067}
3068
5b9f8cd3 3069static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3070{
c79dd5b5
TW		 3071 struct iwl_priv *priv =
3072 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3073
3074 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3075 return;
3076
3077 mutex_lock(&priv->mutex);
54b81550 3078 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3079 mutex_unlock(&priv->mutex);
3080}
3081
7878a5a4
MA		 3082#define IWL_DELAY_NEXT_SCAN (HZ*2)
3083
1dda6d28 3084void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3085{
b481de9c 3086 struct ieee80211_conf *conf = NULL;
857485c0 3087 int ret = 0;
b481de9c 3088
1dda6d28
JB		 3089 if (!vif || !priv->is_open)
3090 return;
3091
3092 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 3093 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 3094 return;
3095 }
3096
b481de9c
ZY		 3097 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3098 return;
3099
2a421b91 3100 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 3101
b481de9c
ZY		 3102 conf = ieee80211_get_hw_conf(priv->hw);
3103
3104 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3105 iwlcore_commit_rxon(priv);
b481de9c 3106
1dda6d28 3107 iwl_setup_rxon_timing(priv, vif);
857485c0 3108 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 3109 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 3110 if (ret)
39aadf8c 3111 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 3112 "Attempting to continue.\n");
3113
3114 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
3115
42eb7c64 3116 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 3117
45823531
AK		 3118 if (priv->cfg->ops->hcmd->set_rxon_chain)
3119 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3120
1dda6d28 3121 priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3122
e1623446 3123 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3124 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3125
c213d745 3126 if (vif->bss_conf.use_short_preamble)
b481de9c
ZY		 3127 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3128 else
3129 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3130
3131 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3132 if (vif->bss_conf.use_short_slot)
b481de9c
ZY		 3133 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
3134 else
3135 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3136 }
3137
e0158e61 3138 iwlcore_commit_rxon(priv);
b481de9c 3139
fe6b23dd 3140 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
1dda6d28 3141 vif->bss_conf.aid, priv->active_rxon.bssid_addr);
fe6b23dd 3142
1dda6d28 3143 switch (vif->type) {
05c914fe 3144 case NL80211_IFTYPE_STATION:
b481de9c 3145 break;
05c914fe 3146 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 3147 iwl_send_beacon_cmd(priv);
b481de9c 3148 break;
b481de9c 3149 default:
15b1687c 3150 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 3151 __func__, vif->type);
b481de9c
ZY		 3152 break;
3153 }
3154
04816448
GE		 3155 /* the chain noise calibration will enabled PM upon completion
3156 * If chain noise has already been run, then we need to enable
3157 * power management here */
3158 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 3159 iwl_power_update_mode(priv, false);
c90a74ba
EG		 3160
3161 /* Enable Rx differential gain and sensitivity calibrations */
3162 iwl_chain_noise_reset(priv);
3163 priv->start_calib = 1;
3164
508e32e1
RC		 3165}
3166
b481de9c
ZY		 3167/*****************************************************************************
3168 *
3169 * mac80211 entry point functions
3170 *
3171 *****************************************************************************/
3172
154b25ce 3173#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3174
f0b6e2e8
RC		 3175/*
3176 * Not a mac80211 entry point function, but it fits in with all the
3177 * other mac80211 functions grouped here.
3178 */
dd7a2509
JB		 3179static int iwl_mac_setup_register(struct iwl_priv *priv,
3180 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3181{
3182 int ret;
3183 struct ieee80211_hw *hw = priv->hw;
3184 hw->rate_control_algorithm = "iwl-agn-rs";
3185
3186 /* Tell mac80211 our characteristics */
3187 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8
RC		 3188 IEEE80211_HW_AMPDU_AGGREGATION |
3189 IEEE80211_HW_SPECTRUM_MGMT;
3190
3191 if (!priv->cfg->broken_powersave)
3192 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3193 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3194
ba37a3d0
JB		 3195 if (priv->cfg->sku & IWL_SKU_N)
3196 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3197 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3198
8d9698b3 3199 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3200 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3201
f0b6e2e8
RC		 3202 hw->wiphy->interface_modes =
3203 BIT(NL80211_IFTYPE_STATION) |
3204 BIT(NL80211_IFTYPE_ADHOC);
3205
f6c8f152 3206 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3207 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3208
3209 /*
3210 * For now, disable PS by default because it affects
3211 * RX performance significantly.
3212 */
5be83de5 3213 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3214
1382c71c 3215 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3216 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3217 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3218
3219 /* Default value; 4 EDCA QOS priorities */
3220 hw->queues = 4;
3221
3222 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3223
3224 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3225 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3226 &priv->bands[IEEE80211_BAND_2GHZ];
3227 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3228 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3229 &priv->bands[IEEE80211_BAND_5GHZ];
3230
3231 ret = ieee80211_register_hw(priv->hw);
3232 if (ret) {
3233 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3234 return ret;
3235 }
3236 priv->mac80211_registered = 1;
3237
3238 return 0;
3239}
3240
3241
5b9f8cd3 3242static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 3243{
c79dd5b5 3244 struct iwl_priv *priv = hw->priv;
5a66926a 3245 int ret;
b481de9c 3246
e1623446 3247 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3248
3249 /* we should be verifying the device is ready to be opened */
3250 mutex_lock(&priv->mutex);
5b9f8cd3 3251 ret = __iwl_up(priv);
b481de9c 3252 mutex_unlock(&priv->mutex);
5a66926a 3253
e655b9f0 3254 if (ret)
6cd0b1cb 3255 return ret;
e655b9f0 3256
c1842d61
TW		 3257 if (iwl_is_rfkill(priv))
3258 goto out;
3259
e1623446 3260 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3261
fe9b6b72 3262 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3263 * mac80211 will not be run successfully. */
154b25ce
EG		 3264 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3265 test_bit(STATUS_READY, &priv->status),
3266 UCODE_READY_TIMEOUT);
3267 if (!ret) {
3268 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3269 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3270 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3271 return -ETIMEDOUT;
5a66926a 3272 }
fe9b6b72 3273 }
0a078ffa 3274
e932a609
JB		 3275 iwl_led_start(priv);
3276
c1842d61 3277out:
0a078ffa 3278 priv->is_open = 1;
e1623446 3279 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3280 return 0;
3281}
3282
5b9f8cd3 3283static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 3284{
c79dd5b5 3285 struct iwl_priv *priv = hw->priv;
b481de9c 3286
e1623446 3287 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3288
19cc1087 3289 if (!priv->is_open)
e655b9f0 3290 return;
e655b9f0 3291
b481de9c 3292 priv->is_open = 0;
5a66926a 3293
5bddf549 3294 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY		 3295 /* stop mac, cancel any scan request and clear
3296 * RXON_FILTER_ASSOC_MSK BIT
3297 */
5a66926a 3298 mutex_lock(&priv->mutex);
2a421b91 3299 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3300 mutex_unlock(&priv->mutex);
fde3571f
MA		 3301 }
3302
5b9f8cd3 3303 iwl_down(priv);
5a66926a
ZY		 3304
3305 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3306
3307 /* enable interrupts again in order to receive rfkill changes */
3308 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3309 iwl_enable_interrupts(priv);
948c171c 3310
e1623446 3311 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3312}
3313
5b9f8cd3 3314static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3315{
c79dd5b5 3316 struct iwl_priv *priv = hw->priv;
b481de9c 3317
e1623446 3318 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3319
e1623446 3320 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3321 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3322
74bcdb33 3323 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3324 dev_kfree_skb_any(skb);
3325
e1623446 3326 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3327 return NETDEV_TX_OK;
b481de9c
ZY		 3328}
3329
1dda6d28 3330void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3331{
857485c0 3332 int ret = 0;
b481de9c 3333
d986bcd1 3334 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 3335 return;
3336
3337 /* The following should be done only at AP bring up */
3195c1f3 3338 if (!iwl_is_associated(priv)) {
b481de9c
ZY		 3339
3340 /* RXON - unassoc (to set timing command) */
3341 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3342 iwlcore_commit_rxon(priv);
b481de9c
ZY		 3343
3344 /* RXON Timing */
1dda6d28 3345 iwl_setup_rxon_timing(priv, vif);
857485c0 3346 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 3347 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 3348 if (ret)
39aadf8c 3349 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 3350 "Attempting to continue.\n");
3351
f513dfff
DH		 3352 /* AP has all antennas */
3353 priv->chain_noise_data.active_chains =
3354 priv->hw_params.valid_rx_ant;
3355 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK		 3356 if (priv->cfg->ops->hcmd->set_rxon_chain)
3357 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c 3358
1dda6d28
JB		 3359 priv->staging_rxon.assoc_id = 0;
3360
c213d745 3361 if (vif->bss_conf.use_short_preamble)
b481de9c
ZY		 3362 priv->staging_rxon.flags |=
3363 RXON_FLG_SHORT_PREAMBLE_MSK;
3364 else
3365 priv->staging_rxon.flags &=
3366 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3367
3368 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3369 if (vif->bss_conf.use_short_slot)
b481de9c
ZY		 3370 priv->staging_rxon.flags |=
3371 RXON_FLG_SHORT_SLOT_MSK;
3372 else
3373 priv->staging_rxon.flags &=
3374 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3375 }
3376 /* restore RXON assoc */
3377 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3378 iwlcore_commit_rxon(priv);
e1493deb 3379 }
5b9f8cd3 3380 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3381
3382 /* FIXME - we need to add code here to detect a totally new
3383 * configuration, reset the AP, unassoc, rxon timing, assoc,
3384 * clear sta table, add BCAST sta... */
3385}
3386
5b9f8cd3 3387static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3388 struct ieee80211_vif *vif,
3389 struct ieee80211_key_conf *keyconf,
3390 struct ieee80211_sta *sta,
3391 u32 iv32, u16 *phase1key)
ab885f8c 3392{
ab885f8c 3393
9f58671e 3394 struct iwl_priv *priv = hw->priv;
e1623446 3395 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3396
bdbb612f 3397 iwl_update_tkip_key(priv, keyconf, sta,
b3fbdcf4 3398 iv32, phase1key);
ab885f8c 3399
e1623446 3400 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3401}
3402
5b9f8cd3 3403static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3404 struct ieee80211_vif *vif,
3405 struct ieee80211_sta *sta,
b481de9c
ZY		 3406 struct ieee80211_key_conf *key)
3407{
c79dd5b5 3408 struct iwl_priv *priv = hw->priv;
42986796
WT		 3409 int ret;
3410 u8 sta_id;
3411 bool is_default_wep_key = false;
b481de9c 3412
e1623446 3413 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3414
90e8e424 3415 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3416 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3417 return -EOPNOTSUPP;
3418 }
b481de9c 3419
0af8bcae
JB		 3420 sta_id = iwl_sta_id_or_broadcast(priv, sta);
3421 if (sta_id == IWL_INVALID_STATION)
3422 return -EINVAL;
b481de9c 3423
6974e363 3424 mutex_lock(&priv->mutex);
2a421b91 3425 iwl_scan_cancel_timeout(priv, 100);
6974e363 3426
a90178fa
JB		 3427 /*
3428 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3429 * so far, we are in legacy wep mode (group key only), otherwise we are
3430 * in 1X mode.
a90178fa
JB		 3431 * In legacy wep mode, we use another host command to the uCode.
3432 */
3433 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
6974e363
EG		 3434 if (cmd == SET_KEY)
3435 is_default_wep_key = !priv->key_mapping_key;
3436 else
ccc038ab
EG		 3437 is_default_wep_key =
3438 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3439 }
052c4b9f 3440
b481de9c 3441 switch (cmd) {
deb09c43 3442 case SET_KEY:
6974e363
EG		 3443 if (is_default_wep_key)
3444 ret = iwl_set_default_wep_key(priv, key);
deb09c43 3445 else
7480513f 3446 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 3447
e1623446 3448 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3449 break;
3450 case DISABLE_KEY:
6974e363
EG		 3451 if (is_default_wep_key)
3452 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 3453 else
3ec47732 3454 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 3455
e1623446 3456 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3457 break;
3458 default:
deb09c43 3459 ret = -EINVAL;
b481de9c
ZY		 3460 }
3461
72e15d71 3462 mutex_unlock(&priv->mutex);
e1623446 3463 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3464
deb09c43 3465 return ret;
b481de9c
ZY		 3466}
3467
cfecc6b4
WYG		 3468/*
3469 * switch to RTS/CTS for TX
3470 */
3471static void iwl_enable_rts_cts(struct iwl_priv *priv)
3472{
3473
3474 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3475 return;
3476
3477 priv->staging_rxon.flags &= ~RXON_FLG_SELF_CTS_EN;
3478 if (!test_bit(STATUS_SCANNING, &priv->status)) {
3479 IWL_DEBUG_INFO(priv, "use RTS/CTS protection\n");
3480 iwlcore_commit_rxon(priv);
3481 } else {
3482 /* scanning, defer the request until scan completed */
3483 IWL_DEBUG_INFO(priv, "defer setting RTS/CTS protection\n");
3484 }
3485}
3486
5b9f8cd3 3487static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3488 struct ieee80211_vif *vif,
832f47e3
JB		 3489 enum ieee80211_ampdu_mlme_action action,
3490 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3491{
3492 struct iwl_priv *priv = hw->priv;
4620fefa 3493 int ret = -EINVAL;
d783b061 3494
e1623446 3495 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3496 sta->addr, tid);
d783b061
TW		 3497
3498 if (!(priv->cfg->sku & IWL_SKU_N))
3499 return -EACCES;
3500
4620fefa
JB		 3501 mutex_lock(&priv->mutex);
3502
d783b061
TW		 3503 switch (action) {
3504 case IEEE80211_AMPDU_RX_START:
e1623446 3505 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3506 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3507 break;
d783b061 3508 case IEEE80211_AMPDU_RX_STOP:
e1623446 3509 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3510 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3511 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3512 ret = 0;
3513 break;
d783b061 3514 case IEEE80211_AMPDU_TX_START:
e1623446 3515 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3516 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3517 if (ret == 0) {
3518 priv->_agn.agg_tids_count++;
3519 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3520 priv->_agn.agg_tids_count);
3521 }
4620fefa 3522 break;
d783b061 3523 case IEEE80211_AMPDU_TX_STOP:
e1623446 3524 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3525 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3526 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3527 priv->_agn.agg_tids_count--;
3528 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3529 priv->_agn.agg_tids_count);
3530 }
5c2207c6 3531 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3532 ret = 0;
3533 break;
f0527971 3534 case IEEE80211_AMPDU_TX_OPERATIONAL:
cfecc6b4
WYG		 3535 if (priv->cfg->use_rts_for_ht) {
3536 /*
3537 * switch to RTS/CTS if it is the prefer protection
3538 * method for HT traffic
3539 */
3540 iwl_enable_rts_cts(priv);
3541 }
3542 ret = 0;
d783b061
TW		 3543 break;
3544 }
4620fefa
JB		 3545 mutex_unlock(&priv->mutex);
3546
3547 return ret;
d783b061 3548}
9f58671e 3549
6ab10ff8
JB		 3550static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3551 struct ieee80211_vif *vif,
3552 enum sta_notify_cmd cmd,
3553 struct ieee80211_sta *sta)
3554{
3555 struct iwl_priv *priv = hw->priv;
3556 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3557 int sta_id;
3558
6ab10ff8 3559 switch (cmd) {
6ab10ff8
JB		 3560 case STA_NOTIFY_SLEEP:
3561 WARN_ON(!sta_priv->client);
3562 sta_priv->asleep = true;
3563 if (atomic_read(&sta_priv->pending_frames) > 0)
3564 ieee80211_sta_block_awake(hw, sta, true);
3565 break;
3566 case STA_NOTIFY_AWAKE:
3567 WARN_ON(!sta_priv->client);
49dcc819
DH		 3568 if (!sta_priv->asleep)
3569 break;
6ab10ff8 3570 sta_priv->asleep = false;
2a87c26b 3571 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3572 if (sta_id != IWL_INVALID_STATION)
3573 iwl_sta_modify_ps_wake(priv, sta_id);
3574 break;
3575 default:
3576 break;
3577 }
3578}
3579
fe6b23dd
RC		 3580static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3581 struct ieee80211_vif *vif,
3582 struct ieee80211_sta *sta)
3583{
3584 struct iwl_priv *priv = hw->priv;
3585 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
eafdfbd3 3586 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3587 int ret;
3588 u8 sta_id;
3589
3590 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3591 sta->addr);
da5ae1cf
RC		 3592 mutex_lock(&priv->mutex);
3593 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3594 sta->addr);
3595 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3596
3597 atomic_set(&sta_priv->pending_frames, 0);
3598 if (vif->type == NL80211_IFTYPE_AP)
3599 sta_priv->client = true;
3600
3601 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3602 &sta_id);
3603 if (ret) {
3604 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3605 sta->addr, ret);
3606 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3607 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3608 return ret;
3609 }
3610
fd1af15d
JB		 3611 sta_priv->common.sta_id = sta_id;
3612
fe6b23dd 3613 /* Initialize rate scaling */
91dd6c27 3614 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3615 sta->addr);
3616 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3617 mutex_unlock(&priv->mutex);
fe6b23dd 3618
fd1af15d 3619 return 0;
fe6b23dd
RC		 3620}
3621
79d07325
WYG		 3622static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3623 struct ieee80211_channel_switch *ch_switch)
3624{
3625 struct iwl_priv *priv = hw->priv;
3626 const struct iwl_channel_info *ch_info;
3627 struct ieee80211_conf *conf = &hw->conf;
3628 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3629 u16 ch;
3630 unsigned long flags = 0;
3631
3632 IWL_DEBUG_MAC80211(priv, "enter\n");
3633
3634 if (iwl_is_rfkill(priv))
3635 goto out_exit;
3636
3637 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3638 test_bit(STATUS_SCANNING, &priv->status))
3639 goto out_exit;
3640
3641 if (!iwl_is_associated(priv))
3642 goto out_exit;
3643
3644 /* channel switch in progress */
3645 if (priv->switch_rxon.switch_in_progress == true)
3646 goto out_exit;
3647
3648 mutex_lock(&priv->mutex);
3649 if (priv->cfg->ops->lib->set_channel_switch) {
3650
3651 ch = ieee80211_frequency_to_channel(
3652 ch_switch->channel->center_freq);
3653 if (le16_to_cpu(priv->active_rxon.channel) != ch) {
3654 ch_info = iwl_get_channel_info(priv,
3655 conf->channel->band,
3656 ch);
3657 if (!is_channel_valid(ch_info)) {
3658 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3659 goto out;
3660 }
3661 spin_lock_irqsave(&priv->lock, flags);
3662
3663 priv->current_ht_config.smps = conf->smps_mode;
3664
3665 /* Configure HT40 channels */
3666 ht_conf->is_ht = conf_is_ht(conf);
3667 if (ht_conf->is_ht) {
3668 if (conf_is_ht40_minus(conf)) {
3669 ht_conf->extension_chan_offset =
3670 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3671 ht_conf->is_40mhz = true;
3672 } else if (conf_is_ht40_plus(conf)) {
3673 ht_conf->extension_chan_offset =
3674 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3675 ht_conf->is_40mhz = true;
3676 } else {
3677 ht_conf->extension_chan_offset =
3678 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3679 ht_conf->is_40mhz = false;
3680 }
3681 } else
3682 ht_conf->is_40mhz = false;
3683
3684 /* if we are switching from ht to 2.4 clear flags
3685 * from any ht related info since 2.4 does not
3686 * support ht */
3687 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
3688 priv->staging_rxon.flags = 0;
3689
3690 iwl_set_rxon_channel(priv, conf->channel);
3691 iwl_set_rxon_ht(priv, ht_conf);
3692 iwl_set_flags_for_band(priv, conf->channel->band,
3693 priv->vif);
3694 spin_unlock_irqrestore(&priv->lock, flags);
3695
3696 iwl_set_rate(priv);
3697 /*
3698 * at this point, staging_rxon has the
3699 * configuration for channel switch
3700 */
3701 if (priv->cfg->ops->lib->set_channel_switch(priv,
3702 ch_switch))
3703 priv->switch_rxon.switch_in_progress = false;
3704 }
3705 }
3706out:
3707 mutex_unlock(&priv->mutex);
3708out_exit:
3709 if (!priv->switch_rxon.switch_in_progress)
3710 ieee80211_chswitch_done(priv->vif, false);
3711 IWL_DEBUG_MAC80211(priv, "leave\n");
3712}
3713
716c74b0
WYG		 3714static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3715{
3716 struct iwl_priv *priv = hw->priv;
3717
3718 mutex_lock(&priv->mutex);
3719 IWL_DEBUG_MAC80211(priv, "enter\n");
3720
3721 /* do not support "flush" */
3722 if (!priv->cfg->ops->lib->txfifo_flush)
3723 goto done;
3724
3725 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3726 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3727 goto done;
3728 }
3729 if (iwl_is_rfkill(priv)) {
3730 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3731 goto done;
3732 }
3733
3734 /*
3735 * mac80211 will not push any more frames for transmit
3736 * until the flush is completed
3737 */
3738 if (drop) {
3739 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3740 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3741 IWL_ERR(priv, "flush request fail\n");
3742 goto done;
3743 }
3744 }
3745 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3746 iwlagn_wait_tx_queue_empty(priv);
3747done:
3748 mutex_unlock(&priv->mutex);
3749 IWL_DEBUG_MAC80211(priv, "leave\n");
3750}
3751
b481de9c
ZY		 3752/*****************************************************************************
3753 *
3754 * driver setup and teardown
3755 *
3756 *****************************************************************************/
3757
4e39317d 3758static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3759{
d21050c7 3760 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 3761
3762 init_waitqueue_head(&priv->wait_command_queue);
3763
5b9f8cd3
EG		 3764 INIT_WORK(&priv->restart, iwl_bg_restart);
3765 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3766 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3767 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 3768 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
4a4a9e81
TW		 3769 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3770 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3771
2a421b91 3772 iwl_setup_scan_deferred_work(priv);
bb8c093b 3773
4e39317d
EG		 3774 if (priv->cfg->ops->lib->setup_deferred_work)
3775 priv->cfg->ops->lib->setup_deferred_work(priv);
3776
3777 init_timer(&priv->statistics_periodic);
3778 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3779 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3780
a9e1cb6a
WYG		 3781 init_timer(&priv->ucode_trace);
3782 priv->ucode_trace.data = (unsigned long)priv;
3783 priv->ucode_trace.function = iwl_bg_ucode_trace;
3784
b74e31a9
WYG		 3785 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3786 init_timer(&priv->monitor_recover);
3787 priv->monitor_recover.data = (unsigned long)priv;
3788 priv->monitor_recover.function =
3789 priv->cfg->ops->lib->recover_from_tx_stall;
3790 }
3791
ef850d7c
MA		 3792 if (!priv->cfg->use_isr_legacy)
3793 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3794 iwl_irq_tasklet, (unsigned long)priv);
3795 else
3796 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3797 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 3798}
3799
4e39317d 3800static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3801{
4e39317d
EG		 3802 if (priv->cfg->ops->lib->cancel_deferred_work)
3803 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3804
3ae6a054 3805 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3806 cancel_delayed_work(&priv->scan_check);
88be0264 3807 cancel_work_sync(&priv->start_internal_scan);
b481de9c 3808 cancel_delayed_work(&priv->alive_start);
815e629b 3809 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 3810 cancel_work_sync(&priv->beacon_update);
4e39317d 3811 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3812 del_timer_sync(&priv->ucode_trace);
b74e31a9
WYG		 3813 if (priv->cfg->ops->lib->recover_from_tx_stall)
3814 del_timer_sync(&priv->monitor_recover);
b481de9c
ZY		 3815}
3816
89f186a8
RC		 3817static void iwl_init_hw_rates(struct iwl_priv *priv,
3818 struct ieee80211_rate *rates)
3819{
3820 int i;
3821
3822 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3823 rates[i].bitrate = iwl_rates[i].ieee * 5;
3824 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3825 rates[i].hw_value_short = i;
3826 rates[i].flags = 0;
3827 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3828 /*
3829 * If CCK != 1M then set short preamble rate flag.
3830 */
3831 rates[i].flags |=
3832 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3833 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3834 }
3835 }
3836}
3837
3838static int iwl_init_drv(struct iwl_priv *priv)
3839{
3840 int ret;
3841
3842 priv->ibss_beacon = NULL;
3843
89f186a8
RC		 3844 spin_lock_init(&priv->sta_lock);
3845 spin_lock_init(&priv->hcmd_lock);
3846
3847 INIT_LIST_HEAD(&priv->free_frames);
3848
3849 mutex_init(&priv->mutex);
d2dfe6df 3850 mutex_init(&priv->sync_cmd_mutex);
89f186a8 3851
89f186a8
RC		 3852 priv->ieee_channels = NULL;
3853 priv->ieee_rates = NULL;
3854 priv->band = IEEE80211_BAND_2GHZ;
3855
3856 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3857 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3858 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3859 priv->_agn.agg_tids_count = 0;
89f186a8 3860
8a472da4
WYG		 3861 /* initialize force reset */
3862 priv->force_reset[IWL_RF_RESET].reset_duration =
3863 IWL_DELAY_NEXT_FORCE_RF_RESET;
3864 priv->force_reset[IWL_FW_RESET].reset_duration =
3865 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 3866
3867 /* Choose which receivers/antennas to use */
3868 if (priv->cfg->ops->hcmd->set_rxon_chain)
3869 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3870
3871 iwl_init_scan_params(priv);
3872
89f186a8
RC		 3873 /* Set the tx_power_user_lmt to the lowest power level
3874 * this value will get overwritten by channel max power avg
3875 * from eeprom */
b744cb79 3876 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 3877
3878 ret = iwl_init_channel_map(priv);
3879 if (ret) {
3880 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3881 goto err;
3882 }
3883
3884 ret = iwlcore_init_geos(priv);
3885 if (ret) {
3886 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3887 goto err_free_channel_map;
3888 }
3889 iwl_init_hw_rates(priv, priv->ieee_rates);
3890
3891 return 0;
3892
3893err_free_channel_map:
3894 iwl_free_channel_map(priv);
3895err:
3896 return ret;
3897}
3898
3899static void iwl_uninit_drv(struct iwl_priv *priv)
3900{
3901 iwl_calib_free_results(priv);
3902 iwlcore_free_geos(priv);
3903 iwl_free_channel_map(priv);
811ecc99 3904 kfree(priv->scan_cmd);
89f186a8
RC		 3905}
3906
5b9f8cd3
EG		 3907static struct ieee80211_ops iwl_hw_ops = {
3908 .tx = iwl_mac_tx,
3909 .start = iwl_mac_start,
3910 .stop = iwl_mac_stop,
3911 .add_interface = iwl_mac_add_interface,
3912 .remove_interface = iwl_mac_remove_interface,
3913 .config = iwl_mac_config,
5b9f8cd3
EG		 3914 .configure_filter = iwl_configure_filter,
3915 .set_key = iwl_mac_set_key,
3916 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 3917 .conf_tx = iwl_mac_conf_tx,
3918 .reset_tsf = iwl_mac_reset_tsf,
3919 .bss_info_changed = iwl_bss_info_changed,
3920 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 3921 .hw_scan = iwl_mac_hw_scan,
3922 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 3923 .sta_add = iwlagn_mac_sta_add,
3924 .sta_remove = iwl_mac_sta_remove,
79d07325 3925 .channel_switch = iwl_mac_channel_switch,
716c74b0 3926 .flush = iwl_mac_flush,
b481de9c
ZY		 3927};
3928
5b9f8cd3 3929static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 3930{
3931 int err = 0;
c79dd5b5 3932 struct iwl_priv *priv;
b481de9c 3933 struct ieee80211_hw *hw;
82b9a121 3934 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3935 unsigned long flags;
c6fa17ed 3936 u16 pci_cmd, num_mac;
b481de9c 3937
316c30d9
AK		 3938 /************************
3939 * 1. Allocating HW data
3940 ************************/
3941
6440adb5
CB		 3942 /* Disabling hardware scan means that mac80211 will perform scans
3943 * "the hard way", rather than using device's scan. */
1ea87396 3944 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3945 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK		 3946 dev_printk(KERN_DEBUG, &(pdev->dev),
3947 "Disabling hw_scan\n");
5b9f8cd3 3948 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 3949 }
3950
5b9f8cd3 3951 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3952 if (!hw) {
b481de9c
ZY		 3953 err = -ENOMEM;
3954 goto out;
3955 }
1d0a082d
AK		 3956 priv = hw->priv;
3957 /* At this point both hw and priv are allocated. */
3958
b481de9c
ZY		 3959 SET_IEEE80211_DEV(hw, &pdev->dev);
3960
e1623446 3961 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3962 priv->cfg = cfg;
b481de9c 3963 priv->pci_dev = pdev;
40cefda9 3964 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3965
20594eb0
WYG		 3966 if (iwl_alloc_traffic_mem(priv))
3967 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3968
316c30d9
AK		 3969 /**************************
3970 * 2. Initializing PCI bus
3971 **************************/
1a7123cd
JL		 3972 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3973 PCIE_LINK_STATE_CLKPM);
3974
316c30d9
AK		 3975 if (pci_enable_device(pdev)) {
3976 err = -ENODEV;
3977 goto out_ieee80211_free_hw;
3978 }
3979
3980 pci_set_master(pdev);
3981
093d874c 3982 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3983 if (!err)
093d874c 3984 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3985 if (err) {
093d874c 3986 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3987 if (!err)
093d874c 3988 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3989 /* both attempts failed: */
316c30d9 3990 if (err) {
978785a3 3991 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3992 goto out_pci_disable_device;
cc2a8ea8 3993 }
316c30d9
AK		 3994 }
3995
3996 err = pci_request_regions(pdev, DRV_NAME);
3997 if (err)
3998 goto out_pci_disable_device;
3999
4000 pci_set_drvdata(pdev, priv);
4001
316c30d9
AK		 4002
4003 /***********************
4004 * 3. Read REV register
4005 ***********************/
4006 priv->hw_base = pci_iomap(pdev, 0, 0);
4007 if (!priv->hw_base) {
4008 err = -ENODEV;
4009 goto out_pci_release_regions;
4010 }
4011
e1623446 4012 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 4013 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4014 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 4015
731a29b7 4016 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 4017 * we should init now
4018 */
4019 spin_lock_init(&priv->reg_lock);
731a29b7 4020 spin_lock_init(&priv->lock);
4843b5a7
RC		 4021
4022 /*
4023 * stop and reset the on-board processor just in case it is in a
4024 * strange state ... like being left stranded by a primary kernel
4025 * and this is now the kdump kernel trying to start up
4026 */
4027 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4028
b661c819 4029 iwl_hw_detect(priv);
c11362c0 4030 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 4031 priv->cfg->name, priv->hw_rev);
316c30d9 4032
e7b63581
TW		 4033 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4034 * PCI Tx retries from interfering with C3 CPU state */
4035 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4036
086ed117
MA		 4037 iwl_prepare_card_hw(priv);
4038 if (!priv->hw_ready) {
4039 IWL_WARN(priv, "Failed, HW not ready\n");
4040 goto out_iounmap;
4041 }
4042
91238714
TW		 4043 /*****************
4044 * 4. Read EEPROM
4045 *****************/
316c30d9
AK		 4046 /* Read the EEPROM */
4047 err = iwl_eeprom_init(priv);
4048 if (err) {
15b1687c 4049 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4050 goto out_iounmap;
4051 }
8614f360
TW		 4052 err = iwl_eeprom_check_version(priv);
4053 if (err)
c8f16138 4054 goto out_free_eeprom;
8614f360 4055
02883017 4056 /* extract MAC Address */
c6fa17ed
WYG		 4057 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4058 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4059 priv->hw->wiphy->addresses = priv->addresses;
4060 priv->hw->wiphy->n_addresses = 1;
4061 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4062 if (num_mac > 1) {
4063 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4064 ETH_ALEN);
4065 priv->addresses[1].addr[5]++;
4066 priv->hw->wiphy->n_addresses++;
4067 }
316c30d9
AK		 4068
4069 /************************
4070 * 5. Setup HW constants
4071 ************************/
da154e30 4072 if (iwl_set_hw_params(priv)) {
15b1687c 4073 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4074 goto out_free_eeprom;
316c30d9
AK		 4075 }
4076
4077 /*******************
6ba87956 4078 * 6. Setup priv
316c30d9 4079 *******************/
b481de9c 4080
6ba87956 4081 err = iwl_init_drv(priv);
bf85ea4f 4082 if (err)
399f4900 4083 goto out_free_eeprom;
bf85ea4f 4084 /* At this point both hw and priv are initialized. */
316c30d9 4085
316c30d9 4086 /********************
09f9bf79 4087 * 7. Setup services
316c30d9 4088 ********************/
0359facc 4089 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4090 iwl_disable_interrupts(priv);
0359facc 4091 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4092
6cd0b1cb
HS		 4093 pci_enable_msi(priv->pci_dev);
4094
ef850d7c
MA		 4095 iwl_alloc_isr_ict(priv);
4096 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4097 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4098 if (err) {
4099 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4100 goto out_disable_msi;
4101 }
316c30d9 4102
4e39317d 4103 iwl_setup_deferred_work(priv);
653fa4a0 4104 iwl_setup_rx_handlers(priv);
316c30d9 4105
158bea07
JB		 4106 /*********************************************
4107 * 8. Enable interrupts and read RFKILL state
4108 *********************************************/
6ba87956 4109
6cd0b1cb
HS		 4110 /* enable interrupts if needed: hw bug w/a */
4111 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4112 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4113 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4114 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4115 }
4116
4117 iwl_enable_interrupts(priv);
4118
6cd0b1cb
HS		 4119 /* If platform's RF_KILL switch is NOT set to KILL */
4120 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4121 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4122 else
4123 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4124
a60e77e5
JB		 4125 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4126 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4127
58d0f361 4128 iwl_power_initialize(priv);
39b73fb1 4129 iwl_tt_initialize(priv);
158bea07 4130
a15707d8 4131 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4132
b08dfd04 4133 err = iwl_request_firmware(priv, true);
158bea07 4134 if (err)
7d47618a 4135 goto out_destroy_workqueue;
158bea07 4136
b481de9c
ZY		 4137 return 0;
4138
7d47618a 4139 out_destroy_workqueue:
c8f16138
RC		 4140 destroy_workqueue(priv->workqueue);
4141 priv->workqueue = NULL;
795cc0ad 4142 free_irq(priv->pci_dev->irq, priv);
ef850d7c 4143 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 4144 out_disable_msi:
4145 pci_disable_msi(priv->pci_dev);
6ba87956 4146 iwl_uninit_drv(priv);
073d3f5f
TW		 4147 out_free_eeprom:
4148 iwl_eeprom_free(priv);
b481de9c
ZY		 4149 out_iounmap:
4150 pci_iounmap(pdev, priv->hw_base);
4151 out_pci_release_regions:
316c30d9 4152 pci_set_drvdata(pdev, NULL);
623d563e 4153 pci_release_regions(pdev);
b481de9c
ZY		 4154 out_pci_disable_device:
4155 pci_disable_device(pdev);
b481de9c 4156 out_ieee80211_free_hw:
20594eb0 4157 iwl_free_traffic_mem(priv);
d7c76f4c 4158 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4159 out:
4160 return err;
4161}
4162
5b9f8cd3 4163static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4164{
c79dd5b5 4165 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4166 unsigned long flags;
b481de9c
ZY		 4167
4168 if (!priv)
4169 return;
4170
a15707d8 4171 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4172
e1623446 4173 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4174
67249625 4175 iwl_dbgfs_unregister(priv);
5b9f8cd3 4176 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4177
5b9f8cd3
EG		 4178 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4179 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4180 * we need to set STATUS_EXIT_PENDING bit.
4181 */
4182 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4183 if (priv->mac80211_registered) {
4184 ieee80211_unregister_hw(priv->hw);
4185 priv->mac80211_registered = 0;
0b124c31 4186 } else {
5b9f8cd3 4187 iwl_down(priv);
c4f55232
RR		 4188 }
4189
c166b25a
BC		 4190 /*
4191 * Make sure device is reset to low power before unloading driver.
4192 * This may be redundant with iwl_down(), but there are paths to
4193 * run iwl_down() without calling apm_ops.stop(), and there are
4194 * paths to avoid running iwl_down() at all before leaving driver.
4195 * This (inexpensive) call *makes sure* device is reset.
4196 */
4197 priv->cfg->ops->lib->apm_ops.stop(priv);
4198
39b73fb1
WYG		 4199 iwl_tt_exit(priv);
4200
0359facc
MA		 4201 /* make sure we flush any pending irq or
4202 * tasklet for the driver
4203 */
4204 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4205 iwl_disable_interrupts(priv);
0359facc
MA		 4206 spin_unlock_irqrestore(&priv->lock, flags);
4207
4208 iwl_synchronize_irq(priv);
4209
5b9f8cd3 4210 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4211
4212 if (priv->rxq.bd)
54b81550 4213 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4214 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4215
073d3f5f 4216 iwl_eeprom_free(priv);
b481de9c 4217
b481de9c 4218
948c171c
MA		 4219 /*netif_stop_queue(dev); */
4220 flush_workqueue(priv->workqueue);
4221
5b9f8cd3 4222 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4223 * priv->workqueue... so we can't take down the workqueue
4224 * until now... */
4225 destroy_workqueue(priv->workqueue);
4226 priv->workqueue = NULL;
20594eb0 4227 iwl_free_traffic_mem(priv);
b481de9c 4228
6cd0b1cb
HS		 4229 free_irq(priv->pci_dev->irq, priv);
4230 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4231 pci_iounmap(pdev, priv->hw_base);
4232 pci_release_regions(pdev);
4233 pci_disable_device(pdev);
4234 pci_set_drvdata(pdev, NULL);
4235
6ba87956 4236 iwl_uninit_drv(priv);
b481de9c 4237
ef850d7c
MA		 4238 iwl_free_isr_ict(priv);
4239
b481de9c
ZY		 4240 if (priv->ibss_beacon)
4241 dev_kfree_skb(priv->ibss_beacon);
4242
4243 ieee80211_free_hw(priv->hw);
4244}
4245
b481de9c
ZY		 4246
4247/*****************************************************************************
4248 *
4249 * driver and module entry point
4250 *
4251 *****************************************************************************/
4252
fed9017e 4253/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4254static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4255#ifdef CONFIG_IWL4965
fed9017e
RR		 4256 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4257 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4258#endif /* CONFIG_IWL4965 */
5a6a256e 4259#ifdef CONFIG_IWL5000
ac592574
WYG		 4260/* 5100 Series WiFi */
4261 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4262 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4263 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4264 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4265 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4266 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4267 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4268 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4269 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4270 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4271 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4272 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4273 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4274 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4275 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4276 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4277 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4278 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4279 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4280 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4281 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4282 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4283 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4284 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4285
4286/* 5300 Series WiFi */
4287 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4288 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4289 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4290 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4291 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4292 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4293 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4294 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4295 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4296 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4297 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4298 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4299
4300/* 5350 Series WiFi/WiMax */
4301 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4302 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4303 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4304
4305/* 5150 Series Wifi/WiMax */
4306 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4307 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4308 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4309 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4310 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4311 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4312
4313 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4314 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4315 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4316 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4317
4318/* 6x00 Series */
5953a62e
WYG		 4319 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4320 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4321 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4322 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4323 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4324 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4325 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4326 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4327 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4328 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4329
95b13014
SZ		 4330/* 6x00 Series Gen2a */
4331 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4332 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4333 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
1808972f
SZ		 4334 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4335 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4336 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4337 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
9f6e1baf
SZ		 4338 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4339 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4340 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4341 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4342 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4343 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4344 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4345
4346/* 6x00 Series Gen2b */
4347 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4348 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4349 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4350 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4351 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4352 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4353 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4354 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4355 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4356 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4357 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
9f6e1baf
SZ		 4358 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4359 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4360 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4361 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4362 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4363 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4364 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4365 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4366 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4367 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4368 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4369 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4370 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4371 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4372 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4373 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4374 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4375
4376/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4377 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4378 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4379 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4380 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4381 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4382 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4383
03264339
SZ		 4384/* 6x50 WiFi/WiMax Series Gen2 */
4385 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4386 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4387 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4388 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4389 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4390 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4391
77dcb6a9 4392/* 1000 Series WiFi */
4bd0914f
WYG		 4393 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4394 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4395 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4396 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4397 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4398 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4399 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4400 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4401 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4402 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4403 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4404 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 4405#endif /* CONFIG_IWL5000 */
7100e924 4406
fed9017e
RR		 4407 {0}
4408};
4409MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4410
4411static struct pci_driver iwl_driver = {
b481de9c 4412 .name = DRV_NAME,
fed9017e 4413 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4414 .probe = iwl_pci_probe,
4415 .remove = __devexit_p(iwl_pci_remove),
b481de9c 4416#ifdef CONFIG_PM
5b9f8cd3
EG		 4417 .suspend = iwl_pci_suspend,
4418 .resume = iwl_pci_resume,
b481de9c
ZY		 4419#endif
4420};
4421
5b9f8cd3 4422static int __init iwl_init(void)
b481de9c
ZY		 4423{
4424
4425 int ret;
c96c31e4
JP		 4426 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4427 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4428
e227ceac 4429 ret = iwlagn_rate_control_register();
897e1cf2 4430 if (ret) {
c96c31e4 4431 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4432 return ret;
4433 }
4434
fed9017e 4435 ret = pci_register_driver(&iwl_driver);
b481de9c 4436 if (ret) {
c96c31e4 4437 pr_err("Unable to initialize PCI module\n");
897e1cf2 4438 goto error_register;
b481de9c 4439 }
b481de9c
ZY		 4440
4441 return ret;
897e1cf2 4442
897e1cf2 4443error_register:
e227ceac 4444 iwlagn_rate_control_unregister();
897e1cf2 4445 return ret;
b481de9c
ZY		 4446}
4447
5b9f8cd3 4448static void __exit iwl_exit(void)
b481de9c 4449{
fed9017e 4450 pci_unregister_driver(&iwl_driver);
e227ceac 4451 iwlagn_rate_control_unregister();
b481de9c
ZY		 4452}
4453
5b9f8cd3
EG		 4454module_exit(iwl_exit);
4455module_init(iwl_init);
a562a9dd
RC		 4456
4457#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4458module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4459MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4460module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4461MODULE_PARM_DESC(debug, "debug output mask");
4462#endif
4463
2b068618
WYG		 4464module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4465MODULE_PARM_DESC(swcrypto50,
4466 "using crypto in software (default 0 [hardware]) (deprecated)");
4467module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4468MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4469module_param_named(queues_num50,
4470 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4471MODULE_PARM_DESC(queues_num50,
4472 "number of hw queues in 50xx series (deprecated)");
4473module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4474MODULE_PARM_DESC(queues_num, "number of hw queues.");
4475module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4476MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4477module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4478MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4479module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4480 int, S_IRUGO);
4481MODULE_PARM_DESC(amsdu_size_8K50,
4482 "enable 8K amsdu size in 50XX series (deprecated)");
4483module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4484 int, S_IRUGO);
4485MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4486module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4487MODULE_PARM_DESC(fw_restart50,
4488 "restart firmware in case of error (deprecated)");
4489module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4490MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4491module_param_named(
4492 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4493MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
dd7a2509
JB		 4494
4495module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4496 S_IRUGO);
4497MODULE_PARM_DESC(ucode_alternative,
4498 "specify ucode alternative to use from ucode file");
Linux kernel - Deliverables
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