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iwlagn: use SKU information in the EEPROM
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY		 34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY		 38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY		 41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY		 45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY		 48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO		 52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
0de76736 60#include "iwl-agn-calib.h"
a1175124 61#include "iwl-agn.h"
b481de9c 62
416e1438 63
b481de9c
ZY		 64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
b481de9c
ZY		 70/*
71 * module name, copyright, version, etc.
b481de9c 72 */
d783b061 73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 74
0a6857e7 75#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 76#define VD "d"
77#else
78#define VD
79#endif
80
81963d68 81#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 82
b481de9c
ZY		 83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
bee008b7 90static int iwlagn_ant_coupling;
f37837c9 91static bool iwlagn_bt_ch_announce = 1;
bee008b7 92
5b9f8cd3 93void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f 94{
246ed355 95 struct iwl_rxon_context *ctx;
5da4b55f 96
246ed355
JB		 97 if (priv->cfg->ops->hcmd->set_rxon_chain) {
98 for_each_context(priv, ctx) {
99 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
100 iwlcore_commit_rxon(priv, ctx);
101 }
102 }
5da4b55f
MA		 103}
104
fcab423d 105static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 106{
107 struct list_head *element;
108
e1623446 109 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 110 priv->frames_count);
111
112 while (!list_empty(&priv->free_frames)) {
113 element = priv->free_frames.next;
114 list_del(element);
fcab423d 115 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 116 priv->frames_count--;
117 }
118
119 if (priv->frames_count) {
39aadf8c 120 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 121 priv->frames_count);
122 priv->frames_count = 0;
123 }
124}
125
fcab423d 126static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 127{
fcab423d 128 struct iwl_frame *frame;
b481de9c
ZY		 129 struct list_head *element;
130 if (list_empty(&priv->free_frames)) {
131 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
132 if (!frame) {
15b1687c 133 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 134 return NULL;
135 }
136
137 priv->frames_count++;
138 return frame;
139 }
140
141 element = priv->free_frames.next;
142 list_del(element);
fcab423d 143 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 144}
145
fcab423d 146static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 147{
148 memset(frame, 0, sizeof(*frame));
149 list_add(&frame->list, &priv->free_frames);
150}
151
47ff65c4 152static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
77834543
JB		 153 struct ieee80211_hdr *hdr,
154 int left)
b481de9c 155{
77834543
JB		 156 lockdep_assert_held(&priv->mutex);
157
12e934dc 158 if (!priv->beacon_skb)
b481de9c
ZY		 159 return 0;
160
12e934dc 161 if (priv->beacon_skb->len > left)
b481de9c
ZY		 162 return 0;
163
12e934dc 164 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
b481de9c 165
12e934dc 166 return priv->beacon_skb->len;
b481de9c
ZY		 167}
168
47ff65c4
DH		 169/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
170static void iwl_set_beacon_tim(struct iwl_priv *priv,
77834543
JB		 171 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
172 u8 *beacon, u32 frame_size)
47ff65c4
DH		 173{
174 u16 tim_idx;
175 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
176
177 /*
178 * The index is relative to frame start but we start looking at the
179 * variable-length part of the beacon.
180 */
181 tim_idx = mgmt->u.beacon.variable - beacon;
182
183 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
184 while ((tim_idx < (frame_size - 2)) &&
185 (beacon[tim_idx] != WLAN_EID_TIM))
186 tim_idx += beacon[tim_idx+1] + 2;
187
188 /* If TIM field was found, set variables */
189 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
190 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
191 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
192 } else
193 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
194}
195
5b9f8cd3 196static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 197 struct iwl_frame *frame)
4bf64efd
TW		 198{
199 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 200 u32 frame_size;
201 u32 rate_flags;
202 u32 rate;
203 /*
204 * We have to set up the TX command, the TX Beacon command, and the
205 * beacon contents.
206 */
4bf64efd 207
76d04815
JB		 208 lockdep_assert_held(&priv->mutex);
209
210 if (!priv->beacon_ctx) {
211 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
950094cb 212 return 0;
76d04815
JB		 213 }
214
47ff65c4 215 /* Initialize memory */
4bf64efd
TW		 216 tx_beacon_cmd = &frame->u.beacon;
217 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
218
47ff65c4 219 /* Set up TX beacon contents */
4bf64efd 220 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 221 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 222 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
223 return 0;
40bbfd4c
JB		 224 if (!frame_size)
225 return 0;
4bf64efd 226
47ff65c4 227 /* Set up TX command fields */
4bf64efd 228 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
76d04815 229 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
47ff65c4
DH		 230 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
231 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
232 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 233
47ff65c4
DH		 234 /* Set up TX beacon command fields */
235 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
77834543 236 frame_size);
4bf64efd 237
47ff65c4 238 /* Set up packet rate and flags */
76d04815 239 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
0e1654fa
JB		 240 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
241 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 242 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
243 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
244 rate_flags |= RATE_MCS_CCK_MSK;
245 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
246 rate_flags);
4bf64efd
TW		 247
248 return sizeof(*tx_beacon_cmd) + frame_size;
249}
2295c66b
JB		 250
251int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 252{
fcab423d 253 struct iwl_frame *frame;
b481de9c
ZY		 254 unsigned int frame_size;
255 int rc;
b481de9c 256
fcab423d 257 frame = iwl_get_free_frame(priv);
b481de9c 258 if (!frame) {
15b1687c 259 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 260 "command.\n");
261 return -ENOMEM;
262 }
263
47ff65c4
DH		 264 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
265 if (!frame_size) {
266 IWL_ERR(priv, "Error configuring the beacon command\n");
267 iwl_free_frame(priv, frame);
268 return -EINVAL;
269 }
b481de9c 270
857485c0 271 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 272 &frame->u.cmd[0]);
273
fcab423d 274 iwl_free_frame(priv, frame);
b481de9c
ZY		 275
276 return rc;
277}
278
7aaa1d79
SO		 279static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
280{
281 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
282
283 dma_addr_t addr = get_unaligned_le32(&tb->lo);
284 if (sizeof(dma_addr_t) > sizeof(u32))
285 addr |=
286 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
287
288 return addr;
289}
290
291static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
292{
293 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
294
295 return le16_to_cpu(tb->hi_n_len) >> 4;
296}
297
298static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
299 dma_addr_t addr, u16 len)
300{
301 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
302 u16 hi_n_len = len << 4;
303
304 put_unaligned_le32(addr, &tb->lo);
305 if (sizeof(dma_addr_t) > sizeof(u32))
306 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
307
308 tb->hi_n_len = cpu_to_le16(hi_n_len);
309
310 tfd->num_tbs = idx + 1;
311}
312
313static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
314{
315 return tfd->num_tbs & 0x1f;
316}
317
318/**
319 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
320 * @priv - driver private data
321 * @txq - tx queue
322 *
323 * Does NOT advance any TFD circular buffer read/write indexes
324 * Does NOT free the TFD itself (which is within circular buffer)
325 */
326void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
327{
59606ffa 328 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 329 struct iwl_tfd *tfd;
330 struct pci_dev *dev = priv->pci_dev;
331 int index = txq->q.read_ptr;
332 int i;
333 int num_tbs;
334
335 tfd = &tfd_tmp[index];
336
337 /* Sanity check on number of chunks */
338 num_tbs = iwl_tfd_get_num_tbs(tfd);
339
340 if (num_tbs >= IWL_NUM_OF_TBS) {
341 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
342 /* @todo issue fatal error, it is quite serious situation */
343 return;
344 }
345
346 /* Unmap tx_cmd */
347 if (num_tbs)
348 pci_unmap_single(dev,
2e724443
FT		 349 dma_unmap_addr(&txq->meta[index], mapping),
350 dma_unmap_len(&txq->meta[index], len),
96891cee 351 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 352
353 /* Unmap chunks, if any. */
ff0d91c3 354 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 355 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
356 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
357
ff0d91c3
JB		 358 /* free SKB */
359 if (txq->txb) {
360 struct sk_buff *skb;
6f80240e 361
ff0d91c3 362 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 363
ff0d91c3
JB		 364 /* can be called from irqs-disabled context */
365 if (skb) {
366 dev_kfree_skb_any(skb);
367 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 368 }
369 }
370}
371
372int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
373 struct iwl_tx_queue *txq,
374 dma_addr_t addr, u16 len,
375 u8 reset, u8 pad)
376{
377 struct iwl_queue *q;
59606ffa 378 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 379 u32 num_tbs;
380
381 q = &txq->q;
59606ffa
SO		 382 tfd_tmp = (struct iwl_tfd *)txq->tfds;
383 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 384
385 if (reset)
386 memset(tfd, 0, sizeof(*tfd));
387
388 num_tbs = iwl_tfd_get_num_tbs(tfd);
389
390 /* Each TFD can point to a maximum 20 Tx buffers */
391 if (num_tbs >= IWL_NUM_OF_TBS) {
392 IWL_ERR(priv, "Error can not send more than %d chunks\n",
393 IWL_NUM_OF_TBS);
394 return -EINVAL;
395 }
396
397 BUG_ON(addr & ~DMA_BIT_MASK(36));
398 if (unlikely(addr & ~IWL_TX_DMA_MASK))
399 IWL_ERR(priv, "Unaligned address = %llx\n",
400 (unsigned long long)addr);
401
402 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
403
404 return 0;
405}
406
a8e74e27
SO		 407/*
408 * Tell nic where to find circular buffer of Tx Frame Descriptors for
409 * given Tx queue, and enable the DMA channel used for that queue.
410 *
411 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
412 * channels supported in hardware.
413 */
414int iwl_hw_tx_queue_init(struct iwl_priv *priv,
415 struct iwl_tx_queue *txq)
416{
a8e74e27
SO		 417 int txq_id = txq->q.id;
418
a8e74e27
SO		 419 /* Circular buffer (TFD queue in DRAM) physical base address */
420 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
421 txq->q.dma_addr >> 8);
422
a8e74e27
SO		 423 return 0;
424}
425
b481de9c
ZY		 426/******************************************************************************
427 *
428 * Generic RX handler implementations
429 *
430 ******************************************************************************/
885ba202
TW		 431static void iwl_rx_reply_alive(struct iwl_priv *priv,
432 struct iwl_rx_mem_buffer *rxb)
b481de9c 433{
2f301227 434 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 435 struct iwl_alive_resp *palive;
b481de9c
ZY		 436 struct delayed_work *pwork;
437
438 palive = &pkt->u.alive_frame;
439
e1623446 440 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 441 "0x%01X 0x%01X\n",
442 palive->is_valid, palive->ver_type,
443 palive->ver_subtype);
444
445 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 446 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 447 memcpy(&priv->card_alive_init,
448 &pkt->u.alive_frame,
885ba202 449 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 450 pwork = &priv->init_alive_start;
451 } else {
e1623446 452 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 453 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 454 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 455 pwork = &priv->alive_start;
456 }
457
458 /* We delay the ALIVE response by 5ms to
459 * give the HW RF Kill time to activate... */
460 if (palive->is_valid == UCODE_VALID_OK)
461 queue_delayed_work(priv->workqueue, pwork,
462 msecs_to_jiffies(5));
463 else
39aadf8c 464 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 465}
466
5b9f8cd3 467static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 468{
c79dd5b5
TW		 469 struct iwl_priv *priv =
470 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 471 struct sk_buff *beacon;
472
76d04815
JB		 473 mutex_lock(&priv->mutex);
474 if (!priv->beacon_ctx) {
475 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
476 goto out;
477 }
b481de9c 478
60744f62
JB		 479 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
480 /*
481 * The ucode will send beacon notifications even in
482 * IBSS mode, but we don't want to process them. But
483 * we need to defer the type check to here due to
484 * requiring locking around the beacon_ctx access.
485 */
486 goto out;
487 }
488
76d04815
JB		 489 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
490 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
b481de9c 491 if (!beacon) {
77834543 492 IWL_ERR(priv, "update beacon failed -- keeping old\n");
76d04815 493 goto out;
b481de9c
ZY		 494 }
495
b481de9c 496 /* new beacon skb is allocated every time; dispose previous.*/
77834543 497 dev_kfree_skb(priv->beacon_skb);
b481de9c 498
12e934dc 499 priv->beacon_skb = beacon;
b481de9c 500
2295c66b 501 iwlagn_send_beacon_cmd(priv);
76d04815
JB		 502 out:
503 mutex_unlock(&priv->mutex);
b481de9c
ZY		 504}
505
fbba9410
WYG		 506static void iwl_bg_bt_runtime_config(struct work_struct *work)
507{
508 struct iwl_priv *priv =
509 container_of(work, struct iwl_priv, bt_runtime_config);
510
511 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
512 return;
513
514 /* dont send host command if rf-kill is on */
515 if (!iwl_is_ready_rf(priv))
516 return;
517 priv->cfg->ops->hcmd->send_bt_config(priv);
518}
519
bee008b7
WYG		 520static void iwl_bg_bt_full_concurrency(struct work_struct *work)
521{
522 struct iwl_priv *priv =
523 container_of(work, struct iwl_priv, bt_full_concurrency);
246ed355 524 struct iwl_rxon_context *ctx;
bee008b7
WYG		 525
526 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
527 return;
528
529 /* dont send host command if rf-kill is on */
530 if (!iwl_is_ready_rf(priv))
531 return;
532
533 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
534 priv->bt_full_concurrent ?
535 "full concurrency" : "3-wire");
536
537 /*
538 * LQ & RXON updated cmds must be sent before BT Config cmd
539 * to avoid 3-wire collisions
540 */
246ed355
JB		 541 mutex_lock(&priv->mutex);
542 for_each_context(priv, ctx) {
543 if (priv->cfg->ops->hcmd->set_rxon_chain)
544 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
545 iwlcore_commit_rxon(priv, ctx);
546 }
547 mutex_unlock(&priv->mutex);
bee008b7
WYG		 548
549 priv->cfg->ops->hcmd->send_bt_config(priv);
550}
551
4e39317d 552/**
5b9f8cd3 553 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 554 *
555 * This callback is provided in order to send a statistics request.
556 *
557 * This timer function is continually reset to execute within
558 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
559 * was received. We need to ensure we receive the statistics in order
560 * to update the temperature used for calibrating the TXPOWER.
561 */
5b9f8cd3 562static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 563{
564 struct iwl_priv *priv = (struct iwl_priv *)data;
565
566 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
567 return;
568
61780ee3
MA		 569 /* dont send host command if rf-kill is on */
570 if (!iwl_is_ready_rf(priv))
571 return;
572
ef8d5529 573 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 574}
575
a9e1cb6a
WYG		 576
577static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
578 u32 start_idx, u32 num_events,
579 u32 mode)
580{
581 u32 i;
582 u32 ptr; /* SRAM byte address of log data */
583 u32 ev, time, data; /* event log data */
584 unsigned long reg_flags;
585
586 if (mode == 0)
587 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
588 else
589 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
590
591 /* Make sure device is powered up for SRAM reads */
592 spin_lock_irqsave(&priv->reg_lock, reg_flags);
593 if (iwl_grab_nic_access(priv)) {
594 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
595 return;
596 }
597
598 /* Set starting address; reads will auto-increment */
599 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
600 rmb();
601
602 /*
603 * "time" is actually "data" for mode 0 (no timestamp).
604 * place event id # at far right for easier visual parsing.
605 */
606 for (i = 0; i < num_events; i++) {
607 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
608 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
609 if (mode == 0) {
610 trace_iwlwifi_dev_ucode_cont_event(priv,
611 0, time, ev);
612 } else {
613 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
614 trace_iwlwifi_dev_ucode_cont_event(priv,
615 time, data, ev);
616 }
617 }
618 /* Allow device to power down */
619 iwl_release_nic_access(priv);
620 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
621}
622
875295f1 623static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 624{
625 u32 capacity; /* event log capacity in # entries */
626 u32 base; /* SRAM byte address of event log header */
627 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
628 u32 num_wraps; /* # times uCode wrapped to top of log */
629 u32 next_entry; /* index of next entry to be written by uCode */
630
631 if (priv->ucode_type == UCODE_INIT)
632 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
633 else
634 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
635 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
636 capacity = iwl_read_targ_mem(priv, base);
637 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
638 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
639 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
640 } else
641 return;
642
643 if (num_wraps == priv->event_log.num_wraps) {
644 iwl_print_cont_event_trace(priv,
645 base, priv->event_log.next_entry,
646 next_entry - priv->event_log.next_entry,
647 mode);
648 priv->event_log.non_wraps_count++;
649 } else {
650 if ((num_wraps - priv->event_log.num_wraps) > 1)
651 priv->event_log.wraps_more_count++;
652 else
653 priv->event_log.wraps_once_count++;
654 trace_iwlwifi_dev_ucode_wrap_event(priv,
655 num_wraps - priv->event_log.num_wraps,
656 next_entry, priv->event_log.next_entry);
657 if (next_entry < priv->event_log.next_entry) {
658 iwl_print_cont_event_trace(priv, base,
659 priv->event_log.next_entry,
660 capacity - priv->event_log.next_entry,
661 mode);
662
663 iwl_print_cont_event_trace(priv, base, 0,
664 next_entry, mode);
665 } else {
666 iwl_print_cont_event_trace(priv, base,
667 next_entry, capacity - next_entry,
668 mode);
669
670 iwl_print_cont_event_trace(priv, base, 0,
671 next_entry, mode);
672 }
673 }
674 priv->event_log.num_wraps = num_wraps;
675 priv->event_log.next_entry = next_entry;
676}
677
678/**
679 * iwl_bg_ucode_trace - Timer callback to log ucode event
680 *
681 * The timer is continually set to execute every
682 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
683 * this function is to perform continuous uCode event logging operation
684 * if enabled
685 */
686static void iwl_bg_ucode_trace(unsigned long data)
687{
688 struct iwl_priv *priv = (struct iwl_priv *)data;
689
690 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
691 return;
692
693 if (priv->event_log.ucode_trace) {
694 iwl_continuous_event_trace(priv);
695 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
696 mod_timer(&priv->ucode_trace,
697 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
698 }
699}
700
5b9f8cd3 701static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 702 struct iwl_rx_mem_buffer *rxb)
b481de9c 703{
2f301227 704 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 705 struct iwl4965_beacon_notif *beacon =
706 (struct iwl4965_beacon_notif *)pkt->u.raw;
a85d7cca 707#ifdef CONFIG_IWLWIFI_DEBUG
e7d326ac 708 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 709
e1623446 710 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 711 "tsf %d %d rate %d\n",
25a6572c 712 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 713 beacon->beacon_notify_hdr.failure_frame,
714 le32_to_cpu(beacon->ibss_mgr_status),
715 le32_to_cpu(beacon->high_tsf),
716 le32_to_cpu(beacon->low_tsf), rate);
717#endif
718
a85d7cca
JB		 719 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
720
60744f62 721 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 722 queue_work(priv->workqueue, &priv->beacon_update);
723}
724
b481de9c
ZY		 725/* Handle notification from uCode that card's power state is changing
726 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 727static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 728 struct iwl_rx_mem_buffer *rxb)
b481de9c 729{
2f301227 730 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 731 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
732 unsigned long status = priv->status;
733
3a41bbd5 734 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 735 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 736 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
737 (flags & CT_CARD_DISABLED) ?
738 "Reached" : "Not reached");
b481de9c
ZY		 739
740 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 741 CT_CARD_DISABLED)) {
b481de9c 742
3395f6e9 743 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 744 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
745
a8b50a0a
MA		 746 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
747 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 748
749 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 750 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 751 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 752 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 753 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 754 }
3a41bbd5 755 if (flags & CT_CARD_DISABLED)
39b73fb1 756 iwl_tt_enter_ct_kill(priv);
b481de9c 757 }
3a41bbd5 758 if (!(flags & CT_CARD_DISABLED))
39b73fb1 759 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 760
761 if (flags & HW_CARD_DISABLED)
762 set_bit(STATUS_RF_KILL_HW, &priv->status);
763 else
764 clear_bit(STATUS_RF_KILL_HW, &priv->status);
765
766
b481de9c 767 if (!(flags & RXON_CARD_DISABLED))
2a421b91 768 iwl_scan_cancel(priv);
b481de9c
ZY		 769
770 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 771 test_bit(STATUS_RF_KILL_HW, &priv->status)))
772 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
773 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 774 else
775 wake_up_interruptible(&priv->wait_command_queue);
776}
777
65550636
WYG		 778static void iwl_bg_tx_flush(struct work_struct *work)
779{
780 struct iwl_priv *priv =
781 container_of(work, struct iwl_priv, tx_flush);
782
783 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
784 return;
785
786 /* do nothing if rf-kill is on */
787 if (!iwl_is_ready_rf(priv))
788 return;
789
790 if (priv->cfg->ops->lib->txfifo_flush) {
791 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
792 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
793 }
794}
795
b481de9c 796/**
5b9f8cd3 797 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 798 *
799 * Setup the RX handlers for each of the reply types sent from the uCode
800 * to the host.
801 *
802 * This function chains into the hardware specific files for them to setup
803 * any hardware specific handlers as well.
804 */
653fa4a0 805static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 806{
885ba202 807 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 808 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
809 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 810 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
811 iwl_rx_spectrum_measure_notif;
5b9f8cd3 812 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 813 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 814 iwl_rx_pm_debug_statistics_notif;
815 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 816
9fbab516
BC		 817 /*
818 * The same handler is used for both the REPLY to a discrete
819 * statistics request from the host as well as for the periodic
820 * statistics notifications (after received beacons) from the uCode.
b481de9c 821 */
ef8d5529 822 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 823 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 824
825 iwl_setup_rx_scan_handlers(priv);
826
37a44211 827 /* status change handler */
5b9f8cd3 828 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 829
c1354754
TW		 830 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
831 iwl_rx_missed_beacon_notif;
37a44211 832 /* Rx handlers */
8d801080
WYG		 833 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
834 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 835 /* block ack */
74bcdb33 836 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 837 /* Set up hardware specific Rx handlers */
d4789efe 838 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 839}
840
b481de9c 841/**
a55360e4 842 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 843 *
844 * Uses the priv->rx_handlers callback function array to invoke
845 * the appropriate handlers, including command responses,
846 * frame-received notifications, and other notifications.
847 */
a55360e4 848void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 849{
a55360e4 850 struct iwl_rx_mem_buffer *rxb;
db11d634 851 struct iwl_rx_packet *pkt;
a55360e4 852 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 853 u32 r, i;
854 int reclaim;
855 unsigned long flags;
5c0eef96 856 u8 fill_rx = 0;
d68ab680 857 u32 count = 8;
4752c93c 858 int total_empty;
b481de9c 859
6440adb5
CB		 860 /* uCode's read index (stored in shared DRAM) indicates the last Rx
861 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 862 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 863 i = rxq->read;
864
865 /* Rx interrupt, but nothing sent from uCode */
866 if (i == r)
e1623446 867 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 868
4752c93c 869 /* calculate total frames need to be restock after handling RX */
7300515d 870 total_empty = r - rxq->write_actual;
4752c93c
MA		 871 if (total_empty < 0)
872 total_empty += RX_QUEUE_SIZE;
873
874 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 875 fill_rx = 1;
876
b481de9c 877 while (i != r) {
f4989d9b
JB		 878 int len;
879
b481de9c
ZY		 880 rxb = rxq->queue[i];
881
9fbab516 882 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 883 * then a bug has been introduced in the queue refilling
884 * routines -- catch it here */
885 BUG_ON(rxb == NULL);
886
887 rxq->queue[i] = NULL;
888
2f301227
ZY		 889 pci_unmap_page(priv->pci_dev, rxb->page_dma,
890 PAGE_SIZE << priv->hw_params.rx_page_order,
891 PCI_DMA_FROMDEVICE);
892 pkt = rxb_addr(rxb);
b481de9c 893
f4989d9b
JB		 894 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
895 len += sizeof(u32); /* account for status word */
896 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 897
b481de9c
ZY		 898 /* Reclaim a command buffer only if this packet is a response
899 * to a (driver-originated) command.
900 * If the packet (e.g. Rx frame) originated from uCode,
901 * there is no command buffer to reclaim.
902 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
903 * but apparently a few don't get set; catch them here. */
904 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
905 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 906 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 907 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 908 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 909 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
910 (pkt->hdr.cmd != REPLY_TX);
911
912 /* Based on type of command response or notification,
913 * handle those that need handling via function in
5b9f8cd3 914 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 915 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 916 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 917 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 918 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 919 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 920 } else {
921 /* No handling needed */
e1623446 922 IWL_DEBUG_RX(priv,
b481de9c
ZY		 923 "r %d i %d No handler needed for %s, 0x%02x\n",
924 r, i, get_cmd_string(pkt->hdr.cmd),
925 pkt->hdr.cmd);
926 }
927
29b1b268
ZY		 928 /*
929 * XXX: After here, we should always check rxb->page
930 * against NULL before touching it or its virtual
931 * memory (pkt). Because some rx_handler might have
932 * already taken or freed the pages.
933 */
934
b481de9c 935 if (reclaim) {
2f301227
ZY		 936 /* Invoke any callbacks, transfer the buffer to caller,
937 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 938 * as we reclaim the driver command queue */
29b1b268 939 if (rxb->page)
17b88929 940 iwl_tx_cmd_complete(priv, rxb);
b481de9c 941 else
39aadf8c 942 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 943 }
944
7300515d
ZY		 945 /* Reuse the page if possible. For notification packets and
946 * SKBs that fail to Rx correctly, add them back into the
947 * rx_free list for reuse later. */
948 spin_lock_irqsave(&rxq->lock, flags);
2f301227 949 if (rxb->page != NULL) {
7300515d
ZY		 950 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
951 0, PAGE_SIZE << priv->hw_params.rx_page_order,
952 PCI_DMA_FROMDEVICE);
953 list_add_tail(&rxb->list, &rxq->rx_free);
954 rxq->free_count++;
955 } else
956 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 957
b481de9c 958 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 959
b481de9c 960 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 961 /* If there are a lot of unused frames,
962 * restock the Rx queue so ucode wont assert. */
963 if (fill_rx) {
964 count++;
965 if (count >= 8) {
7300515d 966 rxq->read = i;
54b81550 967 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 968 count = 0;
969 }
970 }
b481de9c
ZY		 971 }
972
973 /* Backtrack one entry */
7300515d 974 rxq->read = i;
4752c93c 975 if (fill_rx)
54b81550 976 iwlagn_rx_replenish_now(priv);
4752c93c 977 else
54b81550 978 iwlagn_rx_queue_restock(priv);
a55360e4 979}
a55360e4 980
0359facc
MA		 981/* call this function to flush any scheduled tasklet */
982static inline void iwl_synchronize_irq(struct iwl_priv *priv)
983{
a96a27f9 984 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 985 synchronize_irq(priv->pci_dev->irq);
986 tasklet_kill(&priv->irq_tasklet);
987}
988
ef850d7c 989static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 990{
991 u32 inta, handled = 0;
992 u32 inta_fh;
993 unsigned long flags;
c2e61da2 994 u32 i;
0a6857e7 995#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 996 u32 inta_mask;
997#endif
998
999 spin_lock_irqsave(&priv->lock, flags);
1000
1001 /* Ack/clear/reset pending uCode interrupts.
1002 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1003 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1004 inta = iwl_read32(priv, CSR_INT);
1005 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1006
1007 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1008 * Any new interrupts that happen after this, either while we're
1009 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1010 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1011 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1012
0a6857e7 1013#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1014 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1015 /* just for debug */
3395f6e9 1016 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1017 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1018 inta, inta_mask, inta_fh);
1019 }
1020#endif
1021
2f301227
ZY		 1022 spin_unlock_irqrestore(&priv->lock, flags);
1023
b481de9c
ZY		 1024 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1025 * atomic, make sure that inta covers all the interrupts that
1026 * we've discovered, even if FH interrupt came in just after
1027 * reading CSR_INT. */
6f83eaa1 1028 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1029 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1030 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1031 inta |= CSR_INT_BIT_FH_TX;
1032
1033 /* Now service all interrupt bits discovered above. */
1034 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1035 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1036
1037 /* Tell the device to stop sending interrupts */
5b9f8cd3 1038 iwl_disable_interrupts(priv);
b481de9c 1039
a83b9141 1040 priv->isr_stats.hw++;
5b9f8cd3 1041 iwl_irq_handle_error(priv);
b481de9c
ZY		 1042
1043 handled |= CSR_INT_BIT_HW_ERR;
1044
b481de9c
ZY		 1045 return;
1046 }
1047
0a6857e7 1048#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1049 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1050 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1051 if (inta & CSR_INT_BIT_SCD) {
e1623446 1052 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1053 "the frame/frames.\n");
a83b9141
WYG		 1054 priv->isr_stats.sch++;
1055 }
b481de9c
ZY		 1056
1057 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1058 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1059 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1060 priv->isr_stats.alive++;
1061 }
b481de9c
ZY		 1062 }
1063#endif
1064 /* Safely ignore these bits for debug checks below */
25c03d8e 1065 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1066
9fbab516 1067 /* HW RF KILL switch toggled */
b481de9c
ZY		 1068 if (inta & CSR_INT_BIT_RF_KILL) {
1069 int hw_rf_kill = 0;
3395f6e9 1070 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1071 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1072 hw_rf_kill = 1;
1073
4c423a2b 1074 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1075 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1076
a83b9141
WYG		 1077 priv->isr_stats.rfkill++;
1078
a9efa652 1079 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1080 * the driver allows loading the ucode even if the radio
1081 * is killed. Hence update the killswitch state here. The
1082 * rfkill handler will care about restarting if needed.
a9efa652 1083 */
6cd0b1cb
HS		 1084 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1085 if (hw_rf_kill)
1086 set_bit(STATUS_RF_KILL_HW, &priv->status);
1087 else
1088 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1089 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1090 }
b481de9c
ZY		 1091
1092 handled |= CSR_INT_BIT_RF_KILL;
1093 }
1094
9fbab516 1095 /* Chip got too hot and stopped itself */
b481de9c 1096 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1097 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1098 priv->isr_stats.ctkill++;
b481de9c
ZY		 1099 handled |= CSR_INT_BIT_CT_KILL;
1100 }
1101
1102 /* Error detected by uCode */
1103 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1104 IWL_ERR(priv, "Microcode SW error detected. "
1105 " Restarting 0x%X.\n", inta);
a83b9141 1106 priv->isr_stats.sw++;
5b9f8cd3 1107 iwl_irq_handle_error(priv);
b481de9c
ZY		 1108 handled |= CSR_INT_BIT_SW_ERR;
1109 }
1110
c2e61da2
BC		 1111 /*
1112 * uCode wakes up after power-down sleep.
1113 * Tell device about any new tx or host commands enqueued,
1114 * and about any Rx buffers made available while asleep.
1115 */
b481de9c 1116 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1117 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1118 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1119 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1120 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1121 priv->isr_stats.wakeup++;
b481de9c
ZY		 1122 handled |= CSR_INT_BIT_WAKEUP;
1123 }
1124
1125 /* All uCode command responses, including Tx command responses,
1126 * Rx "responses" (frame-received notification), and other
1127 * notifications from uCode come through here*/
1128 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1129 iwl_rx_handle(priv);
a83b9141 1130 priv->isr_stats.rx++;
b481de9c
ZY		 1131 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1132 }
1133
c72cd19f 1134 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1135 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1136 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1137 priv->isr_stats.tx++;
b481de9c 1138 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1139 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1140 priv->ucode_write_complete = 1;
1141 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1142 }
1143
a83b9141 1144 if (inta & ~handled) {
15b1687c 1145 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1146 priv->isr_stats.unhandled++;
1147 }
b481de9c 1148
40cefda9 1149 if (inta & ~(priv->inta_mask)) {
39aadf8c 1150 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1151 inta & ~priv->inta_mask);
39aadf8c 1152 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1153 }
1154
1155 /* Re-enable all interrupts */
0359facc
MA		 1156 /* only Re-enable if diabled by irq */
1157 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1158 iwl_enable_interrupts(priv);
b481de9c 1159
0a6857e7 1160#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1161 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1162 inta = iwl_read32(priv, CSR_INT);
1163 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1164 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1165 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1166 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1167 }
1168#endif
b481de9c
ZY		 1169}
1170
ef850d7c
MA		 1171/* tasklet for iwlagn interrupt */
1172static void iwl_irq_tasklet(struct iwl_priv *priv)
1173{
1174 u32 inta = 0;
1175 u32 handled = 0;
1176 unsigned long flags;
8756990f 1177 u32 i;
ef850d7c
MA		 1178#ifdef CONFIG_IWLWIFI_DEBUG
1179 u32 inta_mask;
1180#endif
1181
1182 spin_lock_irqsave(&priv->lock, flags);
1183
1184 /* Ack/clear/reset pending uCode interrupts.
1185 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1186 */
48a6be6a
SZ		 1187 /* There is a hardware bug in the interrupt mask function that some
1188 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1189 * they are disabled in the CSR_INT_MASK register. Furthermore the
1190 * ICT interrupt handling mechanism has another bug that might cause
1191 * these unmasked interrupts fail to be detected. We workaround the
1192 * hardware bugs here by ACKing all the possible interrupts so that
1193 * interrupt coalescing can still be achieved.
1194 */
4a35ecf8 1195 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1196
a4c8b2a6 1197 inta = priv->_agn.inta;
ef850d7c
MA		 1198
1199#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1200 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1201 /* just for debug */
1202 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1203 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1204 inta, inta_mask);
1205 }
1206#endif
2f301227
ZY		 1207
1208 spin_unlock_irqrestore(&priv->lock, flags);
1209
a4c8b2a6
JB		 1210 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1211 priv->_agn.inta = 0;
ef850d7c
MA		 1212
1213 /* Now service all interrupt bits discovered above. */
1214 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1215 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1216
1217 /* Tell the device to stop sending interrupts */
1218 iwl_disable_interrupts(priv);
1219
1220 priv->isr_stats.hw++;
1221 iwl_irq_handle_error(priv);
1222
1223 handled |= CSR_INT_BIT_HW_ERR;
1224
ef850d7c
MA		 1225 return;
1226 }
1227
1228#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1229 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1230 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1231 if (inta & CSR_INT_BIT_SCD) {
1232 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1233 "the frame/frames.\n");
1234 priv->isr_stats.sch++;
1235 }
1236
1237 /* Alive notification via Rx interrupt will do the real work */
1238 if (inta & CSR_INT_BIT_ALIVE) {
1239 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1240 priv->isr_stats.alive++;
1241 }
1242 }
1243#endif
1244 /* Safely ignore these bits for debug checks below */
1245 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1246
1247 /* HW RF KILL switch toggled */
1248 if (inta & CSR_INT_BIT_RF_KILL) {
1249 int hw_rf_kill = 0;
1250 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1251 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1252 hw_rf_kill = 1;
1253
4c423a2b 1254 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1255 hw_rf_kill ? "disable radio" : "enable radio");
1256
1257 priv->isr_stats.rfkill++;
1258
1259 /* driver only loads ucode once setting the interface up.
1260 * the driver allows loading the ucode even if the radio
1261 * is killed. Hence update the killswitch state here. The
1262 * rfkill handler will care about restarting if needed.
1263 */
1264 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1265 if (hw_rf_kill)
1266 set_bit(STATUS_RF_KILL_HW, &priv->status);
1267 else
1268 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1269 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1270 }
1271
1272 handled |= CSR_INT_BIT_RF_KILL;
1273 }
1274
1275 /* Chip got too hot and stopped itself */
1276 if (inta & CSR_INT_BIT_CT_KILL) {
1277 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1278 priv->isr_stats.ctkill++;
1279 handled |= CSR_INT_BIT_CT_KILL;
1280 }
1281
1282 /* Error detected by uCode */
1283 if (inta & CSR_INT_BIT_SW_ERR) {
1284 IWL_ERR(priv, "Microcode SW error detected. "
1285 " Restarting 0x%X.\n", inta);
1286 priv->isr_stats.sw++;
ef850d7c
MA		 1287 iwl_irq_handle_error(priv);
1288 handled |= CSR_INT_BIT_SW_ERR;
1289 }
1290
1291 /* uCode wakes up after power-down sleep */
1292 if (inta & CSR_INT_BIT_WAKEUP) {
1293 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1294 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1295 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1296 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1297
1298 priv->isr_stats.wakeup++;
1299
1300 handled |= CSR_INT_BIT_WAKEUP;
1301 }
1302
1303 /* All uCode command responses, including Tx command responses,
1304 * Rx "responses" (frame-received notification), and other
1305 * notifications from uCode come through here*/
40cefda9
MA		 1306 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1307 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1308 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1309 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1310 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1311 iwl_write32(priv, CSR_FH_INT_STATUS,
1312 CSR49_FH_INT_RX_MASK);
1313 }
1314 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1315 handled |= CSR_INT_BIT_RX_PERIODIC;
1316 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1317 }
1318 /* Sending RX interrupt require many steps to be done in the
1319 * the device:
1320 * 1- write interrupt to current index in ICT table.
1321 * 2- dma RX frame.
1322 * 3- update RX shared data to indicate last write index.
1323 * 4- send interrupt.
1324 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1325 * but the shared data changes does not reflect this;
1326 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1327 */
74ba67ed
BC		 1328
1329 /* Disable periodic interrupt; we use it as just a one-shot. */
1330 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1331 CSR_INT_PERIODIC_DIS);
ef850d7c 1332 iwl_rx_handle(priv);
74ba67ed
BC		 1333
1334 /*
1335 * Enable periodic interrupt in 8 msec only if we received
1336 * real RX interrupt (instead of just periodic int), to catch
1337 * any dangling Rx interrupt. If it was just the periodic
1338 * interrupt, there was no dangling Rx activity, and no need
1339 * to extend the periodic interrupt; one-shot is enough.
1340 */
40cefda9 1341 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1342 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1343 CSR_INT_PERIODIC_ENA);
1344
ef850d7c 1345 priv->isr_stats.rx++;
ef850d7c
MA		 1346 }
1347
c72cd19f 1348 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1349 if (inta & CSR_INT_BIT_FH_TX) {
1350 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1351 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1352 priv->isr_stats.tx++;
1353 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1354 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1355 priv->ucode_write_complete = 1;
1356 wake_up_interruptible(&priv->wait_command_queue);
1357 }
1358
1359 if (inta & ~handled) {
1360 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1361 priv->isr_stats.unhandled++;
1362 }
1363
40cefda9 1364 if (inta & ~(priv->inta_mask)) {
ef850d7c 1365 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1366 inta & ~priv->inta_mask);
ef850d7c
MA		 1367 }
1368
ef850d7c
MA		 1369 /* Re-enable all interrupts */
1370 /* only Re-enable if diabled by irq */
1371 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1372 iwl_enable_interrupts(priv);
ef850d7c
MA		 1373}
1374
872c8ddc
WYG		 1375/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1376#define ACK_CNT_RATIO (50)
1377#define BA_TIMEOUT_CNT (5)
1378#define BA_TIMEOUT_MAX (16)
1379
1380/**
1381 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1382 *
1383 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1384 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1385 * operation state.
1386 */
1387bool iwl_good_ack_health(struct iwl_priv *priv,
1388 struct iwl_rx_packet *pkt)
1389{
1390 bool rc = true;
1391 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1392 int ba_timeout_delta;
1393
1394 actual_ack_cnt_delta =
1395 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
f3aebeee 1396 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1397 expected_ack_cnt_delta =
1398 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
f3aebeee 1399 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1400 ba_timeout_delta =
1401 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
f3aebeee 1402 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1403 if ((priv->_agn.agg_tids_count > 0) &&
1404 (expected_ack_cnt_delta > 0) &&
1405 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1406 < ACK_CNT_RATIO) &&
1407 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1408 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1409 " expected_ack_cnt = %d\n",
1410 actual_ack_cnt_delta, expected_ack_cnt_delta);
1411
d73e4923
JB		 1412#ifdef CONFIG_IWLWIFI_DEBUGFS
1413 /*
1414 * This is ifdef'ed on DEBUGFS because otherwise the
1415 * statistics aren't available. If DEBUGFS is set but
1416 * DEBUG is not, these will just compile out.
1417 */
872c8ddc 1418 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
f3aebeee 1419 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1420 IWL_DEBUG_RADIO(priv,
1421 "ack_or_ba_timeout_collision delta = %d\n",
f3aebeee 1422 priv->_agn.delta_statistics.tx.
872c8ddc
WYG		 1423 ack_or_ba_timeout_collision);
1424#endif
1425 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1426 ba_timeout_delta);
1427 if (!actual_ack_cnt_delta &&
1428 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1429 rc = false;
1430 }
1431 return rc;
1432}
1433
a83b9141 1434
7d47618a
EG		 1435/*****************************************************************************
1436 *
1437 * sysfs attributes
1438 *
1439 *****************************************************************************/
1440
1441#ifdef CONFIG_IWLWIFI_DEBUG
1442
1443/*
1444 * The following adds a new attribute to the sysfs representation
1445 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1446 * used for controlling the debug level.
1447 *
1448 * See the level definitions in iwl for details.
1449 *
1450 * The debug_level being managed using sysfs below is a per device debug
1451 * level that is used instead of the global debug level if it (the per
1452 * device debug level) is set.
1453 */
1454static ssize_t show_debug_level(struct device *d,
1455 struct device_attribute *attr, char *buf)
1456{
1457 struct iwl_priv *priv = dev_get_drvdata(d);
1458 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1459}
1460static ssize_t store_debug_level(struct device *d,
1461 struct device_attribute *attr,
1462 const char *buf, size_t count)
1463{
1464 struct iwl_priv *priv = dev_get_drvdata(d);
1465 unsigned long val;
1466 int ret;
1467
1468 ret = strict_strtoul(buf, 0, &val);
1469 if (ret)
1470 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1471 else {
1472 priv->debug_level = val;
1473 if (iwl_alloc_traffic_mem(priv))
1474 IWL_ERR(priv,
1475 "Not enough memory to generate traffic log\n");
1476 }
1477 return strnlen(buf, count);
1478}
1479
1480static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1481 show_debug_level, store_debug_level);
1482
1483
1484#endif /* CONFIG_IWLWIFI_DEBUG */
1485
1486
1487static ssize_t show_temperature(struct device *d,
1488 struct device_attribute *attr, char *buf)
1489{
1490 struct iwl_priv *priv = dev_get_drvdata(d);
1491
1492 if (!iwl_is_alive(priv))
1493 return -EAGAIN;
1494
1495 return sprintf(buf, "%d\n", priv->temperature);
1496}
1497
1498static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1499
1500static ssize_t show_tx_power(struct device *d,
1501 struct device_attribute *attr, char *buf)
1502{
1503 struct iwl_priv *priv = dev_get_drvdata(d);
1504
1505 if (!iwl_is_ready_rf(priv))
1506 return sprintf(buf, "off\n");
1507 else
1508 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1509}
1510
1511static ssize_t store_tx_power(struct device *d,
1512 struct device_attribute *attr,
1513 const char *buf, size_t count)
1514{
1515 struct iwl_priv *priv = dev_get_drvdata(d);
1516 unsigned long val;
1517 int ret;
1518
1519 ret = strict_strtoul(buf, 10, &val);
1520 if (ret)
1521 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1522 else {
1523 ret = iwl_set_tx_power(priv, val, false);
1524 if (ret)
1525 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1526 ret);
1527 else
1528 ret = count;
1529 }
1530 return ret;
1531}
1532
1533static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1534
7d47618a
EG		 1535static struct attribute *iwl_sysfs_entries[] = {
1536 &dev_attr_temperature.attr,
1537 &dev_attr_tx_power.attr,
7d47618a
EG		 1538#ifdef CONFIG_IWLWIFI_DEBUG
1539 &dev_attr_debug_level.attr,
1540#endif
1541 NULL
1542};
1543
1544static struct attribute_group iwl_attribute_group = {
1545 .name = NULL, /* put in device directory */
1546 .attrs = iwl_sysfs_entries,
1547};
1548
b481de9c
ZY		 1549/******************************************************************************
1550 *
1551 * uCode download functions
1552 *
1553 ******************************************************************************/
1554
5b9f8cd3 1555static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1556{
98c92211
TW		 1557 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1558 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1559 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1560 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1561 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1562 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1563}
1564
5b9f8cd3 1565static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1566{
1567 /* Remove all resets to allow NIC to operate */
1568 iwl_write32(priv, CSR_RESET, 0);
1569}
1570
dd7a2509
JB		 1571struct iwlagn_ucode_capabilities {
1572 u32 max_probe_length;
6a822d06 1573 u32 standard_phy_calibration_size;
ece9c4ee 1574 bool pan;
dd7a2509 1575};
edcdf8b2 1576
b08dfd04 1577static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1578static int iwl_mac_setup_register(struct iwl_priv *priv,
1579 struct iwlagn_ucode_capabilities *capa);
b08dfd04 1580
39396085
JS		 1581#define UCODE_EXPERIMENTAL_INDEX 100
1582#define UCODE_EXPERIMENTAL_TAG "exp"
1583
b08dfd04
JB		 1584static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1585{
1586 const char *name_pre = priv->cfg->fw_name_pre;
39396085 1587 char tag[8];
b08dfd04 1588
39396085
JS		 1589 if (first) {
1590#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1591 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1592 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1593 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1594#endif
b08dfd04 1595 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS		 1596 sprintf(tag, "%d", priv->fw_index);
1597 } else {
b08dfd04 1598 priv->fw_index--;
39396085
JS		 1599 sprintf(tag, "%d", priv->fw_index);
1600 }
b08dfd04
JB		 1601
1602 if (priv->fw_index < priv->cfg->ucode_api_min) {
1603 IWL_ERR(priv, "no suitable firmware found!\n");
1604 return -ENOENT;
1605 }
1606
39396085 1607 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1608
39396085
JS		 1609 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1610 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1611 ? "EXPERIMENTAL " : "",
b08dfd04
JB		 1612 priv->firmware_name);
1613
1614 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1615 &priv->pci_dev->dev, GFP_KERNEL, priv,
1616 iwl_ucode_callback);
1617}
1618
0e9a44dc
JB		 1619struct iwlagn_firmware_pieces {
1620 const void *inst, *data, *init, *init_data, *boot;
1621 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1622
1623 u32 build;
b2e640d4
JB		 1624
1625 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1626 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1627};
1628
1629static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1630 const struct firmware *ucode_raw,
1631 struct iwlagn_firmware_pieces *pieces)
1632{
1633 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1634 u32 api_ver, hdr_size;
1635 const u8 *src;
1636
1637 priv->ucode_ver = le32_to_cpu(ucode->ver);
1638 api_ver = IWL_UCODE_API(priv->ucode_ver);
1639
1640 switch (api_ver) {
1641 default:
1642 /*
1643 * 4965 doesn't revision the firmware file format
1644 * along with the API version, it always uses v1
1645 * file format.
1646 */
1647 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1648 CSR_HW_REV_TYPE_4965) {
1649 hdr_size = 28;
1650 if (ucode_raw->size < hdr_size) {
1651 IWL_ERR(priv, "File size too small!\n");
1652 return -EINVAL;
1653 }
1654 pieces->build = le32_to_cpu(ucode->u.v2.build);
1655 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1656 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1657 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1658 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1659 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1660 src = ucode->u.v2.data;
1661 break;
1662 }
1663 /* fall through for 4965 */
1664 case 0:
1665 case 1:
1666 case 2:
1667 hdr_size = 24;
1668 if (ucode_raw->size < hdr_size) {
1669 IWL_ERR(priv, "File size too small!\n");
1670 return -EINVAL;
1671 }
1672 pieces->build = 0;
1673 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1674 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1675 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1676 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1677 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1678 src = ucode->u.v1.data;
1679 break;
1680 }
1681
1682 /* Verify size of file vs. image size info in file's header */
1683 if (ucode_raw->size != hdr_size + pieces->inst_size +
1684 pieces->data_size + pieces->init_size +
1685 pieces->init_data_size + pieces->boot_size) {
1686
1687 IWL_ERR(priv,
1688 "uCode file size %d does not match expected size\n",
1689 (int)ucode_raw->size);
1690 return -EINVAL;
1691 }
1692
1693 pieces->inst = src;
1694 src += pieces->inst_size;
1695 pieces->data = src;
1696 src += pieces->data_size;
1697 pieces->init = src;
1698 src += pieces->init_size;
1699 pieces->init_data = src;
1700 src += pieces->init_data_size;
1701 pieces->boot = src;
1702 src += pieces->boot_size;
1703
1704 return 0;
1705}
1706
dd7a2509
JB		 1707static int iwlagn_wanted_ucode_alternative = 1;
1708
1709static int iwlagn_load_firmware(struct iwl_priv *priv,
1710 const struct firmware *ucode_raw,
1711 struct iwlagn_firmware_pieces *pieces,
1712 struct iwlagn_ucode_capabilities *capa)
1713{
1714 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1715 struct iwl_ucode_tlv *tlv;
1716 size_t len = ucode_raw->size;
1717 const u8 *data;
1718 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1719 u64 alternatives;
ad8d8333
WYG		 1720 u32 tlv_len;
1721 enum iwl_ucode_tlv_type tlv_type;
1722 const u8 *tlv_data;
dd7a2509 1723
ad8d8333
WYG		 1724 if (len < sizeof(*ucode)) {
1725 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1726 return -EINVAL;
ad8d8333 1727 }
dd7a2509 1728
ad8d8333
WYG		 1729 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1730 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1731 le32_to_cpu(ucode->magic));
dd7a2509 1732 return -EINVAL;
ad8d8333 1733 }
dd7a2509
JB		 1734
1735 /*
1736 * Check which alternatives are present, and "downgrade"
1737 * when the chosen alternative is not present, warning
1738 * the user when that happens. Some files may not have
1739 * any alternatives, so don't warn in that case.
1740 */
1741 alternatives = le64_to_cpu(ucode->alternatives);
1742 tmp = wanted_alternative;
1743 if (wanted_alternative > 63)
1744 wanted_alternative = 63;
1745 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1746 wanted_alternative--;
1747 if (wanted_alternative && wanted_alternative != tmp)
1748 IWL_WARN(priv,
1749 "uCode alternative %d not available, choosing %d\n",
1750 tmp, wanted_alternative);
1751
1752 priv->ucode_ver = le32_to_cpu(ucode->ver);
1753 pieces->build = le32_to_cpu(ucode->build);
1754 data = ucode->data;
1755
1756 len -= sizeof(*ucode);
1757
704da534 1758 while (len >= sizeof(*tlv)) {
dd7a2509 1759 u16 tlv_alt;
dd7a2509
JB		 1760
1761 len -= sizeof(*tlv);
1762 tlv = (void *)data;
1763
1764 tlv_len = le32_to_cpu(tlv->length);
1765 tlv_type = le16_to_cpu(tlv->type);
1766 tlv_alt = le16_to_cpu(tlv->alternative);
1767 tlv_data = tlv->data;
1768
ad8d8333
WYG		 1769 if (len < tlv_len) {
1770 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1771 len, tlv_len);
dd7a2509 1772 return -EINVAL;
ad8d8333 1773 }
dd7a2509
JB		 1774 len -= ALIGN(tlv_len, 4);
1775 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1776
1777 /*
1778 * Alternative 0 is always valid.
1779 *
1780 * Skip alternative TLVs that are not selected.
1781 */
1782 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1783 continue;
1784
1785 switch (tlv_type) {
1786 case IWL_UCODE_TLV_INST:
1787 pieces->inst = tlv_data;
1788 pieces->inst_size = tlv_len;
1789 break;
1790 case IWL_UCODE_TLV_DATA:
1791 pieces->data = tlv_data;
1792 pieces->data_size = tlv_len;
1793 break;
1794 case IWL_UCODE_TLV_INIT:
1795 pieces->init = tlv_data;
1796 pieces->init_size = tlv_len;
1797 break;
1798 case IWL_UCODE_TLV_INIT_DATA:
1799 pieces->init_data = tlv_data;
1800 pieces->init_data_size = tlv_len;
1801 break;
1802 case IWL_UCODE_TLV_BOOT:
1803 pieces->boot = tlv_data;
1804 pieces->boot_size = tlv_len;
1805 break;
1806 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1807 if (tlv_len != sizeof(u32))
1808 goto invalid_tlv_len;
1809 capa->max_probe_length =
ad8d8333 1810 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1811 break;
ece9c4ee
JB		 1812 case IWL_UCODE_TLV_PAN:
1813 if (tlv_len)
1814 goto invalid_tlv_len;
1815 capa->pan = true;
1816 break;
b2e640d4 1817 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1818 if (tlv_len != sizeof(u32))
1819 goto invalid_tlv_len;
1820 pieces->init_evtlog_ptr =
ad8d8333 1821 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1822 break;
1823 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 1824 if (tlv_len != sizeof(u32))
1825 goto invalid_tlv_len;
1826 pieces->init_evtlog_size =
ad8d8333 1827 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1828 break;
1829 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 1830 if (tlv_len != sizeof(u32))
1831 goto invalid_tlv_len;
1832 pieces->init_errlog_ptr =
ad8d8333 1833 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1834 break;
1835 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 1836 if (tlv_len != sizeof(u32))
1837 goto invalid_tlv_len;
1838 pieces->inst_evtlog_ptr =
ad8d8333 1839 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1840 break;
1841 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 1842 if (tlv_len != sizeof(u32))
1843 goto invalid_tlv_len;
1844 pieces->inst_evtlog_size =
ad8d8333 1845 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1846 break;
1847 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 1848 if (tlv_len != sizeof(u32))
1849 goto invalid_tlv_len;
1850 pieces->inst_errlog_ptr =
ad8d8333 1851 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 1852 break;
c8312fac
WYG		 1853 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1854 if (tlv_len)
704da534
JB		 1855 goto invalid_tlv_len;
1856 priv->enhance_sensitivity_table = true;
c8312fac 1857 break;
6a822d06 1858 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 1859 if (tlv_len != sizeof(u32))
1860 goto invalid_tlv_len;
1861 capa->standard_phy_calibration_size =
6a822d06
WYG		 1862 le32_to_cpup((__le32 *)tlv_data);
1863 break;
dd7a2509 1864 default:
ad8d8333 1865 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 1866 break;
1867 }
1868 }
1869
ad8d8333
WYG		 1870 if (len) {
1871 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1872 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 1873 return -EINVAL;
ad8d8333 1874 }
dd7a2509 1875
704da534
JB		 1876 return 0;
1877
1878 invalid_tlv_len:
1879 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1880 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1881
1882 return -EINVAL;
dd7a2509
JB		 1883}
1884
b481de9c 1885/**
b08dfd04 1886 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1887 *
b08dfd04
JB		 1888 * If loaded successfully, copies the firmware into buffers
1889 * for the card to fetch (via DMA).
b481de9c 1890 */
b08dfd04 1891static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1892{
b08dfd04 1893 struct iwl_priv *priv = context;
cc0f555d 1894 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 1895 int err;
1896 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 1897 const unsigned int api_max = priv->cfg->ucode_api_max;
1898 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 1899 u32 api_ver;
3e4de761 1900 char buildstr[25];
0e9a44dc 1901 u32 build;
dd7a2509
JB		 1902 struct iwlagn_ucode_capabilities ucode_capa = {
1903 .max_probe_length = 200,
6a822d06 1904 .standard_phy_calibration_size =
642454cc 1905 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 1906 };
0e9a44dc
JB		 1907
1908 memset(&pieces, 0, sizeof(pieces));
b481de9c 1909
b08dfd04 1910 if (!ucode_raw) {
39396085
JS		 1911 if (priv->fw_index <= priv->cfg->ucode_api_max)
1912 IWL_ERR(priv,
1913 "request for firmware file '%s' failed.\n",
1914 priv->firmware_name);
b08dfd04 1915 goto try_again;
b481de9c
ZY		 1916 }
1917
b08dfd04
JB		 1918 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1919 priv->firmware_name, ucode_raw->size);
b481de9c 1920
22adba2a
JB		 1921 /* Make sure that we got at least the API version number */
1922 if (ucode_raw->size < 4) {
15b1687c 1923 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1924 goto try_again;
b481de9c
ZY		 1925 }
1926
1927 /* Data from ucode file: header followed by uCode images */
cc0f555d 1928 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1929
0e9a44dc
JB		 1930 if (ucode->ver)
1931 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1932 else
dd7a2509
JB		 1933 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1934 &ucode_capa);
22adba2a 1935
0e9a44dc
JB		 1936 if (err)
1937 goto try_again;
b481de9c 1938
a0987a8d 1939 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 1940 build = pieces.build;
a0987a8d 1941
0e9a44dc
JB		 1942 /*
1943 * api_ver should match the api version forming part of the
1944 * firmware filename ... but we don't check for that and only rely
1945 * on the API version read from firmware header from here on forward
1946 */
65cccfb0
WYG		 1947 /* no api version check required for experimental uCode */
1948 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1949 if (api_ver < api_min || api_ver > api_max) {
1950 IWL_ERR(priv,
1951 "Driver unable to support your firmware API. "
1952 "Driver supports v%u, firmware is v%u.\n",
1953 api_max, api_ver);
1954 goto try_again;
1955 }
b08dfd04 1956
65cccfb0
WYG		 1957 if (api_ver != api_max)
1958 IWL_ERR(priv,
1959 "Firmware has old API version. Expected v%u, "
1960 "got v%u. New firmware can be obtained "
1961 "from http://www.intellinuxwireless.org.\n",
1962 api_max, api_ver);
1963 }
a0987a8d 1964
3e4de761 1965 if (build)
39396085
JS		 1966 sprintf(buildstr, " build %u%s", build,
1967 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1968 ? " (EXP)" : "");
3e4de761
JB		 1969 else
1970 buildstr[0] = '\0';
1971
1972 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1973 IWL_UCODE_MAJOR(priv->ucode_ver),
1974 IWL_UCODE_MINOR(priv->ucode_ver),
1975 IWL_UCODE_API(priv->ucode_ver),
1976 IWL_UCODE_SERIAL(priv->ucode_ver),
1977 buildstr);
a0987a8d 1978
5ebeb5a6
RC		 1979 snprintf(priv->hw->wiphy->fw_version,
1980 sizeof(priv->hw->wiphy->fw_version),
3e4de761 1981 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 1982 IWL_UCODE_MAJOR(priv->ucode_ver),
1983 IWL_UCODE_MINOR(priv->ucode_ver),
1984 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 1985 IWL_UCODE_SERIAL(priv->ucode_ver),
1986 buildstr);
b481de9c 1987
b08dfd04
JB		 1988 /*
1989 * For any of the failures below (before allocating pci memory)
1990 * we will try to load a version with a smaller API -- maybe the
1991 * user just got a corrupted version of the latest API.
1992 */
1993
0e9a44dc
JB		 1994 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1995 priv->ucode_ver);
1996 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1997 pieces.inst_size);
1998 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1999 pieces.data_size);
2000 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2001 pieces.init_size);
2002 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2003 pieces.init_data_size);
2004 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2005 pieces.boot_size);
b481de9c
ZY		 2006
2007 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2008 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2009 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2010 pieces.inst_size);
b08dfd04 2011 goto try_again;
b481de9c
ZY		 2012 }
2013
0e9a44dc
JB		 2014 if (pieces.data_size > priv->hw_params.max_data_size) {
2015 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2016 pieces.data_size);
b08dfd04 2017 goto try_again;
b481de9c 2018 }
0e9a44dc
JB		 2019
2020 if (pieces.init_size > priv->hw_params.max_inst_size) {
2021 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2022 pieces.init_size);
b08dfd04 2023 goto try_again;
b481de9c 2024 }
0e9a44dc
JB		 2025
2026 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2027 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2028 pieces.init_data_size);
b08dfd04 2029 goto try_again;
b481de9c 2030 }
0e9a44dc
JB		 2031
2032 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2033 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2034 pieces.boot_size);
b08dfd04 2035 goto try_again;
b481de9c
ZY		 2036 }
2037
2038 /* Allocate ucode buffers for card's bus-master loading ... */
2039
2040 /* Runtime instructions and 2 copies of data:
2041 * 1) unmodified from disk
2042 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2043 priv->ucode_code.len = pieces.inst_size;
98c92211 2044 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2045
0e9a44dc 2046 priv->ucode_data.len = pieces.data_size;
98c92211 2047 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2048
0e9a44dc 2049 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2050 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2051
1f304e4e
ZY		 2052 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2053 !priv->ucode_data_backup.v_addr)
2054 goto err_pci_alloc;
2055
b481de9c 2056 /* Initialization instructions and data */
0e9a44dc
JB		 2057 if (pieces.init_size && pieces.init_data_size) {
2058 priv->ucode_init.len = pieces.init_size;
98c92211 2059 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2060
0e9a44dc 2061 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2062 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2063
2064 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2065 goto err_pci_alloc;
2066 }
b481de9c
ZY		 2067
2068 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2069 if (pieces.boot_size) {
2070 priv->ucode_boot.len = pieces.boot_size;
98c92211 2071 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2072
90e759d1
TW		 2073 if (!priv->ucode_boot.v_addr)
2074 goto err_pci_alloc;
2075 }
b481de9c 2076
b2e640d4
JB		 2077 /* Now that we can no longer fail, copy information */
2078
2079 /*
2080 * The (size - 16) / 12 formula is based on the information recorded
2081 * for each event, which is of mode 1 (including timestamp) for all
2082 * new microcodes that include this information.
2083 */
2084 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2085 if (pieces.init_evtlog_size)
2086 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2087 else
7cb1b088
WYG		 2088 priv->_agn.init_evtlog_size =
2089 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2090 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2091 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2092 if (pieces.inst_evtlog_size)
2093 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2094 else
7cb1b088
WYG		 2095 priv->_agn.inst_evtlog_size =
2096 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2097 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2098
ece9c4ee
JB		 2099 if (ucode_capa.pan) {
2100 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
c10afb6e 2101 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
ece9c4ee
JB		 2102 } else
2103 priv->sta_key_max_num = STA_KEY_MAX_NUM;
c10afb6e 2104
b481de9c
ZY		 2105 /* Copy images into buffers for card's bus-master reads ... */
2106
2107 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2108 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2109 pieces.inst_size);
2110 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2111
e1623446 2112 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2113 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2114
0e9a44dc
JB		 2115 /*
2116 * Runtime data
2117 * NOTE: Copy into backup buffer will be done in iwl_up()
2118 */
2119 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2120 pieces.data_size);
2121 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2122 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2123
2124 /* Initialization instructions */
2125 if (pieces.init_size) {
e1623446 2126 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2127 pieces.init_size);
2128 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2129 }
2130
0e9a44dc
JB		 2131 /* Initialization data */
2132 if (pieces.init_data_size) {
e1623446 2133 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2134 pieces.init_data_size);
2135 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2136 pieces.init_data_size);
b481de9c
ZY		 2137 }
2138
0e9a44dc
JB		 2139 /* Bootstrap instructions */
2140 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2141 pieces.boot_size);
2142 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2143
6a822d06
WYG		 2144 /*
2145 * figure out the offset of chain noise reset and gain commands
2146 * base on the size of standard phy calibration commands table size
2147 */
2148 if (ucode_capa.standard_phy_calibration_size >
2149 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2150 ucode_capa.standard_phy_calibration_size =
2151 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2152
2153 priv->_agn.phy_calib_chain_noise_reset_cmd =
2154 ucode_capa.standard_phy_calibration_size;
2155 priv->_agn.phy_calib_chain_noise_gain_cmd =
2156 ucode_capa.standard_phy_calibration_size + 1;
2157
b08dfd04
JB		 2158 /**************************************************
2159 * This is still part of probe() in a sense...
2160 *
2161 * 9. Setup and register with mac80211 and debugfs
2162 **************************************************/
dd7a2509 2163 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2164 if (err)
2165 goto out_unbind;
2166
2167 err = iwl_dbgfs_register(priv, DRV_NAME);
2168 if (err)
2169 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2170
7d47618a
EG		 2171 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2172 &iwl_attribute_group);
2173 if (err) {
2174 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2175 goto out_unbind;
2176 }
2177
b481de9c
ZY		 2178 /* We have our copies now, allow OS release its copies */
2179 release_firmware(ucode_raw);
a15707d8 2180 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2181 return;
2182
2183 try_again:
2184 /* try next, if any */
2185 if (iwl_request_firmware(priv, false))
2186 goto out_unbind;
2187 release_firmware(ucode_raw);
2188 return;
b481de9c
ZY		 2189
2190 err_pci_alloc:
15b1687c 2191 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2192 iwl_dealloc_ucode_pci(priv);
b08dfd04 2193 out_unbind:
a15707d8 2194 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2195 device_release_driver(&priv->pci_dev->dev);
b481de9c 2196 release_firmware(ucode_raw);
b481de9c
ZY		 2197}
2198
b7a79404
RC		 2199static const char *desc_lookup_text[] = {
2200 "OK",
2201 "FAIL",
2202 "BAD_PARAM",
2203 "BAD_CHECKSUM",
2204 "NMI_INTERRUPT_WDG",
2205 "SYSASSERT",
2206 "FATAL_ERROR",
2207 "BAD_COMMAND",
2208 "HW_ERROR_TUNE_LOCK",
2209 "HW_ERROR_TEMPERATURE",
2210 "ILLEGAL_CHAN_FREQ",
2211 "VCC_NOT_STABLE",
2212 "FH_ERROR",
2213 "NMI_INTERRUPT_HOST",
2214 "NMI_INTERRUPT_ACTION_PT",
2215 "NMI_INTERRUPT_UNKNOWN",
2216 "UCODE_VERSION_MISMATCH",
2217 "HW_ERROR_ABS_LOCK",
2218 "HW_ERROR_CAL_LOCK_FAIL",
2219 "NMI_INTERRUPT_INST_ACTION_PT",
2220 "NMI_INTERRUPT_DATA_ACTION_PT",
2221 "NMI_TRM_HW_ER",
2222 "NMI_INTERRUPT_TRM",
2223 "NMI_INTERRUPT_BREAK_POINT"
2224 "DEBUG_0",
2225 "DEBUG_1",
2226 "DEBUG_2",
2227 "DEBUG_3",
b7a79404
RC		 2228};
2229
4b58645c
JS		 2230static struct { char *name; u8 num; } advanced_lookup[] = {
2231 { "NMI_INTERRUPT_WDG", 0x34 },
2232 { "SYSASSERT", 0x35 },
2233 { "UCODE_VERSION_MISMATCH", 0x37 },
2234 { "BAD_COMMAND", 0x38 },
2235 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2236 { "FATAL_ERROR", 0x3D },
2237 { "NMI_TRM_HW_ERR", 0x46 },
2238 { "NMI_INTERRUPT_TRM", 0x4C },
2239 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2240 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2241 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2242 { "NMI_INTERRUPT_HOST", 0x66 },
2243 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2244 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2245 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2246 { "ADVANCED_SYSASSERT", 0 },
2247};
2248
2249static const char *desc_lookup(u32 num)
b7a79404 2250{
4b58645c
JS		 2251 int i;
2252 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 2253
4b58645c
JS		 2254 if (num < max)
2255 return desc_lookup_text[num];
b7a79404 2256
4b58645c
JS		 2257 max = ARRAY_SIZE(advanced_lookup) - 1;
2258 for (i = 0; i < max; i++) {
2259 if (advanced_lookup[i].num == num)
2260 break;;
2261 }
2262 return advanced_lookup[i].name;
b7a79404
RC		 2263}
2264
2265#define ERROR_START_OFFSET (1 * sizeof(u32))
2266#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2267
2268void iwl_dump_nic_error_log(struct iwl_priv *priv)
2269{
2270 u32 data2, line;
2271 u32 desc, time, count, base, data1;
2272 u32 blink1, blink2, ilink1, ilink2;
461ef382 2273 u32 pc, hcmd;
b7a79404 2274
b2e640d4 2275 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2276 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2277 if (!base)
2278 base = priv->_agn.init_errlog_ptr;
2279 } else {
b7a79404 2280 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2281 if (!base)
2282 base = priv->_agn.inst_errlog_ptr;
2283 }
b7a79404
RC		 2284
2285 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2286 IWL_ERR(priv,
2287 "Not valid error log pointer 0x%08X for %s uCode\n",
2288 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2289 return;
2290 }
2291
2292 count = iwl_read_targ_mem(priv, base);
2293
2294 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2295 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2296 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2297 priv->status, count);
2298 }
2299
2300 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
6e6ebf4b 2301 priv->isr_stats.err_code = desc;
461ef382 2302 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2303 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2304 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2305 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2306 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2307 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2308 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2309 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2310 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2311 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2312
be1a71a1
JB		 2313 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2314 blink1, blink2, ilink1, ilink2);
2315
87563715 2316 IWL_ERR(priv, "Desc Time "
b7a79404 2317 "data1 data2 line\n");
87563715 2318 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2319 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2320 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2321 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2322 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2323}
2324
2325#define EVENT_START_OFFSET (4 * sizeof(u32))
2326
2327/**
2328 * iwl_print_event_log - Dump error event log to syslog
2329 *
2330 */
b03d7d0f
WYG		 2331static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2332 u32 num_events, u32 mode,
2333 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2334{
2335 u32 i;
2336 u32 base; /* SRAM byte address of event log header */
2337 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2338 u32 ptr; /* SRAM byte address of log data */
2339 u32 ev, time, data; /* event log data */
e5854471 2340 unsigned long reg_flags;
b7a79404
RC		 2341
2342 if (num_events == 0)
b03d7d0f 2343 return pos;
b2e640d4
JB		 2344
2345 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2346 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2347 if (!base)
2348 base = priv->_agn.init_evtlog_ptr;
2349 } else {
b7a79404 2350 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2351 if (!base)
2352 base = priv->_agn.inst_evtlog_ptr;
2353 }
b7a79404
RC		 2354
2355 if (mode == 0)
2356 event_size = 2 * sizeof(u32);
2357 else
2358 event_size = 3 * sizeof(u32);
2359
2360 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2361
e5854471
BC		 2362 /* Make sure device is powered up for SRAM reads */
2363 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2364 iwl_grab_nic_access(priv);
2365
2366 /* Set starting address; reads will auto-increment */
2367 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2368 rmb();
2369
b7a79404
RC		 2370 /* "time" is actually "data" for mode 0 (no timestamp).
2371 * place event id # at far right for easier visual parsing. */
2372 for (i = 0; i < num_events; i++) {
e5854471
BC		 2373 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2374 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2375 if (mode == 0) {
2376 /* data, ev */
b03d7d0f
WYG		 2377 if (bufsz) {
2378 pos += scnprintf(*buf + pos, bufsz - pos,
2379 "EVT_LOG:0x%08x:%04u\n",
2380 time, ev);
2381 } else {
2382 trace_iwlwifi_dev_ucode_event(priv, 0,
2383 time, ev);
2384 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2385 time, ev);
2386 }
b7a79404 2387 } else {
e5854471 2388 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2389 if (bufsz) {
2390 pos += scnprintf(*buf + pos, bufsz - pos,
2391 "EVT_LOGT:%010u:0x%08x:%04u\n",
2392 time, data, ev);
2393 } else {
2394 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2395 time, data, ev);
b03d7d0f
WYG		 2396 trace_iwlwifi_dev_ucode_event(priv, time,
2397 data, ev);
2398 }
b7a79404
RC		 2399 }
2400 }
e5854471
BC		 2401
2402 /* Allow device to power down */
2403 iwl_release_nic_access(priv);
2404 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2405 return pos;
b7a79404
RC		 2406}
2407
c341ddb2
WYG		 2408/**
2409 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2410 */
b03d7d0f
WYG		 2411static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2412 u32 num_wraps, u32 next_entry,
2413 u32 size, u32 mode,
2414 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2415{
2416 /*
2417 * display the newest DEFAULT_LOG_ENTRIES entries
2418 * i.e the entries just before the next ont that uCode would fill.
2419 */
2420 if (num_wraps) {
2421 if (next_entry < size) {
b03d7d0f
WYG		 2422 pos = iwl_print_event_log(priv,
2423 capacity - (size - next_entry),
2424 size - next_entry, mode,
2425 pos, buf, bufsz);
2426 pos = iwl_print_event_log(priv, 0,
2427 next_entry, mode,
2428 pos, buf, bufsz);
c341ddb2 2429 } else
b03d7d0f
WYG		 2430 pos = iwl_print_event_log(priv, next_entry - size,
2431 size, mode, pos, buf, bufsz);
c341ddb2 2432 } else {
b03d7d0f
WYG		 2433 if (next_entry < size) {
2434 pos = iwl_print_event_log(priv, 0, next_entry,
2435 mode, pos, buf, bufsz);
2436 } else {
2437 pos = iwl_print_event_log(priv, next_entry - size,
2438 size, mode, pos, buf, bufsz);
2439 }
c341ddb2 2440 }
b03d7d0f 2441 return pos;
c341ddb2
WYG		 2442}
2443
c341ddb2
WYG		 2444#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2445
b03d7d0f
WYG		 2446int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2447 char **buf, bool display)
b7a79404
RC		 2448{
2449 u32 base; /* SRAM byte address of event log header */
2450 u32 capacity; /* event log capacity in # entries */
2451 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2452 u32 num_wraps; /* # times uCode wrapped to top of log */
2453 u32 next_entry; /* index of next entry to be written by uCode */
2454 u32 size; /* # entries that we'll print */
b2e640d4 2455 u32 logsize;
b03d7d0f
WYG		 2456 int pos = 0;
2457 size_t bufsz = 0;
b7a79404 2458
b2e640d4 2459 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2460 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2461 logsize = priv->_agn.init_evtlog_size;
2462 if (!base)
2463 base = priv->_agn.init_evtlog_ptr;
2464 } else {
b7a79404 2465 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2466 logsize = priv->_agn.inst_evtlog_size;
2467 if (!base)
2468 base = priv->_agn.inst_evtlog_ptr;
2469 }
b7a79404
RC		 2470
2471 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2472 IWL_ERR(priv,
2473 "Invalid event log pointer 0x%08X for %s uCode\n",
2474 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2475 return -EINVAL;
b7a79404
RC		 2476 }
2477
2478 /* event log header */
2479 capacity = iwl_read_targ_mem(priv, base);
2480 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2481 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2482 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2483
b2e640d4 2484 if (capacity > logsize) {
84c40692 2485 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2486 capacity, logsize);
2487 capacity = logsize;
84c40692
BC		 2488 }
2489
b2e640d4 2490 if (next_entry > logsize) {
84c40692 2491 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2492 next_entry, logsize);
2493 next_entry = logsize;
84c40692
BC		 2494 }
2495
b7a79404
RC		 2496 size = num_wraps ? capacity : next_entry;
2497
2498 /* bail out if nothing in log */
2499 if (size == 0) {
2500 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2501 return pos;
b7a79404
RC		 2502 }
2503
f37837c9
WYG		 2504 /* enable/disable bt channel announcement */
2505 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2506
c341ddb2 2507#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2508 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2509 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2510 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2511#else
2512 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2513 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2514#endif
2515 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2516 size);
b7a79404 2517
c341ddb2 2518#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2519 if (display) {
2520 if (full_log)
2521 bufsz = capacity * 48;
2522 else
2523 bufsz = size * 48;
2524 *buf = kmalloc(bufsz, GFP_KERNEL);
2525 if (!*buf)
937c397e 2526 return -ENOMEM;
b03d7d0f 2527 }
c341ddb2
WYG		 2528 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2529 /*
2530 * if uCode has wrapped back to top of log,
2531 * start at the oldest entry,
2532 * i.e the next one that uCode would fill.
2533 */
2534 if (num_wraps)
b03d7d0f
WYG		 2535 pos = iwl_print_event_log(priv, next_entry,
2536 capacity - next_entry, mode,
2537 pos, buf, bufsz);
c341ddb2 2538 /* (then/else) start at top of log */
b03d7d0f
WYG		 2539 pos = iwl_print_event_log(priv, 0,
2540 next_entry, mode, pos, buf, bufsz);
c341ddb2 2541 } else
b03d7d0f
WYG		 2542 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2543 next_entry, size, mode,
2544 pos, buf, bufsz);
c341ddb2 2545#else
b03d7d0f
WYG		 2546 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2547 next_entry, size, mode,
2548 pos, buf, bufsz);
b7a79404 2549#endif
b03d7d0f 2550 return pos;
c341ddb2 2551}
b7a79404 2552
0975cc8f
WYG		 2553static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2554{
2555 struct iwl_ct_kill_config cmd;
2556 struct iwl_ct_kill_throttling_config adv_cmd;
2557 unsigned long flags;
2558 int ret = 0;
2559
2560 spin_lock_irqsave(&priv->lock, flags);
2561 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2562 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2563 spin_unlock_irqrestore(&priv->lock, flags);
2564 priv->thermal_throttle.ct_kill_toggle = false;
2565
7cb1b088 2566 if (priv->cfg->base_params->support_ct_kill_exit) {
0975cc8f
WYG		 2567 adv_cmd.critical_temperature_enter =
2568 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2569 adv_cmd.critical_temperature_exit =
2570 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2571
2572 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2573 sizeof(adv_cmd), &adv_cmd);
2574 if (ret)
2575 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2576 else
2577 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2578 "succeeded, "
2579 "critical temperature enter is %d,"
2580 "exit is %d\n",
2581 priv->hw_params.ct_kill_threshold,
2582 priv->hw_params.ct_kill_exit_threshold);
2583 } else {
2584 cmd.critical_temperature_R =
2585 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2586
2587 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2588 sizeof(cmd), &cmd);
2589 if (ret)
2590 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2591 else
2592 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2593 "succeeded, "
2594 "critical temperature is %d\n",
2595 priv->hw_params.ct_kill_threshold);
2596 }
2597}
2598
6d6a1afd
SZ		 2599static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2600{
2601 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2602 struct iwl_host_cmd cmd = {
2603 .id = CALIBRATION_CFG_CMD,
2604 .len = sizeof(struct iwl_calib_cfg_cmd),
2605 .data = &calib_cfg_cmd,
2606 };
2607
2608 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2609 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
7cb1b088 2610 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
6d6a1afd
SZ		 2611
2612 return iwl_send_cmd(priv, &cmd);
2613}
2614
2615
b481de9c 2616/**
4a4a9e81 2617 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2618 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2619 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2620 */
4a4a9e81 2621static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2622{
57aab75a 2623 int ret = 0;
246ed355 2624 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 2625
e1623446 2626 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2627
2628 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2629 /* We had an error bringing up the hardware, so take it
2630 * all the way back down so we can try again */
e1623446 2631 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2632 goto restart;
2633 }
2634
2635 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2636 * This is a paranoid check, because we would not have gotten the
2637 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2638 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2639 /* Runtime instruction load was bad;
2640 * take it all the way back down so we can try again */
e1623446 2641 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2642 goto restart;
2643 }
2644
57aab75a
TW		 2645 ret = priv->cfg->ops->lib->alive_notify(priv);
2646 if (ret) {
39aadf8c
WT		 2647 IWL_WARN(priv,
2648 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2649 goto restart;
2650 }
2651
6d6a1afd 2652
5b9f8cd3 2653 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2654 set_bit(STATUS_ALIVE, &priv->status);
2655
b74e31a9
WYG		 2656 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2657 /* Enable timer to monitor the driver queues */
2658 mod_timer(&priv->monitor_recover,
2659 jiffies +
7cb1b088
WYG		 2660 msecs_to_jiffies(
2661 priv->cfg->base_params->monitor_recover_period));
b74e31a9
WYG		 2662 }
2663
fee1247a 2664 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2665 return;
2666
bc795df1 2667 /* download priority table before any calibration request */
7cb1b088
WYG		 2668 if (priv->cfg->bt_params &&
2669 priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f
WYG		 2670 /* Configure Bluetooth device coexistence support */
2671 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2672 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2673 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2674 priv->cfg->ops->hcmd->send_bt_config(priv);
2675 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
a5901cbb 2676 iwlagn_send_prio_tbl(priv);
f7322f8f
WYG		 2677
2678 /* FIXME: w/a to force change uCode BT state machine */
2679 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2680 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2681 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2682 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2683 }
bc795df1
WYG		 2684 if (priv->hw_params.calib_rt_cfg)
2685 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2686
36d6825b 2687 ieee80211_wake_queues(priv->hw);
b481de9c 2688
470ab2dd 2689 priv->active_rate = IWL_RATES_MASK;
b481de9c 2690
2f748dec
WYG		 2691 /* Configure Tx antenna selection based on H/W config */
2692 if (priv->cfg->ops->hcmd->set_tx_ant)
2693 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2694
246ed355 2695 if (iwl_is_associated_ctx(ctx)) {
c1adf9fb 2696 struct iwl_rxon_cmd *active_rxon =
246ed355 2697 (struct iwl_rxon_cmd *)&ctx->active;
019fb97d 2698 /* apply any changes in staging */
246ed355 2699 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2700 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2701 } else {
d0fe478c 2702 struct iwl_rxon_context *tmp;
b481de9c 2703 /* Initialize our rx_config data */
d0fe478c
JB		 2704 for_each_context(priv, tmp)
2705 iwl_connection_init_rx_config(priv, tmp);
45823531
AK		 2706
2707 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 2708 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c
ZY		 2709 }
2710
7cb1b088
WYG		 2711 if (priv->cfg->bt_params &&
2712 !priv->cfg->bt_params->advanced_bt_coexist) {
aeb4a2ee
WYG		 2713 /* Configure Bluetooth device coexistence support */
2714 priv->cfg->ops->hcmd->send_bt_config(priv);
2715 }
b481de9c 2716
4a4a9e81
TW		 2717 iwl_reset_run_time_calib(priv);
2718
b481de9c 2719 /* Configure the adapter for unassociated operation */
246ed355 2720 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 2721
2722 /* At this point, the NIC is initialized and operational */
47f4a587 2723 iwl_rf_kill_ct_config(priv);
5a66926a 2724
e932a609 2725 iwl_leds_init(priv);
fe00b5a5 2726
e1623446 2727 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2728 set_bit(STATUS_READY, &priv->status);
5a66926a 2729 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2730
e312c24c 2731 iwl_power_update_mode(priv, true);
7e246191
RC		 2732 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2733
c46fbefa 2734
b481de9c
ZY		 2735 return;
2736
2737 restart:
2738 queue_work(priv->workqueue, &priv->restart);
2739}
2740
4e39317d 2741static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2742
5b9f8cd3 2743static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2744{
2745 unsigned long flags;
2746 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2747
e1623446 2748 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2749
d745d472
SG		 2750 iwl_scan_cancel_timeout(priv, 200);
2751
2752 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2753
b62177a0
SG		 2754 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2755 * to prevent rearm timer */
2756 if (priv->cfg->ops->lib->recover_from_tx_stall)
2757 del_timer_sync(&priv->monitor_recover);
2758
dcef732c 2759 iwl_clear_ucode_stations(priv, NULL);
a194e324 2760 iwl_dealloc_bcast_stations(priv);
db125c78 2761 iwl_clear_driver_stations(priv);
b481de9c 2762
a1174138 2763 /* reset BT coex data */
da5dbb97 2764 priv->bt_status = 0;
7cb1b088
WYG		 2765 if (priv->cfg->bt_params)
2766 priv->bt_traffic_load =
2767 priv->cfg->bt_params->bt_init_traffic_load;
2768 else
2769 priv->bt_traffic_load = 0;
a1174138 2770 priv->bt_sco_active = false;
bee008b7
WYG		 2771 priv->bt_full_concurrent = false;
2772 priv->bt_ci_compliance = 0;
a1174138 2773
b481de9c
ZY		 2774 /* Unblock any waiting calls */
2775 wake_up_interruptible_all(&priv->wait_command_queue);
2776
b481de9c
ZY		 2777 /* Wipe out the EXIT_PENDING status bit if we are not actually
2778 * exiting the module */
2779 if (!exit_pending)
2780 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2781
2782 /* stop and reset the on-board processor */
3395f6e9 2783 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2784
2785 /* tell the device to stop sending interrupts */
0359facc 2786 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2787 iwl_disable_interrupts(priv);
0359facc
MA		 2788 spin_unlock_irqrestore(&priv->lock, flags);
2789 iwl_synchronize_irq(priv);
b481de9c
ZY		 2790
2791 if (priv->mac80211_registered)
2792 ieee80211_stop_queues(priv->hw);
2793
5b9f8cd3 2794 /* If we have not previously called iwl_init() then
a60e77e5 2795 * clear all bits but the RF Kill bit and return */
fee1247a 2796 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2797 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2798 STATUS_RF_KILL_HW |
9788864e
RC		 2799 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2800 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2801 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2802 STATUS_EXIT_PENDING;
b481de9c
ZY		 2803 goto exit;
2804 }
2805
6da3a13e 2806 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2807 * bit and continue taking the NIC down. */
b481de9c
ZY		 2808 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2809 STATUS_RF_KILL_HW |
9788864e
RC		 2810 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2811 STATUS_GEO_CONFIGURED |
b481de9c 2812 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2813 STATUS_FW_ERROR |
2814 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2815 STATUS_EXIT_PENDING;
b481de9c 2816
ef850d7c 2817 /* device going down, Stop using ICT table */
e39fdee1
WYG		 2818 if (priv->cfg->ops->lib->isr_ops.disable)
2819 priv->cfg->ops->lib->isr_ops.disable(priv);
b481de9c 2820
74bcdb33 2821 iwlagn_txq_ctx_stop(priv);
54b81550 2822 iwlagn_rxq_stop(priv);
b481de9c 2823
309e731a
BC		 2824 /* Power-down device's busmaster DMA clocks */
2825 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2826 udelay(5);
2827
309e731a
BC		 2828 /* Make sure (redundant) we've released our request to stay awake */
2829 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2830
4d2ccdb9 2831 /* Stop the device, and put it in low power state */
14e8e4af 2832 iwl_apm_stop(priv);
4d2ccdb9 2833
b481de9c 2834 exit:
885ba202 2835 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c 2836
77834543 2837 dev_kfree_skb(priv->beacon_skb);
12e934dc 2838 priv->beacon_skb = NULL;
b481de9c
ZY		 2839
2840 /* clear out any free frames */
fcab423d 2841 iwl_clear_free_frames(priv);
b481de9c
ZY		 2842}
2843
5b9f8cd3 2844static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2845{
2846 mutex_lock(&priv->mutex);
5b9f8cd3 2847 __iwl_down(priv);
b481de9c 2848 mutex_unlock(&priv->mutex);
b24d22b1 2849
4e39317d 2850 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2851}
2852
086ed117
MA		 2853#define HW_READY_TIMEOUT (50)
2854
2855static int iwl_set_hw_ready(struct iwl_priv *priv)
2856{
2857 int ret = 0;
2858
2859 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2860 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2861
2862 /* See if we got it */
2863 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2864 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2865 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2866 HW_READY_TIMEOUT);
2867 if (ret != -ETIMEDOUT)
2868 priv->hw_ready = true;
2869 else
2870 priv->hw_ready = false;
2871
2872 IWL_DEBUG_INFO(priv, "hardware %s\n",
2873 (priv->hw_ready == 1) ? "ready" : "not ready");
2874 return ret;
2875}
2876
2877static int iwl_prepare_card_hw(struct iwl_priv *priv)
2878{
2879 int ret = 0;
2880
91dd6c27 2881 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2882
3354a0f6
MA		 2883 ret = iwl_set_hw_ready(priv);
2884 if (priv->hw_ready)
2885 return ret;
2886
2887 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 2888 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2889 CSR_HW_IF_CONFIG_REG_PREPARE);
2890
2891 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2892 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2893 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2894
3354a0f6 2895 /* HW should be ready by now, check again. */
086ed117
MA		 2896 if (ret != -ETIMEDOUT)
2897 iwl_set_hw_ready(priv);
2898
2899 return ret;
2900}
2901
b481de9c
ZY		 2902#define MAX_HW_RESTARTS 5
2903
5b9f8cd3 2904static int __iwl_up(struct iwl_priv *priv)
b481de9c 2905{
a194e324 2906 struct iwl_rxon_context *ctx;
57aab75a
TW		 2907 int i;
2908 int ret;
b481de9c
ZY		 2909
2910 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2911 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 2912 return -EIO;
2913 }
2914
e903fbd4 2915 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2916 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 2917 return -EIO;
2918 }
2919
a194e324 2920 for_each_context(priv, ctx) {
a30e3112 2921 ret = iwlagn_alloc_bcast_station(priv, ctx);
a194e324
JB		 2922 if (ret) {
2923 iwl_dealloc_bcast_stations(priv);
2924 return ret;
2925 }
2926 }
2c810ccd 2927
086ed117
MA		 2928 iwl_prepare_card_hw(priv);
2929
2930 if (!priv->hw_ready) {
2931 IWL_WARN(priv, "Exit HW not ready\n");
2932 return -EIO;
2933 }
2934
e655b9f0 2935 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2936 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2937 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2938 else
e655b9f0 2939 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2940
c1842d61 2941 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 2942 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2943
5b9f8cd3 2944 iwl_enable_interrupts(priv);
a60e77e5 2945 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2946 return 0;
b481de9c
ZY		 2947 }
2948
3395f6e9 2949 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2950
13bb9483 2951 /* must be initialised before iwl_hw_nic_init */
751ca305
JB		 2952 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2953 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2954 else
2955 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
13bb9483 2956
74bcdb33 2957 ret = iwlagn_hw_nic_init(priv);
57aab75a 2958 if (ret) {
15b1687c 2959 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2960 return ret;
b481de9c
ZY		 2961 }
2962
2963 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2964 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2965 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 2966 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2967
2968 /* clear (again), then enable host interrupts */
3395f6e9 2969 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2970 iwl_enable_interrupts(priv);
b481de9c
ZY		 2971
2972 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2973 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2974 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2975
2976 /* Copy original ucode data image from disk into backup cache.
2977 * This will be used to initialize the on-board processor's
2978 * data SRAM for a clean start when the runtime program first loads. */
2979 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2980 priv->ucode_data.len);
b481de9c 2981
b481de9c
ZY		 2982 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2983
b481de9c
ZY		 2984 /* load bootstrap state machine,
2985 * load bootstrap program into processor's memory,
2986 * prepare to load the "initialize" uCode */
57aab75a 2987 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2988
57aab75a 2989 if (ret) {
15b1687c
WT		 2990 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2991 ret);
b481de9c
ZY		 2992 continue;
2993 }
2994
2995 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2996 iwl_nic_start(priv);
b481de9c 2997
e1623446 2998 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 2999
3000 return 0;
3001 }
3002
3003 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 3004 __iwl_down(priv);
64e72c3e 3005 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 3006
3007 /* tried to restart and config the device for as long as our
3008 * patience could withstand */
15b1687c 3009 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 3010 return -EIO;
3011}
3012
3013
3014/*****************************************************************************
3015 *
3016 * Workqueue callbacks
3017 *
3018 *****************************************************************************/
3019
4a4a9e81 3020static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 3021{
c79dd5b5
TW		 3022 struct iwl_priv *priv =
3023 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 3024
3025 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3026 return;
3027
3028 mutex_lock(&priv->mutex);
f3ccc08c 3029 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 3030 mutex_unlock(&priv->mutex);
3031}
3032
4a4a9e81 3033static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 3034{
c79dd5b5
TW		 3035 struct iwl_priv *priv =
3036 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 3037
3038 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3039 return;
3040
258c44a0 3041 /* enable dram interrupt */
e39fdee1
WYG		 3042 if (priv->cfg->ops->lib->isr_ops.reset)
3043 priv->cfg->ops->lib->isr_ops.reset(priv);
258c44a0 3044
b481de9c 3045 mutex_lock(&priv->mutex);
4a4a9e81 3046 iwl_alive_start(priv);
b481de9c
ZY		 3047 mutex_unlock(&priv->mutex);
3048}
3049
16e727e8
EG		 3050static void iwl_bg_run_time_calib_work(struct work_struct *work)
3051{
3052 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3053 run_time_calib_work);
3054
3055 mutex_lock(&priv->mutex);
3056
3057 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3058 test_bit(STATUS_SCANNING, &priv->status)) {
3059 mutex_unlock(&priv->mutex);
3060 return;
3061 }
3062
3063 if (priv->start_calib) {
7cb1b088
WYG		 3064 if (priv->cfg->bt_params &&
3065 priv->cfg->bt_params->bt_statistics) {
7980fba5
WYG		 3066 iwl_chain_noise_calibration(priv,
3067 (void *)&priv->_agn.statistics_bt);
3068 iwl_sensitivity_calibration(priv,
3069 (void *)&priv->_agn.statistics_bt);
3070 } else {
3071 iwl_chain_noise_calibration(priv,
3072 (void *)&priv->_agn.statistics);
3073 iwl_sensitivity_calibration(priv,
3074 (void *)&priv->_agn.statistics);
3075 }
16e727e8
EG		 3076 }
3077
3078 mutex_unlock(&priv->mutex);
16e727e8
EG		 3079}
3080
5b9f8cd3 3081static void iwl_bg_restart(struct work_struct *data)
b481de9c 3082{
c79dd5b5 3083 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 3084
3085 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3086 return;
3087
19cc1087 3088 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
8bd413e6 3089 struct iwl_rxon_context *ctx;
bee008b7
WYG		 3090 bool bt_sco, bt_full_concurrent;
3091 u8 bt_ci_compliance;
511b082d 3092 u8 bt_load;
da5dbb97 3093 u8 bt_status;
511b082d 3094
19cc1087 3095 mutex_lock(&priv->mutex);
8bd413e6
JB		 3096 for_each_context(priv, ctx)
3097 ctx->vif = NULL;
19cc1087 3098 priv->is_open = 0;
511b082d
JB		 3099
3100 /*
3101 * __iwl_down() will clear the BT status variables,
3102 * which is correct, but when we restart we really
3103 * want to keep them so restore them afterwards.
3104 *
3105 * The restart process will later pick them up and
3106 * re-configure the hw when we reconfigure the BT
3107 * command.
3108 */
3109 bt_sco = priv->bt_sco_active;
bee008b7
WYG		 3110 bt_full_concurrent = priv->bt_full_concurrent;
3111 bt_ci_compliance = priv->bt_ci_compliance;
511b082d 3112 bt_load = priv->bt_traffic_load;
da5dbb97 3113 bt_status = priv->bt_status;
511b082d 3114
a1174138 3115 __iwl_down(priv);
511b082d
JB		 3116
3117 priv->bt_sco_active = bt_sco;
bee008b7
WYG		 3118 priv->bt_full_concurrent = bt_full_concurrent;
3119 priv->bt_ci_compliance = bt_ci_compliance;
511b082d 3120 priv->bt_traffic_load = bt_load;
da5dbb97 3121 priv->bt_status = bt_status;
511b082d 3122
19cc1087 3123 mutex_unlock(&priv->mutex);
a1174138 3124 iwl_cancel_deferred_work(priv);
19cc1087
JB		 3125 ieee80211_restart_hw(priv->hw);
3126 } else {
3127 iwl_down(priv);
80676518
JB		 3128
3129 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3130 return;
3131
3132 mutex_lock(&priv->mutex);
3133 __iwl_up(priv);
3134 mutex_unlock(&priv->mutex);
19cc1087 3135 }
b481de9c
ZY		 3136}
3137
5b9f8cd3 3138static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3139{
c79dd5b5
TW		 3140 struct iwl_priv *priv =
3141 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3142
3143 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3144 return;
3145
3146 mutex_lock(&priv->mutex);
54b81550 3147 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3148 mutex_unlock(&priv->mutex);
3149}
3150
b481de9c
ZY		 3151/*****************************************************************************
3152 *
3153 * mac80211 entry point functions
3154 *
3155 *****************************************************************************/
3156
154b25ce 3157#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3158
f0b6e2e8
RC		 3159/*
3160 * Not a mac80211 entry point function, but it fits in with all the
3161 * other mac80211 functions grouped here.
3162 */
dd7a2509
JB		 3163static int iwl_mac_setup_register(struct iwl_priv *priv,
3164 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3165{
3166 int ret;
3167 struct ieee80211_hw *hw = priv->hw;
d0fe478c
JB		 3168 struct iwl_rxon_context *ctx;
3169
f0b6e2e8
RC		 3170 hw->rate_control_algorithm = "iwl-agn-rs";
3171
3172 /* Tell mac80211 our characteristics */
3173 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8 3174 IEEE80211_HW_AMPDU_AGGREGATION |
2491fa42 3175 IEEE80211_HW_NEED_DTIM_PERIOD |
f0b6e2e8
RC		 3176 IEEE80211_HW_SPECTRUM_MGMT;
3177
7cb1b088 3178 if (!priv->cfg->base_params->broken_powersave)
f0b6e2e8
RC		 3179 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3180 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3181
ba37a3d0
JB		 3182 if (priv->cfg->sku & IWL_SKU_N)
3183 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3184 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3185
8d9698b3 3186 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3187 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3188
d0fe478c
JB		 3189 for_each_context(priv, ctx) {
3190 hw->wiphy->interface_modes |= ctx->interface_modes;
3191 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3192 }
f0b6e2e8 3193
f6c8f152 3194 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3195 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3196
3197 /*
3198 * For now, disable PS by default because it affects
3199 * RX performance significantly.
3200 */
5be83de5 3201 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3202
1382c71c 3203 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3204 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3205 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3206
3207 /* Default value; 4 EDCA QOS priorities */
3208 hw->queues = 4;
3209
3210 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3211
3212 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3213 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3214 &priv->bands[IEEE80211_BAND_2GHZ];
3215 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3216 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3217 &priv->bands[IEEE80211_BAND_5GHZ];
3218
3219 ret = ieee80211_register_hw(priv->hw);
3220 if (ret) {
3221 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3222 return ret;
3223 }
3224 priv->mac80211_registered = 1;
3225
3226 return 0;
3227}
3228
3229
2295c66b 3230int iwlagn_mac_start(struct ieee80211_hw *hw)
b481de9c 3231{
c79dd5b5 3232 struct iwl_priv *priv = hw->priv;
5a66926a 3233 int ret;
b481de9c 3234
e1623446 3235 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3236
3237 /* we should be verifying the device is ready to be opened */
3238 mutex_lock(&priv->mutex);
5b9f8cd3 3239 ret = __iwl_up(priv);
b481de9c 3240 mutex_unlock(&priv->mutex);
5a66926a 3241
e655b9f0 3242 if (ret)
6cd0b1cb 3243 return ret;
e655b9f0 3244
c1842d61
TW		 3245 if (iwl_is_rfkill(priv))
3246 goto out;
3247
e1623446 3248 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3249
fe9b6b72 3250 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3251 * mac80211 will not be run successfully. */
154b25ce
EG		 3252 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3253 test_bit(STATUS_READY, &priv->status),
3254 UCODE_READY_TIMEOUT);
3255 if (!ret) {
3256 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3257 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3258 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3259 return -ETIMEDOUT;
5a66926a 3260 }
fe9b6b72 3261 }
0a078ffa 3262
e932a609
JB		 3263 iwl_led_start(priv);
3264
c1842d61 3265out:
0a078ffa 3266 priv->is_open = 1;
e1623446 3267 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3268 return 0;
3269}
3270
2295c66b 3271void iwlagn_mac_stop(struct ieee80211_hw *hw)
b481de9c 3272{
c79dd5b5 3273 struct iwl_priv *priv = hw->priv;
b481de9c 3274
e1623446 3275 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3276
19cc1087 3277 if (!priv->is_open)
e655b9f0 3278 return;
e655b9f0 3279
b481de9c 3280 priv->is_open = 0;
5a66926a 3281
5b9f8cd3 3282 iwl_down(priv);
5a66926a
ZY		 3283
3284 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3285
3286 /* enable interrupts again in order to receive rfkill changes */
3287 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3288 iwl_enable_interrupts(priv);
948c171c 3289
e1623446 3290 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3291}
3292
2295c66b 3293int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3294{
c79dd5b5 3295 struct iwl_priv *priv = hw->priv;
b481de9c 3296
e1623446 3297 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3298
e1623446 3299 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3300 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3301
74bcdb33 3302 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3303 dev_kfree_skb_any(skb);
3304
e1623446 3305 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3306 return NETDEV_TX_OK;
b481de9c
ZY		 3307}
3308
2295c66b
JB		 3309void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3310 struct ieee80211_vif *vif,
3311 struct ieee80211_key_conf *keyconf,
3312 struct ieee80211_sta *sta,
3313 u32 iv32, u16 *phase1key)
ab885f8c 3314{
9f58671e 3315 struct iwl_priv *priv = hw->priv;
a194e324
JB		 3316 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3317
e1623446 3318 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3319
a194e324 3320 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
b3fbdcf4 3321 iv32, phase1key);
ab885f8c 3322
e1623446 3323 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3324}
3325
2295c66b
JB		 3326int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3327 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3328 struct ieee80211_key_conf *key)
b481de9c 3329{
c79dd5b5 3330 struct iwl_priv *priv = hw->priv;
a194e324 3331 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
c10afb6e 3332 struct iwl_rxon_context *ctx = vif_priv->ctx;
42986796
WT		 3333 int ret;
3334 u8 sta_id;
3335 bool is_default_wep_key = false;
b481de9c 3336
e1623446 3337 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3338
90e8e424 3339 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3340 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3341 return -EOPNOTSUPP;
3342 }
b481de9c 3343
a194e324 3344 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
0af8bcae
JB		 3345 if (sta_id == IWL_INVALID_STATION)
3346 return -EINVAL;
b481de9c 3347
6974e363 3348 mutex_lock(&priv->mutex);
2a421b91 3349 iwl_scan_cancel_timeout(priv, 100);
6974e363 3350
a90178fa
JB		 3351 /*
3352 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3353 * so far, we are in legacy wep mode (group key only), otherwise we are
3354 * in 1X mode.
a90178fa
JB		 3355 * In legacy wep mode, we use another host command to the uCode.
3356 */
97359d12
JB		 3357 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3358 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 3359 !sta) {
6974e363 3360 if (cmd == SET_KEY)
c10afb6e 3361 is_default_wep_key = !ctx->key_mapping_keys;
6974e363 3362 else
ccc038ab
EG		 3363 is_default_wep_key =
3364 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3365 }
052c4b9f 3366
b481de9c 3367 switch (cmd) {
deb09c43 3368 case SET_KEY:
6974e363 3369 if (is_default_wep_key)
2995bafa 3370 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
deb09c43 3371 else
a194e324
JB		 3372 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3373 key, sta_id);
deb09c43 3374
e1623446 3375 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3376 break;
3377 case DISABLE_KEY:
6974e363 3378 if (is_default_wep_key)
c10afb6e 3379 ret = iwl_remove_default_wep_key(priv, ctx, key);
deb09c43 3380 else
c10afb6e 3381 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
deb09c43 3382
e1623446 3383 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3384 break;
3385 default:
deb09c43 3386 ret = -EINVAL;
b481de9c
ZY		 3387 }
3388
72e15d71 3389 mutex_unlock(&priv->mutex);
e1623446 3390 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3391
deb09c43 3392 return ret;
b481de9c
ZY		 3393}
3394
2295c66b
JB		 3395int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3396 struct ieee80211_vif *vif,
3397 enum ieee80211_ampdu_mlme_action action,
3398 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3399{
3400 struct iwl_priv *priv = hw->priv;
4620fefa 3401 int ret = -EINVAL;
d783b061 3402
e1623446 3403 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3404 sta->addr, tid);
d783b061
TW		 3405
3406 if (!(priv->cfg->sku & IWL_SKU_N))
3407 return -EACCES;
3408
4620fefa
JB		 3409 mutex_lock(&priv->mutex);
3410
d783b061
TW		 3411 switch (action) {
3412 case IEEE80211_AMPDU_RX_START:
e1623446 3413 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3414 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3415 break;
d783b061 3416 case IEEE80211_AMPDU_RX_STOP:
e1623446 3417 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3418 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3419 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3420 ret = 0;
3421 break;
d783b061 3422 case IEEE80211_AMPDU_TX_START:
e1623446 3423 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3424 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3425 if (ret == 0) {
3426 priv->_agn.agg_tids_count++;
3427 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3428 priv->_agn.agg_tids_count);
3429 }
4620fefa 3430 break;
d783b061 3431 case IEEE80211_AMPDU_TX_STOP:
e1623446 3432 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3433 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3434 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3435 priv->_agn.agg_tids_count--;
3436 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3437 priv->_agn.agg_tids_count);
3438 }
5c2207c6 3439 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 3440 ret = 0;
7cb1b088
WYG		 3441 if (priv->cfg->ht_params &&
3442 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 3443 struct iwl_station_priv *sta_priv =
3444 (void *) sta->drv_priv;
3445 /*
3446 * switch off RTS/CTS if it was previously enabled
3447 */
3448
3449 sta_priv->lq_sta.lq.general_params.flags &=
3450 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3451 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3452 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
94597ab2 3453 }
4620fefa 3454 break;
f0527971 3455 case IEEE80211_AMPDU_TX_OPERATIONAL:
7cb1b088
WYG		 3456 if (priv->cfg->ht_params &&
3457 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 3458 struct iwl_station_priv *sta_priv =
3459 (void *) sta->drv_priv;
3460
cfecc6b4
WYG		 3461 /*
3462 * switch to RTS/CTS if it is the prefer protection
3463 * method for HT traffic
3464 */
94597ab2
JB		 3465
3466 sta_priv->lq_sta.lq.general_params.flags |=
3467 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3468 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3469 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
cfecc6b4
WYG		 3470 }
3471 ret = 0;
d783b061
TW		 3472 break;
3473 }
4620fefa
JB		 3474 mutex_unlock(&priv->mutex);
3475
3476 return ret;
d783b061 3477}
9f58671e 3478
2295c66b
JB		 3479int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3480 struct ieee80211_vif *vif,
3481 struct ieee80211_sta *sta)
fe6b23dd
RC		 3482{
3483 struct iwl_priv *priv = hw->priv;
3484 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
a194e324 3485 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
eafdfbd3 3486 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3487 int ret;
3488 u8 sta_id;
3489
3490 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3491 sta->addr);
da5ae1cf
RC		 3492 mutex_lock(&priv->mutex);
3493 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3494 sta->addr);
3495 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3496
3497 atomic_set(&sta_priv->pending_frames, 0);
3498 if (vif->type == NL80211_IFTYPE_AP)
3499 sta_priv->client = true;
3500
a194e324 3501 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
238d781d 3502 is_ap, sta, &sta_id);
fe6b23dd
RC		 3503 if (ret) {
3504 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3505 sta->addr, ret);
3506 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3507 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3508 return ret;
3509 }
3510
fd1af15d
JB		 3511 sta_priv->common.sta_id = sta_id;
3512
fe6b23dd 3513 /* Initialize rate scaling */
91dd6c27 3514 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3515 sta->addr);
3516 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3517 mutex_unlock(&priv->mutex);
fe6b23dd 3518
fd1af15d 3519 return 0;
fe6b23dd
RC		 3520}
3521
2295c66b
JB		 3522void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3523 struct ieee80211_channel_switch *ch_switch)
79d07325
WYG		 3524{
3525 struct iwl_priv *priv = hw->priv;
3526 const struct iwl_channel_info *ch_info;
3527 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 3528 struct ieee80211_channel *channel = ch_switch->channel;
79d07325 3529 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
246ed355
JB		 3530 /*
3531 * MULTI-FIXME
3532 * When we add support for multiple interfaces, we need to
3533 * revisit this. The channel switch command in the device
3534 * only affects the BSS context, but what does that really
3535 * mean? And what if we get a CSA on the second interface?
3536 * This needs a lot of work.
3537 */
3538 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
79d07325
WYG		 3539 u16 ch;
3540 unsigned long flags = 0;
3541
3542 IWL_DEBUG_MAC80211(priv, "enter\n");
3543
3544 if (iwl_is_rfkill(priv))
3545 goto out_exit;
3546
3547 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3548 test_bit(STATUS_SCANNING, &priv->status))
3549 goto out_exit;
3550
246ed355 3551 if (!iwl_is_associated_ctx(ctx))
79d07325
WYG		 3552 goto out_exit;
3553
3554 /* channel switch in progress */
3555 if (priv->switch_rxon.switch_in_progress == true)
3556 goto out_exit;
3557
3558 mutex_lock(&priv->mutex);
3559 if (priv->cfg->ops->lib->set_channel_switch) {
3560
aa2dc6b5 3561 ch = channel->hw_value;
246ed355 3562 if (le16_to_cpu(ctx->active.channel) != ch) {
79d07325 3563 ch_info = iwl_get_channel_info(priv,
aa2dc6b5 3564 channel->band,
79d07325
WYG		 3565 ch);
3566 if (!is_channel_valid(ch_info)) {
3567 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3568 goto out;
3569 }
3570 spin_lock_irqsave(&priv->lock, flags);
3571
3572 priv->current_ht_config.smps = conf->smps_mode;
3573
3574 /* Configure HT40 channels */
7e6a5886
JB		 3575 ctx->ht.enabled = conf_is_ht(conf);
3576 if (ctx->ht.enabled) {
79d07325 3577 if (conf_is_ht40_minus(conf)) {
7e6a5886 3578 ctx->ht.extension_chan_offset =
79d07325 3579 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
7e6a5886 3580 ctx->ht.is_40mhz = true;
79d07325 3581 } else if (conf_is_ht40_plus(conf)) {
7e6a5886 3582 ctx->ht.extension_chan_offset =
79d07325 3583 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
7e6a5886 3584 ctx->ht.is_40mhz = true;
79d07325 3585 } else {
7e6a5886 3586 ctx->ht.extension_chan_offset =
79d07325 3587 IEEE80211_HT_PARAM_CHA_SEC_NONE;
7e6a5886 3588 ctx->ht.is_40mhz = false;
79d07325
WYG		 3589 }
3590 } else
7e6a5886 3591 ctx->ht.is_40mhz = false;
79d07325 3592
246ed355
JB		 3593 if ((le16_to_cpu(ctx->staging.channel) != ch))
3594 ctx->staging.flags = 0;
79d07325 3595
246ed355 3596 iwl_set_rxon_channel(priv, channel, ctx);
79d07325 3597 iwl_set_rxon_ht(priv, ht_conf);
246ed355 3598 iwl_set_flags_for_band(priv, ctx, channel->band,
8bd413e6 3599 ctx->vif);
79d07325
WYG		 3600 spin_unlock_irqrestore(&priv->lock, flags);
3601
3602 iwl_set_rate(priv);
3603 /*
3604 * at this point, staging_rxon has the
3605 * configuration for channel switch
3606 */
3607 if (priv->cfg->ops->lib->set_channel_switch(priv,
3608 ch_switch))
3609 priv->switch_rxon.switch_in_progress = false;
3610 }
3611 }
3612out:
3613 mutex_unlock(&priv->mutex);
3614out_exit:
3615 if (!priv->switch_rxon.switch_in_progress)
8bd413e6 3616 ieee80211_chswitch_done(ctx->vif, false);
79d07325
WYG		 3617 IWL_DEBUG_MAC80211(priv, "leave\n");
3618}
3619
2295c66b
JB		 3620void iwlagn_configure_filter(struct ieee80211_hw *hw,
3621 unsigned int changed_flags,
3622 unsigned int *total_flags,
3623 u64 multicast)
8b8ab9d5
JB		 3624{
3625 struct iwl_priv *priv = hw->priv;
3626 __le32 filter_or = 0, filter_nand = 0;
246ed355 3627 struct iwl_rxon_context *ctx;
8b8ab9d5
JB		 3628
3629#define CHK(test, flag) do { \
3630 if (*total_flags & (test)) \
3631 filter_or |= (flag); \
3632 else \
3633 filter_nand |= (flag); \
3634 } while (0)
3635
3636 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3637 changed_flags, *total_flags);
3638
3639 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3640 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3641 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3642
3643#undef CHK
3644
3645 mutex_lock(&priv->mutex);
3646
246ed355
JB		 3647 for_each_context(priv, ctx) {
3648 ctx->staging.filter_flags &= ~filter_nand;
3649 ctx->staging.filter_flags |= filter_or;
749ff4ef
SG		 3650
3651 /*
3652 * Not committing directly because hardware can perform a scan,
3653 * but we'll eventually commit the filter flags change anyway.
3654 */
246ed355 3655 }
8b8ab9d5
JB		 3656
3657 mutex_unlock(&priv->mutex);
3658
3659 /*
3660 * Receiving all multicast frames is always enabled by the
3661 * default flags setup in iwl_connection_init_rx_config()
3662 * since we currently do not support programming multicast
3663 * filters into the device.
3664 */
3665 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3666 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3667}
3668
2295c66b 3669void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
716c74b0
WYG		 3670{
3671 struct iwl_priv *priv = hw->priv;
3672
3673 mutex_lock(&priv->mutex);
3674 IWL_DEBUG_MAC80211(priv, "enter\n");
3675
3676 /* do not support "flush" */
3677 if (!priv->cfg->ops->lib->txfifo_flush)
3678 goto done;
3679
3680 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3681 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3682 goto done;
3683 }
3684 if (iwl_is_rfkill(priv)) {
3685 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3686 goto done;
3687 }
3688
3689 /*
3690 * mac80211 will not push any more frames for transmit
3691 * until the flush is completed
3692 */
3693 if (drop) {
3694 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3695 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3696 IWL_ERR(priv, "flush request fail\n");
3697 goto done;
3698 }
3699 }
3700 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3701 iwlagn_wait_tx_queue_empty(priv);
3702done:
3703 mutex_unlock(&priv->mutex);
3704 IWL_DEBUG_MAC80211(priv, "leave\n");
3705}
3706
b481de9c
ZY		 3707/*****************************************************************************
3708 *
3709 * driver setup and teardown
3710 *
3711 *****************************************************************************/
3712
4e39317d 3713static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3714{
d21050c7 3715 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 3716
3717 init_waitqueue_head(&priv->wait_command_queue);
3718
5b9f8cd3
EG		 3719 INIT_WORK(&priv->restart, iwl_bg_restart);
3720 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3721 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3722 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 3723 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 3724 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 3725 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4a4a9e81
TW		 3726 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3727 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3728
2a421b91 3729 iwl_setup_scan_deferred_work(priv);
bb8c093b 3730
4e39317d
EG		 3731 if (priv->cfg->ops->lib->setup_deferred_work)
3732 priv->cfg->ops->lib->setup_deferred_work(priv);
3733
3734 init_timer(&priv->statistics_periodic);
3735 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3736 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3737
a9e1cb6a
WYG		 3738 init_timer(&priv->ucode_trace);
3739 priv->ucode_trace.data = (unsigned long)priv;
3740 priv->ucode_trace.function = iwl_bg_ucode_trace;
3741
b74e31a9
WYG		 3742 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3743 init_timer(&priv->monitor_recover);
3744 priv->monitor_recover.data = (unsigned long)priv;
3745 priv->monitor_recover.function =
3746 priv->cfg->ops->lib->recover_from_tx_stall;
3747 }
3748
7cb1b088 3749 if (!priv->cfg->base_params->use_isr_legacy)
ef850d7c
MA		 3750 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3751 iwl_irq_tasklet, (unsigned long)priv);
3752 else
3753 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3754 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 3755}
3756
4e39317d 3757static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3758{
4e39317d
EG		 3759 if (priv->cfg->ops->lib->cancel_deferred_work)
3760 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3761
3ae6a054 3762 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3763 cancel_delayed_work(&priv->alive_start);
815e629b 3764 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 3765 cancel_work_sync(&priv->beacon_update);
e7e16b90
SG		 3766
3767 iwl_cancel_scan_deferred_work(priv);
3768
bee008b7 3769 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 3770 cancel_work_sync(&priv->bt_runtime_config);
e7e16b90 3771
4e39317d 3772 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3773 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY		 3774}
3775
89f186a8
RC		 3776static void iwl_init_hw_rates(struct iwl_priv *priv,
3777 struct ieee80211_rate *rates)
3778{
3779 int i;
3780
3781 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3782 rates[i].bitrate = iwl_rates[i].ieee * 5;
3783 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3784 rates[i].hw_value_short = i;
3785 rates[i].flags = 0;
3786 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3787 /*
3788 * If CCK != 1M then set short preamble rate flag.
3789 */
3790 rates[i].flags |=
3791 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3792 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3793 }
3794 }
3795}
3796
3797static int iwl_init_drv(struct iwl_priv *priv)
3798{
3799 int ret;
3800
89f186a8
RC		 3801 spin_lock_init(&priv->sta_lock);
3802 spin_lock_init(&priv->hcmd_lock);
3803
3804 INIT_LIST_HEAD(&priv->free_frames);
3805
3806 mutex_init(&priv->mutex);
d2dfe6df 3807 mutex_init(&priv->sync_cmd_mutex);
89f186a8 3808
89f186a8
RC		 3809 priv->ieee_channels = NULL;
3810 priv->ieee_rates = NULL;
3811 priv->band = IEEE80211_BAND_2GHZ;
3812
3813 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3814 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3815 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3816 priv->_agn.agg_tids_count = 0;
89f186a8 3817
8a472da4
WYG		 3818 /* initialize force reset */
3819 priv->force_reset[IWL_RF_RESET].reset_duration =
3820 IWL_DELAY_NEXT_FORCE_RF_RESET;
3821 priv->force_reset[IWL_FW_RESET].reset_duration =
3822 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 3823
3824 /* Choose which receivers/antennas to use */
3825 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355
JB		 3826 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3827 &priv->contexts[IWL_RXON_CTX_BSS]);
89f186a8
RC		 3828
3829 iwl_init_scan_params(priv);
3830
22bf59a0 3831 /* init bt coex */
7cb1b088
WYG		 3832 if (priv->cfg->bt_params &&
3833 priv->cfg->bt_params->advanced_bt_coexist) {
b6e116e8
WYG		 3834 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3835 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3836 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG		 3837 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3838 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3839 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
22bf59a0
WYG		 3840 }
3841
89f186a8
RC		 3842 /* Set the tx_power_user_lmt to the lowest power level
3843 * this value will get overwritten by channel max power avg
3844 * from eeprom */
b744cb79 3845 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
a25a66ac 3846 priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 3847
3848 ret = iwl_init_channel_map(priv);
3849 if (ret) {
3850 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3851 goto err;
3852 }
3853
3854 ret = iwlcore_init_geos(priv);
3855 if (ret) {
3856 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3857 goto err_free_channel_map;
3858 }
3859 iwl_init_hw_rates(priv, priv->ieee_rates);
3860
3861 return 0;
3862
3863err_free_channel_map:
3864 iwl_free_channel_map(priv);
3865err:
3866 return ret;
3867}
3868
3869static void iwl_uninit_drv(struct iwl_priv *priv)
3870{
3871 iwl_calib_free_results(priv);
3872 iwlcore_free_geos(priv);
3873 iwl_free_channel_map(priv);
811ecc99 3874 kfree(priv->scan_cmd);
89f186a8
RC		 3875}
3876
ae79d23d 3877#ifdef CONFIG_IWL5000
dc21b545 3878struct ieee80211_ops iwlagn_hw_ops = {
2295c66b
JB		 3879 .tx = iwlagn_mac_tx,
3880 .start = iwlagn_mac_start,
3881 .stop = iwlagn_mac_stop,
5b9f8cd3
EG		 3882 .add_interface = iwl_mac_add_interface,
3883 .remove_interface = iwl_mac_remove_interface,
d4daaea6 3884 .change_interface = iwl_mac_change_interface,
2295c66b 3885 .config = iwlagn_mac_config,
8b8ab9d5 3886 .configure_filter = iwlagn_configure_filter,
2295c66b
JB		 3887 .set_key = iwlagn_mac_set_key,
3888 .update_tkip_key = iwlagn_mac_update_tkip_key,
5b9f8cd3 3889 .conf_tx = iwl_mac_conf_tx,
2295c66b
JB		 3890 .bss_info_changed = iwlagn_bss_info_changed,
3891 .ampdu_action = iwlagn_mac_ampdu_action,
6ab10ff8 3892 .hw_scan = iwl_mac_hw_scan,
2295c66b 3893 .sta_notify = iwlagn_mac_sta_notify,
fe6b23dd
RC		 3894 .sta_add = iwlagn_mac_sta_add,
3895 .sta_remove = iwl_mac_sta_remove,
2295c66b
JB		 3896 .channel_switch = iwlagn_mac_channel_switch,
3897 .flush = iwlagn_mac_flush,
a85d7cca 3898 .tx_last_beacon = iwl_mac_tx_last_beacon,
b481de9c 3899};
ae79d23d 3900#endif
b481de9c 3901
3867fe04
WYG		 3902static void iwl_hw_detect(struct iwl_priv *priv)
3903{
3904 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3905 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3906 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
49ded76b 3907 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3867fe04
WYG		 3908}
3909
07d4f1ad
WYG		 3910static int iwl_set_hw_params(struct iwl_priv *priv)
3911{
3912 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3913 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3914 if (priv->cfg->mod_params->amsdu_size_8K)
3915 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3916 else
3917 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3918
3919 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3920
3921 if (priv->cfg->mod_params->disable_11n)
3922 priv->cfg->sku &= ~IWL_SKU_N;
3923
3924 /* Device-specific setup */
3925 return priv->cfg->ops->lib->set_hw_params(priv);
3926}
3927
e72f368b
JB		 3928static const u8 iwlagn_bss_ac_to_fifo[] = {
3929 IWL_TX_FIFO_VO,
3930 IWL_TX_FIFO_VI,
3931 IWL_TX_FIFO_BE,
3932 IWL_TX_FIFO_BK,
3933};
3934
3935static const u8 iwlagn_bss_ac_to_queue[] = {
3936 0, 1, 2, 3,
3937};
3938
3939static const u8 iwlagn_pan_ac_to_fifo[] = {
3940 IWL_TX_FIFO_VO_IPAN,
3941 IWL_TX_FIFO_VI_IPAN,
3942 IWL_TX_FIFO_BE_IPAN,
3943 IWL_TX_FIFO_BK_IPAN,
3944};
3945
3946static const u8 iwlagn_pan_ac_to_queue[] = {
3947 7, 6, 5, 4,
3948};
3949
5b9f8cd3 3950static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c 3951{
246ed355 3952 int err = 0, i;
c79dd5b5 3953 struct iwl_priv *priv;
b481de9c 3954 struct ieee80211_hw *hw;
82b9a121 3955 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3956 unsigned long flags;
c6fa17ed 3957 u16 pci_cmd, num_mac;
b481de9c 3958
316c30d9
AK		 3959 /************************
3960 * 1. Allocating HW data
3961 ************************/
3962
6440adb5
CB		 3963 /* Disabling hardware scan means that mac80211 will perform scans
3964 * "the hard way", rather than using device's scan. */
1ea87396 3965 if (cfg->mod_params->disable_hw_scan) {
72645eff
WYG		 3966 dev_printk(KERN_DEBUG, &(pdev->dev),
3967 "sw scan support is deprecated\n");
ae79d23d 3968#ifdef CONFIG_IWL5000
dc21b545 3969 iwlagn_hw_ops.hw_scan = NULL;
ae79d23d 3970#endif
2295c66b
JB		 3971#ifdef CONFIG_IWL4965
3972 iwl4965_hw_ops.hw_scan = NULL;
3973#endif
b481de9c
ZY		 3974 }
3975
dc21b545 3976 hw = iwl_alloc_all(cfg);
1d0a082d 3977 if (!hw) {
b481de9c
ZY		 3978 err = -ENOMEM;
3979 goto out;
3980 }
1d0a082d
AK		 3981 priv = hw->priv;
3982 /* At this point both hw and priv are allocated. */
3983
246ed355
JB		 3984 /*
3985 * The default context is always valid,
3986 * more may be discovered when firmware
3987 * is loaded.
3988 */
3989 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3990
3991 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3992 priv->contexts[i].ctxid = i;
3993
763cc3bf
JB		 3994 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3995 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
8f2d3d2a
JB		 3996 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3997 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3998 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 3999 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 4000 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
c10afb6e 4001 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
e72f368b
JB		 4002 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4003 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
d0fe478c
JB		 4004 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4005 BIT(NL80211_IFTYPE_ADHOC);
4006 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4007 BIT(NL80211_IFTYPE_STATION);
2295c66b 4008 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
d0fe478c
JB		 4009 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4010 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4011 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
ece9c4ee
JB		 4012
4013 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4014 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4015 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4016 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4017 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4018 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4019 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4020 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
e72f368b
JB		 4021 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4022 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4023 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
d0fe478c
JB		 4024 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4025 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4026 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4027 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4028 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
ece9c4ee
JB		 4029
4030 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
8f2d3d2a 4031
b481de9c
ZY		 4032 SET_IEEE80211_DEV(hw, &pdev->dev);
4033
e1623446 4034 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 4035 priv->cfg = cfg;
b481de9c 4036 priv->pci_dev = pdev;
40cefda9 4037 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 4038
bee008b7
WYG		 4039 /* is antenna coupling more than 35dB ? */
4040 priv->bt_ant_couple_ok =
4041 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4042 true : false;
4043
f37837c9
WYG		 4044 /* enable/disable bt channel announcement */
4045 priv->bt_ch_announce = iwlagn_bt_ch_announce;
4046
20594eb0
WYG		 4047 if (iwl_alloc_traffic_mem(priv))
4048 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4049
316c30d9
AK		 4050 /**************************
4051 * 2. Initializing PCI bus
4052 **************************/
1a7123cd
JL		 4053 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4054 PCIE_LINK_STATE_CLKPM);
4055
316c30d9
AK		 4056 if (pci_enable_device(pdev)) {
4057 err = -ENODEV;
4058 goto out_ieee80211_free_hw;
4059 }
4060
4061 pci_set_master(pdev);
4062
093d874c 4063 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 4064 if (!err)
093d874c 4065 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 4066 if (err) {
093d874c 4067 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4068 if (!err)
093d874c 4069 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4070 /* both attempts failed: */
316c30d9 4071 if (err) {
978785a3 4072 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 4073 goto out_pci_disable_device;
cc2a8ea8 4074 }
316c30d9
AK		 4075 }
4076
4077 err = pci_request_regions(pdev, DRV_NAME);
4078 if (err)
4079 goto out_pci_disable_device;
4080
4081 pci_set_drvdata(pdev, priv);
4082
316c30d9
AK		 4083
4084 /***********************
4085 * 3. Read REV register
4086 ***********************/
4087 priv->hw_base = pci_iomap(pdev, 0, 0);
4088 if (!priv->hw_base) {
4089 err = -ENODEV;
4090 goto out_pci_release_regions;
4091 }
4092
e1623446 4093 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 4094 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4095 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 4096
731a29b7 4097 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 4098 * we should init now
4099 */
4100 spin_lock_init(&priv->reg_lock);
731a29b7 4101 spin_lock_init(&priv->lock);
4843b5a7
RC		 4102
4103 /*
4104 * stop and reset the on-board processor just in case it is in a
4105 * strange state ... like being left stranded by a primary kernel
4106 * and this is now the kdump kernel trying to start up
4107 */
4108 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4109
b661c819 4110 iwl_hw_detect(priv);
c11362c0 4111 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 4112 priv->cfg->name, priv->hw_rev);
316c30d9 4113
e7b63581
TW		 4114 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4115 * PCI Tx retries from interfering with C3 CPU state */
4116 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4117
086ed117
MA		 4118 iwl_prepare_card_hw(priv);
4119 if (!priv->hw_ready) {
4120 IWL_WARN(priv, "Failed, HW not ready\n");
4121 goto out_iounmap;
4122 }
4123
91238714
TW		 4124 /*****************
4125 * 4. Read EEPROM
4126 *****************/
316c30d9
AK		 4127 /* Read the EEPROM */
4128 err = iwl_eeprom_init(priv);
4129 if (err) {
15b1687c 4130 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4131 goto out_iounmap;
4132 }
8614f360
TW		 4133 err = iwl_eeprom_check_version(priv);
4134 if (err)
c8f16138 4135 goto out_free_eeprom;
8614f360 4136
21a5b3c6
WYG		 4137 err = iwl_eeprom_check_sku(priv);
4138 if (err)
4139 goto out_free_eeprom;
4140
02883017 4141 /* extract MAC Address */
c6fa17ed
WYG		 4142 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4143 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4144 priv->hw->wiphy->addresses = priv->addresses;
4145 priv->hw->wiphy->n_addresses = 1;
4146 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4147 if (num_mac > 1) {
4148 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4149 ETH_ALEN);
4150 priv->addresses[1].addr[5]++;
4151 priv->hw->wiphy->n_addresses++;
4152 }
316c30d9
AK		 4153
4154 /************************
4155 * 5. Setup HW constants
4156 ************************/
da154e30 4157 if (iwl_set_hw_params(priv)) {
15b1687c 4158 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4159 goto out_free_eeprom;
316c30d9
AK		 4160 }
4161
4162 /*******************
6ba87956 4163 * 6. Setup priv
316c30d9 4164 *******************/
b481de9c 4165
6ba87956 4166 err = iwl_init_drv(priv);
bf85ea4f 4167 if (err)
399f4900 4168 goto out_free_eeprom;
bf85ea4f 4169 /* At this point both hw and priv are initialized. */
316c30d9 4170
316c30d9 4171 /********************
09f9bf79 4172 * 7. Setup services
316c30d9 4173 ********************/
0359facc 4174 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4175 iwl_disable_interrupts(priv);
0359facc 4176 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4177
6cd0b1cb
HS		 4178 pci_enable_msi(priv->pci_dev);
4179
e39fdee1
WYG		 4180 if (priv->cfg->ops->lib->isr_ops.alloc)
4181 priv->cfg->ops->lib->isr_ops.alloc(priv);
4182
4183 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
ef850d7c 4184 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4185 if (err) {
4186 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4187 goto out_disable_msi;
4188 }
316c30d9 4189
4e39317d 4190 iwl_setup_deferred_work(priv);
653fa4a0 4191 iwl_setup_rx_handlers(priv);
316c30d9 4192
158bea07
JB		 4193 /*********************************************
4194 * 8. Enable interrupts and read RFKILL state
4195 *********************************************/
6ba87956 4196
6cd0b1cb
HS		 4197 /* enable interrupts if needed: hw bug w/a */
4198 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4199 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4200 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4201 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4202 }
4203
4204 iwl_enable_interrupts(priv);
4205
6cd0b1cb
HS		 4206 /* If platform's RF_KILL switch is NOT set to KILL */
4207 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4208 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4209 else
4210 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4211
a60e77e5
JB		 4212 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4213 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4214
58d0f361 4215 iwl_power_initialize(priv);
39b73fb1 4216 iwl_tt_initialize(priv);
158bea07 4217
a15707d8 4218 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4219
b08dfd04 4220 err = iwl_request_firmware(priv, true);
158bea07 4221 if (err)
7d47618a 4222 goto out_destroy_workqueue;
158bea07 4223
b481de9c
ZY		 4224 return 0;
4225
7d47618a 4226 out_destroy_workqueue:
c8f16138
RC		 4227 destroy_workqueue(priv->workqueue);
4228 priv->workqueue = NULL;
795cc0ad 4229 free_irq(priv->pci_dev->irq, priv);
e39fdee1
WYG		 4230 if (priv->cfg->ops->lib->isr_ops.free)
4231 priv->cfg->ops->lib->isr_ops.free(priv);
6cd0b1cb
HS		 4232 out_disable_msi:
4233 pci_disable_msi(priv->pci_dev);
6ba87956 4234 iwl_uninit_drv(priv);
073d3f5f
TW		 4235 out_free_eeprom:
4236 iwl_eeprom_free(priv);
b481de9c
ZY		 4237 out_iounmap:
4238 pci_iounmap(pdev, priv->hw_base);
4239 out_pci_release_regions:
316c30d9 4240 pci_set_drvdata(pdev, NULL);
623d563e 4241 pci_release_regions(pdev);
b481de9c
ZY		 4242 out_pci_disable_device:
4243 pci_disable_device(pdev);
b481de9c 4244 out_ieee80211_free_hw:
20594eb0 4245 iwl_free_traffic_mem(priv);
d7c76f4c 4246 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4247 out:
4248 return err;
4249}
4250
5b9f8cd3 4251static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4252{
c79dd5b5 4253 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4254 unsigned long flags;
b481de9c
ZY		 4255
4256 if (!priv)
4257 return;
4258
a15707d8 4259 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4260
e1623446 4261 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4262
67249625 4263 iwl_dbgfs_unregister(priv);
5b9f8cd3 4264 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4265
5b9f8cd3
EG		 4266 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4267 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4268 * we need to set STATUS_EXIT_PENDING bit.
4269 */
4270 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4271 if (priv->mac80211_registered) {
4272 ieee80211_unregister_hw(priv->hw);
4273 priv->mac80211_registered = 0;
0b124c31 4274 } else {
5b9f8cd3 4275 iwl_down(priv);
c4f55232
RR		 4276 }
4277
c166b25a
BC		 4278 /*
4279 * Make sure device is reset to low power before unloading driver.
4280 * This may be redundant with iwl_down(), but there are paths to
4281 * run iwl_down() without calling apm_ops.stop(), and there are
4282 * paths to avoid running iwl_down() at all before leaving driver.
4283 * This (inexpensive) call *makes sure* device is reset.
4284 */
14e8e4af 4285 iwl_apm_stop(priv);
c166b25a 4286
39b73fb1
WYG		 4287 iwl_tt_exit(priv);
4288
0359facc
MA		 4289 /* make sure we flush any pending irq or
4290 * tasklet for the driver
4291 */
4292 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4293 iwl_disable_interrupts(priv);
0359facc
MA		 4294 spin_unlock_irqrestore(&priv->lock, flags);
4295
4296 iwl_synchronize_irq(priv);
4297
5b9f8cd3 4298 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4299
4300 if (priv->rxq.bd)
54b81550 4301 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4302 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4303
073d3f5f 4304 iwl_eeprom_free(priv);
b481de9c 4305
b481de9c 4306
948c171c
MA		 4307 /*netif_stop_queue(dev); */
4308 flush_workqueue(priv->workqueue);
4309
5b9f8cd3 4310 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4311 * priv->workqueue... so we can't take down the workqueue
4312 * until now... */
4313 destroy_workqueue(priv->workqueue);
4314 priv->workqueue = NULL;
20594eb0 4315 iwl_free_traffic_mem(priv);
b481de9c 4316
6cd0b1cb
HS		 4317 free_irq(priv->pci_dev->irq, priv);
4318 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4319 pci_iounmap(pdev, priv->hw_base);
4320 pci_release_regions(pdev);
4321 pci_disable_device(pdev);
4322 pci_set_drvdata(pdev, NULL);
4323
6ba87956 4324 iwl_uninit_drv(priv);
b481de9c 4325
e39fdee1
WYG		 4326 if (priv->cfg->ops->lib->isr_ops.free)
4327 priv->cfg->ops->lib->isr_ops.free(priv);
ef850d7c 4328
77834543 4329 dev_kfree_skb(priv->beacon_skb);
b481de9c
ZY		 4330
4331 ieee80211_free_hw(priv->hw);
4332}
4333
b481de9c
ZY		 4334
4335/*****************************************************************************
4336 *
4337 * driver and module entry point
4338 *
4339 *****************************************************************************/
4340
fed9017e 4341/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4342static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4343#ifdef CONFIG_IWL4965
fed9017e
RR		 4344 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4345 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4346#endif /* CONFIG_IWL4965 */
5a6a256e 4347#ifdef CONFIG_IWL5000
ac592574
WYG		 4348/* 5100 Series WiFi */
4349 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4350 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4351 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4352 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4353 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4354 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4355 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4356 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4357 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4358 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4359 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4360 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4361 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4362 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4363 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4364 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4365 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4366 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4367 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4368 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4369 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4370 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4371 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4372 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4373
4374/* 5300 Series WiFi */
4375 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4376 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4377 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4378 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4379 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4380 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4381 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4382 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4383 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4384 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4385 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4386 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4387
4388/* 5350 Series WiFi/WiMax */
4389 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4390 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4391 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4392
4393/* 5150 Series Wifi/WiMax */
4394 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4395 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4396 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4397 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4398 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4399 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4400
4401 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4402 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4403 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4404 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4405
4406/* 6x00 Series */
5953a62e
WYG		 4407 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4408 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4409 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4410 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4411 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4412 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4413 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4414 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4415 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4416 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4417
95b13014 4418/* 6x00 Series Gen2a */
9f6e1baf
SZ		 4419 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4420 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4421 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4422 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4423 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4424 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4425 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4426
4427/* 6x00 Series Gen2b */
9f6e1baf
SZ		 4428 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4429 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
9f6e1baf 4430 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
8b37d9f0 4431 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl6000g2b_bg_cfg)},
9f6e1baf 4432 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
8b37d9f0 4433 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl6000g2b_bg_cfg)},
9f6e1baf
SZ		 4434 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4435 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4436 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4437 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4438 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4439 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4440 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4441 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4442 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4443 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4444
4445/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4446 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4447 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4448 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4449 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4450 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4451 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4452
03264339
SZ		 4453/* 6x50 WiFi/WiMax Series Gen2 */
4454 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4455 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4456 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4457 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4458 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4459 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4460
77dcb6a9 4461/* 1000 Series WiFi */
4bd0914f
WYG		 4462 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4463 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4464 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4465 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4466 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4467 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4468 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4469 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4470 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4471 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4472 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4473 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
1de19ecc 4474
58a39090 4475/* 100 Series WiFi */
1de19ecc 4476 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
2a21ff44 4477 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
1de19ecc 4478 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
2a21ff44 4479 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
1de19ecc 4480 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
2a21ff44 4481 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
58a39090
WYG		 4482
4483/* 130 Series WiFi */
4484 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4485 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4486 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4487 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4488 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4489 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4490
5a6a256e 4491#endif /* CONFIG_IWL5000 */
7100e924 4492
fed9017e
RR		 4493 {0}
4494};
4495MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4496
4497static struct pci_driver iwl_driver = {
b481de9c 4498 .name = DRV_NAME,
fed9017e 4499 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4500 .probe = iwl_pci_probe,
4501 .remove = __devexit_p(iwl_pci_remove),
f60dc013 4502 .driver.pm = IWL_PM_OPS,
b481de9c
ZY		 4503};
4504
5b9f8cd3 4505static int __init iwl_init(void)
b481de9c
ZY		 4506{
4507
4508 int ret;
c96c31e4
JP		 4509 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4510 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4511
e227ceac 4512 ret = iwlagn_rate_control_register();
897e1cf2 4513 if (ret) {
c96c31e4 4514 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4515 return ret;
4516 }
4517
fed9017e 4518 ret = pci_register_driver(&iwl_driver);
b481de9c 4519 if (ret) {
c96c31e4 4520 pr_err("Unable to initialize PCI module\n");
897e1cf2 4521 goto error_register;
b481de9c 4522 }
b481de9c
ZY		 4523
4524 return ret;
897e1cf2 4525
897e1cf2 4526error_register:
e227ceac 4527 iwlagn_rate_control_unregister();
897e1cf2 4528 return ret;
b481de9c
ZY		 4529}
4530
5b9f8cd3 4531static void __exit iwl_exit(void)
b481de9c 4532{
fed9017e 4533 pci_unregister_driver(&iwl_driver);
e227ceac 4534 iwlagn_rate_control_unregister();
b481de9c
ZY		 4535}
4536
5b9f8cd3
EG		 4537module_exit(iwl_exit);
4538module_init(iwl_init);
a562a9dd
RC		 4539
4540#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4541module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4542MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4543module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4544MODULE_PARM_DESC(debug, "debug output mask");
4545#endif
4546
2b068618
WYG		 4547module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4548MODULE_PARM_DESC(swcrypto50,
4549 "using crypto in software (default 0 [hardware]) (deprecated)");
4550module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4551MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4552module_param_named(queues_num50,
4553 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4554MODULE_PARM_DESC(queues_num50,
4555 "number of hw queues in 50xx series (deprecated)");
4556module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4557MODULE_PARM_DESC(queues_num, "number of hw queues.");
4558module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4559MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4560module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4561MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4562module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4563 int, S_IRUGO);
4564MODULE_PARM_DESC(amsdu_size_8K50,
4565 "enable 8K amsdu size in 50XX series (deprecated)");
4566module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4567 int, S_IRUGO);
4568MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4569module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4570MODULE_PARM_DESC(fw_restart50,
4571 "restart firmware in case of error (deprecated)");
4572module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4573MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4574module_param_named(
4575 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
72645eff
WYG		 4576MODULE_PARM_DESC(disable_hw_scan,
4577 "disable hardware scanning (default 0) (deprecated)");
dd7a2509
JB		 4578
4579module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4580 S_IRUGO);
4581MODULE_PARM_DESC(ucode_alternative,
4582 "specify ucode alternative to use from ucode file");
bee008b7
WYG		 4583
4584module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4585MODULE_PARM_DESC(antenna_coupling,
4586 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9
WYG		 4587
4588module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4589MODULE_PARM_DESC(bt_ch_announce,
4590 "Enable BT channel announcement mode (default: enable)");
Linux kernel - Deliverables
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