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iwlwifi: move AP sta ID to context
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY		 34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY		 38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY		 41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY		 45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY		 48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO		 52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
f0832f13 60#include "iwl-calib.h"
a1175124 61#include "iwl-agn.h"
b481de9c 62
416e1438 63
b481de9c
ZY		 64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
b481de9c
ZY		 70/*
71 * module name, copyright, version, etc.
b481de9c 72 */
d783b061 73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 74
0a6857e7 75#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 76#define VD "d"
77#else
78#define VD
79#endif
80
81963d68 81#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 82
b481de9c
ZY		 83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
bee008b7 90static int iwlagn_ant_coupling;
f37837c9 91static bool iwlagn_bt_ch_announce = 1;
bee008b7 92
b481de9c 93/**
5b9f8cd3 94 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 95 *
01ebd063 96 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 97 * the active_rxon structure is updated with the new data. This
98 * function correctly transitions out of the RXON_ASSOC_MSK state if
99 * a HW tune is required based on the RXON structure changes.
100 */
246ed355 101int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
b481de9c
ZY		 102{
103 /* cast away the const for active_rxon in this function */
246ed355 104 struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
43d59b32
EG		 105 int ret;
106 bool new_assoc =
246ed355 107 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 108
fee1247a 109 if (!iwl_is_alive(priv))
43d59b32 110 return -EBUSY;
b481de9c
ZY		 111
112 /* always get timestamp with Rx frame */
246ed355 113 ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
b481de9c 114
246ed355 115 ret = iwl_check_rxon_cmd(priv, ctx);
43d59b32 116 if (ret) {
15b1687c 117 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 118 return -EINVAL;
119 }
120
0924e519
WYG		 121 /*
122 * receive commit_rxon request
123 * abort any previous channel switch if still in process
124 */
125 if (priv->switch_rxon.switch_in_progress &&
246ed355 126 (priv->switch_rxon.channel != ctx->staging.channel)) {
0924e519
WYG		 127 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
128 le16_to_cpu(priv->switch_rxon.channel));
79d07325 129 iwl_chswitch_done(priv, false);
0924e519
WYG		 130 }
131
b481de9c 132 /* If we don't need to send a full RXON, we can use
5b9f8cd3 133 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 134 * and other flags for the current radio configuration. */
246ed355
JB		 135 if (!iwl_full_rxon_required(priv, ctx)) {
136 ret = iwl_send_rxon_assoc(priv, ctx);
43d59b32 137 if (ret) {
15b1687c 138 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 139 return ret;
b481de9c
ZY		 140 }
141
246ed355
JB		 142 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
143 iwl_print_rx_config_cmd(priv, ctx);
b481de9c
ZY		 144 return 0;
145 }
146
b481de9c
ZY		 147 /* If we are currently associated and the new config requires
148 * an RXON_ASSOC and the new config wants the associated mask enabled,
149 * we must clear the associated from the active configuration
150 * before we apply the new config */
246ed355 151 if (iwl_is_associated_ctx(ctx) && new_assoc) {
e1623446 152 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 153 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
154
8f2d3d2a 155 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355
JB		 156 sizeof(struct iwl_rxon_cmd),
157 active_rxon);
b481de9c
ZY		 158
159 /* If the mask clearing failed then we set
160 * active_rxon back to what it was previously */
43d59b32 161 if (ret) {
b481de9c 162 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 163 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 164 return ret;
b481de9c 165 }
dcef732c
JB		 166 iwl_clear_ucode_stations(priv, ctx);
167 iwl_restore_stations(priv, ctx);
335348b1
JB		 168 ret = iwl_restore_default_wep_keys(priv);
169 if (ret) {
170 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
171 return ret;
172 }
b481de9c
ZY		 173 }
174
e1623446 175 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 176 "* with%s RXON_FILTER_ASSOC_MSK\n"
177 "* channel = %d\n"
e174961c 178 "* bssid = %pM\n",
43d59b32 179 (new_assoc ? "" : "out"),
246ed355
JB		 180 le16_to_cpu(ctx->staging.channel),
181 ctx->staging.bssid_addr);
b481de9c 182
246ed355 183 iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG		 184
185 /* Apply the new configuration
7e246191
RC		 186 * RXON unassoc clears the station table in uCode so restoration of
187 * stations is needed after it (the RXON command) completes
43d59b32
EG		 188 */
189 if (!new_assoc) {
8f2d3d2a 190 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 191 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 192 if (ret) {
15b1687c 193 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 194 return ret;
195 }
91dd6c27 196 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
246ed355 197 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
dcef732c
JB		 198 iwl_clear_ucode_stations(priv, ctx);
199 iwl_restore_stations(priv, ctx);
335348b1
JB		 200 ret = iwl_restore_default_wep_keys(priv);
201 if (ret) {
202 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
203 return ret;
204 }
b481de9c
ZY		 205 }
206
19cc1087 207 priv->start_calib = 0;
9185159d 208 if (new_assoc) {
43d59b32
EG		 209 /* Apply the new configuration
210 * RXON assoc doesn't clear the station table in uCode,
211 */
8f2d3d2a 212 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 213 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 214 if (ret) {
15b1687c 215 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 216 return ret;
217 }
246ed355 218 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
b481de9c 219 }
246ed355 220 iwl_print_rx_config_cmd(priv, ctx);
b481de9c 221
36da7d70
ZY		 222 iwl_init_sensitivity(priv);
223
224 /* If we issue a new RXON command which required a tune then we must
225 * send a new TXPOWER command or we won't be able to Tx any frames */
226 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
227 if (ret) {
15b1687c 228 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 229 return ret;
230 }
231
b481de9c
ZY		 232 return 0;
233}
234
5b9f8cd3 235void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f 236{
246ed355 237 struct iwl_rxon_context *ctx;
5da4b55f 238
246ed355
JB		 239 if (priv->cfg->ops->hcmd->set_rxon_chain) {
240 for_each_context(priv, ctx) {
241 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
242 iwlcore_commit_rxon(priv, ctx);
243 }
244 }
5da4b55f
MA		 245}
246
fcab423d 247static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 248{
249 struct list_head *element;
250
e1623446 251 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 252 priv->frames_count);
253
254 while (!list_empty(&priv->free_frames)) {
255 element = priv->free_frames.next;
256 list_del(element);
fcab423d 257 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 258 priv->frames_count--;
259 }
260
261 if (priv->frames_count) {
39aadf8c 262 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 263 priv->frames_count);
264 priv->frames_count = 0;
265 }
266}
267
fcab423d 268static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 269{
fcab423d 270 struct iwl_frame *frame;
b481de9c
ZY		 271 struct list_head *element;
272 if (list_empty(&priv->free_frames)) {
273 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
274 if (!frame) {
15b1687c 275 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 276 return NULL;
277 }
278
279 priv->frames_count++;
280 return frame;
281 }
282
283 element = priv->free_frames.next;
284 list_del(element);
fcab423d 285 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 286}
287
fcab423d 288static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 289{
290 memset(frame, 0, sizeof(*frame));
291 list_add(&frame->list, &priv->free_frames);
292}
293
47ff65c4 294static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 295 struct ieee80211_hdr *hdr,
73ec1cc2 296 int left)
b481de9c 297{
6abbe554 298 if (!priv->ibss_beacon)
b481de9c
ZY		 299 return 0;
300
301 if (priv->ibss_beacon->len > left)
302 return 0;
303
304 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
305
306 return priv->ibss_beacon->len;
307}
308
47ff65c4
DH		 309/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
310static void iwl_set_beacon_tim(struct iwl_priv *priv,
311 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
312 u8 *beacon, u32 frame_size)
313{
314 u16 tim_idx;
315 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
316
317 /*
318 * The index is relative to frame start but we start looking at the
319 * variable-length part of the beacon.
320 */
321 tim_idx = mgmt->u.beacon.variable - beacon;
322
323 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
324 while ((tim_idx < (frame_size - 2)) &&
325 (beacon[tim_idx] != WLAN_EID_TIM))
326 tim_idx += beacon[tim_idx+1] + 2;
327
328 /* If TIM field was found, set variables */
329 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
330 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
331 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
332 } else
333 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
334}
335
5b9f8cd3 336static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 337 struct iwl_frame *frame)
4bf64efd
TW		 338{
339 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 340 u32 frame_size;
341 u32 rate_flags;
342 u32 rate;
343 /*
344 * We have to set up the TX command, the TX Beacon command, and the
345 * beacon contents.
346 */
4bf64efd 347
47ff65c4 348 /* Initialize memory */
4bf64efd
TW		 349 tx_beacon_cmd = &frame->u.beacon;
350 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
351
47ff65c4 352 /* Set up TX beacon contents */
4bf64efd 353 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 354 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 355 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
356 return 0;
4bf64efd 357
47ff65c4 358 /* Set up TX command fields */
4bf64efd 359 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
a194e324
JB		 360#warning "Use proper STA ID"
361 tx_beacon_cmd->tx.sta_id =
362 priv->contexts[IWL_RXON_CTX_BSS].bcast_sta_id;
47ff65c4
DH		 363 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
364 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
365 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 366
47ff65c4
DH		 367 /* Set up TX beacon command fields */
368 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
369 frame_size);
4bf64efd 370
47ff65c4
DH		 371 /* Set up packet rate and flags */
372 rate = iwl_rate_get_lowest_plcp(priv);
0e1654fa
JB		 373 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
374 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 375 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
376 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
377 rate_flags |= RATE_MCS_CCK_MSK;
378 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
379 rate_flags);
4bf64efd
TW		 380
381 return sizeof(*tx_beacon_cmd) + frame_size;
382}
5b9f8cd3 383static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 384{
fcab423d 385 struct iwl_frame *frame;
b481de9c
ZY		 386 unsigned int frame_size;
387 int rc;
b481de9c 388
fcab423d 389 frame = iwl_get_free_frame(priv);
b481de9c 390 if (!frame) {
15b1687c 391 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 392 "command.\n");
393 return -ENOMEM;
394 }
395
47ff65c4
DH		 396 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
397 if (!frame_size) {
398 IWL_ERR(priv, "Error configuring the beacon command\n");
399 iwl_free_frame(priv, frame);
400 return -EINVAL;
401 }
b481de9c 402
857485c0 403 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 404 &frame->u.cmd[0]);
405
fcab423d 406 iwl_free_frame(priv, frame);
b481de9c
ZY		 407
408 return rc;
409}
410
7aaa1d79
SO		 411static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
412{
413 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
414
415 dma_addr_t addr = get_unaligned_le32(&tb->lo);
416 if (sizeof(dma_addr_t) > sizeof(u32))
417 addr |=
418 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
419
420 return addr;
421}
422
423static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
424{
425 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
426
427 return le16_to_cpu(tb->hi_n_len) >> 4;
428}
429
430static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
431 dma_addr_t addr, u16 len)
432{
433 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
434 u16 hi_n_len = len << 4;
435
436 put_unaligned_le32(addr, &tb->lo);
437 if (sizeof(dma_addr_t) > sizeof(u32))
438 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
439
440 tb->hi_n_len = cpu_to_le16(hi_n_len);
441
442 tfd->num_tbs = idx + 1;
443}
444
445static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
446{
447 return tfd->num_tbs & 0x1f;
448}
449
450/**
451 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
452 * @priv - driver private data
453 * @txq - tx queue
454 *
455 * Does NOT advance any TFD circular buffer read/write indexes
456 * Does NOT free the TFD itself (which is within circular buffer)
457 */
458void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
459{
59606ffa 460 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 461 struct iwl_tfd *tfd;
462 struct pci_dev *dev = priv->pci_dev;
463 int index = txq->q.read_ptr;
464 int i;
465 int num_tbs;
466
467 tfd = &tfd_tmp[index];
468
469 /* Sanity check on number of chunks */
470 num_tbs = iwl_tfd_get_num_tbs(tfd);
471
472 if (num_tbs >= IWL_NUM_OF_TBS) {
473 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
474 /* @todo issue fatal error, it is quite serious situation */
475 return;
476 }
477
478 /* Unmap tx_cmd */
479 if (num_tbs)
480 pci_unmap_single(dev,
2e724443
FT		 481 dma_unmap_addr(&txq->meta[index], mapping),
482 dma_unmap_len(&txq->meta[index], len),
96891cee 483 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 484
485 /* Unmap chunks, if any. */
ff0d91c3 486 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 487 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
488 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
489
ff0d91c3
JB		 490 /* free SKB */
491 if (txq->txb) {
492 struct sk_buff *skb;
6f80240e 493
ff0d91c3 494 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 495
ff0d91c3
JB		 496 /* can be called from irqs-disabled context */
497 if (skb) {
498 dev_kfree_skb_any(skb);
499 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 500 }
501 }
502}
503
504int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
505 struct iwl_tx_queue *txq,
506 dma_addr_t addr, u16 len,
507 u8 reset, u8 pad)
508{
509 struct iwl_queue *q;
59606ffa 510 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 511 u32 num_tbs;
512
513 q = &txq->q;
59606ffa
SO		 514 tfd_tmp = (struct iwl_tfd *)txq->tfds;
515 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 516
517 if (reset)
518 memset(tfd, 0, sizeof(*tfd));
519
520 num_tbs = iwl_tfd_get_num_tbs(tfd);
521
522 /* Each TFD can point to a maximum 20 Tx buffers */
523 if (num_tbs >= IWL_NUM_OF_TBS) {
524 IWL_ERR(priv, "Error can not send more than %d chunks\n",
525 IWL_NUM_OF_TBS);
526 return -EINVAL;
527 }
528
529 BUG_ON(addr & ~DMA_BIT_MASK(36));
530 if (unlikely(addr & ~IWL_TX_DMA_MASK))
531 IWL_ERR(priv, "Unaligned address = %llx\n",
532 (unsigned long long)addr);
533
534 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
535
536 return 0;
537}
538
a8e74e27
SO		 539/*
540 * Tell nic where to find circular buffer of Tx Frame Descriptors for
541 * given Tx queue, and enable the DMA channel used for that queue.
542 *
543 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
544 * channels supported in hardware.
545 */
546int iwl_hw_tx_queue_init(struct iwl_priv *priv,
547 struct iwl_tx_queue *txq)
548{
a8e74e27
SO		 549 int txq_id = txq->q.id;
550
a8e74e27
SO		 551 /* Circular buffer (TFD queue in DRAM) physical base address */
552 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
553 txq->q.dma_addr >> 8);
554
a8e74e27
SO		 555 return 0;
556}
557
b481de9c
ZY		 558/******************************************************************************
559 *
560 * Generic RX handler implementations
561 *
562 ******************************************************************************/
885ba202
TW		 563static void iwl_rx_reply_alive(struct iwl_priv *priv,
564 struct iwl_rx_mem_buffer *rxb)
b481de9c 565{
2f301227 566 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 567 struct iwl_alive_resp *palive;
b481de9c
ZY		 568 struct delayed_work *pwork;
569
570 palive = &pkt->u.alive_frame;
571
e1623446 572 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 573 "0x%01X 0x%01X\n",
574 palive->is_valid, palive->ver_type,
575 palive->ver_subtype);
576
577 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 578 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 579 memcpy(&priv->card_alive_init,
580 &pkt->u.alive_frame,
885ba202 581 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 582 pwork = &priv->init_alive_start;
583 } else {
e1623446 584 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 585 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 586 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 587 pwork = &priv->alive_start;
588 }
589
590 /* We delay the ALIVE response by 5ms to
591 * give the HW RF Kill time to activate... */
592 if (palive->is_valid == UCODE_VALID_OK)
593 queue_delayed_work(priv->workqueue, pwork,
594 msecs_to_jiffies(5));
595 else
39aadf8c 596 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 597}
598
5b9f8cd3 599static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 600{
c79dd5b5
TW		 601 struct iwl_priv *priv =
602 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 603 struct sk_buff *beacon;
604
605 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
8bd413e6
JB		 606#warning "introduce and use beacon context"
607 beacon = ieee80211_beacon_get(priv->hw,
608 priv->contexts[IWL_RXON_CTX_BSS].vif);
b481de9c
ZY		 609
610 if (!beacon) {
15b1687c 611 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY		 612 return;
613 }
614
615 mutex_lock(&priv->mutex);
616 /* new beacon skb is allocated every time; dispose previous.*/
617 if (priv->ibss_beacon)
618 dev_kfree_skb(priv->ibss_beacon);
619
620 priv->ibss_beacon = beacon;
621 mutex_unlock(&priv->mutex);
622
5b9f8cd3 623 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 624}
625
fbba9410
WYG		 626static void iwl_bg_bt_runtime_config(struct work_struct *work)
627{
628 struct iwl_priv *priv =
629 container_of(work, struct iwl_priv, bt_runtime_config);
630
631 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
632 return;
633
634 /* dont send host command if rf-kill is on */
635 if (!iwl_is_ready_rf(priv))
636 return;
637 priv->cfg->ops->hcmd->send_bt_config(priv);
638}
639
bee008b7
WYG		 640static void iwl_bg_bt_full_concurrency(struct work_struct *work)
641{
642 struct iwl_priv *priv =
643 container_of(work, struct iwl_priv, bt_full_concurrency);
246ed355 644 struct iwl_rxon_context *ctx;
bee008b7
WYG		 645
646 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
647 return;
648
649 /* dont send host command if rf-kill is on */
650 if (!iwl_is_ready_rf(priv))
651 return;
652
653 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
654 priv->bt_full_concurrent ?
655 "full concurrency" : "3-wire");
656
657 /*
658 * LQ & RXON updated cmds must be sent before BT Config cmd
659 * to avoid 3-wire collisions
660 */
246ed355
JB		 661 mutex_lock(&priv->mutex);
662 for_each_context(priv, ctx) {
663 if (priv->cfg->ops->hcmd->set_rxon_chain)
664 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
665 iwlcore_commit_rxon(priv, ctx);
666 }
667 mutex_unlock(&priv->mutex);
bee008b7
WYG		 668
669 priv->cfg->ops->hcmd->send_bt_config(priv);
670}
671
4e39317d 672/**
5b9f8cd3 673 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 674 *
675 * This callback is provided in order to send a statistics request.
676 *
677 * This timer function is continually reset to execute within
678 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
679 * was received. We need to ensure we receive the statistics in order
680 * to update the temperature used for calibrating the TXPOWER.
681 */
5b9f8cd3 682static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 683{
684 struct iwl_priv *priv = (struct iwl_priv *)data;
685
686 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
687 return;
688
61780ee3
MA		 689 /* dont send host command if rf-kill is on */
690 if (!iwl_is_ready_rf(priv))
691 return;
692
ef8d5529 693 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 694}
695
a9e1cb6a
WYG		 696
697static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
698 u32 start_idx, u32 num_events,
699 u32 mode)
700{
701 u32 i;
702 u32 ptr; /* SRAM byte address of log data */
703 u32 ev, time, data; /* event log data */
704 unsigned long reg_flags;
705
706 if (mode == 0)
707 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
708 else
709 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
710
711 /* Make sure device is powered up for SRAM reads */
712 spin_lock_irqsave(&priv->reg_lock, reg_flags);
713 if (iwl_grab_nic_access(priv)) {
714 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
715 return;
716 }
717
718 /* Set starting address; reads will auto-increment */
719 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
720 rmb();
721
722 /*
723 * "time" is actually "data" for mode 0 (no timestamp).
724 * place event id # at far right for easier visual parsing.
725 */
726 for (i = 0; i < num_events; i++) {
727 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
728 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
729 if (mode == 0) {
730 trace_iwlwifi_dev_ucode_cont_event(priv,
731 0, time, ev);
732 } else {
733 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
734 trace_iwlwifi_dev_ucode_cont_event(priv,
735 time, data, ev);
736 }
737 }
738 /* Allow device to power down */
739 iwl_release_nic_access(priv);
740 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
741}
742
875295f1 743static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 744{
745 u32 capacity; /* event log capacity in # entries */
746 u32 base; /* SRAM byte address of event log header */
747 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
748 u32 num_wraps; /* # times uCode wrapped to top of log */
749 u32 next_entry; /* index of next entry to be written by uCode */
750
751 if (priv->ucode_type == UCODE_INIT)
752 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
753 else
754 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
755 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
756 capacity = iwl_read_targ_mem(priv, base);
757 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
758 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
759 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
760 } else
761 return;
762
763 if (num_wraps == priv->event_log.num_wraps) {
764 iwl_print_cont_event_trace(priv,
765 base, priv->event_log.next_entry,
766 next_entry - priv->event_log.next_entry,
767 mode);
768 priv->event_log.non_wraps_count++;
769 } else {
770 if ((num_wraps - priv->event_log.num_wraps) > 1)
771 priv->event_log.wraps_more_count++;
772 else
773 priv->event_log.wraps_once_count++;
774 trace_iwlwifi_dev_ucode_wrap_event(priv,
775 num_wraps - priv->event_log.num_wraps,
776 next_entry, priv->event_log.next_entry);
777 if (next_entry < priv->event_log.next_entry) {
778 iwl_print_cont_event_trace(priv, base,
779 priv->event_log.next_entry,
780 capacity - priv->event_log.next_entry,
781 mode);
782
783 iwl_print_cont_event_trace(priv, base, 0,
784 next_entry, mode);
785 } else {
786 iwl_print_cont_event_trace(priv, base,
787 next_entry, capacity - next_entry,
788 mode);
789
790 iwl_print_cont_event_trace(priv, base, 0,
791 next_entry, mode);
792 }
793 }
794 priv->event_log.num_wraps = num_wraps;
795 priv->event_log.next_entry = next_entry;
796}
797
798/**
799 * iwl_bg_ucode_trace - Timer callback to log ucode event
800 *
801 * The timer is continually set to execute every
802 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
803 * this function is to perform continuous uCode event logging operation
804 * if enabled
805 */
806static void iwl_bg_ucode_trace(unsigned long data)
807{
808 struct iwl_priv *priv = (struct iwl_priv *)data;
809
810 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
811 return;
812
813 if (priv->event_log.ucode_trace) {
814 iwl_continuous_event_trace(priv);
815 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
816 mod_timer(&priv->ucode_trace,
817 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
818 }
819}
820
5b9f8cd3 821static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 822 struct iwl_rx_mem_buffer *rxb)
b481de9c 823{
2f301227 824 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 825 struct iwl4965_beacon_notif *beacon =
826 (struct iwl4965_beacon_notif *)pkt->u.raw;
a85d7cca 827#ifdef CONFIG_IWLWIFI_DEBUG
e7d326ac 828 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 829
e1623446 830 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 831 "tsf %d %d rate %d\n",
25a6572c 832 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 833 beacon->beacon_notify_hdr.failure_frame,
834 le32_to_cpu(beacon->ibss_mgr_status),
835 le32_to_cpu(beacon->high_tsf),
836 le32_to_cpu(beacon->low_tsf), rate);
837#endif
838
a85d7cca
JB		 839 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
840
05c914fe 841 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 842 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
843 queue_work(priv->workqueue, &priv->beacon_update);
844}
845
b481de9c
ZY		 846/* Handle notification from uCode that card's power state is changing
847 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 848static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 849 struct iwl_rx_mem_buffer *rxb)
b481de9c 850{
2f301227 851 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 852 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
853 unsigned long status = priv->status;
854
3a41bbd5 855 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 856 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 857 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
858 (flags & CT_CARD_DISABLED) ?
859 "Reached" : "Not reached");
b481de9c
ZY		 860
861 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 862 CT_CARD_DISABLED)) {
b481de9c 863
3395f6e9 864 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 865 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
866
a8b50a0a
MA		 867 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
868 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 869
870 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 871 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 872 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 873 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 874 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 875 }
3a41bbd5 876 if (flags & CT_CARD_DISABLED)
39b73fb1 877 iwl_tt_enter_ct_kill(priv);
b481de9c 878 }
3a41bbd5 879 if (!(flags & CT_CARD_DISABLED))
39b73fb1 880 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 881
882 if (flags & HW_CARD_DISABLED)
883 set_bit(STATUS_RF_KILL_HW, &priv->status);
884 else
885 clear_bit(STATUS_RF_KILL_HW, &priv->status);
886
887
b481de9c 888 if (!(flags & RXON_CARD_DISABLED))
2a421b91 889 iwl_scan_cancel(priv);
b481de9c
ZY		 890
891 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 892 test_bit(STATUS_RF_KILL_HW, &priv->status)))
893 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
894 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 895 else
896 wake_up_interruptible(&priv->wait_command_queue);
897}
898
5b9f8cd3 899int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 900{
e2e3c57b 901 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 902 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW		 903 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
904 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
905 ~APMG_PS_CTRL_MSK_PWR_SRC);
906 } else {
907 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
908 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
909 ~APMG_PS_CTRL_MSK_PWR_SRC);
910 }
911
a8b50a0a 912 return 0;
e2e3c57b
TW		 913}
914
65550636
WYG		 915static void iwl_bg_tx_flush(struct work_struct *work)
916{
917 struct iwl_priv *priv =
918 container_of(work, struct iwl_priv, tx_flush);
919
920 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
921 return;
922
923 /* do nothing if rf-kill is on */
924 if (!iwl_is_ready_rf(priv))
925 return;
926
927 if (priv->cfg->ops->lib->txfifo_flush) {
928 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
929 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
930 }
931}
932
b481de9c 933/**
5b9f8cd3 934 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 935 *
936 * Setup the RX handlers for each of the reply types sent from the uCode
937 * to the host.
938 *
939 * This function chains into the hardware specific files for them to setup
940 * any hardware specific handlers as well.
941 */
653fa4a0 942static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 943{
885ba202 944 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 945 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
946 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 947 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
948 iwl_rx_spectrum_measure_notif;
5b9f8cd3 949 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 950 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 951 iwl_rx_pm_debug_statistics_notif;
952 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 953
9fbab516
BC		 954 /*
955 * The same handler is used for both the REPLY to a discrete
956 * statistics request from the host as well as for the periodic
957 * statistics notifications (after received beacons) from the uCode.
b481de9c 958 */
ef8d5529 959 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 960 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 961
962 iwl_setup_rx_scan_handlers(priv);
963
37a44211 964 /* status change handler */
5b9f8cd3 965 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 966
c1354754
TW		 967 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
968 iwl_rx_missed_beacon_notif;
37a44211 969 /* Rx handlers */
8d801080
WYG		 970 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
971 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 972 /* block ack */
74bcdb33 973 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 974 /* Set up hardware specific Rx handlers */
d4789efe 975 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 976}
977
b481de9c 978/**
a55360e4 979 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 980 *
981 * Uses the priv->rx_handlers callback function array to invoke
982 * the appropriate handlers, including command responses,
983 * frame-received notifications, and other notifications.
984 */
a55360e4 985void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 986{
a55360e4 987 struct iwl_rx_mem_buffer *rxb;
db11d634 988 struct iwl_rx_packet *pkt;
a55360e4 989 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 990 u32 r, i;
991 int reclaim;
992 unsigned long flags;
5c0eef96 993 u8 fill_rx = 0;
d68ab680 994 u32 count = 8;
4752c93c 995 int total_empty;
b481de9c 996
6440adb5
CB		 997 /* uCode's read index (stored in shared DRAM) indicates the last Rx
998 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 999 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 1000 i = rxq->read;
1001
1002 /* Rx interrupt, but nothing sent from uCode */
1003 if (i == r)
e1623446 1004 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 1005
4752c93c 1006 /* calculate total frames need to be restock after handling RX */
7300515d 1007 total_empty = r - rxq->write_actual;
4752c93c
MA		 1008 if (total_empty < 0)
1009 total_empty += RX_QUEUE_SIZE;
1010
1011 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 1012 fill_rx = 1;
1013
b481de9c 1014 while (i != r) {
f4989d9b
JB		 1015 int len;
1016
b481de9c
ZY		 1017 rxb = rxq->queue[i];
1018
9fbab516 1019 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 1020 * then a bug has been introduced in the queue refilling
1021 * routines -- catch it here */
1022 BUG_ON(rxb == NULL);
1023
1024 rxq->queue[i] = NULL;
1025
2f301227
ZY		 1026 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1027 PAGE_SIZE << priv->hw_params.rx_page_order,
1028 PCI_DMA_FROMDEVICE);
1029 pkt = rxb_addr(rxb);
b481de9c 1030
f4989d9b
JB		 1031 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1032 len += sizeof(u32); /* account for status word */
1033 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 1034
b481de9c
ZY		 1035 /* Reclaim a command buffer only if this packet is a response
1036 * to a (driver-originated) command.
1037 * If the packet (e.g. Rx frame) originated from uCode,
1038 * there is no command buffer to reclaim.
1039 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1040 * but apparently a few don't get set; catch them here. */
1041 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1042 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 1043 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 1044 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 1045 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 1046 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1047 (pkt->hdr.cmd != REPLY_TX);
1048
1049 /* Based on type of command response or notification,
1050 * handle those that need handling via function in
5b9f8cd3 1051 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 1052 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1053 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 1054 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 1055 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1056 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 1057 } else {
1058 /* No handling needed */
e1623446 1059 IWL_DEBUG_RX(priv,
b481de9c
ZY		 1060 "r %d i %d No handler needed for %s, 0x%02x\n",
1061 r, i, get_cmd_string(pkt->hdr.cmd),
1062 pkt->hdr.cmd);
1063 }
1064
29b1b268
ZY		 1065 /*
1066 * XXX: After here, we should always check rxb->page
1067 * against NULL before touching it or its virtual
1068 * memory (pkt). Because some rx_handler might have
1069 * already taken or freed the pages.
1070 */
1071
b481de9c 1072 if (reclaim) {
2f301227
ZY		 1073 /* Invoke any callbacks, transfer the buffer to caller,
1074 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1075 * as we reclaim the driver command queue */
29b1b268 1076 if (rxb->page)
17b88929 1077 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1078 else
39aadf8c 1079 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1080 }
1081
7300515d
ZY		 1082 /* Reuse the page if possible. For notification packets and
1083 * SKBs that fail to Rx correctly, add them back into the
1084 * rx_free list for reuse later. */
1085 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1086 if (rxb->page != NULL) {
7300515d
ZY		 1087 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1088 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1089 PCI_DMA_FROMDEVICE);
1090 list_add_tail(&rxb->list, &rxq->rx_free);
1091 rxq->free_count++;
1092 } else
1093 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1094
b481de9c 1095 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1096
b481de9c 1097 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1098 /* If there are a lot of unused frames,
1099 * restock the Rx queue so ucode wont assert. */
1100 if (fill_rx) {
1101 count++;
1102 if (count >= 8) {
7300515d 1103 rxq->read = i;
54b81550 1104 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1105 count = 0;
1106 }
1107 }
b481de9c
ZY		 1108 }
1109
1110 /* Backtrack one entry */
7300515d 1111 rxq->read = i;
4752c93c 1112 if (fill_rx)
54b81550 1113 iwlagn_rx_replenish_now(priv);
4752c93c 1114 else
54b81550 1115 iwlagn_rx_queue_restock(priv);
a55360e4 1116}
a55360e4 1117
0359facc
MA		 1118/* call this function to flush any scheduled tasklet */
1119static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1120{
a96a27f9 1121 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1122 synchronize_irq(priv->pci_dev->irq);
1123 tasklet_kill(&priv->irq_tasklet);
1124}
1125
ef850d7c 1126static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1127{
1128 u32 inta, handled = 0;
1129 u32 inta_fh;
1130 unsigned long flags;
c2e61da2 1131 u32 i;
0a6857e7 1132#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1133 u32 inta_mask;
1134#endif
1135
1136 spin_lock_irqsave(&priv->lock, flags);
1137
1138 /* Ack/clear/reset pending uCode interrupts.
1139 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1140 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1141 inta = iwl_read32(priv, CSR_INT);
1142 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1143
1144 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1145 * Any new interrupts that happen after this, either while we're
1146 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1147 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1148 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1149
0a6857e7 1150#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1151 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1152 /* just for debug */
3395f6e9 1153 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1154 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1155 inta, inta_mask, inta_fh);
1156 }
1157#endif
1158
2f301227
ZY		 1159 spin_unlock_irqrestore(&priv->lock, flags);
1160
b481de9c
ZY		 1161 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1162 * atomic, make sure that inta covers all the interrupts that
1163 * we've discovered, even if FH interrupt came in just after
1164 * reading CSR_INT. */
6f83eaa1 1165 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1166 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1167 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1168 inta |= CSR_INT_BIT_FH_TX;
1169
1170 /* Now service all interrupt bits discovered above. */
1171 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1172 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1173
1174 /* Tell the device to stop sending interrupts */
5b9f8cd3 1175 iwl_disable_interrupts(priv);
b481de9c 1176
a83b9141 1177 priv->isr_stats.hw++;
5b9f8cd3 1178 iwl_irq_handle_error(priv);
b481de9c
ZY		 1179
1180 handled |= CSR_INT_BIT_HW_ERR;
1181
b481de9c
ZY		 1182 return;
1183 }
1184
0a6857e7 1185#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1186 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1187 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1188 if (inta & CSR_INT_BIT_SCD) {
e1623446 1189 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1190 "the frame/frames.\n");
a83b9141
WYG		 1191 priv->isr_stats.sch++;
1192 }
b481de9c
ZY		 1193
1194 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1195 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1196 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1197 priv->isr_stats.alive++;
1198 }
b481de9c
ZY		 1199 }
1200#endif
1201 /* Safely ignore these bits for debug checks below */
25c03d8e 1202 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1203
9fbab516 1204 /* HW RF KILL switch toggled */
b481de9c
ZY		 1205 if (inta & CSR_INT_BIT_RF_KILL) {
1206 int hw_rf_kill = 0;
3395f6e9 1207 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1208 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1209 hw_rf_kill = 1;
1210
4c423a2b 1211 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1212 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1213
a83b9141
WYG		 1214 priv->isr_stats.rfkill++;
1215
a9efa652 1216 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1217 * the driver allows loading the ucode even if the radio
1218 * is killed. Hence update the killswitch state here. The
1219 * rfkill handler will care about restarting if needed.
a9efa652 1220 */
6cd0b1cb
HS		 1221 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1222 if (hw_rf_kill)
1223 set_bit(STATUS_RF_KILL_HW, &priv->status);
1224 else
1225 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1226 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1227 }
b481de9c
ZY		 1228
1229 handled |= CSR_INT_BIT_RF_KILL;
1230 }
1231
9fbab516 1232 /* Chip got too hot and stopped itself */
b481de9c 1233 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1234 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1235 priv->isr_stats.ctkill++;
b481de9c
ZY		 1236 handled |= CSR_INT_BIT_CT_KILL;
1237 }
1238
1239 /* Error detected by uCode */
1240 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1241 IWL_ERR(priv, "Microcode SW error detected. "
1242 " Restarting 0x%X.\n", inta);
a83b9141
WYG		 1243 priv->isr_stats.sw++;
1244 priv->isr_stats.sw_err = inta;
5b9f8cd3 1245 iwl_irq_handle_error(priv);
b481de9c
ZY		 1246 handled |= CSR_INT_BIT_SW_ERR;
1247 }
1248
c2e61da2
BC		 1249 /*
1250 * uCode wakes up after power-down sleep.
1251 * Tell device about any new tx or host commands enqueued,
1252 * and about any Rx buffers made available while asleep.
1253 */
b481de9c 1254 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1255 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1256 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1257 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1258 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1259 priv->isr_stats.wakeup++;
b481de9c
ZY		 1260 handled |= CSR_INT_BIT_WAKEUP;
1261 }
1262
1263 /* All uCode command responses, including Tx command responses,
1264 * Rx "responses" (frame-received notification), and other
1265 * notifications from uCode come through here*/
1266 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1267 iwl_rx_handle(priv);
a83b9141 1268 priv->isr_stats.rx++;
b481de9c
ZY		 1269 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1270 }
1271
c72cd19f 1272 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1273 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1274 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1275 priv->isr_stats.tx++;
b481de9c 1276 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1277 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1278 priv->ucode_write_complete = 1;
1279 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1280 }
1281
a83b9141 1282 if (inta & ~handled) {
15b1687c 1283 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1284 priv->isr_stats.unhandled++;
1285 }
b481de9c 1286
40cefda9 1287 if (inta & ~(priv->inta_mask)) {
39aadf8c 1288 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1289 inta & ~priv->inta_mask);
39aadf8c 1290 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1291 }
1292
1293 /* Re-enable all interrupts */
0359facc
MA		 1294 /* only Re-enable if diabled by irq */
1295 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1296 iwl_enable_interrupts(priv);
b481de9c 1297
0a6857e7 1298#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1299 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1300 inta = iwl_read32(priv, CSR_INT);
1301 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1302 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1303 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1304 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1305 }
1306#endif
b481de9c
ZY		 1307}
1308
ef850d7c
MA		 1309/* tasklet for iwlagn interrupt */
1310static void iwl_irq_tasklet(struct iwl_priv *priv)
1311{
1312 u32 inta = 0;
1313 u32 handled = 0;
1314 unsigned long flags;
8756990f 1315 u32 i;
ef850d7c
MA		 1316#ifdef CONFIG_IWLWIFI_DEBUG
1317 u32 inta_mask;
1318#endif
1319
1320 spin_lock_irqsave(&priv->lock, flags);
1321
1322 /* Ack/clear/reset pending uCode interrupts.
1323 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1324 */
48a6be6a
SZ		 1325 /* There is a hardware bug in the interrupt mask function that some
1326 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1327 * they are disabled in the CSR_INT_MASK register. Furthermore the
1328 * ICT interrupt handling mechanism has another bug that might cause
1329 * these unmasked interrupts fail to be detected. We workaround the
1330 * hardware bugs here by ACKing all the possible interrupts so that
1331 * interrupt coalescing can still be achieved.
1332 */
4a35ecf8 1333 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1334
a4c8b2a6 1335 inta = priv->_agn.inta;
ef850d7c
MA		 1336
1337#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1338 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1339 /* just for debug */
1340 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1341 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1342 inta, inta_mask);
1343 }
1344#endif
2f301227
ZY		 1345
1346 spin_unlock_irqrestore(&priv->lock, flags);
1347
a4c8b2a6
JB		 1348 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1349 priv->_agn.inta = 0;
ef850d7c
MA		 1350
1351 /* Now service all interrupt bits discovered above. */
1352 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1353 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1354
1355 /* Tell the device to stop sending interrupts */
1356 iwl_disable_interrupts(priv);
1357
1358 priv->isr_stats.hw++;
1359 iwl_irq_handle_error(priv);
1360
1361 handled |= CSR_INT_BIT_HW_ERR;
1362
ef850d7c
MA		 1363 return;
1364 }
1365
1366#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1367 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1368 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1369 if (inta & CSR_INT_BIT_SCD) {
1370 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1371 "the frame/frames.\n");
1372 priv->isr_stats.sch++;
1373 }
1374
1375 /* Alive notification via Rx interrupt will do the real work */
1376 if (inta & CSR_INT_BIT_ALIVE) {
1377 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1378 priv->isr_stats.alive++;
1379 }
1380 }
1381#endif
1382 /* Safely ignore these bits for debug checks below */
1383 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1384
1385 /* HW RF KILL switch toggled */
1386 if (inta & CSR_INT_BIT_RF_KILL) {
1387 int hw_rf_kill = 0;
1388 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1389 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1390 hw_rf_kill = 1;
1391
4c423a2b 1392 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1393 hw_rf_kill ? "disable radio" : "enable radio");
1394
1395 priv->isr_stats.rfkill++;
1396
1397 /* driver only loads ucode once setting the interface up.
1398 * the driver allows loading the ucode even if the radio
1399 * is killed. Hence update the killswitch state here. The
1400 * rfkill handler will care about restarting if needed.
1401 */
1402 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1403 if (hw_rf_kill)
1404 set_bit(STATUS_RF_KILL_HW, &priv->status);
1405 else
1406 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1407 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1408 }
1409
1410 handled |= CSR_INT_BIT_RF_KILL;
1411 }
1412
1413 /* Chip got too hot and stopped itself */
1414 if (inta & CSR_INT_BIT_CT_KILL) {
1415 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1416 priv->isr_stats.ctkill++;
1417 handled |= CSR_INT_BIT_CT_KILL;
1418 }
1419
1420 /* Error detected by uCode */
1421 if (inta & CSR_INT_BIT_SW_ERR) {
1422 IWL_ERR(priv, "Microcode SW error detected. "
1423 " Restarting 0x%X.\n", inta);
1424 priv->isr_stats.sw++;
1425 priv->isr_stats.sw_err = inta;
1426 iwl_irq_handle_error(priv);
1427 handled |= CSR_INT_BIT_SW_ERR;
1428 }
1429
1430 /* uCode wakes up after power-down sleep */
1431 if (inta & CSR_INT_BIT_WAKEUP) {
1432 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1433 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1434 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1435 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1436
1437 priv->isr_stats.wakeup++;
1438
1439 handled |= CSR_INT_BIT_WAKEUP;
1440 }
1441
1442 /* All uCode command responses, including Tx command responses,
1443 * Rx "responses" (frame-received notification), and other
1444 * notifications from uCode come through here*/
40cefda9
MA		 1445 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1446 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1447 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1448 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1449 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1450 iwl_write32(priv, CSR_FH_INT_STATUS,
1451 CSR49_FH_INT_RX_MASK);
1452 }
1453 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1454 handled |= CSR_INT_BIT_RX_PERIODIC;
1455 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1456 }
1457 /* Sending RX interrupt require many steps to be done in the
1458 * the device:
1459 * 1- write interrupt to current index in ICT table.
1460 * 2- dma RX frame.
1461 * 3- update RX shared data to indicate last write index.
1462 * 4- send interrupt.
1463 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1464 * but the shared data changes does not reflect this;
1465 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1466 */
74ba67ed
BC		 1467
1468 /* Disable periodic interrupt; we use it as just a one-shot. */
1469 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1470 CSR_INT_PERIODIC_DIS);
ef850d7c 1471 iwl_rx_handle(priv);
74ba67ed
BC		 1472
1473 /*
1474 * Enable periodic interrupt in 8 msec only if we received
1475 * real RX interrupt (instead of just periodic int), to catch
1476 * any dangling Rx interrupt. If it was just the periodic
1477 * interrupt, there was no dangling Rx activity, and no need
1478 * to extend the periodic interrupt; one-shot is enough.
1479 */
40cefda9 1480 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1481 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1482 CSR_INT_PERIODIC_ENA);
1483
ef850d7c 1484 priv->isr_stats.rx++;
ef850d7c
MA		 1485 }
1486
c72cd19f 1487 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1488 if (inta & CSR_INT_BIT_FH_TX) {
1489 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1490 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1491 priv->isr_stats.tx++;
1492 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1493 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1494 priv->ucode_write_complete = 1;
1495 wake_up_interruptible(&priv->wait_command_queue);
1496 }
1497
1498 if (inta & ~handled) {
1499 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1500 priv->isr_stats.unhandled++;
1501 }
1502
40cefda9 1503 if (inta & ~(priv->inta_mask)) {
ef850d7c 1504 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1505 inta & ~priv->inta_mask);
ef850d7c
MA		 1506 }
1507
ef850d7c
MA		 1508 /* Re-enable all interrupts */
1509 /* only Re-enable if diabled by irq */
1510 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1511 iwl_enable_interrupts(priv);
ef850d7c
MA		 1512}
1513
872c8ddc
WYG		 1514/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1515#define ACK_CNT_RATIO (50)
1516#define BA_TIMEOUT_CNT (5)
1517#define BA_TIMEOUT_MAX (16)
1518
1519/**
1520 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1521 *
1522 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1523 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1524 * operation state.
1525 */
1526bool iwl_good_ack_health(struct iwl_priv *priv,
1527 struct iwl_rx_packet *pkt)
1528{
1529 bool rc = true;
1530 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1531 int ba_timeout_delta;
1532
1533 actual_ack_cnt_delta =
1534 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
f3aebeee 1535 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1536 expected_ack_cnt_delta =
1537 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
f3aebeee 1538 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1539 ba_timeout_delta =
1540 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
f3aebeee 1541 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1542 if ((priv->_agn.agg_tids_count > 0) &&
1543 (expected_ack_cnt_delta > 0) &&
1544 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1545 < ACK_CNT_RATIO) &&
1546 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1547 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1548 " expected_ack_cnt = %d\n",
1549 actual_ack_cnt_delta, expected_ack_cnt_delta);
1550
d73e4923
JB		 1551#ifdef CONFIG_IWLWIFI_DEBUGFS
1552 /*
1553 * This is ifdef'ed on DEBUGFS because otherwise the
1554 * statistics aren't available. If DEBUGFS is set but
1555 * DEBUG is not, these will just compile out.
1556 */
872c8ddc 1557 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
f3aebeee 1558 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1559 IWL_DEBUG_RADIO(priv,
1560 "ack_or_ba_timeout_collision delta = %d\n",
f3aebeee 1561 priv->_agn.delta_statistics.tx.
872c8ddc
WYG		 1562 ack_or_ba_timeout_collision);
1563#endif
1564 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1565 ba_timeout_delta);
1566 if (!actual_ack_cnt_delta &&
1567 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1568 rc = false;
1569 }
1570 return rc;
1571}
1572
a83b9141 1573
7d47618a
EG		 1574/*****************************************************************************
1575 *
1576 * sysfs attributes
1577 *
1578 *****************************************************************************/
1579
1580#ifdef CONFIG_IWLWIFI_DEBUG
1581
1582/*
1583 * The following adds a new attribute to the sysfs representation
1584 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1585 * used for controlling the debug level.
1586 *
1587 * See the level definitions in iwl for details.
1588 *
1589 * The debug_level being managed using sysfs below is a per device debug
1590 * level that is used instead of the global debug level if it (the per
1591 * device debug level) is set.
1592 */
1593static ssize_t show_debug_level(struct device *d,
1594 struct device_attribute *attr, char *buf)
1595{
1596 struct iwl_priv *priv = dev_get_drvdata(d);
1597 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1598}
1599static ssize_t store_debug_level(struct device *d,
1600 struct device_attribute *attr,
1601 const char *buf, size_t count)
1602{
1603 struct iwl_priv *priv = dev_get_drvdata(d);
1604 unsigned long val;
1605 int ret;
1606
1607 ret = strict_strtoul(buf, 0, &val);
1608 if (ret)
1609 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1610 else {
1611 priv->debug_level = val;
1612 if (iwl_alloc_traffic_mem(priv))
1613 IWL_ERR(priv,
1614 "Not enough memory to generate traffic log\n");
1615 }
1616 return strnlen(buf, count);
1617}
1618
1619static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1620 show_debug_level, store_debug_level);
1621
1622
1623#endif /* CONFIG_IWLWIFI_DEBUG */
1624
1625
1626static ssize_t show_temperature(struct device *d,
1627 struct device_attribute *attr, char *buf)
1628{
1629 struct iwl_priv *priv = dev_get_drvdata(d);
1630
1631 if (!iwl_is_alive(priv))
1632 return -EAGAIN;
1633
1634 return sprintf(buf, "%d\n", priv->temperature);
1635}
1636
1637static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1638
1639static ssize_t show_tx_power(struct device *d,
1640 struct device_attribute *attr, char *buf)
1641{
1642 struct iwl_priv *priv = dev_get_drvdata(d);
1643
1644 if (!iwl_is_ready_rf(priv))
1645 return sprintf(buf, "off\n");
1646 else
1647 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1648}
1649
1650static ssize_t store_tx_power(struct device *d,
1651 struct device_attribute *attr,
1652 const char *buf, size_t count)
1653{
1654 struct iwl_priv *priv = dev_get_drvdata(d);
1655 unsigned long val;
1656 int ret;
1657
1658 ret = strict_strtoul(buf, 10, &val);
1659 if (ret)
1660 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1661 else {
1662 ret = iwl_set_tx_power(priv, val, false);
1663 if (ret)
1664 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1665 ret);
1666 else
1667 ret = count;
1668 }
1669 return ret;
1670}
1671
1672static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1673
7d47618a
EG		 1674static struct attribute *iwl_sysfs_entries[] = {
1675 &dev_attr_temperature.attr,
1676 &dev_attr_tx_power.attr,
7d47618a
EG		 1677#ifdef CONFIG_IWLWIFI_DEBUG
1678 &dev_attr_debug_level.attr,
1679#endif
1680 NULL
1681};
1682
1683static struct attribute_group iwl_attribute_group = {
1684 .name = NULL, /* put in device directory */
1685 .attrs = iwl_sysfs_entries,
1686};
1687
b481de9c
ZY		 1688/******************************************************************************
1689 *
1690 * uCode download functions
1691 *
1692 ******************************************************************************/
1693
5b9f8cd3 1694static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1695{
98c92211
TW		 1696 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1697 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1698 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1699 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1700 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1701 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1702}
1703
5b9f8cd3 1704static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1705{
1706 /* Remove all resets to allow NIC to operate */
1707 iwl_write32(priv, CSR_RESET, 0);
1708}
1709
dd7a2509
JB		 1710struct iwlagn_ucode_capabilities {
1711 u32 max_probe_length;
6a822d06 1712 u32 standard_phy_calibration_size;
dd7a2509 1713};
edcdf8b2 1714
b08dfd04 1715static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1716static int iwl_mac_setup_register(struct iwl_priv *priv,
1717 struct iwlagn_ucode_capabilities *capa);
b08dfd04 1718
39396085
JS		 1719#define UCODE_EXPERIMENTAL_INDEX 100
1720#define UCODE_EXPERIMENTAL_TAG "exp"
1721
b08dfd04
JB		 1722static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1723{
1724 const char *name_pre = priv->cfg->fw_name_pre;
39396085 1725 char tag[8];
b08dfd04 1726
39396085
JS		 1727 if (first) {
1728#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1729 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1730 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1731 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1732#endif
b08dfd04 1733 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS		 1734 sprintf(tag, "%d", priv->fw_index);
1735 } else {
b08dfd04 1736 priv->fw_index--;
39396085
JS		 1737 sprintf(tag, "%d", priv->fw_index);
1738 }
b08dfd04
JB		 1739
1740 if (priv->fw_index < priv->cfg->ucode_api_min) {
1741 IWL_ERR(priv, "no suitable firmware found!\n");
1742 return -ENOENT;
1743 }
1744
39396085 1745 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1746
39396085
JS		 1747 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1748 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1749 ? "EXPERIMENTAL " : "",
b08dfd04
JB		 1750 priv->firmware_name);
1751
1752 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1753 &priv->pci_dev->dev, GFP_KERNEL, priv,
1754 iwl_ucode_callback);
1755}
1756
0e9a44dc
JB		 1757struct iwlagn_firmware_pieces {
1758 const void *inst, *data, *init, *init_data, *boot;
1759 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1760
1761 u32 build;
b2e640d4
JB		 1762
1763 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1764 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1765};
1766
1767static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1768 const struct firmware *ucode_raw,
1769 struct iwlagn_firmware_pieces *pieces)
1770{
1771 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1772 u32 api_ver, hdr_size;
1773 const u8 *src;
1774
1775 priv->ucode_ver = le32_to_cpu(ucode->ver);
1776 api_ver = IWL_UCODE_API(priv->ucode_ver);
1777
1778 switch (api_ver) {
1779 default:
1780 /*
1781 * 4965 doesn't revision the firmware file format
1782 * along with the API version, it always uses v1
1783 * file format.
1784 */
1785 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1786 CSR_HW_REV_TYPE_4965) {
1787 hdr_size = 28;
1788 if (ucode_raw->size < hdr_size) {
1789 IWL_ERR(priv, "File size too small!\n");
1790 return -EINVAL;
1791 }
1792 pieces->build = le32_to_cpu(ucode->u.v2.build);
1793 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1794 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1795 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1796 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1797 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1798 src = ucode->u.v2.data;
1799 break;
1800 }
1801 /* fall through for 4965 */
1802 case 0:
1803 case 1:
1804 case 2:
1805 hdr_size = 24;
1806 if (ucode_raw->size < hdr_size) {
1807 IWL_ERR(priv, "File size too small!\n");
1808 return -EINVAL;
1809 }
1810 pieces->build = 0;
1811 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1812 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1813 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1814 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1815 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1816 src = ucode->u.v1.data;
1817 break;
1818 }
1819
1820 /* Verify size of file vs. image size info in file's header */
1821 if (ucode_raw->size != hdr_size + pieces->inst_size +
1822 pieces->data_size + pieces->init_size +
1823 pieces->init_data_size + pieces->boot_size) {
1824
1825 IWL_ERR(priv,
1826 "uCode file size %d does not match expected size\n",
1827 (int)ucode_raw->size);
1828 return -EINVAL;
1829 }
1830
1831 pieces->inst = src;
1832 src += pieces->inst_size;
1833 pieces->data = src;
1834 src += pieces->data_size;
1835 pieces->init = src;
1836 src += pieces->init_size;
1837 pieces->init_data = src;
1838 src += pieces->init_data_size;
1839 pieces->boot = src;
1840 src += pieces->boot_size;
1841
1842 return 0;
1843}
1844
dd7a2509
JB		 1845static int iwlagn_wanted_ucode_alternative = 1;
1846
1847static int iwlagn_load_firmware(struct iwl_priv *priv,
1848 const struct firmware *ucode_raw,
1849 struct iwlagn_firmware_pieces *pieces,
1850 struct iwlagn_ucode_capabilities *capa)
1851{
1852 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1853 struct iwl_ucode_tlv *tlv;
1854 size_t len = ucode_raw->size;
1855 const u8 *data;
1856 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1857 u64 alternatives;
ad8d8333
WYG		 1858 u32 tlv_len;
1859 enum iwl_ucode_tlv_type tlv_type;
1860 const u8 *tlv_data;
dd7a2509 1861
ad8d8333
WYG		 1862 if (len < sizeof(*ucode)) {
1863 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1864 return -EINVAL;
ad8d8333 1865 }
dd7a2509 1866
ad8d8333
WYG		 1867 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1868 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1869 le32_to_cpu(ucode->magic));
dd7a2509 1870 return -EINVAL;
ad8d8333 1871 }
dd7a2509
JB		 1872
1873 /*
1874 * Check which alternatives are present, and "downgrade"
1875 * when the chosen alternative is not present, warning
1876 * the user when that happens. Some files may not have
1877 * any alternatives, so don't warn in that case.
1878 */
1879 alternatives = le64_to_cpu(ucode->alternatives);
1880 tmp = wanted_alternative;
1881 if (wanted_alternative > 63)
1882 wanted_alternative = 63;
1883 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1884 wanted_alternative--;
1885 if (wanted_alternative && wanted_alternative != tmp)
1886 IWL_WARN(priv,
1887 "uCode alternative %d not available, choosing %d\n",
1888 tmp, wanted_alternative);
1889
1890 priv->ucode_ver = le32_to_cpu(ucode->ver);
1891 pieces->build = le32_to_cpu(ucode->build);
1892 data = ucode->data;
1893
1894 len -= sizeof(*ucode);
1895
704da534 1896 while (len >= sizeof(*tlv)) {
dd7a2509 1897 u16 tlv_alt;
dd7a2509
JB		 1898
1899 len -= sizeof(*tlv);
1900 tlv = (void *)data;
1901
1902 tlv_len = le32_to_cpu(tlv->length);
1903 tlv_type = le16_to_cpu(tlv->type);
1904 tlv_alt = le16_to_cpu(tlv->alternative);
1905 tlv_data = tlv->data;
1906
ad8d8333
WYG		 1907 if (len < tlv_len) {
1908 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1909 len, tlv_len);
dd7a2509 1910 return -EINVAL;
ad8d8333 1911 }
dd7a2509
JB		 1912 len -= ALIGN(tlv_len, 4);
1913 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1914
1915 /*
1916 * Alternative 0 is always valid.
1917 *
1918 * Skip alternative TLVs that are not selected.
1919 */
1920 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1921 continue;
1922
1923 switch (tlv_type) {
1924 case IWL_UCODE_TLV_INST:
1925 pieces->inst = tlv_data;
1926 pieces->inst_size = tlv_len;
1927 break;
1928 case IWL_UCODE_TLV_DATA:
1929 pieces->data = tlv_data;
1930 pieces->data_size = tlv_len;
1931 break;
1932 case IWL_UCODE_TLV_INIT:
1933 pieces->init = tlv_data;
1934 pieces->init_size = tlv_len;
1935 break;
1936 case IWL_UCODE_TLV_INIT_DATA:
1937 pieces->init_data = tlv_data;
1938 pieces->init_data_size = tlv_len;
1939 break;
1940 case IWL_UCODE_TLV_BOOT:
1941 pieces->boot = tlv_data;
1942 pieces->boot_size = tlv_len;
1943 break;
1944 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1945 if (tlv_len != sizeof(u32))
1946 goto invalid_tlv_len;
1947 capa->max_probe_length =
ad8d8333 1948 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1949 break;
b2e640d4 1950 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1951 if (tlv_len != sizeof(u32))
1952 goto invalid_tlv_len;
1953 pieces->init_evtlog_ptr =
ad8d8333 1954 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1955 break;
1956 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 1957 if (tlv_len != sizeof(u32))
1958 goto invalid_tlv_len;
1959 pieces->init_evtlog_size =
ad8d8333 1960 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1961 break;
1962 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 1963 if (tlv_len != sizeof(u32))
1964 goto invalid_tlv_len;
1965 pieces->init_errlog_ptr =
ad8d8333 1966 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1967 break;
1968 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 1969 if (tlv_len != sizeof(u32))
1970 goto invalid_tlv_len;
1971 pieces->inst_evtlog_ptr =
ad8d8333 1972 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1973 break;
1974 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 1975 if (tlv_len != sizeof(u32))
1976 goto invalid_tlv_len;
1977 pieces->inst_evtlog_size =
ad8d8333 1978 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1979 break;
1980 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 1981 if (tlv_len != sizeof(u32))
1982 goto invalid_tlv_len;
1983 pieces->inst_errlog_ptr =
ad8d8333 1984 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 1985 break;
c8312fac
WYG		 1986 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1987 if (tlv_len)
704da534
JB		 1988 goto invalid_tlv_len;
1989 priv->enhance_sensitivity_table = true;
c8312fac 1990 break;
6a822d06 1991 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 1992 if (tlv_len != sizeof(u32))
1993 goto invalid_tlv_len;
1994 capa->standard_phy_calibration_size =
6a822d06
WYG		 1995 le32_to_cpup((__le32 *)tlv_data);
1996 break;
dd7a2509 1997 default:
ad8d8333 1998 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 1999 break;
2000 }
2001 }
2002
ad8d8333
WYG		 2003 if (len) {
2004 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2005 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 2006 return -EINVAL;
ad8d8333 2007 }
dd7a2509 2008
704da534
JB		 2009 return 0;
2010
2011 invalid_tlv_len:
2012 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2013 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2014
2015 return -EINVAL;
dd7a2509
JB		 2016}
2017
b481de9c 2018/**
b08dfd04 2019 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 2020 *
b08dfd04
JB		 2021 * If loaded successfully, copies the firmware into buffers
2022 * for the card to fetch (via DMA).
b481de9c 2023 */
b08dfd04 2024static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 2025{
b08dfd04 2026 struct iwl_priv *priv = context;
cc0f555d 2027 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 2028 int err;
2029 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 2030 const unsigned int api_max = priv->cfg->ucode_api_max;
2031 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 2032 u32 api_ver;
3e4de761 2033 char buildstr[25];
0e9a44dc 2034 u32 build;
dd7a2509
JB		 2035 struct iwlagn_ucode_capabilities ucode_capa = {
2036 .max_probe_length = 200,
6a822d06
WYG		 2037 .standard_phy_calibration_size =
2038 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 2039 };
0e9a44dc
JB		 2040
2041 memset(&pieces, 0, sizeof(pieces));
b481de9c 2042
b08dfd04 2043 if (!ucode_raw) {
39396085
JS		 2044 if (priv->fw_index <= priv->cfg->ucode_api_max)
2045 IWL_ERR(priv,
2046 "request for firmware file '%s' failed.\n",
2047 priv->firmware_name);
b08dfd04 2048 goto try_again;
b481de9c
ZY		 2049 }
2050
b08dfd04
JB		 2051 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2052 priv->firmware_name, ucode_raw->size);
b481de9c 2053
22adba2a
JB		 2054 /* Make sure that we got at least the API version number */
2055 if (ucode_raw->size < 4) {
15b1687c 2056 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 2057 goto try_again;
b481de9c
ZY		 2058 }
2059
2060 /* Data from ucode file: header followed by uCode images */
cc0f555d 2061 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2062
0e9a44dc
JB		 2063 if (ucode->ver)
2064 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2065 else
dd7a2509
JB		 2066 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2067 &ucode_capa);
22adba2a 2068
0e9a44dc
JB		 2069 if (err)
2070 goto try_again;
b481de9c 2071
a0987a8d 2072 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 2073 build = pieces.build;
a0987a8d 2074
0e9a44dc
JB		 2075 /*
2076 * api_ver should match the api version forming part of the
2077 * firmware filename ... but we don't check for that and only rely
2078 * on the API version read from firmware header from here on forward
2079 */
a0987a8d 2080 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2081 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 2082 "Driver supports v%u, firmware is v%u.\n",
2083 api_max, api_ver);
b08dfd04 2084 goto try_again;
a0987a8d 2085 }
b08dfd04 2086
a0987a8d 2087 if (api_ver != api_max)
978785a3 2088 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 2089 "got v%u. New firmware can be obtained "
2090 "from http://www.intellinuxwireless.org.\n",
2091 api_max, api_ver);
2092
3e4de761 2093 if (build)
39396085
JS		 2094 sprintf(buildstr, " build %u%s", build,
2095 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2096 ? " (EXP)" : "");
3e4de761
JB		 2097 else
2098 buildstr[0] = '\0';
2099
2100 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2101 IWL_UCODE_MAJOR(priv->ucode_ver),
2102 IWL_UCODE_MINOR(priv->ucode_ver),
2103 IWL_UCODE_API(priv->ucode_ver),
2104 IWL_UCODE_SERIAL(priv->ucode_ver),
2105 buildstr);
a0987a8d 2106
5ebeb5a6
RC		 2107 snprintf(priv->hw->wiphy->fw_version,
2108 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2109 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2110 IWL_UCODE_MAJOR(priv->ucode_ver),
2111 IWL_UCODE_MINOR(priv->ucode_ver),
2112 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2113 IWL_UCODE_SERIAL(priv->ucode_ver),
2114 buildstr);
b481de9c 2115
b08dfd04
JB		 2116 /*
2117 * For any of the failures below (before allocating pci memory)
2118 * we will try to load a version with a smaller API -- maybe the
2119 * user just got a corrupted version of the latest API.
2120 */
2121
0e9a44dc
JB		 2122 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2123 priv->ucode_ver);
2124 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2125 pieces.inst_size);
2126 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2127 pieces.data_size);
2128 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2129 pieces.init_size);
2130 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2131 pieces.init_data_size);
2132 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2133 pieces.boot_size);
b481de9c
ZY		 2134
2135 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2136 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2137 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2138 pieces.inst_size);
b08dfd04 2139 goto try_again;
b481de9c
ZY		 2140 }
2141
0e9a44dc
JB		 2142 if (pieces.data_size > priv->hw_params.max_data_size) {
2143 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2144 pieces.data_size);
b08dfd04 2145 goto try_again;
b481de9c 2146 }
0e9a44dc
JB		 2147
2148 if (pieces.init_size > priv->hw_params.max_inst_size) {
2149 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2150 pieces.init_size);
b08dfd04 2151 goto try_again;
b481de9c 2152 }
0e9a44dc
JB		 2153
2154 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2155 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2156 pieces.init_data_size);
b08dfd04 2157 goto try_again;
b481de9c 2158 }
0e9a44dc
JB		 2159
2160 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2161 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2162 pieces.boot_size);
b08dfd04 2163 goto try_again;
b481de9c
ZY		 2164 }
2165
2166 /* Allocate ucode buffers for card's bus-master loading ... */
2167
2168 /* Runtime instructions and 2 copies of data:
2169 * 1) unmodified from disk
2170 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2171 priv->ucode_code.len = pieces.inst_size;
98c92211 2172 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2173
0e9a44dc 2174 priv->ucode_data.len = pieces.data_size;
98c92211 2175 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2176
0e9a44dc 2177 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2178 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2179
1f304e4e
ZY		 2180 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2181 !priv->ucode_data_backup.v_addr)
2182 goto err_pci_alloc;
2183
b481de9c 2184 /* Initialization instructions and data */
0e9a44dc
JB		 2185 if (pieces.init_size && pieces.init_data_size) {
2186 priv->ucode_init.len = pieces.init_size;
98c92211 2187 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2188
0e9a44dc 2189 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2190 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2191
2192 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2193 goto err_pci_alloc;
2194 }
b481de9c
ZY		 2195
2196 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2197 if (pieces.boot_size) {
2198 priv->ucode_boot.len = pieces.boot_size;
98c92211 2199 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2200
90e759d1
TW		 2201 if (!priv->ucode_boot.v_addr)
2202 goto err_pci_alloc;
2203 }
b481de9c 2204
b2e640d4
JB		 2205 /* Now that we can no longer fail, copy information */
2206
2207 /*
2208 * The (size - 16) / 12 formula is based on the information recorded
2209 * for each event, which is of mode 1 (including timestamp) for all
2210 * new microcodes that include this information.
2211 */
2212 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2213 if (pieces.init_evtlog_size)
2214 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2215 else
2216 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2217 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2218 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2219 if (pieces.inst_evtlog_size)
2220 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2221 else
2222 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2223 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2224
b481de9c
ZY		 2225 /* Copy images into buffers for card's bus-master reads ... */
2226
2227 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2228 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2229 pieces.inst_size);
2230 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2231
e1623446 2232 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2233 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2234
0e9a44dc
JB		 2235 /*
2236 * Runtime data
2237 * NOTE: Copy into backup buffer will be done in iwl_up()
2238 */
2239 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2240 pieces.data_size);
2241 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2242 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2243
2244 /* Initialization instructions */
2245 if (pieces.init_size) {
e1623446 2246 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2247 pieces.init_size);
2248 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2249 }
2250
0e9a44dc
JB		 2251 /* Initialization data */
2252 if (pieces.init_data_size) {
e1623446 2253 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2254 pieces.init_data_size);
2255 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2256 pieces.init_data_size);
b481de9c
ZY		 2257 }
2258
0e9a44dc
JB		 2259 /* Bootstrap instructions */
2260 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2261 pieces.boot_size);
2262 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2263
6a822d06
WYG		 2264 /*
2265 * figure out the offset of chain noise reset and gain commands
2266 * base on the size of standard phy calibration commands table size
2267 */
2268 if (ucode_capa.standard_phy_calibration_size >
2269 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2270 ucode_capa.standard_phy_calibration_size =
2271 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2272
2273 priv->_agn.phy_calib_chain_noise_reset_cmd =
2274 ucode_capa.standard_phy_calibration_size;
2275 priv->_agn.phy_calib_chain_noise_gain_cmd =
2276 ucode_capa.standard_phy_calibration_size + 1;
2277
b08dfd04
JB		 2278 /**************************************************
2279 * This is still part of probe() in a sense...
2280 *
2281 * 9. Setup and register with mac80211 and debugfs
2282 **************************************************/
dd7a2509 2283 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2284 if (err)
2285 goto out_unbind;
2286
2287 err = iwl_dbgfs_register(priv, DRV_NAME);
2288 if (err)
2289 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2290
7d47618a
EG		 2291 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2292 &iwl_attribute_group);
2293 if (err) {
2294 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2295 goto out_unbind;
2296 }
2297
b481de9c
ZY		 2298 /* We have our copies now, allow OS release its copies */
2299 release_firmware(ucode_raw);
a15707d8 2300 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2301 return;
2302
2303 try_again:
2304 /* try next, if any */
2305 if (iwl_request_firmware(priv, false))
2306 goto out_unbind;
2307 release_firmware(ucode_raw);
2308 return;
b481de9c
ZY		 2309
2310 err_pci_alloc:
15b1687c 2311 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2312 iwl_dealloc_ucode_pci(priv);
b08dfd04 2313 out_unbind:
a15707d8 2314 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2315 device_release_driver(&priv->pci_dev->dev);
b481de9c 2316 release_firmware(ucode_raw);
b481de9c
ZY		 2317}
2318
b7a79404
RC		 2319static const char *desc_lookup_text[] = {
2320 "OK",
2321 "FAIL",
2322 "BAD_PARAM",
2323 "BAD_CHECKSUM",
2324 "NMI_INTERRUPT_WDG",
2325 "SYSASSERT",
2326 "FATAL_ERROR",
2327 "BAD_COMMAND",
2328 "HW_ERROR_TUNE_LOCK",
2329 "HW_ERROR_TEMPERATURE",
2330 "ILLEGAL_CHAN_FREQ",
2331 "VCC_NOT_STABLE",
2332 "FH_ERROR",
2333 "NMI_INTERRUPT_HOST",
2334 "NMI_INTERRUPT_ACTION_PT",
2335 "NMI_INTERRUPT_UNKNOWN",
2336 "UCODE_VERSION_MISMATCH",
2337 "HW_ERROR_ABS_LOCK",
2338 "HW_ERROR_CAL_LOCK_FAIL",
2339 "NMI_INTERRUPT_INST_ACTION_PT",
2340 "NMI_INTERRUPT_DATA_ACTION_PT",
2341 "NMI_TRM_HW_ER",
2342 "NMI_INTERRUPT_TRM",
2343 "NMI_INTERRUPT_BREAK_POINT"
2344 "DEBUG_0",
2345 "DEBUG_1",
2346 "DEBUG_2",
2347 "DEBUG_3",
b7a79404
RC		 2348};
2349
4b58645c
JS		 2350static struct { char *name; u8 num; } advanced_lookup[] = {
2351 { "NMI_INTERRUPT_WDG", 0x34 },
2352 { "SYSASSERT", 0x35 },
2353 { "UCODE_VERSION_MISMATCH", 0x37 },
2354 { "BAD_COMMAND", 0x38 },
2355 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2356 { "FATAL_ERROR", 0x3D },
2357 { "NMI_TRM_HW_ERR", 0x46 },
2358 { "NMI_INTERRUPT_TRM", 0x4C },
2359 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2360 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2361 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2362 { "NMI_INTERRUPT_HOST", 0x66 },
2363 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2364 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2365 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2366 { "ADVANCED_SYSASSERT", 0 },
2367};
2368
2369static const char *desc_lookup(u32 num)
b7a79404 2370{
4b58645c
JS		 2371 int i;
2372 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 2373
4b58645c
JS		 2374 if (num < max)
2375 return desc_lookup_text[num];
b7a79404 2376
4b58645c
JS		 2377 max = ARRAY_SIZE(advanced_lookup) - 1;
2378 for (i = 0; i < max; i++) {
2379 if (advanced_lookup[i].num == num)
2380 break;;
2381 }
2382 return advanced_lookup[i].name;
b7a79404
RC		 2383}
2384
2385#define ERROR_START_OFFSET (1 * sizeof(u32))
2386#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2387
2388void iwl_dump_nic_error_log(struct iwl_priv *priv)
2389{
2390 u32 data2, line;
2391 u32 desc, time, count, base, data1;
2392 u32 blink1, blink2, ilink1, ilink2;
461ef382 2393 u32 pc, hcmd;
b7a79404 2394
b2e640d4 2395 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2396 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2397 if (!base)
2398 base = priv->_agn.init_errlog_ptr;
2399 } else {
b7a79404 2400 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2401 if (!base)
2402 base = priv->_agn.inst_errlog_ptr;
2403 }
b7a79404
RC		 2404
2405 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2406 IWL_ERR(priv,
2407 "Not valid error log pointer 0x%08X for %s uCode\n",
2408 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2409 return;
2410 }
2411
2412 count = iwl_read_targ_mem(priv, base);
2413
2414 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2415 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2416 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2417 priv->status, count);
2418 }
2419
2420 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
461ef382 2421 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2422 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2423 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2424 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2425 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2426 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2427 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2428 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2429 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2430 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2431
be1a71a1
JB		 2432 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2433 blink1, blink2, ilink1, ilink2);
2434
87563715 2435 IWL_ERR(priv, "Desc Time "
b7a79404 2436 "data1 data2 line\n");
87563715 2437 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2438 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2439 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2440 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2441 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2442}
2443
2444#define EVENT_START_OFFSET (4 * sizeof(u32))
2445
2446/**
2447 * iwl_print_event_log - Dump error event log to syslog
2448 *
2449 */
b03d7d0f
WYG		 2450static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2451 u32 num_events, u32 mode,
2452 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2453{
2454 u32 i;
2455 u32 base; /* SRAM byte address of event log header */
2456 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2457 u32 ptr; /* SRAM byte address of log data */
2458 u32 ev, time, data; /* event log data */
e5854471 2459 unsigned long reg_flags;
b7a79404
RC		 2460
2461 if (num_events == 0)
b03d7d0f 2462 return pos;
b2e640d4
JB		 2463
2464 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2465 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2466 if (!base)
2467 base = priv->_agn.init_evtlog_ptr;
2468 } else {
b7a79404 2469 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2470 if (!base)
2471 base = priv->_agn.inst_evtlog_ptr;
2472 }
b7a79404
RC		 2473
2474 if (mode == 0)
2475 event_size = 2 * sizeof(u32);
2476 else
2477 event_size = 3 * sizeof(u32);
2478
2479 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2480
e5854471
BC		 2481 /* Make sure device is powered up for SRAM reads */
2482 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2483 iwl_grab_nic_access(priv);
2484
2485 /* Set starting address; reads will auto-increment */
2486 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2487 rmb();
2488
b7a79404
RC		 2489 /* "time" is actually "data" for mode 0 (no timestamp).
2490 * place event id # at far right for easier visual parsing. */
2491 for (i = 0; i < num_events; i++) {
e5854471
BC		 2492 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2493 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2494 if (mode == 0) {
2495 /* data, ev */
b03d7d0f
WYG		 2496 if (bufsz) {
2497 pos += scnprintf(*buf + pos, bufsz - pos,
2498 "EVT_LOG:0x%08x:%04u\n",
2499 time, ev);
2500 } else {
2501 trace_iwlwifi_dev_ucode_event(priv, 0,
2502 time, ev);
2503 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2504 time, ev);
2505 }
b7a79404 2506 } else {
e5854471 2507 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2508 if (bufsz) {
2509 pos += scnprintf(*buf + pos, bufsz - pos,
2510 "EVT_LOGT:%010u:0x%08x:%04u\n",
2511 time, data, ev);
2512 } else {
2513 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2514 time, data, ev);
b03d7d0f
WYG		 2515 trace_iwlwifi_dev_ucode_event(priv, time,
2516 data, ev);
2517 }
b7a79404
RC		 2518 }
2519 }
e5854471
BC		 2520
2521 /* Allow device to power down */
2522 iwl_release_nic_access(priv);
2523 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2524 return pos;
b7a79404
RC		 2525}
2526
c341ddb2
WYG		 2527/**
2528 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2529 */
b03d7d0f
WYG		 2530static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2531 u32 num_wraps, u32 next_entry,
2532 u32 size, u32 mode,
2533 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2534{
2535 /*
2536 * display the newest DEFAULT_LOG_ENTRIES entries
2537 * i.e the entries just before the next ont that uCode would fill.
2538 */
2539 if (num_wraps) {
2540 if (next_entry < size) {
b03d7d0f
WYG		 2541 pos = iwl_print_event_log(priv,
2542 capacity - (size - next_entry),
2543 size - next_entry, mode,
2544 pos, buf, bufsz);
2545 pos = iwl_print_event_log(priv, 0,
2546 next_entry, mode,
2547 pos, buf, bufsz);
c341ddb2 2548 } else
b03d7d0f
WYG		 2549 pos = iwl_print_event_log(priv, next_entry - size,
2550 size, mode, pos, buf, bufsz);
c341ddb2 2551 } else {
b03d7d0f
WYG		 2552 if (next_entry < size) {
2553 pos = iwl_print_event_log(priv, 0, next_entry,
2554 mode, pos, buf, bufsz);
2555 } else {
2556 pos = iwl_print_event_log(priv, next_entry - size,
2557 size, mode, pos, buf, bufsz);
2558 }
c341ddb2 2559 }
b03d7d0f 2560 return pos;
c341ddb2
WYG		 2561}
2562
c341ddb2
WYG		 2563#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2564
b03d7d0f
WYG		 2565int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2566 char **buf, bool display)
b7a79404
RC		 2567{
2568 u32 base; /* SRAM byte address of event log header */
2569 u32 capacity; /* event log capacity in # entries */
2570 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2571 u32 num_wraps; /* # times uCode wrapped to top of log */
2572 u32 next_entry; /* index of next entry to be written by uCode */
2573 u32 size; /* # entries that we'll print */
b2e640d4 2574 u32 logsize;
b03d7d0f
WYG		 2575 int pos = 0;
2576 size_t bufsz = 0;
b7a79404 2577
b2e640d4 2578 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2579 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2580 logsize = priv->_agn.init_evtlog_size;
2581 if (!base)
2582 base = priv->_agn.init_evtlog_ptr;
2583 } else {
b7a79404 2584 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2585 logsize = priv->_agn.inst_evtlog_size;
2586 if (!base)
2587 base = priv->_agn.inst_evtlog_ptr;
2588 }
b7a79404
RC		 2589
2590 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2591 IWL_ERR(priv,
2592 "Invalid event log pointer 0x%08X for %s uCode\n",
2593 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2594 return -EINVAL;
b7a79404
RC		 2595 }
2596
2597 /* event log header */
2598 capacity = iwl_read_targ_mem(priv, base);
2599 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2600 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2601 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2602
b2e640d4 2603 if (capacity > logsize) {
84c40692 2604 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2605 capacity, logsize);
2606 capacity = logsize;
84c40692
BC		 2607 }
2608
b2e640d4 2609 if (next_entry > logsize) {
84c40692 2610 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2611 next_entry, logsize);
2612 next_entry = logsize;
84c40692
BC		 2613 }
2614
b7a79404
RC		 2615 size = num_wraps ? capacity : next_entry;
2616
2617 /* bail out if nothing in log */
2618 if (size == 0) {
2619 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2620 return pos;
b7a79404
RC		 2621 }
2622
f37837c9
WYG		 2623 /* enable/disable bt channel announcement */
2624 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2625
c341ddb2 2626#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2627 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2628 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2629 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2630#else
2631 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2632 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2633#endif
2634 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2635 size);
b7a79404 2636
c341ddb2 2637#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2638 if (display) {
2639 if (full_log)
2640 bufsz = capacity * 48;
2641 else
2642 bufsz = size * 48;
2643 *buf = kmalloc(bufsz, GFP_KERNEL);
2644 if (!*buf)
937c397e 2645 return -ENOMEM;
b03d7d0f 2646 }
c341ddb2
WYG		 2647 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2648 /*
2649 * if uCode has wrapped back to top of log,
2650 * start at the oldest entry,
2651 * i.e the next one that uCode would fill.
2652 */
2653 if (num_wraps)
b03d7d0f
WYG		 2654 pos = iwl_print_event_log(priv, next_entry,
2655 capacity - next_entry, mode,
2656 pos, buf, bufsz);
c341ddb2 2657 /* (then/else) start at top of log */
b03d7d0f
WYG		 2658 pos = iwl_print_event_log(priv, 0,
2659 next_entry, mode, pos, buf, bufsz);
c341ddb2 2660 } else
b03d7d0f
WYG		 2661 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2662 next_entry, size, mode,
2663 pos, buf, bufsz);
c341ddb2 2664#else
b03d7d0f
WYG		 2665 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2666 next_entry, size, mode,
2667 pos, buf, bufsz);
b7a79404 2668#endif
b03d7d0f 2669 return pos;
c341ddb2 2670}
b7a79404 2671
0975cc8f
WYG		 2672static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2673{
2674 struct iwl_ct_kill_config cmd;
2675 struct iwl_ct_kill_throttling_config adv_cmd;
2676 unsigned long flags;
2677 int ret = 0;
2678
2679 spin_lock_irqsave(&priv->lock, flags);
2680 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2681 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2682 spin_unlock_irqrestore(&priv->lock, flags);
2683 priv->thermal_throttle.ct_kill_toggle = false;
2684
2685 if (priv->cfg->support_ct_kill_exit) {
2686 adv_cmd.critical_temperature_enter =
2687 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2688 adv_cmd.critical_temperature_exit =
2689 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2690
2691 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2692 sizeof(adv_cmd), &adv_cmd);
2693 if (ret)
2694 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2695 else
2696 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2697 "succeeded, "
2698 "critical temperature enter is %d,"
2699 "exit is %d\n",
2700 priv->hw_params.ct_kill_threshold,
2701 priv->hw_params.ct_kill_exit_threshold);
2702 } else {
2703 cmd.critical_temperature_R =
2704 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2705
2706 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2707 sizeof(cmd), &cmd);
2708 if (ret)
2709 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2710 else
2711 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2712 "succeeded, "
2713 "critical temperature is %d\n",
2714 priv->hw_params.ct_kill_threshold);
2715 }
2716}
2717
b481de9c 2718/**
4a4a9e81 2719 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2720 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2721 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2722 */
4a4a9e81 2723static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2724{
57aab75a 2725 int ret = 0;
246ed355 2726 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 2727
e1623446 2728 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2729
2730 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2731 /* We had an error bringing up the hardware, so take it
2732 * all the way back down so we can try again */
e1623446 2733 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2734 goto restart;
2735 }
2736
2737 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2738 * This is a paranoid check, because we would not have gotten the
2739 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2740 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2741 /* Runtime instruction load was bad;
2742 * take it all the way back down so we can try again */
e1623446 2743 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2744 goto restart;
2745 }
2746
57aab75a
TW		 2747 ret = priv->cfg->ops->lib->alive_notify(priv);
2748 if (ret) {
39aadf8c
WT		 2749 IWL_WARN(priv,
2750 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2751 goto restart;
2752 }
2753
5b9f8cd3 2754 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2755 set_bit(STATUS_ALIVE, &priv->status);
2756
b74e31a9
WYG		 2757 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2758 /* Enable timer to monitor the driver queues */
2759 mod_timer(&priv->monitor_recover,
2760 jiffies +
2761 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2762 }
2763
fee1247a 2764 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2765 return;
2766
36d6825b 2767 ieee80211_wake_queues(priv->hw);
b481de9c 2768
470ab2dd 2769 priv->active_rate = IWL_RATES_MASK;
b481de9c 2770
2f748dec
WYG		 2771 /* Configure Tx antenna selection based on H/W config */
2772 if (priv->cfg->ops->hcmd->set_tx_ant)
2773 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2774
246ed355 2775 if (iwl_is_associated_ctx(ctx)) {
c1adf9fb 2776 struct iwl_rxon_cmd *active_rxon =
246ed355 2777 (struct iwl_rxon_cmd *)&ctx->active;
019fb97d 2778 /* apply any changes in staging */
246ed355 2779 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2780 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2781 } else {
2782 /* Initialize our rx_config data */
1dda6d28 2783 iwl_connection_init_rx_config(priv, NULL);
45823531
AK		 2784
2785 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 2786 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c
ZY		 2787 }
2788
aeb4a2ee
WYG		 2789 if (!priv->cfg->advanced_bt_coexist) {
2790 /* Configure Bluetooth device coexistence support */
2791 priv->cfg->ops->hcmd->send_bt_config(priv);
2792 }
b481de9c 2793
4a4a9e81
TW		 2794 iwl_reset_run_time_calib(priv);
2795
b481de9c 2796 /* Configure the adapter for unassociated operation */
246ed355 2797 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 2798
2799 /* At this point, the NIC is initialized and operational */
47f4a587 2800 iwl_rf_kill_ct_config(priv);
5a66926a 2801
e932a609 2802 iwl_leds_init(priv);
fe00b5a5 2803
e1623446 2804 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2805 set_bit(STATUS_READY, &priv->status);
5a66926a 2806 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2807
e312c24c 2808 iwl_power_update_mode(priv, true);
7e246191
RC		 2809 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2810
c46fbefa 2811
b481de9c
ZY		 2812 return;
2813
2814 restart:
2815 queue_work(priv->workqueue, &priv->restart);
2816}
2817
4e39317d 2818static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2819
5b9f8cd3 2820static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2821{
2822 unsigned long flags;
2823 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2824
e1623446 2825 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2826
b481de9c
ZY		 2827 if (!exit_pending)
2828 set_bit(STATUS_EXIT_PENDING, &priv->status);
2829
b62177a0
SG		 2830 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2831 * to prevent rearm timer */
2832 if (priv->cfg->ops->lib->recover_from_tx_stall)
2833 del_timer_sync(&priv->monitor_recover);
2834
dcef732c 2835 iwl_clear_ucode_stations(priv, NULL);
a194e324 2836 iwl_dealloc_bcast_stations(priv);
db125c78 2837 iwl_clear_driver_stations(priv);
b481de9c 2838
a1174138 2839 /* reset BT coex data */
da5dbb97 2840 priv->bt_status = 0;
a4b96cc4 2841 priv->bt_traffic_load = priv->cfg->bt_init_traffic_load;
a1174138 2842 priv->bt_sco_active = false;
bee008b7
WYG		 2843 priv->bt_full_concurrent = false;
2844 priv->bt_ci_compliance = 0;
a1174138 2845
b481de9c
ZY		 2846 /* Unblock any waiting calls */
2847 wake_up_interruptible_all(&priv->wait_command_queue);
2848
b481de9c
ZY		 2849 /* Wipe out the EXIT_PENDING status bit if we are not actually
2850 * exiting the module */
2851 if (!exit_pending)
2852 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2853
2854 /* stop and reset the on-board processor */
3395f6e9 2855 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2856
2857 /* tell the device to stop sending interrupts */
0359facc 2858 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2859 iwl_disable_interrupts(priv);
0359facc
MA		 2860 spin_unlock_irqrestore(&priv->lock, flags);
2861 iwl_synchronize_irq(priv);
b481de9c
ZY		 2862
2863 if (priv->mac80211_registered)
2864 ieee80211_stop_queues(priv->hw);
2865
5b9f8cd3 2866 /* If we have not previously called iwl_init() then
a60e77e5 2867 * clear all bits but the RF Kill bit and return */
fee1247a 2868 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2869 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2870 STATUS_RF_KILL_HW |
9788864e
RC		 2871 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2872 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2873 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2874 STATUS_EXIT_PENDING;
b481de9c
ZY		 2875 goto exit;
2876 }
2877
6da3a13e 2878 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2879 * bit and continue taking the NIC down. */
b481de9c
ZY		 2880 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2881 STATUS_RF_KILL_HW |
9788864e
RC		 2882 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2883 STATUS_GEO_CONFIGURED |
b481de9c 2884 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2885 STATUS_FW_ERROR |
2886 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2887 STATUS_EXIT_PENDING;
b481de9c 2888
ef850d7c
MA		 2889 /* device going down, Stop using ICT table */
2890 iwl_disable_ict(priv);
b481de9c 2891
74bcdb33 2892 iwlagn_txq_ctx_stop(priv);
54b81550 2893 iwlagn_rxq_stop(priv);
b481de9c 2894
309e731a
BC		 2895 /* Power-down device's busmaster DMA clocks */
2896 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2897 udelay(5);
2898
309e731a
BC		 2899 /* Make sure (redundant) we've released our request to stay awake */
2900 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2901
4d2ccdb9
BC		 2902 /* Stop the device, and put it in low power state */
2903 priv->cfg->ops->lib->apm_ops.stop(priv);
2904
b481de9c 2905 exit:
885ba202 2906 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 2907
2908 if (priv->ibss_beacon)
2909 dev_kfree_skb(priv->ibss_beacon);
2910 priv->ibss_beacon = NULL;
2911
2912 /* clear out any free frames */
fcab423d 2913 iwl_clear_free_frames(priv);
b481de9c
ZY		 2914}
2915
5b9f8cd3 2916static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2917{
2918 mutex_lock(&priv->mutex);
5b9f8cd3 2919 __iwl_down(priv);
b481de9c 2920 mutex_unlock(&priv->mutex);
b24d22b1 2921
4e39317d 2922 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2923}
2924
086ed117
MA		 2925#define HW_READY_TIMEOUT (50)
2926
2927static int iwl_set_hw_ready(struct iwl_priv *priv)
2928{
2929 int ret = 0;
2930
2931 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2932 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2933
2934 /* See if we got it */
2935 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2936 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2937 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2938 HW_READY_TIMEOUT);
2939 if (ret != -ETIMEDOUT)
2940 priv->hw_ready = true;
2941 else
2942 priv->hw_ready = false;
2943
2944 IWL_DEBUG_INFO(priv, "hardware %s\n",
2945 (priv->hw_ready == 1) ? "ready" : "not ready");
2946 return ret;
2947}
2948
2949static int iwl_prepare_card_hw(struct iwl_priv *priv)
2950{
2951 int ret = 0;
2952
91dd6c27 2953 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2954
3354a0f6
MA		 2955 ret = iwl_set_hw_ready(priv);
2956 if (priv->hw_ready)
2957 return ret;
2958
2959 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 2960 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2961 CSR_HW_IF_CONFIG_REG_PREPARE);
2962
2963 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2964 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2965 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2966
3354a0f6 2967 /* HW should be ready by now, check again. */
086ed117
MA		 2968 if (ret != -ETIMEDOUT)
2969 iwl_set_hw_ready(priv);
2970
2971 return ret;
2972}
2973
b481de9c
ZY		 2974#define MAX_HW_RESTARTS 5
2975
5b9f8cd3 2976static int __iwl_up(struct iwl_priv *priv)
b481de9c 2977{
a194e324 2978 struct iwl_rxon_context *ctx;
57aab75a
TW		 2979 int i;
2980 int ret;
b481de9c
ZY		 2981
2982 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2983 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 2984 return -EIO;
2985 }
2986
e903fbd4 2987 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2988 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 2989 return -EIO;
2990 }
2991
a194e324
JB		 2992 for_each_context(priv, ctx) {
2993 ret = iwl_alloc_bcast_station(priv, ctx, true);
2994 if (ret) {
2995 iwl_dealloc_bcast_stations(priv);
2996 return ret;
2997 }
2998 }
2c810ccd 2999
086ed117
MA		 3000 iwl_prepare_card_hw(priv);
3001
3002 if (!priv->hw_ready) {
3003 IWL_WARN(priv, "Exit HW not ready\n");
3004 return -EIO;
3005 }
3006
e655b9f0 3007 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 3008 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 3009 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3010 else
e655b9f0 3011 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3012
c1842d61 3013 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 3014 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3015
5b9f8cd3 3016 iwl_enable_interrupts(priv);
a60e77e5 3017 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 3018 return 0;
b481de9c
ZY		 3019 }
3020
3395f6e9 3021 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 3022
13bb9483 3023 /* must be initialised before iwl_hw_nic_init */
751ca305
JB		 3024 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3025 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3026 else
3027 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
13bb9483 3028
74bcdb33 3029 ret = iwlagn_hw_nic_init(priv);
57aab75a 3030 if (ret) {
15b1687c 3031 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 3032 return ret;
b481de9c
ZY		 3033 }
3034
3035 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3036 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3037 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 3038 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3039
3040 /* clear (again), then enable host interrupts */
3395f6e9 3041 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 3042 iwl_enable_interrupts(priv);
b481de9c
ZY		 3043
3044 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3045 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3046 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3047
3048 /* Copy original ucode data image from disk into backup cache.
3049 * This will be used to initialize the on-board processor's
3050 * data SRAM for a clean start when the runtime program first loads. */
3051 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 3052 priv->ucode_data.len);
b481de9c 3053
b481de9c
ZY		 3054 for (i = 0; i < MAX_HW_RESTARTS; i++) {
3055
b481de9c
ZY		 3056 /* load bootstrap state machine,
3057 * load bootstrap program into processor's memory,
3058 * prepare to load the "initialize" uCode */
57aab75a 3059 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 3060
57aab75a 3061 if (ret) {
15b1687c
WT		 3062 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3063 ret);
b481de9c
ZY		 3064 continue;
3065 }
3066
3067 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 3068 iwl_nic_start(priv);
b481de9c 3069
e1623446 3070 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 3071
3072 return 0;
3073 }
3074
3075 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 3076 __iwl_down(priv);
64e72c3e 3077 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 3078
3079 /* tried to restart and config the device for as long as our
3080 * patience could withstand */
15b1687c 3081 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 3082 return -EIO;
3083}
3084
3085
3086/*****************************************************************************
3087 *
3088 * Workqueue callbacks
3089 *
3090 *****************************************************************************/
3091
4a4a9e81 3092static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 3093{
c79dd5b5
TW		 3094 struct iwl_priv *priv =
3095 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 3096
3097 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3098 return;
3099
3100 mutex_lock(&priv->mutex);
f3ccc08c 3101 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 3102 mutex_unlock(&priv->mutex);
3103}
3104
4a4a9e81 3105static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 3106{
c79dd5b5
TW		 3107 struct iwl_priv *priv =
3108 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 3109
3110 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3111 return;
3112
258c44a0
MA		 3113 /* enable dram interrupt */
3114 iwl_reset_ict(priv);
3115
b481de9c 3116 mutex_lock(&priv->mutex);
4a4a9e81 3117 iwl_alive_start(priv);
b481de9c
ZY		 3118 mutex_unlock(&priv->mutex);
3119}
3120
16e727e8
EG		 3121static void iwl_bg_run_time_calib_work(struct work_struct *work)
3122{
3123 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3124 run_time_calib_work);
3125
3126 mutex_lock(&priv->mutex);
3127
3128 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3129 test_bit(STATUS_SCANNING, &priv->status)) {
3130 mutex_unlock(&priv->mutex);
3131 return;
3132 }
3133
3134 if (priv->start_calib) {
7980fba5
WYG		 3135 if (priv->cfg->bt_statistics) {
3136 iwl_chain_noise_calibration(priv,
3137 (void *)&priv->_agn.statistics_bt);
3138 iwl_sensitivity_calibration(priv,
3139 (void *)&priv->_agn.statistics_bt);
3140 } else {
3141 iwl_chain_noise_calibration(priv,
3142 (void *)&priv->_agn.statistics);
3143 iwl_sensitivity_calibration(priv,
3144 (void *)&priv->_agn.statistics);
3145 }
16e727e8
EG		 3146 }
3147
3148 mutex_unlock(&priv->mutex);
16e727e8
EG		 3149}
3150
5b9f8cd3 3151static void iwl_bg_restart(struct work_struct *data)
b481de9c 3152{
c79dd5b5 3153 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 3154
3155 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3156 return;
3157
19cc1087 3158 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
8bd413e6 3159 struct iwl_rxon_context *ctx;
bee008b7
WYG		 3160 bool bt_sco, bt_full_concurrent;
3161 u8 bt_ci_compliance;
511b082d 3162 u8 bt_load;
da5dbb97 3163 u8 bt_status;
511b082d 3164
19cc1087 3165 mutex_lock(&priv->mutex);
8bd413e6
JB		 3166 for_each_context(priv, ctx)
3167 ctx->vif = NULL;
19cc1087 3168 priv->is_open = 0;
511b082d
JB		 3169
3170 /*
3171 * __iwl_down() will clear the BT status variables,
3172 * which is correct, but when we restart we really
3173 * want to keep them so restore them afterwards.
3174 *
3175 * The restart process will later pick them up and
3176 * re-configure the hw when we reconfigure the BT
3177 * command.
3178 */
3179 bt_sco = priv->bt_sco_active;
bee008b7
WYG		 3180 bt_full_concurrent = priv->bt_full_concurrent;
3181 bt_ci_compliance = priv->bt_ci_compliance;
511b082d 3182 bt_load = priv->bt_traffic_load;
da5dbb97 3183 bt_status = priv->bt_status;
511b082d 3184
a1174138 3185 __iwl_down(priv);
511b082d
JB		 3186
3187 priv->bt_sco_active = bt_sco;
bee008b7
WYG		 3188 priv->bt_full_concurrent = bt_full_concurrent;
3189 priv->bt_ci_compliance = bt_ci_compliance;
511b082d 3190 priv->bt_traffic_load = bt_load;
da5dbb97 3191 priv->bt_status = bt_status;
511b082d 3192
19cc1087 3193 mutex_unlock(&priv->mutex);
a1174138 3194 iwl_cancel_deferred_work(priv);
19cc1087
JB		 3195 ieee80211_restart_hw(priv->hw);
3196 } else {
3197 iwl_down(priv);
80676518
JB		 3198
3199 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3200 return;
3201
3202 mutex_lock(&priv->mutex);
3203 __iwl_up(priv);
3204 mutex_unlock(&priv->mutex);
19cc1087 3205 }
b481de9c
ZY		 3206}
3207
5b9f8cd3 3208static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3209{
c79dd5b5
TW		 3210 struct iwl_priv *priv =
3211 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3212
3213 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3214 return;
3215
3216 mutex_lock(&priv->mutex);
54b81550 3217 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3218 mutex_unlock(&priv->mutex);
3219}
3220
7878a5a4
MA		 3221#define IWL_DELAY_NEXT_SCAN (HZ*2)
3222
1dda6d28 3223void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3224{
246ed355 3225 struct iwl_rxon_context *ctx;
b481de9c 3226 struct ieee80211_conf *conf = NULL;
857485c0 3227 int ret = 0;
b481de9c 3228
1dda6d28
JB		 3229 if (!vif || !priv->is_open)
3230 return;
3231
246ed355
JB		 3232 ctx = iwl_rxon_ctx_from_vif(vif);
3233
1dda6d28 3234 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 3235 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 3236 return;
3237 }
3238
b481de9c
ZY		 3239 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3240 return;
3241
2a421b91 3242 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 3243
b481de9c
ZY		 3244 conf = ieee80211_get_hw_conf(priv->hw);
3245
246ed355
JB		 3246 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3247 iwlcore_commit_rxon(priv, ctx);
b481de9c 3248
948f5a2f 3249 ret = iwl_send_rxon_timing(priv, vif);
857485c0 3250 if (ret)
8f2d3d2a 3251 IWL_WARN(priv, "RXON timing - "
b481de9c
ZY		 3252 "Attempting to continue.\n");
3253
246ed355 3254 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3255
42eb7c64 3256 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 3257
45823531 3258 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3259 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
45823531 3260
246ed355 3261 ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3262
e1623446 3263 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3264 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3265
c213d745 3266 if (vif->bss_conf.use_short_preamble)
246ed355 3267 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3268 else
246ed355 3269 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3270
246ed355 3271 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3272 if (vif->bss_conf.use_short_slot)
246ed355 3273 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3274 else
246ed355 3275 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3276 }
3277
246ed355 3278 iwlcore_commit_rxon(priv, ctx);
b481de9c 3279
fe6b23dd 3280 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
246ed355 3281 vif->bss_conf.aid, ctx->active.bssid_addr);
fe6b23dd 3282
1dda6d28 3283 switch (vif->type) {
05c914fe 3284 case NL80211_IFTYPE_STATION:
b481de9c 3285 break;
05c914fe 3286 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 3287 iwl_send_beacon_cmd(priv);
b481de9c 3288 break;
b481de9c 3289 default:
15b1687c 3290 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 3291 __func__, vif->type);
b481de9c
ZY		 3292 break;
3293 }
3294
04816448
GE		 3295 /* the chain noise calibration will enabled PM upon completion
3296 * If chain noise has already been run, then we need to enable
3297 * power management here */
3298 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 3299 iwl_power_update_mode(priv, false);
c90a74ba
EG		 3300
3301 /* Enable Rx differential gain and sensitivity calibrations */
3302 iwl_chain_noise_reset(priv);
3303 priv->start_calib = 1;
3304
508e32e1
RC		 3305}
3306
b481de9c
ZY		 3307/*****************************************************************************
3308 *
3309 * mac80211 entry point functions
3310 *
3311 *****************************************************************************/
3312
154b25ce 3313#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3314
f0b6e2e8
RC		 3315/*
3316 * Not a mac80211 entry point function, but it fits in with all the
3317 * other mac80211 functions grouped here.
3318 */
dd7a2509
JB		 3319static int iwl_mac_setup_register(struct iwl_priv *priv,
3320 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3321{
3322 int ret;
3323 struct ieee80211_hw *hw = priv->hw;
3324 hw->rate_control_algorithm = "iwl-agn-rs";
3325
3326 /* Tell mac80211 our characteristics */
3327 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8
RC		 3328 IEEE80211_HW_AMPDU_AGGREGATION |
3329 IEEE80211_HW_SPECTRUM_MGMT;
3330
3331 if (!priv->cfg->broken_powersave)
3332 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3333 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3334
ba37a3d0
JB		 3335 if (priv->cfg->sku & IWL_SKU_N)
3336 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3337 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3338
8d9698b3 3339 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3340 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3341
f0b6e2e8
RC		 3342 hw->wiphy->interface_modes =
3343 BIT(NL80211_IFTYPE_STATION) |
3344 BIT(NL80211_IFTYPE_ADHOC);
3345
f6c8f152 3346 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3347 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3348
3349 /*
3350 * For now, disable PS by default because it affects
3351 * RX performance significantly.
3352 */
5be83de5 3353 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3354
1382c71c 3355 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3356 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3357 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3358
3359 /* Default value; 4 EDCA QOS priorities */
3360 hw->queues = 4;
3361
3362 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3363
3364 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3365 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3366 &priv->bands[IEEE80211_BAND_2GHZ];
3367 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3368 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3369 &priv->bands[IEEE80211_BAND_5GHZ];
3370
3371 ret = ieee80211_register_hw(priv->hw);
3372 if (ret) {
3373 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3374 return ret;
3375 }
3376 priv->mac80211_registered = 1;
3377
3378 return 0;
3379}
3380
3381
5b9f8cd3 3382static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 3383{
c79dd5b5 3384 struct iwl_priv *priv = hw->priv;
5a66926a 3385 int ret;
b481de9c 3386
e1623446 3387 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3388
3389 /* we should be verifying the device is ready to be opened */
3390 mutex_lock(&priv->mutex);
5b9f8cd3 3391 ret = __iwl_up(priv);
b481de9c 3392 mutex_unlock(&priv->mutex);
5a66926a 3393
e655b9f0 3394 if (ret)
6cd0b1cb 3395 return ret;
e655b9f0 3396
c1842d61
TW		 3397 if (iwl_is_rfkill(priv))
3398 goto out;
3399
e1623446 3400 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3401
fe9b6b72 3402 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3403 * mac80211 will not be run successfully. */
154b25ce
EG		 3404 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3405 test_bit(STATUS_READY, &priv->status),
3406 UCODE_READY_TIMEOUT);
3407 if (!ret) {
3408 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3409 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3410 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3411 return -ETIMEDOUT;
5a66926a 3412 }
fe9b6b72 3413 }
0a078ffa 3414
e932a609
JB		 3415 iwl_led_start(priv);
3416
c1842d61 3417out:
0a078ffa 3418 priv->is_open = 1;
e1623446 3419 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3420 return 0;
3421}
3422
5b9f8cd3 3423static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 3424{
c79dd5b5 3425 struct iwl_priv *priv = hw->priv;
b481de9c 3426
e1623446 3427 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3428
19cc1087 3429 if (!priv->is_open)
e655b9f0 3430 return;
e655b9f0 3431
b481de9c 3432 priv->is_open = 0;
5a66926a 3433
5bddf549 3434 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY		 3435 /* stop mac, cancel any scan request and clear
3436 * RXON_FILTER_ASSOC_MSK BIT
3437 */
5a66926a 3438 mutex_lock(&priv->mutex);
2a421b91 3439 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3440 mutex_unlock(&priv->mutex);
fde3571f
MA		 3441 }
3442
5b9f8cd3 3443 iwl_down(priv);
5a66926a
ZY		 3444
3445 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3446
3447 /* enable interrupts again in order to receive rfkill changes */
3448 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3449 iwl_enable_interrupts(priv);
948c171c 3450
e1623446 3451 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3452}
3453
5b9f8cd3 3454static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3455{
c79dd5b5 3456 struct iwl_priv *priv = hw->priv;
b481de9c 3457
e1623446 3458 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3459
e1623446 3460 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3461 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3462
74bcdb33 3463 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3464 dev_kfree_skb_any(skb);
3465
e1623446 3466 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3467 return NETDEV_TX_OK;
b481de9c
ZY		 3468}
3469
1dda6d28 3470void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3471{
246ed355 3472 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
857485c0 3473 int ret = 0;
b481de9c 3474
d986bcd1 3475 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 3476 return;
3477
3478 /* The following should be done only at AP bring up */
246ed355 3479 if (!iwl_is_associated_ctx(ctx)) {
b481de9c
ZY		 3480
3481 /* RXON - unassoc (to set timing command) */
246ed355
JB		 3482 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3483 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 3484
3485 /* RXON Timing */
948f5a2f 3486 ret = iwl_send_rxon_timing(priv, vif);
857485c0 3487 if (ret)
8f2d3d2a 3488 IWL_WARN(priv, "RXON timing failed - "
b481de9c
ZY		 3489 "Attempting to continue.\n");
3490
f513dfff
DH		 3491 /* AP has all antennas */
3492 priv->chain_noise_data.active_chains =
3493 priv->hw_params.valid_rx_ant;
3494 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531 3495 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3496 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c 3497
246ed355 3498 ctx->staging.assoc_id = 0;
1dda6d28 3499
c213d745 3500 if (vif->bss_conf.use_short_preamble)
246ed355 3501 ctx->staging.flags |=
b481de9c
ZY		 3502 RXON_FLG_SHORT_PREAMBLE_MSK;
3503 else
246ed355 3504 ctx->staging.flags &=
b481de9c
ZY		 3505 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3506
246ed355 3507 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3508 if (vif->bss_conf.use_short_slot)
246ed355 3509 ctx->staging.flags |=
b481de9c
ZY		 3510 RXON_FLG_SHORT_SLOT_MSK;
3511 else
246ed355 3512 ctx->staging.flags &=
b481de9c 3513 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3514 }
3515 /* restore RXON assoc */
246ed355
JB		 3516 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3517 iwlcore_commit_rxon(priv, ctx);
e1493deb 3518 }
5b9f8cd3 3519 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3520
3521 /* FIXME - we need to add code here to detect a totally new
3522 * configuration, reset the AP, unassoc, rxon timing, assoc,
3523 * clear sta table, add BCAST sta... */
3524}
3525
5b9f8cd3 3526static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3527 struct ieee80211_vif *vif,
3528 struct ieee80211_key_conf *keyconf,
3529 struct ieee80211_sta *sta,
3530 u32 iv32, u16 *phase1key)
ab885f8c 3531{
ab885f8c 3532
9f58671e 3533 struct iwl_priv *priv = hw->priv;
a194e324
JB		 3534 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3535
e1623446 3536 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3537
a194e324 3538 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
b3fbdcf4 3539 iv32, phase1key);
ab885f8c 3540
e1623446 3541 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3542}
3543
5b9f8cd3 3544static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3545 struct ieee80211_vif *vif,
3546 struct ieee80211_sta *sta,
b481de9c
ZY		 3547 struct ieee80211_key_conf *key)
3548{
c79dd5b5 3549 struct iwl_priv *priv = hw->priv;
a194e324 3550 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
42986796
WT		 3551 int ret;
3552 u8 sta_id;
3553 bool is_default_wep_key = false;
b481de9c 3554
e1623446 3555 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3556
90e8e424 3557 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3558 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3559 return -EOPNOTSUPP;
3560 }
b481de9c 3561
a194e324 3562 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
0af8bcae
JB		 3563 if (sta_id == IWL_INVALID_STATION)
3564 return -EINVAL;
b481de9c 3565
6974e363 3566 mutex_lock(&priv->mutex);
2a421b91 3567 iwl_scan_cancel_timeout(priv, 100);
6974e363 3568
a90178fa
JB		 3569 /*
3570 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3571 * so far, we are in legacy wep mode (group key only), otherwise we are
3572 * in 1X mode.
a90178fa
JB		 3573 * In legacy wep mode, we use another host command to the uCode.
3574 */
97359d12
JB		 3575 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3576 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 3577 !sta) {
6974e363
EG		 3578 if (cmd == SET_KEY)
3579 is_default_wep_key = !priv->key_mapping_key;
3580 else
ccc038ab
EG		 3581 is_default_wep_key =
3582 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3583 }
052c4b9f 3584
b481de9c 3585 switch (cmd) {
deb09c43 3586 case SET_KEY:
6974e363 3587 if (is_default_wep_key)
2995bafa 3588 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
deb09c43 3589 else
a194e324
JB		 3590 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3591 key, sta_id);
deb09c43 3592
e1623446 3593 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3594 break;
3595 case DISABLE_KEY:
6974e363
EG		 3596 if (is_default_wep_key)
3597 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 3598 else
3ec47732 3599 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 3600
e1623446 3601 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3602 break;
3603 default:
deb09c43 3604 ret = -EINVAL;
b481de9c
ZY		 3605 }
3606
72e15d71 3607 mutex_unlock(&priv->mutex);
e1623446 3608 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3609
deb09c43 3610 return ret;
b481de9c
ZY		 3611}
3612
5b9f8cd3 3613static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3614 struct ieee80211_vif *vif,
832f47e3
JB		 3615 enum ieee80211_ampdu_mlme_action action,
3616 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3617{
3618 struct iwl_priv *priv = hw->priv;
4620fefa 3619 int ret = -EINVAL;
d783b061 3620
e1623446 3621 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3622 sta->addr, tid);
d783b061
TW		 3623
3624 if (!(priv->cfg->sku & IWL_SKU_N))
3625 return -EACCES;
3626
4620fefa
JB		 3627 mutex_lock(&priv->mutex);
3628
d783b061
TW		 3629 switch (action) {
3630 case IEEE80211_AMPDU_RX_START:
e1623446 3631 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3632 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3633 break;
d783b061 3634 case IEEE80211_AMPDU_RX_STOP:
e1623446 3635 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3636 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3637 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3638 ret = 0;
3639 break;
d783b061 3640 case IEEE80211_AMPDU_TX_START:
e1623446 3641 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3642 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3643 if (ret == 0) {
3644 priv->_agn.agg_tids_count++;
3645 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3646 priv->_agn.agg_tids_count);
3647 }
4620fefa 3648 break;
d783b061 3649 case IEEE80211_AMPDU_TX_STOP:
e1623446 3650 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3651 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3652 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3653 priv->_agn.agg_tids_count--;
3654 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3655 priv->_agn.agg_tids_count);
3656 }
5c2207c6 3657 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 3658 ret = 0;
94597ab2
JB		 3659 if (priv->cfg->use_rts_for_aggregation) {
3660 struct iwl_station_priv *sta_priv =
3661 (void *) sta->drv_priv;
3662 /*
3663 * switch off RTS/CTS if it was previously enabled
3664 */
3665
3666 sta_priv->lq_sta.lq.general_params.flags &=
3667 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3668 iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3669 CMD_ASYNC, false);
3670 }
4620fefa 3671 break;
f0527971 3672 case IEEE80211_AMPDU_TX_OPERATIONAL:
94597ab2
JB		 3673 if (priv->cfg->use_rts_for_aggregation) {
3674 struct iwl_station_priv *sta_priv =
3675 (void *) sta->drv_priv;
3676
cfecc6b4
WYG		 3677 /*
3678 * switch to RTS/CTS if it is the prefer protection
3679 * method for HT traffic
3680 */
94597ab2
JB		 3681
3682 sta_priv->lq_sta.lq.general_params.flags |=
3683 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3684 iwl_send_lq_cmd(priv, &sta_priv->lq_sta.lq,
3685 CMD_ASYNC, false);
cfecc6b4
WYG		 3686 }
3687 ret = 0;
d783b061
TW		 3688 break;
3689 }
4620fefa
JB		 3690 mutex_unlock(&priv->mutex);
3691
3692 return ret;
d783b061 3693}
9f58671e 3694
6ab10ff8
JB		 3695static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3696 struct ieee80211_vif *vif,
3697 enum sta_notify_cmd cmd,
3698 struct ieee80211_sta *sta)
3699{
3700 struct iwl_priv *priv = hw->priv;
3701 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3702 int sta_id;
3703
6ab10ff8 3704 switch (cmd) {
6ab10ff8
JB		 3705 case STA_NOTIFY_SLEEP:
3706 WARN_ON(!sta_priv->client);
3707 sta_priv->asleep = true;
3708 if (atomic_read(&sta_priv->pending_frames) > 0)
3709 ieee80211_sta_block_awake(hw, sta, true);
3710 break;
3711 case STA_NOTIFY_AWAKE:
3712 WARN_ON(!sta_priv->client);
49dcc819
DH		 3713 if (!sta_priv->asleep)
3714 break;
6ab10ff8 3715 sta_priv->asleep = false;
2a87c26b 3716 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3717 if (sta_id != IWL_INVALID_STATION)
3718 iwl_sta_modify_ps_wake(priv, sta_id);
3719 break;
3720 default:
3721 break;
3722 }
3723}
3724
fe6b23dd
RC		 3725static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3726 struct ieee80211_vif *vif,
3727 struct ieee80211_sta *sta)
3728{
3729 struct iwl_priv *priv = hw->priv;
3730 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
a194e324 3731 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
eafdfbd3 3732 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3733 int ret;
3734 u8 sta_id;
3735
3736 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3737 sta->addr);
da5ae1cf
RC		 3738 mutex_lock(&priv->mutex);
3739 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3740 sta->addr);
3741 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3742
3743 atomic_set(&sta_priv->pending_frames, 0);
3744 if (vif->type == NL80211_IFTYPE_AP)
3745 sta_priv->client = true;
3746
a194e324
JB		 3747 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3748 is_ap, &sta->ht_cap, &sta_id);
fe6b23dd
RC		 3749 if (ret) {
3750 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3751 sta->addr, ret);
3752 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3753 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3754 return ret;
3755 }
3756
fd1af15d
JB		 3757 sta_priv->common.sta_id = sta_id;
3758
fe6b23dd 3759 /* Initialize rate scaling */
91dd6c27 3760 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3761 sta->addr);
3762 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3763 mutex_unlock(&priv->mutex);
fe6b23dd 3764
fd1af15d 3765 return 0;
fe6b23dd
RC		 3766}
3767
79d07325
WYG		 3768static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3769 struct ieee80211_channel_switch *ch_switch)
3770{
3771 struct iwl_priv *priv = hw->priv;
3772 const struct iwl_channel_info *ch_info;
3773 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 3774 struct ieee80211_channel *channel = ch_switch->channel;
79d07325 3775 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
246ed355
JB		 3776 /*
3777 * MULTI-FIXME
3778 * When we add support for multiple interfaces, we need to
3779 * revisit this. The channel switch command in the device
3780 * only affects the BSS context, but what does that really
3781 * mean? And what if we get a CSA on the second interface?
3782 * This needs a lot of work.
3783 */
3784 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
79d07325
WYG		 3785 u16 ch;
3786 unsigned long flags = 0;
3787
3788 IWL_DEBUG_MAC80211(priv, "enter\n");
3789
3790 if (iwl_is_rfkill(priv))
3791 goto out_exit;
3792
3793 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3794 test_bit(STATUS_SCANNING, &priv->status))
3795 goto out_exit;
3796
246ed355 3797 if (!iwl_is_associated_ctx(ctx))
79d07325
WYG		 3798 goto out_exit;
3799
3800 /* channel switch in progress */
3801 if (priv->switch_rxon.switch_in_progress == true)
3802 goto out_exit;
3803
3804 mutex_lock(&priv->mutex);
3805 if (priv->cfg->ops->lib->set_channel_switch) {
3806
aa2dc6b5 3807 ch = channel->hw_value;
246ed355 3808 if (le16_to_cpu(ctx->active.channel) != ch) {
79d07325 3809 ch_info = iwl_get_channel_info(priv,
aa2dc6b5 3810 channel->band,
79d07325
WYG		 3811 ch);
3812 if (!is_channel_valid(ch_info)) {
3813 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3814 goto out;
3815 }
3816 spin_lock_irqsave(&priv->lock, flags);
3817
3818 priv->current_ht_config.smps = conf->smps_mode;
3819
3820 /* Configure HT40 channels */
3821 ht_conf->is_ht = conf_is_ht(conf);
3822 if (ht_conf->is_ht) {
3823 if (conf_is_ht40_minus(conf)) {
3824 ht_conf->extension_chan_offset =
3825 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3826 ht_conf->is_40mhz = true;
3827 } else if (conf_is_ht40_plus(conf)) {
3828 ht_conf->extension_chan_offset =
3829 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3830 ht_conf->is_40mhz = true;
3831 } else {
3832 ht_conf->extension_chan_offset =
3833 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3834 ht_conf->is_40mhz = false;
3835 }
3836 } else
3837 ht_conf->is_40mhz = false;
3838
246ed355
JB		 3839 if ((le16_to_cpu(ctx->staging.channel) != ch))
3840 ctx->staging.flags = 0;
79d07325 3841
246ed355 3842 iwl_set_rxon_channel(priv, channel, ctx);
79d07325 3843 iwl_set_rxon_ht(priv, ht_conf);
246ed355 3844 iwl_set_flags_for_band(priv, ctx, channel->band,
8bd413e6 3845 ctx->vif);
79d07325
WYG		 3846 spin_unlock_irqrestore(&priv->lock, flags);
3847
3848 iwl_set_rate(priv);
3849 /*
3850 * at this point, staging_rxon has the
3851 * configuration for channel switch
3852 */
3853 if (priv->cfg->ops->lib->set_channel_switch(priv,
3854 ch_switch))
3855 priv->switch_rxon.switch_in_progress = false;
3856 }
3857 }
3858out:
3859 mutex_unlock(&priv->mutex);
3860out_exit:
3861 if (!priv->switch_rxon.switch_in_progress)
8bd413e6 3862 ieee80211_chswitch_done(ctx->vif, false);
79d07325
WYG		 3863 IWL_DEBUG_MAC80211(priv, "leave\n");
3864}
3865
8b8ab9d5
JB		 3866static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3867 unsigned int changed_flags,
3868 unsigned int *total_flags,
3869 u64 multicast)
3870{
3871 struct iwl_priv *priv = hw->priv;
3872 __le32 filter_or = 0, filter_nand = 0;
246ed355 3873 struct iwl_rxon_context *ctx;
8b8ab9d5
JB		 3874
3875#define CHK(test, flag) do { \
3876 if (*total_flags & (test)) \
3877 filter_or |= (flag); \
3878 else \
3879 filter_nand |= (flag); \
3880 } while (0)
3881
3882 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3883 changed_flags, *total_flags);
3884
3885 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3886 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3887 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3888
3889#undef CHK
3890
3891 mutex_lock(&priv->mutex);
3892
246ed355
JB		 3893 for_each_context(priv, ctx) {
3894 ctx->staging.filter_flags &= ~filter_nand;
3895 ctx->staging.filter_flags |= filter_or;
3896 iwlcore_commit_rxon(priv, ctx);
3897 }
8b8ab9d5
JB		 3898
3899 mutex_unlock(&priv->mutex);
3900
3901 /*
3902 * Receiving all multicast frames is always enabled by the
3903 * default flags setup in iwl_connection_init_rx_config()
3904 * since we currently do not support programming multicast
3905 * filters into the device.
3906 */
3907 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3908 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3909}
3910
716c74b0
WYG		 3911static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3912{
3913 struct iwl_priv *priv = hw->priv;
3914
3915 mutex_lock(&priv->mutex);
3916 IWL_DEBUG_MAC80211(priv, "enter\n");
3917
3918 /* do not support "flush" */
3919 if (!priv->cfg->ops->lib->txfifo_flush)
3920 goto done;
3921
3922 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3923 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3924 goto done;
3925 }
3926 if (iwl_is_rfkill(priv)) {
3927 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3928 goto done;
3929 }
3930
3931 /*
3932 * mac80211 will not push any more frames for transmit
3933 * until the flush is completed
3934 */
3935 if (drop) {
3936 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3937 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3938 IWL_ERR(priv, "flush request fail\n");
3939 goto done;
3940 }
3941 }
3942 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3943 iwlagn_wait_tx_queue_empty(priv);
3944done:
3945 mutex_unlock(&priv->mutex);
3946 IWL_DEBUG_MAC80211(priv, "leave\n");
3947}
3948
b481de9c
ZY		 3949/*****************************************************************************
3950 *
3951 * driver setup and teardown
3952 *
3953 *****************************************************************************/
3954
4e39317d 3955static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3956{
d21050c7 3957 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 3958
3959 init_waitqueue_head(&priv->wait_command_queue);
3960
5b9f8cd3
EG		 3961 INIT_WORK(&priv->restart, iwl_bg_restart);
3962 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3963 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3964 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 3965 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 3966 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 3967 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4a4a9e81
TW		 3968 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3969 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3970
2a421b91 3971 iwl_setup_scan_deferred_work(priv);
bb8c093b 3972
4e39317d
EG		 3973 if (priv->cfg->ops->lib->setup_deferred_work)
3974 priv->cfg->ops->lib->setup_deferred_work(priv);
3975
3976 init_timer(&priv->statistics_periodic);
3977 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3978 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3979
a9e1cb6a
WYG		 3980 init_timer(&priv->ucode_trace);
3981 priv->ucode_trace.data = (unsigned long)priv;
3982 priv->ucode_trace.function = iwl_bg_ucode_trace;
3983
b74e31a9
WYG		 3984 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3985 init_timer(&priv->monitor_recover);
3986 priv->monitor_recover.data = (unsigned long)priv;
3987 priv->monitor_recover.function =
3988 priv->cfg->ops->lib->recover_from_tx_stall;
3989 }
3990
ef850d7c
MA		 3991 if (!priv->cfg->use_isr_legacy)
3992 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3993 iwl_irq_tasklet, (unsigned long)priv);
3994 else
3995 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3996 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 3997}
3998
4e39317d 3999static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 4000{
4e39317d
EG		 4001 if (priv->cfg->ops->lib->cancel_deferred_work)
4002 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 4003
3ae6a054 4004 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 4005 cancel_delayed_work(&priv->scan_check);
88be0264 4006 cancel_work_sync(&priv->start_internal_scan);
b481de9c 4007 cancel_delayed_work(&priv->alive_start);
815e629b 4008 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 4009 cancel_work_sync(&priv->beacon_update);
bee008b7 4010 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 4011 cancel_work_sync(&priv->bt_runtime_config);
4e39317d 4012 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 4013 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY		 4014}
4015
89f186a8
RC		 4016static void iwl_init_hw_rates(struct iwl_priv *priv,
4017 struct ieee80211_rate *rates)
4018{
4019 int i;
4020
4021 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4022 rates[i].bitrate = iwl_rates[i].ieee * 5;
4023 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4024 rates[i].hw_value_short = i;
4025 rates[i].flags = 0;
4026 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4027 /*
4028 * If CCK != 1M then set short preamble rate flag.
4029 */
4030 rates[i].flags |=
4031 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4032 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4033 }
4034 }
4035}
4036
4037static int iwl_init_drv(struct iwl_priv *priv)
4038{
4039 int ret;
4040
4041 priv->ibss_beacon = NULL;
4042
89f186a8
RC		 4043 spin_lock_init(&priv->sta_lock);
4044 spin_lock_init(&priv->hcmd_lock);
4045
4046 INIT_LIST_HEAD(&priv->free_frames);
4047
4048 mutex_init(&priv->mutex);
d2dfe6df 4049 mutex_init(&priv->sync_cmd_mutex);
89f186a8 4050
89f186a8
RC		 4051 priv->ieee_channels = NULL;
4052 priv->ieee_rates = NULL;
4053 priv->band = IEEE80211_BAND_2GHZ;
4054
4055 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 4056 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 4057 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 4058 priv->_agn.agg_tids_count = 0;
89f186a8 4059
8a472da4
WYG		 4060 /* initialize force reset */
4061 priv->force_reset[IWL_RF_RESET].reset_duration =
4062 IWL_DELAY_NEXT_FORCE_RF_RESET;
4063 priv->force_reset[IWL_FW_RESET].reset_duration =
4064 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 4065
4066 /* Choose which receivers/antennas to use */
4067 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355
JB		 4068 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4069 &priv->contexts[IWL_RXON_CTX_BSS]);
89f186a8
RC		 4070
4071 iwl_init_scan_params(priv);
4072
22bf59a0
WYG		 4073 /* init bt coex */
4074 if (priv->cfg->advanced_bt_coexist) {
b6e116e8
WYG		 4075 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4076 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4077 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG		 4078 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4079 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4080 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4081 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4082 }
4083
89f186a8
RC		 4084 /* Set the tx_power_user_lmt to the lowest power level
4085 * this value will get overwritten by channel max power avg
4086 * from eeprom */
b744cb79 4087 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 4088
4089 ret = iwl_init_channel_map(priv);
4090 if (ret) {
4091 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4092 goto err;
4093 }
4094
4095 ret = iwlcore_init_geos(priv);
4096 if (ret) {
4097 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4098 goto err_free_channel_map;
4099 }
4100 iwl_init_hw_rates(priv, priv->ieee_rates);
4101
4102 return 0;
4103
4104err_free_channel_map:
4105 iwl_free_channel_map(priv);
4106err:
4107 return ret;
4108}
4109
4110static void iwl_uninit_drv(struct iwl_priv *priv)
4111{
4112 iwl_calib_free_results(priv);
4113 iwlcore_free_geos(priv);
4114 iwl_free_channel_map(priv);
811ecc99 4115 kfree(priv->scan_cmd);
89f186a8
RC		 4116}
4117
5b9f8cd3
EG		 4118static struct ieee80211_ops iwl_hw_ops = {
4119 .tx = iwl_mac_tx,
4120 .start = iwl_mac_start,
4121 .stop = iwl_mac_stop,
4122 .add_interface = iwl_mac_add_interface,
4123 .remove_interface = iwl_mac_remove_interface,
4124 .config = iwl_mac_config,
8b8ab9d5 4125 .configure_filter = iwlagn_configure_filter,
5b9f8cd3
EG		 4126 .set_key = iwl_mac_set_key,
4127 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 4128 .conf_tx = iwl_mac_conf_tx,
4129 .reset_tsf = iwl_mac_reset_tsf,
4130 .bss_info_changed = iwl_bss_info_changed,
4131 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 4132 .hw_scan = iwl_mac_hw_scan,
4133 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 4134 .sta_add = iwlagn_mac_sta_add,
4135 .sta_remove = iwl_mac_sta_remove,
79d07325 4136 .channel_switch = iwl_mac_channel_switch,
716c74b0 4137 .flush = iwl_mac_flush,
a85d7cca 4138 .tx_last_beacon = iwl_mac_tx_last_beacon,
b481de9c
ZY		 4139};
4140
3867fe04
WYG		 4141static void iwl_hw_detect(struct iwl_priv *priv)
4142{
4143 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4144 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4145 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
49ded76b 4146 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3867fe04
WYG		 4147}
4148
07d4f1ad
WYG		 4149static int iwl_set_hw_params(struct iwl_priv *priv)
4150{
4151 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4152 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4153 if (priv->cfg->mod_params->amsdu_size_8K)
4154 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4155 else
4156 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4157
4158 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4159
4160 if (priv->cfg->mod_params->disable_11n)
4161 priv->cfg->sku &= ~IWL_SKU_N;
4162
4163 /* Device-specific setup */
4164 return priv->cfg->ops->lib->set_hw_params(priv);
4165}
4166
5b9f8cd3 4167static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c 4168{
246ed355 4169 int err = 0, i;
c79dd5b5 4170 struct iwl_priv *priv;
b481de9c 4171 struct ieee80211_hw *hw;
82b9a121 4172 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 4173 unsigned long flags;
c6fa17ed 4174 u16 pci_cmd, num_mac;
b481de9c 4175
316c30d9
AK		 4176 /************************
4177 * 1. Allocating HW data
4178 ************************/
4179
6440adb5
CB		 4180 /* Disabling hardware scan means that mac80211 will perform scans
4181 * "the hard way", rather than using device's scan. */
1ea87396 4182 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 4183 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK		 4184 dev_printk(KERN_DEBUG, &(pdev->dev),
4185 "Disabling hw_scan\n");
5b9f8cd3 4186 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 4187 }
4188
5b9f8cd3 4189 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 4190 if (!hw) {
b481de9c
ZY		 4191 err = -ENOMEM;
4192 goto out;
4193 }
1d0a082d
AK		 4194 priv = hw->priv;
4195 /* At this point both hw and priv are allocated. */
4196
246ed355
JB		 4197 /*
4198 * The default context is always valid,
4199 * more may be discovered when firmware
4200 * is loaded.
4201 */
4202 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4203
4204 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4205 priv->contexts[i].ctxid = i;
4206
8f2d3d2a
JB		 4207 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4208 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4209 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 4210 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 4211 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
8f2d3d2a
JB		 4212 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 1);
4213
b481de9c
ZY		 4214 SET_IEEE80211_DEV(hw, &pdev->dev);
4215
e1623446 4216 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 4217 priv->cfg = cfg;
b481de9c 4218 priv->pci_dev = pdev;
40cefda9 4219 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 4220
bee008b7
WYG		 4221 /* is antenna coupling more than 35dB ? */
4222 priv->bt_ant_couple_ok =
4223 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4224 true : false;
4225
f37837c9
WYG		 4226 /* enable/disable bt channel announcement */
4227 priv->bt_ch_announce = iwlagn_bt_ch_announce;
4228
20594eb0
WYG		 4229 if (iwl_alloc_traffic_mem(priv))
4230 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4231
316c30d9
AK		 4232 /**************************
4233 * 2. Initializing PCI bus
4234 **************************/
1a7123cd
JL		 4235 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4236 PCIE_LINK_STATE_CLKPM);
4237
316c30d9
AK		 4238 if (pci_enable_device(pdev)) {
4239 err = -ENODEV;
4240 goto out_ieee80211_free_hw;
4241 }
4242
4243 pci_set_master(pdev);
4244
093d874c 4245 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 4246 if (!err)
093d874c 4247 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 4248 if (err) {
093d874c 4249 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4250 if (!err)
093d874c 4251 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4252 /* both attempts failed: */
316c30d9 4253 if (err) {
978785a3 4254 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 4255 goto out_pci_disable_device;
cc2a8ea8 4256 }
316c30d9
AK		 4257 }
4258
4259 err = pci_request_regions(pdev, DRV_NAME);
4260 if (err)
4261 goto out_pci_disable_device;
4262
4263 pci_set_drvdata(pdev, priv);
4264
316c30d9
AK		 4265
4266 /***********************
4267 * 3. Read REV register
4268 ***********************/
4269 priv->hw_base = pci_iomap(pdev, 0, 0);
4270 if (!priv->hw_base) {
4271 err = -ENODEV;
4272 goto out_pci_release_regions;
4273 }
4274
e1623446 4275 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 4276 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4277 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 4278
731a29b7 4279 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 4280 * we should init now
4281 */
4282 spin_lock_init(&priv->reg_lock);
731a29b7 4283 spin_lock_init(&priv->lock);
4843b5a7
RC		 4284
4285 /*
4286 * stop and reset the on-board processor just in case it is in a
4287 * strange state ... like being left stranded by a primary kernel
4288 * and this is now the kdump kernel trying to start up
4289 */
4290 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4291
b661c819 4292 iwl_hw_detect(priv);
c11362c0 4293 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 4294 priv->cfg->name, priv->hw_rev);
316c30d9 4295
e7b63581
TW		 4296 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4297 * PCI Tx retries from interfering with C3 CPU state */
4298 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4299
086ed117
MA		 4300 iwl_prepare_card_hw(priv);
4301 if (!priv->hw_ready) {
4302 IWL_WARN(priv, "Failed, HW not ready\n");
4303 goto out_iounmap;
4304 }
4305
91238714
TW		 4306 /*****************
4307 * 4. Read EEPROM
4308 *****************/
316c30d9
AK		 4309 /* Read the EEPROM */
4310 err = iwl_eeprom_init(priv);
4311 if (err) {
15b1687c 4312 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4313 goto out_iounmap;
4314 }
8614f360
TW		 4315 err = iwl_eeprom_check_version(priv);
4316 if (err)
c8f16138 4317 goto out_free_eeprom;
8614f360 4318
02883017 4319 /* extract MAC Address */
c6fa17ed
WYG		 4320 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4321 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4322 priv->hw->wiphy->addresses = priv->addresses;
4323 priv->hw->wiphy->n_addresses = 1;
4324 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4325 if (num_mac > 1) {
4326 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4327 ETH_ALEN);
4328 priv->addresses[1].addr[5]++;
4329 priv->hw->wiphy->n_addresses++;
4330 }
316c30d9
AK		 4331
4332 /************************
4333 * 5. Setup HW constants
4334 ************************/
da154e30 4335 if (iwl_set_hw_params(priv)) {
15b1687c 4336 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4337 goto out_free_eeprom;
316c30d9
AK		 4338 }
4339
4340 /*******************
6ba87956 4341 * 6. Setup priv
316c30d9 4342 *******************/
b481de9c 4343
6ba87956 4344 err = iwl_init_drv(priv);
bf85ea4f 4345 if (err)
399f4900 4346 goto out_free_eeprom;
bf85ea4f 4347 /* At this point both hw and priv are initialized. */
316c30d9 4348
316c30d9 4349 /********************
09f9bf79 4350 * 7. Setup services
316c30d9 4351 ********************/
0359facc 4352 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4353 iwl_disable_interrupts(priv);
0359facc 4354 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4355
6cd0b1cb
HS		 4356 pci_enable_msi(priv->pci_dev);
4357
ef850d7c
MA		 4358 iwl_alloc_isr_ict(priv);
4359 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4360 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4361 if (err) {
4362 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4363 goto out_disable_msi;
4364 }
316c30d9 4365
4e39317d 4366 iwl_setup_deferred_work(priv);
653fa4a0 4367 iwl_setup_rx_handlers(priv);
316c30d9 4368
158bea07
JB		 4369 /*********************************************
4370 * 8. Enable interrupts and read RFKILL state
4371 *********************************************/
6ba87956 4372
6cd0b1cb
HS		 4373 /* enable interrupts if needed: hw bug w/a */
4374 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4375 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4376 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4377 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4378 }
4379
4380 iwl_enable_interrupts(priv);
4381
6cd0b1cb
HS		 4382 /* If platform's RF_KILL switch is NOT set to KILL */
4383 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4384 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4385 else
4386 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4387
a60e77e5
JB		 4388 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4389 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4390
58d0f361 4391 iwl_power_initialize(priv);
39b73fb1 4392 iwl_tt_initialize(priv);
158bea07 4393
a15707d8 4394 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4395
b08dfd04 4396 err = iwl_request_firmware(priv, true);
158bea07 4397 if (err)
7d47618a 4398 goto out_destroy_workqueue;
158bea07 4399
b481de9c
ZY		 4400 return 0;
4401
7d47618a 4402 out_destroy_workqueue:
c8f16138
RC		 4403 destroy_workqueue(priv->workqueue);
4404 priv->workqueue = NULL;
795cc0ad 4405 free_irq(priv->pci_dev->irq, priv);
ef850d7c 4406 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 4407 out_disable_msi:
4408 pci_disable_msi(priv->pci_dev);
6ba87956 4409 iwl_uninit_drv(priv);
073d3f5f
TW		 4410 out_free_eeprom:
4411 iwl_eeprom_free(priv);
b481de9c
ZY		 4412 out_iounmap:
4413 pci_iounmap(pdev, priv->hw_base);
4414 out_pci_release_regions:
316c30d9 4415 pci_set_drvdata(pdev, NULL);
623d563e 4416 pci_release_regions(pdev);
b481de9c
ZY		 4417 out_pci_disable_device:
4418 pci_disable_device(pdev);
b481de9c 4419 out_ieee80211_free_hw:
20594eb0 4420 iwl_free_traffic_mem(priv);
d7c76f4c 4421 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4422 out:
4423 return err;
4424}
4425
5b9f8cd3 4426static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4427{
c79dd5b5 4428 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4429 unsigned long flags;
b481de9c
ZY		 4430
4431 if (!priv)
4432 return;
4433
a15707d8 4434 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4435
e1623446 4436 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4437
67249625 4438 iwl_dbgfs_unregister(priv);
5b9f8cd3 4439 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4440
5b9f8cd3
EG		 4441 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4442 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4443 * we need to set STATUS_EXIT_PENDING bit.
4444 */
4445 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4446 if (priv->mac80211_registered) {
4447 ieee80211_unregister_hw(priv->hw);
4448 priv->mac80211_registered = 0;
0b124c31 4449 } else {
5b9f8cd3 4450 iwl_down(priv);
c4f55232
RR		 4451 }
4452
c166b25a
BC		 4453 /*
4454 * Make sure device is reset to low power before unloading driver.
4455 * This may be redundant with iwl_down(), but there are paths to
4456 * run iwl_down() without calling apm_ops.stop(), and there are
4457 * paths to avoid running iwl_down() at all before leaving driver.
4458 * This (inexpensive) call *makes sure* device is reset.
4459 */
4460 priv->cfg->ops->lib->apm_ops.stop(priv);
4461
39b73fb1
WYG		 4462 iwl_tt_exit(priv);
4463
0359facc
MA		 4464 /* make sure we flush any pending irq or
4465 * tasklet for the driver
4466 */
4467 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4468 iwl_disable_interrupts(priv);
0359facc
MA		 4469 spin_unlock_irqrestore(&priv->lock, flags);
4470
4471 iwl_synchronize_irq(priv);
4472
5b9f8cd3 4473 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4474
4475 if (priv->rxq.bd)
54b81550 4476 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4477 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4478
073d3f5f 4479 iwl_eeprom_free(priv);
b481de9c 4480
b481de9c 4481
948c171c
MA		 4482 /*netif_stop_queue(dev); */
4483 flush_workqueue(priv->workqueue);
4484
5b9f8cd3 4485 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4486 * priv->workqueue... so we can't take down the workqueue
4487 * until now... */
4488 destroy_workqueue(priv->workqueue);
4489 priv->workqueue = NULL;
20594eb0 4490 iwl_free_traffic_mem(priv);
b481de9c 4491
6cd0b1cb
HS		 4492 free_irq(priv->pci_dev->irq, priv);
4493 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4494 pci_iounmap(pdev, priv->hw_base);
4495 pci_release_regions(pdev);
4496 pci_disable_device(pdev);
4497 pci_set_drvdata(pdev, NULL);
4498
6ba87956 4499 iwl_uninit_drv(priv);
b481de9c 4500
ef850d7c
MA		 4501 iwl_free_isr_ict(priv);
4502
b481de9c
ZY		 4503 if (priv->ibss_beacon)
4504 dev_kfree_skb(priv->ibss_beacon);
4505
4506 ieee80211_free_hw(priv->hw);
4507}
4508
b481de9c
ZY		 4509
4510/*****************************************************************************
4511 *
4512 * driver and module entry point
4513 *
4514 *****************************************************************************/
4515
fed9017e 4516/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4517static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4518#ifdef CONFIG_IWL4965
fed9017e
RR		 4519 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4520 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4521#endif /* CONFIG_IWL4965 */
5a6a256e 4522#ifdef CONFIG_IWL5000
ac592574
WYG		 4523/* 5100 Series WiFi */
4524 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4525 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4526 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4527 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4528 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4529 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4530 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4531 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4532 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4533 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4534 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4535 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4536 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4537 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4538 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4539 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4540 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4541 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4542 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4543 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4544 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4545 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4546 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4547 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4548
4549/* 5300 Series WiFi */
4550 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4551 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4552 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4553 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4554 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4555 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4556 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4557 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4558 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4559 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4560 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4561 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4562
4563/* 5350 Series WiFi/WiMax */
4564 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4565 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4566 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4567
4568/* 5150 Series Wifi/WiMax */
4569 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4570 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4571 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4572 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4573 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4574 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4575
4576 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4577 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4578 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4579 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4580
4581/* 6x00 Series */
5953a62e
WYG		 4582 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4583 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4584 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4585 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4586 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4587 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4588 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4589 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4590 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4591 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4592
95b13014
SZ		 4593/* 6x00 Series Gen2a */
4594 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4595 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4596 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
1808972f
SZ		 4597 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4598 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4599 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4600 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
9f6e1baf
SZ		 4601 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4602 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4603 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4604 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4605 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4606 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4607 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4608
4609/* 6x00 Series Gen2b */
4610 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4611 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4612 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4613 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4614 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4615 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4616 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4617 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4618 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4619 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4620 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
9f6e1baf
SZ		 4621 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4622 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4623 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4624 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4625 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4626 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4627 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4628 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4629 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4630 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4631 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4632 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4633 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4634 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4635 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4636 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4637 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4638
4639/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4640 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4641 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4642 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4643 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4644 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4645 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4646
03264339
SZ		 4647/* 6x50 WiFi/WiMax Series Gen2 */
4648 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4649 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4650 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4651 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4652 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4653 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4654
77dcb6a9 4655/* 1000 Series WiFi */
4bd0914f
WYG		 4656 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4657 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4658 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4659 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4660 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4661 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4662 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4663 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4664 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4665 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4666 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4667 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 4668#endif /* CONFIG_IWL5000 */
7100e924 4669
fed9017e
RR		 4670 {0}
4671};
4672MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4673
4674static struct pci_driver iwl_driver = {
b481de9c 4675 .name = DRV_NAME,
fed9017e 4676 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4677 .probe = iwl_pci_probe,
4678 .remove = __devexit_p(iwl_pci_remove),
b481de9c 4679#ifdef CONFIG_PM
5b9f8cd3
EG		 4680 .suspend = iwl_pci_suspend,
4681 .resume = iwl_pci_resume,
b481de9c
ZY		 4682#endif
4683};
4684
5b9f8cd3 4685static int __init iwl_init(void)
b481de9c
ZY		 4686{
4687
4688 int ret;
c96c31e4
JP		 4689 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4690 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4691
e227ceac 4692 ret = iwlagn_rate_control_register();
897e1cf2 4693 if (ret) {
c96c31e4 4694 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4695 return ret;
4696 }
4697
fed9017e 4698 ret = pci_register_driver(&iwl_driver);
b481de9c 4699 if (ret) {
c96c31e4 4700 pr_err("Unable to initialize PCI module\n");
897e1cf2 4701 goto error_register;
b481de9c 4702 }
b481de9c
ZY		 4703
4704 return ret;
897e1cf2 4705
897e1cf2 4706error_register:
e227ceac 4707 iwlagn_rate_control_unregister();
897e1cf2 4708 return ret;
b481de9c
ZY		 4709}
4710
5b9f8cd3 4711static void __exit iwl_exit(void)
b481de9c 4712{
fed9017e 4713 pci_unregister_driver(&iwl_driver);
e227ceac 4714 iwlagn_rate_control_unregister();
b481de9c
ZY		 4715}
4716
5b9f8cd3
EG		 4717module_exit(iwl_exit);
4718module_init(iwl_init);
a562a9dd
RC		 4719
4720#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4721module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4722MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4723module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4724MODULE_PARM_DESC(debug, "debug output mask");
4725#endif
4726
2b068618
WYG		 4727module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4728MODULE_PARM_DESC(swcrypto50,
4729 "using crypto in software (default 0 [hardware]) (deprecated)");
4730module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4731MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4732module_param_named(queues_num50,
4733 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4734MODULE_PARM_DESC(queues_num50,
4735 "number of hw queues in 50xx series (deprecated)");
4736module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4737MODULE_PARM_DESC(queues_num, "number of hw queues.");
4738module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4739MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4740module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4741MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4742module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4743 int, S_IRUGO);
4744MODULE_PARM_DESC(amsdu_size_8K50,
4745 "enable 8K amsdu size in 50XX series (deprecated)");
4746module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4747 int, S_IRUGO);
4748MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4749module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4750MODULE_PARM_DESC(fw_restart50,
4751 "restart firmware in case of error (deprecated)");
4752module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4753MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4754module_param_named(
4755 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4756MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
dd7a2509
JB		 4757
4758module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4759 S_IRUGO);
4760MODULE_PARM_DESC(ucode_alternative,
4761 "specify ucode alternative to use from ucode file");
bee008b7
WYG		 4762
4763module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4764MODULE_PARM_DESC(antenna_coupling,
4765 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9
WYG		 4766
4767module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4768MODULE_PARM_DESC(bt_ch_announce,
4769 "Enable BT channel announcement mode (default: enable)");
Linux kernel - Deliverables
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