Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/skbuff.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/firmware.h> | |
b481de9c ZY |
40 | #include <linux/etherdevice.h> |
41 | #include <linux/if_arp.h> | |
42 | ||
b481de9c ZY |
43 | #include <net/mac80211.h> |
44 | ||
45 | #include <asm/div64.h> | |
46 | ||
a3139c59 SO |
47 | #define DRV_NAME "iwlagn" |
48 | ||
6bc913bd | 49 | #include "iwl-eeprom.h" |
3e0d4cb1 | 50 | #include "iwl-dev.h" |
fee1247a | 51 | #include "iwl-core.h" |
3395f6e9 | 52 | #include "iwl-io.h" |
b481de9c | 53 | #include "iwl-helpers.h" |
6974e363 | 54 | #include "iwl-sta.h" |
f0832f13 | 55 | #include "iwl-calib.h" |
b481de9c | 56 | |
416e1438 | 57 | |
b481de9c ZY |
58 | /****************************************************************************** |
59 | * | |
60 | * module boiler plate | |
61 | * | |
62 | ******************************************************************************/ | |
63 | ||
b481de9c ZY |
64 | /* |
65 | * module name, copyright, version, etc. | |
b481de9c | 66 | */ |
d783b061 | 67 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 68 | |
0a6857e7 | 69 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
70 | #define VD "d" |
71 | #else | |
72 | #define VD | |
73 | #endif | |
74 | ||
80bc5393 | 75 | #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT |
b481de9c ZY |
76 | #define VS "s" |
77 | #else | |
78 | #define VS | |
79 | #endif | |
80 | ||
df48c323 | 81 | #define DRV_VERSION IWLWIFI_VERSION VD VS |
b481de9c | 82 | |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 87 | MODULE_LICENSE("GPL"); |
4fc22b21 | 88 | MODULE_ALIAS("iwl4965"); |
b481de9c | 89 | |
b481de9c | 90 | /*************** STATION TABLE MANAGEMENT **** |
9fbab516 | 91 | * mac80211 should be examined to determine if sta_info is duplicating |
b481de9c ZY |
92 | * the functionality provided here |
93 | */ | |
94 | ||
95 | /**************************************************************/ | |
96 | ||
b481de9c | 97 | /** |
5b9f8cd3 | 98 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 99 | * |
01ebd063 | 100 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
101 | * the active_rxon structure is updated with the new data. This |
102 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
103 | * a HW tune is required based on the RXON structure changes. | |
104 | */ | |
e0158e61 | 105 | int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
106 | { |
107 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 108 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
109 | int ret; |
110 | bool new_assoc = | |
111 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 112 | |
fee1247a | 113 | if (!iwl_is_alive(priv)) |
43d59b32 | 114 | return -EBUSY; |
b481de9c ZY |
115 | |
116 | /* always get timestamp with Rx frame */ | |
117 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
a326a5d0 EG |
118 | /* allow CTS-to-self if possible. this is relevant only for |
119 | * 5000, but will not damage 4965 */ | |
120 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
b481de9c | 121 | |
8ccde88a | 122 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 123 | if (ret) { |
15b1687c | 124 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
125 | return -EINVAL; |
126 | } | |
127 | ||
128 | /* If we don't need to send a full RXON, we can use | |
5b9f8cd3 | 129 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 130 | * and other flags for the current radio configuration. */ |
54559703 | 131 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
132 | ret = iwl_send_rxon_assoc(priv); |
133 | if (ret) { | |
15b1687c | 134 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 135 | return ret; |
b481de9c ZY |
136 | } |
137 | ||
138 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
139 | return 0; |
140 | } | |
141 | ||
142 | /* station table will be cleared */ | |
143 | priv->assoc_station_added = 0; | |
144 | ||
b481de9c ZY |
145 | /* If we are currently associated and the new config requires |
146 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
147 | * we must clear the associated from the active configuration | |
148 | * before we apply the new config */ | |
43d59b32 | 149 | if (iwl_is_associated(priv) && new_assoc) { |
e1623446 | 150 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
151 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
152 | ||
43d59b32 | 153 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 154 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
155 | &priv->active_rxon); |
156 | ||
157 | /* If the mask clearing failed then we set | |
158 | * active_rxon back to what it was previously */ | |
43d59b32 | 159 | if (ret) { |
b481de9c | 160 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 161 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 162 | return ret; |
b481de9c | 163 | } |
b481de9c ZY |
164 | } |
165 | ||
e1623446 | 166 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
167 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
168 | "* channel = %d\n" | |
e174961c | 169 | "* bssid = %pM\n", |
43d59b32 | 170 | (new_assoc ? "" : "out"), |
b481de9c | 171 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 172 | priv->staging_rxon.bssid_addr); |
b481de9c | 173 | |
5b9f8cd3 | 174 | iwl_set_rxon_hwcrypto(priv, !priv->hw_params.sw_crypto); |
43d59b32 EG |
175 | |
176 | /* Apply the new configuration | |
177 | * RXON unassoc clears the station table in uCode, send it before | |
178 | * we add the bcast station. If assoc bit is set, we will send RXON | |
179 | * after having added the bcast and bssid station. | |
180 | */ | |
181 | if (!new_assoc) { | |
182 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 183 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 184 | if (ret) { |
15b1687c | 185 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
186 | return ret; |
187 | } | |
188 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
189 | } |
190 | ||
c587de0b | 191 | iwl_clear_stations_table(priv); |
556f8db7 | 192 | |
19cc1087 | 193 | priv->start_calib = 0; |
b481de9c | 194 | |
b481de9c | 195 | /* Add the broadcast address so we can send broadcast frames */ |
4f40e4d9 | 196 | if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) == |
43d59b32 | 197 | IWL_INVALID_STATION) { |
15b1687c | 198 | IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n"); |
b481de9c ZY |
199 | return -EIO; |
200 | } | |
201 | ||
202 | /* If we have set the ASSOC_MSK and we are in BSS mode then | |
203 | * add the IWL_AP_ID to the station rate table */ | |
9185159d | 204 | if (new_assoc) { |
05c914fe | 205 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
9185159d TW |
206 | ret = iwl_rxon_add_station(priv, |
207 | priv->active_rxon.bssid_addr, 1); | |
208 | if (ret == IWL_INVALID_STATION) { | |
15b1687c WT |
209 | IWL_ERR(priv, |
210 | "Error adding AP address for TX.\n"); | |
9185159d TW |
211 | return -EIO; |
212 | } | |
213 | priv->assoc_station_added = 1; | |
214 | if (priv->default_wep_key && | |
215 | iwl_send_static_wepkey_cmd(priv, 0)) | |
15b1687c WT |
216 | IWL_ERR(priv, |
217 | "Could not send WEP static key.\n"); | |
b481de9c | 218 | } |
43d59b32 EG |
219 | |
220 | /* Apply the new configuration | |
221 | * RXON assoc doesn't clear the station table in uCode, | |
222 | */ | |
223 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
224 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
225 | if (ret) { | |
15b1687c | 226 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
227 | return ret; |
228 | } | |
229 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c ZY |
230 | } |
231 | ||
36da7d70 ZY |
232 | iwl_init_sensitivity(priv); |
233 | ||
234 | /* If we issue a new RXON command which required a tune then we must | |
235 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
236 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
237 | if (ret) { | |
15b1687c | 238 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
239 | return ret; |
240 | } | |
241 | ||
b481de9c ZY |
242 | return 0; |
243 | } | |
244 | ||
5b9f8cd3 | 245 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
246 | { |
247 | ||
45823531 AK |
248 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
249 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
e0158e61 | 250 | iwlcore_commit_rxon(priv); |
5da4b55f MA |
251 | } |
252 | ||
fcab423d | 253 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
254 | { |
255 | struct list_head *element; | |
256 | ||
e1623446 | 257 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
258 | priv->frames_count); |
259 | ||
260 | while (!list_empty(&priv->free_frames)) { | |
261 | element = priv->free_frames.next; | |
262 | list_del(element); | |
fcab423d | 263 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
264 | priv->frames_count--; |
265 | } | |
266 | ||
267 | if (priv->frames_count) { | |
39aadf8c | 268 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
269 | priv->frames_count); |
270 | priv->frames_count = 0; | |
271 | } | |
272 | } | |
273 | ||
fcab423d | 274 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 275 | { |
fcab423d | 276 | struct iwl_frame *frame; |
b481de9c ZY |
277 | struct list_head *element; |
278 | if (list_empty(&priv->free_frames)) { | |
279 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
280 | if (!frame) { | |
15b1687c | 281 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
282 | return NULL; |
283 | } | |
284 | ||
285 | priv->frames_count++; | |
286 | return frame; | |
287 | } | |
288 | ||
289 | element = priv->free_frames.next; | |
290 | list_del(element); | |
fcab423d | 291 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
292 | } |
293 | ||
fcab423d | 294 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
295 | { |
296 | memset(frame, 0, sizeof(*frame)); | |
297 | list_add(&frame->list, &priv->free_frames); | |
298 | } | |
299 | ||
4bf64efd TW |
300 | static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv, |
301 | struct ieee80211_hdr *hdr, | |
73ec1cc2 | 302 | int left) |
b481de9c | 303 | { |
3109ece1 | 304 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
305 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
306 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
307 | return 0; |
308 | ||
309 | if (priv->ibss_beacon->len > left) | |
310 | return 0; | |
311 | ||
312 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
313 | ||
314 | return priv->ibss_beacon->len; | |
315 | } | |
316 | ||
5b9f8cd3 | 317 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
4bf64efd TW |
318 | struct iwl_frame *frame, u8 rate) |
319 | { | |
320 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
321 | unsigned int frame_size; | |
322 | ||
323 | tx_beacon_cmd = &frame->u.beacon; | |
324 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
325 | ||
326 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; | |
327 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
328 | ||
329 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, | |
4bf64efd TW |
330 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
331 | ||
332 | BUG_ON(frame_size > MAX_MPDU_SIZE); | |
333 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | |
334 | ||
335 | if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) | |
336 | tx_beacon_cmd->tx.rate_n_flags = | |
337 | iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); | |
338 | else | |
339 | tx_beacon_cmd->tx.rate_n_flags = | |
340 | iwl_hw_set_rate_n_flags(rate, 0); | |
341 | ||
342 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
343 | TX_CMD_FLG_TSF_MSK | | |
344 | TX_CMD_FLG_STA_RATE_MSK; | |
345 | ||
346 | return sizeof(*tx_beacon_cmd) + frame_size; | |
347 | } | |
5b9f8cd3 | 348 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 349 | { |
fcab423d | 350 | struct iwl_frame *frame; |
b481de9c ZY |
351 | unsigned int frame_size; |
352 | int rc; | |
353 | u8 rate; | |
354 | ||
fcab423d | 355 | frame = iwl_get_free_frame(priv); |
b481de9c ZY |
356 | |
357 | if (!frame) { | |
15b1687c | 358 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
359 | "command.\n"); |
360 | return -ENOMEM; | |
361 | } | |
362 | ||
5b9f8cd3 | 363 | rate = iwl_rate_get_lowest_plcp(priv); |
b481de9c | 364 | |
5b9f8cd3 | 365 | frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate); |
b481de9c | 366 | |
857485c0 | 367 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
368 | &frame->u.cmd[0]); |
369 | ||
fcab423d | 370 | iwl_free_frame(priv, frame); |
b481de9c ZY |
371 | |
372 | return rc; | |
373 | } | |
374 | ||
7aaa1d79 SO |
375 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
376 | { | |
377 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
378 | ||
379 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
380 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
381 | addr |= | |
382 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
383 | ||
384 | return addr; | |
385 | } | |
386 | ||
387 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
388 | { | |
389 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
390 | ||
391 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
392 | } | |
393 | ||
394 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
395 | dma_addr_t addr, u16 len) | |
396 | { | |
397 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
398 | u16 hi_n_len = len << 4; | |
399 | ||
400 | put_unaligned_le32(addr, &tb->lo); | |
401 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
402 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
403 | ||
404 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
405 | ||
406 | tfd->num_tbs = idx + 1; | |
407 | } | |
408 | ||
409 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
410 | { | |
411 | return tfd->num_tbs & 0x1f; | |
412 | } | |
413 | ||
414 | /** | |
415 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
416 | * @priv - driver private data | |
417 | * @txq - tx queue | |
418 | * | |
419 | * Does NOT advance any TFD circular buffer read/write indexes | |
420 | * Does NOT free the TFD itself (which is within circular buffer) | |
421 | */ | |
422 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
423 | { | |
59606ffa | 424 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
425 | struct iwl_tfd *tfd; |
426 | struct pci_dev *dev = priv->pci_dev; | |
427 | int index = txq->q.read_ptr; | |
428 | int i; | |
429 | int num_tbs; | |
430 | ||
431 | tfd = &tfd_tmp[index]; | |
432 | ||
433 | /* Sanity check on number of chunks */ | |
434 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
435 | ||
436 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
437 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
438 | /* @todo issue fatal error, it is quite serious situation */ | |
439 | return; | |
440 | } | |
441 | ||
442 | /* Unmap tx_cmd */ | |
443 | if (num_tbs) | |
444 | pci_unmap_single(dev, | |
445 | pci_unmap_addr(&txq->cmd[index]->meta, mapping), | |
446 | pci_unmap_len(&txq->cmd[index]->meta, len), | |
96891cee | 447 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
448 | |
449 | /* Unmap chunks, if any. */ | |
450 | for (i = 1; i < num_tbs; i++) { | |
451 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
452 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
453 | ||
454 | if (txq->txb) { | |
455 | dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]); | |
456 | txq->txb[txq->q.read_ptr].skb[i - 1] = NULL; | |
457 | } | |
458 | } | |
459 | } | |
460 | ||
461 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
462 | struct iwl_tx_queue *txq, | |
463 | dma_addr_t addr, u16 len, | |
464 | u8 reset, u8 pad) | |
465 | { | |
466 | struct iwl_queue *q; | |
59606ffa | 467 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
468 | u32 num_tbs; |
469 | ||
470 | q = &txq->q; | |
59606ffa SO |
471 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
472 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
473 | |
474 | if (reset) | |
475 | memset(tfd, 0, sizeof(*tfd)); | |
476 | ||
477 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
478 | ||
479 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
480 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
481 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
482 | IWL_NUM_OF_TBS); | |
483 | return -EINVAL; | |
484 | } | |
485 | ||
486 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
487 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
488 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
489 | (unsigned long long)addr); | |
490 | ||
491 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
a8e74e27 SO |
496 | /* |
497 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
498 | * given Tx queue, and enable the DMA channel used for that queue. | |
499 | * | |
500 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
501 | * channels supported in hardware. | |
502 | */ | |
503 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
504 | struct iwl_tx_queue *txq) | |
505 | { | |
a8e74e27 SO |
506 | int txq_id = txq->q.id; |
507 | ||
a8e74e27 SO |
508 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
509 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
510 | txq->q.dma_addr >> 8); | |
511 | ||
a8e74e27 SO |
512 | return 0; |
513 | } | |
514 | ||
515 | ||
b481de9c ZY |
516 | /****************************************************************************** |
517 | * | |
518 | * Misc. internal state and helper functions | |
519 | * | |
520 | ******************************************************************************/ | |
b481de9c | 521 | |
b481de9c | 522 | #define MAX_UCODE_BEACON_INTERVAL 4096 |
b481de9c | 523 | |
3195c1f3 | 524 | static u16 iwl_adjust_beacon_interval(u16 beacon_val) |
b481de9c ZY |
525 | { |
526 | u16 new_val = 0; | |
527 | u16 beacon_factor = 0; | |
528 | ||
3195c1f3 TW |
529 | beacon_factor = (beacon_val + MAX_UCODE_BEACON_INTERVAL) |
530 | / MAX_UCODE_BEACON_INTERVAL; | |
b481de9c ZY |
531 | new_val = beacon_val / beacon_factor; |
532 | ||
41d2f291 JL |
533 | if (!new_val) |
534 | new_val = MAX_UCODE_BEACON_INTERVAL; | |
535 | ||
3195c1f3 | 536 | return new_val; |
b481de9c ZY |
537 | } |
538 | ||
3195c1f3 | 539 | static void iwl_setup_rxon_timing(struct iwl_priv *priv) |
b481de9c | 540 | { |
3195c1f3 TW |
541 | u64 tsf; |
542 | s32 interval_tm, rem; | |
b481de9c ZY |
543 | unsigned long flags; |
544 | struct ieee80211_conf *conf = NULL; | |
545 | u16 beacon_int = 0; | |
546 | ||
547 | conf = ieee80211_get_hw_conf(priv->hw); | |
548 | ||
549 | spin_lock_irqsave(&priv->lock, flags); | |
3195c1f3 | 550 | priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp); |
b5d7be5e | 551 | priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval); |
b481de9c | 552 | |
05c914fe | 553 | if (priv->iw_mode == NL80211_IFTYPE_STATION) { |
3195c1f3 | 554 | beacon_int = iwl_adjust_beacon_interval(priv->beacon_int); |
b481de9c ZY |
555 | priv->rxon_timing.atim_window = 0; |
556 | } else { | |
57c4d7b4 JB |
557 | beacon_int = iwl_adjust_beacon_interval( |
558 | priv->vif->bss_conf.beacon_int); | |
3195c1f3 | 559 | |
b481de9c ZY |
560 | /* TODO: we need to get atim_window from upper stack |
561 | * for now we set to 0 */ | |
562 | priv->rxon_timing.atim_window = 0; | |
563 | } | |
564 | ||
3195c1f3 | 565 | priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int); |
b481de9c | 566 | |
3195c1f3 TW |
567 | tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */ |
568 | interval_tm = beacon_int * 1024; | |
569 | rem = do_div(tsf, interval_tm); | |
570 | priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem); | |
571 | ||
572 | spin_unlock_irqrestore(&priv->lock, flags); | |
e1623446 | 573 | IWL_DEBUG_ASSOC(priv, "beacon interval %d beacon timer %d beacon tim %d\n", |
3195c1f3 TW |
574 | le16_to_cpu(priv->rxon_timing.beacon_interval), |
575 | le32_to_cpu(priv->rxon_timing.beacon_init_val), | |
576 | le16_to_cpu(priv->rxon_timing.atim_window)); | |
b481de9c ZY |
577 | } |
578 | ||
b481de9c ZY |
579 | /****************************************************************************** |
580 | * | |
581 | * Generic RX handler implementations | |
582 | * | |
583 | ******************************************************************************/ | |
885ba202 TW |
584 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
585 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 586 | { |
db11d634 | 587 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
885ba202 | 588 | struct iwl_alive_resp *palive; |
b481de9c ZY |
589 | struct delayed_work *pwork; |
590 | ||
591 | palive = &pkt->u.alive_frame; | |
592 | ||
e1623446 | 593 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
594 | "0x%01X 0x%01X\n", |
595 | palive->is_valid, palive->ver_type, | |
596 | palive->ver_subtype); | |
597 | ||
598 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 599 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
600 | memcpy(&priv->card_alive_init, |
601 | &pkt->u.alive_frame, | |
885ba202 | 602 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
603 | pwork = &priv->init_alive_start; |
604 | } else { | |
e1623446 | 605 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 606 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 607 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
608 | pwork = &priv->alive_start; |
609 | } | |
610 | ||
611 | /* We delay the ALIVE response by 5ms to | |
612 | * give the HW RF Kill time to activate... */ | |
613 | if (palive->is_valid == UCODE_VALID_OK) | |
614 | queue_delayed_work(priv->workqueue, pwork, | |
615 | msecs_to_jiffies(5)); | |
616 | else | |
39aadf8c | 617 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
618 | } |
619 | ||
5b9f8cd3 | 620 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 621 | { |
c79dd5b5 TW |
622 | struct iwl_priv *priv = |
623 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
624 | struct sk_buff *beacon; |
625 | ||
626 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 627 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
628 | |
629 | if (!beacon) { | |
15b1687c | 630 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
631 | return; |
632 | } | |
633 | ||
634 | mutex_lock(&priv->mutex); | |
635 | /* new beacon skb is allocated every time; dispose previous.*/ | |
636 | if (priv->ibss_beacon) | |
637 | dev_kfree_skb(priv->ibss_beacon); | |
638 | ||
639 | priv->ibss_beacon = beacon; | |
640 | mutex_unlock(&priv->mutex); | |
641 | ||
5b9f8cd3 | 642 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
643 | } |
644 | ||
4e39317d | 645 | /** |
5b9f8cd3 | 646 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
647 | * |
648 | * This callback is provided in order to send a statistics request. | |
649 | * | |
650 | * This timer function is continually reset to execute within | |
651 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
652 | * was received. We need to ensure we receive the statistics in order | |
653 | * to update the temperature used for calibrating the TXPOWER. | |
654 | */ | |
5b9f8cd3 | 655 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
656 | { |
657 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
658 | ||
659 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
660 | return; | |
661 | ||
61780ee3 MA |
662 | /* dont send host command if rf-kill is on */ |
663 | if (!iwl_is_ready_rf(priv)) | |
664 | return; | |
665 | ||
4e39317d EG |
666 | iwl_send_statistics_request(priv, CMD_ASYNC); |
667 | } | |
668 | ||
5b9f8cd3 | 669 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 670 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 671 | { |
0a6857e7 | 672 | #ifdef CONFIG_IWLWIFI_DEBUG |
db11d634 | 673 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
2aa6ab86 TW |
674 | struct iwl4965_beacon_notif *beacon = |
675 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 676 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 677 | |
e1623446 | 678 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 679 | "tsf %d %d rate %d\n", |
25a6572c | 680 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
681 | beacon->beacon_notify_hdr.failure_frame, |
682 | le32_to_cpu(beacon->ibss_mgr_status), | |
683 | le32_to_cpu(beacon->high_tsf), | |
684 | le32_to_cpu(beacon->low_tsf), rate); | |
685 | #endif | |
686 | ||
05c914fe | 687 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
688 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
689 | queue_work(priv->workqueue, &priv->beacon_update); | |
690 | } | |
691 | ||
b481de9c ZY |
692 | /* Handle notification from uCode that card's power state is changing |
693 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 694 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 695 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 696 | { |
db11d634 | 697 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
698 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
699 | unsigned long status = priv->status; | |
a8b50a0a | 700 | unsigned long reg_flags; |
b481de9c | 701 | |
e1623446 | 702 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n", |
b481de9c ZY |
703 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
704 | (flags & SW_CARD_DISABLED) ? "Kill" : "On"); | |
705 | ||
706 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
707 | RF_CARD_DISABLED)) { | |
708 | ||
3395f6e9 | 709 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
710 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
711 | ||
a8b50a0a MA |
712 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
713 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
714 | |
715 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 716 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 717 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 718 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c ZY |
719 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
720 | ||
b481de9c ZY |
721 | } |
722 | ||
723 | if (flags & RF_CARD_DISABLED) { | |
3395f6e9 | 724 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c | 725 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
3395f6e9 | 726 | iwl_read32(priv, CSR_UCODE_DRV_GP1); |
a8b50a0a | 727 | spin_lock_irqsave(&priv->reg_lock, reg_flags); |
3395f6e9 TW |
728 | if (!iwl_grab_nic_access(priv)) |
729 | iwl_release_nic_access(priv); | |
a8b50a0a | 730 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); |
b481de9c ZY |
731 | } |
732 | } | |
733 | ||
734 | if (flags & HW_CARD_DISABLED) | |
735 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
736 | else | |
737 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
738 | ||
739 | ||
b481de9c | 740 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 741 | iwl_scan_cancel(priv); |
b481de9c ZY |
742 | |
743 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
744 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
745 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
746 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
747 | else |
748 | wake_up_interruptible(&priv->wait_command_queue); | |
749 | } | |
750 | ||
5b9f8cd3 | 751 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b | 752 | { |
e2e3c57b | 753 | if (src == IWL_PWR_SRC_VAUX) { |
3fdb68de | 754 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
755 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
756 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
757 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
758 | } else { | |
759 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
760 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
761 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
762 | } | |
763 | ||
a8b50a0a | 764 | return 0; |
e2e3c57b TW |
765 | } |
766 | ||
b481de9c | 767 | /** |
5b9f8cd3 | 768 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
769 | * |
770 | * Setup the RX handlers for each of the reply types sent from the uCode | |
771 | * to the host. | |
772 | * | |
773 | * This function chains into the hardware specific files for them to setup | |
774 | * any hardware specific handlers as well. | |
775 | */ | |
653fa4a0 | 776 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 777 | { |
885ba202 | 778 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
779 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
780 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
5b9f8cd3 | 781 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 782 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
783 | iwl_rx_pm_debug_statistics_notif; |
784 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 785 | |
9fbab516 BC |
786 | /* |
787 | * The same handler is used for both the REPLY to a discrete | |
788 | * statistics request from the host as well as for the periodic | |
789 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 790 | */ |
8f91aecb EG |
791 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics; |
792 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; | |
2a421b91 | 793 | |
21c339bf | 794 | iwl_setup_spectrum_handlers(priv); |
2a421b91 TW |
795 | iwl_setup_rx_scan_handlers(priv); |
796 | ||
37a44211 | 797 | /* status change handler */ |
5b9f8cd3 | 798 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 799 | |
c1354754 TW |
800 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
801 | iwl_rx_missed_beacon_notif; | |
37a44211 | 802 | /* Rx handlers */ |
1781a07f EG |
803 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy; |
804 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx; | |
653fa4a0 EG |
805 | /* block ack */ |
806 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba; | |
9fbab516 | 807 | /* Set up hardware specific Rx handlers */ |
d4789efe | 808 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
809 | } |
810 | ||
b481de9c | 811 | /** |
a55360e4 | 812 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
813 | * |
814 | * Uses the priv->rx_handlers callback function array to invoke | |
815 | * the appropriate handlers, including command responses, | |
816 | * frame-received notifications, and other notifications. | |
817 | */ | |
a55360e4 | 818 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 819 | { |
a55360e4 | 820 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 821 | struct iwl_rx_packet *pkt; |
a55360e4 | 822 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
823 | u32 r, i; |
824 | int reclaim; | |
825 | unsigned long flags; | |
5c0eef96 | 826 | u8 fill_rx = 0; |
d68ab680 | 827 | u32 count = 8; |
4752c93c | 828 | int total_empty; |
b481de9c | 829 | |
6440adb5 CB |
830 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
831 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 832 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
833 | i = rxq->read; |
834 | ||
835 | /* Rx interrupt, but nothing sent from uCode */ | |
836 | if (i == r) | |
e1623446 | 837 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 838 | |
4752c93c MA |
839 | /* calculate total frames need to be restock after handling RX */ |
840 | total_empty = r - priv->rxq.write_actual; | |
841 | if (total_empty < 0) | |
842 | total_empty += RX_QUEUE_SIZE; | |
843 | ||
844 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
845 | fill_rx = 1; |
846 | ||
b481de9c ZY |
847 | while (i != r) { |
848 | rxb = rxq->queue[i]; | |
849 | ||
9fbab516 | 850 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
851 | * then a bug has been introduced in the queue refilling |
852 | * routines -- catch it here */ | |
853 | BUG_ON(rxb == NULL); | |
854 | ||
855 | rxq->queue[i] = NULL; | |
856 | ||
df833b1d RC |
857 | pci_unmap_single(priv->pci_dev, rxb->real_dma_addr, |
858 | priv->hw_params.rx_buf_size + 256, | |
859 | PCI_DMA_FROMDEVICE); | |
db11d634 | 860 | pkt = (struct iwl_rx_packet *)rxb->skb->data; |
b481de9c ZY |
861 | |
862 | /* Reclaim a command buffer only if this packet is a response | |
863 | * to a (driver-originated) command. | |
864 | * If the packet (e.g. Rx frame) originated from uCode, | |
865 | * there is no command buffer to reclaim. | |
866 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
867 | * but apparently a few don't get set; catch them here. */ | |
868 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
869 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 870 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 871 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 872 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
873 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
874 | (pkt->hdr.cmd != REPLY_TX); | |
875 | ||
876 | /* Based on type of command response or notification, | |
877 | * handle those that need handling via function in | |
5b9f8cd3 | 878 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 879 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 880 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 881 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
b481de9c | 882 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
a83b9141 | 883 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
b481de9c ZY |
884 | } else { |
885 | /* No handling needed */ | |
e1623446 | 886 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
887 | "r %d i %d No handler needed for %s, 0x%02x\n", |
888 | r, i, get_cmd_string(pkt->hdr.cmd), | |
889 | pkt->hdr.cmd); | |
890 | } | |
891 | ||
892 | if (reclaim) { | |
9fbab516 | 893 | /* Invoke any callbacks, transfer the skb to caller, and |
857485c0 | 894 | * fire off the (possibly) blocking iwl_send_cmd() |
b481de9c ZY |
895 | * as we reclaim the driver command queue */ |
896 | if (rxb && rxb->skb) | |
17b88929 | 897 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 898 | else |
39aadf8c | 899 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
900 | } |
901 | ||
902 | /* For now we just don't re-use anything. We can tweak this | |
903 | * later to try and re-use notification packets and SKBs that | |
904 | * fail to Rx correctly */ | |
905 | if (rxb->skb != NULL) { | |
906 | priv->alloc_rxb_skb--; | |
907 | dev_kfree_skb_any(rxb->skb); | |
908 | rxb->skb = NULL; | |
909 | } | |
910 | ||
b481de9c ZY |
911 | spin_lock_irqsave(&rxq->lock, flags); |
912 | list_add_tail(&rxb->list, &priv->rxq.rx_used); | |
913 | spin_unlock_irqrestore(&rxq->lock, flags); | |
914 | i = (i + 1) & RX_QUEUE_MASK; | |
5c0eef96 MA |
915 | /* If there are a lot of unused frames, |
916 | * restock the Rx queue so ucode wont assert. */ | |
917 | if (fill_rx) { | |
918 | count++; | |
919 | if (count >= 8) { | |
920 | priv->rxq.read = i; | |
4752c93c | 921 | iwl_rx_replenish_now(priv); |
5c0eef96 MA |
922 | count = 0; |
923 | } | |
924 | } | |
b481de9c ZY |
925 | } |
926 | ||
927 | /* Backtrack one entry */ | |
928 | priv->rxq.read = i; | |
4752c93c MA |
929 | if (fill_rx) |
930 | iwl_rx_replenish_now(priv); | |
931 | else | |
932 | iwl_rx_queue_restock(priv); | |
a55360e4 | 933 | } |
a55360e4 | 934 | |
0359facc MA |
935 | /* call this function to flush any scheduled tasklet */ |
936 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
937 | { | |
a96a27f9 | 938 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
939 | synchronize_irq(priv->pci_dev->irq); |
940 | tasklet_kill(&priv->irq_tasklet); | |
941 | } | |
942 | ||
ef850d7c | 943 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
944 | { |
945 | u32 inta, handled = 0; | |
946 | u32 inta_fh; | |
947 | unsigned long flags; | |
0a6857e7 | 948 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
949 | u32 inta_mask; |
950 | #endif | |
951 | ||
952 | spin_lock_irqsave(&priv->lock, flags); | |
953 | ||
954 | /* Ack/clear/reset pending uCode interrupts. | |
955 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
956 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
957 | inta = iwl_read32(priv, CSR_INT); |
958 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
959 | |
960 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
961 | * Any new interrupts that happen after this, either while we're | |
962 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
963 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
964 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 965 | |
0a6857e7 | 966 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 967 | if (priv->debug_level & IWL_DL_ISR) { |
9fbab516 | 968 | /* just for debug */ |
3395f6e9 | 969 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 970 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
971 | inta, inta_mask, inta_fh); |
972 | } | |
973 | #endif | |
974 | ||
975 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
976 | * atomic, make sure that inta covers all the interrupts that | |
977 | * we've discovered, even if FH interrupt came in just after | |
978 | * reading CSR_INT. */ | |
6f83eaa1 | 979 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 980 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 981 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
982 | inta |= CSR_INT_BIT_FH_TX; |
983 | ||
984 | /* Now service all interrupt bits discovered above. */ | |
985 | if (inta & CSR_INT_BIT_HW_ERR) { | |
15b1687c | 986 | IWL_ERR(priv, "Microcode HW error detected. Restarting.\n"); |
b481de9c ZY |
987 | |
988 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 989 | iwl_disable_interrupts(priv); |
b481de9c | 990 | |
a83b9141 | 991 | priv->isr_stats.hw++; |
5b9f8cd3 | 992 | iwl_irq_handle_error(priv); |
b481de9c ZY |
993 | |
994 | handled |= CSR_INT_BIT_HW_ERR; | |
995 | ||
996 | spin_unlock_irqrestore(&priv->lock, flags); | |
997 | ||
998 | return; | |
999 | } | |
1000 | ||
0a6857e7 | 1001 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 1002 | if (priv->debug_level & (IWL_DL_ISR)) { |
b481de9c | 1003 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 1004 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1005 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1006 | "the frame/frames.\n"); |
a83b9141 WYG |
1007 | priv->isr_stats.sch++; |
1008 | } | |
b481de9c ZY |
1009 | |
1010 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 1011 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1012 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
1013 | priv->isr_stats.alive++; |
1014 | } | |
b481de9c ZY |
1015 | } |
1016 | #endif | |
1017 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1018 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1019 | |
9fbab516 | 1020 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
1021 | if (inta & CSR_INT_BIT_RF_KILL) { |
1022 | int hw_rf_kill = 0; | |
3395f6e9 | 1023 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
1024 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1025 | hw_rf_kill = 1; | |
1026 | ||
e1623446 | 1027 | IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 1028 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 1029 | |
a83b9141 WYG |
1030 | priv->isr_stats.rfkill++; |
1031 | ||
a9efa652 | 1032 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
1033 | * the driver allows loading the ucode even if the radio |
1034 | * is killed. Hence update the killswitch state here. The | |
1035 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 1036 | */ |
6cd0b1cb HS |
1037 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
1038 | if (hw_rf_kill) | |
1039 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1040 | else | |
1041 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1042 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 1043 | } |
b481de9c ZY |
1044 | |
1045 | handled |= CSR_INT_BIT_RF_KILL; | |
1046 | } | |
1047 | ||
9fbab516 | 1048 | /* Chip got too hot and stopped itself */ |
b481de9c | 1049 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 1050 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 1051 | priv->isr_stats.ctkill++; |
b481de9c ZY |
1052 | handled |= CSR_INT_BIT_CT_KILL; |
1053 | } | |
1054 | ||
1055 | /* Error detected by uCode */ | |
1056 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1057 | IWL_ERR(priv, "Microcode SW error detected. " |
1058 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
1059 | priv->isr_stats.sw++; |
1060 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 1061 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1062 | handled |= CSR_INT_BIT_SW_ERR; |
1063 | } | |
1064 | ||
1065 | /* uCode wakes up after power-down sleep */ | |
1066 | if (inta & CSR_INT_BIT_WAKEUP) { | |
e1623446 | 1067 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1068 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
babcebfa TW |
1069 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); |
1070 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1071 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1072 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1073 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1074 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
b481de9c | 1075 | |
a83b9141 WYG |
1076 | priv->isr_stats.wakeup++; |
1077 | ||
b481de9c ZY |
1078 | handled |= CSR_INT_BIT_WAKEUP; |
1079 | } | |
1080 | ||
1081 | /* All uCode command responses, including Tx command responses, | |
1082 | * Rx "responses" (frame-received notification), and other | |
1083 | * notifications from uCode come through here*/ | |
1084 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1085 | iwl_rx_handle(priv); |
a83b9141 | 1086 | priv->isr_stats.rx++; |
b481de9c ZY |
1087 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1088 | } | |
1089 | ||
1090 | if (inta & CSR_INT_BIT_FH_TX) { | |
e1623446 | 1091 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); |
a83b9141 | 1092 | priv->isr_stats.tx++; |
b481de9c | 1093 | handled |= CSR_INT_BIT_FH_TX; |
dbb983b7 RR |
1094 | /* FH finished to write, send event */ |
1095 | priv->ucode_write_complete = 1; | |
1096 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1097 | } |
1098 | ||
a83b9141 | 1099 | if (inta & ~handled) { |
15b1687c | 1100 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1101 | priv->isr_stats.unhandled++; |
1102 | } | |
b481de9c | 1103 | |
40cefda9 | 1104 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1105 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1106 | inta & ~priv->inta_mask); |
39aadf8c | 1107 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1108 | } |
1109 | ||
1110 | /* Re-enable all interrupts */ | |
0359facc MA |
1111 | /* only Re-enable if diabled by irq */ |
1112 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1113 | iwl_enable_interrupts(priv); |
b481de9c | 1114 | |
0a6857e7 | 1115 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 1116 | if (priv->debug_level & (IWL_DL_ISR)) { |
3395f6e9 TW |
1117 | inta = iwl_read32(priv, CSR_INT); |
1118 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1119 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1120 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1121 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1122 | } | |
1123 | #endif | |
1124 | spin_unlock_irqrestore(&priv->lock, flags); | |
1125 | } | |
1126 | ||
ef850d7c MA |
1127 | /* tasklet for iwlagn interrupt */ |
1128 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1129 | { | |
1130 | u32 inta = 0; | |
1131 | u32 handled = 0; | |
1132 | unsigned long flags; | |
1133 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1134 | u32 inta_mask; | |
1135 | #endif | |
1136 | ||
1137 | spin_lock_irqsave(&priv->lock, flags); | |
1138 | ||
1139 | /* Ack/clear/reset pending uCode interrupts. | |
1140 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1141 | */ | |
1142 | iwl_write32(priv, CSR_INT, priv->inta); | |
1143 | ||
1144 | inta = priv->inta; | |
1145 | ||
1146 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1147 | if (priv->debug_level & IWL_DL_ISR) { | |
1148 | /* just for debug */ | |
1149 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1150 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1151 | inta, inta_mask); | |
1152 | } | |
1153 | #endif | |
1154 | /* saved interrupt in inta variable now we can reset priv->inta */ | |
1155 | priv->inta = 0; | |
1156 | ||
1157 | /* Now service all interrupt bits discovered above. */ | |
1158 | if (inta & CSR_INT_BIT_HW_ERR) { | |
1159 | IWL_ERR(priv, "Microcode HW error detected. Restarting.\n"); | |
1160 | ||
1161 | /* Tell the device to stop sending interrupts */ | |
1162 | iwl_disable_interrupts(priv); | |
1163 | ||
1164 | priv->isr_stats.hw++; | |
1165 | iwl_irq_handle_error(priv); | |
1166 | ||
1167 | handled |= CSR_INT_BIT_HW_ERR; | |
1168 | ||
1169 | spin_unlock_irqrestore(&priv->lock, flags); | |
1170 | ||
1171 | return; | |
1172 | } | |
1173 | ||
1174 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1175 | if (priv->debug_level & (IWL_DL_ISR)) { | |
1176 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ | |
1177 | if (inta & CSR_INT_BIT_SCD) { | |
1178 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1179 | "the frame/frames.\n"); | |
1180 | priv->isr_stats.sch++; | |
1181 | } | |
1182 | ||
1183 | /* Alive notification via Rx interrupt will do the real work */ | |
1184 | if (inta & CSR_INT_BIT_ALIVE) { | |
1185 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1186 | priv->isr_stats.alive++; | |
1187 | } | |
1188 | } | |
1189 | #endif | |
1190 | /* Safely ignore these bits for debug checks below */ | |
1191 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1192 | ||
1193 | /* HW RF KILL switch toggled */ | |
1194 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1195 | int hw_rf_kill = 0; | |
1196 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1197 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1198 | hw_rf_kill = 1; | |
1199 | ||
1200 | IWL_DEBUG_RF_KILL(priv, "RF_KILL bit toggled to %s.\n", | |
1201 | hw_rf_kill ? "disable radio" : "enable radio"); | |
1202 | ||
1203 | priv->isr_stats.rfkill++; | |
1204 | ||
1205 | /* driver only loads ucode once setting the interface up. | |
1206 | * the driver allows loading the ucode even if the radio | |
1207 | * is killed. Hence update the killswitch state here. The | |
1208 | * rfkill handler will care about restarting if needed. | |
1209 | */ | |
1210 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1211 | if (hw_rf_kill) | |
1212 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1213 | else | |
1214 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1215 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1216 | } |
1217 | ||
1218 | handled |= CSR_INT_BIT_RF_KILL; | |
1219 | } | |
1220 | ||
1221 | /* Chip got too hot and stopped itself */ | |
1222 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1223 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1224 | priv->isr_stats.ctkill++; | |
1225 | handled |= CSR_INT_BIT_CT_KILL; | |
1226 | } | |
1227 | ||
1228 | /* Error detected by uCode */ | |
1229 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1230 | IWL_ERR(priv, "Microcode SW error detected. " | |
1231 | " Restarting 0x%X.\n", inta); | |
1232 | priv->isr_stats.sw++; | |
1233 | priv->isr_stats.sw_err = inta; | |
1234 | iwl_irq_handle_error(priv); | |
1235 | handled |= CSR_INT_BIT_SW_ERR; | |
1236 | } | |
1237 | ||
1238 | /* uCode wakes up after power-down sleep */ | |
1239 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1240 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1241 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
1242 | iwl_txq_update_write_ptr(priv, &priv->txq[0]); | |
1243 | iwl_txq_update_write_ptr(priv, &priv->txq[1]); | |
1244 | iwl_txq_update_write_ptr(priv, &priv->txq[2]); | |
1245 | iwl_txq_update_write_ptr(priv, &priv->txq[3]); | |
1246 | iwl_txq_update_write_ptr(priv, &priv->txq[4]); | |
1247 | iwl_txq_update_write_ptr(priv, &priv->txq[5]); | |
1248 | ||
1249 | priv->isr_stats.wakeup++; | |
1250 | ||
1251 | handled |= CSR_INT_BIT_WAKEUP; | |
1252 | } | |
1253 | ||
1254 | /* All uCode command responses, including Tx command responses, | |
1255 | * Rx "responses" (frame-received notification), and other | |
1256 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1257 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1258 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1259 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1260 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1261 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1262 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1263 | CSR49_FH_INT_RX_MASK); | |
1264 | } | |
1265 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1266 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1267 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1268 | } | |
1269 | /* Sending RX interrupt require many steps to be done in the | |
1270 | * the device: | |
1271 | * 1- write interrupt to current index in ICT table. | |
1272 | * 2- dma RX frame. | |
1273 | * 3- update RX shared data to indicate last write index. | |
1274 | * 4- send interrupt. | |
1275 | * This could lead to RX race, driver could receive RX interrupt | |
1276 | * but the shared data changes does not reflect this. | |
1277 | * this could lead to RX race, RX periodic will solve this race | |
1278 | */ | |
1279 | iwl_write32(priv, CSR_INT_PERIODIC_REG, | |
1280 | CSR_INT_PERIODIC_DIS); | |
ef850d7c | 1281 | iwl_rx_handle(priv); |
40cefda9 MA |
1282 | /* Only set RX periodic if real RX is received. */ |
1283 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) | |
1284 | iwl_write32(priv, CSR_INT_PERIODIC_REG, | |
1285 | CSR_INT_PERIODIC_ENA); | |
1286 | ||
ef850d7c | 1287 | priv->isr_stats.rx++; |
ef850d7c MA |
1288 | } |
1289 | ||
1290 | if (inta & CSR_INT_BIT_FH_TX) { | |
1291 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
1292 | IWL_DEBUG_ISR(priv, "Tx interrupt\n"); | |
1293 | priv->isr_stats.tx++; | |
1294 | handled |= CSR_INT_BIT_FH_TX; | |
1295 | /* FH finished to write, send event */ | |
1296 | priv->ucode_write_complete = 1; | |
1297 | wake_up_interruptible(&priv->wait_command_queue); | |
1298 | } | |
1299 | ||
1300 | if (inta & ~handled) { | |
1301 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1302 | priv->isr_stats.unhandled++; | |
1303 | } | |
1304 | ||
40cefda9 | 1305 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1306 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1307 | inta & ~priv->inta_mask); |
ef850d7c MA |
1308 | } |
1309 | ||
1310 | ||
1311 | /* Re-enable all interrupts */ | |
1312 | /* only Re-enable if diabled by irq */ | |
1313 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1314 | iwl_enable_interrupts(priv); | |
1315 | ||
1316 | spin_unlock_irqrestore(&priv->lock, flags); | |
1317 | ||
1318 | } | |
1319 | ||
a83b9141 | 1320 | |
b481de9c ZY |
1321 | /****************************************************************************** |
1322 | * | |
1323 | * uCode download functions | |
1324 | * | |
1325 | ******************************************************************************/ | |
1326 | ||
5b9f8cd3 | 1327 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1328 | { |
98c92211 TW |
1329 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1330 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1331 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1332 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1333 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1334 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1335 | } |
1336 | ||
5b9f8cd3 | 1337 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1338 | { |
1339 | /* Remove all resets to allow NIC to operate */ | |
1340 | iwl_write32(priv, CSR_RESET, 0); | |
1341 | } | |
1342 | ||
1343 | ||
b481de9c | 1344 | /** |
5b9f8cd3 | 1345 | * iwl_read_ucode - Read uCode images from disk file. |
b481de9c ZY |
1346 | * |
1347 | * Copy into buffers for card to fetch via bus-mastering | |
1348 | */ | |
5b9f8cd3 | 1349 | static int iwl_read_ucode(struct iwl_priv *priv) |
b481de9c | 1350 | { |
14b3d338 | 1351 | struct iwl_ucode *ucode; |
a0987a8d | 1352 | int ret = -EINVAL, index; |
b481de9c | 1353 | const struct firmware *ucode_raw; |
a0987a8d RC |
1354 | const char *name_pre = priv->cfg->fw_name_pre; |
1355 | const unsigned int api_max = priv->cfg->ucode_api_max; | |
1356 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
1357 | char buf[25]; | |
b481de9c ZY |
1358 | u8 *src; |
1359 | size_t len; | |
a0987a8d | 1360 | u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size; |
b481de9c ZY |
1361 | |
1362 | /* Ask kernel firmware_class module to get the boot firmware off disk. | |
1363 | * request_firmware() is synchronous, file is in memory on return. */ | |
a0987a8d RC |
1364 | for (index = api_max; index >= api_min; index--) { |
1365 | sprintf(buf, "%s%d%s", name_pre, index, ".ucode"); | |
1366 | ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); | |
1367 | if (ret < 0) { | |
15b1687c | 1368 | IWL_ERR(priv, "%s firmware file req failed: %d\n", |
a0987a8d RC |
1369 | buf, ret); |
1370 | if (ret == -ENOENT) | |
1371 | continue; | |
1372 | else | |
1373 | goto error; | |
1374 | } else { | |
1375 | if (index < api_max) | |
15b1687c WT |
1376 | IWL_ERR(priv, "Loaded firmware %s, " |
1377 | "which is deprecated. " | |
1378 | "Please use API v%u instead.\n", | |
a0987a8d | 1379 | buf, api_max); |
15b1687c | 1380 | |
e1623446 | 1381 | IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n", |
a0987a8d RC |
1382 | buf, ucode_raw->size); |
1383 | break; | |
1384 | } | |
b481de9c ZY |
1385 | } |
1386 | ||
a0987a8d RC |
1387 | if (ret < 0) |
1388 | goto error; | |
b481de9c ZY |
1389 | |
1390 | /* Make sure that we got at least our header! */ | |
1391 | if (ucode_raw->size < sizeof(*ucode)) { | |
15b1687c | 1392 | IWL_ERR(priv, "File size way too small!\n"); |
90e759d1 | 1393 | ret = -EINVAL; |
b481de9c ZY |
1394 | goto err_release; |
1395 | } | |
1396 | ||
1397 | /* Data from ucode file: header followed by uCode images */ | |
1398 | ucode = (void *)ucode_raw->data; | |
1399 | ||
c02b3acd | 1400 | priv->ucode_ver = le32_to_cpu(ucode->ver); |
a0987a8d | 1401 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
b481de9c ZY |
1402 | inst_size = le32_to_cpu(ucode->inst_size); |
1403 | data_size = le32_to_cpu(ucode->data_size); | |
1404 | init_size = le32_to_cpu(ucode->init_size); | |
1405 | init_data_size = le32_to_cpu(ucode->init_data_size); | |
1406 | boot_size = le32_to_cpu(ucode->boot_size); | |
1407 | ||
a0987a8d RC |
1408 | /* api_ver should match the api version forming part of the |
1409 | * firmware filename ... but we don't check for that and only rely | |
877d0310 | 1410 | * on the API version read from firmware header from here on forward */ |
a0987a8d RC |
1411 | |
1412 | if (api_ver < api_min || api_ver > api_max) { | |
15b1687c | 1413 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
1414 | "Driver supports v%u, firmware is v%u.\n", |
1415 | api_max, api_ver); | |
1416 | priv->ucode_ver = 0; | |
1417 | ret = -EINVAL; | |
1418 | goto err_release; | |
1419 | } | |
1420 | if (api_ver != api_max) | |
978785a3 | 1421 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
1422 | "got v%u. New firmware can be obtained " |
1423 | "from http://www.intellinuxwireless.org.\n", | |
1424 | api_max, api_ver); | |
1425 | ||
978785a3 TW |
1426 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n", |
1427 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1428 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1429 | IWL_UCODE_API(priv->ucode_ver), | |
1430 | IWL_UCODE_SERIAL(priv->ucode_ver)); | |
a0987a8d | 1431 | |
e1623446 | 1432 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
a0987a8d | 1433 | priv->ucode_ver); |
e1623446 | 1434 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n", |
b481de9c | 1435 | inst_size); |
e1623446 | 1436 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n", |
b481de9c | 1437 | data_size); |
e1623446 | 1438 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n", |
b481de9c | 1439 | init_size); |
e1623446 | 1440 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n", |
b481de9c | 1441 | init_data_size); |
e1623446 | 1442 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n", |
b481de9c ZY |
1443 | boot_size); |
1444 | ||
1445 | /* Verify size of file vs. image size info in file's header */ | |
1446 | if (ucode_raw->size < sizeof(*ucode) + | |
1447 | inst_size + data_size + init_size + | |
1448 | init_data_size + boot_size) { | |
1449 | ||
e1623446 | 1450 | IWL_DEBUG_INFO(priv, "uCode file size %d too small\n", |
b481de9c | 1451 | (int)ucode_raw->size); |
90e759d1 | 1452 | ret = -EINVAL; |
b481de9c ZY |
1453 | goto err_release; |
1454 | } | |
1455 | ||
1456 | /* Verify that uCode images will fit in card's SRAM */ | |
099b40b7 | 1457 | if (inst_size > priv->hw_params.max_inst_size) { |
e1623446 | 1458 | IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n", |
90e759d1 TW |
1459 | inst_size); |
1460 | ret = -EINVAL; | |
b481de9c ZY |
1461 | goto err_release; |
1462 | } | |
1463 | ||
099b40b7 | 1464 | if (data_size > priv->hw_params.max_data_size) { |
e1623446 | 1465 | IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n", |
90e759d1 TW |
1466 | data_size); |
1467 | ret = -EINVAL; | |
b481de9c ZY |
1468 | goto err_release; |
1469 | } | |
099b40b7 | 1470 | if (init_size > priv->hw_params.max_inst_size) { |
e1623446 TW |
1471 | IWL_INFO(priv, "uCode init instr len %d too large to fit in\n", |
1472 | init_size); | |
90e759d1 | 1473 | ret = -EINVAL; |
b481de9c ZY |
1474 | goto err_release; |
1475 | } | |
099b40b7 | 1476 | if (init_data_size > priv->hw_params.max_data_size) { |
e1623446 | 1477 | IWL_INFO(priv, "uCode init data len %d too large to fit in\n", |
90e759d1 TW |
1478 | init_data_size); |
1479 | ret = -EINVAL; | |
b481de9c ZY |
1480 | goto err_release; |
1481 | } | |
099b40b7 | 1482 | if (boot_size > priv->hw_params.max_bsm_size) { |
e1623446 TW |
1483 | IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n", |
1484 | boot_size); | |
90e759d1 | 1485 | ret = -EINVAL; |
b481de9c ZY |
1486 | goto err_release; |
1487 | } | |
1488 | ||
1489 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1490 | ||
1491 | /* Runtime instructions and 2 copies of data: | |
1492 | * 1) unmodified from disk | |
1493 | * 2) backup cache for save/restore during power-downs */ | |
1494 | priv->ucode_code.len = inst_size; | |
98c92211 | 1495 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c ZY |
1496 | |
1497 | priv->ucode_data.len = data_size; | |
98c92211 | 1498 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c ZY |
1499 | |
1500 | priv->ucode_data_backup.len = data_size; | |
98c92211 | 1501 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 1502 | |
1f304e4e ZY |
1503 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
1504 | !priv->ucode_data_backup.v_addr) | |
1505 | goto err_pci_alloc; | |
1506 | ||
b481de9c | 1507 | /* Initialization instructions and data */ |
90e759d1 TW |
1508 | if (init_size && init_data_size) { |
1509 | priv->ucode_init.len = init_size; | |
98c92211 | 1510 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 TW |
1511 | |
1512 | priv->ucode_init_data.len = init_data_size; | |
98c92211 | 1513 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1514 | |
1515 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1516 | goto err_pci_alloc; | |
1517 | } | |
b481de9c ZY |
1518 | |
1519 | /* Bootstrap (instructions only, no data) */ | |
90e759d1 TW |
1520 | if (boot_size) { |
1521 | priv->ucode_boot.len = boot_size; | |
98c92211 | 1522 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 1523 | |
90e759d1 TW |
1524 | if (!priv->ucode_boot.v_addr) |
1525 | goto err_pci_alloc; | |
1526 | } | |
b481de9c ZY |
1527 | |
1528 | /* Copy images into buffers for card's bus-master reads ... */ | |
1529 | ||
1530 | /* Runtime instructions (first block of data in file) */ | |
1531 | src = &ucode->data[0]; | |
1532 | len = priv->ucode_code.len; | |
e1623446 | 1533 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len); |
b481de9c | 1534 | memcpy(priv->ucode_code.v_addr, src, len); |
e1623446 | 1535 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
1536 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
1537 | ||
1538 | /* Runtime data (2nd block) | |
5b9f8cd3 | 1539 | * NOTE: Copy into backup buffer will be done in iwl_up() */ |
b481de9c ZY |
1540 | src = &ucode->data[inst_size]; |
1541 | len = priv->ucode_data.len; | |
e1623446 | 1542 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len); |
b481de9c ZY |
1543 | memcpy(priv->ucode_data.v_addr, src, len); |
1544 | memcpy(priv->ucode_data_backup.v_addr, src, len); | |
1545 | ||
1546 | /* Initialization instructions (3rd block) */ | |
1547 | if (init_size) { | |
1548 | src = &ucode->data[inst_size + data_size]; | |
1549 | len = priv->ucode_init.len; | |
e1623446 | 1550 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
90e759d1 | 1551 | len); |
b481de9c ZY |
1552 | memcpy(priv->ucode_init.v_addr, src, len); |
1553 | } | |
1554 | ||
1555 | /* Initialization data (4th block) */ | |
1556 | if (init_data_size) { | |
1557 | src = &ucode->data[inst_size + data_size + init_size]; | |
1558 | len = priv->ucode_init_data.len; | |
e1623446 | 1559 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
90e759d1 | 1560 | len); |
b481de9c ZY |
1561 | memcpy(priv->ucode_init_data.v_addr, src, len); |
1562 | } | |
1563 | ||
1564 | /* Bootstrap instructions (5th block) */ | |
1565 | src = &ucode->data[inst_size + data_size + init_size + init_data_size]; | |
1566 | len = priv->ucode_boot.len; | |
e1623446 | 1567 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len); |
b481de9c ZY |
1568 | memcpy(priv->ucode_boot.v_addr, src, len); |
1569 | ||
1570 | /* We have our copies now, allow OS release its copies */ | |
1571 | release_firmware(ucode_raw); | |
1572 | return 0; | |
1573 | ||
1574 | err_pci_alloc: | |
15b1687c | 1575 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
90e759d1 | 1576 | ret = -ENOMEM; |
5b9f8cd3 | 1577 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
1578 | |
1579 | err_release: | |
1580 | release_firmware(ucode_raw); | |
1581 | ||
1582 | error: | |
90e759d1 | 1583 | return ret; |
b481de9c ZY |
1584 | } |
1585 | ||
b481de9c | 1586 | /** |
4a4a9e81 | 1587 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 1588 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 1589 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 1590 | */ |
4a4a9e81 | 1591 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 1592 | { |
57aab75a | 1593 | int ret = 0; |
b481de9c | 1594 | |
e1623446 | 1595 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
1596 | |
1597 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
1598 | /* We had an error bringing up the hardware, so take it | |
1599 | * all the way back down so we can try again */ | |
e1623446 | 1600 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
1601 | goto restart; |
1602 | } | |
1603 | ||
1604 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
1605 | * This is a paranoid check, because we would not have gotten the | |
1606 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 1607 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
1608 | /* Runtime instruction load was bad; |
1609 | * take it all the way back down so we can try again */ | |
e1623446 | 1610 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
1611 | goto restart; |
1612 | } | |
1613 | ||
c587de0b | 1614 | iwl_clear_stations_table(priv); |
57aab75a TW |
1615 | ret = priv->cfg->ops->lib->alive_notify(priv); |
1616 | if (ret) { | |
39aadf8c WT |
1617 | IWL_WARN(priv, |
1618 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
1619 | goto restart; |
1620 | } | |
1621 | ||
5b9f8cd3 | 1622 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
1623 | set_bit(STATUS_ALIVE, &priv->status); |
1624 | ||
fee1247a | 1625 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
1626 | return; |
1627 | ||
36d6825b | 1628 | ieee80211_wake_queues(priv->hw); |
b481de9c ZY |
1629 | |
1630 | priv->active_rate = priv->rates_mask; | |
1631 | priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK; | |
1632 | ||
3109ece1 | 1633 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
1634 | struct iwl_rxon_cmd *active_rxon = |
1635 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
019fb97d MA |
1636 | /* apply any changes in staging */ |
1637 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
b481de9c ZY |
1638 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
1639 | } else { | |
1640 | /* Initialize our rx_config data */ | |
5b9f8cd3 | 1641 | iwl_connection_init_rx_config(priv, priv->iw_mode); |
45823531 AK |
1642 | |
1643 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
1644 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
1645 | ||
b481de9c ZY |
1646 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
1647 | } | |
1648 | ||
9fbab516 | 1649 | /* Configure Bluetooth device coexistence support */ |
5b9f8cd3 | 1650 | iwl_send_bt_config(priv); |
b481de9c | 1651 | |
4a4a9e81 TW |
1652 | iwl_reset_run_time_calib(priv); |
1653 | ||
b481de9c | 1654 | /* Configure the adapter for unassociated operation */ |
e0158e61 | 1655 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
1656 | |
1657 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 1658 | iwl_rf_kill_ct_config(priv); |
5a66926a | 1659 | |
fe00b5a5 RC |
1660 | iwl_leds_register(priv); |
1661 | ||
e1623446 | 1662 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 1663 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 1664 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 1665 | |
58d0f361 | 1666 | iwl_power_update_mode(priv, 1); |
c46fbefa | 1667 | |
ada17513 MA |
1668 | /* reassociate for ADHOC mode */ |
1669 | if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) { | |
1670 | struct sk_buff *beacon = ieee80211_beacon_get(priv->hw, | |
1671 | priv->vif); | |
1672 | if (beacon) | |
1673 | iwl_mac_beacon_update(priv->hw, beacon); | |
1674 | } | |
1675 | ||
1676 | ||
c46fbefa | 1677 | if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status)) |
5b9f8cd3 | 1678 | iwl_set_mode(priv, priv->iw_mode); |
c46fbefa | 1679 | |
b481de9c ZY |
1680 | return; |
1681 | ||
1682 | restart: | |
1683 | queue_work(priv->workqueue, &priv->restart); | |
1684 | } | |
1685 | ||
4e39317d | 1686 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 1687 | |
5b9f8cd3 | 1688 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1689 | { |
1690 | unsigned long flags; | |
1691 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 1692 | |
e1623446 | 1693 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 1694 | |
b481de9c ZY |
1695 | if (!exit_pending) |
1696 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
1697 | ||
ab53d8af MA |
1698 | iwl_leds_unregister(priv); |
1699 | ||
c587de0b | 1700 | iwl_clear_stations_table(priv); |
b481de9c ZY |
1701 | |
1702 | /* Unblock any waiting calls */ | |
1703 | wake_up_interruptible_all(&priv->wait_command_queue); | |
1704 | ||
b481de9c ZY |
1705 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
1706 | * exiting the module */ | |
1707 | if (!exit_pending) | |
1708 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
1709 | ||
1710 | /* stop and reset the on-board processor */ | |
3395f6e9 | 1711 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
1712 | |
1713 | /* tell the device to stop sending interrupts */ | |
0359facc | 1714 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 1715 | iwl_disable_interrupts(priv); |
0359facc MA |
1716 | spin_unlock_irqrestore(&priv->lock, flags); |
1717 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
1718 | |
1719 | if (priv->mac80211_registered) | |
1720 | ieee80211_stop_queues(priv->hw); | |
1721 | ||
5b9f8cd3 | 1722 | /* If we have not previously called iwl_init() then |
a60e77e5 | 1723 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 1724 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
1725 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1726 | STATUS_RF_KILL_HW | | |
9788864e RC |
1727 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1728 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
1729 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
1730 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
1731 | goto exit; |
1732 | } | |
1733 | ||
6da3a13e | 1734 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 1735 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
1736 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
1737 | STATUS_RF_KILL_HW | | |
9788864e RC |
1738 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
1739 | STATUS_GEO_CONFIGURED | | |
b481de9c | 1740 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
1741 | STATUS_FW_ERROR | |
1742 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
1743 | STATUS_EXIT_PENDING; | |
b481de9c | 1744 | |
ef850d7c MA |
1745 | /* device going down, Stop using ICT table */ |
1746 | iwl_disable_ict(priv); | |
b481de9c | 1747 | spin_lock_irqsave(&priv->lock, flags); |
3395f6e9 | 1748 | iwl_clear_bit(priv, CSR_GP_CNTRL, |
9fbab516 | 1749 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
b481de9c ZY |
1750 | spin_unlock_irqrestore(&priv->lock, flags); |
1751 | ||
da1bc453 | 1752 | iwl_txq_ctx_stop(priv); |
b3bbacb7 | 1753 | iwl_rxq_stop(priv); |
b481de9c | 1754 | |
a8b50a0a MA |
1755 | iwl_write_prph(priv, APMG_CLK_DIS_REG, |
1756 | APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
1757 | |
1758 | udelay(5); | |
1759 | ||
7f066108 | 1760 | /* FIXME: apm_ops.suspend(priv) */ |
6da3a13e | 1761 | if (exit_pending) |
d535311e GG |
1762 | priv->cfg->ops->lib->apm_ops.stop(priv); |
1763 | else | |
1764 | priv->cfg->ops->lib->apm_ops.reset(priv); | |
b481de9c | 1765 | exit: |
885ba202 | 1766 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
1767 | |
1768 | if (priv->ibss_beacon) | |
1769 | dev_kfree_skb(priv->ibss_beacon); | |
1770 | priv->ibss_beacon = NULL; | |
1771 | ||
1772 | /* clear out any free frames */ | |
fcab423d | 1773 | iwl_clear_free_frames(priv); |
b481de9c ZY |
1774 | } |
1775 | ||
5b9f8cd3 | 1776 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
1777 | { |
1778 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 1779 | __iwl_down(priv); |
b481de9c | 1780 | mutex_unlock(&priv->mutex); |
b24d22b1 | 1781 | |
4e39317d | 1782 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
1783 | } |
1784 | ||
086ed117 MA |
1785 | #define HW_READY_TIMEOUT (50) |
1786 | ||
1787 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
1788 | { | |
1789 | int ret = 0; | |
1790 | ||
1791 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1792 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
1793 | ||
1794 | /* See if we got it */ | |
1795 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1796 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
1797 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
1798 | HW_READY_TIMEOUT); | |
1799 | if (ret != -ETIMEDOUT) | |
1800 | priv->hw_ready = true; | |
1801 | else | |
1802 | priv->hw_ready = false; | |
1803 | ||
1804 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
1805 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
1806 | return ret; | |
1807 | } | |
1808 | ||
1809 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
1810 | { | |
1811 | int ret = 0; | |
1812 | ||
1813 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n"); | |
1814 | ||
3354a0f6 MA |
1815 | ret = iwl_set_hw_ready(priv); |
1816 | if (priv->hw_ready) | |
1817 | return ret; | |
1818 | ||
1819 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
1820 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
1821 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
1822 | ||
1823 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
1824 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
1825 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
1826 | ||
3354a0f6 | 1827 | /* HW should be ready by now, check again. */ |
086ed117 MA |
1828 | if (ret != -ETIMEDOUT) |
1829 | iwl_set_hw_ready(priv); | |
1830 | ||
1831 | return ret; | |
1832 | } | |
1833 | ||
b481de9c ZY |
1834 | #define MAX_HW_RESTARTS 5 |
1835 | ||
5b9f8cd3 | 1836 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 1837 | { |
57aab75a TW |
1838 | int i; |
1839 | int ret; | |
b481de9c ZY |
1840 | |
1841 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 1842 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
1843 | return -EIO; |
1844 | } | |
1845 | ||
e903fbd4 | 1846 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 1847 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
1848 | return -EIO; |
1849 | } | |
1850 | ||
086ed117 MA |
1851 | iwl_prepare_card_hw(priv); |
1852 | ||
1853 | if (!priv->hw_ready) { | |
1854 | IWL_WARN(priv, "Exit HW not ready\n"); | |
1855 | return -EIO; | |
1856 | } | |
1857 | ||
e655b9f0 | 1858 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 1859 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 1860 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1861 | else |
e655b9f0 | 1862 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 1863 | |
c1842d61 | 1864 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
1865 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
1866 | ||
5b9f8cd3 | 1867 | iwl_enable_interrupts(priv); |
a60e77e5 | 1868 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 1869 | return 0; |
b481de9c ZY |
1870 | } |
1871 | ||
3395f6e9 | 1872 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 1873 | |
1053d35f | 1874 | ret = iwl_hw_nic_init(priv); |
57aab75a | 1875 | if (ret) { |
15b1687c | 1876 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 1877 | return ret; |
b481de9c ZY |
1878 | } |
1879 | ||
1880 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
1881 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1882 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
1883 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
1884 | ||
1885 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 1886 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 1887 | iwl_enable_interrupts(priv); |
b481de9c ZY |
1888 | |
1889 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
1890 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
1891 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
1892 | |
1893 | /* Copy original ucode data image from disk into backup cache. | |
1894 | * This will be used to initialize the on-board processor's | |
1895 | * data SRAM for a clean start when the runtime program first loads. */ | |
1896 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 1897 | priv->ucode_data.len); |
b481de9c | 1898 | |
b481de9c ZY |
1899 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
1900 | ||
c587de0b | 1901 | iwl_clear_stations_table(priv); |
b481de9c ZY |
1902 | |
1903 | /* load bootstrap state machine, | |
1904 | * load bootstrap program into processor's memory, | |
1905 | * prepare to load the "initialize" uCode */ | |
57aab75a | 1906 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 1907 | |
57aab75a | 1908 | if (ret) { |
15b1687c WT |
1909 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
1910 | ret); | |
b481de9c ZY |
1911 | continue; |
1912 | } | |
1913 | ||
1914 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 1915 | iwl_nic_start(priv); |
b481de9c | 1916 | |
e1623446 | 1917 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
1918 | |
1919 | return 0; | |
1920 | } | |
1921 | ||
1922 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 1923 | __iwl_down(priv); |
64e72c3e | 1924 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
1925 | |
1926 | /* tried to restart and config the device for as long as our | |
1927 | * patience could withstand */ | |
15b1687c | 1928 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
1929 | return -EIO; |
1930 | } | |
1931 | ||
1932 | ||
1933 | /***************************************************************************** | |
1934 | * | |
1935 | * Workqueue callbacks | |
1936 | * | |
1937 | *****************************************************************************/ | |
1938 | ||
4a4a9e81 | 1939 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 1940 | { |
c79dd5b5 TW |
1941 | struct iwl_priv *priv = |
1942 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
1943 | |
1944 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1945 | return; | |
1946 | ||
1947 | mutex_lock(&priv->mutex); | |
f3ccc08c | 1948 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
1949 | mutex_unlock(&priv->mutex); |
1950 | } | |
1951 | ||
4a4a9e81 | 1952 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 1953 | { |
c79dd5b5 TW |
1954 | struct iwl_priv *priv = |
1955 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
1956 | |
1957 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1958 | return; | |
1959 | ||
258c44a0 MA |
1960 | /* enable dram interrupt */ |
1961 | iwl_reset_ict(priv); | |
1962 | ||
b481de9c | 1963 | mutex_lock(&priv->mutex); |
4a4a9e81 | 1964 | iwl_alive_start(priv); |
b481de9c ZY |
1965 | mutex_unlock(&priv->mutex); |
1966 | } | |
1967 | ||
16e727e8 EG |
1968 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
1969 | { | |
1970 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
1971 | run_time_calib_work); | |
1972 | ||
1973 | mutex_lock(&priv->mutex); | |
1974 | ||
1975 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
1976 | test_bit(STATUS_SCANNING, &priv->status)) { | |
1977 | mutex_unlock(&priv->mutex); | |
1978 | return; | |
1979 | } | |
1980 | ||
1981 | if (priv->start_calib) { | |
1982 | iwl_chain_noise_calibration(priv, &priv->statistics); | |
1983 | ||
1984 | iwl_sensitivity_calibration(priv, &priv->statistics); | |
1985 | } | |
1986 | ||
1987 | mutex_unlock(&priv->mutex); | |
1988 | return; | |
1989 | } | |
1990 | ||
5b9f8cd3 | 1991 | static void iwl_bg_up(struct work_struct *data) |
b481de9c | 1992 | { |
c79dd5b5 | 1993 | struct iwl_priv *priv = container_of(data, struct iwl_priv, up); |
b481de9c ZY |
1994 | |
1995 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
1996 | return; | |
1997 | ||
1998 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 1999 | __iwl_up(priv); |
b481de9c ZY |
2000 | mutex_unlock(&priv->mutex); |
2001 | } | |
2002 | ||
5b9f8cd3 | 2003 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2004 | { |
c79dd5b5 | 2005 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2006 | |
2007 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2008 | return; | |
2009 | ||
19cc1087 JB |
2010 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
2011 | mutex_lock(&priv->mutex); | |
2012 | priv->vif = NULL; | |
2013 | priv->is_open = 0; | |
2014 | mutex_unlock(&priv->mutex); | |
2015 | iwl_down(priv); | |
2016 | ieee80211_restart_hw(priv->hw); | |
2017 | } else { | |
2018 | iwl_down(priv); | |
2019 | queue_work(priv->workqueue, &priv->up); | |
2020 | } | |
b481de9c ZY |
2021 | } |
2022 | ||
5b9f8cd3 | 2023 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2024 | { |
c79dd5b5 TW |
2025 | struct iwl_priv *priv = |
2026 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2027 | |
2028 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2029 | return; | |
2030 | ||
2031 | mutex_lock(&priv->mutex); | |
a55360e4 | 2032 | iwl_rx_replenish(priv); |
b481de9c ZY |
2033 | mutex_unlock(&priv->mutex); |
2034 | } | |
2035 | ||
7878a5a4 MA |
2036 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
2037 | ||
5bbe233b | 2038 | void iwl_post_associate(struct iwl_priv *priv) |
b481de9c | 2039 | { |
b481de9c | 2040 | struct ieee80211_conf *conf = NULL; |
857485c0 | 2041 | int ret = 0; |
1ff50bda | 2042 | unsigned long flags; |
b481de9c | 2043 | |
05c914fe | 2044 | if (priv->iw_mode == NL80211_IFTYPE_AP) { |
15b1687c | 2045 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
2046 | return; |
2047 | } | |
2048 | ||
e1623446 | 2049 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
e174961c | 2050 | priv->assoc_id, priv->active_rxon.bssid_addr); |
b481de9c ZY |
2051 | |
2052 | ||
2053 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2054 | return; | |
2055 | ||
b481de9c | 2056 | |
508e32e1 | 2057 | if (!priv->vif || !priv->is_open) |
948c171c | 2058 | return; |
508e32e1 | 2059 | |
2a421b91 | 2060 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 2061 | |
b481de9c ZY |
2062 | conf = ieee80211_get_hw_conf(priv->hw); |
2063 | ||
2064 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2065 | iwlcore_commit_rxon(priv); |
b481de9c | 2066 | |
3195c1f3 | 2067 | iwl_setup_rxon_timing(priv); |
857485c0 | 2068 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2069 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2070 | if (ret) |
39aadf8c | 2071 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2072 | "Attempting to continue.\n"); |
2073 | ||
2074 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2075 | ||
42eb7c64 | 2076 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 2077 | |
45823531 AK |
2078 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2079 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2080 | ||
b481de9c ZY |
2081 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); |
2082 | ||
e1623446 | 2083 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
b481de9c ZY |
2084 | priv->assoc_id, priv->beacon_int); |
2085 | ||
2086 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2087 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2088 | else | |
2089 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2090 | ||
2091 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2092 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2093 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2094 | else | |
2095 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2096 | ||
05c914fe | 2097 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2098 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
2099 | ||
2100 | } | |
2101 | ||
e0158e61 | 2102 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2103 | |
2104 | switch (priv->iw_mode) { | |
05c914fe | 2105 | case NL80211_IFTYPE_STATION: |
b481de9c ZY |
2106 | break; |
2107 | ||
05c914fe | 2108 | case NL80211_IFTYPE_ADHOC: |
b481de9c | 2109 | |
c46fbefa AK |
2110 | /* assume default assoc id */ |
2111 | priv->assoc_id = 1; | |
b481de9c | 2112 | |
4f40e4d9 | 2113 | iwl_rxon_add_station(priv, priv->bssid, 0); |
5b9f8cd3 | 2114 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2115 | |
2116 | break; | |
2117 | ||
2118 | default: | |
15b1687c | 2119 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
3ac7f146 | 2120 | __func__, priv->iw_mode); |
b481de9c ZY |
2121 | break; |
2122 | } | |
2123 | ||
05c914fe | 2124 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2125 | priv->assoc_station_added = 1; |
2126 | ||
1ff50bda EG |
2127 | spin_lock_irqsave(&priv->lock, flags); |
2128 | iwl_activate_qos(priv, 0); | |
2129 | spin_unlock_irqrestore(&priv->lock, flags); | |
292ae174 | 2130 | |
04816448 GE |
2131 | /* the chain noise calibration will enabled PM upon completion |
2132 | * If chain noise has already been run, then we need to enable | |
2133 | * power management here */ | |
2134 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
7af2c460 | 2135 | iwl_power_update_mode(priv, 0); |
c90a74ba EG |
2136 | |
2137 | /* Enable Rx differential gain and sensitivity calibrations */ | |
2138 | iwl_chain_noise_reset(priv); | |
2139 | priv->start_calib = 1; | |
2140 | ||
508e32e1 RC |
2141 | } |
2142 | ||
b481de9c ZY |
2143 | /***************************************************************************** |
2144 | * | |
2145 | * mac80211 entry point functions | |
2146 | * | |
2147 | *****************************************************************************/ | |
2148 | ||
154b25ce | 2149 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 2150 | |
5b9f8cd3 | 2151 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2152 | { |
c79dd5b5 | 2153 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2154 | int ret; |
b481de9c | 2155 | |
e1623446 | 2156 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2157 | |
2158 | /* we should be verifying the device is ready to be opened */ | |
2159 | mutex_lock(&priv->mutex); | |
2160 | ||
5a66926a ZY |
2161 | /* fetch ucode file from disk, alloc and copy to bus-master buffers ... |
2162 | * ucode filename and max sizes are card-specific. */ | |
b481de9c | 2163 | |
5a66926a | 2164 | if (!priv->ucode_code.len) { |
5b9f8cd3 | 2165 | ret = iwl_read_ucode(priv); |
5a66926a | 2166 | if (ret) { |
15b1687c | 2167 | IWL_ERR(priv, "Could not read microcode: %d\n", ret); |
5a66926a | 2168 | mutex_unlock(&priv->mutex); |
6cd0b1cb | 2169 | return ret; |
5a66926a ZY |
2170 | } |
2171 | } | |
b481de9c | 2172 | |
5b9f8cd3 | 2173 | ret = __iwl_up(priv); |
5a66926a | 2174 | |
b481de9c | 2175 | mutex_unlock(&priv->mutex); |
5a66926a | 2176 | |
e655b9f0 | 2177 | if (ret) |
6cd0b1cb | 2178 | return ret; |
e655b9f0 | 2179 | |
c1842d61 TW |
2180 | if (iwl_is_rfkill(priv)) |
2181 | goto out; | |
2182 | ||
e1623446 | 2183 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2184 | |
fe9b6b72 | 2185 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 2186 | * mac80211 will not be run successfully. */ |
154b25ce EG |
2187 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
2188 | test_bit(STATUS_READY, &priv->status), | |
2189 | UCODE_READY_TIMEOUT); | |
2190 | if (!ret) { | |
2191 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 2192 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 2193 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 2194 | return -ETIMEDOUT; |
5a66926a | 2195 | } |
fe9b6b72 | 2196 | } |
0a078ffa | 2197 | |
c1842d61 | 2198 | out: |
0a078ffa | 2199 | priv->is_open = 1; |
e1623446 | 2200 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2201 | return 0; |
2202 | } | |
2203 | ||
5b9f8cd3 | 2204 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2205 | { |
c79dd5b5 | 2206 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2207 | |
e1623446 | 2208 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2209 | |
19cc1087 | 2210 | if (!priv->is_open) |
e655b9f0 | 2211 | return; |
e655b9f0 | 2212 | |
b481de9c | 2213 | priv->is_open = 0; |
5a66926a | 2214 | |
fee1247a | 2215 | if (iwl_is_ready_rf(priv)) { |
e655b9f0 ZY |
2216 | /* stop mac, cancel any scan request and clear |
2217 | * RXON_FILTER_ASSOC_MSK BIT | |
2218 | */ | |
5a66926a | 2219 | mutex_lock(&priv->mutex); |
2a421b91 | 2220 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 2221 | mutex_unlock(&priv->mutex); |
fde3571f MA |
2222 | } |
2223 | ||
5b9f8cd3 | 2224 | iwl_down(priv); |
5a66926a ZY |
2225 | |
2226 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
2227 | |
2228 | /* enable interrupts again in order to receive rfkill changes */ | |
2229 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
2230 | iwl_enable_interrupts(priv); | |
948c171c | 2231 | |
e1623446 | 2232 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2233 | } |
2234 | ||
5b9f8cd3 | 2235 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2236 | { |
c79dd5b5 | 2237 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2238 | |
e1623446 | 2239 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2240 | |
e1623446 | 2241 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2242 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2243 | |
e039fa4a | 2244 | if (iwl_tx_skb(priv, skb)) |
b481de9c ZY |
2245 | dev_kfree_skb_any(skb); |
2246 | ||
e1623446 | 2247 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 2248 | return NETDEV_TX_OK; |
b481de9c ZY |
2249 | } |
2250 | ||
60690a6a | 2251 | void iwl_config_ap(struct iwl_priv *priv) |
b481de9c | 2252 | { |
857485c0 | 2253 | int ret = 0; |
1ff50bda | 2254 | unsigned long flags; |
b481de9c | 2255 | |
d986bcd1 | 2256 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
2257 | return; |
2258 | ||
2259 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 2260 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
2261 | |
2262 | /* RXON - unassoc (to set timing command) */ | |
2263 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2264 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2265 | |
2266 | /* RXON Timing */ | |
3195c1f3 | 2267 | iwl_setup_rxon_timing(priv); |
857485c0 | 2268 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2269 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2270 | if (ret) |
39aadf8c | 2271 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2272 | "Attempting to continue.\n"); |
2273 | ||
45823531 AK |
2274 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2275 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c ZY |
2276 | |
2277 | /* FIXME: what should be the assoc_id for AP? */ | |
2278 | priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id); | |
2279 | if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) | |
2280 | priv->staging_rxon.flags |= | |
2281 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2282 | else | |
2283 | priv->staging_rxon.flags &= | |
2284 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2285 | ||
2286 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
2287 | if (priv->assoc_capability & | |
2288 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
2289 | priv->staging_rxon.flags |= | |
2290 | RXON_FLG_SHORT_SLOT_MSK; | |
2291 | else | |
2292 | priv->staging_rxon.flags &= | |
2293 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2294 | ||
05c914fe | 2295 | if (priv->iw_mode == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
2296 | priv->staging_rxon.flags &= |
2297 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2298 | } | |
2299 | /* restore RXON assoc */ | |
2300 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2301 | iwlcore_commit_rxon(priv); |
1ff50bda EG |
2302 | spin_lock_irqsave(&priv->lock, flags); |
2303 | iwl_activate_qos(priv, 1); | |
2304 | spin_unlock_irqrestore(&priv->lock, flags); | |
4f40e4d9 | 2305 | iwl_rxon_add_station(priv, iwl_bcast_addr, 0); |
e1493deb | 2306 | } |
5b9f8cd3 | 2307 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
2308 | |
2309 | /* FIXME - we need to add code here to detect a totally new | |
2310 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
2311 | * clear sta table, add BCAST sta... */ | |
2312 | } | |
2313 | ||
5b9f8cd3 | 2314 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
ab885f8c EG |
2315 | struct ieee80211_key_conf *keyconf, const u8 *addr, |
2316 | u32 iv32, u16 *phase1key) | |
2317 | { | |
ab885f8c | 2318 | |
9f58671e | 2319 | struct iwl_priv *priv = hw->priv; |
e1623446 | 2320 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2321 | |
9f58671e | 2322 | iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key); |
ab885f8c | 2323 | |
e1623446 | 2324 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2325 | } |
2326 | ||
5b9f8cd3 | 2327 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
2328 | struct ieee80211_vif *vif, |
2329 | struct ieee80211_sta *sta, | |
b481de9c ZY |
2330 | struct ieee80211_key_conf *key) |
2331 | { | |
c79dd5b5 | 2332 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
2333 | const u8 *addr; |
2334 | int ret; | |
2335 | u8 sta_id; | |
2336 | bool is_default_wep_key = false; | |
b481de9c | 2337 | |
e1623446 | 2338 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 2339 | |
099b40b7 | 2340 | if (priv->hw_params.sw_crypto) { |
e1623446 | 2341 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
2342 | return -EOPNOTSUPP; |
2343 | } | |
42986796 | 2344 | addr = sta ? sta->addr : iwl_bcast_addr; |
c587de0b | 2345 | sta_id = iwl_find_station(priv, addr); |
6974e363 | 2346 | if (sta_id == IWL_INVALID_STATION) { |
e1623446 | 2347 | IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n", |
e174961c | 2348 | addr); |
6974e363 | 2349 | return -EINVAL; |
b481de9c | 2350 | |
deb09c43 | 2351 | } |
b481de9c | 2352 | |
6974e363 | 2353 | mutex_lock(&priv->mutex); |
2a421b91 | 2354 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 EG |
2355 | mutex_unlock(&priv->mutex); |
2356 | ||
2357 | /* If we are getting WEP group key and we didn't receive any key mapping | |
2358 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
2359 | * in 1X mode. | |
2360 | * In legacy wep mode, we use another host command to the uCode */ | |
5425e490 | 2361 | if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id && |
05c914fe | 2362 | priv->iw_mode != NL80211_IFTYPE_AP) { |
6974e363 EG |
2363 | if (cmd == SET_KEY) |
2364 | is_default_wep_key = !priv->key_mapping_key; | |
2365 | else | |
ccc038ab EG |
2366 | is_default_wep_key = |
2367 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2368 | } |
052c4b9f | 2369 | |
b481de9c | 2370 | switch (cmd) { |
deb09c43 | 2371 | case SET_KEY: |
6974e363 EG |
2372 | if (is_default_wep_key) |
2373 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 2374 | else |
7480513f | 2375 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 | 2376 | |
e1623446 | 2377 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
2378 | break; |
2379 | case DISABLE_KEY: | |
6974e363 EG |
2380 | if (is_default_wep_key) |
2381 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 2382 | else |
3ec47732 | 2383 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 2384 | |
e1623446 | 2385 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
2386 | break; |
2387 | default: | |
deb09c43 | 2388 | ret = -EINVAL; |
b481de9c ZY |
2389 | } |
2390 | ||
e1623446 | 2391 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 2392 | |
deb09c43 | 2393 | return ret; |
b481de9c ZY |
2394 | } |
2395 | ||
5b9f8cd3 | 2396 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
d783b061 | 2397 | enum ieee80211_ampdu_mlme_action action, |
17741cdc | 2398 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) |
d783b061 TW |
2399 | { |
2400 | struct iwl_priv *priv = hw->priv; | |
5c2207c6 | 2401 | int ret; |
d783b061 | 2402 | |
e1623446 | 2403 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 2404 | sta->addr, tid); |
d783b061 TW |
2405 | |
2406 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
2407 | return -EACCES; | |
2408 | ||
2409 | switch (action) { | |
2410 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 2411 | IWL_DEBUG_HT(priv, "start Rx\n"); |
9f58671e | 2412 | return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn); |
d783b061 | 2413 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 2414 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
5c2207c6 WYG |
2415 | ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid); |
2416 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2417 | return 0; | |
2418 | else | |
2419 | return ret; | |
d783b061 | 2420 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 2421 | IWL_DEBUG_HT(priv, "start Tx\n"); |
17741cdc | 2422 | return iwl_tx_agg_start(priv, sta->addr, tid, ssn); |
d783b061 | 2423 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 2424 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
5c2207c6 WYG |
2425 | ret = iwl_tx_agg_stop(priv, sta->addr, tid); |
2426 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2427 | return 0; | |
2428 | else | |
2429 | return ret; | |
d783b061 | 2430 | default: |
e1623446 | 2431 | IWL_DEBUG_HT(priv, "unknown\n"); |
d783b061 TW |
2432 | return -EINVAL; |
2433 | break; | |
2434 | } | |
2435 | return 0; | |
2436 | } | |
9f58671e | 2437 | |
5b9f8cd3 | 2438 | static int iwl_mac_get_stats(struct ieee80211_hw *hw, |
b481de9c ZY |
2439 | struct ieee80211_low_level_stats *stats) |
2440 | { | |
bf403db8 EK |
2441 | struct iwl_priv *priv = hw->priv; |
2442 | ||
2443 | priv = hw->priv; | |
e1623446 TW |
2444 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
2445 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
b481de9c ZY |
2446 | |
2447 | return 0; | |
2448 | } | |
2449 | ||
b481de9c ZY |
2450 | /***************************************************************************** |
2451 | * | |
2452 | * sysfs attributes | |
2453 | * | |
2454 | *****************************************************************************/ | |
2455 | ||
0a6857e7 | 2456 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
2457 | |
2458 | /* | |
2459 | * The following adds a new attribute to the sysfs representation | |
c3a739fa | 2460 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) |
b481de9c ZY |
2461 | * used for controlling the debug level. |
2462 | * | |
2463 | * See the level definitions in iwl for details. | |
2464 | */ | |
2465 | ||
8cf769c6 EK |
2466 | static ssize_t show_debug_level(struct device *d, |
2467 | struct device_attribute *attr, char *buf) | |
b481de9c | 2468 | { |
928841b1 | 2469 | struct iwl_priv *priv = dev_get_drvdata(d); |
8cf769c6 EK |
2470 | |
2471 | return sprintf(buf, "0x%08X\n", priv->debug_level); | |
b481de9c | 2472 | } |
8cf769c6 EK |
2473 | static ssize_t store_debug_level(struct device *d, |
2474 | struct device_attribute *attr, | |
b481de9c ZY |
2475 | const char *buf, size_t count) |
2476 | { | |
928841b1 | 2477 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2478 | unsigned long val; |
2479 | int ret; | |
b481de9c | 2480 | |
9257746f TW |
2481 | ret = strict_strtoul(buf, 0, &val); |
2482 | if (ret) | |
978785a3 | 2483 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); |
b481de9c | 2484 | else |
8cf769c6 | 2485 | priv->debug_level = val; |
b481de9c ZY |
2486 | |
2487 | return strnlen(buf, count); | |
2488 | } | |
2489 | ||
8cf769c6 EK |
2490 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
2491 | show_debug_level, store_debug_level); | |
2492 | ||
b481de9c | 2493 | |
0a6857e7 | 2494 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 2495 | |
b481de9c | 2496 | |
bc6f59bc TW |
2497 | static ssize_t show_version(struct device *d, |
2498 | struct device_attribute *attr, char *buf) | |
2499 | { | |
928841b1 | 2500 | struct iwl_priv *priv = dev_get_drvdata(d); |
885ba202 | 2501 | struct iwl_alive_resp *palive = &priv->card_alive; |
f236a265 TW |
2502 | ssize_t pos = 0; |
2503 | u16 eeprom_ver; | |
bc6f59bc TW |
2504 | |
2505 | if (palive->is_valid) | |
f236a265 TW |
2506 | pos += sprintf(buf + pos, |
2507 | "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n" | |
2508 | "fw type: 0x%01X 0x%01X\n", | |
bc6f59bc TW |
2509 | palive->ucode_major, palive->ucode_minor, |
2510 | palive->sw_rev[0], palive->sw_rev[1], | |
2511 | palive->ver_type, palive->ver_subtype); | |
bc6f59bc | 2512 | else |
f236a265 TW |
2513 | pos += sprintf(buf + pos, "fw not loaded\n"); |
2514 | ||
2515 | if (priv->eeprom) { | |
2516 | eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); | |
0848e297 WYG |
2517 | pos += sprintf(buf + pos, "NVM Type: %s, version: 0x%x\n", |
2518 | (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) | |
2519 | ? "OTP" : "EEPROM", eeprom_ver); | |
2520 | ||
f236a265 TW |
2521 | } else { |
2522 | pos += sprintf(buf + pos, "EEPROM not initialzed\n"); | |
2523 | } | |
2524 | ||
2525 | return pos; | |
bc6f59bc TW |
2526 | } |
2527 | ||
2528 | static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL); | |
2529 | ||
b481de9c ZY |
2530 | static ssize_t show_temperature(struct device *d, |
2531 | struct device_attribute *attr, char *buf) | |
2532 | { | |
928841b1 | 2533 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 2534 | |
fee1247a | 2535 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2536 | return -EAGAIN; |
2537 | ||
91dbc5bd | 2538 | return sprintf(buf, "%d\n", priv->temperature); |
b481de9c ZY |
2539 | } |
2540 | ||
2541 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
2542 | ||
b481de9c ZY |
2543 | static ssize_t show_tx_power(struct device *d, |
2544 | struct device_attribute *attr, char *buf) | |
2545 | { | |
928841b1 | 2546 | struct iwl_priv *priv = dev_get_drvdata(d); |
91f39e8e JS |
2547 | |
2548 | if (!iwl_is_ready_rf(priv)) | |
2549 | return sprintf(buf, "off\n"); | |
2550 | else | |
2551 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
b481de9c ZY |
2552 | } |
2553 | ||
2554 | static ssize_t store_tx_power(struct device *d, | |
2555 | struct device_attribute *attr, | |
2556 | const char *buf, size_t count) | |
2557 | { | |
928841b1 | 2558 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2559 | unsigned long val; |
2560 | int ret; | |
b481de9c | 2561 | |
9257746f TW |
2562 | ret = strict_strtoul(buf, 10, &val); |
2563 | if (ret) | |
978785a3 | 2564 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); |
b481de9c | 2565 | else |
630fe9b6 | 2566 | iwl_set_tx_power(priv, val, false); |
b481de9c ZY |
2567 | |
2568 | return count; | |
2569 | } | |
2570 | ||
2571 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
2572 | ||
2573 | static ssize_t show_flags(struct device *d, | |
2574 | struct device_attribute *attr, char *buf) | |
2575 | { | |
928841b1 | 2576 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
2577 | |
2578 | return sprintf(buf, "0x%04X\n", priv->active_rxon.flags); | |
2579 | } | |
2580 | ||
2581 | static ssize_t store_flags(struct device *d, | |
2582 | struct device_attribute *attr, | |
2583 | const char *buf, size_t count) | |
2584 | { | |
928841b1 | 2585 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2586 | unsigned long val; |
2587 | u32 flags; | |
2588 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2589 | if (ret) |
9257746f TW |
2590 | return ret; |
2591 | flags = (u32)val; | |
b481de9c ZY |
2592 | |
2593 | mutex_lock(&priv->mutex); | |
2594 | if (le32_to_cpu(priv->staging_rxon.flags) != flags) { | |
2595 | /* Cancel any currently running scans... */ | |
2a421b91 | 2596 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2597 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2598 | else { |
e1623446 | 2599 | IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags); |
b481de9c | 2600 | priv->staging_rxon.flags = cpu_to_le32(flags); |
e0158e61 | 2601 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2602 | } |
2603 | } | |
2604 | mutex_unlock(&priv->mutex); | |
2605 | ||
2606 | return count; | |
2607 | } | |
2608 | ||
2609 | static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags); | |
2610 | ||
2611 | static ssize_t show_filter_flags(struct device *d, | |
2612 | struct device_attribute *attr, char *buf) | |
2613 | { | |
928841b1 | 2614 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c ZY |
2615 | |
2616 | return sprintf(buf, "0x%04X\n", | |
2617 | le32_to_cpu(priv->active_rxon.filter_flags)); | |
2618 | } | |
2619 | ||
2620 | static ssize_t store_filter_flags(struct device *d, | |
2621 | struct device_attribute *attr, | |
2622 | const char *buf, size_t count) | |
2623 | { | |
928841b1 | 2624 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
2625 | unsigned long val; |
2626 | u32 filter_flags; | |
2627 | int ret = strict_strtoul(buf, 0, &val); | |
926f0b2e | 2628 | if (ret) |
9257746f TW |
2629 | return ret; |
2630 | filter_flags = (u32)val; | |
b481de9c ZY |
2631 | |
2632 | mutex_lock(&priv->mutex); | |
2633 | if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) { | |
2634 | /* Cancel any currently running scans... */ | |
2a421b91 | 2635 | if (iwl_scan_cancel_timeout(priv, 100)) |
39aadf8c | 2636 | IWL_WARN(priv, "Could not cancel scan.\n"); |
b481de9c | 2637 | else { |
e1623446 | 2638 | IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = " |
b481de9c ZY |
2639 | "0x%04X\n", filter_flags); |
2640 | priv->staging_rxon.filter_flags = | |
2641 | cpu_to_le32(filter_flags); | |
e0158e61 | 2642 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2643 | } |
2644 | } | |
2645 | mutex_unlock(&priv->mutex); | |
2646 | ||
2647 | return count; | |
2648 | } | |
2649 | ||
2650 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | |
2651 | store_filter_flags); | |
2652 | ||
b481de9c ZY |
2653 | static ssize_t store_power_level(struct device *d, |
2654 | struct device_attribute *attr, | |
2655 | const char *buf, size_t count) | |
2656 | { | |
c79dd5b5 | 2657 | struct iwl_priv *priv = dev_get_drvdata(d); |
298df1f6 | 2658 | int ret; |
9257746f TW |
2659 | unsigned long mode; |
2660 | ||
b481de9c | 2661 | |
b481de9c ZY |
2662 | mutex_lock(&priv->mutex); |
2663 | ||
9257746f | 2664 | ret = strict_strtoul(buf, 10, &mode); |
926f0b2e | 2665 | if (ret) |
9257746f TW |
2666 | goto out; |
2667 | ||
298df1f6 EK |
2668 | ret = iwl_power_set_user_mode(priv, mode); |
2669 | if (ret) { | |
e1623446 | 2670 | IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n"); |
5da4b55f | 2671 | goto out; |
b481de9c | 2672 | } |
298df1f6 | 2673 | ret = count; |
b481de9c ZY |
2674 | |
2675 | out: | |
2676 | mutex_unlock(&priv->mutex); | |
298df1f6 | 2677 | return ret; |
b481de9c ZY |
2678 | } |
2679 | ||
b481de9c ZY |
2680 | static ssize_t show_power_level(struct device *d, |
2681 | struct device_attribute *attr, char *buf) | |
2682 | { | |
c79dd5b5 | 2683 | struct iwl_priv *priv = dev_get_drvdata(d); |
298df1f6 | 2684 | int mode = priv->power_data.user_power_setting; |
5da4b55f | 2685 | int level = priv->power_data.power_mode; |
b481de9c ZY |
2686 | char *p = buf; |
2687 | ||
7af2c460 JB |
2688 | p += sprintf(p, "INDEX:%d\t", level); |
2689 | p += sprintf(p, "USER:%d\n", mode); | |
3ac7f146 | 2690 | return p - buf + 1; |
b481de9c ZY |
2691 | } |
2692 | ||
2693 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | |
2694 | store_power_level); | |
2695 | ||
0b4d0ab4 WYG |
2696 | static ssize_t show_qos(struct device *d, |
2697 | struct device_attribute *attr, char *buf) | |
2698 | { | |
4eaf16bc | 2699 | struct iwl_priv *priv = dev_get_drvdata(d); |
0b4d0ab4 WYG |
2700 | char *p = buf; |
2701 | int q; | |
2702 | ||
2703 | for (q = 0; q < AC_NUM; q++) { | |
2704 | p += sprintf(p, "\tcw_min\tcw_max\taifsn\ttxop\n"); | |
2705 | p += sprintf(p, "AC[%d]\t%u\t%u\t%u\t%u\n", q, | |
2706 | priv->qos_data.def_qos_parm.ac[q].cw_min, | |
2707 | priv->qos_data.def_qos_parm.ac[q].cw_max, | |
2708 | priv->qos_data.def_qos_parm.ac[q].aifsn, | |
2709 | priv->qos_data.def_qos_parm.ac[q].edca_txop); | |
2710 | } | |
2711 | ||
2712 | return p - buf + 1; | |
2713 | } | |
2714 | ||
2715 | static DEVICE_ATTR(qos, S_IRUGO, show_qos, NULL); | |
b481de9c ZY |
2716 | |
2717 | static ssize_t show_statistics(struct device *d, | |
2718 | struct device_attribute *attr, char *buf) | |
2719 | { | |
c79dd5b5 | 2720 | struct iwl_priv *priv = dev_get_drvdata(d); |
8f91aecb | 2721 | u32 size = sizeof(struct iwl_notif_statistics); |
b481de9c | 2722 | u32 len = 0, ofs = 0; |
3ac7f146 | 2723 | u8 *data = (u8 *)&priv->statistics; |
b481de9c ZY |
2724 | int rc = 0; |
2725 | ||
fee1247a | 2726 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
2727 | return -EAGAIN; |
2728 | ||
2729 | mutex_lock(&priv->mutex); | |
49ea8596 | 2730 | rc = iwl_send_statistics_request(priv, 0); |
b481de9c ZY |
2731 | mutex_unlock(&priv->mutex); |
2732 | ||
2733 | if (rc) { | |
2734 | len = sprintf(buf, | |
2735 | "Error sending statistics request: 0x%08X\n", rc); | |
2736 | return len; | |
2737 | } | |
2738 | ||
2739 | while (size && (PAGE_SIZE - len)) { | |
2740 | hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len, | |
2741 | PAGE_SIZE - len, 1); | |
2742 | len = strlen(buf); | |
2743 | if (PAGE_SIZE - len) | |
2744 | buf[len++] = '\n'; | |
2745 | ||
2746 | ofs += 16; | |
2747 | size -= min(size, 16U); | |
2748 | } | |
2749 | ||
2750 | return len; | |
2751 | } | |
2752 | ||
2753 | static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL); | |
2754 | ||
b481de9c | 2755 | |
b481de9c ZY |
2756 | /***************************************************************************** |
2757 | * | |
2758 | * driver setup and teardown | |
2759 | * | |
2760 | *****************************************************************************/ | |
2761 | ||
4e39317d | 2762 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 2763 | { |
d21050c7 | 2764 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
2765 | |
2766 | init_waitqueue_head(&priv->wait_command_queue); | |
2767 | ||
5b9f8cd3 EG |
2768 | INIT_WORK(&priv->up, iwl_bg_up); |
2769 | INIT_WORK(&priv->restart, iwl_bg_restart); | |
2770 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 2771 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 2772 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
4a4a9e81 TW |
2773 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
2774 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 2775 | |
2a421b91 | 2776 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 2777 | |
4e39317d EG |
2778 | if (priv->cfg->ops->lib->setup_deferred_work) |
2779 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
2780 | ||
2781 | init_timer(&priv->statistics_periodic); | |
2782 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 2783 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 2784 | |
ef850d7c MA |
2785 | if (!priv->cfg->use_isr_legacy) |
2786 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
2787 | iwl_irq_tasklet, (unsigned long)priv); | |
2788 | else | |
2789 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
2790 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
2791 | } |
2792 | ||
4e39317d | 2793 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 2794 | { |
4e39317d EG |
2795 | if (priv->cfg->ops->lib->cancel_deferred_work) |
2796 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 2797 | |
3ae6a054 | 2798 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c ZY |
2799 | cancel_delayed_work(&priv->scan_check); |
2800 | cancel_delayed_work(&priv->alive_start); | |
b481de9c | 2801 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 2802 | del_timer_sync(&priv->statistics_periodic); |
b481de9c ZY |
2803 | } |
2804 | ||
5b9f8cd3 | 2805 | static struct attribute *iwl_sysfs_entries[] = { |
b481de9c ZY |
2806 | &dev_attr_flags.attr, |
2807 | &dev_attr_filter_flags.attr, | |
b481de9c | 2808 | &dev_attr_power_level.attr, |
b481de9c | 2809 | &dev_attr_statistics.attr, |
b481de9c | 2810 | &dev_attr_temperature.attr, |
b481de9c | 2811 | &dev_attr_tx_power.attr, |
8cf769c6 EK |
2812 | #ifdef CONFIG_IWLWIFI_DEBUG |
2813 | &dev_attr_debug_level.attr, | |
2814 | #endif | |
bc6f59bc | 2815 | &dev_attr_version.attr, |
0b4d0ab4 | 2816 | &dev_attr_qos.attr, |
b481de9c ZY |
2817 | NULL |
2818 | }; | |
2819 | ||
5b9f8cd3 | 2820 | static struct attribute_group iwl_attribute_group = { |
b481de9c | 2821 | .name = NULL, /* put in device directory */ |
5b9f8cd3 | 2822 | .attrs = iwl_sysfs_entries, |
b481de9c ZY |
2823 | }; |
2824 | ||
5b9f8cd3 EG |
2825 | static struct ieee80211_ops iwl_hw_ops = { |
2826 | .tx = iwl_mac_tx, | |
2827 | .start = iwl_mac_start, | |
2828 | .stop = iwl_mac_stop, | |
2829 | .add_interface = iwl_mac_add_interface, | |
2830 | .remove_interface = iwl_mac_remove_interface, | |
2831 | .config = iwl_mac_config, | |
5b9f8cd3 EG |
2832 | .configure_filter = iwl_configure_filter, |
2833 | .set_key = iwl_mac_set_key, | |
2834 | .update_tkip_key = iwl_mac_update_tkip_key, | |
2835 | .get_stats = iwl_mac_get_stats, | |
2836 | .get_tx_stats = iwl_mac_get_tx_stats, | |
2837 | .conf_tx = iwl_mac_conf_tx, | |
2838 | .reset_tsf = iwl_mac_reset_tsf, | |
2839 | .bss_info_changed = iwl_bss_info_changed, | |
2840 | .ampdu_action = iwl_mac_ampdu_action, | |
cb43dc25 | 2841 | .hw_scan = iwl_mac_hw_scan |
b481de9c ZY |
2842 | }; |
2843 | ||
5b9f8cd3 | 2844 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
2845 | { |
2846 | int err = 0; | |
c79dd5b5 | 2847 | struct iwl_priv *priv; |
b481de9c | 2848 | struct ieee80211_hw *hw; |
82b9a121 | 2849 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 2850 | unsigned long flags; |
6cd0b1cb | 2851 | u16 pci_cmd; |
b481de9c | 2852 | |
316c30d9 AK |
2853 | /************************ |
2854 | * 1. Allocating HW data | |
2855 | ************************/ | |
2856 | ||
6440adb5 CB |
2857 | /* Disabling hardware scan means that mac80211 will perform scans |
2858 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 2859 | if (cfg->mod_params->disable_hw_scan) { |
bf403db8 EK |
2860 | if (cfg->mod_params->debug & IWL_DL_INFO) |
2861 | dev_printk(KERN_DEBUG, &(pdev->dev), | |
2862 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 2863 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
2864 | } |
2865 | ||
5b9f8cd3 | 2866 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 2867 | if (!hw) { |
b481de9c ZY |
2868 | err = -ENOMEM; |
2869 | goto out; | |
2870 | } | |
1d0a082d AK |
2871 | priv = hw->priv; |
2872 | /* At this point both hw and priv are allocated. */ | |
2873 | ||
b481de9c ZY |
2874 | SET_IEEE80211_DEV(hw, &pdev->dev); |
2875 | ||
e1623446 | 2876 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 2877 | priv->cfg = cfg; |
b481de9c | 2878 | priv->pci_dev = pdev; |
40cefda9 | 2879 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 2880 | |
0a6857e7 | 2881 | #ifdef CONFIG_IWLWIFI_DEBUG |
bf403db8 | 2882 | priv->debug_level = priv->cfg->mod_params->debug; |
b481de9c ZY |
2883 | atomic_set(&priv->restrict_refcnt, 0); |
2884 | #endif | |
b481de9c | 2885 | |
316c30d9 AK |
2886 | /************************** |
2887 | * 2. Initializing PCI bus | |
2888 | **************************/ | |
2889 | if (pci_enable_device(pdev)) { | |
2890 | err = -ENODEV; | |
2891 | goto out_ieee80211_free_hw; | |
2892 | } | |
2893 | ||
2894 | pci_set_master(pdev); | |
2895 | ||
093d874c | 2896 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 2897 | if (!err) |
093d874c | 2898 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 2899 | if (err) { |
093d874c | 2900 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2901 | if (!err) |
093d874c | 2902 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 2903 | /* both attempts failed: */ |
316c30d9 | 2904 | if (err) { |
978785a3 | 2905 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 2906 | goto out_pci_disable_device; |
cc2a8ea8 | 2907 | } |
316c30d9 AK |
2908 | } |
2909 | ||
2910 | err = pci_request_regions(pdev, DRV_NAME); | |
2911 | if (err) | |
2912 | goto out_pci_disable_device; | |
2913 | ||
2914 | pci_set_drvdata(pdev, priv); | |
2915 | ||
316c30d9 AK |
2916 | |
2917 | /*********************** | |
2918 | * 3. Read REV register | |
2919 | ***********************/ | |
2920 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
2921 | if (!priv->hw_base) { | |
2922 | err = -ENODEV; | |
2923 | goto out_pci_release_regions; | |
2924 | } | |
2925 | ||
e1623446 | 2926 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 2927 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 2928 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 2929 | |
a8b50a0a MA |
2930 | /* this spin lock will be used in apm_ops.init and EEPROM access |
2931 | * we should init now | |
2932 | */ | |
2933 | spin_lock_init(&priv->reg_lock); | |
b661c819 | 2934 | iwl_hw_detect(priv); |
978785a3 | 2935 | IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n", |
b661c819 | 2936 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 2937 | |
e7b63581 TW |
2938 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
2939 | * PCI Tx retries from interfering with C3 CPU state */ | |
2940 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
2941 | ||
086ed117 MA |
2942 | iwl_prepare_card_hw(priv); |
2943 | if (!priv->hw_ready) { | |
2944 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
2945 | goto out_iounmap; | |
2946 | } | |
2947 | ||
91238714 TW |
2948 | /* amp init */ |
2949 | err = priv->cfg->ops->lib->apm_ops.init(priv); | |
316c30d9 | 2950 | if (err < 0) { |
808ff697 | 2951 | IWL_ERR(priv, "Failed to init APMG\n"); |
316c30d9 AK |
2952 | goto out_iounmap; |
2953 | } | |
91238714 TW |
2954 | /***************** |
2955 | * 4. Read EEPROM | |
2956 | *****************/ | |
316c30d9 AK |
2957 | /* Read the EEPROM */ |
2958 | err = iwl_eeprom_init(priv); | |
2959 | if (err) { | |
15b1687c | 2960 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
2961 | goto out_iounmap; |
2962 | } | |
8614f360 TW |
2963 | err = iwl_eeprom_check_version(priv); |
2964 | if (err) | |
c8f16138 | 2965 | goto out_free_eeprom; |
8614f360 | 2966 | |
02883017 | 2967 | /* extract MAC Address */ |
316c30d9 | 2968 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
e1623446 | 2969 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
316c30d9 AK |
2970 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
2971 | ||
2972 | /************************ | |
2973 | * 5. Setup HW constants | |
2974 | ************************/ | |
da154e30 | 2975 | if (iwl_set_hw_params(priv)) { |
15b1687c | 2976 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 2977 | goto out_free_eeprom; |
316c30d9 AK |
2978 | } |
2979 | ||
2980 | /******************* | |
6ba87956 | 2981 | * 6. Setup priv |
316c30d9 | 2982 | *******************/ |
b481de9c | 2983 | |
6ba87956 | 2984 | err = iwl_init_drv(priv); |
bf85ea4f | 2985 | if (err) |
399f4900 | 2986 | goto out_free_eeprom; |
bf85ea4f | 2987 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 2988 | |
316c30d9 | 2989 | /******************** |
09f9bf79 | 2990 | * 7. Setup services |
316c30d9 | 2991 | ********************/ |
0359facc | 2992 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2993 | iwl_disable_interrupts(priv); |
0359facc | 2994 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 2995 | |
6cd0b1cb HS |
2996 | pci_enable_msi(priv->pci_dev); |
2997 | ||
ef850d7c MA |
2998 | iwl_alloc_isr_ict(priv); |
2999 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, | |
3000 | IRQF_SHARED, DRV_NAME, priv); | |
6cd0b1cb HS |
3001 | if (err) { |
3002 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
3003 | goto out_disable_msi; | |
3004 | } | |
5b9f8cd3 | 3005 | err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group); |
316c30d9 | 3006 | if (err) { |
15b1687c | 3007 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
795cc0ad | 3008 | goto out_free_irq; |
316c30d9 AK |
3009 | } |
3010 | ||
4e39317d | 3011 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3012 | iwl_setup_rx_handlers(priv); |
316c30d9 | 3013 | |
6ba87956 | 3014 | /********************************** |
09f9bf79 | 3015 | * 8. Setup and register mac80211 |
6ba87956 TW |
3016 | **********************************/ |
3017 | ||
6cd0b1cb HS |
3018 | /* enable interrupts if needed: hw bug w/a */ |
3019 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
3020 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
3021 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
3022 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
3023 | } | |
3024 | ||
3025 | iwl_enable_interrupts(priv); | |
3026 | ||
6ba87956 TW |
3027 | err = iwl_setup_mac(priv); |
3028 | if (err) | |
3029 | goto out_remove_sysfs; | |
3030 | ||
3031 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
3032 | if (err) | |
a75fbe8d | 3033 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); |
6ba87956 | 3034 | |
6cd0b1cb HS |
3035 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3036 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3037 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3038 | else | |
3039 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3040 | |
a60e77e5 JB |
3041 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
3042 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 3043 | |
58d0f361 | 3044 | iwl_power_initialize(priv); |
b481de9c ZY |
3045 | return 0; |
3046 | ||
316c30d9 | 3047 | out_remove_sysfs: |
c8f16138 RC |
3048 | destroy_workqueue(priv->workqueue); |
3049 | priv->workqueue = NULL; | |
5b9f8cd3 | 3050 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
795cc0ad HS |
3051 | out_free_irq: |
3052 | free_irq(priv->pci_dev->irq, priv); | |
ef850d7c | 3053 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
3054 | out_disable_msi: |
3055 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 3056 | iwl_uninit_drv(priv); |
073d3f5f TW |
3057 | out_free_eeprom: |
3058 | iwl_eeprom_free(priv); | |
b481de9c ZY |
3059 | out_iounmap: |
3060 | pci_iounmap(pdev, priv->hw_base); | |
3061 | out_pci_release_regions: | |
316c30d9 | 3062 | pci_set_drvdata(pdev, NULL); |
623d563e | 3063 | pci_release_regions(pdev); |
b481de9c ZY |
3064 | out_pci_disable_device: |
3065 | pci_disable_device(pdev); | |
b481de9c ZY |
3066 | out_ieee80211_free_hw: |
3067 | ieee80211_free_hw(priv->hw); | |
3068 | out: | |
3069 | return err; | |
3070 | } | |
3071 | ||
5b9f8cd3 | 3072 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 3073 | { |
c79dd5b5 | 3074 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 3075 | unsigned long flags; |
b481de9c ZY |
3076 | |
3077 | if (!priv) | |
3078 | return; | |
3079 | ||
e1623446 | 3080 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 3081 | |
67249625 | 3082 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 3083 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 3084 | |
5b9f8cd3 EG |
3085 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
3086 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
3087 | * we need to set STATUS_EXIT_PENDING bit. |
3088 | */ | |
3089 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
3090 | if (priv->mac80211_registered) { |
3091 | ieee80211_unregister_hw(priv->hw); | |
3092 | priv->mac80211_registered = 0; | |
0b124c31 | 3093 | } else { |
5b9f8cd3 | 3094 | iwl_down(priv); |
c4f55232 RR |
3095 | } |
3096 | ||
0359facc MA |
3097 | /* make sure we flush any pending irq or |
3098 | * tasklet for the driver | |
3099 | */ | |
3100 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 3101 | iwl_disable_interrupts(priv); |
0359facc MA |
3102 | spin_unlock_irqrestore(&priv->lock, flags); |
3103 | ||
3104 | iwl_synchronize_irq(priv); | |
3105 | ||
5b9f8cd3 | 3106 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
3107 | |
3108 | if (priv->rxq.bd) | |
a55360e4 | 3109 | iwl_rx_queue_free(priv, &priv->rxq); |
1053d35f | 3110 | iwl_hw_txq_ctx_free(priv); |
b481de9c | 3111 | |
c587de0b | 3112 | iwl_clear_stations_table(priv); |
073d3f5f | 3113 | iwl_eeprom_free(priv); |
b481de9c | 3114 | |
b481de9c | 3115 | |
948c171c MA |
3116 | /*netif_stop_queue(dev); */ |
3117 | flush_workqueue(priv->workqueue); | |
3118 | ||
5b9f8cd3 | 3119 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3120 | * priv->workqueue... so we can't take down the workqueue |
3121 | * until now... */ | |
3122 | destroy_workqueue(priv->workqueue); | |
3123 | priv->workqueue = NULL; | |
3124 | ||
6cd0b1cb HS |
3125 | free_irq(priv->pci_dev->irq, priv); |
3126 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
3127 | pci_iounmap(pdev, priv->hw_base); |
3128 | pci_release_regions(pdev); | |
3129 | pci_disable_device(pdev); | |
3130 | pci_set_drvdata(pdev, NULL); | |
3131 | ||
6ba87956 | 3132 | iwl_uninit_drv(priv); |
b481de9c | 3133 | |
ef850d7c MA |
3134 | iwl_free_isr_ict(priv); |
3135 | ||
b481de9c ZY |
3136 | if (priv->ibss_beacon) |
3137 | dev_kfree_skb(priv->ibss_beacon); | |
3138 | ||
3139 | ieee80211_free_hw(priv->hw); | |
3140 | } | |
3141 | ||
b481de9c ZY |
3142 | |
3143 | /***************************************************************************** | |
3144 | * | |
3145 | * driver and module entry point | |
3146 | * | |
3147 | *****************************************************************************/ | |
3148 | ||
fed9017e RR |
3149 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
3150 | static struct pci_device_id iwl_hw_card_ids[] = { | |
4fc22b21 | 3151 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
3152 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
3153 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 3154 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 3155 | #ifdef CONFIG_IWL5000 |
47408639 EK |
3156 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)}, |
3157 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)}, | |
3158 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, | |
3159 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, | |
3160 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, | |
3161 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, | |
5a6a256e | 3162 | {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)}, |
47408639 EK |
3163 | {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)}, |
3164 | {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)}, | |
3165 | {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)}, | |
e96a8495 TW |
3166 | /* 5350 WiFi/WiMax */ |
3167 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, | |
3168 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, | |
3169 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, | |
7100e924 TW |
3170 | /* 5150 Wifi/WiMax */ |
3171 | {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
3172 | {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)}, | |
e1228374 JS |
3173 | /* 6000/6050 Series */ |
3174 | {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)}, | |
3175 | {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)}, | |
3176 | {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)}, | |
3177 | {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)}, | |
542cc793 | 3178 | {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000_2agn_cfg)}, |
e1228374 | 3179 | {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)}, |
542cc793 | 3180 | {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000_2agn_cfg)}, |
e1228374 JS |
3181 | {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)}, |
3182 | {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)}, | |
3183 | {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)}, | |
3184 | {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
3185 | {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)}, | |
3186 | {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)}, | |
77dcb6a9 JS |
3187 | /* 1000 Series WiFi */ |
3188 | {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)}, | |
3189 | {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)}, | |
5a6a256e | 3190 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 3191 | |
fed9017e RR |
3192 | {0} |
3193 | }; | |
3194 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
3195 | ||
3196 | static struct pci_driver iwl_driver = { | |
b481de9c | 3197 | .name = DRV_NAME, |
fed9017e | 3198 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
3199 | .probe = iwl_pci_probe, |
3200 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 3201 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
3202 | .suspend = iwl_pci_suspend, |
3203 | .resume = iwl_pci_resume, | |
b481de9c ZY |
3204 | #endif |
3205 | }; | |
3206 | ||
5b9f8cd3 | 3207 | static int __init iwl_init(void) |
b481de9c ZY |
3208 | { |
3209 | ||
3210 | int ret; | |
3211 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
3212 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 3213 | |
e227ceac | 3214 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 3215 | if (ret) { |
a3139c59 SO |
3216 | printk(KERN_ERR DRV_NAME |
3217 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
3218 | return ret; |
3219 | } | |
3220 | ||
fed9017e | 3221 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 3222 | if (ret) { |
a3139c59 | 3223 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 3224 | goto error_register; |
b481de9c | 3225 | } |
b481de9c ZY |
3226 | |
3227 | return ret; | |
897e1cf2 | 3228 | |
897e1cf2 | 3229 | error_register: |
e227ceac | 3230 | iwlagn_rate_control_unregister(); |
897e1cf2 | 3231 | return ret; |
b481de9c ZY |
3232 | } |
3233 | ||
5b9f8cd3 | 3234 | static void __exit iwl_exit(void) |
b481de9c | 3235 | { |
fed9017e | 3236 | pci_unregister_driver(&iwl_driver); |
e227ceac | 3237 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
3238 | } |
3239 | ||
5b9f8cd3 EG |
3240 | module_exit(iwl_exit); |
3241 | module_init(iwl_init); |