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wl1271: use per-channel max tx power passed by mac80211 when scanning
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
b481de9c
ZY		 30#include <linux/kernel.h>
31#include <linux/module.h>
b481de9c
ZY		 32#include <linux/init.h>
33#include <linux/pci.h>
5a0e3ad6 34#include <linux/slab.h>
b481de9c
ZY		 35#include <linux/dma-mapping.h>
36#include <linux/delay.h>
d43c36dc 37#include <linux/sched.h>
b481de9c
ZY		 38#include <linux/skbuff.h>
39#include <linux/netdevice.h>
40#include <linux/wireless.h>
41#include <linux/firmware.h>
b481de9c
ZY		 42#include <linux/etherdevice.h>
43#include <linux/if_arp.h>
44
b481de9c
ZY		 45#include <net/mac80211.h>
46
47#include <asm/div64.h>
48
a3139c59
SO		 49#define DRV_NAME "iwlagn"
50
6bc913bd 51#include "iwl-eeprom.h"
3e0d4cb1 52#include "iwl-dev.h"
fee1247a 53#include "iwl-core.h"
3395f6e9 54#include "iwl-io.h"
b481de9c 55#include "iwl-helpers.h"
6974e363 56#include "iwl-sta.h"
f0832f13 57#include "iwl-calib.h"
a1175124 58#include "iwl-agn.h"
b481de9c 59
416e1438 60
b481de9c
ZY		 61/******************************************************************************
62 *
63 * module boiler plate
64 *
65 ******************************************************************************/
66
b481de9c
ZY		 67/*
68 * module name, copyright, version, etc.
b481de9c 69 */
d783b061 70#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 71
0a6857e7 72#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 73#define VD "d"
74#else
75#define VD
76#endif
77
81963d68 78#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 79
b481de9c
ZY		 80
81MODULE_DESCRIPTION(DRV_DESCRIPTION);
82MODULE_VERSION(DRV_VERSION);
a7b75207 83MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 84MODULE_LICENSE("GPL");
4fc22b21 85MODULE_ALIAS("iwl4965");
b481de9c 86
b481de9c 87/**
5b9f8cd3 88 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 89 *
01ebd063 90 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 91 * the active_rxon structure is updated with the new data. This
92 * function correctly transitions out of the RXON_ASSOC_MSK state if
93 * a HW tune is required based on the RXON structure changes.
94 */
e0158e61 95int iwl_commit_rxon(struct iwl_priv *priv)
b481de9c
ZY		 96{
97 /* cast away the const for active_rxon in this function */
c1adf9fb 98 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG		 99 int ret;
100 bool new_assoc =
101 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 102
fee1247a 103 if (!iwl_is_alive(priv))
43d59b32 104 return -EBUSY;
b481de9c
ZY		 105
106 /* always get timestamp with Rx frame */
107 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
108
8ccde88a 109 ret = iwl_check_rxon_cmd(priv);
43d59b32 110 if (ret) {
15b1687c 111 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 112 return -EINVAL;
113 }
114
0924e519
WYG		 115 /*
116 * receive commit_rxon request
117 * abort any previous channel switch if still in process
118 */
119 if (priv->switch_rxon.switch_in_progress &&
120 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
121 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
122 le16_to_cpu(priv->switch_rxon.channel));
79d07325 123 iwl_chswitch_done(priv, false);
0924e519
WYG		 124 }
125
b481de9c 126 /* If we don't need to send a full RXON, we can use
5b9f8cd3 127 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 128 * and other flags for the current radio configuration. */
54559703 129 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG		 130 ret = iwl_send_rxon_assoc(priv);
131 if (ret) {
15b1687c 132 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 133 return ret;
b481de9c
ZY		 134 }
135
136 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 137 iwl_print_rx_config_cmd(priv);
b481de9c
ZY		 138 return 0;
139 }
140
b481de9c
ZY		 141 /* If we are currently associated and the new config requires
142 * an RXON_ASSOC and the new config wants the associated mask enabled,
143 * we must clear the associated from the active configuration
144 * before we apply the new config */
43d59b32 145 if (iwl_is_associated(priv) && new_assoc) {
e1623446 146 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 147 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
148
43d59b32 149 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 150 sizeof(struct iwl_rxon_cmd),
b481de9c
ZY		 151 &priv->active_rxon);
152
153 /* If the mask clearing failed then we set
154 * active_rxon back to what it was previously */
43d59b32 155 if (ret) {
b481de9c 156 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 157 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 158 return ret;
b481de9c 159 }
2c810ccd 160 iwl_clear_ucode_stations(priv);
7e246191 161 iwl_restore_stations(priv);
335348b1
JB		 162 ret = iwl_restore_default_wep_keys(priv);
163 if (ret) {
164 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
165 return ret;
166 }
b481de9c
ZY		 167 }
168
e1623446 169 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 170 "* with%s RXON_FILTER_ASSOC_MSK\n"
171 "* channel = %d\n"
e174961c 172 "* bssid = %pM\n",
43d59b32 173 (new_assoc ? "" : "out"),
b481de9c 174 le16_to_cpu(priv->staging_rxon.channel),
e174961c 175 priv->staging_rxon.bssid_addr);
b481de9c 176
90e8e424 177 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG		 178
179 /* Apply the new configuration
7e246191
RC		 180 * RXON unassoc clears the station table in uCode so restoration of
181 * stations is needed after it (the RXON command) completes
43d59b32
EG		 182 */
183 if (!new_assoc) {
184 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 185 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 186 if (ret) {
15b1687c 187 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 188 return ret;
189 }
91dd6c27 190 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
43d59b32 191 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
2c810ccd 192 iwl_clear_ucode_stations(priv);
7e246191 193 iwl_restore_stations(priv);
335348b1
JB		 194 ret = iwl_restore_default_wep_keys(priv);
195 if (ret) {
196 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
197 return ret;
198 }
b481de9c
ZY		 199 }
200
19cc1087 201 priv->start_calib = 0;
9185159d 202 if (new_assoc) {
47eef9bd
WYG		 203 /*
204 * allow CTS-to-self if possible for new association.
205 * this is relevant only for 5000 series and up,
206 * but will not damage 4965
207 */
208 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
209
43d59b32
EG		 210 /* Apply the new configuration
211 * RXON assoc doesn't clear the station table in uCode,
212 */
213 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
214 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
215 if (ret) {
15b1687c 216 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 217 return ret;
218 }
219 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 220 }
a643565e 221 iwl_print_rx_config_cmd(priv);
b481de9c 222
36da7d70
ZY		 223 iwl_init_sensitivity(priv);
224
225 /* If we issue a new RXON command which required a tune then we must
226 * send a new TXPOWER command or we won't be able to Tx any frames */
227 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
228 if (ret) {
15b1687c 229 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 230 return ret;
231 }
232
b481de9c
ZY		 233 return 0;
234}
235
5b9f8cd3 236void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA		 237{
238
45823531
AK		 239 if (priv->cfg->ops->hcmd->set_rxon_chain)
240 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 241 iwlcore_commit_rxon(priv);
5da4b55f
MA		 242}
243
fcab423d 244static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 245{
246 struct list_head *element;
247
e1623446 248 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 249 priv->frames_count);
250
251 while (!list_empty(&priv->free_frames)) {
252 element = priv->free_frames.next;
253 list_del(element);
fcab423d 254 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 255 priv->frames_count--;
256 }
257
258 if (priv->frames_count) {
39aadf8c 259 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 260 priv->frames_count);
261 priv->frames_count = 0;
262 }
263}
264
fcab423d 265static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 266{
fcab423d 267 struct iwl_frame *frame;
b481de9c
ZY		 268 struct list_head *element;
269 if (list_empty(&priv->free_frames)) {
270 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
271 if (!frame) {
15b1687c 272 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 273 return NULL;
274 }
275
276 priv->frames_count++;
277 return frame;
278 }
279
280 element = priv->free_frames.next;
281 list_del(element);
fcab423d 282 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 283}
284
fcab423d 285static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 286{
287 memset(frame, 0, sizeof(*frame));
288 list_add(&frame->list, &priv->free_frames);
289}
290
47ff65c4 291static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 292 struct ieee80211_hdr *hdr,
73ec1cc2 293 int left)
b481de9c 294{
3109ece1 295 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB		 296 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
297 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
ZY		 298 return 0;
299
300 if (priv->ibss_beacon->len > left)
301 return 0;
302
303 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
304
305 return priv->ibss_beacon->len;
306}
307
47ff65c4
DH		 308/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
309static void iwl_set_beacon_tim(struct iwl_priv *priv,
310 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
311 u8 *beacon, u32 frame_size)
312{
313 u16 tim_idx;
314 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
315
316 /*
317 * The index is relative to frame start but we start looking at the
318 * variable-length part of the beacon.
319 */
320 tim_idx = mgmt->u.beacon.variable - beacon;
321
322 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
323 while ((tim_idx < (frame_size - 2)) &&
324 (beacon[tim_idx] != WLAN_EID_TIM))
325 tim_idx += beacon[tim_idx+1] + 2;
326
327 /* If TIM field was found, set variables */
328 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
329 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
330 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
331 } else
332 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
333}
334
5b9f8cd3 335static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 336 struct iwl_frame *frame)
4bf64efd
TW		 337{
338 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 339 u32 frame_size;
340 u32 rate_flags;
341 u32 rate;
342 /*
343 * We have to set up the TX command, the TX Beacon command, and the
344 * beacon contents.
345 */
4bf64efd 346
47ff65c4 347 /* Initialize memory */
4bf64efd
TW		 348 tx_beacon_cmd = &frame->u.beacon;
349 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
350
47ff65c4 351 /* Set up TX beacon contents */
4bf64efd 352 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 353 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 354 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
355 return 0;
4bf64efd 356
47ff65c4 357 /* Set up TX command fields */
4bf64efd 358 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
47ff65c4
DH		 359 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
360 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
361 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
362 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 363
47ff65c4
DH		 364 /* Set up TX beacon command fields */
365 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
366 frame_size);
4bf64efd 367
47ff65c4
DH		 368 /* Set up packet rate and flags */
369 rate = iwl_rate_get_lowest_plcp(priv);
0e1654fa
JB		 370 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
371 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 372 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
373 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
374 rate_flags |= RATE_MCS_CCK_MSK;
375 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
376 rate_flags);
4bf64efd
TW		 377
378 return sizeof(*tx_beacon_cmd) + frame_size;
379}
5b9f8cd3 380static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 381{
fcab423d 382 struct iwl_frame *frame;
b481de9c
ZY		 383 unsigned int frame_size;
384 int rc;
b481de9c 385
fcab423d 386 frame = iwl_get_free_frame(priv);
b481de9c 387 if (!frame) {
15b1687c 388 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 389 "command.\n");
390 return -ENOMEM;
391 }
392
47ff65c4
DH		 393 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
394 if (!frame_size) {
395 IWL_ERR(priv, "Error configuring the beacon command\n");
396 iwl_free_frame(priv, frame);
397 return -EINVAL;
398 }
b481de9c 399
857485c0 400 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 401 &frame->u.cmd[0]);
402
fcab423d 403 iwl_free_frame(priv, frame);
b481de9c
ZY		 404
405 return rc;
406}
407
7aaa1d79
SO		 408static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
409{
410 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
411
412 dma_addr_t addr = get_unaligned_le32(&tb->lo);
413 if (sizeof(dma_addr_t) > sizeof(u32))
414 addr |=
415 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
416
417 return addr;
418}
419
420static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
421{
422 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
423
424 return le16_to_cpu(tb->hi_n_len) >> 4;
425}
426
427static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
428 dma_addr_t addr, u16 len)
429{
430 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
431 u16 hi_n_len = len << 4;
432
433 put_unaligned_le32(addr, &tb->lo);
434 if (sizeof(dma_addr_t) > sizeof(u32))
435 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
436
437 tb->hi_n_len = cpu_to_le16(hi_n_len);
438
439 tfd->num_tbs = idx + 1;
440}
441
442static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
443{
444 return tfd->num_tbs & 0x1f;
445}
446
447/**
448 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
449 * @priv - driver private data
450 * @txq - tx queue
451 *
452 * Does NOT advance any TFD circular buffer read/write indexes
453 * Does NOT free the TFD itself (which is within circular buffer)
454 */
455void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
456{
59606ffa 457 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 458 struct iwl_tfd *tfd;
459 struct pci_dev *dev = priv->pci_dev;
460 int index = txq->q.read_ptr;
461 int i;
462 int num_tbs;
463
464 tfd = &tfd_tmp[index];
465
466 /* Sanity check on number of chunks */
467 num_tbs = iwl_tfd_get_num_tbs(tfd);
468
469 if (num_tbs >= IWL_NUM_OF_TBS) {
470 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
471 /* @todo issue fatal error, it is quite serious situation */
472 return;
473 }
474
475 /* Unmap tx_cmd */
476 if (num_tbs)
477 pci_unmap_single(dev,
2e724443
FT		 478 dma_unmap_addr(&txq->meta[index], mapping),
479 dma_unmap_len(&txq->meta[index], len),
96891cee 480 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 481
482 /* Unmap chunks, if any. */
ff0d91c3 483 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 484 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
485 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
486
ff0d91c3
JB		 487 /* free SKB */
488 if (txq->txb) {
489 struct sk_buff *skb;
6f80240e 490
ff0d91c3 491 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 492
ff0d91c3
JB		 493 /* can be called from irqs-disabled context */
494 if (skb) {
495 dev_kfree_skb_any(skb);
496 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 497 }
498 }
499}
500
501int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
502 struct iwl_tx_queue *txq,
503 dma_addr_t addr, u16 len,
504 u8 reset, u8 pad)
505{
506 struct iwl_queue *q;
59606ffa 507 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 508 u32 num_tbs;
509
510 q = &txq->q;
59606ffa
SO		 511 tfd_tmp = (struct iwl_tfd *)txq->tfds;
512 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 513
514 if (reset)
515 memset(tfd, 0, sizeof(*tfd));
516
517 num_tbs = iwl_tfd_get_num_tbs(tfd);
518
519 /* Each TFD can point to a maximum 20 Tx buffers */
520 if (num_tbs >= IWL_NUM_OF_TBS) {
521 IWL_ERR(priv, "Error can not send more than %d chunks\n",
522 IWL_NUM_OF_TBS);
523 return -EINVAL;
524 }
525
526 BUG_ON(addr & ~DMA_BIT_MASK(36));
527 if (unlikely(addr & ~IWL_TX_DMA_MASK))
528 IWL_ERR(priv, "Unaligned address = %llx\n",
529 (unsigned long long)addr);
530
531 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
532
533 return 0;
534}
535
a8e74e27
SO		 536/*
537 * Tell nic where to find circular buffer of Tx Frame Descriptors for
538 * given Tx queue, and enable the DMA channel used for that queue.
539 *
540 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
541 * channels supported in hardware.
542 */
543int iwl_hw_tx_queue_init(struct iwl_priv *priv,
544 struct iwl_tx_queue *txq)
545{
a8e74e27
SO		 546 int txq_id = txq->q.id;
547
a8e74e27
SO		 548 /* Circular buffer (TFD queue in DRAM) physical base address */
549 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
550 txq->q.dma_addr >> 8);
551
a8e74e27
SO		 552 return 0;
553}
554
b481de9c
ZY		 555/******************************************************************************
556 *
557 * Generic RX handler implementations
558 *
559 ******************************************************************************/
885ba202
TW		 560static void iwl_rx_reply_alive(struct iwl_priv *priv,
561 struct iwl_rx_mem_buffer *rxb)
b481de9c 562{
2f301227 563 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 564 struct iwl_alive_resp *palive;
b481de9c
ZY		 565 struct delayed_work *pwork;
566
567 palive = &pkt->u.alive_frame;
568
e1623446 569 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 570 "0x%01X 0x%01X\n",
571 palive->is_valid, palive->ver_type,
572 palive->ver_subtype);
573
574 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 575 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 576 memcpy(&priv->card_alive_init,
577 &pkt->u.alive_frame,
885ba202 578 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 579 pwork = &priv->init_alive_start;
580 } else {
e1623446 581 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 582 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 583 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 584 pwork = &priv->alive_start;
585 }
586
587 /* We delay the ALIVE response by 5ms to
588 * give the HW RF Kill time to activate... */
589 if (palive->is_valid == UCODE_VALID_OK)
590 queue_delayed_work(priv->workqueue, pwork,
591 msecs_to_jiffies(5));
592 else
39aadf8c 593 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 594}
595
5b9f8cd3 596static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 597{
c79dd5b5
TW		 598 struct iwl_priv *priv =
599 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 600 struct sk_buff *beacon;
601
602 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 603 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY		 604
605 if (!beacon) {
15b1687c 606 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY		 607 return;
608 }
609
610 mutex_lock(&priv->mutex);
611 /* new beacon skb is allocated every time; dispose previous.*/
612 if (priv->ibss_beacon)
613 dev_kfree_skb(priv->ibss_beacon);
614
615 priv->ibss_beacon = beacon;
616 mutex_unlock(&priv->mutex);
617
5b9f8cd3 618 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 619}
620
4e39317d 621/**
5b9f8cd3 622 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 623 *
624 * This callback is provided in order to send a statistics request.
625 *
626 * This timer function is continually reset to execute within
627 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
628 * was received. We need to ensure we receive the statistics in order
629 * to update the temperature used for calibrating the TXPOWER.
630 */
5b9f8cd3 631static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 632{
633 struct iwl_priv *priv = (struct iwl_priv *)data;
634
635 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
636 return;
637
61780ee3
MA		 638 /* dont send host command if rf-kill is on */
639 if (!iwl_is_ready_rf(priv))
640 return;
641
ef8d5529 642 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 643}
644
a9e1cb6a
WYG		 645
646static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
647 u32 start_idx, u32 num_events,
648 u32 mode)
649{
650 u32 i;
651 u32 ptr; /* SRAM byte address of log data */
652 u32 ev, time, data; /* event log data */
653 unsigned long reg_flags;
654
655 if (mode == 0)
656 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
657 else
658 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
659
660 /* Make sure device is powered up for SRAM reads */
661 spin_lock_irqsave(&priv->reg_lock, reg_flags);
662 if (iwl_grab_nic_access(priv)) {
663 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
664 return;
665 }
666
667 /* Set starting address; reads will auto-increment */
668 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
669 rmb();
670
671 /*
672 * "time" is actually "data" for mode 0 (no timestamp).
673 * place event id # at far right for easier visual parsing.
674 */
675 for (i = 0; i < num_events; i++) {
676 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
677 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
678 if (mode == 0) {
679 trace_iwlwifi_dev_ucode_cont_event(priv,
680 0, time, ev);
681 } else {
682 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
683 trace_iwlwifi_dev_ucode_cont_event(priv,
684 time, data, ev);
685 }
686 }
687 /* Allow device to power down */
688 iwl_release_nic_access(priv);
689 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
690}
691
875295f1 692static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 693{
694 u32 capacity; /* event log capacity in # entries */
695 u32 base; /* SRAM byte address of event log header */
696 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
697 u32 num_wraps; /* # times uCode wrapped to top of log */
698 u32 next_entry; /* index of next entry to be written by uCode */
699
700 if (priv->ucode_type == UCODE_INIT)
701 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
702 else
703 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
704 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
705 capacity = iwl_read_targ_mem(priv, base);
706 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
707 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
708 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
709 } else
710 return;
711
712 if (num_wraps == priv->event_log.num_wraps) {
713 iwl_print_cont_event_trace(priv,
714 base, priv->event_log.next_entry,
715 next_entry - priv->event_log.next_entry,
716 mode);
717 priv->event_log.non_wraps_count++;
718 } else {
719 if ((num_wraps - priv->event_log.num_wraps) > 1)
720 priv->event_log.wraps_more_count++;
721 else
722 priv->event_log.wraps_once_count++;
723 trace_iwlwifi_dev_ucode_wrap_event(priv,
724 num_wraps - priv->event_log.num_wraps,
725 next_entry, priv->event_log.next_entry);
726 if (next_entry < priv->event_log.next_entry) {
727 iwl_print_cont_event_trace(priv, base,
728 priv->event_log.next_entry,
729 capacity - priv->event_log.next_entry,
730 mode);
731
732 iwl_print_cont_event_trace(priv, base, 0,
733 next_entry, mode);
734 } else {
735 iwl_print_cont_event_trace(priv, base,
736 next_entry, capacity - next_entry,
737 mode);
738
739 iwl_print_cont_event_trace(priv, base, 0,
740 next_entry, mode);
741 }
742 }
743 priv->event_log.num_wraps = num_wraps;
744 priv->event_log.next_entry = next_entry;
745}
746
747/**
748 * iwl_bg_ucode_trace - Timer callback to log ucode event
749 *
750 * The timer is continually set to execute every
751 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
752 * this function is to perform continuous uCode event logging operation
753 * if enabled
754 */
755static void iwl_bg_ucode_trace(unsigned long data)
756{
757 struct iwl_priv *priv = (struct iwl_priv *)data;
758
759 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
760 return;
761
762 if (priv->event_log.ucode_trace) {
763 iwl_continuous_event_trace(priv);
764 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
765 mod_timer(&priv->ucode_trace,
766 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
767 }
768}
769
5b9f8cd3 770static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 771 struct iwl_rx_mem_buffer *rxb)
b481de9c 772{
0a6857e7 773#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 774 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 775 struct iwl4965_beacon_notif *beacon =
776 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 777 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 778
e1623446 779 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 780 "tsf %d %d rate %d\n",
25a6572c 781 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 782 beacon->beacon_notify_hdr.failure_frame,
783 le32_to_cpu(beacon->ibss_mgr_status),
784 le32_to_cpu(beacon->high_tsf),
785 le32_to_cpu(beacon->low_tsf), rate);
786#endif
787
05c914fe 788 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY		 789 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
790 queue_work(priv->workqueue, &priv->beacon_update);
791}
792
b481de9c
ZY		 793/* Handle notification from uCode that card's power state is changing
794 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 795static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 796 struct iwl_rx_mem_buffer *rxb)
b481de9c 797{
2f301227 798 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 799 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
800 unsigned long status = priv->status;
801
3a41bbd5 802 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 803 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 804 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
805 (flags & CT_CARD_DISABLED) ?
806 "Reached" : "Not reached");
b481de9c
ZY		 807
808 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 809 CT_CARD_DISABLED)) {
b481de9c 810
3395f6e9 811 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 812 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
813
a8b50a0a
MA		 814 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
815 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 816
817 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 818 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 819 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 820 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 821 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 822 }
3a41bbd5 823 if (flags & CT_CARD_DISABLED)
39b73fb1 824 iwl_tt_enter_ct_kill(priv);
b481de9c 825 }
3a41bbd5 826 if (!(flags & CT_CARD_DISABLED))
39b73fb1 827 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 828
829 if (flags & HW_CARD_DISABLED)
830 set_bit(STATUS_RF_KILL_HW, &priv->status);
831 else
832 clear_bit(STATUS_RF_KILL_HW, &priv->status);
833
834
b481de9c 835 if (!(flags & RXON_CARD_DISABLED))
2a421b91 836 iwl_scan_cancel(priv);
b481de9c
ZY		 837
838 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 839 test_bit(STATUS_RF_KILL_HW, &priv->status)))
840 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
841 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 842 else
843 wake_up_interruptible(&priv->wait_command_queue);
844}
845
5b9f8cd3 846int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 847{
e2e3c57b 848 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 849 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW		 850 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
851 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
852 ~APMG_PS_CTRL_MSK_PWR_SRC);
853 } else {
854 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
855 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
856 ~APMG_PS_CTRL_MSK_PWR_SRC);
857 }
858
a8b50a0a 859 return 0;
e2e3c57b
TW		 860}
861
65550636
WYG		 862static void iwl_bg_tx_flush(struct work_struct *work)
863{
864 struct iwl_priv *priv =
865 container_of(work, struct iwl_priv, tx_flush);
866
867 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
868 return;
869
870 /* do nothing if rf-kill is on */
871 if (!iwl_is_ready_rf(priv))
872 return;
873
874 if (priv->cfg->ops->lib->txfifo_flush) {
875 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
876 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
877 }
878}
879
b481de9c 880/**
5b9f8cd3 881 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 882 *
883 * Setup the RX handlers for each of the reply types sent from the uCode
884 * to the host.
885 *
886 * This function chains into the hardware specific files for them to setup
887 * any hardware specific handlers as well.
888 */
653fa4a0 889static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 890{
885ba202 891 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 892 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
893 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 894 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
895 iwl_rx_spectrum_measure_notif;
5b9f8cd3 896 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 897 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 898 iwl_rx_pm_debug_statistics_notif;
899 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 900
9fbab516
BC		 901 /*
902 * The same handler is used for both the REPLY to a discrete
903 * statistics request from the host as well as for the periodic
904 * statistics notifications (after received beacons) from the uCode.
b481de9c 905 */
ef8d5529 906 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 907 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 908
909 iwl_setup_rx_scan_handlers(priv);
910
37a44211 911 /* status change handler */
5b9f8cd3 912 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 913
c1354754
TW		 914 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
915 iwl_rx_missed_beacon_notif;
37a44211 916 /* Rx handlers */
8d801080
WYG		 917 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
918 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 919 /* block ack */
74bcdb33 920 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 921 /* Set up hardware specific Rx handlers */
d4789efe 922 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 923}
924
b481de9c 925/**
a55360e4 926 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 927 *
928 * Uses the priv->rx_handlers callback function array to invoke
929 * the appropriate handlers, including command responses,
930 * frame-received notifications, and other notifications.
931 */
a55360e4 932void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 933{
a55360e4 934 struct iwl_rx_mem_buffer *rxb;
db11d634 935 struct iwl_rx_packet *pkt;
a55360e4 936 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 937 u32 r, i;
938 int reclaim;
939 unsigned long flags;
5c0eef96 940 u8 fill_rx = 0;
d68ab680 941 u32 count = 8;
4752c93c 942 int total_empty;
b481de9c 943
6440adb5
CB		 944 /* uCode's read index (stored in shared DRAM) indicates the last Rx
945 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 946 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 947 i = rxq->read;
948
949 /* Rx interrupt, but nothing sent from uCode */
950 if (i == r)
e1623446 951 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 952
4752c93c 953 /* calculate total frames need to be restock after handling RX */
7300515d 954 total_empty = r - rxq->write_actual;
4752c93c
MA		 955 if (total_empty < 0)
956 total_empty += RX_QUEUE_SIZE;
957
958 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 959 fill_rx = 1;
960
b481de9c 961 while (i != r) {
f4989d9b
JB		 962 int len;
963
b481de9c
ZY		 964 rxb = rxq->queue[i];
965
9fbab516 966 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 967 * then a bug has been introduced in the queue refilling
968 * routines -- catch it here */
969 BUG_ON(rxb == NULL);
970
971 rxq->queue[i] = NULL;
972
2f301227
ZY		 973 pci_unmap_page(priv->pci_dev, rxb->page_dma,
974 PAGE_SIZE << priv->hw_params.rx_page_order,
975 PCI_DMA_FROMDEVICE);
976 pkt = rxb_addr(rxb);
b481de9c 977
f4989d9b
JB		 978 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
979 len += sizeof(u32); /* account for status word */
980 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 981
b481de9c
ZY		 982 /* Reclaim a command buffer only if this packet is a response
983 * to a (driver-originated) command.
984 * If the packet (e.g. Rx frame) originated from uCode,
985 * there is no command buffer to reclaim.
986 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
987 * but apparently a few don't get set; catch them here. */
988 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
989 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 990 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 991 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 992 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 993 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
994 (pkt->hdr.cmd != REPLY_TX);
995
996 /* Based on type of command response or notification,
997 * handle those that need handling via function in
5b9f8cd3 998 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 999 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1000 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 1001 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 1002 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1003 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 1004 } else {
1005 /* No handling needed */
e1623446 1006 IWL_DEBUG_RX(priv,
b481de9c
ZY		 1007 "r %d i %d No handler needed for %s, 0x%02x\n",
1008 r, i, get_cmd_string(pkt->hdr.cmd),
1009 pkt->hdr.cmd);
1010 }
1011
29b1b268
ZY		 1012 /*
1013 * XXX: After here, we should always check rxb->page
1014 * against NULL before touching it or its virtual
1015 * memory (pkt). Because some rx_handler might have
1016 * already taken or freed the pages.
1017 */
1018
b481de9c 1019 if (reclaim) {
2f301227
ZY		 1020 /* Invoke any callbacks, transfer the buffer to caller,
1021 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1022 * as we reclaim the driver command queue */
29b1b268 1023 if (rxb->page)
17b88929 1024 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1025 else
39aadf8c 1026 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1027 }
1028
7300515d
ZY		 1029 /* Reuse the page if possible. For notification packets and
1030 * SKBs that fail to Rx correctly, add them back into the
1031 * rx_free list for reuse later. */
1032 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1033 if (rxb->page != NULL) {
7300515d
ZY		 1034 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1035 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1036 PCI_DMA_FROMDEVICE);
1037 list_add_tail(&rxb->list, &rxq->rx_free);
1038 rxq->free_count++;
1039 } else
1040 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1041
b481de9c 1042 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1043
b481de9c 1044 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1045 /* If there are a lot of unused frames,
1046 * restock the Rx queue so ucode wont assert. */
1047 if (fill_rx) {
1048 count++;
1049 if (count >= 8) {
7300515d 1050 rxq->read = i;
54b81550 1051 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1052 count = 0;
1053 }
1054 }
b481de9c
ZY		 1055 }
1056
1057 /* Backtrack one entry */
7300515d 1058 rxq->read = i;
4752c93c 1059 if (fill_rx)
54b81550 1060 iwlagn_rx_replenish_now(priv);
4752c93c 1061 else
54b81550 1062 iwlagn_rx_queue_restock(priv);
a55360e4 1063}
a55360e4 1064
0359facc
MA		 1065/* call this function to flush any scheduled tasklet */
1066static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1067{
a96a27f9 1068 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1069 synchronize_irq(priv->pci_dev->irq);
1070 tasklet_kill(&priv->irq_tasklet);
1071}
1072
ef850d7c 1073static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1074{
1075 u32 inta, handled = 0;
1076 u32 inta_fh;
1077 unsigned long flags;
c2e61da2 1078 u32 i;
0a6857e7 1079#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1080 u32 inta_mask;
1081#endif
1082
1083 spin_lock_irqsave(&priv->lock, flags);
1084
1085 /* Ack/clear/reset pending uCode interrupts.
1086 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1087 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1088 inta = iwl_read32(priv, CSR_INT);
1089 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1090
1091 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1092 * Any new interrupts that happen after this, either while we're
1093 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1094 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1095 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1096
0a6857e7 1097#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1098 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1099 /* just for debug */
3395f6e9 1100 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1101 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1102 inta, inta_mask, inta_fh);
1103 }
1104#endif
1105
2f301227
ZY		 1106 spin_unlock_irqrestore(&priv->lock, flags);
1107
b481de9c
ZY		 1108 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1109 * atomic, make sure that inta covers all the interrupts that
1110 * we've discovered, even if FH interrupt came in just after
1111 * reading CSR_INT. */
6f83eaa1 1112 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1113 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1114 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1115 inta |= CSR_INT_BIT_FH_TX;
1116
1117 /* Now service all interrupt bits discovered above. */
1118 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1119 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1120
1121 /* Tell the device to stop sending interrupts */
5b9f8cd3 1122 iwl_disable_interrupts(priv);
b481de9c 1123
a83b9141 1124 priv->isr_stats.hw++;
5b9f8cd3 1125 iwl_irq_handle_error(priv);
b481de9c
ZY		 1126
1127 handled |= CSR_INT_BIT_HW_ERR;
1128
b481de9c
ZY		 1129 return;
1130 }
1131
0a6857e7 1132#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1133 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1134 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1135 if (inta & CSR_INT_BIT_SCD) {
e1623446 1136 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1137 "the frame/frames.\n");
a83b9141
WYG		 1138 priv->isr_stats.sch++;
1139 }
b481de9c
ZY		 1140
1141 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1142 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1143 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1144 priv->isr_stats.alive++;
1145 }
b481de9c
ZY		 1146 }
1147#endif
1148 /* Safely ignore these bits for debug checks below */
25c03d8e 1149 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1150
9fbab516 1151 /* HW RF KILL switch toggled */
b481de9c
ZY		 1152 if (inta & CSR_INT_BIT_RF_KILL) {
1153 int hw_rf_kill = 0;
3395f6e9 1154 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1155 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1156 hw_rf_kill = 1;
1157
4c423a2b 1158 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1159 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1160
a83b9141
WYG		 1161 priv->isr_stats.rfkill++;
1162
a9efa652 1163 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1164 * the driver allows loading the ucode even if the radio
1165 * is killed. Hence update the killswitch state here. The
1166 * rfkill handler will care about restarting if needed.
a9efa652 1167 */
6cd0b1cb
HS		 1168 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1169 if (hw_rf_kill)
1170 set_bit(STATUS_RF_KILL_HW, &priv->status);
1171 else
1172 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1173 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1174 }
b481de9c
ZY		 1175
1176 handled |= CSR_INT_BIT_RF_KILL;
1177 }
1178
9fbab516 1179 /* Chip got too hot and stopped itself */
b481de9c 1180 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1181 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1182 priv->isr_stats.ctkill++;
b481de9c
ZY		 1183 handled |= CSR_INT_BIT_CT_KILL;
1184 }
1185
1186 /* Error detected by uCode */
1187 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1188 IWL_ERR(priv, "Microcode SW error detected. "
1189 " Restarting 0x%X.\n", inta);
a83b9141
WYG		 1190 priv->isr_stats.sw++;
1191 priv->isr_stats.sw_err = inta;
5b9f8cd3 1192 iwl_irq_handle_error(priv);
b481de9c
ZY		 1193 handled |= CSR_INT_BIT_SW_ERR;
1194 }
1195
c2e61da2
BC		 1196 /*
1197 * uCode wakes up after power-down sleep.
1198 * Tell device about any new tx or host commands enqueued,
1199 * and about any Rx buffers made available while asleep.
1200 */
b481de9c 1201 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1202 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1203 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1204 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1205 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1206 priv->isr_stats.wakeup++;
b481de9c
ZY		 1207 handled |= CSR_INT_BIT_WAKEUP;
1208 }
1209
1210 /* All uCode command responses, including Tx command responses,
1211 * Rx "responses" (frame-received notification), and other
1212 * notifications from uCode come through here*/
1213 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1214 iwl_rx_handle(priv);
a83b9141 1215 priv->isr_stats.rx++;
b481de9c
ZY		 1216 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1217 }
1218
c72cd19f 1219 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1220 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1221 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1222 priv->isr_stats.tx++;
b481de9c 1223 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1224 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1225 priv->ucode_write_complete = 1;
1226 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1227 }
1228
a83b9141 1229 if (inta & ~handled) {
15b1687c 1230 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1231 priv->isr_stats.unhandled++;
1232 }
b481de9c 1233
40cefda9 1234 if (inta & ~(priv->inta_mask)) {
39aadf8c 1235 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1236 inta & ~priv->inta_mask);
39aadf8c 1237 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1238 }
1239
1240 /* Re-enable all interrupts */
0359facc
MA		 1241 /* only Re-enable if diabled by irq */
1242 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1243 iwl_enable_interrupts(priv);
b481de9c 1244
0a6857e7 1245#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1246 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1247 inta = iwl_read32(priv, CSR_INT);
1248 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1249 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1250 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1251 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1252 }
1253#endif
b481de9c
ZY		 1254}
1255
ef850d7c
MA		 1256/* tasklet for iwlagn interrupt */
1257static void iwl_irq_tasklet(struct iwl_priv *priv)
1258{
1259 u32 inta = 0;
1260 u32 handled = 0;
1261 unsigned long flags;
8756990f 1262 u32 i;
ef850d7c
MA		 1263#ifdef CONFIG_IWLWIFI_DEBUG
1264 u32 inta_mask;
1265#endif
1266
1267 spin_lock_irqsave(&priv->lock, flags);
1268
1269 /* Ack/clear/reset pending uCode interrupts.
1270 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1271 */
48a6be6a
SZ		 1272 /* There is a hardware bug in the interrupt mask function that some
1273 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1274 * they are disabled in the CSR_INT_MASK register. Furthermore the
1275 * ICT interrupt handling mechanism has another bug that might cause
1276 * these unmasked interrupts fail to be detected. We workaround the
1277 * hardware bugs here by ACKing all the possible interrupts so that
1278 * interrupt coalescing can still be achieved.
1279 */
4a35ecf8 1280 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1281
a4c8b2a6 1282 inta = priv->_agn.inta;
ef850d7c
MA		 1283
1284#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1285 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1286 /* just for debug */
1287 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1288 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1289 inta, inta_mask);
1290 }
1291#endif
2f301227
ZY		 1292
1293 spin_unlock_irqrestore(&priv->lock, flags);
1294
a4c8b2a6
JB		 1295 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1296 priv->_agn.inta = 0;
ef850d7c
MA		 1297
1298 /* Now service all interrupt bits discovered above. */
1299 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1300 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1301
1302 /* Tell the device to stop sending interrupts */
1303 iwl_disable_interrupts(priv);
1304
1305 priv->isr_stats.hw++;
1306 iwl_irq_handle_error(priv);
1307
1308 handled |= CSR_INT_BIT_HW_ERR;
1309
ef850d7c
MA		 1310 return;
1311 }
1312
1313#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1314 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1315 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1316 if (inta & CSR_INT_BIT_SCD) {
1317 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1318 "the frame/frames.\n");
1319 priv->isr_stats.sch++;
1320 }
1321
1322 /* Alive notification via Rx interrupt will do the real work */
1323 if (inta & CSR_INT_BIT_ALIVE) {
1324 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1325 priv->isr_stats.alive++;
1326 }
1327 }
1328#endif
1329 /* Safely ignore these bits for debug checks below */
1330 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1331
1332 /* HW RF KILL switch toggled */
1333 if (inta & CSR_INT_BIT_RF_KILL) {
1334 int hw_rf_kill = 0;
1335 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1336 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1337 hw_rf_kill = 1;
1338
4c423a2b 1339 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1340 hw_rf_kill ? "disable radio" : "enable radio");
1341
1342 priv->isr_stats.rfkill++;
1343
1344 /* driver only loads ucode once setting the interface up.
1345 * the driver allows loading the ucode even if the radio
1346 * is killed. Hence update the killswitch state here. The
1347 * rfkill handler will care about restarting if needed.
1348 */
1349 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1350 if (hw_rf_kill)
1351 set_bit(STATUS_RF_KILL_HW, &priv->status);
1352 else
1353 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1354 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1355 }
1356
1357 handled |= CSR_INT_BIT_RF_KILL;
1358 }
1359
1360 /* Chip got too hot and stopped itself */
1361 if (inta & CSR_INT_BIT_CT_KILL) {
1362 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1363 priv->isr_stats.ctkill++;
1364 handled |= CSR_INT_BIT_CT_KILL;
1365 }
1366
1367 /* Error detected by uCode */
1368 if (inta & CSR_INT_BIT_SW_ERR) {
1369 IWL_ERR(priv, "Microcode SW error detected. "
1370 " Restarting 0x%X.\n", inta);
1371 priv->isr_stats.sw++;
1372 priv->isr_stats.sw_err = inta;
1373 iwl_irq_handle_error(priv);
1374 handled |= CSR_INT_BIT_SW_ERR;
1375 }
1376
1377 /* uCode wakes up after power-down sleep */
1378 if (inta & CSR_INT_BIT_WAKEUP) {
1379 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1380 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1381 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1382 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1383
1384 priv->isr_stats.wakeup++;
1385
1386 handled |= CSR_INT_BIT_WAKEUP;
1387 }
1388
1389 /* All uCode command responses, including Tx command responses,
1390 * Rx "responses" (frame-received notification), and other
1391 * notifications from uCode come through here*/
40cefda9
MA		 1392 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1393 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1394 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1395 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1396 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1397 iwl_write32(priv, CSR_FH_INT_STATUS,
1398 CSR49_FH_INT_RX_MASK);
1399 }
1400 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1401 handled |= CSR_INT_BIT_RX_PERIODIC;
1402 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1403 }
1404 /* Sending RX interrupt require many steps to be done in the
1405 * the device:
1406 * 1- write interrupt to current index in ICT table.
1407 * 2- dma RX frame.
1408 * 3- update RX shared data to indicate last write index.
1409 * 4- send interrupt.
1410 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1411 * but the shared data changes does not reflect this;
1412 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1413 */
74ba67ed
BC		 1414
1415 /* Disable periodic interrupt; we use it as just a one-shot. */
1416 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1417 CSR_INT_PERIODIC_DIS);
ef850d7c 1418 iwl_rx_handle(priv);
74ba67ed
BC		 1419
1420 /*
1421 * Enable periodic interrupt in 8 msec only if we received
1422 * real RX interrupt (instead of just periodic int), to catch
1423 * any dangling Rx interrupt. If it was just the periodic
1424 * interrupt, there was no dangling Rx activity, and no need
1425 * to extend the periodic interrupt; one-shot is enough.
1426 */
40cefda9 1427 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1428 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1429 CSR_INT_PERIODIC_ENA);
1430
ef850d7c 1431 priv->isr_stats.rx++;
ef850d7c
MA		 1432 }
1433
c72cd19f 1434 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1435 if (inta & CSR_INT_BIT_FH_TX) {
1436 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1437 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1438 priv->isr_stats.tx++;
1439 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1440 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1441 priv->ucode_write_complete = 1;
1442 wake_up_interruptible(&priv->wait_command_queue);
1443 }
1444
1445 if (inta & ~handled) {
1446 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1447 priv->isr_stats.unhandled++;
1448 }
1449
40cefda9 1450 if (inta & ~(priv->inta_mask)) {
ef850d7c 1451 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1452 inta & ~priv->inta_mask);
ef850d7c
MA		 1453 }
1454
ef850d7c
MA		 1455 /* Re-enable all interrupts */
1456 /* only Re-enable if diabled by irq */
1457 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1458 iwl_enable_interrupts(priv);
ef850d7c
MA		 1459}
1460
872c8ddc
WYG		 1461/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1462#define ACK_CNT_RATIO (50)
1463#define BA_TIMEOUT_CNT (5)
1464#define BA_TIMEOUT_MAX (16)
1465
1466/**
1467 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1468 *
1469 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1470 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1471 * operation state.
1472 */
1473bool iwl_good_ack_health(struct iwl_priv *priv,
1474 struct iwl_rx_packet *pkt)
1475{
1476 bool rc = true;
1477 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1478 int ba_timeout_delta;
1479
1480 actual_ack_cnt_delta =
1481 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
f3aebeee 1482 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1483 expected_ack_cnt_delta =
1484 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
f3aebeee 1485 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1486 ba_timeout_delta =
1487 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
f3aebeee 1488 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1489 if ((priv->_agn.agg_tids_count > 0) &&
1490 (expected_ack_cnt_delta > 0) &&
1491 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1492 < ACK_CNT_RATIO) &&
1493 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1494 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1495 " expected_ack_cnt = %d\n",
1496 actual_ack_cnt_delta, expected_ack_cnt_delta);
1497
d73e4923
JB		 1498#ifdef CONFIG_IWLWIFI_DEBUGFS
1499 /*
1500 * This is ifdef'ed on DEBUGFS because otherwise the
1501 * statistics aren't available. If DEBUGFS is set but
1502 * DEBUG is not, these will just compile out.
1503 */
872c8ddc 1504 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
f3aebeee 1505 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1506 IWL_DEBUG_RADIO(priv,
1507 "ack_or_ba_timeout_collision delta = %d\n",
f3aebeee 1508 priv->_agn.delta_statistics.tx.
872c8ddc
WYG		 1509 ack_or_ba_timeout_collision);
1510#endif
1511 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1512 ba_timeout_delta);
1513 if (!actual_ack_cnt_delta &&
1514 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1515 rc = false;
1516 }
1517 return rc;
1518}
1519
a83b9141 1520
7d47618a
EG		 1521/*****************************************************************************
1522 *
1523 * sysfs attributes
1524 *
1525 *****************************************************************************/
1526
1527#ifdef CONFIG_IWLWIFI_DEBUG
1528
1529/*
1530 * The following adds a new attribute to the sysfs representation
1531 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1532 * used for controlling the debug level.
1533 *
1534 * See the level definitions in iwl for details.
1535 *
1536 * The debug_level being managed using sysfs below is a per device debug
1537 * level that is used instead of the global debug level if it (the per
1538 * device debug level) is set.
1539 */
1540static ssize_t show_debug_level(struct device *d,
1541 struct device_attribute *attr, char *buf)
1542{
1543 struct iwl_priv *priv = dev_get_drvdata(d);
1544 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1545}
1546static ssize_t store_debug_level(struct device *d,
1547 struct device_attribute *attr,
1548 const char *buf, size_t count)
1549{
1550 struct iwl_priv *priv = dev_get_drvdata(d);
1551 unsigned long val;
1552 int ret;
1553
1554 ret = strict_strtoul(buf, 0, &val);
1555 if (ret)
1556 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1557 else {
1558 priv->debug_level = val;
1559 if (iwl_alloc_traffic_mem(priv))
1560 IWL_ERR(priv,
1561 "Not enough memory to generate traffic log\n");
1562 }
1563 return strnlen(buf, count);
1564}
1565
1566static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1567 show_debug_level, store_debug_level);
1568
1569
1570#endif /* CONFIG_IWLWIFI_DEBUG */
1571
1572
1573static ssize_t show_temperature(struct device *d,
1574 struct device_attribute *attr, char *buf)
1575{
1576 struct iwl_priv *priv = dev_get_drvdata(d);
1577
1578 if (!iwl_is_alive(priv))
1579 return -EAGAIN;
1580
1581 return sprintf(buf, "%d\n", priv->temperature);
1582}
1583
1584static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1585
1586static ssize_t show_tx_power(struct device *d,
1587 struct device_attribute *attr, char *buf)
1588{
1589 struct iwl_priv *priv = dev_get_drvdata(d);
1590
1591 if (!iwl_is_ready_rf(priv))
1592 return sprintf(buf, "off\n");
1593 else
1594 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1595}
1596
1597static ssize_t store_tx_power(struct device *d,
1598 struct device_attribute *attr,
1599 const char *buf, size_t count)
1600{
1601 struct iwl_priv *priv = dev_get_drvdata(d);
1602 unsigned long val;
1603 int ret;
1604
1605 ret = strict_strtoul(buf, 10, &val);
1606 if (ret)
1607 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1608 else {
1609 ret = iwl_set_tx_power(priv, val, false);
1610 if (ret)
1611 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1612 ret);
1613 else
1614 ret = count;
1615 }
1616 return ret;
1617}
1618
1619static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1620
1621static ssize_t show_rts_ht_protection(struct device *d,
1622 struct device_attribute *attr, char *buf)
1623{
1624 struct iwl_priv *priv = dev_get_drvdata(d);
1625
1626 return sprintf(buf, "%s\n",
1627 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
1628}
1629
1630static ssize_t store_rts_ht_protection(struct device *d,
1631 struct device_attribute *attr,
1632 const char *buf, size_t count)
1633{
1634 struct iwl_priv *priv = dev_get_drvdata(d);
1635 unsigned long val;
1636 int ret;
1637
1638 ret = strict_strtoul(buf, 10, &val);
1639 if (ret)
1640 IWL_INFO(priv, "Input is not in decimal form.\n");
1641 else {
1642 if (!iwl_is_associated(priv))
1643 priv->cfg->use_rts_for_ht = val ? true : false;
1644 else
1645 IWL_ERR(priv, "Sta associated with AP - "
1646 "Change protection mechanism is not allowed\n");
1647 ret = count;
1648 }
1649 return ret;
1650}
1651
1652static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
1653 show_rts_ht_protection, store_rts_ht_protection);
1654
1655
1656static struct attribute *iwl_sysfs_entries[] = {
1657 &dev_attr_temperature.attr,
1658 &dev_attr_tx_power.attr,
1659 &dev_attr_rts_ht_protection.attr,
1660#ifdef CONFIG_IWLWIFI_DEBUG
1661 &dev_attr_debug_level.attr,
1662#endif
1663 NULL
1664};
1665
1666static struct attribute_group iwl_attribute_group = {
1667 .name = NULL, /* put in device directory */
1668 .attrs = iwl_sysfs_entries,
1669};
1670
b481de9c
ZY		 1671/******************************************************************************
1672 *
1673 * uCode download functions
1674 *
1675 ******************************************************************************/
1676
5b9f8cd3 1677static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1678{
98c92211
TW		 1679 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1680 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1681 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1682 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1683 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1684 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1685}
1686
5b9f8cd3 1687static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1688{
1689 /* Remove all resets to allow NIC to operate */
1690 iwl_write32(priv, CSR_RESET, 0);
1691}
1692
dd7a2509
JB		 1693struct iwlagn_ucode_capabilities {
1694 u32 max_probe_length;
1695};
edcdf8b2 1696
b08dfd04 1697static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1698static int iwl_mac_setup_register(struct iwl_priv *priv,
1699 struct iwlagn_ucode_capabilities *capa);
b08dfd04
JB		 1700
1701static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1702{
1703 const char *name_pre = priv->cfg->fw_name_pre;
1704
1705 if (first)
1706 priv->fw_index = priv->cfg->ucode_api_max;
1707 else
1708 priv->fw_index--;
1709
1710 if (priv->fw_index < priv->cfg->ucode_api_min) {
1711 IWL_ERR(priv, "no suitable firmware found!\n");
1712 return -ENOENT;
1713 }
1714
1715 sprintf(priv->firmware_name, "%s%d%s",
1716 name_pre, priv->fw_index, ".ucode");
1717
1718 IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
1719 priv->firmware_name);
1720
1721 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1722 &priv->pci_dev->dev, GFP_KERNEL, priv,
1723 iwl_ucode_callback);
1724}
1725
0e9a44dc
JB		 1726struct iwlagn_firmware_pieces {
1727 const void *inst, *data, *init, *init_data, *boot;
1728 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1729
1730 u32 build;
b2e640d4
JB		 1731
1732 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1733 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1734};
1735
1736static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1737 const struct firmware *ucode_raw,
1738 struct iwlagn_firmware_pieces *pieces)
1739{
1740 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1741 u32 api_ver, hdr_size;
1742 const u8 *src;
1743
1744 priv->ucode_ver = le32_to_cpu(ucode->ver);
1745 api_ver = IWL_UCODE_API(priv->ucode_ver);
1746
1747 switch (api_ver) {
1748 default:
1749 /*
1750 * 4965 doesn't revision the firmware file format
1751 * along with the API version, it always uses v1
1752 * file format.
1753 */
1754 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1755 CSR_HW_REV_TYPE_4965) {
1756 hdr_size = 28;
1757 if (ucode_raw->size < hdr_size) {
1758 IWL_ERR(priv, "File size too small!\n");
1759 return -EINVAL;
1760 }
1761 pieces->build = le32_to_cpu(ucode->u.v2.build);
1762 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1763 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1764 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1765 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1766 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1767 src = ucode->u.v2.data;
1768 break;
1769 }
1770 /* fall through for 4965 */
1771 case 0:
1772 case 1:
1773 case 2:
1774 hdr_size = 24;
1775 if (ucode_raw->size < hdr_size) {
1776 IWL_ERR(priv, "File size too small!\n");
1777 return -EINVAL;
1778 }
1779 pieces->build = 0;
1780 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1781 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1782 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1783 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1784 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1785 src = ucode->u.v1.data;
1786 break;
1787 }
1788
1789 /* Verify size of file vs. image size info in file's header */
1790 if (ucode_raw->size != hdr_size + pieces->inst_size +
1791 pieces->data_size + pieces->init_size +
1792 pieces->init_data_size + pieces->boot_size) {
1793
1794 IWL_ERR(priv,
1795 "uCode file size %d does not match expected size\n",
1796 (int)ucode_raw->size);
1797 return -EINVAL;
1798 }
1799
1800 pieces->inst = src;
1801 src += pieces->inst_size;
1802 pieces->data = src;
1803 src += pieces->data_size;
1804 pieces->init = src;
1805 src += pieces->init_size;
1806 pieces->init_data = src;
1807 src += pieces->init_data_size;
1808 pieces->boot = src;
1809 src += pieces->boot_size;
1810
1811 return 0;
1812}
1813
dd7a2509
JB		 1814static int iwlagn_wanted_ucode_alternative = 1;
1815
1816static int iwlagn_load_firmware(struct iwl_priv *priv,
1817 const struct firmware *ucode_raw,
1818 struct iwlagn_firmware_pieces *pieces,
1819 struct iwlagn_ucode_capabilities *capa)
1820{
1821 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1822 struct iwl_ucode_tlv *tlv;
1823 size_t len = ucode_raw->size;
1824 const u8 *data;
1825 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1826 u64 alternatives;
ad8d8333
WYG		 1827 u32 tlv_len;
1828 enum iwl_ucode_tlv_type tlv_type;
1829 const u8 *tlv_data;
1830 int ret = 0;
dd7a2509 1831
ad8d8333
WYG		 1832 if (len < sizeof(*ucode)) {
1833 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1834 return -EINVAL;
ad8d8333 1835 }
dd7a2509 1836
ad8d8333
WYG		 1837 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1838 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1839 le32_to_cpu(ucode->magic));
dd7a2509 1840 return -EINVAL;
ad8d8333 1841 }
dd7a2509
JB		 1842
1843 /*
1844 * Check which alternatives are present, and "downgrade"
1845 * when the chosen alternative is not present, warning
1846 * the user when that happens. Some files may not have
1847 * any alternatives, so don't warn in that case.
1848 */
1849 alternatives = le64_to_cpu(ucode->alternatives);
1850 tmp = wanted_alternative;
1851 if (wanted_alternative > 63)
1852 wanted_alternative = 63;
1853 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1854 wanted_alternative--;
1855 if (wanted_alternative && wanted_alternative != tmp)
1856 IWL_WARN(priv,
1857 "uCode alternative %d not available, choosing %d\n",
1858 tmp, wanted_alternative);
1859
1860 priv->ucode_ver = le32_to_cpu(ucode->ver);
1861 pieces->build = le32_to_cpu(ucode->build);
1862 data = ucode->data;
1863
1864 len -= sizeof(*ucode);
1865
ad8d8333 1866 while (len >= sizeof(*tlv) && !ret) {
dd7a2509 1867 u16 tlv_alt;
ad8d8333 1868 u32 fixed_tlv_size = 4;
dd7a2509
JB		 1869
1870 len -= sizeof(*tlv);
1871 tlv = (void *)data;
1872
1873 tlv_len = le32_to_cpu(tlv->length);
1874 tlv_type = le16_to_cpu(tlv->type);
1875 tlv_alt = le16_to_cpu(tlv->alternative);
1876 tlv_data = tlv->data;
1877
ad8d8333
WYG		 1878 if (len < tlv_len) {
1879 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1880 len, tlv_len);
dd7a2509 1881 return -EINVAL;
ad8d8333 1882 }
dd7a2509
JB		 1883 len -= ALIGN(tlv_len, 4);
1884 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1885
1886 /*
1887 * Alternative 0 is always valid.
1888 *
1889 * Skip alternative TLVs that are not selected.
1890 */
1891 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1892 continue;
1893
1894 switch (tlv_type) {
1895 case IWL_UCODE_TLV_INST:
1896 pieces->inst = tlv_data;
1897 pieces->inst_size = tlv_len;
1898 break;
1899 case IWL_UCODE_TLV_DATA:
1900 pieces->data = tlv_data;
1901 pieces->data_size = tlv_len;
1902 break;
1903 case IWL_UCODE_TLV_INIT:
1904 pieces->init = tlv_data;
1905 pieces->init_size = tlv_len;
1906 break;
1907 case IWL_UCODE_TLV_INIT_DATA:
1908 pieces->init_data = tlv_data;
1909 pieces->init_data_size = tlv_len;
1910 break;
1911 case IWL_UCODE_TLV_BOOT:
1912 pieces->boot = tlv_data;
1913 pieces->boot_size = tlv_len;
1914 break;
1915 case IWL_UCODE_TLV_PROBE_MAX_LEN:
ad8d8333
WYG		 1916 if (tlv_len != fixed_tlv_size)
1917 ret = -EINVAL;
1918 else
1919 capa->max_probe_length =
1920 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1921 break;
b2e640d4 1922 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
ad8d8333
WYG		 1923 if (tlv_len != fixed_tlv_size)
1924 ret = -EINVAL;
1925 else
1926 pieces->init_evtlog_ptr =
1927 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1928 break;
1929 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
ad8d8333
WYG		 1930 if (tlv_len != fixed_tlv_size)
1931 ret = -EINVAL;
1932 else
1933 pieces->init_evtlog_size =
1934 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1935 break;
1936 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
ad8d8333
WYG		 1937 if (tlv_len != fixed_tlv_size)
1938 ret = -EINVAL;
1939 else
1940 pieces->init_errlog_ptr =
1941 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1942 break;
1943 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
ad8d8333
WYG		 1944 if (tlv_len != fixed_tlv_size)
1945 ret = -EINVAL;
1946 else
1947 pieces->inst_evtlog_ptr =
1948 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1949 break;
1950 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
ad8d8333
WYG		 1951 if (tlv_len != fixed_tlv_size)
1952 ret = -EINVAL;
1953 else
1954 pieces->inst_evtlog_size =
1955 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1956 break;
1957 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
ad8d8333
WYG		 1958 if (tlv_len != fixed_tlv_size)
1959 ret = -EINVAL;
1960 else
1961 pieces->inst_errlog_ptr =
1962 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 1963 break;
c8312fac
WYG		 1964 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1965 if (tlv_len)
1966 ret = -EINVAL;
1967 else
1968 priv->enhance_sensitivity_table = true;
1969 break;
dd7a2509 1970 default:
ad8d8333 1971 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 1972 break;
1973 }
1974 }
1975
ad8d8333
WYG		 1976 if (len) {
1977 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1978 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1979 ret = -EINVAL;
1980 } else if (ret) {
1981 IWL_ERR(priv, "TLV %d has invalid size: %u\n",
1982 tlv_type, tlv_len);
1983 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)tlv_data, tlv_len);
1984 }
dd7a2509 1985
ad8d8333 1986 return ret;
dd7a2509
JB		 1987}
1988
b481de9c 1989/**
b08dfd04 1990 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1991 *
b08dfd04
JB		 1992 * If loaded successfully, copies the firmware into buffers
1993 * for the card to fetch (via DMA).
b481de9c 1994 */
b08dfd04 1995static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1996{
b08dfd04 1997 struct iwl_priv *priv = context;
cc0f555d 1998 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 1999 int err;
2000 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 2001 const unsigned int api_max = priv->cfg->ucode_api_max;
2002 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 2003 u32 api_ver;
3e4de761 2004 char buildstr[25];
0e9a44dc 2005 u32 build;
dd7a2509
JB		 2006 struct iwlagn_ucode_capabilities ucode_capa = {
2007 .max_probe_length = 200,
2008 };
0e9a44dc
JB		 2009
2010 memset(&pieces, 0, sizeof(pieces));
b481de9c 2011
b08dfd04
JB		 2012 if (!ucode_raw) {
2013 IWL_ERR(priv, "request for firmware file '%s' failed.\n",
2014 priv->firmware_name);
2015 goto try_again;
b481de9c
ZY		 2016 }
2017
b08dfd04
JB		 2018 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2019 priv->firmware_name, ucode_raw->size);
b481de9c 2020
22adba2a
JB		 2021 /* Make sure that we got at least the API version number */
2022 if (ucode_raw->size < 4) {
15b1687c 2023 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 2024 goto try_again;
b481de9c
ZY		 2025 }
2026
2027 /* Data from ucode file: header followed by uCode images */
cc0f555d 2028 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2029
0e9a44dc
JB		 2030 if (ucode->ver)
2031 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2032 else
dd7a2509
JB		 2033 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2034 &ucode_capa);
22adba2a 2035
0e9a44dc
JB		 2036 if (err)
2037 goto try_again;
b481de9c 2038
a0987a8d 2039 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 2040 build = pieces.build;
a0987a8d 2041
0e9a44dc
JB		 2042 /*
2043 * api_ver should match the api version forming part of the
2044 * firmware filename ... but we don't check for that and only rely
2045 * on the API version read from firmware header from here on forward
2046 */
a0987a8d 2047 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2048 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 2049 "Driver supports v%u, firmware is v%u.\n",
2050 api_max, api_ver);
b08dfd04 2051 goto try_again;
a0987a8d 2052 }
b08dfd04 2053
a0987a8d 2054 if (api_ver != api_max)
978785a3 2055 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 2056 "got v%u. New firmware can be obtained "
2057 "from http://www.intellinuxwireless.org.\n",
2058 api_max, api_ver);
2059
3e4de761
JB		 2060 if (build)
2061 sprintf(buildstr, " build %u", build);
2062 else
2063 buildstr[0] = '\0';
2064
2065 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2066 IWL_UCODE_MAJOR(priv->ucode_ver),
2067 IWL_UCODE_MINOR(priv->ucode_ver),
2068 IWL_UCODE_API(priv->ucode_ver),
2069 IWL_UCODE_SERIAL(priv->ucode_ver),
2070 buildstr);
a0987a8d 2071
5ebeb5a6
RC		 2072 snprintf(priv->hw->wiphy->fw_version,
2073 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2074 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2075 IWL_UCODE_MAJOR(priv->ucode_ver),
2076 IWL_UCODE_MINOR(priv->ucode_ver),
2077 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2078 IWL_UCODE_SERIAL(priv->ucode_ver),
2079 buildstr);
b481de9c 2080
b08dfd04
JB		 2081 /*
2082 * For any of the failures below (before allocating pci memory)
2083 * we will try to load a version with a smaller API -- maybe the
2084 * user just got a corrupted version of the latest API.
2085 */
2086
0e9a44dc
JB		 2087 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2088 priv->ucode_ver);
2089 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2090 pieces.inst_size);
2091 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2092 pieces.data_size);
2093 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2094 pieces.init_size);
2095 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2096 pieces.init_data_size);
2097 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2098 pieces.boot_size);
b481de9c
ZY		 2099
2100 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2101 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2102 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2103 pieces.inst_size);
b08dfd04 2104 goto try_again;
b481de9c
ZY		 2105 }
2106
0e9a44dc
JB		 2107 if (pieces.data_size > priv->hw_params.max_data_size) {
2108 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2109 pieces.data_size);
b08dfd04 2110 goto try_again;
b481de9c 2111 }
0e9a44dc
JB		 2112
2113 if (pieces.init_size > priv->hw_params.max_inst_size) {
2114 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2115 pieces.init_size);
b08dfd04 2116 goto try_again;
b481de9c 2117 }
0e9a44dc
JB		 2118
2119 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2120 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2121 pieces.init_data_size);
b08dfd04 2122 goto try_again;
b481de9c 2123 }
0e9a44dc
JB		 2124
2125 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2126 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2127 pieces.boot_size);
b08dfd04 2128 goto try_again;
b481de9c
ZY		 2129 }
2130
2131 /* Allocate ucode buffers for card's bus-master loading ... */
2132
2133 /* Runtime instructions and 2 copies of data:
2134 * 1) unmodified from disk
2135 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2136 priv->ucode_code.len = pieces.inst_size;
98c92211 2137 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2138
0e9a44dc 2139 priv->ucode_data.len = pieces.data_size;
98c92211 2140 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2141
0e9a44dc 2142 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2143 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2144
1f304e4e
ZY		 2145 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2146 !priv->ucode_data_backup.v_addr)
2147 goto err_pci_alloc;
2148
b481de9c 2149 /* Initialization instructions and data */
0e9a44dc
JB		 2150 if (pieces.init_size && pieces.init_data_size) {
2151 priv->ucode_init.len = pieces.init_size;
98c92211 2152 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2153
0e9a44dc 2154 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2155 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2156
2157 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2158 goto err_pci_alloc;
2159 }
b481de9c
ZY		 2160
2161 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2162 if (pieces.boot_size) {
2163 priv->ucode_boot.len = pieces.boot_size;
98c92211 2164 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2165
90e759d1
TW		 2166 if (!priv->ucode_boot.v_addr)
2167 goto err_pci_alloc;
2168 }
b481de9c 2169
b2e640d4
JB		 2170 /* Now that we can no longer fail, copy information */
2171
2172 /*
2173 * The (size - 16) / 12 formula is based on the information recorded
2174 * for each event, which is of mode 1 (including timestamp) for all
2175 * new microcodes that include this information.
2176 */
2177 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2178 if (pieces.init_evtlog_size)
2179 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2180 else
2181 priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size;
2182 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2183 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2184 if (pieces.inst_evtlog_size)
2185 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2186 else
2187 priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size;
2188 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2189
b481de9c
ZY		 2190 /* Copy images into buffers for card's bus-master reads ... */
2191
2192 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2193 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2194 pieces.inst_size);
2195 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2196
e1623446 2197 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2198 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2199
0e9a44dc
JB		 2200 /*
2201 * Runtime data
2202 * NOTE: Copy into backup buffer will be done in iwl_up()
2203 */
2204 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2205 pieces.data_size);
2206 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2207 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2208
2209 /* Initialization instructions */
2210 if (pieces.init_size) {
e1623446 2211 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2212 pieces.init_size);
2213 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2214 }
2215
0e9a44dc
JB		 2216 /* Initialization data */
2217 if (pieces.init_data_size) {
e1623446 2218 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2219 pieces.init_data_size);
2220 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2221 pieces.init_data_size);
b481de9c
ZY		 2222 }
2223
0e9a44dc
JB		 2224 /* Bootstrap instructions */
2225 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2226 pieces.boot_size);
2227 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2228
b08dfd04
JB		 2229 /**************************************************
2230 * This is still part of probe() in a sense...
2231 *
2232 * 9. Setup and register with mac80211 and debugfs
2233 **************************************************/
dd7a2509 2234 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2235 if (err)
2236 goto out_unbind;
2237
2238 err = iwl_dbgfs_register(priv, DRV_NAME);
2239 if (err)
2240 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2241
7d47618a
EG		 2242 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2243 &iwl_attribute_group);
2244 if (err) {
2245 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2246 goto out_unbind;
2247 }
2248
b481de9c
ZY		 2249 /* We have our copies now, allow OS release its copies */
2250 release_firmware(ucode_raw);
a15707d8 2251 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2252 return;
2253
2254 try_again:
2255 /* try next, if any */
2256 if (iwl_request_firmware(priv, false))
2257 goto out_unbind;
2258 release_firmware(ucode_raw);
2259 return;
b481de9c
ZY		 2260
2261 err_pci_alloc:
15b1687c 2262 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2263 iwl_dealloc_ucode_pci(priv);
b08dfd04 2264 out_unbind:
a15707d8 2265 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2266 device_release_driver(&priv->pci_dev->dev);
b481de9c 2267 release_firmware(ucode_raw);
b481de9c
ZY		 2268}
2269
b7a79404
RC		 2270static const char *desc_lookup_text[] = {
2271 "OK",
2272 "FAIL",
2273 "BAD_PARAM",
2274 "BAD_CHECKSUM",
2275 "NMI_INTERRUPT_WDG",
2276 "SYSASSERT",
2277 "FATAL_ERROR",
2278 "BAD_COMMAND",
2279 "HW_ERROR_TUNE_LOCK",
2280 "HW_ERROR_TEMPERATURE",
2281 "ILLEGAL_CHAN_FREQ",
2282 "VCC_NOT_STABLE",
2283 "FH_ERROR",
2284 "NMI_INTERRUPT_HOST",
2285 "NMI_INTERRUPT_ACTION_PT",
2286 "NMI_INTERRUPT_UNKNOWN",
2287 "UCODE_VERSION_MISMATCH",
2288 "HW_ERROR_ABS_LOCK",
2289 "HW_ERROR_CAL_LOCK_FAIL",
2290 "NMI_INTERRUPT_INST_ACTION_PT",
2291 "NMI_INTERRUPT_DATA_ACTION_PT",
2292 "NMI_TRM_HW_ER",
2293 "NMI_INTERRUPT_TRM",
2294 "NMI_INTERRUPT_BREAK_POINT"
2295 "DEBUG_0",
2296 "DEBUG_1",
2297 "DEBUG_2",
2298 "DEBUG_3",
a7fce6ee 2299 "ADVANCED SYSASSERT"
b7a79404
RC		 2300};
2301
2302static const char *desc_lookup(int i)
2303{
2304 int max = ARRAY_SIZE(desc_lookup_text) - 1;
2305
2306 if (i < 0 || i > max)
2307 i = max;
2308
2309 return desc_lookup_text[i];
2310}
2311
2312#define ERROR_START_OFFSET (1 * sizeof(u32))
2313#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2314
2315void iwl_dump_nic_error_log(struct iwl_priv *priv)
2316{
2317 u32 data2, line;
2318 u32 desc, time, count, base, data1;
2319 u32 blink1, blink2, ilink1, ilink2;
461ef382 2320 u32 pc, hcmd;
b7a79404 2321
b2e640d4 2322 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2323 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2324 if (!base)
2325 base = priv->_agn.init_errlog_ptr;
2326 } else {
b7a79404 2327 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2328 if (!base)
2329 base = priv->_agn.inst_errlog_ptr;
2330 }
b7a79404
RC		 2331
2332 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2333 IWL_ERR(priv,
2334 "Not valid error log pointer 0x%08X for %s uCode\n",
2335 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2336 return;
2337 }
2338
2339 count = iwl_read_targ_mem(priv, base);
2340
2341 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2342 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2343 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2344 priv->status, count);
2345 }
2346
2347 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
461ef382 2348 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2349 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2350 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2351 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2352 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2353 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2354 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2355 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2356 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2357 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2358
be1a71a1
JB		 2359 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2360 blink1, blink2, ilink1, ilink2);
2361
87563715 2362 IWL_ERR(priv, "Desc Time "
b7a79404 2363 "data1 data2 line\n");
87563715 2364 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2365 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2366 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2367 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2368 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2369}
2370
2371#define EVENT_START_OFFSET (4 * sizeof(u32))
2372
2373/**
2374 * iwl_print_event_log - Dump error event log to syslog
2375 *
2376 */
b03d7d0f
WYG		 2377static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2378 u32 num_events, u32 mode,
2379 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2380{
2381 u32 i;
2382 u32 base; /* SRAM byte address of event log header */
2383 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2384 u32 ptr; /* SRAM byte address of log data */
2385 u32 ev, time, data; /* event log data */
e5854471 2386 unsigned long reg_flags;
b7a79404
RC		 2387
2388 if (num_events == 0)
b03d7d0f 2389 return pos;
b2e640d4
JB		 2390
2391 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2392 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2393 if (!base)
2394 base = priv->_agn.init_evtlog_ptr;
2395 } else {
b7a79404 2396 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2397 if (!base)
2398 base = priv->_agn.inst_evtlog_ptr;
2399 }
b7a79404
RC		 2400
2401 if (mode == 0)
2402 event_size = 2 * sizeof(u32);
2403 else
2404 event_size = 3 * sizeof(u32);
2405
2406 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2407
e5854471
BC		 2408 /* Make sure device is powered up for SRAM reads */
2409 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2410 iwl_grab_nic_access(priv);
2411
2412 /* Set starting address; reads will auto-increment */
2413 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2414 rmb();
2415
b7a79404
RC		 2416 /* "time" is actually "data" for mode 0 (no timestamp).
2417 * place event id # at far right for easier visual parsing. */
2418 for (i = 0; i < num_events; i++) {
e5854471
BC		 2419 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2420 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2421 if (mode == 0) {
2422 /* data, ev */
b03d7d0f
WYG		 2423 if (bufsz) {
2424 pos += scnprintf(*buf + pos, bufsz - pos,
2425 "EVT_LOG:0x%08x:%04u\n",
2426 time, ev);
2427 } else {
2428 trace_iwlwifi_dev_ucode_event(priv, 0,
2429 time, ev);
2430 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2431 time, ev);
2432 }
b7a79404 2433 } else {
e5854471 2434 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2435 if (bufsz) {
2436 pos += scnprintf(*buf + pos, bufsz - pos,
2437 "EVT_LOGT:%010u:0x%08x:%04u\n",
2438 time, data, ev);
2439 } else {
2440 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2441 time, data, ev);
b03d7d0f
WYG		 2442 trace_iwlwifi_dev_ucode_event(priv, time,
2443 data, ev);
2444 }
b7a79404
RC		 2445 }
2446 }
e5854471
BC		 2447
2448 /* Allow device to power down */
2449 iwl_release_nic_access(priv);
2450 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2451 return pos;
b7a79404
RC		 2452}
2453
c341ddb2
WYG		 2454/**
2455 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2456 */
b03d7d0f
WYG		 2457static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2458 u32 num_wraps, u32 next_entry,
2459 u32 size, u32 mode,
2460 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2461{
2462 /*
2463 * display the newest DEFAULT_LOG_ENTRIES entries
2464 * i.e the entries just before the next ont that uCode would fill.
2465 */
2466 if (num_wraps) {
2467 if (next_entry < size) {
b03d7d0f
WYG		 2468 pos = iwl_print_event_log(priv,
2469 capacity - (size - next_entry),
2470 size - next_entry, mode,
2471 pos, buf, bufsz);
2472 pos = iwl_print_event_log(priv, 0,
2473 next_entry, mode,
2474 pos, buf, bufsz);
c341ddb2 2475 } else
b03d7d0f
WYG		 2476 pos = iwl_print_event_log(priv, next_entry - size,
2477 size, mode, pos, buf, bufsz);
c341ddb2 2478 } else {
b03d7d0f
WYG		 2479 if (next_entry < size) {
2480 pos = iwl_print_event_log(priv, 0, next_entry,
2481 mode, pos, buf, bufsz);
2482 } else {
2483 pos = iwl_print_event_log(priv, next_entry - size,
2484 size, mode, pos, buf, bufsz);
2485 }
c341ddb2 2486 }
b03d7d0f 2487 return pos;
c341ddb2
WYG		 2488}
2489
c341ddb2
WYG		 2490#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2491
b03d7d0f
WYG		 2492int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2493 char **buf, bool display)
b7a79404
RC		 2494{
2495 u32 base; /* SRAM byte address of event log header */
2496 u32 capacity; /* event log capacity in # entries */
2497 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2498 u32 num_wraps; /* # times uCode wrapped to top of log */
2499 u32 next_entry; /* index of next entry to be written by uCode */
2500 u32 size; /* # entries that we'll print */
b2e640d4 2501 u32 logsize;
b03d7d0f
WYG		 2502 int pos = 0;
2503 size_t bufsz = 0;
b7a79404 2504
b2e640d4 2505 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2506 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2507 logsize = priv->_agn.init_evtlog_size;
2508 if (!base)
2509 base = priv->_agn.init_evtlog_ptr;
2510 } else {
b7a79404 2511 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2512 logsize = priv->_agn.inst_evtlog_size;
2513 if (!base)
2514 base = priv->_agn.inst_evtlog_ptr;
2515 }
b7a79404
RC		 2516
2517 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2518 IWL_ERR(priv,
2519 "Invalid event log pointer 0x%08X for %s uCode\n",
2520 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2521 return -EINVAL;
b7a79404
RC		 2522 }
2523
2524 /* event log header */
2525 capacity = iwl_read_targ_mem(priv, base);
2526 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2527 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2528 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2529
b2e640d4 2530 if (capacity > logsize) {
84c40692 2531 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2532 capacity, logsize);
2533 capacity = logsize;
84c40692
BC		 2534 }
2535
b2e640d4 2536 if (next_entry > logsize) {
84c40692 2537 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2538 next_entry, logsize);
2539 next_entry = logsize;
84c40692
BC		 2540 }
2541
b7a79404
RC		 2542 size = num_wraps ? capacity : next_entry;
2543
2544 /* bail out if nothing in log */
2545 if (size == 0) {
2546 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2547 return pos;
b7a79404
RC		 2548 }
2549
c341ddb2 2550#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2551 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2552 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2553 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2554#else
2555 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2556 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2557#endif
2558 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2559 size);
b7a79404 2560
c341ddb2 2561#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2562 if (display) {
2563 if (full_log)
2564 bufsz = capacity * 48;
2565 else
2566 bufsz = size * 48;
2567 *buf = kmalloc(bufsz, GFP_KERNEL);
2568 if (!*buf)
937c397e 2569 return -ENOMEM;
b03d7d0f 2570 }
c341ddb2
WYG		 2571 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2572 /*
2573 * if uCode has wrapped back to top of log,
2574 * start at the oldest entry,
2575 * i.e the next one that uCode would fill.
2576 */
2577 if (num_wraps)
b03d7d0f
WYG		 2578 pos = iwl_print_event_log(priv, next_entry,
2579 capacity - next_entry, mode,
2580 pos, buf, bufsz);
c341ddb2 2581 /* (then/else) start at top of log */
b03d7d0f
WYG		 2582 pos = iwl_print_event_log(priv, 0,
2583 next_entry, mode, pos, buf, bufsz);
c341ddb2 2584 } else
b03d7d0f
WYG		 2585 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2586 next_entry, size, mode,
2587 pos, buf, bufsz);
c341ddb2 2588#else
b03d7d0f
WYG		 2589 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2590 next_entry, size, mode,
2591 pos, buf, bufsz);
b7a79404 2592#endif
b03d7d0f 2593 return pos;
c341ddb2 2594}
b7a79404 2595
b481de9c 2596/**
4a4a9e81 2597 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2598 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2599 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2600 */
4a4a9e81 2601static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2602{
57aab75a 2603 int ret = 0;
b481de9c 2604
e1623446 2605 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2606
2607 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2608 /* We had an error bringing up the hardware, so take it
2609 * all the way back down so we can try again */
e1623446 2610 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2611 goto restart;
2612 }
2613
2614 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2615 * This is a paranoid check, because we would not have gotten the
2616 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2617 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2618 /* Runtime instruction load was bad;
2619 * take it all the way back down so we can try again */
e1623446 2620 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2621 goto restart;
2622 }
2623
57aab75a
TW		 2624 ret = priv->cfg->ops->lib->alive_notify(priv);
2625 if (ret) {
39aadf8c
WT		 2626 IWL_WARN(priv,
2627 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2628 goto restart;
2629 }
2630
5b9f8cd3 2631 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2632 set_bit(STATUS_ALIVE, &priv->status);
2633
b74e31a9
WYG		 2634 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2635 /* Enable timer to monitor the driver queues */
2636 mod_timer(&priv->monitor_recover,
2637 jiffies +
2638 msecs_to_jiffies(priv->cfg->monitor_recover_period));
2639 }
2640
fee1247a 2641 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2642 return;
2643
36d6825b 2644 ieee80211_wake_queues(priv->hw);
b481de9c 2645
470ab2dd 2646 priv->active_rate = IWL_RATES_MASK;
b481de9c 2647
2f748dec
WYG		 2648 /* Configure Tx antenna selection based on H/W config */
2649 if (priv->cfg->ops->hcmd->set_tx_ant)
2650 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2651
3109ece1 2652 if (iwl_is_associated(priv)) {
c1adf9fb
GG		 2653 struct iwl_rxon_cmd *active_rxon =
2654 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA		 2655 /* apply any changes in staging */
2656 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2657 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2658 } else {
2659 /* Initialize our rx_config data */
1dda6d28 2660 iwl_connection_init_rx_config(priv, NULL);
45823531
AK		 2661
2662 if (priv->cfg->ops->hcmd->set_rxon_chain)
2663 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY		 2664 }
2665
9fbab516 2666 /* Configure Bluetooth device coexistence support */
65b52bde 2667 priv->cfg->ops->hcmd->send_bt_config(priv);
b481de9c 2668
4a4a9e81
TW		 2669 iwl_reset_run_time_calib(priv);
2670
b481de9c 2671 /* Configure the adapter for unassociated operation */
e0158e61 2672 iwlcore_commit_rxon(priv);
b481de9c
ZY		 2673
2674 /* At this point, the NIC is initialized and operational */
47f4a587 2675 iwl_rf_kill_ct_config(priv);
5a66926a 2676
e932a609 2677 iwl_leds_init(priv);
fe00b5a5 2678
e1623446 2679 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2680 set_bit(STATUS_READY, &priv->status);
5a66926a 2681 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2682
e312c24c 2683 iwl_power_update_mode(priv, true);
7e246191
RC		 2684 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2685
c46fbefa 2686
b481de9c
ZY		 2687 return;
2688
2689 restart:
2690 queue_work(priv->workqueue, &priv->restart);
2691}
2692
4e39317d 2693static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2694
5b9f8cd3 2695static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2696{
2697 unsigned long flags;
2698 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2699
e1623446 2700 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2701
b481de9c
ZY		 2702 if (!exit_pending)
2703 set_bit(STATUS_EXIT_PENDING, &priv->status);
2704
2c810ccd
JB		 2705 iwl_clear_ucode_stations(priv);
2706 iwl_dealloc_bcast_station(priv);
db125c78 2707 iwl_clear_driver_stations(priv);
b481de9c
ZY		 2708
2709 /* Unblock any waiting calls */
2710 wake_up_interruptible_all(&priv->wait_command_queue);
2711
b481de9c
ZY		 2712 /* Wipe out the EXIT_PENDING status bit if we are not actually
2713 * exiting the module */
2714 if (!exit_pending)
2715 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2716
2717 /* stop and reset the on-board processor */
3395f6e9 2718 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2719
2720 /* tell the device to stop sending interrupts */
0359facc 2721 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2722 iwl_disable_interrupts(priv);
0359facc
MA		 2723 spin_unlock_irqrestore(&priv->lock, flags);
2724 iwl_synchronize_irq(priv);
b481de9c
ZY		 2725
2726 if (priv->mac80211_registered)
2727 ieee80211_stop_queues(priv->hw);
2728
5b9f8cd3 2729 /* If we have not previously called iwl_init() then
a60e77e5 2730 * clear all bits but the RF Kill bit and return */
fee1247a 2731 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2732 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2733 STATUS_RF_KILL_HW |
9788864e
RC		 2734 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2735 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2736 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2737 STATUS_EXIT_PENDING;
b481de9c
ZY		 2738 goto exit;
2739 }
2740
6da3a13e 2741 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2742 * bit and continue taking the NIC down. */
b481de9c
ZY		 2743 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2744 STATUS_RF_KILL_HW |
9788864e
RC		 2745 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2746 STATUS_GEO_CONFIGURED |
b481de9c 2747 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2748 STATUS_FW_ERROR |
2749 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2750 STATUS_EXIT_PENDING;
b481de9c 2751
ef850d7c
MA		 2752 /* device going down, Stop using ICT table */
2753 iwl_disable_ict(priv);
b481de9c 2754
74bcdb33 2755 iwlagn_txq_ctx_stop(priv);
54b81550 2756 iwlagn_rxq_stop(priv);
b481de9c 2757
309e731a
BC		 2758 /* Power-down device's busmaster DMA clocks */
2759 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2760 udelay(5);
2761
309e731a
BC		 2762 /* Make sure (redundant) we've released our request to stay awake */
2763 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2764
4d2ccdb9
BC		 2765 /* Stop the device, and put it in low power state */
2766 priv->cfg->ops->lib->apm_ops.stop(priv);
2767
b481de9c 2768 exit:
885ba202 2769 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 2770
2771 if (priv->ibss_beacon)
2772 dev_kfree_skb(priv->ibss_beacon);
2773 priv->ibss_beacon = NULL;
2774
2775 /* clear out any free frames */
fcab423d 2776 iwl_clear_free_frames(priv);
b481de9c
ZY		 2777}
2778
5b9f8cd3 2779static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2780{
2781 mutex_lock(&priv->mutex);
5b9f8cd3 2782 __iwl_down(priv);
b481de9c 2783 mutex_unlock(&priv->mutex);
b24d22b1 2784
4e39317d 2785 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2786}
2787
086ed117
MA		 2788#define HW_READY_TIMEOUT (50)
2789
2790static int iwl_set_hw_ready(struct iwl_priv *priv)
2791{
2792 int ret = 0;
2793
2794 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2795 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2796
2797 /* See if we got it */
2798 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2799 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2800 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2801 HW_READY_TIMEOUT);
2802 if (ret != -ETIMEDOUT)
2803 priv->hw_ready = true;
2804 else
2805 priv->hw_ready = false;
2806
2807 IWL_DEBUG_INFO(priv, "hardware %s\n",
2808 (priv->hw_ready == 1) ? "ready" : "not ready");
2809 return ret;
2810}
2811
2812static int iwl_prepare_card_hw(struct iwl_priv *priv)
2813{
2814 int ret = 0;
2815
91dd6c27 2816 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2817
3354a0f6
MA		 2818 ret = iwl_set_hw_ready(priv);
2819 if (priv->hw_ready)
2820 return ret;
2821
2822 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 2823 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2824 CSR_HW_IF_CONFIG_REG_PREPARE);
2825
2826 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2827 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2828 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2829
3354a0f6 2830 /* HW should be ready by now, check again. */
086ed117
MA		 2831 if (ret != -ETIMEDOUT)
2832 iwl_set_hw_ready(priv);
2833
2834 return ret;
2835}
2836
b481de9c
ZY		 2837#define MAX_HW_RESTARTS 5
2838
5b9f8cd3 2839static int __iwl_up(struct iwl_priv *priv)
b481de9c 2840{
57aab75a
TW		 2841 int i;
2842 int ret;
b481de9c
ZY		 2843
2844 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2845 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 2846 return -EIO;
2847 }
2848
e903fbd4 2849 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2850 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 2851 return -EIO;
2852 }
2853
2c810ccd
JB		 2854 ret = iwl_alloc_bcast_station(priv, true);
2855 if (ret)
2856 return ret;
2857
086ed117
MA		 2858 iwl_prepare_card_hw(priv);
2859
2860 if (!priv->hw_ready) {
2861 IWL_WARN(priv, "Exit HW not ready\n");
2862 return -EIO;
2863 }
2864
e655b9f0 2865 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2866 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2867 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2868 else
e655b9f0 2869 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2870
c1842d61 2871 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 2872 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2873
5b9f8cd3 2874 iwl_enable_interrupts(priv);
a60e77e5 2875 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2876 return 0;
b481de9c
ZY		 2877 }
2878
3395f6e9 2879 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2880
74bcdb33 2881 ret = iwlagn_hw_nic_init(priv);
57aab75a 2882 if (ret) {
15b1687c 2883 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2884 return ret;
b481de9c
ZY		 2885 }
2886
2887 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2888 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2889 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 2890 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2891
2892 /* clear (again), then enable host interrupts */
3395f6e9 2893 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2894 iwl_enable_interrupts(priv);
b481de9c
ZY		 2895
2896 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2897 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2898 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 2899
2900 /* Copy original ucode data image from disk into backup cache.
2901 * This will be used to initialize the on-board processor's
2902 * data SRAM for a clean start when the runtime program first loads. */
2903 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2904 priv->ucode_data.len);
b481de9c 2905
b481de9c
ZY		 2906 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2907
b481de9c
ZY		 2908 /* load bootstrap state machine,
2909 * load bootstrap program into processor's memory,
2910 * prepare to load the "initialize" uCode */
57aab75a 2911 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2912
57aab75a 2913 if (ret) {
15b1687c
WT		 2914 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2915 ret);
b481de9c
ZY		 2916 continue;
2917 }
2918
2919 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2920 iwl_nic_start(priv);
b481de9c 2921
e1623446 2922 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 2923
2924 return 0;
2925 }
2926
2927 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2928 __iwl_down(priv);
64e72c3e 2929 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 2930
2931 /* tried to restart and config the device for as long as our
2932 * patience could withstand */
15b1687c 2933 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 2934 return -EIO;
2935}
2936
2937
2938/*****************************************************************************
2939 *
2940 * Workqueue callbacks
2941 *
2942 *****************************************************************************/
2943
4a4a9e81 2944static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2945{
c79dd5b5
TW		 2946 struct iwl_priv *priv =
2947 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 2948
2949 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2950 return;
2951
2952 mutex_lock(&priv->mutex);
f3ccc08c 2953 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 2954 mutex_unlock(&priv->mutex);
2955}
2956
4a4a9e81 2957static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2958{
c79dd5b5
TW		 2959 struct iwl_priv *priv =
2960 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 2961
2962 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2963 return;
2964
258c44a0
MA		 2965 /* enable dram interrupt */
2966 iwl_reset_ict(priv);
2967
b481de9c 2968 mutex_lock(&priv->mutex);
4a4a9e81 2969 iwl_alive_start(priv);
b481de9c
ZY		 2970 mutex_unlock(&priv->mutex);
2971}
2972
16e727e8
EG		 2973static void iwl_bg_run_time_calib_work(struct work_struct *work)
2974{
2975 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2976 run_time_calib_work);
2977
2978 mutex_lock(&priv->mutex);
2979
2980 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2981 test_bit(STATUS_SCANNING, &priv->status)) {
2982 mutex_unlock(&priv->mutex);
2983 return;
2984 }
2985
2986 if (priv->start_calib) {
f3aebeee 2987 iwl_chain_noise_calibration(priv, &priv->_agn.statistics);
16e727e8 2988
f3aebeee 2989 iwl_sensitivity_calibration(priv, &priv->_agn.statistics);
16e727e8
EG		 2990 }
2991
2992 mutex_unlock(&priv->mutex);
16e727e8
EG		 2993}
2994
5b9f8cd3 2995static void iwl_bg_restart(struct work_struct *data)
b481de9c 2996{
c79dd5b5 2997 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 2998
2999 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3000 return;
3001
19cc1087
JB		 3002 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3003 mutex_lock(&priv->mutex);
3004 priv->vif = NULL;
3005 priv->is_open = 0;
3006 mutex_unlock(&priv->mutex);
3007 iwl_down(priv);
3008 ieee80211_restart_hw(priv->hw);
3009 } else {
3010 iwl_down(priv);
80676518
JB		 3011
3012 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3013 return;
3014
3015 mutex_lock(&priv->mutex);
3016 __iwl_up(priv);
3017 mutex_unlock(&priv->mutex);
19cc1087 3018 }
b481de9c
ZY		 3019}
3020
5b9f8cd3 3021static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3022{
c79dd5b5
TW		 3023 struct iwl_priv *priv =
3024 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3025
3026 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3027 return;
3028
3029 mutex_lock(&priv->mutex);
54b81550 3030 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3031 mutex_unlock(&priv->mutex);
3032}
3033
7878a5a4
MA		 3034#define IWL_DELAY_NEXT_SCAN (HZ*2)
3035
1dda6d28 3036void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3037{
b481de9c 3038 struct ieee80211_conf *conf = NULL;
857485c0 3039 int ret = 0;
b481de9c 3040
1dda6d28
JB		 3041 if (!vif || !priv->is_open)
3042 return;
3043
3044 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 3045 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 3046 return;
3047 }
3048
b481de9c
ZY		 3049 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3050 return;
3051
2a421b91 3052 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 3053
b481de9c
ZY		 3054 conf = ieee80211_get_hw_conf(priv->hw);
3055
3056 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3057 iwlcore_commit_rxon(priv);
b481de9c 3058
1dda6d28 3059 iwl_setup_rxon_timing(priv, vif);
857485c0 3060 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 3061 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 3062 if (ret)
39aadf8c 3063 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 3064 "Attempting to continue.\n");
3065
3066 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
3067
42eb7c64 3068 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 3069
45823531
AK		 3070 if (priv->cfg->ops->hcmd->set_rxon_chain)
3071 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3072
1dda6d28 3073 priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3074
e1623446 3075 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3076 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3077
c213d745 3078 if (vif->bss_conf.use_short_preamble)
b481de9c
ZY		 3079 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
3080 else
3081 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
3082
3083 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3084 if (vif->bss_conf.use_short_slot)
b481de9c
ZY		 3085 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
3086 else
3087 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3088 }
3089
e0158e61 3090 iwlcore_commit_rxon(priv);
b481de9c 3091
fe6b23dd 3092 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
1dda6d28 3093 vif->bss_conf.aid, priv->active_rxon.bssid_addr);
fe6b23dd 3094
1dda6d28 3095 switch (vif->type) {
05c914fe 3096 case NL80211_IFTYPE_STATION:
b481de9c 3097 break;
05c914fe 3098 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 3099 iwl_send_beacon_cmd(priv);
b481de9c 3100 break;
b481de9c 3101 default:
15b1687c 3102 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 3103 __func__, vif->type);
b481de9c
ZY		 3104 break;
3105 }
3106
04816448
GE		 3107 /* the chain noise calibration will enabled PM upon completion
3108 * If chain noise has already been run, then we need to enable
3109 * power management here */
3110 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 3111 iwl_power_update_mode(priv, false);
c90a74ba
EG		 3112
3113 /* Enable Rx differential gain and sensitivity calibrations */
3114 iwl_chain_noise_reset(priv);
3115 priv->start_calib = 1;
3116
508e32e1
RC		 3117}
3118
b481de9c
ZY		 3119/*****************************************************************************
3120 *
3121 * mac80211 entry point functions
3122 *
3123 *****************************************************************************/
3124
154b25ce 3125#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3126
f0b6e2e8
RC		 3127/*
3128 * Not a mac80211 entry point function, but it fits in with all the
3129 * other mac80211 functions grouped here.
3130 */
dd7a2509
JB		 3131static int iwl_mac_setup_register(struct iwl_priv *priv,
3132 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3133{
3134 int ret;
3135 struct ieee80211_hw *hw = priv->hw;
3136 hw->rate_control_algorithm = "iwl-agn-rs";
3137
3138 /* Tell mac80211 our characteristics */
3139 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8
RC		 3140 IEEE80211_HW_AMPDU_AGGREGATION |
3141 IEEE80211_HW_SPECTRUM_MGMT;
3142
3143 if (!priv->cfg->broken_powersave)
3144 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3145 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3146
ba37a3d0
JB		 3147 if (priv->cfg->sku & IWL_SKU_N)
3148 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3149 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3150
8d9698b3 3151 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3152 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3153
f0b6e2e8
RC		 3154 hw->wiphy->interface_modes =
3155 BIT(NL80211_IFTYPE_STATION) |
3156 BIT(NL80211_IFTYPE_ADHOC);
3157
f6c8f152 3158 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3159 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3160
3161 /*
3162 * For now, disable PS by default because it affects
3163 * RX performance significantly.
3164 */
5be83de5 3165 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3166
1382c71c 3167 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3168 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3169 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3170
3171 /* Default value; 4 EDCA QOS priorities */
3172 hw->queues = 4;
3173
3174 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3175
3176 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3177 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3178 &priv->bands[IEEE80211_BAND_2GHZ];
3179 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3180 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3181 &priv->bands[IEEE80211_BAND_5GHZ];
3182
3183 ret = ieee80211_register_hw(priv->hw);
3184 if (ret) {
3185 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3186 return ret;
3187 }
3188 priv->mac80211_registered = 1;
3189
3190 return 0;
3191}
3192
3193
5b9f8cd3 3194static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 3195{
c79dd5b5 3196 struct iwl_priv *priv = hw->priv;
5a66926a 3197 int ret;
b481de9c 3198
e1623446 3199 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3200
3201 /* we should be verifying the device is ready to be opened */
3202 mutex_lock(&priv->mutex);
5b9f8cd3 3203 ret = __iwl_up(priv);
b481de9c 3204 mutex_unlock(&priv->mutex);
5a66926a 3205
e655b9f0 3206 if (ret)
6cd0b1cb 3207 return ret;
e655b9f0 3208
c1842d61
TW		 3209 if (iwl_is_rfkill(priv))
3210 goto out;
3211
e1623446 3212 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3213
fe9b6b72 3214 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3215 * mac80211 will not be run successfully. */
154b25ce
EG		 3216 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3217 test_bit(STATUS_READY, &priv->status),
3218 UCODE_READY_TIMEOUT);
3219 if (!ret) {
3220 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3221 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3222 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3223 return -ETIMEDOUT;
5a66926a 3224 }
fe9b6b72 3225 }
0a078ffa 3226
e932a609
JB		 3227 iwl_led_start(priv);
3228
c1842d61 3229out:
0a078ffa 3230 priv->is_open = 1;
e1623446 3231 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3232 return 0;
3233}
3234
5b9f8cd3 3235static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 3236{
c79dd5b5 3237 struct iwl_priv *priv = hw->priv;
b481de9c 3238
e1623446 3239 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3240
19cc1087 3241 if (!priv->is_open)
e655b9f0 3242 return;
e655b9f0 3243
b481de9c 3244 priv->is_open = 0;
5a66926a 3245
5bddf549 3246 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY		 3247 /* stop mac, cancel any scan request and clear
3248 * RXON_FILTER_ASSOC_MSK BIT
3249 */
5a66926a 3250 mutex_lock(&priv->mutex);
2a421b91 3251 iwl_scan_cancel_timeout(priv, 100);
fde3571f 3252 mutex_unlock(&priv->mutex);
fde3571f
MA		 3253 }
3254
5b9f8cd3 3255 iwl_down(priv);
5a66926a
ZY		 3256
3257 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3258
3259 /* enable interrupts again in order to receive rfkill changes */
3260 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3261 iwl_enable_interrupts(priv);
948c171c 3262
e1623446 3263 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3264}
3265
5b9f8cd3 3266static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3267{
c79dd5b5 3268 struct iwl_priv *priv = hw->priv;
b481de9c 3269
e1623446 3270 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3271
e1623446 3272 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3273 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3274
74bcdb33 3275 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3276 dev_kfree_skb_any(skb);
3277
e1623446 3278 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3279 return NETDEV_TX_OK;
b481de9c
ZY		 3280}
3281
1dda6d28 3282void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3283{
857485c0 3284 int ret = 0;
b481de9c 3285
d986bcd1 3286 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 3287 return;
3288
3289 /* The following should be done only at AP bring up */
3195c1f3 3290 if (!iwl_is_associated(priv)) {
b481de9c
ZY		 3291
3292 /* RXON - unassoc (to set timing command) */
3293 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 3294 iwlcore_commit_rxon(priv);
b481de9c
ZY		 3295
3296 /* RXON Timing */
1dda6d28 3297 iwl_setup_rxon_timing(priv, vif);
857485c0 3298 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 3299 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 3300 if (ret)
39aadf8c 3301 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY		 3302 "Attempting to continue.\n");
3303
f513dfff
DH		 3304 /* AP has all antennas */
3305 priv->chain_noise_data.active_chains =
3306 priv->hw_params.valid_rx_ant;
3307 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531
AK		 3308 if (priv->cfg->ops->hcmd->set_rxon_chain)
3309 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c 3310
1dda6d28
JB		 3311 priv->staging_rxon.assoc_id = 0;
3312
c213d745 3313 if (vif->bss_conf.use_short_preamble)
b481de9c
ZY		 3314 priv->staging_rxon.flags |=
3315 RXON_FLG_SHORT_PREAMBLE_MSK;
3316 else
3317 priv->staging_rxon.flags &=
3318 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3319
3320 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3321 if (vif->bss_conf.use_short_slot)
b481de9c
ZY		 3322 priv->staging_rxon.flags |=
3323 RXON_FLG_SHORT_SLOT_MSK;
3324 else
3325 priv->staging_rxon.flags &=
3326 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3327 }
3328 /* restore RXON assoc */
3329 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 3330 iwlcore_commit_rxon(priv);
e1493deb 3331 }
5b9f8cd3 3332 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3333
3334 /* FIXME - we need to add code here to detect a totally new
3335 * configuration, reset the AP, unassoc, rxon timing, assoc,
3336 * clear sta table, add BCAST sta... */
3337}
3338
5b9f8cd3 3339static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3340 struct ieee80211_vif *vif,
3341 struct ieee80211_key_conf *keyconf,
3342 struct ieee80211_sta *sta,
3343 u32 iv32, u16 *phase1key)
ab885f8c 3344{
ab885f8c 3345
9f58671e 3346 struct iwl_priv *priv = hw->priv;
e1623446 3347 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3348
bdbb612f 3349 iwl_update_tkip_key(priv, keyconf, sta,
b3fbdcf4 3350 iv32, phase1key);
ab885f8c 3351
e1623446 3352 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3353}
3354
5b9f8cd3 3355static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3356 struct ieee80211_vif *vif,
3357 struct ieee80211_sta *sta,
b481de9c
ZY		 3358 struct ieee80211_key_conf *key)
3359{
c79dd5b5 3360 struct iwl_priv *priv = hw->priv;
42986796
WT		 3361 int ret;
3362 u8 sta_id;
3363 bool is_default_wep_key = false;
b481de9c 3364
e1623446 3365 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3366
90e8e424 3367 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3368 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3369 return -EOPNOTSUPP;
3370 }
b481de9c 3371
0af8bcae
JB		 3372 sta_id = iwl_sta_id_or_broadcast(priv, sta);
3373 if (sta_id == IWL_INVALID_STATION)
3374 return -EINVAL;
b481de9c 3375
6974e363 3376 mutex_lock(&priv->mutex);
2a421b91 3377 iwl_scan_cancel_timeout(priv, 100);
6974e363 3378
a90178fa
JB		 3379 /*
3380 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3381 * so far, we are in legacy wep mode (group key only), otherwise we are
3382 * in 1X mode.
a90178fa
JB		 3383 * In legacy wep mode, we use another host command to the uCode.
3384 */
3385 if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
6974e363
EG		 3386 if (cmd == SET_KEY)
3387 is_default_wep_key = !priv->key_mapping_key;
3388 else
ccc038ab
EG		 3389 is_default_wep_key =
3390 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3391 }
052c4b9f 3392
b481de9c 3393 switch (cmd) {
deb09c43 3394 case SET_KEY:
6974e363
EG		 3395 if (is_default_wep_key)
3396 ret = iwl_set_default_wep_key(priv, key);
deb09c43 3397 else
7480513f 3398 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 3399
e1623446 3400 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3401 break;
3402 case DISABLE_KEY:
6974e363
EG		 3403 if (is_default_wep_key)
3404 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 3405 else
3ec47732 3406 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 3407
e1623446 3408 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3409 break;
3410 default:
deb09c43 3411 ret = -EINVAL;
b481de9c
ZY		 3412 }
3413
72e15d71 3414 mutex_unlock(&priv->mutex);
e1623446 3415 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3416
deb09c43 3417 return ret;
b481de9c
ZY		 3418}
3419
cfecc6b4
WYG		 3420/*
3421 * switch to RTS/CTS for TX
3422 */
3423static void iwl_enable_rts_cts(struct iwl_priv *priv)
3424{
3425
3426 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3427 return;
3428
3429 priv->staging_rxon.flags &= ~RXON_FLG_SELF_CTS_EN;
3430 if (!test_bit(STATUS_SCANNING, &priv->status)) {
3431 IWL_DEBUG_INFO(priv, "use RTS/CTS protection\n");
3432 iwlcore_commit_rxon(priv);
3433 } else {
3434 /* scanning, defer the request until scan completed */
3435 IWL_DEBUG_INFO(priv, "defer setting RTS/CTS protection\n");
3436 }
3437}
3438
5b9f8cd3 3439static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3440 struct ieee80211_vif *vif,
832f47e3
JB		 3441 enum ieee80211_ampdu_mlme_action action,
3442 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3443{
3444 struct iwl_priv *priv = hw->priv;
4620fefa 3445 int ret = -EINVAL;
d783b061 3446
e1623446 3447 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3448 sta->addr, tid);
d783b061
TW		 3449
3450 if (!(priv->cfg->sku & IWL_SKU_N))
3451 return -EACCES;
3452
4620fefa
JB		 3453 mutex_lock(&priv->mutex);
3454
d783b061
TW		 3455 switch (action) {
3456 case IEEE80211_AMPDU_RX_START:
e1623446 3457 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3458 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3459 break;
d783b061 3460 case IEEE80211_AMPDU_RX_STOP:
e1623446 3461 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3462 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3463 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3464 ret = 0;
3465 break;
d783b061 3466 case IEEE80211_AMPDU_TX_START:
e1623446 3467 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3468 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3469 if (ret == 0) {
3470 priv->_agn.agg_tids_count++;
3471 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3472 priv->_agn.agg_tids_count);
3473 }
4620fefa 3474 break;
d783b061 3475 case IEEE80211_AMPDU_TX_STOP:
e1623446 3476 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3477 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3478 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3479 priv->_agn.agg_tids_count--;
3480 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3481 priv->_agn.agg_tids_count);
3482 }
5c2207c6 3483 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3484 ret = 0;
3485 break;
f0527971 3486 case IEEE80211_AMPDU_TX_OPERATIONAL:
cfecc6b4
WYG		 3487 if (priv->cfg->use_rts_for_ht) {
3488 /*
3489 * switch to RTS/CTS if it is the prefer protection
3490 * method for HT traffic
3491 */
3492 iwl_enable_rts_cts(priv);
3493 }
3494 ret = 0;
d783b061
TW		 3495 break;
3496 }
4620fefa
JB		 3497 mutex_unlock(&priv->mutex);
3498
3499 return ret;
d783b061 3500}
9f58671e 3501
6ab10ff8
JB		 3502static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3503 struct ieee80211_vif *vif,
3504 enum sta_notify_cmd cmd,
3505 struct ieee80211_sta *sta)
3506{
3507 struct iwl_priv *priv = hw->priv;
3508 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3509 int sta_id;
3510
6ab10ff8 3511 switch (cmd) {
6ab10ff8
JB		 3512 case STA_NOTIFY_SLEEP:
3513 WARN_ON(!sta_priv->client);
3514 sta_priv->asleep = true;
3515 if (atomic_read(&sta_priv->pending_frames) > 0)
3516 ieee80211_sta_block_awake(hw, sta, true);
3517 break;
3518 case STA_NOTIFY_AWAKE:
3519 WARN_ON(!sta_priv->client);
49dcc819
DH		 3520 if (!sta_priv->asleep)
3521 break;
6ab10ff8 3522 sta_priv->asleep = false;
2a87c26b 3523 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3524 if (sta_id != IWL_INVALID_STATION)
3525 iwl_sta_modify_ps_wake(priv, sta_id);
3526 break;
3527 default:
3528 break;
3529 }
3530}
3531
fe6b23dd
RC		 3532static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3533 struct ieee80211_vif *vif,
3534 struct ieee80211_sta *sta)
3535{
3536 struct iwl_priv *priv = hw->priv;
3537 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
eafdfbd3 3538 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3539 int ret;
3540 u8 sta_id;
3541
3542 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3543 sta->addr);
da5ae1cf
RC		 3544 mutex_lock(&priv->mutex);
3545 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3546 sta->addr);
3547 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3548
3549 atomic_set(&sta_priv->pending_frames, 0);
3550 if (vif->type == NL80211_IFTYPE_AP)
3551 sta_priv->client = true;
3552
3553 ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
3554 &sta_id);
3555 if (ret) {
3556 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3557 sta->addr, ret);
3558 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3559 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3560 return ret;
3561 }
3562
fd1af15d
JB		 3563 sta_priv->common.sta_id = sta_id;
3564
fe6b23dd 3565 /* Initialize rate scaling */
91dd6c27 3566 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3567 sta->addr);
3568 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3569 mutex_unlock(&priv->mutex);
fe6b23dd 3570
fd1af15d 3571 return 0;
fe6b23dd
RC		 3572}
3573
79d07325
WYG		 3574static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3575 struct ieee80211_channel_switch *ch_switch)
3576{
3577 struct iwl_priv *priv = hw->priv;
3578 const struct iwl_channel_info *ch_info;
3579 struct ieee80211_conf *conf = &hw->conf;
3580 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3581 u16 ch;
3582 unsigned long flags = 0;
3583
3584 IWL_DEBUG_MAC80211(priv, "enter\n");
3585
3586 if (iwl_is_rfkill(priv))
3587 goto out_exit;
3588
3589 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3590 test_bit(STATUS_SCANNING, &priv->status))
3591 goto out_exit;
3592
3593 if (!iwl_is_associated(priv))
3594 goto out_exit;
3595
3596 /* channel switch in progress */
3597 if (priv->switch_rxon.switch_in_progress == true)
3598 goto out_exit;
3599
3600 mutex_lock(&priv->mutex);
3601 if (priv->cfg->ops->lib->set_channel_switch) {
3602
3603 ch = ieee80211_frequency_to_channel(
3604 ch_switch->channel->center_freq);
3605 if (le16_to_cpu(priv->active_rxon.channel) != ch) {
3606 ch_info = iwl_get_channel_info(priv,
3607 conf->channel->band,
3608 ch);
3609 if (!is_channel_valid(ch_info)) {
3610 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3611 goto out;
3612 }
3613 spin_lock_irqsave(&priv->lock, flags);
3614
3615 priv->current_ht_config.smps = conf->smps_mode;
3616
3617 /* Configure HT40 channels */
3618 ht_conf->is_ht = conf_is_ht(conf);
3619 if (ht_conf->is_ht) {
3620 if (conf_is_ht40_minus(conf)) {
3621 ht_conf->extension_chan_offset =
3622 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3623 ht_conf->is_40mhz = true;
3624 } else if (conf_is_ht40_plus(conf)) {
3625 ht_conf->extension_chan_offset =
3626 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3627 ht_conf->is_40mhz = true;
3628 } else {
3629 ht_conf->extension_chan_offset =
3630 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3631 ht_conf->is_40mhz = false;
3632 }
3633 } else
3634 ht_conf->is_40mhz = false;
3635
3636 /* if we are switching from ht to 2.4 clear flags
3637 * from any ht related info since 2.4 does not
3638 * support ht */
3639 if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
3640 priv->staging_rxon.flags = 0;
3641
3642 iwl_set_rxon_channel(priv, conf->channel);
3643 iwl_set_rxon_ht(priv, ht_conf);
3644 iwl_set_flags_for_band(priv, conf->channel->band,
3645 priv->vif);
3646 spin_unlock_irqrestore(&priv->lock, flags);
3647
3648 iwl_set_rate(priv);
3649 /*
3650 * at this point, staging_rxon has the
3651 * configuration for channel switch
3652 */
3653 if (priv->cfg->ops->lib->set_channel_switch(priv,
3654 ch_switch))
3655 priv->switch_rxon.switch_in_progress = false;
3656 }
3657 }
3658out:
3659 mutex_unlock(&priv->mutex);
3660out_exit:
3661 if (!priv->switch_rxon.switch_in_progress)
3662 ieee80211_chswitch_done(priv->vif, false);
3663 IWL_DEBUG_MAC80211(priv, "leave\n");
3664}
3665
716c74b0
WYG		 3666static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
3667{
3668 struct iwl_priv *priv = hw->priv;
3669
3670 mutex_lock(&priv->mutex);
3671 IWL_DEBUG_MAC80211(priv, "enter\n");
3672
3673 /* do not support "flush" */
3674 if (!priv->cfg->ops->lib->txfifo_flush)
3675 goto done;
3676
3677 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3678 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3679 goto done;
3680 }
3681 if (iwl_is_rfkill(priv)) {
3682 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3683 goto done;
3684 }
3685
3686 /*
3687 * mac80211 will not push any more frames for transmit
3688 * until the flush is completed
3689 */
3690 if (drop) {
3691 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3692 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3693 IWL_ERR(priv, "flush request fail\n");
3694 goto done;
3695 }
3696 }
3697 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3698 iwlagn_wait_tx_queue_empty(priv);
3699done:
3700 mutex_unlock(&priv->mutex);
3701 IWL_DEBUG_MAC80211(priv, "leave\n");
3702}
3703
b481de9c
ZY		 3704/*****************************************************************************
3705 *
3706 * driver setup and teardown
3707 *
3708 *****************************************************************************/
3709
4e39317d 3710static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3711{
d21050c7 3712 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 3713
3714 init_waitqueue_head(&priv->wait_command_queue);
3715
5b9f8cd3
EG		 3716 INIT_WORK(&priv->restart, iwl_bg_restart);
3717 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3718 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3719 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 3720 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
4a4a9e81
TW		 3721 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3722 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 3723
2a421b91 3724 iwl_setup_scan_deferred_work(priv);
bb8c093b 3725
4e39317d
EG		 3726 if (priv->cfg->ops->lib->setup_deferred_work)
3727 priv->cfg->ops->lib->setup_deferred_work(priv);
3728
3729 init_timer(&priv->statistics_periodic);
3730 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3731 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3732
a9e1cb6a
WYG		 3733 init_timer(&priv->ucode_trace);
3734 priv->ucode_trace.data = (unsigned long)priv;
3735 priv->ucode_trace.function = iwl_bg_ucode_trace;
3736
b74e31a9
WYG		 3737 if (priv->cfg->ops->lib->recover_from_tx_stall) {
3738 init_timer(&priv->monitor_recover);
3739 priv->monitor_recover.data = (unsigned long)priv;
3740 priv->monitor_recover.function =
3741 priv->cfg->ops->lib->recover_from_tx_stall;
3742 }
3743
ef850d7c
MA		 3744 if (!priv->cfg->use_isr_legacy)
3745 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3746 iwl_irq_tasklet, (unsigned long)priv);
3747 else
3748 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3749 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 3750}
3751
4e39317d 3752static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3753{
4e39317d
EG		 3754 if (priv->cfg->ops->lib->cancel_deferred_work)
3755 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3756
3ae6a054 3757 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3758 cancel_delayed_work(&priv->scan_check);
88be0264 3759 cancel_work_sync(&priv->start_internal_scan);
b481de9c 3760 cancel_delayed_work(&priv->alive_start);
815e629b 3761 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 3762 cancel_work_sync(&priv->beacon_update);
4e39317d 3763 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3764 del_timer_sync(&priv->ucode_trace);
b74e31a9
WYG		 3765 if (priv->cfg->ops->lib->recover_from_tx_stall)
3766 del_timer_sync(&priv->monitor_recover);
b481de9c
ZY		 3767}
3768
89f186a8
RC		 3769static void iwl_init_hw_rates(struct iwl_priv *priv,
3770 struct ieee80211_rate *rates)
3771{
3772 int i;
3773
3774 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3775 rates[i].bitrate = iwl_rates[i].ieee * 5;
3776 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3777 rates[i].hw_value_short = i;
3778 rates[i].flags = 0;
3779 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3780 /*
3781 * If CCK != 1M then set short preamble rate flag.
3782 */
3783 rates[i].flags |=
3784 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3785 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3786 }
3787 }
3788}
3789
3790static int iwl_init_drv(struct iwl_priv *priv)
3791{
3792 int ret;
3793
3794 priv->ibss_beacon = NULL;
3795
89f186a8
RC		 3796 spin_lock_init(&priv->sta_lock);
3797 spin_lock_init(&priv->hcmd_lock);
3798
3799 INIT_LIST_HEAD(&priv->free_frames);
3800
3801 mutex_init(&priv->mutex);
d2dfe6df 3802 mutex_init(&priv->sync_cmd_mutex);
89f186a8 3803
89f186a8
RC		 3804 priv->ieee_channels = NULL;
3805 priv->ieee_rates = NULL;
3806 priv->band = IEEE80211_BAND_2GHZ;
3807
3808 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3809 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3810 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3811 priv->_agn.agg_tids_count = 0;
89f186a8 3812
8a472da4
WYG		 3813 /* initialize force reset */
3814 priv->force_reset[IWL_RF_RESET].reset_duration =
3815 IWL_DELAY_NEXT_FORCE_RF_RESET;
3816 priv->force_reset[IWL_FW_RESET].reset_duration =
3817 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 3818
3819 /* Choose which receivers/antennas to use */
3820 if (priv->cfg->ops->hcmd->set_rxon_chain)
3821 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3822
3823 iwl_init_scan_params(priv);
3824
89f186a8
RC		 3825 /* Set the tx_power_user_lmt to the lowest power level
3826 * this value will get overwritten by channel max power avg
3827 * from eeprom */
b744cb79 3828 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 3829
3830 ret = iwl_init_channel_map(priv);
3831 if (ret) {
3832 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3833 goto err;
3834 }
3835
3836 ret = iwlcore_init_geos(priv);
3837 if (ret) {
3838 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3839 goto err_free_channel_map;
3840 }
3841 iwl_init_hw_rates(priv, priv->ieee_rates);
3842
3843 return 0;
3844
3845err_free_channel_map:
3846 iwl_free_channel_map(priv);
3847err:
3848 return ret;
3849}
3850
3851static void iwl_uninit_drv(struct iwl_priv *priv)
3852{
3853 iwl_calib_free_results(priv);
3854 iwlcore_free_geos(priv);
3855 iwl_free_channel_map(priv);
811ecc99 3856 kfree(priv->scan_cmd);
89f186a8
RC		 3857}
3858
5b9f8cd3
EG		 3859static struct ieee80211_ops iwl_hw_ops = {
3860 .tx = iwl_mac_tx,
3861 .start = iwl_mac_start,
3862 .stop = iwl_mac_stop,
3863 .add_interface = iwl_mac_add_interface,
3864 .remove_interface = iwl_mac_remove_interface,
3865 .config = iwl_mac_config,
5b9f8cd3
EG		 3866 .configure_filter = iwl_configure_filter,
3867 .set_key = iwl_mac_set_key,
3868 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 3869 .conf_tx = iwl_mac_conf_tx,
3870 .reset_tsf = iwl_mac_reset_tsf,
3871 .bss_info_changed = iwl_bss_info_changed,
3872 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 3873 .hw_scan = iwl_mac_hw_scan,
3874 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 3875 .sta_add = iwlagn_mac_sta_add,
3876 .sta_remove = iwl_mac_sta_remove,
79d07325 3877 .channel_switch = iwl_mac_channel_switch,
716c74b0 3878 .flush = iwl_mac_flush,
b481de9c
ZY		 3879};
3880
5b9f8cd3 3881static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY		 3882{
3883 int err = 0;
c79dd5b5 3884 struct iwl_priv *priv;
b481de9c 3885 struct ieee80211_hw *hw;
82b9a121 3886 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3887 unsigned long flags;
6cd0b1cb 3888 u16 pci_cmd;
30eabc17 3889 u8 perm_addr[ETH_ALEN];
b481de9c 3890
316c30d9
AK		 3891 /************************
3892 * 1. Allocating HW data
3893 ************************/
3894
6440adb5
CB		 3895 /* Disabling hardware scan means that mac80211 will perform scans
3896 * "the hard way", rather than using device's scan. */
1ea87396 3897 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3898 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK		 3899 dev_printk(KERN_DEBUG, &(pdev->dev),
3900 "Disabling hw_scan\n");
5b9f8cd3 3901 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 3902 }
3903
5b9f8cd3 3904 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3905 if (!hw) {
b481de9c
ZY		 3906 err = -ENOMEM;
3907 goto out;
3908 }
1d0a082d
AK		 3909 priv = hw->priv;
3910 /* At this point both hw and priv are allocated. */
3911
b481de9c
ZY		 3912 SET_IEEE80211_DEV(hw, &pdev->dev);
3913
e1623446 3914 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3915 priv->cfg = cfg;
b481de9c 3916 priv->pci_dev = pdev;
40cefda9 3917 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3918
20594eb0
WYG		 3919 if (iwl_alloc_traffic_mem(priv))
3920 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3921
316c30d9
AK		 3922 /**************************
3923 * 2. Initializing PCI bus
3924 **************************/
3925 if (pci_enable_device(pdev)) {
3926 err = -ENODEV;
3927 goto out_ieee80211_free_hw;
3928 }
3929
3930 pci_set_master(pdev);
3931
093d874c 3932 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3933 if (!err)
093d874c 3934 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3935 if (err) {
093d874c 3936 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3937 if (!err)
093d874c 3938 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3939 /* both attempts failed: */
316c30d9 3940 if (err) {
978785a3 3941 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3942 goto out_pci_disable_device;
cc2a8ea8 3943 }
316c30d9
AK		 3944 }
3945
3946 err = pci_request_regions(pdev, DRV_NAME);
3947 if (err)
3948 goto out_pci_disable_device;
3949
3950 pci_set_drvdata(pdev, priv);
3951
316c30d9
AK		 3952
3953 /***********************
3954 * 3. Read REV register
3955 ***********************/
3956 priv->hw_base = pci_iomap(pdev, 0, 0);
3957 if (!priv->hw_base) {
3958 err = -ENODEV;
3959 goto out_pci_release_regions;
3960 }
3961
e1623446 3962 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3963 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3964 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3965
731a29b7 3966 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 3967 * we should init now
3968 */
3969 spin_lock_init(&priv->reg_lock);
731a29b7 3970 spin_lock_init(&priv->lock);
4843b5a7
RC		 3971
3972 /*
3973 * stop and reset the on-board processor just in case it is in a
3974 * strange state ... like being left stranded by a primary kernel
3975 * and this is now the kdump kernel trying to start up
3976 */
3977 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3978
b661c819 3979 iwl_hw_detect(priv);
c11362c0 3980 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 3981 priv->cfg->name, priv->hw_rev);
316c30d9 3982
e7b63581
TW		 3983 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3984 * PCI Tx retries from interfering with C3 CPU state */
3985 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3986
086ed117
MA		 3987 iwl_prepare_card_hw(priv);
3988 if (!priv->hw_ready) {
3989 IWL_WARN(priv, "Failed, HW not ready\n");
3990 goto out_iounmap;
3991 }
3992
91238714
TW		 3993 /*****************
3994 * 4. Read EEPROM
3995 *****************/
316c30d9
AK		 3996 /* Read the EEPROM */
3997 err = iwl_eeprom_init(priv);
3998 if (err) {
15b1687c 3999 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4000 goto out_iounmap;
4001 }
8614f360
TW		 4002 err = iwl_eeprom_check_version(priv);
4003 if (err)
c8f16138 4004 goto out_free_eeprom;
8614f360 4005
02883017 4006 /* extract MAC Address */
30eabc17
JB		 4007 iwl_eeprom_get_mac(priv, perm_addr);
4008 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", perm_addr);
4009 SET_IEEE80211_PERM_ADDR(priv->hw, perm_addr);
316c30d9
AK		 4010
4011 /************************
4012 * 5. Setup HW constants
4013 ************************/
da154e30 4014 if (iwl_set_hw_params(priv)) {
15b1687c 4015 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4016 goto out_free_eeprom;
316c30d9
AK		 4017 }
4018
4019 /*******************
6ba87956 4020 * 6. Setup priv
316c30d9 4021 *******************/
b481de9c 4022
6ba87956 4023 err = iwl_init_drv(priv);
bf85ea4f 4024 if (err)
399f4900 4025 goto out_free_eeprom;
bf85ea4f 4026 /* At this point both hw and priv are initialized. */
316c30d9 4027
316c30d9 4028 /********************
09f9bf79 4029 * 7. Setup services
316c30d9 4030 ********************/
0359facc 4031 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4032 iwl_disable_interrupts(priv);
0359facc 4033 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4034
6cd0b1cb
HS		 4035 pci_enable_msi(priv->pci_dev);
4036
ef850d7c
MA		 4037 iwl_alloc_isr_ict(priv);
4038 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4039 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4040 if (err) {
4041 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4042 goto out_disable_msi;
4043 }
316c30d9 4044
4e39317d 4045 iwl_setup_deferred_work(priv);
653fa4a0 4046 iwl_setup_rx_handlers(priv);
316c30d9 4047
158bea07
JB		 4048 /*********************************************
4049 * 8. Enable interrupts and read RFKILL state
4050 *********************************************/
6ba87956 4051
6cd0b1cb
HS		 4052 /* enable interrupts if needed: hw bug w/a */
4053 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4054 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4055 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4056 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4057 }
4058
4059 iwl_enable_interrupts(priv);
4060
6cd0b1cb
HS		 4061 /* If platform's RF_KILL switch is NOT set to KILL */
4062 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4063 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4064 else
4065 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4066
a60e77e5
JB		 4067 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4068 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4069
58d0f361 4070 iwl_power_initialize(priv);
39b73fb1 4071 iwl_tt_initialize(priv);
158bea07 4072
a15707d8 4073 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4074
b08dfd04 4075 err = iwl_request_firmware(priv, true);
158bea07 4076 if (err)
7d47618a 4077 goto out_destroy_workqueue;
158bea07 4078
b481de9c
ZY		 4079 return 0;
4080
7d47618a 4081 out_destroy_workqueue:
c8f16138
RC		 4082 destroy_workqueue(priv->workqueue);
4083 priv->workqueue = NULL;
795cc0ad 4084 free_irq(priv->pci_dev->irq, priv);
ef850d7c 4085 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 4086 out_disable_msi:
4087 pci_disable_msi(priv->pci_dev);
6ba87956 4088 iwl_uninit_drv(priv);
073d3f5f
TW		 4089 out_free_eeprom:
4090 iwl_eeprom_free(priv);
b481de9c
ZY		 4091 out_iounmap:
4092 pci_iounmap(pdev, priv->hw_base);
4093 out_pci_release_regions:
316c30d9 4094 pci_set_drvdata(pdev, NULL);
623d563e 4095 pci_release_regions(pdev);
b481de9c
ZY		 4096 out_pci_disable_device:
4097 pci_disable_device(pdev);
b481de9c 4098 out_ieee80211_free_hw:
20594eb0 4099 iwl_free_traffic_mem(priv);
d7c76f4c 4100 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4101 out:
4102 return err;
4103}
4104
5b9f8cd3 4105static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4106{
c79dd5b5 4107 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4108 unsigned long flags;
b481de9c
ZY		 4109
4110 if (!priv)
4111 return;
4112
a15707d8 4113 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4114
e1623446 4115 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4116
67249625 4117 iwl_dbgfs_unregister(priv);
5b9f8cd3 4118 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4119
5b9f8cd3
EG		 4120 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4121 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4122 * we need to set STATUS_EXIT_PENDING bit.
4123 */
4124 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4125 if (priv->mac80211_registered) {
4126 ieee80211_unregister_hw(priv->hw);
4127 priv->mac80211_registered = 0;
0b124c31 4128 } else {
5b9f8cd3 4129 iwl_down(priv);
c4f55232
RR		 4130 }
4131
c166b25a
BC		 4132 /*
4133 * Make sure device is reset to low power before unloading driver.
4134 * This may be redundant with iwl_down(), but there are paths to
4135 * run iwl_down() without calling apm_ops.stop(), and there are
4136 * paths to avoid running iwl_down() at all before leaving driver.
4137 * This (inexpensive) call *makes sure* device is reset.
4138 */
4139 priv->cfg->ops->lib->apm_ops.stop(priv);
4140
39b73fb1
WYG		 4141 iwl_tt_exit(priv);
4142
0359facc
MA		 4143 /* make sure we flush any pending irq or
4144 * tasklet for the driver
4145 */
4146 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4147 iwl_disable_interrupts(priv);
0359facc
MA		 4148 spin_unlock_irqrestore(&priv->lock, flags);
4149
4150 iwl_synchronize_irq(priv);
4151
5b9f8cd3 4152 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4153
4154 if (priv->rxq.bd)
54b81550 4155 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4156 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4157
073d3f5f 4158 iwl_eeprom_free(priv);
b481de9c 4159
b481de9c 4160
948c171c
MA		 4161 /*netif_stop_queue(dev); */
4162 flush_workqueue(priv->workqueue);
4163
5b9f8cd3 4164 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4165 * priv->workqueue... so we can't take down the workqueue
4166 * until now... */
4167 destroy_workqueue(priv->workqueue);
4168 priv->workqueue = NULL;
20594eb0 4169 iwl_free_traffic_mem(priv);
b481de9c 4170
6cd0b1cb
HS		 4171 free_irq(priv->pci_dev->irq, priv);
4172 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4173 pci_iounmap(pdev, priv->hw_base);
4174 pci_release_regions(pdev);
4175 pci_disable_device(pdev);
4176 pci_set_drvdata(pdev, NULL);
4177
6ba87956 4178 iwl_uninit_drv(priv);
b481de9c 4179
ef850d7c
MA		 4180 iwl_free_isr_ict(priv);
4181
b481de9c
ZY		 4182 if (priv->ibss_beacon)
4183 dev_kfree_skb(priv->ibss_beacon);
4184
4185 ieee80211_free_hw(priv->hw);
4186}
4187
b481de9c
ZY		 4188
4189/*****************************************************************************
4190 *
4191 * driver and module entry point
4192 *
4193 *****************************************************************************/
4194
fed9017e 4195/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4196static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4197#ifdef CONFIG_IWL4965
fed9017e
RR		 4198 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4199 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4200#endif /* CONFIG_IWL4965 */
5a6a256e 4201#ifdef CONFIG_IWL5000
ac592574
WYG		 4202/* 5100 Series WiFi */
4203 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4204 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4205 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4206 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4207 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4208 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4209 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4210 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4211 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4212 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4213 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4214 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4215 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4216 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4217 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4218 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4219 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4220 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4221 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4222 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4223 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4224 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4225 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4226 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4227
4228/* 5300 Series WiFi */
4229 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4230 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4231 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4232 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4233 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4234 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4235 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4236 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4237 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4238 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4239 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4240 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4241
4242/* 5350 Series WiFi/WiMax */
4243 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4244 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4245 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4246
4247/* 5150 Series Wifi/WiMax */
4248 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4249 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4250 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4251 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4252 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4253 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4254
4255 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4256 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4257 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4258 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4259
4260/* 6x00 Series */
5953a62e
WYG		 4261 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4262 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4263 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4264 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4265 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4266 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4267 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4268 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4269 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4270 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4271
95b13014
SZ		 4272/* 6x00 Series Gen2a */
4273 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4274 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4275 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
1808972f
SZ		 4276 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4277 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4278 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4279 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
9f6e1baf
SZ		 4280 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4281 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4282 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4283 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4284 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4285 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4286 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4287
4288/* 6x00 Series Gen2b */
4289 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4290 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4291 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4292 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4293 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4294 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4295 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4296 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4297 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4298 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4299 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
9f6e1baf
SZ		 4300 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4301 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4302 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4303 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4304 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4305 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4306 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4307 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4308 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4309 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4310 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4311 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4312 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4313 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4314 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4315 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4316 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4317
4318/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4319 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4320 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4321 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4322 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4323 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4324 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4325
77dcb6a9 4326/* 1000 Series WiFi */
4bd0914f
WYG		 4327 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4328 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4329 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4330 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4331 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4332 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4333 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4334 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4335 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4336 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4337 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4338 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 4339#endif /* CONFIG_IWL5000 */
7100e924 4340
fed9017e
RR		 4341 {0}
4342};
4343MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4344
4345static struct pci_driver iwl_driver = {
b481de9c 4346 .name = DRV_NAME,
fed9017e 4347 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4348 .probe = iwl_pci_probe,
4349 .remove = __devexit_p(iwl_pci_remove),
b481de9c 4350#ifdef CONFIG_PM
5b9f8cd3
EG		 4351 .suspend = iwl_pci_suspend,
4352 .resume = iwl_pci_resume,
b481de9c
ZY		 4353#endif
4354};
4355
5b9f8cd3 4356static int __init iwl_init(void)
b481de9c
ZY		 4357{
4358
4359 int ret;
4360 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
4361 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 4362
e227ceac 4363 ret = iwlagn_rate_control_register();
897e1cf2 4364 if (ret) {
a3139c59
SO		 4365 printk(KERN_ERR DRV_NAME
4366 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4367 return ret;
4368 }
4369
fed9017e 4370 ret = pci_register_driver(&iwl_driver);
b481de9c 4371 if (ret) {
a3139c59 4372 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 4373 goto error_register;
b481de9c 4374 }
b481de9c
ZY		 4375
4376 return ret;
897e1cf2 4377
897e1cf2 4378error_register:
e227ceac 4379 iwlagn_rate_control_unregister();
897e1cf2 4380 return ret;
b481de9c
ZY		 4381}
4382
5b9f8cd3 4383static void __exit iwl_exit(void)
b481de9c 4384{
fed9017e 4385 pci_unregister_driver(&iwl_driver);
e227ceac 4386 iwlagn_rate_control_unregister();
b481de9c
ZY		 4387}
4388
5b9f8cd3
EG		 4389module_exit(iwl_exit);
4390module_init(iwl_init);
a562a9dd
RC		 4391
4392#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4393module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4394MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4395module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4396MODULE_PARM_DESC(debug, "debug output mask");
4397#endif
4398
2b068618
WYG		 4399module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4400MODULE_PARM_DESC(swcrypto50,
4401 "using crypto in software (default 0 [hardware]) (deprecated)");
4402module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4403MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4404module_param_named(queues_num50,
4405 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4406MODULE_PARM_DESC(queues_num50,
4407 "number of hw queues in 50xx series (deprecated)");
4408module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4409MODULE_PARM_DESC(queues_num, "number of hw queues.");
4410module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4411MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4412module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4413MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4414module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4415 int, S_IRUGO);
4416MODULE_PARM_DESC(amsdu_size_8K50,
4417 "enable 8K amsdu size in 50XX series (deprecated)");
4418module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4419 int, S_IRUGO);
4420MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4421module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4422MODULE_PARM_DESC(fw_restart50,
4423 "restart firmware in case of error (deprecated)");
4424module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4425MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4426module_param_named(
4427 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4428MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
dd7a2509
JB		 4429
4430module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4431 S_IRUGO);
4432MODULE_PARM_DESC(ucode_alternative,
4433 "specify ucode alternative to use from ucode file");
Linux kernel - Deliverables
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