Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
901069c7 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
c96c31e4 JP |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
b481de9c ZY |
32 | #include <linux/kernel.h> |
33 | #include <linux/module.h> | |
b481de9c ZY |
34 | #include <linux/init.h> |
35 | #include <linux/pci.h> | |
1a7123cd | 36 | #include <linux/pci-aspm.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
b481de9c ZY |
38 | #include <linux/dma-mapping.h> |
39 | #include <linux/delay.h> | |
d43c36dc | 40 | #include <linux/sched.h> |
b481de9c ZY |
41 | #include <linux/skbuff.h> |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/wireless.h> | |
44 | #include <linux/firmware.h> | |
b481de9c ZY |
45 | #include <linux/etherdevice.h> |
46 | #include <linux/if_arp.h> | |
47 | ||
b481de9c ZY |
48 | #include <net/mac80211.h> |
49 | ||
50 | #include <asm/div64.h> | |
51 | ||
a3139c59 SO |
52 | #define DRV_NAME "iwlagn" |
53 | ||
6bc913bd | 54 | #include "iwl-eeprom.h" |
3e0d4cb1 | 55 | #include "iwl-dev.h" |
fee1247a | 56 | #include "iwl-core.h" |
3395f6e9 | 57 | #include "iwl-io.h" |
b481de9c | 58 | #include "iwl-helpers.h" |
6974e363 | 59 | #include "iwl-sta.h" |
0de76736 | 60 | #include "iwl-agn-calib.h" |
a1175124 | 61 | #include "iwl-agn.h" |
b481de9c | 62 | |
416e1438 | 63 | |
b481de9c ZY |
64 | /****************************************************************************** |
65 | * | |
66 | * module boiler plate | |
67 | * | |
68 | ******************************************************************************/ | |
69 | ||
b481de9c ZY |
70 | /* |
71 | * module name, copyright, version, etc. | |
b481de9c | 72 | */ |
d783b061 | 73 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 74 | |
0a6857e7 | 75 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
76 | #define VD "d" |
77 | #else | |
78 | #define VD | |
79 | #endif | |
80 | ||
81963d68 | 81 | #define DRV_VERSION IWLWIFI_VERSION VD |
b481de9c | 82 | |
b481de9c ZY |
83 | |
84 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
85 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 86 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c ZY |
87 | MODULE_LICENSE("GPL"); |
88 | ||
bee008b7 | 89 | static int iwlagn_ant_coupling; |
f37837c9 | 90 | static bool iwlagn_bt_ch_announce = 1; |
bee008b7 | 91 | |
5b9f8cd3 | 92 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f | 93 | { |
246ed355 | 94 | struct iwl_rxon_context *ctx; |
5da4b55f | 95 | |
246ed355 JB |
96 | if (priv->cfg->ops->hcmd->set_rxon_chain) { |
97 | for_each_context(priv, ctx) { | |
98 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
6163a373 SZ |
99 | if (ctx->active.rx_chain != ctx->staging.rx_chain) |
100 | iwlcore_commit_rxon(priv, ctx); | |
246ed355 JB |
101 | } |
102 | } | |
5da4b55f MA |
103 | } |
104 | ||
fcab423d | 105 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
106 | { |
107 | struct list_head *element; | |
108 | ||
e1623446 | 109 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
110 | priv->frames_count); |
111 | ||
112 | while (!list_empty(&priv->free_frames)) { | |
113 | element = priv->free_frames.next; | |
114 | list_del(element); | |
fcab423d | 115 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
116 | priv->frames_count--; |
117 | } | |
118 | ||
119 | if (priv->frames_count) { | |
39aadf8c | 120 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
121 | priv->frames_count); |
122 | priv->frames_count = 0; | |
123 | } | |
124 | } | |
125 | ||
fcab423d | 126 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 127 | { |
fcab423d | 128 | struct iwl_frame *frame; |
b481de9c ZY |
129 | struct list_head *element; |
130 | if (list_empty(&priv->free_frames)) { | |
131 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
132 | if (!frame) { | |
15b1687c | 133 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
134 | return NULL; |
135 | } | |
136 | ||
137 | priv->frames_count++; | |
138 | return frame; | |
139 | } | |
140 | ||
141 | element = priv->free_frames.next; | |
142 | list_del(element); | |
fcab423d | 143 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
144 | } |
145 | ||
fcab423d | 146 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
147 | { |
148 | memset(frame, 0, sizeof(*frame)); | |
149 | list_add(&frame->list, &priv->free_frames); | |
150 | } | |
151 | ||
47ff65c4 | 152 | static u32 iwl_fill_beacon_frame(struct iwl_priv *priv, |
77834543 JB |
153 | struct ieee80211_hdr *hdr, |
154 | int left) | |
b481de9c | 155 | { |
77834543 JB |
156 | lockdep_assert_held(&priv->mutex); |
157 | ||
12e934dc | 158 | if (!priv->beacon_skb) |
b481de9c ZY |
159 | return 0; |
160 | ||
12e934dc | 161 | if (priv->beacon_skb->len > left) |
b481de9c ZY |
162 | return 0; |
163 | ||
12e934dc | 164 | memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len); |
b481de9c | 165 | |
12e934dc | 166 | return priv->beacon_skb->len; |
b481de9c ZY |
167 | } |
168 | ||
47ff65c4 DH |
169 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ |
170 | static void iwl_set_beacon_tim(struct iwl_priv *priv, | |
77834543 JB |
171 | struct iwl_tx_beacon_cmd *tx_beacon_cmd, |
172 | u8 *beacon, u32 frame_size) | |
47ff65c4 DH |
173 | { |
174 | u16 tim_idx; | |
175 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
176 | ||
177 | /* | |
178 | * The index is relative to frame start but we start looking at the | |
179 | * variable-length part of the beacon. | |
180 | */ | |
181 | tim_idx = mgmt->u.beacon.variable - beacon; | |
182 | ||
183 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
184 | while ((tim_idx < (frame_size - 2)) && | |
185 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
186 | tim_idx += beacon[tim_idx+1] + 2; | |
187 | ||
188 | /* If TIM field was found, set variables */ | |
189 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
190 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
191 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
192 | } else | |
193 | IWL_WARN(priv, "Unable to find TIM Element in beacon\n"); | |
194 | } | |
195 | ||
5b9f8cd3 | 196 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
47ff65c4 | 197 | struct iwl_frame *frame) |
4bf64efd TW |
198 | { |
199 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
47ff65c4 DH |
200 | u32 frame_size; |
201 | u32 rate_flags; | |
202 | u32 rate; | |
203 | /* | |
204 | * We have to set up the TX command, the TX Beacon command, and the | |
205 | * beacon contents. | |
206 | */ | |
4bf64efd | 207 | |
76d04815 JB |
208 | lockdep_assert_held(&priv->mutex); |
209 | ||
210 | if (!priv->beacon_ctx) { | |
211 | IWL_ERR(priv, "trying to build beacon w/o beacon context!\n"); | |
950094cb | 212 | return 0; |
76d04815 JB |
213 | } |
214 | ||
47ff65c4 | 215 | /* Initialize memory */ |
4bf64efd TW |
216 | tx_beacon_cmd = &frame->u.beacon; |
217 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
218 | ||
47ff65c4 | 219 | /* Set up TX beacon contents */ |
4bf64efd | 220 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, |
4bf64efd | 221 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
47ff65c4 DH |
222 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) |
223 | return 0; | |
40bbfd4c JB |
224 | if (!frame_size) |
225 | return 0; | |
4bf64efd | 226 | |
47ff65c4 | 227 | /* Set up TX command fields */ |
4bf64efd | 228 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); |
76d04815 | 229 | tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id; |
47ff65c4 DH |
230 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
231 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
232 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
4bf64efd | 233 | |
47ff65c4 DH |
234 | /* Set up TX beacon command fields */ |
235 | iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame, | |
77834543 | 236 | frame_size); |
4bf64efd | 237 | |
47ff65c4 | 238 | /* Set up packet rate and flags */ |
76d04815 | 239 | rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx); |
0e1654fa JB |
240 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, |
241 | priv->hw_params.valid_tx_ant); | |
47ff65c4 DH |
242 | rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); |
243 | if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) | |
244 | rate_flags |= RATE_MCS_CCK_MSK; | |
245 | tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, | |
246 | rate_flags); | |
4bf64efd TW |
247 | |
248 | return sizeof(*tx_beacon_cmd) + frame_size; | |
249 | } | |
2295c66b JB |
250 | |
251 | int iwlagn_send_beacon_cmd(struct iwl_priv *priv) | |
b481de9c | 252 | { |
fcab423d | 253 | struct iwl_frame *frame; |
b481de9c ZY |
254 | unsigned int frame_size; |
255 | int rc; | |
b4ebd28f JB |
256 | struct iwl_host_cmd cmd = { |
257 | .id = REPLY_TX_BEACON, | |
258 | .flags = CMD_SIZE_HUGE, | |
259 | }; | |
b481de9c | 260 | |
fcab423d | 261 | frame = iwl_get_free_frame(priv); |
b481de9c | 262 | if (!frame) { |
15b1687c | 263 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
264 | "command.\n"); |
265 | return -ENOMEM; | |
266 | } | |
267 | ||
47ff65c4 DH |
268 | frame_size = iwl_hw_get_beacon_cmd(priv, frame); |
269 | if (!frame_size) { | |
270 | IWL_ERR(priv, "Error configuring the beacon command\n"); | |
271 | iwl_free_frame(priv, frame); | |
272 | return -EINVAL; | |
273 | } | |
b481de9c | 274 | |
b4ebd28f JB |
275 | cmd.len = frame_size; |
276 | cmd.data = &frame->u.cmd[0]; | |
277 | ||
278 | rc = iwl_send_cmd_sync(priv, &cmd); | |
b481de9c | 279 | |
fcab423d | 280 | iwl_free_frame(priv, frame); |
b481de9c ZY |
281 | |
282 | return rc; | |
283 | } | |
284 | ||
7aaa1d79 SO |
285 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
286 | { | |
287 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
288 | ||
289 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
290 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
291 | addr |= | |
292 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
293 | ||
294 | return addr; | |
295 | } | |
296 | ||
297 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
298 | { | |
299 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
300 | ||
301 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
302 | } | |
303 | ||
304 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
305 | dma_addr_t addr, u16 len) | |
306 | { | |
307 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
308 | u16 hi_n_len = len << 4; | |
309 | ||
310 | put_unaligned_le32(addr, &tb->lo); | |
311 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
312 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
313 | ||
314 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
315 | ||
316 | tfd->num_tbs = idx + 1; | |
317 | } | |
318 | ||
319 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
320 | { | |
321 | return tfd->num_tbs & 0x1f; | |
322 | } | |
323 | ||
324 | /** | |
325 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
326 | * @priv - driver private data | |
327 | * @txq - tx queue | |
328 | * | |
329 | * Does NOT advance any TFD circular buffer read/write indexes | |
330 | * Does NOT free the TFD itself (which is within circular buffer) | |
331 | */ | |
332 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
333 | { | |
59606ffa | 334 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
335 | struct iwl_tfd *tfd; |
336 | struct pci_dev *dev = priv->pci_dev; | |
337 | int index = txq->q.read_ptr; | |
338 | int i; | |
339 | int num_tbs; | |
340 | ||
341 | tfd = &tfd_tmp[index]; | |
342 | ||
343 | /* Sanity check on number of chunks */ | |
344 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
345 | ||
346 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
347 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
348 | /* @todo issue fatal error, it is quite serious situation */ | |
349 | return; | |
350 | } | |
351 | ||
352 | /* Unmap tx_cmd */ | |
353 | if (num_tbs) | |
354 | pci_unmap_single(dev, | |
2e724443 FT |
355 | dma_unmap_addr(&txq->meta[index], mapping), |
356 | dma_unmap_len(&txq->meta[index], len), | |
96891cee | 357 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
358 | |
359 | /* Unmap chunks, if any. */ | |
ff0d91c3 | 360 | for (i = 1; i < num_tbs; i++) |
7aaa1d79 SO |
361 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), |
362 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
363 | ||
ff0d91c3 JB |
364 | /* free SKB */ |
365 | if (txq->txb) { | |
366 | struct sk_buff *skb; | |
6f80240e | 367 | |
ff0d91c3 | 368 | skb = txq->txb[txq->q.read_ptr].skb; |
6f80240e | 369 | |
ff0d91c3 JB |
370 | /* can be called from irqs-disabled context */ |
371 | if (skb) { | |
372 | dev_kfree_skb_any(skb); | |
373 | txq->txb[txq->q.read_ptr].skb = NULL; | |
7aaa1d79 SO |
374 | } |
375 | } | |
376 | } | |
377 | ||
378 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
379 | struct iwl_tx_queue *txq, | |
380 | dma_addr_t addr, u16 len, | |
381 | u8 reset, u8 pad) | |
382 | { | |
383 | struct iwl_queue *q; | |
59606ffa | 384 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
385 | u32 num_tbs; |
386 | ||
387 | q = &txq->q; | |
59606ffa SO |
388 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
389 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
390 | |
391 | if (reset) | |
392 | memset(tfd, 0, sizeof(*tfd)); | |
393 | ||
394 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
395 | ||
396 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
397 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
398 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
399 | IWL_NUM_OF_TBS); | |
400 | return -EINVAL; | |
401 | } | |
402 | ||
3e41ace5 JB |
403 | if (WARN_ON(addr & ~DMA_BIT_MASK(36))) |
404 | return -EINVAL; | |
405 | ||
7aaa1d79 SO |
406 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) |
407 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
408 | (unsigned long long)addr); | |
409 | ||
410 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
a8e74e27 SO |
415 | /* |
416 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
417 | * given Tx queue, and enable the DMA channel used for that queue. | |
418 | * | |
f7d046f9 | 419 | * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA |
a8e74e27 SO |
420 | * channels supported in hardware. |
421 | */ | |
422 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
423 | struct iwl_tx_queue *txq) | |
424 | { | |
a8e74e27 SO |
425 | int txq_id = txq->q.id; |
426 | ||
a8e74e27 SO |
427 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
428 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
429 | txq->q.dma_addr >> 8); | |
430 | ||
a8e74e27 SO |
431 | return 0; |
432 | } | |
433 | ||
5b9f8cd3 | 434 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 435 | { |
c79dd5b5 TW |
436 | struct iwl_priv *priv = |
437 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
438 | struct sk_buff *beacon; |
439 | ||
76d04815 JB |
440 | mutex_lock(&priv->mutex); |
441 | if (!priv->beacon_ctx) { | |
442 | IWL_ERR(priv, "updating beacon w/o beacon context!\n"); | |
443 | goto out; | |
444 | } | |
b481de9c | 445 | |
60744f62 JB |
446 | if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) { |
447 | /* | |
448 | * The ucode will send beacon notifications even in | |
449 | * IBSS mode, but we don't want to process them. But | |
450 | * we need to defer the type check to here due to | |
451 | * requiring locking around the beacon_ctx access. | |
452 | */ | |
453 | goto out; | |
454 | } | |
455 | ||
76d04815 JB |
456 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ |
457 | beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif); | |
b481de9c | 458 | if (!beacon) { |
77834543 | 459 | IWL_ERR(priv, "update beacon failed -- keeping old\n"); |
76d04815 | 460 | goto out; |
b481de9c ZY |
461 | } |
462 | ||
b481de9c | 463 | /* new beacon skb is allocated every time; dispose previous.*/ |
77834543 | 464 | dev_kfree_skb(priv->beacon_skb); |
b481de9c | 465 | |
12e934dc | 466 | priv->beacon_skb = beacon; |
b481de9c | 467 | |
2295c66b | 468 | iwlagn_send_beacon_cmd(priv); |
76d04815 JB |
469 | out: |
470 | mutex_unlock(&priv->mutex); | |
b481de9c ZY |
471 | } |
472 | ||
fbba9410 WYG |
473 | static void iwl_bg_bt_runtime_config(struct work_struct *work) |
474 | { | |
475 | struct iwl_priv *priv = | |
476 | container_of(work, struct iwl_priv, bt_runtime_config); | |
477 | ||
478 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
479 | return; | |
480 | ||
481 | /* dont send host command if rf-kill is on */ | |
482 | if (!iwl_is_ready_rf(priv)) | |
483 | return; | |
484 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
485 | } | |
486 | ||
bee008b7 WYG |
487 | static void iwl_bg_bt_full_concurrency(struct work_struct *work) |
488 | { | |
489 | struct iwl_priv *priv = | |
490 | container_of(work, struct iwl_priv, bt_full_concurrency); | |
246ed355 | 491 | struct iwl_rxon_context *ctx; |
bee008b7 | 492 | |
dc1a4068 SG |
493 | mutex_lock(&priv->mutex); |
494 | ||
bee008b7 | 495 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
dc1a4068 | 496 | goto out; |
bee008b7 WYG |
497 | |
498 | /* dont send host command if rf-kill is on */ | |
499 | if (!iwl_is_ready_rf(priv)) | |
dc1a4068 | 500 | goto out; |
bee008b7 WYG |
501 | |
502 | IWL_DEBUG_INFO(priv, "BT coex in %s mode\n", | |
503 | priv->bt_full_concurrent ? | |
504 | "full concurrency" : "3-wire"); | |
505 | ||
506 | /* | |
507 | * LQ & RXON updated cmds must be sent before BT Config cmd | |
508 | * to avoid 3-wire collisions | |
509 | */ | |
246ed355 JB |
510 | for_each_context(priv, ctx) { |
511 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
512 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
513 | iwlcore_commit_rxon(priv, ctx); | |
514 | } | |
bee008b7 WYG |
515 | |
516 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
dc1a4068 SG |
517 | out: |
518 | mutex_unlock(&priv->mutex); | |
bee008b7 WYG |
519 | } |
520 | ||
4e39317d | 521 | /** |
5b9f8cd3 | 522 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
523 | * |
524 | * This callback is provided in order to send a statistics request. | |
525 | * | |
526 | * This timer function is continually reset to execute within | |
527 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
528 | * was received. We need to ensure we receive the statistics in order | |
529 | * to update the temperature used for calibrating the TXPOWER. | |
530 | */ | |
5b9f8cd3 | 531 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
532 | { |
533 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
534 | ||
535 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
536 | return; | |
537 | ||
61780ee3 MA |
538 | /* dont send host command if rf-kill is on */ |
539 | if (!iwl_is_ready_rf(priv)) | |
540 | return; | |
541 | ||
ef8d5529 | 542 | iwl_send_statistics_request(priv, CMD_ASYNC, false); |
4e39317d EG |
543 | } |
544 | ||
a9e1cb6a WYG |
545 | |
546 | static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |
547 | u32 start_idx, u32 num_events, | |
548 | u32 mode) | |
549 | { | |
550 | u32 i; | |
551 | u32 ptr; /* SRAM byte address of log data */ | |
552 | u32 ev, time, data; /* event log data */ | |
553 | unsigned long reg_flags; | |
554 | ||
555 | if (mode == 0) | |
556 | ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); | |
557 | else | |
558 | ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); | |
559 | ||
560 | /* Make sure device is powered up for SRAM reads */ | |
561 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
562 | if (iwl_grab_nic_access(priv)) { | |
563 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
564 | return; | |
565 | } | |
566 | ||
567 | /* Set starting address; reads will auto-increment */ | |
02a7fa00 | 568 | iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr); |
a9e1cb6a WYG |
569 | rmb(); |
570 | ||
571 | /* | |
572 | * "time" is actually "data" for mode 0 (no timestamp). | |
573 | * place event id # at far right for easier visual parsing. | |
574 | */ | |
575 | for (i = 0; i < num_events; i++) { | |
02a7fa00 JB |
576 | ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
577 | time = iwl_read32(priv, HBUS_TARG_MEM_RDAT); | |
a9e1cb6a WYG |
578 | if (mode == 0) { |
579 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
580 | 0, time, ev); | |
581 | } else { | |
02a7fa00 | 582 | data = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
a9e1cb6a WYG |
583 | trace_iwlwifi_dev_ucode_cont_event(priv, |
584 | time, data, ev); | |
585 | } | |
586 | } | |
587 | /* Allow device to power down */ | |
588 | iwl_release_nic_access(priv); | |
589 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
590 | } | |
591 | ||
875295f1 | 592 | static void iwl_continuous_event_trace(struct iwl_priv *priv) |
a9e1cb6a WYG |
593 | { |
594 | u32 capacity; /* event log capacity in # entries */ | |
595 | u32 base; /* SRAM byte address of event log header */ | |
596 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
597 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
598 | u32 next_entry; /* index of next entry to be written by uCode */ | |
599 | ||
d7d5783c | 600 | base = priv->device_pointers.error_event_table; |
a9e1cb6a WYG |
601 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { |
602 | capacity = iwl_read_targ_mem(priv, base); | |
603 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
604 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
605 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
606 | } else | |
607 | return; | |
608 | ||
609 | if (num_wraps == priv->event_log.num_wraps) { | |
610 | iwl_print_cont_event_trace(priv, | |
611 | base, priv->event_log.next_entry, | |
612 | next_entry - priv->event_log.next_entry, | |
613 | mode); | |
614 | priv->event_log.non_wraps_count++; | |
615 | } else { | |
616 | if ((num_wraps - priv->event_log.num_wraps) > 1) | |
617 | priv->event_log.wraps_more_count++; | |
618 | else | |
619 | priv->event_log.wraps_once_count++; | |
620 | trace_iwlwifi_dev_ucode_wrap_event(priv, | |
621 | num_wraps - priv->event_log.num_wraps, | |
622 | next_entry, priv->event_log.next_entry); | |
623 | if (next_entry < priv->event_log.next_entry) { | |
624 | iwl_print_cont_event_trace(priv, base, | |
625 | priv->event_log.next_entry, | |
626 | capacity - priv->event_log.next_entry, | |
627 | mode); | |
628 | ||
629 | iwl_print_cont_event_trace(priv, base, 0, | |
630 | next_entry, mode); | |
631 | } else { | |
632 | iwl_print_cont_event_trace(priv, base, | |
633 | next_entry, capacity - next_entry, | |
634 | mode); | |
635 | ||
636 | iwl_print_cont_event_trace(priv, base, 0, | |
637 | next_entry, mode); | |
638 | } | |
639 | } | |
640 | priv->event_log.num_wraps = num_wraps; | |
641 | priv->event_log.next_entry = next_entry; | |
642 | } | |
643 | ||
644 | /** | |
645 | * iwl_bg_ucode_trace - Timer callback to log ucode event | |
646 | * | |
647 | * The timer is continually set to execute every | |
648 | * UCODE_TRACE_PERIOD milliseconds after the last timer expired | |
649 | * this function is to perform continuous uCode event logging operation | |
650 | * if enabled | |
651 | */ | |
652 | static void iwl_bg_ucode_trace(unsigned long data) | |
653 | { | |
654 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
655 | ||
656 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
657 | return; | |
658 | ||
659 | if (priv->event_log.ucode_trace) { | |
660 | iwl_continuous_event_trace(priv); | |
661 | /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */ | |
662 | mod_timer(&priv->ucode_trace, | |
663 | jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD)); | |
664 | } | |
665 | } | |
666 | ||
65550636 WYG |
667 | static void iwl_bg_tx_flush(struct work_struct *work) |
668 | { | |
669 | struct iwl_priv *priv = | |
670 | container_of(work, struct iwl_priv, tx_flush); | |
671 | ||
672 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
673 | return; | |
674 | ||
675 | /* do nothing if rf-kill is on */ | |
676 | if (!iwl_is_ready_rf(priv)) | |
677 | return; | |
678 | ||
679 | if (priv->cfg->ops->lib->txfifo_flush) { | |
680 | IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n"); | |
681 | iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL); | |
682 | } | |
683 | } | |
684 | ||
b481de9c | 685 | /** |
a55360e4 | 686 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
687 | * |
688 | * Uses the priv->rx_handlers callback function array to invoke | |
689 | * the appropriate handlers, including command responses, | |
690 | * frame-received notifications, and other notifications. | |
691 | */ | |
f945f108 | 692 | static void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 693 | { |
a55360e4 | 694 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 695 | struct iwl_rx_packet *pkt; |
a55360e4 | 696 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
697 | u32 r, i; |
698 | int reclaim; | |
699 | unsigned long flags; | |
5c0eef96 | 700 | u8 fill_rx = 0; |
d68ab680 | 701 | u32 count = 8; |
4752c93c | 702 | int total_empty; |
b481de9c | 703 | |
6440adb5 CB |
704 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
705 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 706 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
707 | i = rxq->read; |
708 | ||
709 | /* Rx interrupt, but nothing sent from uCode */ | |
710 | if (i == r) | |
e1623446 | 711 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 712 | |
4752c93c | 713 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 714 | total_empty = r - rxq->write_actual; |
4752c93c MA |
715 | if (total_empty < 0) |
716 | total_empty += RX_QUEUE_SIZE; | |
717 | ||
718 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
719 | fill_rx = 1; |
720 | ||
b481de9c | 721 | while (i != r) { |
f4989d9b JB |
722 | int len; |
723 | ||
b481de9c ZY |
724 | rxb = rxq->queue[i]; |
725 | ||
9fbab516 | 726 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
727 | * then a bug has been introduced in the queue refilling |
728 | * routines -- catch it here */ | |
3e41ace5 JB |
729 | if (WARN_ON(rxb == NULL)) { |
730 | i = (i + 1) & RX_QUEUE_MASK; | |
731 | continue; | |
732 | } | |
b481de9c ZY |
733 | |
734 | rxq->queue[i] = NULL; | |
735 | ||
2f301227 ZY |
736 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
737 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
738 | PCI_DMA_FROMDEVICE); | |
739 | pkt = rxb_addr(rxb); | |
b481de9c | 740 | |
f4989d9b JB |
741 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
742 | len += sizeof(u32); /* account for status word */ | |
743 | trace_iwlwifi_dev_rx(priv, pkt, len); | |
be1a71a1 | 744 | |
b481de9c ZY |
745 | /* Reclaim a command buffer only if this packet is a response |
746 | * to a (driver-originated) command. | |
747 | * If the packet (e.g. Rx frame) originated from uCode, | |
748 | * there is no command buffer to reclaim. | |
749 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
750 | * but apparently a few don't get set; catch them here. */ | |
751 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
752 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 753 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 754 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 755 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
756 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
757 | (pkt->hdr.cmd != REPLY_TX); | |
758 | ||
7194207c JB |
759 | /* |
760 | * Do the notification wait before RX handlers so | |
761 | * even if the RX handler consumes the RXB we have | |
762 | * access to it in the notification wait entry. | |
763 | */ | |
764 | if (!list_empty(&priv->_agn.notif_waits)) { | |
765 | struct iwl_notification_wait *w; | |
766 | ||
767 | spin_lock(&priv->_agn.notif_wait_lock); | |
768 | list_for_each_entry(w, &priv->_agn.notif_waits, list) { | |
769 | if (w->cmd == pkt->hdr.cmd) { | |
770 | w->triggered = true; | |
771 | if (w->fn) | |
09f18afe | 772 | w->fn(priv, pkt, w->fn_data); |
7194207c JB |
773 | } |
774 | } | |
775 | spin_unlock(&priv->_agn.notif_wait_lock); | |
776 | ||
777 | wake_up_all(&priv->_agn.notif_waitq); | |
778 | } | |
4613e72d CK |
779 | if (priv->pre_rx_handler) |
780 | priv->pre_rx_handler(priv, rxb); | |
7194207c | 781 | |
b481de9c ZY |
782 | /* Based on type of command response or notification, |
783 | * handle those that need handling via function in | |
5b9f8cd3 | 784 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 785 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 786 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 787 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
a83b9141 | 788 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 789 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
790 | } else { |
791 | /* No handling needed */ | |
e1623446 | 792 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
793 | "r %d i %d No handler needed for %s, 0x%02x\n", |
794 | r, i, get_cmd_string(pkt->hdr.cmd), | |
795 | pkt->hdr.cmd); | |
796 | } | |
797 | ||
29b1b268 ZY |
798 | /* |
799 | * XXX: After here, we should always check rxb->page | |
800 | * against NULL before touching it or its virtual | |
801 | * memory (pkt). Because some rx_handler might have | |
802 | * already taken or freed the pages. | |
803 | */ | |
804 | ||
b481de9c | 805 | if (reclaim) { |
2f301227 ZY |
806 | /* Invoke any callbacks, transfer the buffer to caller, |
807 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 808 | * as we reclaim the driver command queue */ |
29b1b268 | 809 | if (rxb->page) |
17b88929 | 810 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 811 | else |
39aadf8c | 812 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
813 | } |
814 | ||
7300515d ZY |
815 | /* Reuse the page if possible. For notification packets and |
816 | * SKBs that fail to Rx correctly, add them back into the | |
817 | * rx_free list for reuse later. */ | |
818 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 819 | if (rxb->page != NULL) { |
7300515d ZY |
820 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
821 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
822 | PCI_DMA_FROMDEVICE); | |
823 | list_add_tail(&rxb->list, &rxq->rx_free); | |
824 | rxq->free_count++; | |
825 | } else | |
826 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 827 | |
b481de9c | 828 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 829 | |
b481de9c | 830 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
831 | /* If there are a lot of unused frames, |
832 | * restock the Rx queue so ucode wont assert. */ | |
833 | if (fill_rx) { | |
834 | count++; | |
835 | if (count >= 8) { | |
7300515d | 836 | rxq->read = i; |
54b81550 | 837 | iwlagn_rx_replenish_now(priv); |
5c0eef96 MA |
838 | count = 0; |
839 | } | |
840 | } | |
b481de9c ZY |
841 | } |
842 | ||
843 | /* Backtrack one entry */ | |
7300515d | 844 | rxq->read = i; |
4752c93c | 845 | if (fill_rx) |
54b81550 | 846 | iwlagn_rx_replenish_now(priv); |
4752c93c | 847 | else |
54b81550 | 848 | iwlagn_rx_queue_restock(priv); |
a55360e4 | 849 | } |
a55360e4 | 850 | |
ef850d7c MA |
851 | /* tasklet for iwlagn interrupt */ |
852 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
853 | { | |
854 | u32 inta = 0; | |
855 | u32 handled = 0; | |
856 | unsigned long flags; | |
8756990f | 857 | u32 i; |
ef850d7c MA |
858 | #ifdef CONFIG_IWLWIFI_DEBUG |
859 | u32 inta_mask; | |
860 | #endif | |
861 | ||
862 | spin_lock_irqsave(&priv->lock, flags); | |
863 | ||
864 | /* Ack/clear/reset pending uCode interrupts. | |
865 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
866 | */ | |
48a6be6a SZ |
867 | /* There is a hardware bug in the interrupt mask function that some |
868 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
869 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
870 | * ICT interrupt handling mechanism has another bug that might cause | |
871 | * these unmasked interrupts fail to be detected. We workaround the | |
872 | * hardware bugs here by ACKing all the possible interrupts so that | |
873 | * interrupt coalescing can still be achieved. | |
874 | */ | |
4a35ecf8 | 875 | iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask); |
ef850d7c | 876 | |
a4c8b2a6 | 877 | inta = priv->_agn.inta; |
ef850d7c MA |
878 | |
879 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 880 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
881 | /* just for debug */ |
882 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
883 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
884 | inta, inta_mask); | |
885 | } | |
886 | #endif | |
2f301227 ZY |
887 | |
888 | spin_unlock_irqrestore(&priv->lock, flags); | |
889 | ||
a4c8b2a6 JB |
890 | /* saved interrupt in inta variable now we can reset priv->_agn.inta */ |
891 | priv->_agn.inta = 0; | |
ef850d7c MA |
892 | |
893 | /* Now service all interrupt bits discovered above. */ | |
894 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 895 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
896 | |
897 | /* Tell the device to stop sending interrupts */ | |
898 | iwl_disable_interrupts(priv); | |
899 | ||
900 | priv->isr_stats.hw++; | |
901 | iwl_irq_handle_error(priv); | |
902 | ||
903 | handled |= CSR_INT_BIT_HW_ERR; | |
904 | ||
ef850d7c MA |
905 | return; |
906 | } | |
907 | ||
908 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 909 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
910 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
911 | if (inta & CSR_INT_BIT_SCD) { | |
912 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
913 | "the frame/frames.\n"); | |
914 | priv->isr_stats.sch++; | |
915 | } | |
916 | ||
917 | /* Alive notification via Rx interrupt will do the real work */ | |
918 | if (inta & CSR_INT_BIT_ALIVE) { | |
919 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
920 | priv->isr_stats.alive++; | |
921 | } | |
922 | } | |
923 | #endif | |
924 | /* Safely ignore these bits for debug checks below */ | |
925 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
926 | ||
927 | /* HW RF KILL switch toggled */ | |
928 | if (inta & CSR_INT_BIT_RF_KILL) { | |
929 | int hw_rf_kill = 0; | |
930 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
931 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
932 | hw_rf_kill = 1; | |
933 | ||
4c423a2b | 934 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
935 | hw_rf_kill ? "disable radio" : "enable radio"); |
936 | ||
937 | priv->isr_stats.rfkill++; | |
938 | ||
939 | /* driver only loads ucode once setting the interface up. | |
940 | * the driver allows loading the ucode even if the radio | |
941 | * is killed. Hence update the killswitch state here. The | |
942 | * rfkill handler will care about restarting if needed. | |
943 | */ | |
944 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
945 | if (hw_rf_kill) | |
946 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
947 | else | |
948 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 949 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
950 | } |
951 | ||
952 | handled |= CSR_INT_BIT_RF_KILL; | |
953 | } | |
954 | ||
955 | /* Chip got too hot and stopped itself */ | |
956 | if (inta & CSR_INT_BIT_CT_KILL) { | |
957 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
958 | priv->isr_stats.ctkill++; | |
959 | handled |= CSR_INT_BIT_CT_KILL; | |
960 | } | |
961 | ||
962 | /* Error detected by uCode */ | |
963 | if (inta & CSR_INT_BIT_SW_ERR) { | |
964 | IWL_ERR(priv, "Microcode SW error detected. " | |
965 | " Restarting 0x%X.\n", inta); | |
966 | priv->isr_stats.sw++; | |
ef850d7c MA |
967 | iwl_irq_handle_error(priv); |
968 | handled |= CSR_INT_BIT_SW_ERR; | |
969 | } | |
970 | ||
971 | /* uCode wakes up after power-down sleep */ | |
972 | if (inta & CSR_INT_BIT_WAKEUP) { | |
973 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
974 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
8756990f BC |
975 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
976 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
ef850d7c MA |
977 | |
978 | priv->isr_stats.wakeup++; | |
979 | ||
980 | handled |= CSR_INT_BIT_WAKEUP; | |
981 | } | |
982 | ||
983 | /* All uCode command responses, including Tx command responses, | |
984 | * Rx "responses" (frame-received notification), and other | |
985 | * notifications from uCode come through here*/ | |
40cefda9 MA |
986 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
987 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 988 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
989 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
990 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
991 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
f7d046f9 | 992 | CSR_FH_INT_RX_MASK); |
40cefda9 MA |
993 | } |
994 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
995 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
996 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
997 | } | |
998 | /* Sending RX interrupt require many steps to be done in the | |
999 | * the device: | |
1000 | * 1- write interrupt to current index in ICT table. | |
1001 | * 2- dma RX frame. | |
1002 | * 3- update RX shared data to indicate last write index. | |
1003 | * 4- send interrupt. | |
1004 | * This could lead to RX race, driver could receive RX interrupt | |
74ba67ed BC |
1005 | * but the shared data changes does not reflect this; |
1006 | * periodic interrupt will detect any dangling Rx activity. | |
40cefda9 | 1007 | */ |
74ba67ed BC |
1008 | |
1009 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1010 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
40cefda9 | 1011 | CSR_INT_PERIODIC_DIS); |
ef850d7c | 1012 | iwl_rx_handle(priv); |
74ba67ed BC |
1013 | |
1014 | /* | |
1015 | * Enable periodic interrupt in 8 msec only if we received | |
1016 | * real RX interrupt (instead of just periodic int), to catch | |
1017 | * any dangling Rx interrupt. If it was just the periodic | |
1018 | * interrupt, there was no dangling Rx activity, and no need | |
1019 | * to extend the periodic interrupt; one-shot is enough. | |
1020 | */ | |
40cefda9 | 1021 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) |
74ba67ed | 1022 | iwl_write8(priv, CSR_INT_PERIODIC_REG, |
40cefda9 MA |
1023 | CSR_INT_PERIODIC_ENA); |
1024 | ||
ef850d7c | 1025 | priv->isr_stats.rx++; |
ef850d7c MA |
1026 | } |
1027 | ||
c72cd19f | 1028 | /* This "Tx" DMA channel is used only for loading uCode */ |
ef850d7c | 1029 | if (inta & CSR_INT_BIT_FH_TX) { |
f7d046f9 | 1030 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK); |
c72cd19f | 1031 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
ef850d7c MA |
1032 | priv->isr_stats.tx++; |
1033 | handled |= CSR_INT_BIT_FH_TX; | |
c72cd19f | 1034 | /* Wake up uCode load routine, now that load is complete */ |
ef850d7c MA |
1035 | priv->ucode_write_complete = 1; |
1036 | wake_up_interruptible(&priv->wait_command_queue); | |
1037 | } | |
1038 | ||
1039 | if (inta & ~handled) { | |
1040 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1041 | priv->isr_stats.unhandled++; | |
1042 | } | |
1043 | ||
40cefda9 | 1044 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1045 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1046 | inta & ~priv->inta_mask); |
ef850d7c MA |
1047 | } |
1048 | ||
ef850d7c | 1049 | /* Re-enable all interrupts */ |
62e45c14 | 1050 | /* only Re-enable if disabled by irq */ |
ef850d7c MA |
1051 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) |
1052 | iwl_enable_interrupts(priv); | |
3dd823e6 DF |
1053 | /* Re-enable RF_KILL if it occurred */ |
1054 | else if (handled & CSR_INT_BIT_RF_KILL) | |
1055 | iwl_enable_rfkill_int(priv); | |
ef850d7c MA |
1056 | } |
1057 | ||
7d47618a EG |
1058 | /***************************************************************************** |
1059 | * | |
1060 | * sysfs attributes | |
1061 | * | |
1062 | *****************************************************************************/ | |
1063 | ||
1064 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1065 | ||
1066 | /* | |
1067 | * The following adds a new attribute to the sysfs representation | |
1068 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) | |
1069 | * used for controlling the debug level. | |
1070 | * | |
1071 | * See the level definitions in iwl for details. | |
1072 | * | |
1073 | * The debug_level being managed using sysfs below is a per device debug | |
1074 | * level that is used instead of the global debug level if it (the per | |
1075 | * device debug level) is set. | |
1076 | */ | |
1077 | static ssize_t show_debug_level(struct device *d, | |
1078 | struct device_attribute *attr, char *buf) | |
1079 | { | |
1080 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1081 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
1082 | } | |
1083 | static ssize_t store_debug_level(struct device *d, | |
1084 | struct device_attribute *attr, | |
1085 | const char *buf, size_t count) | |
1086 | { | |
1087 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1088 | unsigned long val; | |
1089 | int ret; | |
1090 | ||
1091 | ret = strict_strtoul(buf, 0, &val); | |
1092 | if (ret) | |
1093 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); | |
1094 | else { | |
1095 | priv->debug_level = val; | |
1096 | if (iwl_alloc_traffic_mem(priv)) | |
1097 | IWL_ERR(priv, | |
1098 | "Not enough memory to generate traffic log\n"); | |
1099 | } | |
1100 | return strnlen(buf, count); | |
1101 | } | |
1102 | ||
1103 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
1104 | show_debug_level, store_debug_level); | |
1105 | ||
1106 | ||
1107 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
1108 | ||
1109 | ||
1110 | static ssize_t show_temperature(struct device *d, | |
1111 | struct device_attribute *attr, char *buf) | |
1112 | { | |
1113 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1114 | ||
1115 | if (!iwl_is_alive(priv)) | |
1116 | return -EAGAIN; | |
1117 | ||
1118 | return sprintf(buf, "%d\n", priv->temperature); | |
1119 | } | |
1120 | ||
1121 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
1122 | ||
1123 | static ssize_t show_tx_power(struct device *d, | |
1124 | struct device_attribute *attr, char *buf) | |
1125 | { | |
1126 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1127 | ||
1128 | if (!iwl_is_ready_rf(priv)) | |
1129 | return sprintf(buf, "off\n"); | |
1130 | else | |
1131 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
1132 | } | |
1133 | ||
1134 | static ssize_t store_tx_power(struct device *d, | |
1135 | struct device_attribute *attr, | |
1136 | const char *buf, size_t count) | |
1137 | { | |
1138 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1139 | unsigned long val; | |
1140 | int ret; | |
1141 | ||
1142 | ret = strict_strtoul(buf, 10, &val); | |
1143 | if (ret) | |
1144 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); | |
1145 | else { | |
1146 | ret = iwl_set_tx_power(priv, val, false); | |
1147 | if (ret) | |
1148 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
1149 | ret); | |
1150 | else | |
1151 | ret = count; | |
1152 | } | |
1153 | return ret; | |
1154 | } | |
1155 | ||
1156 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
1157 | ||
7d47618a EG |
1158 | static struct attribute *iwl_sysfs_entries[] = { |
1159 | &dev_attr_temperature.attr, | |
1160 | &dev_attr_tx_power.attr, | |
7d47618a EG |
1161 | #ifdef CONFIG_IWLWIFI_DEBUG |
1162 | &dev_attr_debug_level.attr, | |
1163 | #endif | |
1164 | NULL | |
1165 | }; | |
1166 | ||
1167 | static struct attribute_group iwl_attribute_group = { | |
1168 | .name = NULL, /* put in device directory */ | |
1169 | .attrs = iwl_sysfs_entries, | |
1170 | }; | |
1171 | ||
b481de9c ZY |
1172 | /****************************************************************************** |
1173 | * | |
1174 | * uCode download functions | |
1175 | * | |
1176 | ******************************************************************************/ | |
1177 | ||
dbf28e21 JB |
1178 | static void iwl_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc) |
1179 | { | |
1180 | if (desc->v_addr) | |
1181 | dma_free_coherent(&pci_dev->dev, desc->len, | |
1182 | desc->v_addr, desc->p_addr); | |
1183 | desc->v_addr = NULL; | |
1184 | desc->len = 0; | |
1185 | } | |
1186 | ||
1187 | static void iwl_free_fw_img(struct pci_dev *pci_dev, struct fw_img *img) | |
1188 | { | |
1189 | iwl_free_fw_desc(pci_dev, &img->code); | |
1190 | iwl_free_fw_desc(pci_dev, &img->data); | |
1191 | } | |
1192 | ||
1193 | static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc, | |
1194 | const void *data, size_t len) | |
1195 | { | |
1196 | if (!len) { | |
1197 | desc->v_addr = NULL; | |
1198 | return -EINVAL; | |
1199 | } | |
1200 | ||
1201 | desc->v_addr = dma_alloc_coherent(&pci_dev->dev, len, | |
1202 | &desc->p_addr, GFP_KERNEL); | |
1203 | if (!desc->v_addr) | |
1204 | return -ENOMEM; | |
1205 | desc->len = len; | |
1206 | memcpy(desc->v_addr, data, len); | |
1207 | return 0; | |
1208 | } | |
1209 | ||
5b9f8cd3 | 1210 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1211 | { |
dbf28e21 JB |
1212 | iwl_free_fw_img(priv->pci_dev, &priv->ucode_rt); |
1213 | iwl_free_fw_img(priv->pci_dev, &priv->ucode_init); | |
b481de9c ZY |
1214 | } |
1215 | ||
dd7a2509 JB |
1216 | struct iwlagn_ucode_capabilities { |
1217 | u32 max_probe_length; | |
6a822d06 | 1218 | u32 standard_phy_calibration_size; |
3997ff39 | 1219 | u32 flags; |
dd7a2509 | 1220 | }; |
edcdf8b2 | 1221 | |
b08dfd04 | 1222 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
dd7a2509 JB |
1223 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
1224 | struct iwlagn_ucode_capabilities *capa); | |
b08dfd04 | 1225 | |
39396085 JS |
1226 | #define UCODE_EXPERIMENTAL_INDEX 100 |
1227 | #define UCODE_EXPERIMENTAL_TAG "exp" | |
1228 | ||
b08dfd04 JB |
1229 | static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) |
1230 | { | |
1231 | const char *name_pre = priv->cfg->fw_name_pre; | |
39396085 | 1232 | char tag[8]; |
b08dfd04 | 1233 | |
39396085 JS |
1234 | if (first) { |
1235 | #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE | |
1236 | priv->fw_index = UCODE_EXPERIMENTAL_INDEX; | |
1237 | strcpy(tag, UCODE_EXPERIMENTAL_TAG); | |
1238 | } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) { | |
1239 | #endif | |
b08dfd04 | 1240 | priv->fw_index = priv->cfg->ucode_api_max; |
39396085 JS |
1241 | sprintf(tag, "%d", priv->fw_index); |
1242 | } else { | |
b08dfd04 | 1243 | priv->fw_index--; |
39396085 JS |
1244 | sprintf(tag, "%d", priv->fw_index); |
1245 | } | |
b08dfd04 JB |
1246 | |
1247 | if (priv->fw_index < priv->cfg->ucode_api_min) { | |
1248 | IWL_ERR(priv, "no suitable firmware found!\n"); | |
1249 | return -ENOENT; | |
1250 | } | |
1251 | ||
39396085 | 1252 | sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); |
b08dfd04 | 1253 | |
39396085 JS |
1254 | IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n", |
1255 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
1256 | ? "EXPERIMENTAL " : "", | |
b08dfd04 JB |
1257 | priv->firmware_name); |
1258 | ||
1259 | return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, | |
1260 | &priv->pci_dev->dev, GFP_KERNEL, priv, | |
1261 | iwl_ucode_callback); | |
1262 | } | |
1263 | ||
0e9a44dc | 1264 | struct iwlagn_firmware_pieces { |
1fc35276 JB |
1265 | const void *inst, *data, *init, *init_data; |
1266 | size_t inst_size, data_size, init_size, init_data_size; | |
0e9a44dc JB |
1267 | |
1268 | u32 build; | |
b2e640d4 JB |
1269 | |
1270 | u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; | |
1271 | u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; | |
0e9a44dc JB |
1272 | }; |
1273 | ||
1274 | static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |
1275 | const struct firmware *ucode_raw, | |
1276 | struct iwlagn_firmware_pieces *pieces) | |
1277 | { | |
1278 | struct iwl_ucode_header *ucode = (void *)ucode_raw->data; | |
1279 | u32 api_ver, hdr_size; | |
1280 | const u8 *src; | |
1281 | ||
1282 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1283 | api_ver = IWL_UCODE_API(priv->ucode_ver); | |
1284 | ||
1285 | switch (api_ver) { | |
1286 | default: | |
f7d046f9 WYG |
1287 | hdr_size = 28; |
1288 | if (ucode_raw->size < hdr_size) { | |
1289 | IWL_ERR(priv, "File size too small!\n"); | |
1290 | return -EINVAL; | |
0e9a44dc | 1291 | } |
f7d046f9 WYG |
1292 | pieces->build = le32_to_cpu(ucode->u.v2.build); |
1293 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | |
1294 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | |
1295 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | |
1296 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | |
f7d046f9 WYG |
1297 | src = ucode->u.v2.data; |
1298 | break; | |
0e9a44dc JB |
1299 | case 0: |
1300 | case 1: | |
1301 | case 2: | |
1302 | hdr_size = 24; | |
1303 | if (ucode_raw->size < hdr_size) { | |
1304 | IWL_ERR(priv, "File size too small!\n"); | |
1305 | return -EINVAL; | |
1306 | } | |
1307 | pieces->build = 0; | |
1308 | pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size); | |
1309 | pieces->data_size = le32_to_cpu(ucode->u.v1.data_size); | |
1310 | pieces->init_size = le32_to_cpu(ucode->u.v1.init_size); | |
1311 | pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size); | |
0e9a44dc JB |
1312 | src = ucode->u.v1.data; |
1313 | break; | |
1314 | } | |
1315 | ||
1316 | /* Verify size of file vs. image size info in file's header */ | |
1317 | if (ucode_raw->size != hdr_size + pieces->inst_size + | |
1318 | pieces->data_size + pieces->init_size + | |
1fc35276 | 1319 | pieces->init_data_size) { |
0e9a44dc JB |
1320 | |
1321 | IWL_ERR(priv, | |
1322 | "uCode file size %d does not match expected size\n", | |
1323 | (int)ucode_raw->size); | |
1324 | return -EINVAL; | |
1325 | } | |
1326 | ||
1327 | pieces->inst = src; | |
1328 | src += pieces->inst_size; | |
1329 | pieces->data = src; | |
1330 | src += pieces->data_size; | |
1331 | pieces->init = src; | |
1332 | src += pieces->init_size; | |
1333 | pieces->init_data = src; | |
1334 | src += pieces->init_data_size; | |
0e9a44dc JB |
1335 | |
1336 | return 0; | |
1337 | } | |
1338 | ||
dd7a2509 JB |
1339 | static int iwlagn_wanted_ucode_alternative = 1; |
1340 | ||
1341 | static int iwlagn_load_firmware(struct iwl_priv *priv, | |
1342 | const struct firmware *ucode_raw, | |
1343 | struct iwlagn_firmware_pieces *pieces, | |
1344 | struct iwlagn_ucode_capabilities *capa) | |
1345 | { | |
1346 | struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data; | |
1347 | struct iwl_ucode_tlv *tlv; | |
1348 | size_t len = ucode_raw->size; | |
1349 | const u8 *data; | |
1350 | int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp; | |
1351 | u64 alternatives; | |
ad8d8333 WYG |
1352 | u32 tlv_len; |
1353 | enum iwl_ucode_tlv_type tlv_type; | |
1354 | const u8 *tlv_data; | |
dd7a2509 | 1355 | |
ad8d8333 WYG |
1356 | if (len < sizeof(*ucode)) { |
1357 | IWL_ERR(priv, "uCode has invalid length: %zd\n", len); | |
dd7a2509 | 1358 | return -EINVAL; |
ad8d8333 | 1359 | } |
dd7a2509 | 1360 | |
ad8d8333 WYG |
1361 | if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) { |
1362 | IWL_ERR(priv, "invalid uCode magic: 0X%x\n", | |
1363 | le32_to_cpu(ucode->magic)); | |
dd7a2509 | 1364 | return -EINVAL; |
ad8d8333 | 1365 | } |
dd7a2509 JB |
1366 | |
1367 | /* | |
1368 | * Check which alternatives are present, and "downgrade" | |
1369 | * when the chosen alternative is not present, warning | |
1370 | * the user when that happens. Some files may not have | |
1371 | * any alternatives, so don't warn in that case. | |
1372 | */ | |
1373 | alternatives = le64_to_cpu(ucode->alternatives); | |
1374 | tmp = wanted_alternative; | |
1375 | if (wanted_alternative > 63) | |
1376 | wanted_alternative = 63; | |
1377 | while (wanted_alternative && !(alternatives & BIT(wanted_alternative))) | |
1378 | wanted_alternative--; | |
1379 | if (wanted_alternative && wanted_alternative != tmp) | |
1380 | IWL_WARN(priv, | |
1381 | "uCode alternative %d not available, choosing %d\n", | |
1382 | tmp, wanted_alternative); | |
1383 | ||
1384 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1385 | pieces->build = le32_to_cpu(ucode->build); | |
1386 | data = ucode->data; | |
1387 | ||
1388 | len -= sizeof(*ucode); | |
1389 | ||
704da534 | 1390 | while (len >= sizeof(*tlv)) { |
dd7a2509 | 1391 | u16 tlv_alt; |
dd7a2509 JB |
1392 | |
1393 | len -= sizeof(*tlv); | |
1394 | tlv = (void *)data; | |
1395 | ||
1396 | tlv_len = le32_to_cpu(tlv->length); | |
1397 | tlv_type = le16_to_cpu(tlv->type); | |
1398 | tlv_alt = le16_to_cpu(tlv->alternative); | |
1399 | tlv_data = tlv->data; | |
1400 | ||
ad8d8333 WYG |
1401 | if (len < tlv_len) { |
1402 | IWL_ERR(priv, "invalid TLV len: %zd/%u\n", | |
1403 | len, tlv_len); | |
dd7a2509 | 1404 | return -EINVAL; |
ad8d8333 | 1405 | } |
dd7a2509 JB |
1406 | len -= ALIGN(tlv_len, 4); |
1407 | data += sizeof(*tlv) + ALIGN(tlv_len, 4); | |
1408 | ||
1409 | /* | |
1410 | * Alternative 0 is always valid. | |
1411 | * | |
1412 | * Skip alternative TLVs that are not selected. | |
1413 | */ | |
1414 | if (tlv_alt != 0 && tlv_alt != wanted_alternative) | |
1415 | continue; | |
1416 | ||
1417 | switch (tlv_type) { | |
1418 | case IWL_UCODE_TLV_INST: | |
1419 | pieces->inst = tlv_data; | |
1420 | pieces->inst_size = tlv_len; | |
1421 | break; | |
1422 | case IWL_UCODE_TLV_DATA: | |
1423 | pieces->data = tlv_data; | |
1424 | pieces->data_size = tlv_len; | |
1425 | break; | |
1426 | case IWL_UCODE_TLV_INIT: | |
1427 | pieces->init = tlv_data; | |
1428 | pieces->init_size = tlv_len; | |
1429 | break; | |
1430 | case IWL_UCODE_TLV_INIT_DATA: | |
1431 | pieces->init_data = tlv_data; | |
1432 | pieces->init_data_size = tlv_len; | |
1433 | break; | |
1434 | case IWL_UCODE_TLV_BOOT: | |
1fc35276 | 1435 | IWL_ERR(priv, "Found unexpected BOOT ucode\n"); |
dd7a2509 JB |
1436 | break; |
1437 | case IWL_UCODE_TLV_PROBE_MAX_LEN: | |
704da534 JB |
1438 | if (tlv_len != sizeof(u32)) |
1439 | goto invalid_tlv_len; | |
1440 | capa->max_probe_length = | |
ad8d8333 | 1441 | le32_to_cpup((__le32 *)tlv_data); |
dd7a2509 | 1442 | break; |
ece9c4ee JB |
1443 | case IWL_UCODE_TLV_PAN: |
1444 | if (tlv_len) | |
1445 | goto invalid_tlv_len; | |
3997ff39 JB |
1446 | capa->flags |= IWL_UCODE_TLV_FLAGS_PAN; |
1447 | break; | |
1448 | case IWL_UCODE_TLV_FLAGS: | |
1449 | /* must be at least one u32 */ | |
1450 | if (tlv_len < sizeof(u32)) | |
1451 | goto invalid_tlv_len; | |
1452 | /* and a proper number of u32s */ | |
1453 | if (tlv_len % sizeof(u32)) | |
1454 | goto invalid_tlv_len; | |
1455 | /* | |
1456 | * This driver only reads the first u32 as | |
1457 | * right now no more features are defined, | |
1458 | * if that changes then either the driver | |
1459 | * will not work with the new firmware, or | |
1460 | * it'll not take advantage of new features. | |
1461 | */ | |
1462 | capa->flags = le32_to_cpup((__le32 *)tlv_data); | |
ece9c4ee | 1463 | break; |
b2e640d4 | 1464 | case IWL_UCODE_TLV_INIT_EVTLOG_PTR: |
704da534 JB |
1465 | if (tlv_len != sizeof(u32)) |
1466 | goto invalid_tlv_len; | |
1467 | pieces->init_evtlog_ptr = | |
ad8d8333 | 1468 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1469 | break; |
1470 | case IWL_UCODE_TLV_INIT_EVTLOG_SIZE: | |
704da534 JB |
1471 | if (tlv_len != sizeof(u32)) |
1472 | goto invalid_tlv_len; | |
1473 | pieces->init_evtlog_size = | |
ad8d8333 | 1474 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1475 | break; |
1476 | case IWL_UCODE_TLV_INIT_ERRLOG_PTR: | |
704da534 JB |
1477 | if (tlv_len != sizeof(u32)) |
1478 | goto invalid_tlv_len; | |
1479 | pieces->init_errlog_ptr = | |
ad8d8333 | 1480 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1481 | break; |
1482 | case IWL_UCODE_TLV_RUNT_EVTLOG_PTR: | |
704da534 JB |
1483 | if (tlv_len != sizeof(u32)) |
1484 | goto invalid_tlv_len; | |
1485 | pieces->inst_evtlog_ptr = | |
ad8d8333 | 1486 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1487 | break; |
1488 | case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE: | |
704da534 JB |
1489 | if (tlv_len != sizeof(u32)) |
1490 | goto invalid_tlv_len; | |
1491 | pieces->inst_evtlog_size = | |
ad8d8333 | 1492 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1493 | break; |
1494 | case IWL_UCODE_TLV_RUNT_ERRLOG_PTR: | |
704da534 JB |
1495 | if (tlv_len != sizeof(u32)) |
1496 | goto invalid_tlv_len; | |
1497 | pieces->inst_errlog_ptr = | |
ad8d8333 | 1498 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 | 1499 | break; |
c8312fac WYG |
1500 | case IWL_UCODE_TLV_ENHANCE_SENS_TBL: |
1501 | if (tlv_len) | |
704da534 JB |
1502 | goto invalid_tlv_len; |
1503 | priv->enhance_sensitivity_table = true; | |
c8312fac | 1504 | break; |
6a822d06 | 1505 | case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE: |
704da534 JB |
1506 | if (tlv_len != sizeof(u32)) |
1507 | goto invalid_tlv_len; | |
1508 | capa->standard_phy_calibration_size = | |
6a822d06 WYG |
1509 | le32_to_cpup((__le32 *)tlv_data); |
1510 | break; | |
dd7a2509 | 1511 | default: |
6fc3ba99 | 1512 | IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type); |
dd7a2509 JB |
1513 | break; |
1514 | } | |
1515 | } | |
1516 | ||
ad8d8333 WYG |
1517 | if (len) { |
1518 | IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len); | |
1519 | iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len); | |
704da534 | 1520 | return -EINVAL; |
ad8d8333 | 1521 | } |
dd7a2509 | 1522 | |
704da534 JB |
1523 | return 0; |
1524 | ||
1525 | invalid_tlv_len: | |
1526 | IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len); | |
1527 | iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len); | |
1528 | ||
1529 | return -EINVAL; | |
dd7a2509 JB |
1530 | } |
1531 | ||
b481de9c | 1532 | /** |
b08dfd04 | 1533 | * iwl_ucode_callback - callback when firmware was loaded |
b481de9c | 1534 | * |
b08dfd04 JB |
1535 | * If loaded successfully, copies the firmware into buffers |
1536 | * for the card to fetch (via DMA). | |
b481de9c | 1537 | */ |
b08dfd04 | 1538 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) |
b481de9c | 1539 | { |
b08dfd04 | 1540 | struct iwl_priv *priv = context; |
cc0f555d | 1541 | struct iwl_ucode_header *ucode; |
0e9a44dc JB |
1542 | int err; |
1543 | struct iwlagn_firmware_pieces pieces; | |
a0987a8d RC |
1544 | const unsigned int api_max = priv->cfg->ucode_api_max; |
1545 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
0e9a44dc | 1546 | u32 api_ver; |
3e4de761 | 1547 | char buildstr[25]; |
0e9a44dc | 1548 | u32 build; |
dd7a2509 JB |
1549 | struct iwlagn_ucode_capabilities ucode_capa = { |
1550 | .max_probe_length = 200, | |
6a822d06 | 1551 | .standard_phy_calibration_size = |
642454cc | 1552 | IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE, |
dd7a2509 | 1553 | }; |
0e9a44dc JB |
1554 | |
1555 | memset(&pieces, 0, sizeof(pieces)); | |
b481de9c | 1556 | |
b08dfd04 | 1557 | if (!ucode_raw) { |
39396085 JS |
1558 | if (priv->fw_index <= priv->cfg->ucode_api_max) |
1559 | IWL_ERR(priv, | |
1560 | "request for firmware file '%s' failed.\n", | |
1561 | priv->firmware_name); | |
b08dfd04 | 1562 | goto try_again; |
b481de9c ZY |
1563 | } |
1564 | ||
b08dfd04 JB |
1565 | IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", |
1566 | priv->firmware_name, ucode_raw->size); | |
b481de9c | 1567 | |
22adba2a JB |
1568 | /* Make sure that we got at least the API version number */ |
1569 | if (ucode_raw->size < 4) { | |
15b1687c | 1570 | IWL_ERR(priv, "File size way too small!\n"); |
b08dfd04 | 1571 | goto try_again; |
b481de9c ZY |
1572 | } |
1573 | ||
1574 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1575 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1576 | |
0e9a44dc JB |
1577 | if (ucode->ver) |
1578 | err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces); | |
1579 | else | |
dd7a2509 JB |
1580 | err = iwlagn_load_firmware(priv, ucode_raw, &pieces, |
1581 | &ucode_capa); | |
22adba2a | 1582 | |
0e9a44dc JB |
1583 | if (err) |
1584 | goto try_again; | |
b481de9c | 1585 | |
a0987a8d | 1586 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
0e9a44dc | 1587 | build = pieces.build; |
a0987a8d | 1588 | |
0e9a44dc JB |
1589 | /* |
1590 | * api_ver should match the api version forming part of the | |
1591 | * firmware filename ... but we don't check for that and only rely | |
1592 | * on the API version read from firmware header from here on forward | |
1593 | */ | |
65cccfb0 WYG |
1594 | /* no api version check required for experimental uCode */ |
1595 | if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) { | |
1596 | if (api_ver < api_min || api_ver > api_max) { | |
1597 | IWL_ERR(priv, | |
1598 | "Driver unable to support your firmware API. " | |
1599 | "Driver supports v%u, firmware is v%u.\n", | |
1600 | api_max, api_ver); | |
1601 | goto try_again; | |
1602 | } | |
b08dfd04 | 1603 | |
65cccfb0 WYG |
1604 | if (api_ver != api_max) |
1605 | IWL_ERR(priv, | |
1606 | "Firmware has old API version. Expected v%u, " | |
1607 | "got v%u. New firmware can be obtained " | |
1608 | "from http://www.intellinuxwireless.org.\n", | |
1609 | api_max, api_ver); | |
1610 | } | |
a0987a8d | 1611 | |
3e4de761 | 1612 | if (build) |
39396085 JS |
1613 | sprintf(buildstr, " build %u%s", build, |
1614 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
1615 | ? " (EXP)" : ""); | |
3e4de761 JB |
1616 | else |
1617 | buildstr[0] = '\0'; | |
1618 | ||
1619 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n", | |
1620 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1621 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1622 | IWL_UCODE_API(priv->ucode_ver), | |
1623 | IWL_UCODE_SERIAL(priv->ucode_ver), | |
1624 | buildstr); | |
a0987a8d | 1625 | |
5ebeb5a6 RC |
1626 | snprintf(priv->hw->wiphy->fw_version, |
1627 | sizeof(priv->hw->wiphy->fw_version), | |
3e4de761 | 1628 | "%u.%u.%u.%u%s", |
5ebeb5a6 RC |
1629 | IWL_UCODE_MAJOR(priv->ucode_ver), |
1630 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1631 | IWL_UCODE_API(priv->ucode_ver), | |
3e4de761 JB |
1632 | IWL_UCODE_SERIAL(priv->ucode_ver), |
1633 | buildstr); | |
b481de9c | 1634 | |
b08dfd04 JB |
1635 | /* |
1636 | * For any of the failures below (before allocating pci memory) | |
1637 | * we will try to load a version with a smaller API -- maybe the | |
1638 | * user just got a corrupted version of the latest API. | |
1639 | */ | |
1640 | ||
0e9a44dc JB |
1641 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
1642 | priv->ucode_ver); | |
1643 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n", | |
1644 | pieces.inst_size); | |
1645 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n", | |
1646 | pieces.data_size); | |
1647 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n", | |
1648 | pieces.init_size); | |
1649 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n", | |
1650 | pieces.init_data_size); | |
b481de9c ZY |
1651 | |
1652 | /* Verify that uCode images will fit in card's SRAM */ | |
0e9a44dc JB |
1653 | if (pieces.inst_size > priv->hw_params.max_inst_size) { |
1654 | IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n", | |
1655 | pieces.inst_size); | |
b08dfd04 | 1656 | goto try_again; |
b481de9c ZY |
1657 | } |
1658 | ||
0e9a44dc JB |
1659 | if (pieces.data_size > priv->hw_params.max_data_size) { |
1660 | IWL_ERR(priv, "uCode data len %Zd too large to fit in\n", | |
1661 | pieces.data_size); | |
b08dfd04 | 1662 | goto try_again; |
b481de9c | 1663 | } |
0e9a44dc JB |
1664 | |
1665 | if (pieces.init_size > priv->hw_params.max_inst_size) { | |
1666 | IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n", | |
1667 | pieces.init_size); | |
b08dfd04 | 1668 | goto try_again; |
b481de9c | 1669 | } |
0e9a44dc JB |
1670 | |
1671 | if (pieces.init_data_size > priv->hw_params.max_data_size) { | |
1672 | IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n", | |
1673 | pieces.init_data_size); | |
b08dfd04 | 1674 | goto try_again; |
b481de9c | 1675 | } |
0e9a44dc | 1676 | |
b481de9c ZY |
1677 | /* Allocate ucode buffers for card's bus-master loading ... */ |
1678 | ||
1679 | /* Runtime instructions and 2 copies of data: | |
1680 | * 1) unmodified from disk | |
1681 | * 2) backup cache for save/restore during power-downs */ | |
dbf28e21 JB |
1682 | if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.code, |
1683 | pieces.inst, pieces.inst_size)) | |
1684 | goto err_pci_alloc; | |
1685 | if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.data, | |
1686 | pieces.data, pieces.data_size)) | |
1f304e4e ZY |
1687 | goto err_pci_alloc; |
1688 | ||
b481de9c | 1689 | /* Initialization instructions and data */ |
0e9a44dc | 1690 | if (pieces.init_size && pieces.init_data_size) { |
dbf28e21 JB |
1691 | if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.code, |
1692 | pieces.init, pieces.init_size)) | |
1693 | goto err_pci_alloc; | |
1694 | if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.data, | |
1695 | pieces.init_data, pieces.init_data_size)) | |
90e759d1 TW |
1696 | goto err_pci_alloc; |
1697 | } | |
b481de9c | 1698 | |
b2e640d4 JB |
1699 | /* Now that we can no longer fail, copy information */ |
1700 | ||
1701 | /* | |
1702 | * The (size - 16) / 12 formula is based on the information recorded | |
1703 | * for each event, which is of mode 1 (including timestamp) for all | |
1704 | * new microcodes that include this information. | |
1705 | */ | |
1706 | priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr; | |
1707 | if (pieces.init_evtlog_size) | |
1708 | priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12; | |
1709 | else | |
7cb1b088 WYG |
1710 | priv->_agn.init_evtlog_size = |
1711 | priv->cfg->base_params->max_event_log_size; | |
b2e640d4 JB |
1712 | priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr; |
1713 | priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr; | |
1714 | if (pieces.inst_evtlog_size) | |
1715 | priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12; | |
1716 | else | |
7cb1b088 WYG |
1717 | priv->_agn.inst_evtlog_size = |
1718 | priv->cfg->base_params->max_event_log_size; | |
b2e640d4 JB |
1719 | priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; |
1720 | ||
d2690c0d JB |
1721 | priv->new_scan_threshold_behaviour = |
1722 | !!(ucode_capa.flags & IWL_UCODE_TLV_FLAGS_NEWSCAN); | |
1723 | ||
3997ff39 | 1724 | if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) { |
ece9c4ee | 1725 | priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN); |
c10afb6e | 1726 | priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN; |
ece9c4ee JB |
1727 | } else |
1728 | priv->sta_key_max_num = STA_KEY_MAX_NUM; | |
c10afb6e | 1729 | |
17445b8c JB |
1730 | if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
1731 | priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM; | |
1732 | else | |
1733 | priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM; | |
1734 | ||
6a822d06 WYG |
1735 | /* |
1736 | * figure out the offset of chain noise reset and gain commands | |
1737 | * base on the size of standard phy calibration commands table size | |
1738 | */ | |
1739 | if (ucode_capa.standard_phy_calibration_size > | |
1740 | IWL_MAX_PHY_CALIBRATE_TBL_SIZE) | |
1741 | ucode_capa.standard_phy_calibration_size = | |
1742 | IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE; | |
1743 | ||
1744 | priv->_agn.phy_calib_chain_noise_reset_cmd = | |
1745 | ucode_capa.standard_phy_calibration_size; | |
1746 | priv->_agn.phy_calib_chain_noise_gain_cmd = | |
1747 | ucode_capa.standard_phy_calibration_size + 1; | |
1748 | ||
b08dfd04 JB |
1749 | /************************************************** |
1750 | * This is still part of probe() in a sense... | |
1751 | * | |
1752 | * 9. Setup and register with mac80211 and debugfs | |
1753 | **************************************************/ | |
dd7a2509 | 1754 | err = iwl_mac_setup_register(priv, &ucode_capa); |
b08dfd04 JB |
1755 | if (err) |
1756 | goto out_unbind; | |
1757 | ||
1758 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
1759 | if (err) | |
1760 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
1761 | ||
7d47618a EG |
1762 | err = sysfs_create_group(&priv->pci_dev->dev.kobj, |
1763 | &iwl_attribute_group); | |
1764 | if (err) { | |
1765 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); | |
1766 | goto out_unbind; | |
1767 | } | |
1768 | ||
b481de9c ZY |
1769 | /* We have our copies now, allow OS release its copies */ |
1770 | release_firmware(ucode_raw); | |
a15707d8 | 1771 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 JB |
1772 | return; |
1773 | ||
1774 | try_again: | |
1775 | /* try next, if any */ | |
1776 | if (iwl_request_firmware(priv, false)) | |
1777 | goto out_unbind; | |
1778 | release_firmware(ucode_raw); | |
1779 | return; | |
b481de9c ZY |
1780 | |
1781 | err_pci_alloc: | |
15b1687c | 1782 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
5b9f8cd3 | 1783 | iwl_dealloc_ucode_pci(priv); |
b08dfd04 | 1784 | out_unbind: |
a15707d8 | 1785 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 | 1786 | device_release_driver(&priv->pci_dev->dev); |
b481de9c | 1787 | release_firmware(ucode_raw); |
b481de9c ZY |
1788 | } |
1789 | ||
b7a79404 RC |
1790 | static const char *desc_lookup_text[] = { |
1791 | "OK", | |
1792 | "FAIL", | |
1793 | "BAD_PARAM", | |
1794 | "BAD_CHECKSUM", | |
1795 | "NMI_INTERRUPT_WDG", | |
1796 | "SYSASSERT", | |
1797 | "FATAL_ERROR", | |
1798 | "BAD_COMMAND", | |
1799 | "HW_ERROR_TUNE_LOCK", | |
1800 | "HW_ERROR_TEMPERATURE", | |
1801 | "ILLEGAL_CHAN_FREQ", | |
1802 | "VCC_NOT_STABLE", | |
1803 | "FH_ERROR", | |
1804 | "NMI_INTERRUPT_HOST", | |
1805 | "NMI_INTERRUPT_ACTION_PT", | |
1806 | "NMI_INTERRUPT_UNKNOWN", | |
1807 | "UCODE_VERSION_MISMATCH", | |
1808 | "HW_ERROR_ABS_LOCK", | |
1809 | "HW_ERROR_CAL_LOCK_FAIL", | |
1810 | "NMI_INTERRUPT_INST_ACTION_PT", | |
1811 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
1812 | "NMI_TRM_HW_ER", | |
1813 | "NMI_INTERRUPT_TRM", | |
1814 | "NMI_INTERRUPT_BREAK_POINT" | |
1815 | "DEBUG_0", | |
1816 | "DEBUG_1", | |
1817 | "DEBUG_2", | |
1818 | "DEBUG_3", | |
b7a79404 RC |
1819 | }; |
1820 | ||
4b58645c JS |
1821 | static struct { char *name; u8 num; } advanced_lookup[] = { |
1822 | { "NMI_INTERRUPT_WDG", 0x34 }, | |
1823 | { "SYSASSERT", 0x35 }, | |
1824 | { "UCODE_VERSION_MISMATCH", 0x37 }, | |
1825 | { "BAD_COMMAND", 0x38 }, | |
1826 | { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, | |
1827 | { "FATAL_ERROR", 0x3D }, | |
1828 | { "NMI_TRM_HW_ERR", 0x46 }, | |
1829 | { "NMI_INTERRUPT_TRM", 0x4C }, | |
1830 | { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, | |
1831 | { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, | |
1832 | { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, | |
1833 | { "NMI_INTERRUPT_HOST", 0x66 }, | |
1834 | { "NMI_INTERRUPT_ACTION_PT", 0x7C }, | |
1835 | { "NMI_INTERRUPT_UNKNOWN", 0x84 }, | |
1836 | { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, | |
1837 | { "ADVANCED_SYSASSERT", 0 }, | |
1838 | }; | |
1839 | ||
1840 | static const char *desc_lookup(u32 num) | |
b7a79404 | 1841 | { |
4b58645c JS |
1842 | int i; |
1843 | int max = ARRAY_SIZE(desc_lookup_text); | |
b7a79404 | 1844 | |
4b58645c JS |
1845 | if (num < max) |
1846 | return desc_lookup_text[num]; | |
b7a79404 | 1847 | |
4b58645c JS |
1848 | max = ARRAY_SIZE(advanced_lookup) - 1; |
1849 | for (i = 0; i < max; i++) { | |
1850 | if (advanced_lookup[i].num == num) | |
1851 | break;; | |
1852 | } | |
1853 | return advanced_lookup[i].name; | |
b7a79404 RC |
1854 | } |
1855 | ||
1856 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
1857 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
1858 | ||
1859 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
1860 | { | |
1861 | u32 data2, line; | |
1862 | u32 desc, time, count, base, data1; | |
1863 | u32 blink1, blink2, ilink1, ilink2; | |
461ef382 | 1864 | u32 pc, hcmd; |
e46f6538 | 1865 | struct iwl_error_event_table table; |
b7a79404 | 1866 | |
d7d5783c | 1867 | base = priv->device_pointers.error_event_table; |
ca7966c8 | 1868 | if (priv->ucode_type == UCODE_SUBTYPE_INIT) { |
b2e640d4 JB |
1869 | if (!base) |
1870 | base = priv->_agn.init_errlog_ptr; | |
1871 | } else { | |
b2e640d4 JB |
1872 | if (!base) |
1873 | base = priv->_agn.inst_errlog_ptr; | |
1874 | } | |
b7a79404 RC |
1875 | |
1876 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
1877 | IWL_ERR(priv, |
1878 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
ca7966c8 JB |
1879 | base, |
1880 | (priv->ucode_type == UCODE_SUBTYPE_INIT) | |
1881 | ? "Init" : "RT"); | |
b7a79404 RC |
1882 | return; |
1883 | } | |
1884 | ||
e46f6538 JB |
1885 | iwl_read_targ_mem_words(priv, base, &table, sizeof(table)); |
1886 | ||
1887 | count = table.valid; | |
b7a79404 RC |
1888 | |
1889 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
1890 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
1891 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
1892 | priv->status, count); | |
1893 | } | |
1894 | ||
e46f6538 | 1895 | desc = table.error_id; |
6e6ebf4b | 1896 | priv->isr_stats.err_code = desc; |
e46f6538 JB |
1897 | pc = table.pc; |
1898 | blink1 = table.blink1; | |
1899 | blink2 = table.blink2; | |
1900 | ilink1 = table.ilink1; | |
1901 | ilink2 = table.ilink2; | |
1902 | data1 = table.data1; | |
1903 | data2 = table.data2; | |
1904 | line = table.line; | |
1905 | time = table.tsf_low; | |
1906 | hcmd = table.hcmd; | |
b7a79404 | 1907 | |
be1a71a1 JB |
1908 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line, |
1909 | blink1, blink2, ilink1, ilink2); | |
1910 | ||
87563715 | 1911 | IWL_ERR(priv, "Desc Time " |
b7a79404 | 1912 | "data1 data2 line\n"); |
87563715 | 1913 | IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", |
b7a79404 | 1914 | desc_lookup(desc), desc, time, data1, data2, line); |
461ef382 WYG |
1915 | IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n"); |
1916 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", | |
1917 | pc, blink1, blink2, ilink1, ilink2, hcmd); | |
b7a79404 RC |
1918 | } |
1919 | ||
1920 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
1921 | ||
1922 | /** | |
1923 | * iwl_print_event_log - Dump error event log to syslog | |
1924 | * | |
1925 | */ | |
b03d7d0f WYG |
1926 | static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
1927 | u32 num_events, u32 mode, | |
1928 | int pos, char **buf, size_t bufsz) | |
b7a79404 RC |
1929 | { |
1930 | u32 i; | |
1931 | u32 base; /* SRAM byte address of event log header */ | |
1932 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
1933 | u32 ptr; /* SRAM byte address of log data */ | |
1934 | u32 ev, time, data; /* event log data */ | |
e5854471 | 1935 | unsigned long reg_flags; |
b7a79404 RC |
1936 | |
1937 | if (num_events == 0) | |
b03d7d0f | 1938 | return pos; |
b2e640d4 | 1939 | |
d7d5783c | 1940 | base = priv->device_pointers.log_event_table; |
ca7966c8 | 1941 | if (priv->ucode_type == UCODE_SUBTYPE_INIT) { |
b2e640d4 JB |
1942 | if (!base) |
1943 | base = priv->_agn.init_evtlog_ptr; | |
1944 | } else { | |
b2e640d4 JB |
1945 | if (!base) |
1946 | base = priv->_agn.inst_evtlog_ptr; | |
1947 | } | |
b7a79404 RC |
1948 | |
1949 | if (mode == 0) | |
1950 | event_size = 2 * sizeof(u32); | |
1951 | else | |
1952 | event_size = 3 * sizeof(u32); | |
1953 | ||
1954 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
1955 | ||
e5854471 BC |
1956 | /* Make sure device is powered up for SRAM reads */ |
1957 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
1958 | iwl_grab_nic_access(priv); | |
1959 | ||
1960 | /* Set starting address; reads will auto-increment */ | |
02a7fa00 | 1961 | iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr); |
e5854471 BC |
1962 | rmb(); |
1963 | ||
b7a79404 RC |
1964 | /* "time" is actually "data" for mode 0 (no timestamp). |
1965 | * place event id # at far right for easier visual parsing. */ | |
1966 | for (i = 0; i < num_events; i++) { | |
02a7fa00 JB |
1967 | ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
1968 | time = iwl_read32(priv, HBUS_TARG_MEM_RDAT); | |
b7a79404 RC |
1969 | if (mode == 0) { |
1970 | /* data, ev */ | |
b03d7d0f WYG |
1971 | if (bufsz) { |
1972 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1973 | "EVT_LOG:0x%08x:%04u\n", | |
1974 | time, ev); | |
1975 | } else { | |
1976 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
1977 | time, ev); | |
1978 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", | |
1979 | time, ev); | |
1980 | } | |
b7a79404 | 1981 | } else { |
02a7fa00 | 1982 | data = iwl_read32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
1983 | if (bufsz) { |
1984 | pos += scnprintf(*buf + pos, bufsz - pos, | |
1985 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
1986 | time, data, ev); | |
1987 | } else { | |
1988 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
b7a79404 | 1989 | time, data, ev); |
b03d7d0f WYG |
1990 | trace_iwlwifi_dev_ucode_event(priv, time, |
1991 | data, ev); | |
1992 | } | |
b7a79404 RC |
1993 | } |
1994 | } | |
e5854471 BC |
1995 | |
1996 | /* Allow device to power down */ | |
1997 | iwl_release_nic_access(priv); | |
1998 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 1999 | return pos; |
b7a79404 RC |
2000 | } |
2001 | ||
c341ddb2 WYG |
2002 | /** |
2003 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
2004 | */ | |
b03d7d0f WYG |
2005 | static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
2006 | u32 num_wraps, u32 next_entry, | |
2007 | u32 size, u32 mode, | |
2008 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
2009 | { |
2010 | /* | |
2011 | * display the newest DEFAULT_LOG_ENTRIES entries | |
2012 | * i.e the entries just before the next ont that uCode would fill. | |
2013 | */ | |
2014 | if (num_wraps) { | |
2015 | if (next_entry < size) { | |
b03d7d0f WYG |
2016 | pos = iwl_print_event_log(priv, |
2017 | capacity - (size - next_entry), | |
2018 | size - next_entry, mode, | |
2019 | pos, buf, bufsz); | |
2020 | pos = iwl_print_event_log(priv, 0, | |
2021 | next_entry, mode, | |
2022 | pos, buf, bufsz); | |
c341ddb2 | 2023 | } else |
b03d7d0f WYG |
2024 | pos = iwl_print_event_log(priv, next_entry - size, |
2025 | size, mode, pos, buf, bufsz); | |
c341ddb2 | 2026 | } else { |
b03d7d0f WYG |
2027 | if (next_entry < size) { |
2028 | pos = iwl_print_event_log(priv, 0, next_entry, | |
2029 | mode, pos, buf, bufsz); | |
2030 | } else { | |
2031 | pos = iwl_print_event_log(priv, next_entry - size, | |
2032 | size, mode, pos, buf, bufsz); | |
2033 | } | |
c341ddb2 | 2034 | } |
b03d7d0f | 2035 | return pos; |
c341ddb2 WYG |
2036 | } |
2037 | ||
c341ddb2 WYG |
2038 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) |
2039 | ||
b03d7d0f WYG |
2040 | int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
2041 | char **buf, bool display) | |
b7a79404 RC |
2042 | { |
2043 | u32 base; /* SRAM byte address of event log header */ | |
2044 | u32 capacity; /* event log capacity in # entries */ | |
2045 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
2046 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
2047 | u32 next_entry; /* index of next entry to be written by uCode */ | |
2048 | u32 size; /* # entries that we'll print */ | |
b2e640d4 | 2049 | u32 logsize; |
b03d7d0f WYG |
2050 | int pos = 0; |
2051 | size_t bufsz = 0; | |
b7a79404 | 2052 | |
d7d5783c | 2053 | base = priv->device_pointers.log_event_table; |
ca7966c8 | 2054 | if (priv->ucode_type == UCODE_SUBTYPE_INIT) { |
b2e640d4 JB |
2055 | logsize = priv->_agn.init_evtlog_size; |
2056 | if (!base) | |
2057 | base = priv->_agn.init_evtlog_ptr; | |
2058 | } else { | |
b2e640d4 JB |
2059 | logsize = priv->_agn.inst_evtlog_size; |
2060 | if (!base) | |
2061 | base = priv->_agn.inst_evtlog_ptr; | |
2062 | } | |
b7a79404 RC |
2063 | |
2064 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2065 | IWL_ERR(priv, |
2066 | "Invalid event log pointer 0x%08X for %s uCode\n", | |
ca7966c8 JB |
2067 | base, |
2068 | (priv->ucode_type == UCODE_SUBTYPE_INIT) | |
2069 | ? "Init" : "RT"); | |
937c397e | 2070 | return -EINVAL; |
b7a79404 RC |
2071 | } |
2072 | ||
2073 | /* event log header */ | |
2074 | capacity = iwl_read_targ_mem(priv, base); | |
2075 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
2076 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
2077 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
2078 | ||
b2e640d4 | 2079 | if (capacity > logsize) { |
84c40692 | 2080 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", |
b2e640d4 JB |
2081 | capacity, logsize); |
2082 | capacity = logsize; | |
84c40692 BC |
2083 | } |
2084 | ||
b2e640d4 | 2085 | if (next_entry > logsize) { |
84c40692 | 2086 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", |
b2e640d4 JB |
2087 | next_entry, logsize); |
2088 | next_entry = logsize; | |
84c40692 BC |
2089 | } |
2090 | ||
b7a79404 RC |
2091 | size = num_wraps ? capacity : next_entry; |
2092 | ||
2093 | /* bail out if nothing in log */ | |
2094 | if (size == 0) { | |
2095 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
b03d7d0f | 2096 | return pos; |
b7a79404 RC |
2097 | } |
2098 | ||
9f28ebc3 | 2099 | /* enable/disable bt channel inhibition */ |
f37837c9 WYG |
2100 | priv->bt_ch_announce = iwlagn_bt_ch_announce; |
2101 | ||
c341ddb2 | 2102 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 2103 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
2104 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
2105 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2106 | #else | |
2107 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
2108 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2109 | #endif | |
2110 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n", | |
2111 | size); | |
b7a79404 | 2112 | |
c341ddb2 | 2113 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
2114 | if (display) { |
2115 | if (full_log) | |
2116 | bufsz = capacity * 48; | |
2117 | else | |
2118 | bufsz = size * 48; | |
2119 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
2120 | if (!*buf) | |
937c397e | 2121 | return -ENOMEM; |
b03d7d0f | 2122 | } |
c341ddb2 WYG |
2123 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
2124 | /* | |
2125 | * if uCode has wrapped back to top of log, | |
2126 | * start at the oldest entry, | |
2127 | * i.e the next one that uCode would fill. | |
2128 | */ | |
2129 | if (num_wraps) | |
b03d7d0f WYG |
2130 | pos = iwl_print_event_log(priv, next_entry, |
2131 | capacity - next_entry, mode, | |
2132 | pos, buf, bufsz); | |
c341ddb2 | 2133 | /* (then/else) start at top of log */ |
b03d7d0f WYG |
2134 | pos = iwl_print_event_log(priv, 0, |
2135 | next_entry, mode, pos, buf, bufsz); | |
c341ddb2 | 2136 | } else |
b03d7d0f WYG |
2137 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2138 | next_entry, size, mode, | |
2139 | pos, buf, bufsz); | |
c341ddb2 | 2140 | #else |
b03d7d0f WYG |
2141 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2142 | next_entry, size, mode, | |
2143 | pos, buf, bufsz); | |
b7a79404 | 2144 | #endif |
b03d7d0f | 2145 | return pos; |
c341ddb2 | 2146 | } |
b7a79404 | 2147 | |
0975cc8f WYG |
2148 | static void iwl_rf_kill_ct_config(struct iwl_priv *priv) |
2149 | { | |
2150 | struct iwl_ct_kill_config cmd; | |
2151 | struct iwl_ct_kill_throttling_config adv_cmd; | |
2152 | unsigned long flags; | |
2153 | int ret = 0; | |
2154 | ||
2155 | spin_lock_irqsave(&priv->lock, flags); | |
2156 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
2157 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | |
2158 | spin_unlock_irqrestore(&priv->lock, flags); | |
2159 | priv->thermal_throttle.ct_kill_toggle = false; | |
2160 | ||
7cb1b088 | 2161 | if (priv->cfg->base_params->support_ct_kill_exit) { |
0975cc8f WYG |
2162 | adv_cmd.critical_temperature_enter = |
2163 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
2164 | adv_cmd.critical_temperature_exit = | |
2165 | cpu_to_le32(priv->hw_params.ct_kill_exit_threshold); | |
2166 | ||
2167 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
2168 | sizeof(adv_cmd), &adv_cmd); | |
2169 | if (ret) | |
2170 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2171 | else | |
2172 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2173 | "succeeded, " | |
2174 | "critical temperature enter is %d," | |
2175 | "exit is %d\n", | |
2176 | priv->hw_params.ct_kill_threshold, | |
2177 | priv->hw_params.ct_kill_exit_threshold); | |
2178 | } else { | |
2179 | cmd.critical_temperature_R = | |
2180 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
2181 | ||
2182 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
2183 | sizeof(cmd), &cmd); | |
2184 | if (ret) | |
2185 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2186 | else | |
2187 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2188 | "succeeded, " | |
2189 | "critical temperature is %d\n", | |
2190 | priv->hw_params.ct_kill_threshold); | |
2191 | } | |
2192 | } | |
2193 | ||
6d6a1afd SZ |
2194 | static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg) |
2195 | { | |
2196 | struct iwl_calib_cfg_cmd calib_cfg_cmd; | |
2197 | struct iwl_host_cmd cmd = { | |
2198 | .id = CALIBRATION_CFG_CMD, | |
2199 | .len = sizeof(struct iwl_calib_cfg_cmd), | |
2200 | .data = &calib_cfg_cmd, | |
2201 | }; | |
2202 | ||
2203 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
2204 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
7cb1b088 | 2205 | calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg); |
6d6a1afd SZ |
2206 | |
2207 | return iwl_send_cmd(priv, &cmd); | |
2208 | } | |
2209 | ||
2210 | ||
b481de9c | 2211 | /** |
4a4a9e81 | 2212 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2213 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 2214 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 2215 | */ |
4613e72d | 2216 | int iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 2217 | { |
57aab75a | 2218 | int ret = 0; |
246ed355 | 2219 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 2220 | |
ca7966c8 | 2221 | iwl_reset_ict(priv); |
b481de9c | 2222 | |
ca7966c8 | 2223 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
6d6a1afd | 2224 | |
5b9f8cd3 | 2225 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
2226 | set_bit(STATUS_ALIVE, &priv->status); |
2227 | ||
22de94de SG |
2228 | /* Enable watchdog to monitor the driver tx queues */ |
2229 | iwl_setup_watchdog(priv); | |
b74e31a9 | 2230 | |
fee1247a | 2231 | if (iwl_is_rfkill(priv)) |
ca7966c8 | 2232 | return -ERFKILL; |
b481de9c | 2233 | |
bc795df1 | 2234 | /* download priority table before any calibration request */ |
7cb1b088 WYG |
2235 | if (priv->cfg->bt_params && |
2236 | priv->cfg->bt_params->advanced_bt_coexist) { | |
f7322f8f WYG |
2237 | /* Configure Bluetooth device coexistence support */ |
2238 | priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; | |
2239 | priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; | |
2240 | priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; | |
2241 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
2242 | priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS; | |
a5901cbb | 2243 | iwlagn_send_prio_tbl(priv); |
f7322f8f WYG |
2244 | |
2245 | /* FIXME: w/a to force change uCode BT state machine */ | |
ca7966c8 JB |
2246 | ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN, |
2247 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); | |
2248 | if (ret) | |
2249 | return ret; | |
2250 | ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE, | |
2251 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); | |
2252 | if (ret) | |
2253 | return ret; | |
f7322f8f | 2254 | } |
bc795df1 WYG |
2255 | if (priv->hw_params.calib_rt_cfg) |
2256 | iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg); | |
2257 | ||
36d6825b | 2258 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2259 | |
470ab2dd | 2260 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2261 | |
2f748dec WYG |
2262 | /* Configure Tx antenna selection based on H/W config */ |
2263 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
2264 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
2265 | ||
246ed355 | 2266 | if (iwl_is_associated_ctx(ctx)) { |
c1adf9fb | 2267 | struct iwl_rxon_cmd *active_rxon = |
246ed355 | 2268 | (struct iwl_rxon_cmd *)&ctx->active; |
019fb97d | 2269 | /* apply any changes in staging */ |
246ed355 | 2270 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2271 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2272 | } else { | |
d0fe478c | 2273 | struct iwl_rxon_context *tmp; |
b481de9c | 2274 | /* Initialize our rx_config data */ |
d0fe478c JB |
2275 | for_each_context(priv, tmp) |
2276 | iwl_connection_init_rx_config(priv, tmp); | |
45823531 AK |
2277 | |
2278 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 | 2279 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); |
b481de9c ZY |
2280 | } |
2281 | ||
73b78a22 WYG |
2282 | if (!priv->cfg->bt_params || (priv->cfg->bt_params && |
2283 | !priv->cfg->bt_params->advanced_bt_coexist)) { | |
2284 | /* | |
2285 | * default is 2-wire BT coexexistence support | |
2286 | */ | |
aeb4a2ee WYG |
2287 | priv->cfg->ops->hcmd->send_bt_config(priv); |
2288 | } | |
b481de9c | 2289 | |
4a4a9e81 TW |
2290 | iwl_reset_run_time_calib(priv); |
2291 | ||
9e2e7422 WYG |
2292 | set_bit(STATUS_READY, &priv->status); |
2293 | ||
b481de9c | 2294 | /* Configure the adapter for unassociated operation */ |
ca7966c8 JB |
2295 | ret = iwlcore_commit_rxon(priv, ctx); |
2296 | if (ret) | |
2297 | return ret; | |
b481de9c ZY |
2298 | |
2299 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 2300 | iwl_rf_kill_ct_config(priv); |
5a66926a | 2301 | |
e1623446 | 2302 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
c46fbefa | 2303 | |
ca7966c8 | 2304 | return iwl_power_update_mode(priv, true); |
b481de9c ZY |
2305 | } |
2306 | ||
4e39317d | 2307 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2308 | |
5b9f8cd3 | 2309 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c | 2310 | { |
22dd2fd2 | 2311 | int exit_pending; |
b481de9c | 2312 | |
e1623446 | 2313 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2314 | |
d745d472 SG |
2315 | iwl_scan_cancel_timeout(priv, 200); |
2316 | ||
2317 | exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2318 | |
b62177a0 SG |
2319 | /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set |
2320 | * to prevent rearm timer */ | |
22de94de | 2321 | del_timer_sync(&priv->watchdog); |
b62177a0 | 2322 | |
dcef732c | 2323 | iwl_clear_ucode_stations(priv, NULL); |
a194e324 | 2324 | iwl_dealloc_bcast_stations(priv); |
db125c78 | 2325 | iwl_clear_driver_stations(priv); |
b481de9c | 2326 | |
a1174138 | 2327 | /* reset BT coex data */ |
da5dbb97 | 2328 | priv->bt_status = 0; |
7cb1b088 WYG |
2329 | if (priv->cfg->bt_params) |
2330 | priv->bt_traffic_load = | |
2331 | priv->cfg->bt_params->bt_init_traffic_load; | |
2332 | else | |
2333 | priv->bt_traffic_load = 0; | |
bee008b7 WYG |
2334 | priv->bt_full_concurrent = false; |
2335 | priv->bt_ci_compliance = 0; | |
a1174138 | 2336 | |
b481de9c ZY |
2337 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2338 | * exiting the module */ | |
2339 | if (!exit_pending) | |
2340 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2341 | ||
b481de9c ZY |
2342 | if (priv->mac80211_registered) |
2343 | ieee80211_stop_queues(priv->hw); | |
2344 | ||
1a10f433 | 2345 | /* Clear out all status bits but a few that are stable across reset */ |
b481de9c ZY |
2346 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2347 | STATUS_RF_KILL_HW | | |
9788864e RC |
2348 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2349 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2350 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
2351 | STATUS_FW_ERROR | |
2352 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2353 | STATUS_EXIT_PENDING; | |
b481de9c | 2354 | |
bc4f8ada | 2355 | iwlagn_stop_device(priv); |
4d2ccdb9 | 2356 | |
77834543 | 2357 | dev_kfree_skb(priv->beacon_skb); |
12e934dc | 2358 | priv->beacon_skb = NULL; |
b481de9c ZY |
2359 | |
2360 | /* clear out any free frames */ | |
fcab423d | 2361 | iwl_clear_free_frames(priv); |
b481de9c ZY |
2362 | } |
2363 | ||
5b9f8cd3 | 2364 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2365 | { |
2366 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2367 | __iwl_down(priv); |
b481de9c | 2368 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2369 | |
4e39317d | 2370 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
2371 | } |
2372 | ||
086ed117 MA |
2373 | #define HW_READY_TIMEOUT (50) |
2374 | ||
4cd2bf76 | 2375 | /* Note: returns poll_bit return value, which is >= 0 if success */ |
086ed117 MA |
2376 | static int iwl_set_hw_ready(struct iwl_priv *priv) |
2377 | { | |
4cd2bf76 | 2378 | int ret; |
086ed117 MA |
2379 | |
2380 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2381 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
2382 | ||
2383 | /* See if we got it */ | |
2384 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2385 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2386 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2387 | HW_READY_TIMEOUT); | |
086ed117 | 2388 | |
4cd2bf76 | 2389 | IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : ""); |
086ed117 MA |
2390 | return ret; |
2391 | } | |
2392 | ||
4cd2bf76 | 2393 | /* Note: returns standard 0/-ERROR code */ |
3e14c1fd | 2394 | int iwl_prepare_card_hw(struct iwl_priv *priv) |
086ed117 | 2395 | { |
4cd2bf76 | 2396 | int ret; |
086ed117 | 2397 | |
91dd6c27 | 2398 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n"); |
086ed117 | 2399 | |
3354a0f6 | 2400 | ret = iwl_set_hw_ready(priv); |
4cd2bf76 JB |
2401 | if (ret >= 0) |
2402 | return 0; | |
3354a0f6 MA |
2403 | |
2404 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
2405 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
2406 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
2407 | ||
2408 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2409 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
2410 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
2411 | ||
4cd2bf76 JB |
2412 | if (ret < 0) |
2413 | return ret; | |
086ed117 | 2414 | |
4cd2bf76 JB |
2415 | /* HW should be ready by now, check again. */ |
2416 | ret = iwl_set_hw_ready(priv); | |
2417 | if (ret >= 0) | |
2418 | return 0; | |
086ed117 MA |
2419 | return ret; |
2420 | } | |
2421 | ||
b481de9c ZY |
2422 | #define MAX_HW_RESTARTS 5 |
2423 | ||
5b9f8cd3 | 2424 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 2425 | { |
a194e324 | 2426 | struct iwl_rxon_context *ctx; |
57aab75a | 2427 | int ret; |
b481de9c | 2428 | |
ca7966c8 JB |
2429 | lockdep_assert_held(&priv->mutex); |
2430 | ||
b481de9c | 2431 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { |
39aadf8c | 2432 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2433 | return -EIO; |
2434 | } | |
2435 | ||
a194e324 | 2436 | for_each_context(priv, ctx) { |
a30e3112 | 2437 | ret = iwlagn_alloc_bcast_station(priv, ctx); |
a194e324 JB |
2438 | if (ret) { |
2439 | iwl_dealloc_bcast_stations(priv); | |
2440 | return ret; | |
2441 | } | |
2442 | } | |
2c810ccd | 2443 | |
ca7966c8 JB |
2444 | ret = iwlagn_run_init_ucode(priv); |
2445 | if (ret) { | |
2446 | IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret); | |
2447 | goto error; | |
2448 | } | |
b481de9c | 2449 | |
ca7966c8 | 2450 | ret = iwlagn_load_ucode_wait_alive(priv, |
dbf28e21 | 2451 | &priv->ucode_rt, |
ca7966c8 JB |
2452 | UCODE_SUBTYPE_REGULAR, |
2453 | UCODE_SUBTYPE_REGULAR_NEW); | |
2454 | if (ret) { | |
2455 | IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret); | |
2456 | goto error; | |
b481de9c ZY |
2457 | } |
2458 | ||
ca7966c8 JB |
2459 | ret = iwl_alive_start(priv); |
2460 | if (ret) | |
2461 | goto error; | |
2462 | return 0; | |
2463 | ||
2464 | error: | |
b481de9c | 2465 | set_bit(STATUS_EXIT_PENDING, &priv->status); |
5b9f8cd3 | 2466 | __iwl_down(priv); |
64e72c3e | 2467 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c | 2468 | |
ca7966c8 JB |
2469 | IWL_ERR(priv, "Unable to initialize device.\n"); |
2470 | return ret; | |
b481de9c ZY |
2471 | } |
2472 | ||
2473 | ||
2474 | /***************************************************************************** | |
2475 | * | |
2476 | * Workqueue callbacks | |
2477 | * | |
2478 | *****************************************************************************/ | |
2479 | ||
16e727e8 EG |
2480 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
2481 | { | |
2482 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
2483 | run_time_calib_work); | |
2484 | ||
2485 | mutex_lock(&priv->mutex); | |
2486 | ||
2487 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
2488 | test_bit(STATUS_SCANNING, &priv->status)) { | |
2489 | mutex_unlock(&priv->mutex); | |
2490 | return; | |
2491 | } | |
2492 | ||
2493 | if (priv->start_calib) { | |
0da0e5bf JB |
2494 | iwl_chain_noise_calibration(priv); |
2495 | iwl_sensitivity_calibration(priv); | |
16e727e8 EG |
2496 | } |
2497 | ||
2498 | mutex_unlock(&priv->mutex); | |
16e727e8 EG |
2499 | } |
2500 | ||
e43e85c4 JB |
2501 | static void iwlagn_prepare_restart(struct iwl_priv *priv) |
2502 | { | |
2503 | struct iwl_rxon_context *ctx; | |
2504 | bool bt_full_concurrent; | |
2505 | u8 bt_ci_compliance; | |
2506 | u8 bt_load; | |
2507 | u8 bt_status; | |
2508 | ||
2509 | lockdep_assert_held(&priv->mutex); | |
2510 | ||
2511 | for_each_context(priv, ctx) | |
2512 | ctx->vif = NULL; | |
2513 | priv->is_open = 0; | |
2514 | ||
2515 | /* | |
2516 | * __iwl_down() will clear the BT status variables, | |
2517 | * which is correct, but when we restart we really | |
2518 | * want to keep them so restore them afterwards. | |
2519 | * | |
2520 | * The restart process will later pick them up and | |
2521 | * re-configure the hw when we reconfigure the BT | |
2522 | * command. | |
2523 | */ | |
2524 | bt_full_concurrent = priv->bt_full_concurrent; | |
2525 | bt_ci_compliance = priv->bt_ci_compliance; | |
2526 | bt_load = priv->bt_traffic_load; | |
2527 | bt_status = priv->bt_status; | |
2528 | ||
2529 | __iwl_down(priv); | |
2530 | ||
2531 | priv->bt_full_concurrent = bt_full_concurrent; | |
2532 | priv->bt_ci_compliance = bt_ci_compliance; | |
2533 | priv->bt_traffic_load = bt_load; | |
2534 | priv->bt_status = bt_status; | |
2535 | } | |
2536 | ||
5b9f8cd3 | 2537 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2538 | { |
c79dd5b5 | 2539 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2540 | |
2541 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2542 | return; | |
2543 | ||
19cc1087 JB |
2544 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
2545 | mutex_lock(&priv->mutex); | |
e43e85c4 | 2546 | iwlagn_prepare_restart(priv); |
19cc1087 | 2547 | mutex_unlock(&priv->mutex); |
a1174138 | 2548 | iwl_cancel_deferred_work(priv); |
19cc1087 JB |
2549 | ieee80211_restart_hw(priv->hw); |
2550 | } else { | |
ca7966c8 | 2551 | WARN_ON(1); |
19cc1087 | 2552 | } |
b481de9c ZY |
2553 | } |
2554 | ||
5b9f8cd3 | 2555 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2556 | { |
c79dd5b5 TW |
2557 | struct iwl_priv *priv = |
2558 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2559 | |
2560 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2561 | return; | |
2562 | ||
2563 | mutex_lock(&priv->mutex); | |
54b81550 | 2564 | iwlagn_rx_replenish(priv); |
b481de9c ZY |
2565 | mutex_unlock(&priv->mutex); |
2566 | } | |
2567 | ||
266af4c7 JB |
2568 | static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb, |
2569 | struct ieee80211_channel *chan, | |
2570 | enum nl80211_channel_type channel_type, | |
2571 | unsigned int wait) | |
2572 | { | |
2573 | struct iwl_priv *priv = hw->priv; | |
2574 | int ret; | |
2575 | ||
2576 | /* Not supported if we don't have PAN */ | |
2577 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) { | |
2578 | ret = -EOPNOTSUPP; | |
2579 | goto free; | |
2580 | } | |
2581 | ||
2582 | /* Not supported on pre-P2P firmware */ | |
2583 | if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes & | |
2584 | BIT(NL80211_IFTYPE_P2P_CLIENT))) { | |
2585 | ret = -EOPNOTSUPP; | |
2586 | goto free; | |
2587 | } | |
2588 | ||
2589 | mutex_lock(&priv->mutex); | |
2590 | ||
2591 | if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) { | |
2592 | /* | |
2593 | * If the PAN context is free, use the normal | |
2594 | * way of doing remain-on-channel offload + TX. | |
2595 | */ | |
2596 | ret = 1; | |
2597 | goto out; | |
2598 | } | |
2599 | ||
2600 | /* TODO: queue up if scanning? */ | |
2601 | if (test_bit(STATUS_SCANNING, &priv->status) || | |
2602 | priv->_agn.offchan_tx_skb) { | |
2603 | ret = -EBUSY; | |
2604 | goto out; | |
2605 | } | |
2606 | ||
2607 | /* | |
2608 | * max_scan_ie_len doesn't include the blank SSID or the header, | |
2609 | * so need to add that again here. | |
2610 | */ | |
2611 | if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) { | |
2612 | ret = -ENOBUFS; | |
2613 | goto out; | |
2614 | } | |
2615 | ||
2616 | priv->_agn.offchan_tx_skb = skb; | |
2617 | priv->_agn.offchan_tx_timeout = wait; | |
2618 | priv->_agn.offchan_tx_chan = chan; | |
2619 | ||
2620 | ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif, | |
2621 | IWL_SCAN_OFFCH_TX, chan->band); | |
2622 | if (ret) | |
2623 | priv->_agn.offchan_tx_skb = NULL; | |
2624 | out: | |
2625 | mutex_unlock(&priv->mutex); | |
2626 | free: | |
2627 | if (ret < 0) | |
2628 | kfree_skb(skb); | |
2629 | ||
2630 | return ret; | |
2631 | } | |
2632 | ||
2633 | static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw) | |
2634 | { | |
2635 | struct iwl_priv *priv = hw->priv; | |
2636 | int ret; | |
2637 | ||
2638 | mutex_lock(&priv->mutex); | |
2639 | ||
f8a22a2b DC |
2640 | if (!priv->_agn.offchan_tx_skb) { |
2641 | ret = -EINVAL; | |
2642 | goto unlock; | |
2643 | } | |
266af4c7 JB |
2644 | |
2645 | priv->_agn.offchan_tx_skb = NULL; | |
2646 | ||
2647 | ret = iwl_scan_cancel_timeout(priv, 200); | |
2648 | if (ret) | |
2649 | ret = -EIO; | |
f8a22a2b | 2650 | unlock: |
266af4c7 JB |
2651 | mutex_unlock(&priv->mutex); |
2652 | ||
2653 | return ret; | |
2654 | } | |
2655 | ||
b481de9c ZY |
2656 | /***************************************************************************** |
2657 | * | |
2658 | * mac80211 entry point functions | |
2659 | * | |
2660 | *****************************************************************************/ | |
2661 | ||
f0b6e2e8 RC |
2662 | /* |
2663 | * Not a mac80211 entry point function, but it fits in with all the | |
2664 | * other mac80211 functions grouped here. | |
2665 | */ | |
dd7a2509 JB |
2666 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
2667 | struct iwlagn_ucode_capabilities *capa) | |
f0b6e2e8 RC |
2668 | { |
2669 | int ret; | |
2670 | struct ieee80211_hw *hw = priv->hw; | |
d0fe478c JB |
2671 | struct iwl_rxon_context *ctx; |
2672 | ||
f0b6e2e8 RC |
2673 | hw->rate_control_algorithm = "iwl-agn-rs"; |
2674 | ||
2675 | /* Tell mac80211 our characteristics */ | |
2676 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
f0b6e2e8 | 2677 | IEEE80211_HW_AMPDU_AGGREGATION | |
2491fa42 | 2678 | IEEE80211_HW_NEED_DTIM_PERIOD | |
6fb5511a JB |
2679 | IEEE80211_HW_SPECTRUM_MGMT | |
2680 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
f0b6e2e8 | 2681 | |
9b768832 JB |
2682 | hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF; |
2683 | ||
23c0fcc6 WYG |
2684 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | |
2685 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
f0b6e2e8 | 2686 | |
ba37a3d0 JB |
2687 | if (priv->cfg->sku & IWL_SKU_N) |
2688 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | |
2689 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
2690 | ||
3997ff39 JB |
2691 | if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP) |
2692 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; | |
2693 | ||
8d9698b3 | 2694 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
fd1af15d JB |
2695 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
2696 | ||
d0fe478c JB |
2697 | for_each_context(priv, ctx) { |
2698 | hw->wiphy->interface_modes |= ctx->interface_modes; | |
2699 | hw->wiphy->interface_modes |= ctx->exclusive_interface_modes; | |
2700 | } | |
f0b6e2e8 | 2701 | |
9b9190d9 JB |
2702 | hw->wiphy->max_remain_on_channel_duration = 1000; |
2703 | ||
f6c8f152 | 2704 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | |
274102a8 JB |
2705 | WIPHY_FLAG_DISABLE_BEACON_HINTS | |
2706 | WIPHY_FLAG_IBSS_RSN; | |
f0b6e2e8 RC |
2707 | |
2708 | /* | |
2709 | * For now, disable PS by default because it affects | |
2710 | * RX performance significantly. | |
2711 | */ | |
5be83de5 | 2712 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
f0b6e2e8 | 2713 | |
1382c71c | 2714 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; |
f0b6e2e8 | 2715 | /* we create the 802.11 header and a zero-length SSID element */ |
dd7a2509 | 2716 | hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2; |
f0b6e2e8 RC |
2717 | |
2718 | /* Default value; 4 EDCA QOS priorities */ | |
2719 | hw->queues = 4; | |
2720 | ||
2721 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | |
2722 | ||
2723 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
2724 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
2725 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2726 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
2727 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
2728 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
2729 | ||
5ed540ae WYG |
2730 | iwl_leds_init(priv); |
2731 | ||
f0b6e2e8 RC |
2732 | ret = ieee80211_register_hw(priv->hw); |
2733 | if (ret) { | |
2734 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
2735 | return ret; | |
2736 | } | |
2737 | priv->mac80211_registered = 1; | |
2738 | ||
2739 | return 0; | |
2740 | } | |
2741 | ||
2742 | ||
2dedbf58 | 2743 | static int iwlagn_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2744 | { |
c79dd5b5 | 2745 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2746 | int ret; |
b481de9c | 2747 | |
e1623446 | 2748 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2749 | |
2750 | /* we should be verifying the device is ready to be opened */ | |
2751 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2752 | ret = __iwl_up(priv); |
b481de9c | 2753 | mutex_unlock(&priv->mutex); |
e655b9f0 | 2754 | if (ret) |
6cd0b1cb | 2755 | return ret; |
e655b9f0 | 2756 | |
e1623446 | 2757 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2758 | |
ca7966c8 JB |
2759 | /* Now we should be done, and the READY bit should be set. */ |
2760 | if (WARN_ON(!test_bit(STATUS_READY, &priv->status))) | |
2761 | ret = -EIO; | |
0a078ffa | 2762 | |
5ed540ae | 2763 | iwlagn_led_enable(priv); |
e932a609 | 2764 | |
0a078ffa | 2765 | priv->is_open = 1; |
e1623446 | 2766 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2767 | return 0; |
2768 | } | |
2769 | ||
2dedbf58 | 2770 | static void iwlagn_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 2771 | { |
c79dd5b5 | 2772 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2773 | |
e1623446 | 2774 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 2775 | |
19cc1087 | 2776 | if (!priv->is_open) |
e655b9f0 | 2777 | return; |
e655b9f0 | 2778 | |
b481de9c | 2779 | priv->is_open = 0; |
5a66926a | 2780 | |
5b9f8cd3 | 2781 | iwl_down(priv); |
5a66926a ZY |
2782 | |
2783 | flush_workqueue(priv->workqueue); | |
6cd0b1cb | 2784 | |
554d1d02 SG |
2785 | /* User space software may expect getting rfkill changes |
2786 | * even if interface is down */ | |
6cd0b1cb | 2787 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
554d1d02 | 2788 | iwl_enable_rfkill_int(priv); |
948c171c | 2789 | |
e1623446 | 2790 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
2791 | } |
2792 | ||
2dedbf58 | 2793 | static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 2794 | { |
c79dd5b5 | 2795 | struct iwl_priv *priv = hw->priv; |
b481de9c | 2796 | |
e1623446 | 2797 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 2798 | |
e1623446 | 2799 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 2800 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 2801 | |
74bcdb33 | 2802 | if (iwlagn_tx_skb(priv, skb)) |
b481de9c ZY |
2803 | dev_kfree_skb_any(skb); |
2804 | ||
e1623446 | 2805 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
b481de9c ZY |
2806 | } |
2807 | ||
2dedbf58 JB |
2808 | static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw, |
2809 | struct ieee80211_vif *vif, | |
2810 | struct ieee80211_key_conf *keyconf, | |
2811 | struct ieee80211_sta *sta, | |
2812 | u32 iv32, u16 *phase1key) | |
ab885f8c | 2813 | { |
9f58671e | 2814 | struct iwl_priv *priv = hw->priv; |
a194e324 JB |
2815 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
2816 | ||
e1623446 | 2817 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 2818 | |
a194e324 | 2819 | iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta, |
b3fbdcf4 | 2820 | iv32, phase1key); |
ab885f8c | 2821 | |
e1623446 | 2822 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
2823 | } |
2824 | ||
2dedbf58 JB |
2825 | static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
2826 | struct ieee80211_vif *vif, | |
2827 | struct ieee80211_sta *sta, | |
2828 | struct ieee80211_key_conf *key) | |
b481de9c | 2829 | { |
c79dd5b5 | 2830 | struct iwl_priv *priv = hw->priv; |
a194e324 | 2831 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
c10afb6e | 2832 | struct iwl_rxon_context *ctx = vif_priv->ctx; |
42986796 WT |
2833 | int ret; |
2834 | u8 sta_id; | |
2835 | bool is_default_wep_key = false; | |
b481de9c | 2836 | |
e1623446 | 2837 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 2838 | |
9d143e9a | 2839 | if (iwlagn_mod_params.sw_crypto) { |
e1623446 | 2840 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
2841 | return -EOPNOTSUPP; |
2842 | } | |
b481de9c | 2843 | |
274102a8 JB |
2844 | /* |
2845 | * To support IBSS RSN, don't program group keys in IBSS, the | |
2846 | * hardware will then not attempt to decrypt the frames. | |
2847 | */ | |
2848 | if (vif->type == NL80211_IFTYPE_ADHOC && | |
2849 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) | |
2850 | return -EOPNOTSUPP; | |
2851 | ||
a194e324 | 2852 | sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta); |
0af8bcae JB |
2853 | if (sta_id == IWL_INVALID_STATION) |
2854 | return -EINVAL; | |
b481de9c | 2855 | |
6974e363 | 2856 | mutex_lock(&priv->mutex); |
2a421b91 | 2857 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 | 2858 | |
a90178fa JB |
2859 | /* |
2860 | * If we are getting WEP group key and we didn't receive any key mapping | |
6974e363 EG |
2861 | * so far, we are in legacy wep mode (group key only), otherwise we are |
2862 | * in 1X mode. | |
a90178fa JB |
2863 | * In legacy wep mode, we use another host command to the uCode. |
2864 | */ | |
97359d12 JB |
2865 | if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || |
2866 | key->cipher == WLAN_CIPHER_SUITE_WEP104) && | |
54c8067a | 2867 | !sta) { |
6974e363 | 2868 | if (cmd == SET_KEY) |
c10afb6e | 2869 | is_default_wep_key = !ctx->key_mapping_keys; |
6974e363 | 2870 | else |
ccc038ab EG |
2871 | is_default_wep_key = |
2872 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 2873 | } |
052c4b9f | 2874 | |
b481de9c | 2875 | switch (cmd) { |
deb09c43 | 2876 | case SET_KEY: |
6974e363 | 2877 | if (is_default_wep_key) |
2995bafa | 2878 | ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key); |
deb09c43 | 2879 | else |
a194e324 JB |
2880 | ret = iwl_set_dynamic_key(priv, vif_priv->ctx, |
2881 | key, sta_id); | |
deb09c43 | 2882 | |
e1623446 | 2883 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
2884 | break; |
2885 | case DISABLE_KEY: | |
6974e363 | 2886 | if (is_default_wep_key) |
c10afb6e | 2887 | ret = iwl_remove_default_wep_key(priv, ctx, key); |
deb09c43 | 2888 | else |
c10afb6e | 2889 | ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id); |
deb09c43 | 2890 | |
e1623446 | 2891 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
2892 | break; |
2893 | default: | |
deb09c43 | 2894 | ret = -EINVAL; |
b481de9c ZY |
2895 | } |
2896 | ||
72e15d71 | 2897 | mutex_unlock(&priv->mutex); |
e1623446 | 2898 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 2899 | |
deb09c43 | 2900 | return ret; |
b481de9c ZY |
2901 | } |
2902 | ||
2dedbf58 JB |
2903 | static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw, |
2904 | struct ieee80211_vif *vif, | |
2905 | enum ieee80211_ampdu_mlme_action action, | |
2906 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, | |
2907 | u8 buf_size) | |
d783b061 TW |
2908 | { |
2909 | struct iwl_priv *priv = hw->priv; | |
4620fefa | 2910 | int ret = -EINVAL; |
7b090687 | 2911 | struct iwl_station_priv *sta_priv = (void *) sta->drv_priv; |
d783b061 | 2912 | |
e1623446 | 2913 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 2914 | sta->addr, tid); |
d783b061 TW |
2915 | |
2916 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
2917 | return -EACCES; | |
2918 | ||
4620fefa JB |
2919 | mutex_lock(&priv->mutex); |
2920 | ||
d783b061 TW |
2921 | switch (action) { |
2922 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 2923 | IWL_DEBUG_HT(priv, "start Rx\n"); |
4620fefa JB |
2924 | ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn); |
2925 | break; | |
d783b061 | 2926 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 2927 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
619753ff | 2928 | ret = iwl_sta_rx_agg_stop(priv, sta, tid); |
5c2207c6 | 2929 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa JB |
2930 | ret = 0; |
2931 | break; | |
d783b061 | 2932 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 2933 | IWL_DEBUG_HT(priv, "start Tx\n"); |
619753ff | 2934 | ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn); |
d5a0ffa3 WYG |
2935 | if (ret == 0) { |
2936 | priv->_agn.agg_tids_count++; | |
2937 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
2938 | priv->_agn.agg_tids_count); | |
2939 | } | |
4620fefa | 2940 | break; |
d783b061 | 2941 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 2942 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
619753ff | 2943 | ret = iwlagn_tx_agg_stop(priv, vif, sta, tid); |
d5a0ffa3 WYG |
2944 | if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) { |
2945 | priv->_agn.agg_tids_count--; | |
2946 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
2947 | priv->_agn.agg_tids_count); | |
2948 | } | |
5c2207c6 | 2949 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa | 2950 | ret = 0; |
7cb1b088 WYG |
2951 | if (priv->cfg->ht_params && |
2952 | priv->cfg->ht_params->use_rts_for_aggregation) { | |
94597ab2 JB |
2953 | struct iwl_station_priv *sta_priv = |
2954 | (void *) sta->drv_priv; | |
2955 | /* | |
2956 | * switch off RTS/CTS if it was previously enabled | |
2957 | */ | |
2958 | ||
2959 | sta_priv->lq_sta.lq.general_params.flags &= | |
2960 | ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
7e6a5886 JB |
2961 | iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), |
2962 | &sta_priv->lq_sta.lq, CMD_ASYNC, false); | |
94597ab2 | 2963 | } |
4620fefa | 2964 | break; |
f0527971 | 2965 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
c8823ec1 JB |
2966 | buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF); |
2967 | ||
2968 | iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size); | |
2969 | ||
7b090687 JB |
2970 | /* |
2971 | * If the limit is 0, then it wasn't initialised yet, | |
2972 | * use the default. We can do that since we take the | |
2973 | * minimum below, and we don't want to go above our | |
2974 | * default due to hardware restrictions. | |
2975 | */ | |
2976 | if (sta_priv->max_agg_bufsize == 0) | |
2977 | sta_priv->max_agg_bufsize = | |
2978 | LINK_QUAL_AGG_FRAME_LIMIT_DEF; | |
2979 | ||
2980 | /* | |
2981 | * Even though in theory the peer could have different | |
2982 | * aggregation reorder buffer sizes for different sessions, | |
2983 | * our ucode doesn't allow for that and has a global limit | |
2984 | * for each station. Therefore, use the minimum of all the | |
2985 | * aggregation sessions and our default value. | |
2986 | */ | |
2987 | sta_priv->max_agg_bufsize = | |
2988 | min(sta_priv->max_agg_bufsize, buf_size); | |
2989 | ||
7cb1b088 WYG |
2990 | if (priv->cfg->ht_params && |
2991 | priv->cfg->ht_params->use_rts_for_aggregation) { | |
cfecc6b4 WYG |
2992 | /* |
2993 | * switch to RTS/CTS if it is the prefer protection | |
2994 | * method for HT traffic | |
2995 | */ | |
94597ab2 JB |
2996 | |
2997 | sta_priv->lq_sta.lq.general_params.flags |= | |
2998 | LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
cfecc6b4 | 2999 | } |
7b090687 JB |
3000 | |
3001 | sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit = | |
3002 | sta_priv->max_agg_bufsize; | |
3003 | ||
3004 | iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), | |
3005 | &sta_priv->lq_sta.lq, CMD_ASYNC, false); | |
cfecc6b4 | 3006 | ret = 0; |
d783b061 TW |
3007 | break; |
3008 | } | |
4620fefa JB |
3009 | mutex_unlock(&priv->mutex); |
3010 | ||
3011 | return ret; | |
d783b061 | 3012 | } |
9f58671e | 3013 | |
2dedbf58 JB |
3014 | static int iwlagn_mac_sta_add(struct ieee80211_hw *hw, |
3015 | struct ieee80211_vif *vif, | |
3016 | struct ieee80211_sta *sta) | |
fe6b23dd RC |
3017 | { |
3018 | struct iwl_priv *priv = hw->priv; | |
3019 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
a194e324 | 3020 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
eafdfbd3 | 3021 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
fe6b23dd RC |
3022 | int ret; |
3023 | u8 sta_id; | |
3024 | ||
3025 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", | |
3026 | sta->addr); | |
da5ae1cf RC |
3027 | mutex_lock(&priv->mutex); |
3028 | IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n", | |
3029 | sta->addr); | |
3030 | sta_priv->common.sta_id = IWL_INVALID_STATION; | |
fe6b23dd RC |
3031 | |
3032 | atomic_set(&sta_priv->pending_frames, 0); | |
3033 | if (vif->type == NL80211_IFTYPE_AP) | |
3034 | sta_priv->client = true; | |
3035 | ||
a194e324 | 3036 | ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr, |
238d781d | 3037 | is_ap, sta, &sta_id); |
fe6b23dd RC |
3038 | if (ret) { |
3039 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
3040 | sta->addr, ret); | |
3041 | /* Should we return success if return code is EEXIST ? */ | |
da5ae1cf | 3042 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
3043 | return ret; |
3044 | } | |
3045 | ||
fd1af15d JB |
3046 | sta_priv->common.sta_id = sta_id; |
3047 | ||
fe6b23dd | 3048 | /* Initialize rate scaling */ |
91dd6c27 | 3049 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n", |
fe6b23dd RC |
3050 | sta->addr); |
3051 | iwl_rs_rate_init(priv, sta, sta_id); | |
da5ae1cf | 3052 | mutex_unlock(&priv->mutex); |
fe6b23dd | 3053 | |
fd1af15d | 3054 | return 0; |
fe6b23dd RC |
3055 | } |
3056 | ||
2dedbf58 JB |
3057 | static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw, |
3058 | struct ieee80211_channel_switch *ch_switch) | |
79d07325 WYG |
3059 | { |
3060 | struct iwl_priv *priv = hw->priv; | |
3061 | const struct iwl_channel_info *ch_info; | |
3062 | struct ieee80211_conf *conf = &hw->conf; | |
aa2dc6b5 | 3063 | struct ieee80211_channel *channel = ch_switch->channel; |
79d07325 | 3064 | struct iwl_ht_config *ht_conf = &priv->current_ht_config; |
246ed355 JB |
3065 | /* |
3066 | * MULTI-FIXME | |
3067 | * When we add support for multiple interfaces, we need to | |
3068 | * revisit this. The channel switch command in the device | |
3069 | * only affects the BSS context, but what does that really | |
3070 | * mean? And what if we get a CSA on the second interface? | |
3071 | * This needs a lot of work. | |
3072 | */ | |
3073 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
79d07325 WYG |
3074 | u16 ch; |
3075 | unsigned long flags = 0; | |
3076 | ||
3077 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3078 | ||
dc1a4068 SG |
3079 | mutex_lock(&priv->mutex); |
3080 | ||
79d07325 | 3081 | if (iwl_is_rfkill(priv)) |
dc1a4068 | 3082 | goto out; |
79d07325 WYG |
3083 | |
3084 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
3085 | test_bit(STATUS_SCANNING, &priv->status)) | |
dc1a4068 | 3086 | goto out; |
79d07325 | 3087 | |
246ed355 | 3088 | if (!iwl_is_associated_ctx(ctx)) |
dc1a4068 | 3089 | goto out; |
79d07325 WYG |
3090 | |
3091 | /* channel switch in progress */ | |
3092 | if (priv->switch_rxon.switch_in_progress == true) | |
dc1a4068 | 3093 | goto out; |
79d07325 | 3094 | |
79d07325 WYG |
3095 | if (priv->cfg->ops->lib->set_channel_switch) { |
3096 | ||
aa2dc6b5 | 3097 | ch = channel->hw_value; |
246ed355 | 3098 | if (le16_to_cpu(ctx->active.channel) != ch) { |
79d07325 | 3099 | ch_info = iwl_get_channel_info(priv, |
aa2dc6b5 | 3100 | channel->band, |
79d07325 WYG |
3101 | ch); |
3102 | if (!is_channel_valid(ch_info)) { | |
3103 | IWL_DEBUG_MAC80211(priv, "invalid channel\n"); | |
3104 | goto out; | |
3105 | } | |
3106 | spin_lock_irqsave(&priv->lock, flags); | |
3107 | ||
3108 | priv->current_ht_config.smps = conf->smps_mode; | |
3109 | ||
3110 | /* Configure HT40 channels */ | |
7e6a5886 JB |
3111 | ctx->ht.enabled = conf_is_ht(conf); |
3112 | if (ctx->ht.enabled) { | |
79d07325 | 3113 | if (conf_is_ht40_minus(conf)) { |
7e6a5886 | 3114 | ctx->ht.extension_chan_offset = |
79d07325 | 3115 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; |
7e6a5886 | 3116 | ctx->ht.is_40mhz = true; |
79d07325 | 3117 | } else if (conf_is_ht40_plus(conf)) { |
7e6a5886 | 3118 | ctx->ht.extension_chan_offset = |
79d07325 | 3119 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; |
7e6a5886 | 3120 | ctx->ht.is_40mhz = true; |
79d07325 | 3121 | } else { |
7e6a5886 | 3122 | ctx->ht.extension_chan_offset = |
79d07325 | 3123 | IEEE80211_HT_PARAM_CHA_SEC_NONE; |
7e6a5886 | 3124 | ctx->ht.is_40mhz = false; |
79d07325 WYG |
3125 | } |
3126 | } else | |
7e6a5886 | 3127 | ctx->ht.is_40mhz = false; |
79d07325 | 3128 | |
246ed355 JB |
3129 | if ((le16_to_cpu(ctx->staging.channel) != ch)) |
3130 | ctx->staging.flags = 0; | |
79d07325 | 3131 | |
246ed355 | 3132 | iwl_set_rxon_channel(priv, channel, ctx); |
79d07325 | 3133 | iwl_set_rxon_ht(priv, ht_conf); |
246ed355 | 3134 | iwl_set_flags_for_band(priv, ctx, channel->band, |
8bd413e6 | 3135 | ctx->vif); |
79d07325 WYG |
3136 | spin_unlock_irqrestore(&priv->lock, flags); |
3137 | ||
3138 | iwl_set_rate(priv); | |
3139 | /* | |
3140 | * at this point, staging_rxon has the | |
3141 | * configuration for channel switch | |
3142 | */ | |
3143 | if (priv->cfg->ops->lib->set_channel_switch(priv, | |
3144 | ch_switch)) | |
3145 | priv->switch_rxon.switch_in_progress = false; | |
3146 | } | |
3147 | } | |
3148 | out: | |
3149 | mutex_unlock(&priv->mutex); | |
79d07325 | 3150 | if (!priv->switch_rxon.switch_in_progress) |
8bd413e6 | 3151 | ieee80211_chswitch_done(ctx->vif, false); |
79d07325 WYG |
3152 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
3153 | } | |
3154 | ||
2dedbf58 JB |
3155 | static void iwlagn_configure_filter(struct ieee80211_hw *hw, |
3156 | unsigned int changed_flags, | |
3157 | unsigned int *total_flags, | |
3158 | u64 multicast) | |
8b8ab9d5 JB |
3159 | { |
3160 | struct iwl_priv *priv = hw->priv; | |
3161 | __le32 filter_or = 0, filter_nand = 0; | |
246ed355 | 3162 | struct iwl_rxon_context *ctx; |
8b8ab9d5 JB |
3163 | |
3164 | #define CHK(test, flag) do { \ | |
3165 | if (*total_flags & (test)) \ | |
3166 | filter_or |= (flag); \ | |
3167 | else \ | |
3168 | filter_nand |= (flag); \ | |
3169 | } while (0) | |
3170 | ||
3171 | IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n", | |
3172 | changed_flags, *total_flags); | |
3173 | ||
3174 | CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); | |
bdb84fec JB |
3175 | /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */ |
3176 | CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); | |
8b8ab9d5 JB |
3177 | CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); |
3178 | ||
3179 | #undef CHK | |
3180 | ||
3181 | mutex_lock(&priv->mutex); | |
3182 | ||
246ed355 JB |
3183 | for_each_context(priv, ctx) { |
3184 | ctx->staging.filter_flags &= ~filter_nand; | |
3185 | ctx->staging.filter_flags |= filter_or; | |
749ff4ef SG |
3186 | |
3187 | /* | |
3188 | * Not committing directly because hardware can perform a scan, | |
3189 | * but we'll eventually commit the filter flags change anyway. | |
3190 | */ | |
246ed355 | 3191 | } |
8b8ab9d5 JB |
3192 | |
3193 | mutex_unlock(&priv->mutex); | |
3194 | ||
3195 | /* | |
3196 | * Receiving all multicast frames is always enabled by the | |
3197 | * default flags setup in iwl_connection_init_rx_config() | |
3198 | * since we currently do not support programming multicast | |
3199 | * filters into the device. | |
3200 | */ | |
3201 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
3202 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
3203 | } | |
3204 | ||
2dedbf58 | 3205 | static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop) |
716c74b0 WYG |
3206 | { |
3207 | struct iwl_priv *priv = hw->priv; | |
3208 | ||
3209 | mutex_lock(&priv->mutex); | |
3210 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3211 | ||
3212 | /* do not support "flush" */ | |
3213 | if (!priv->cfg->ops->lib->txfifo_flush) | |
3214 | goto done; | |
3215 | ||
3216 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
3217 | IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n"); | |
3218 | goto done; | |
3219 | } | |
3220 | if (iwl_is_rfkill(priv)) { | |
3221 | IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n"); | |
3222 | goto done; | |
3223 | } | |
3224 | ||
3225 | /* | |
3226 | * mac80211 will not push any more frames for transmit | |
3227 | * until the flush is completed | |
3228 | */ | |
3229 | if (drop) { | |
3230 | IWL_DEBUG_MAC80211(priv, "send flush command\n"); | |
3231 | if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) { | |
3232 | IWL_ERR(priv, "flush request fail\n"); | |
3233 | goto done; | |
3234 | } | |
3235 | } | |
3236 | IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n"); | |
3237 | iwlagn_wait_tx_queue_empty(priv); | |
3238 | done: | |
3239 | mutex_unlock(&priv->mutex); | |
3240 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
3241 | } | |
3242 | ||
9b9190d9 JB |
3243 | static void iwlagn_disable_roc(struct iwl_priv *priv) |
3244 | { | |
3245 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN]; | |
3246 | struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel); | |
3247 | ||
3248 | lockdep_assert_held(&priv->mutex); | |
3249 | ||
3250 | if (!ctx->is_active) | |
3251 | return; | |
3252 | ||
3253 | ctx->staging.dev_type = RXON_DEV_TYPE_2STA; | |
3254 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
3255 | iwl_set_rxon_channel(priv, chan, ctx); | |
3256 | iwl_set_flags_for_band(priv, ctx, chan->band, NULL); | |
3257 | ||
3258 | priv->_agn.hw_roc_channel = NULL; | |
3259 | ||
80b38fff | 3260 | iwlcore_commit_rxon(priv, ctx); |
9b9190d9 JB |
3261 | |
3262 | ctx->is_active = false; | |
3263 | } | |
3264 | ||
3265 | static void iwlagn_bg_roc_done(struct work_struct *work) | |
3266 | { | |
3267 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
3268 | _agn.hw_roc_work.work); | |
3269 | ||
3270 | mutex_lock(&priv->mutex); | |
3271 | ieee80211_remain_on_channel_expired(priv->hw); | |
3272 | iwlagn_disable_roc(priv); | |
3273 | mutex_unlock(&priv->mutex); | |
3274 | } | |
3275 | ||
3276 | static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw, | |
3277 | struct ieee80211_channel *channel, | |
3278 | enum nl80211_channel_type channel_type, | |
3279 | int duration) | |
3280 | { | |
3281 | struct iwl_priv *priv = hw->priv; | |
3282 | int err = 0; | |
3283 | ||
3284 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | |
3285 | return -EOPNOTSUPP; | |
3286 | ||
3287 | if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes & | |
3288 | BIT(NL80211_IFTYPE_P2P_CLIENT))) | |
3289 | return -EOPNOTSUPP; | |
3290 | ||
3291 | mutex_lock(&priv->mutex); | |
3292 | ||
3293 | if (priv->contexts[IWL_RXON_CTX_PAN].is_active || | |
3294 | test_bit(STATUS_SCAN_HW, &priv->status)) { | |
3295 | err = -EBUSY; | |
3296 | goto out; | |
3297 | } | |
3298 | ||
3299 | priv->contexts[IWL_RXON_CTX_PAN].is_active = true; | |
3300 | priv->_agn.hw_roc_channel = channel; | |
3301 | priv->_agn.hw_roc_chantype = channel_type; | |
3302 | priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024); | |
80b38fff | 3303 | iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]); |
9b9190d9 JB |
3304 | queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work, |
3305 | msecs_to_jiffies(duration + 20)); | |
3306 | ||
94073919 | 3307 | msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */ |
9b9190d9 JB |
3308 | ieee80211_ready_on_channel(priv->hw); |
3309 | ||
3310 | out: | |
3311 | mutex_unlock(&priv->mutex); | |
3312 | ||
3313 | return err; | |
3314 | } | |
3315 | ||
3316 | static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw) | |
3317 | { | |
3318 | struct iwl_priv *priv = hw->priv; | |
3319 | ||
3320 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | |
3321 | return -EOPNOTSUPP; | |
3322 | ||
3323 | cancel_delayed_work_sync(&priv->_agn.hw_roc_work); | |
3324 | ||
3325 | mutex_lock(&priv->mutex); | |
3326 | iwlagn_disable_roc(priv); | |
3327 | mutex_unlock(&priv->mutex); | |
3328 | ||
3329 | return 0; | |
3330 | } | |
3331 | ||
b481de9c ZY |
3332 | /***************************************************************************** |
3333 | * | |
3334 | * driver setup and teardown | |
3335 | * | |
3336 | *****************************************************************************/ | |
3337 | ||
4e39317d | 3338 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3339 | { |
d21050c7 | 3340 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3341 | |
3342 | init_waitqueue_head(&priv->wait_command_queue); | |
3343 | ||
5b9f8cd3 EG |
3344 | INIT_WORK(&priv->restart, iwl_bg_restart); |
3345 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 3346 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 3347 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
65550636 | 3348 | INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush); |
bee008b7 | 3349 | INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency); |
fbba9410 | 3350 | INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config); |
9b9190d9 | 3351 | INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done); |
2a421b91 | 3352 | |
2a421b91 | 3353 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 3354 | |
4e39317d EG |
3355 | if (priv->cfg->ops->lib->setup_deferred_work) |
3356 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3357 | ||
3358 | init_timer(&priv->statistics_periodic); | |
3359 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3360 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 3361 | |
a9e1cb6a WYG |
3362 | init_timer(&priv->ucode_trace); |
3363 | priv->ucode_trace.data = (unsigned long)priv; | |
3364 | priv->ucode_trace.function = iwl_bg_ucode_trace; | |
3365 | ||
22de94de SG |
3366 | init_timer(&priv->watchdog); |
3367 | priv->watchdog.data = (unsigned long)priv; | |
3368 | priv->watchdog.function = iwl_bg_watchdog; | |
b74e31a9 | 3369 | |
d6b80618 WYG |
3370 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) |
3371 | iwl_irq_tasklet, (unsigned long)priv); | |
b481de9c ZY |
3372 | } |
3373 | ||
4e39317d | 3374 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3375 | { |
4e39317d EG |
3376 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3377 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3378 | |
815e629b | 3379 | cancel_work_sync(&priv->run_time_calib_work); |
b481de9c | 3380 | cancel_work_sync(&priv->beacon_update); |
e7e16b90 SG |
3381 | |
3382 | iwl_cancel_scan_deferred_work(priv); | |
3383 | ||
bee008b7 | 3384 | cancel_work_sync(&priv->bt_full_concurrency); |
fbba9410 | 3385 | cancel_work_sync(&priv->bt_runtime_config); |
e7e16b90 | 3386 | |
4e39317d | 3387 | del_timer_sync(&priv->statistics_periodic); |
a9e1cb6a | 3388 | del_timer_sync(&priv->ucode_trace); |
b481de9c ZY |
3389 | } |
3390 | ||
89f186a8 RC |
3391 | static void iwl_init_hw_rates(struct iwl_priv *priv, |
3392 | struct ieee80211_rate *rates) | |
3393 | { | |
3394 | int i; | |
3395 | ||
3396 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { | |
3397 | rates[i].bitrate = iwl_rates[i].ieee * 5; | |
3398 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
3399 | rates[i].hw_value_short = i; | |
3400 | rates[i].flags = 0; | |
3401 | if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) { | |
3402 | /* | |
3403 | * If CCK != 1M then set short preamble rate flag. | |
3404 | */ | |
3405 | rates[i].flags |= | |
3406 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
3407 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
3408 | } | |
3409 | } | |
3410 | } | |
3411 | ||
3412 | static int iwl_init_drv(struct iwl_priv *priv) | |
3413 | { | |
3414 | int ret; | |
3415 | ||
89f186a8 RC |
3416 | spin_lock_init(&priv->sta_lock); |
3417 | spin_lock_init(&priv->hcmd_lock); | |
3418 | ||
3419 | INIT_LIST_HEAD(&priv->free_frames); | |
3420 | ||
3421 | mutex_init(&priv->mutex); | |
3422 | ||
89f186a8 RC |
3423 | priv->ieee_channels = NULL; |
3424 | priv->ieee_rates = NULL; | |
3425 | priv->band = IEEE80211_BAND_2GHZ; | |
3426 | ||
3427 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
ba37a3d0 | 3428 | priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; |
a13d276f | 3429 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
d5a0ffa3 | 3430 | priv->_agn.agg_tids_count = 0; |
89f186a8 | 3431 | |
8a472da4 WYG |
3432 | /* initialize force reset */ |
3433 | priv->force_reset[IWL_RF_RESET].reset_duration = | |
3434 | IWL_DELAY_NEXT_FORCE_RF_RESET; | |
3435 | priv->force_reset[IWL_FW_RESET].reset_duration = | |
3436 | IWL_DELAY_NEXT_FORCE_FW_RELOAD; | |
89f186a8 | 3437 | |
410f2bb3 SG |
3438 | priv->rx_statistics_jiffies = jiffies; |
3439 | ||
89f186a8 RC |
3440 | /* Choose which receivers/antennas to use */ |
3441 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 JB |
3442 | priv->cfg->ops->hcmd->set_rxon_chain(priv, |
3443 | &priv->contexts[IWL_RXON_CTX_BSS]); | |
89f186a8 RC |
3444 | |
3445 | iwl_init_scan_params(priv); | |
3446 | ||
22bf59a0 | 3447 | /* init bt coex */ |
7cb1b088 WYG |
3448 | if (priv->cfg->bt_params && |
3449 | priv->cfg->bt_params->advanced_bt_coexist) { | |
b6e116e8 WYG |
3450 | priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; |
3451 | priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; | |
3452 | priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; | |
22bf59a0 WYG |
3453 | priv->bt_on_thresh = BT_ON_THRESHOLD_DEF; |
3454 | priv->bt_duration = BT_DURATION_LIMIT_DEF; | |
3455 | priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF; | |
22bf59a0 WYG |
3456 | } |
3457 | ||
89f186a8 RC |
3458 | ret = iwl_init_channel_map(priv); |
3459 | if (ret) { | |
3460 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3461 | goto err; | |
3462 | } | |
3463 | ||
3464 | ret = iwlcore_init_geos(priv); | |
3465 | if (ret) { | |
3466 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3467 | goto err_free_channel_map; | |
3468 | } | |
3469 | iwl_init_hw_rates(priv, priv->ieee_rates); | |
3470 | ||
3471 | return 0; | |
3472 | ||
3473 | err_free_channel_map: | |
3474 | iwl_free_channel_map(priv); | |
3475 | err: | |
3476 | return ret; | |
3477 | } | |
3478 | ||
3479 | static void iwl_uninit_drv(struct iwl_priv *priv) | |
3480 | { | |
3481 | iwl_calib_free_results(priv); | |
3482 | iwlcore_free_geos(priv); | |
3483 | iwl_free_channel_map(priv); | |
811ecc99 | 3484 | kfree(priv->scan_cmd); |
89f186a8 RC |
3485 | } |
3486 | ||
dc21b545 | 3487 | struct ieee80211_ops iwlagn_hw_ops = { |
2295c66b JB |
3488 | .tx = iwlagn_mac_tx, |
3489 | .start = iwlagn_mac_start, | |
3490 | .stop = iwlagn_mac_stop, | |
5b9f8cd3 EG |
3491 | .add_interface = iwl_mac_add_interface, |
3492 | .remove_interface = iwl_mac_remove_interface, | |
d4daaea6 | 3493 | .change_interface = iwl_mac_change_interface, |
2295c66b | 3494 | .config = iwlagn_mac_config, |
8b8ab9d5 | 3495 | .configure_filter = iwlagn_configure_filter, |
2295c66b JB |
3496 | .set_key = iwlagn_mac_set_key, |
3497 | .update_tkip_key = iwlagn_mac_update_tkip_key, | |
5b9f8cd3 | 3498 | .conf_tx = iwl_mac_conf_tx, |
2295c66b JB |
3499 | .bss_info_changed = iwlagn_bss_info_changed, |
3500 | .ampdu_action = iwlagn_mac_ampdu_action, | |
6ab10ff8 | 3501 | .hw_scan = iwl_mac_hw_scan, |
2295c66b | 3502 | .sta_notify = iwlagn_mac_sta_notify, |
fe6b23dd RC |
3503 | .sta_add = iwlagn_mac_sta_add, |
3504 | .sta_remove = iwl_mac_sta_remove, | |
2295c66b JB |
3505 | .channel_switch = iwlagn_mac_channel_switch, |
3506 | .flush = iwlagn_mac_flush, | |
a85d7cca | 3507 | .tx_last_beacon = iwl_mac_tx_last_beacon, |
9b9190d9 JB |
3508 | .remain_on_channel = iwl_mac_remain_on_channel, |
3509 | .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel, | |
266af4c7 JB |
3510 | .offchannel_tx = iwl_mac_offchannel_tx, |
3511 | .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait, | |
4613e72d | 3512 | CFG80211_TESTMODE_CMD(iwl_testmode_cmd) |
b481de9c ZY |
3513 | }; |
3514 | ||
e98a1302 | 3515 | static u32 iwl_hw_detect(struct iwl_priv *priv) |
3867fe04 | 3516 | { |
c2974a1d JB |
3517 | u8 rev_id; |
3518 | ||
3519 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id); | |
3520 | IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id); | |
02a7fa00 | 3521 | return iwl_read32(priv, CSR_HW_REV); |
3867fe04 WYG |
3522 | } |
3523 | ||
07d4f1ad WYG |
3524 | static int iwl_set_hw_params(struct iwl_priv *priv) |
3525 | { | |
3526 | priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; | |
3527 | priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
9d143e9a | 3528 | if (iwlagn_mod_params.amsdu_size_8K) |
07d4f1ad WYG |
3529 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K); |
3530 | else | |
3531 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K); | |
3532 | ||
3533 | priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL; | |
3534 | ||
9d143e9a | 3535 | if (iwlagn_mod_params.disable_11n) |
07d4f1ad WYG |
3536 | priv->cfg->sku &= ~IWL_SKU_N; |
3537 | ||
3538 | /* Device-specific setup */ | |
3539 | return priv->cfg->ops->lib->set_hw_params(priv); | |
3540 | } | |
3541 | ||
e72f368b JB |
3542 | static const u8 iwlagn_bss_ac_to_fifo[] = { |
3543 | IWL_TX_FIFO_VO, | |
3544 | IWL_TX_FIFO_VI, | |
3545 | IWL_TX_FIFO_BE, | |
3546 | IWL_TX_FIFO_BK, | |
3547 | }; | |
3548 | ||
3549 | static const u8 iwlagn_bss_ac_to_queue[] = { | |
3550 | 0, 1, 2, 3, | |
3551 | }; | |
3552 | ||
3553 | static const u8 iwlagn_pan_ac_to_fifo[] = { | |
3554 | IWL_TX_FIFO_VO_IPAN, | |
3555 | IWL_TX_FIFO_VI_IPAN, | |
3556 | IWL_TX_FIFO_BE_IPAN, | |
3557 | IWL_TX_FIFO_BK_IPAN, | |
3558 | }; | |
3559 | ||
3560 | static const u8 iwlagn_pan_ac_to_queue[] = { | |
3561 | 7, 6, 5, 4, | |
3562 | }; | |
3563 | ||
119ea186 WYG |
3564 | /* This function both allocates and initializes hw and priv. */ |
3565 | static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg) | |
3566 | { | |
3567 | struct iwl_priv *priv; | |
3568 | /* mac80211 allocates memory for this device instance, including | |
3569 | * space for this driver's private structure */ | |
3570 | struct ieee80211_hw *hw; | |
3571 | ||
3572 | hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops); | |
3573 | if (hw == NULL) { | |
3574 | pr_err("%s: Can not allocate network device\n", | |
3575 | cfg->name); | |
3576 | goto out; | |
3577 | } | |
3578 | ||
3579 | priv = hw->priv; | |
3580 | priv->hw = hw; | |
3581 | ||
3582 | out: | |
3583 | return hw; | |
3584 | } | |
3585 | ||
5b9f8cd3 | 3586 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c | 3587 | { |
246ed355 | 3588 | int err = 0, i; |
c79dd5b5 | 3589 | struct iwl_priv *priv; |
b481de9c | 3590 | struct ieee80211_hw *hw; |
82b9a121 | 3591 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 3592 | unsigned long flags; |
c6fa17ed | 3593 | u16 pci_cmd, num_mac; |
e98a1302 | 3594 | u32 hw_rev; |
b481de9c | 3595 | |
316c30d9 AK |
3596 | /************************ |
3597 | * 1. Allocating HW data | |
3598 | ************************/ | |
3599 | ||
dc21b545 | 3600 | hw = iwl_alloc_all(cfg); |
1d0a082d | 3601 | if (!hw) { |
b481de9c ZY |
3602 | err = -ENOMEM; |
3603 | goto out; | |
3604 | } | |
1d0a082d AK |
3605 | priv = hw->priv; |
3606 | /* At this point both hw and priv are allocated. */ | |
3607 | ||
ca7966c8 JB |
3608 | priv->ucode_type = UCODE_SUBTYPE_NONE_LOADED; |
3609 | ||
246ed355 JB |
3610 | /* |
3611 | * The default context is always valid, | |
3612 | * more may be discovered when firmware | |
3613 | * is loaded. | |
3614 | */ | |
3615 | priv->valid_contexts = BIT(IWL_RXON_CTX_BSS); | |
3616 | ||
3617 | for (i = 0; i < NUM_IWL_RXON_CTX; i++) | |
3618 | priv->contexts[i].ctxid = i; | |
3619 | ||
763cc3bf JB |
3620 | priv->contexts[IWL_RXON_CTX_BSS].always_active = true; |
3621 | priv->contexts[IWL_RXON_CTX_BSS].is_active = true; | |
8f2d3d2a JB |
3622 | priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON; |
3623 | priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING; | |
3624 | priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC; | |
8dfdb9d5 | 3625 | priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM; |
2995bafa | 3626 | priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID; |
c10afb6e | 3627 | priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY; |
e72f368b JB |
3628 | priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo; |
3629 | priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue; | |
d0fe478c JB |
3630 | priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes = |
3631 | BIT(NL80211_IFTYPE_ADHOC); | |
3632 | priv->contexts[IWL_RXON_CTX_BSS].interface_modes = | |
3633 | BIT(NL80211_IFTYPE_STATION); | |
2295c66b | 3634 | priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP; |
d0fe478c JB |
3635 | priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS; |
3636 | priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS; | |
3637 | priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS; | |
ece9c4ee JB |
3638 | |
3639 | priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON; | |
3640 | priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING; | |
3641 | priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC; | |
3642 | priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM; | |
3643 | priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN; | |
3644 | priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY; | |
3645 | priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID; | |
3646 | priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION; | |
e72f368b JB |
3647 | priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo; |
3648 | priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue; | |
3649 | priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE; | |
d0fe478c JB |
3650 | priv->contexts[IWL_RXON_CTX_PAN].interface_modes = |
3651 | BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP); | |
f35c0c56 WYG |
3652 | #ifdef CONFIG_IWL_P2P |
3653 | priv->contexts[IWL_RXON_CTX_PAN].interface_modes |= | |
3654 | BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO); | |
3655 | #endif | |
d0fe478c JB |
3656 | priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP; |
3657 | priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA; | |
3658 | priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P; | |
ece9c4ee JB |
3659 | |
3660 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); | |
8f2d3d2a | 3661 | |
b481de9c ZY |
3662 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3663 | ||
e1623446 | 3664 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 3665 | priv->cfg = cfg; |
b481de9c | 3666 | priv->pci_dev = pdev; |
40cefda9 | 3667 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 3668 | |
bee008b7 WYG |
3669 | /* is antenna coupling more than 35dB ? */ |
3670 | priv->bt_ant_couple_ok = | |
3671 | (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ? | |
3672 | true : false; | |
3673 | ||
9f28ebc3 | 3674 | /* enable/disable bt channel inhibition */ |
f37837c9 | 3675 | priv->bt_ch_announce = iwlagn_bt_ch_announce; |
9f28ebc3 WYG |
3676 | IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n", |
3677 | (priv->bt_ch_announce) ? "On" : "Off"); | |
f37837c9 | 3678 | |
20594eb0 WYG |
3679 | if (iwl_alloc_traffic_mem(priv)) |
3680 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 3681 | |
316c30d9 AK |
3682 | /************************** |
3683 | * 2. Initializing PCI bus | |
3684 | **************************/ | |
1a7123cd JL |
3685 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
3686 | PCIE_LINK_STATE_CLKPM); | |
3687 | ||
316c30d9 AK |
3688 | if (pci_enable_device(pdev)) { |
3689 | err = -ENODEV; | |
3690 | goto out_ieee80211_free_hw; | |
3691 | } | |
3692 | ||
3693 | pci_set_master(pdev); | |
3694 | ||
093d874c | 3695 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 3696 | if (!err) |
093d874c | 3697 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 3698 | if (err) { |
093d874c | 3699 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3700 | if (!err) |
093d874c | 3701 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3702 | /* both attempts failed: */ |
316c30d9 | 3703 | if (err) { |
978785a3 | 3704 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 3705 | goto out_pci_disable_device; |
cc2a8ea8 | 3706 | } |
316c30d9 AK |
3707 | } |
3708 | ||
3709 | err = pci_request_regions(pdev, DRV_NAME); | |
3710 | if (err) | |
3711 | goto out_pci_disable_device; | |
3712 | ||
3713 | pci_set_drvdata(pdev, priv); | |
3714 | ||
316c30d9 AK |
3715 | |
3716 | /*********************** | |
3717 | * 3. Read REV register | |
3718 | ***********************/ | |
3719 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
3720 | if (!priv->hw_base) { | |
3721 | err = -ENODEV; | |
3722 | goto out_pci_release_regions; | |
3723 | } | |
3724 | ||
e1623446 | 3725 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 3726 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 3727 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 3728 | |
731a29b7 | 3729 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
3730 | * we should init now |
3731 | */ | |
3732 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 3733 | spin_lock_init(&priv->lock); |
4843b5a7 RC |
3734 | |
3735 | /* | |
3736 | * stop and reset the on-board processor just in case it is in a | |
3737 | * strange state ... like being left stranded by a primary kernel | |
3738 | * and this is now the kdump kernel trying to start up | |
3739 | */ | |
3740 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
3741 | ||
e98a1302 | 3742 | hw_rev = iwl_hw_detect(priv); |
c11362c0 | 3743 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", |
e98a1302 | 3744 | priv->cfg->name, hw_rev); |
316c30d9 | 3745 | |
e7b63581 TW |
3746 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3747 | * PCI Tx retries from interfering with C3 CPU state */ | |
3748 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3749 | ||
4cd2bf76 | 3750 | if (iwl_prepare_card_hw(priv)) { |
086ed117 MA |
3751 | IWL_WARN(priv, "Failed, HW not ready\n"); |
3752 | goto out_iounmap; | |
3753 | } | |
3754 | ||
91238714 TW |
3755 | /***************** |
3756 | * 4. Read EEPROM | |
3757 | *****************/ | |
316c30d9 | 3758 | /* Read the EEPROM */ |
e98a1302 | 3759 | err = iwl_eeprom_init(priv, hw_rev); |
316c30d9 | 3760 | if (err) { |
15b1687c | 3761 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
3762 | goto out_iounmap; |
3763 | } | |
8614f360 TW |
3764 | err = iwl_eeprom_check_version(priv); |
3765 | if (err) | |
c8f16138 | 3766 | goto out_free_eeprom; |
8614f360 | 3767 | |
21a5b3c6 WYG |
3768 | err = iwl_eeprom_check_sku(priv); |
3769 | if (err) | |
3770 | goto out_free_eeprom; | |
3771 | ||
02883017 | 3772 | /* extract MAC Address */ |
c6fa17ed WYG |
3773 | iwl_eeprom_get_mac(priv, priv->addresses[0].addr); |
3774 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr); | |
3775 | priv->hw->wiphy->addresses = priv->addresses; | |
3776 | priv->hw->wiphy->n_addresses = 1; | |
3777 | num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS); | |
3778 | if (num_mac > 1) { | |
3779 | memcpy(priv->addresses[1].addr, priv->addresses[0].addr, | |
3780 | ETH_ALEN); | |
3781 | priv->addresses[1].addr[5]++; | |
3782 | priv->hw->wiphy->n_addresses++; | |
3783 | } | |
316c30d9 AK |
3784 | |
3785 | /************************ | |
3786 | * 5. Setup HW constants | |
3787 | ************************/ | |
da154e30 | 3788 | if (iwl_set_hw_params(priv)) { |
15b1687c | 3789 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 3790 | goto out_free_eeprom; |
316c30d9 AK |
3791 | } |
3792 | ||
3793 | /******************* | |
6ba87956 | 3794 | * 6. Setup priv |
316c30d9 | 3795 | *******************/ |
b481de9c | 3796 | |
6ba87956 | 3797 | err = iwl_init_drv(priv); |
bf85ea4f | 3798 | if (err) |
399f4900 | 3799 | goto out_free_eeprom; |
bf85ea4f | 3800 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 3801 | |
316c30d9 | 3802 | /******************** |
09f9bf79 | 3803 | * 7. Setup services |
316c30d9 | 3804 | ********************/ |
0359facc | 3805 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 3806 | iwl_disable_interrupts(priv); |
0359facc | 3807 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 3808 | |
6cd0b1cb HS |
3809 | pci_enable_msi(priv->pci_dev); |
3810 | ||
519d8abd | 3811 | iwl_alloc_isr_ict(priv); |
e39fdee1 | 3812 | |
519d8abd | 3813 | err = request_irq(priv->pci_dev->irq, iwl_isr_ict, |
ef850d7c | 3814 | IRQF_SHARED, DRV_NAME, priv); |
6cd0b1cb HS |
3815 | if (err) { |
3816 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
3817 | goto out_disable_msi; | |
3818 | } | |
316c30d9 | 3819 | |
4e39317d | 3820 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3821 | iwl_setup_rx_handlers(priv); |
4613e72d | 3822 | iwl_testmode_init(priv); |
316c30d9 | 3823 | |
158bea07 JB |
3824 | /********************************************* |
3825 | * 8. Enable interrupts and read RFKILL state | |
3826 | *********************************************/ | |
6ba87956 | 3827 | |
554d1d02 | 3828 | /* enable rfkill interrupt: hw bug w/a */ |
6cd0b1cb HS |
3829 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); |
3830 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
3831 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
3832 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
3833 | } | |
3834 | ||
554d1d02 | 3835 | iwl_enable_rfkill_int(priv); |
6cd0b1cb | 3836 | |
6cd0b1cb HS |
3837 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3838 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3839 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3840 | else | |
3841 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3842 | |
a60e77e5 JB |
3843 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
3844 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 3845 | |
58d0f361 | 3846 | iwl_power_initialize(priv); |
39b73fb1 | 3847 | iwl_tt_initialize(priv); |
158bea07 | 3848 | |
a15707d8 | 3849 | init_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 3850 | |
b08dfd04 | 3851 | err = iwl_request_firmware(priv, true); |
158bea07 | 3852 | if (err) |
7d47618a | 3853 | goto out_destroy_workqueue; |
158bea07 | 3854 | |
b481de9c ZY |
3855 | return 0; |
3856 | ||
7d47618a | 3857 | out_destroy_workqueue: |
c8f16138 RC |
3858 | destroy_workqueue(priv->workqueue); |
3859 | priv->workqueue = NULL; | |
795cc0ad | 3860 | free_irq(priv->pci_dev->irq, priv); |
519d8abd | 3861 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
3862 | out_disable_msi: |
3863 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 3864 | iwl_uninit_drv(priv); |
073d3f5f TW |
3865 | out_free_eeprom: |
3866 | iwl_eeprom_free(priv); | |
b481de9c ZY |
3867 | out_iounmap: |
3868 | pci_iounmap(pdev, priv->hw_base); | |
3869 | out_pci_release_regions: | |
316c30d9 | 3870 | pci_set_drvdata(pdev, NULL); |
623d563e | 3871 | pci_release_regions(pdev); |
b481de9c ZY |
3872 | out_pci_disable_device: |
3873 | pci_disable_device(pdev); | |
b481de9c | 3874 | out_ieee80211_free_hw: |
20594eb0 | 3875 | iwl_free_traffic_mem(priv); |
d7c76f4c | 3876 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
3877 | out: |
3878 | return err; | |
3879 | } | |
3880 | ||
5b9f8cd3 | 3881 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 3882 | { |
c79dd5b5 | 3883 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 3884 | unsigned long flags; |
b481de9c ZY |
3885 | |
3886 | if (!priv) | |
3887 | return; | |
3888 | ||
a15707d8 | 3889 | wait_for_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 3890 | |
e1623446 | 3891 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 3892 | |
67249625 | 3893 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 3894 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 3895 | |
5b9f8cd3 EG |
3896 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
3897 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
3898 | * we need to set STATUS_EXIT_PENDING bit. |
3899 | */ | |
3900 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5ed540ae WYG |
3901 | |
3902 | iwl_leds_exit(priv); | |
3903 | ||
c4f55232 RR |
3904 | if (priv->mac80211_registered) { |
3905 | ieee80211_unregister_hw(priv->hw); | |
3906 | priv->mac80211_registered = 0; | |
3907 | } | |
3908 | ||
1a10f433 | 3909 | /* Reset to low power before unloading driver. */ |
14e8e4af | 3910 | iwl_apm_stop(priv); |
c166b25a | 3911 | |
39b73fb1 WYG |
3912 | iwl_tt_exit(priv); |
3913 | ||
0359facc MA |
3914 | /* make sure we flush any pending irq or |
3915 | * tasklet for the driver | |
3916 | */ | |
3917 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 3918 | iwl_disable_interrupts(priv); |
0359facc MA |
3919 | spin_unlock_irqrestore(&priv->lock, flags); |
3920 | ||
3921 | iwl_synchronize_irq(priv); | |
3922 | ||
5b9f8cd3 | 3923 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
3924 | |
3925 | if (priv->rxq.bd) | |
54b81550 | 3926 | iwlagn_rx_queue_free(priv, &priv->rxq); |
74bcdb33 | 3927 | iwlagn_hw_txq_ctx_free(priv); |
b481de9c | 3928 | |
073d3f5f | 3929 | iwl_eeprom_free(priv); |
b481de9c | 3930 | |
b481de9c | 3931 | |
948c171c MA |
3932 | /*netif_stop_queue(dev); */ |
3933 | flush_workqueue(priv->workqueue); | |
3934 | ||
5b9f8cd3 | 3935 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3936 | * priv->workqueue... so we can't take down the workqueue |
3937 | * until now... */ | |
3938 | destroy_workqueue(priv->workqueue); | |
3939 | priv->workqueue = NULL; | |
20594eb0 | 3940 | iwl_free_traffic_mem(priv); |
b481de9c | 3941 | |
6cd0b1cb HS |
3942 | free_irq(priv->pci_dev->irq, priv); |
3943 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
3944 | pci_iounmap(pdev, priv->hw_base); |
3945 | pci_release_regions(pdev); | |
3946 | pci_disable_device(pdev); | |
3947 | pci_set_drvdata(pdev, NULL); | |
3948 | ||
6ba87956 | 3949 | iwl_uninit_drv(priv); |
b481de9c | 3950 | |
519d8abd | 3951 | iwl_free_isr_ict(priv); |
ef850d7c | 3952 | |
77834543 | 3953 | dev_kfree_skb(priv->beacon_skb); |
b481de9c ZY |
3954 | |
3955 | ieee80211_free_hw(priv->hw); | |
3956 | } | |
3957 | ||
b481de9c ZY |
3958 | |
3959 | /***************************************************************************** | |
3960 | * | |
3961 | * driver and module entry point | |
3962 | * | |
3963 | *****************************************************************************/ | |
3964 | ||
fed9017e | 3965 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
a3aa1884 | 3966 | static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = { |
ac592574 WYG |
3967 | {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */ |
3968 | {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3969 | {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */ | |
3970 | {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3971 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3972 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3973 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */ | |
3974 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3975 | {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */ | |
3976 | {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3977 | {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */ | |
3978 | {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3979 | {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3980 | {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3981 | {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */ | |
3982 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3983 | {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */ | |
3984 | {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3985 | {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */ | |
3986 | {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3987 | {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3988 | {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3989 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */ | |
3990 | {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3991 | ||
3992 | /* 5300 Series WiFi */ | |
3993 | {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */ | |
3994 | {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3995 | {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */ | |
3996 | {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3997 | {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */ | |
3998 | {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
3999 | {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */ | |
4000 | {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4001 | {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */ | |
4002 | {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4003 | {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */ | |
4004 | {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4005 | ||
4006 | /* 5350 Series WiFi/WiMax */ | |
4007 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */ | |
4008 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */ | |
4009 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */ | |
4010 | ||
4011 | /* 5150 Series Wifi/WiMax */ | |
4012 | {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */ | |
4013 | {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4014 | {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */ | |
4015 | {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
4016 | {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */ | |
4017 | {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4018 | ||
4019 | {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */ | |
4020 | {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4021 | {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */ | |
4022 | {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
5953a62e WYG |
4023 | |
4024 | /* 6x00 Series */ | |
5953a62e WYG |
4025 | {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)}, |
4026 | {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)}, | |
4027 | {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)}, | |
4028 | {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)}, | |
4029 | {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)}, | |
4030 | {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)}, | |
4031 | {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)}, | |
4032 | {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)}, | |
4033 | {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)}, | |
4034 | {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)}, | |
4b3e8062 | 4035 | |
003ea981 | 4036 | /* 6x05 Series */ |
8b3ee296 WYG |
4037 | {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)}, |
4038 | {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)}, | |
4039 | {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)}, | |
4040 | {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)}, | |
4041 | {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)}, | |
4042 | {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)}, | |
4043 | {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)}, | |
1808972f | 4044 | |
003ea981 | 4045 | /* 6x30 Series */ |
8b3ee296 WYG |
4046 | {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)}, |
4047 | {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)}, | |
4048 | {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)}, | |
4049 | {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)}, | |
4050 | {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)}, | |
4051 | {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)}, | |
4052 | {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)}, | |
4053 | {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)}, | |
4054 | {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)}, | |
4055 | {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)}, | |
4056 | {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)}, | |
4057 | {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)}, | |
4058 | {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)}, | |
4059 | {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)}, | |
4060 | {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)}, | |
4061 | {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)}, | |
5953a62e WYG |
4062 | |
4063 | /* 6x50 WiFi/WiMax Series */ | |
5953a62e WYG |
4064 | {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)}, |
4065 | {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)}, | |
4066 | {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)}, | |
4067 | {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)}, | |
5953a62e WYG |
4068 | {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)}, |
4069 | {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)}, | |
4070 | ||
003ea981 | 4071 | /* 6150 WiFi/WiMax Series */ |
8b3ee296 WYG |
4072 | {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)}, |
4073 | {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)}, | |
4074 | {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)}, | |
4075 | {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)}, | |
4076 | {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)}, | |
4077 | {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)}, | |
03264339 | 4078 | |
77dcb6a9 | 4079 | /* 1000 Series WiFi */ |
4bd0914f WYG |
4080 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
4081 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
4082 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
4083 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
4084 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
4085 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
4086 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
4087 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
4088 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
4089 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
4090 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
4091 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
1de19ecc | 4092 | |
58a39090 | 4093 | /* 100 Series WiFi */ |
1de19ecc | 4094 | {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)}, |
2a21ff44 | 4095 | {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)}, |
1de19ecc | 4096 | {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)}, |
2a21ff44 | 4097 | {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)}, |
1de19ecc | 4098 | {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)}, |
2a21ff44 | 4099 | {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)}, |
58a39090 WYG |
4100 | |
4101 | /* 130 Series WiFi */ | |
4102 | {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)}, | |
4103 | {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)}, | |
4104 | {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)}, | |
4105 | {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)}, | |
4106 | {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)}, | |
4107 | {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)}, | |
4108 | ||
04b8e751 WYG |
4109 | /* 2x00 Series */ |
4110 | {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)}, | |
4111 | {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)}, | |
4112 | {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)}, | |
4113 | {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)}, | |
4114 | {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)}, | |
4115 | {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)}, | |
4116 | ||
4117 | /* 2x30 Series */ | |
4118 | {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)}, | |
4119 | {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)}, | |
4120 | {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)}, | |
4121 | {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)}, | |
4122 | {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)}, | |
4123 | {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)}, | |
4124 | ||
4125 | /* 6x35 Series */ | |
4126 | {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)}, | |
4127 | {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)}, | |
4128 | {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)}, | |
4129 | {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)}, | |
4130 | {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)}, | |
4131 | {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)}, | |
4132 | {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)}, | |
4133 | {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)}, | |
4134 | {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)}, | |
4135 | ||
b4ed221d WYG |
4136 | /* 105 Series */ |
4137 | {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)}, | |
4138 | {IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)}, | |
4139 | {IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)}, | |
4140 | {IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)}, | |
4141 | {IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)}, | |
4142 | {IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)}, | |
4143 | ||
4144 | /* 135 Series */ | |
4145 | {IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)}, | |
4146 | {IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)}, | |
4147 | {IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)}, | |
4148 | {IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)}, | |
4149 | {IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)}, | |
4150 | {IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)}, | |
04b8e751 | 4151 | |
fed9017e RR |
4152 | {0} |
4153 | }; | |
4154 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
4155 | ||
4156 | static struct pci_driver iwl_driver = { | |
b481de9c | 4157 | .name = DRV_NAME, |
fed9017e | 4158 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
4159 | .probe = iwl_pci_probe, |
4160 | .remove = __devexit_p(iwl_pci_remove), | |
f60dc013 | 4161 | .driver.pm = IWL_PM_OPS, |
b481de9c ZY |
4162 | }; |
4163 | ||
5b9f8cd3 | 4164 | static int __init iwl_init(void) |
b481de9c ZY |
4165 | { |
4166 | ||
4167 | int ret; | |
c96c31e4 JP |
4168 | pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); |
4169 | pr_info(DRV_COPYRIGHT "\n"); | |
897e1cf2 | 4170 | |
e227ceac | 4171 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 4172 | if (ret) { |
c96c31e4 | 4173 | pr_err("Unable to register rate control algorithm: %d\n", ret); |
897e1cf2 RC |
4174 | return ret; |
4175 | } | |
4176 | ||
fed9017e | 4177 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 4178 | if (ret) { |
c96c31e4 | 4179 | pr_err("Unable to initialize PCI module\n"); |
897e1cf2 | 4180 | goto error_register; |
b481de9c | 4181 | } |
b481de9c ZY |
4182 | |
4183 | return ret; | |
897e1cf2 | 4184 | |
897e1cf2 | 4185 | error_register: |
e227ceac | 4186 | iwlagn_rate_control_unregister(); |
897e1cf2 | 4187 | return ret; |
b481de9c ZY |
4188 | } |
4189 | ||
5b9f8cd3 | 4190 | static void __exit iwl_exit(void) |
b481de9c | 4191 | { |
fed9017e | 4192 | pci_unregister_driver(&iwl_driver); |
e227ceac | 4193 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
4194 | } |
4195 | ||
5b9f8cd3 EG |
4196 | module_exit(iwl_exit); |
4197 | module_init(iwl_init); | |
a562a9dd RC |
4198 | |
4199 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 4200 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
4201 | MODULE_PARM_DESC(debug, "debug output mask"); |
4202 | #endif | |
4203 | ||
2b068618 WYG |
4204 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); |
4205 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | |
2b068618 WYG |
4206 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); |
4207 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | |
2b068618 WYG |
4208 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); |
4209 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | |
2b068618 WYG |
4210 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, |
4211 | int, S_IRUGO); | |
4212 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
2b068618 WYG |
4213 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); |
4214 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | |
dd7a2509 JB |
4215 | |
4216 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, | |
4217 | S_IRUGO); | |
4218 | MODULE_PARM_DESC(ucode_alternative, | |
4219 | "specify ucode alternative to use from ucode file"); | |
bee008b7 WYG |
4220 | |
4221 | module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO); | |
4222 | MODULE_PARM_DESC(antenna_coupling, | |
4223 | "specify antenna coupling in dB (defualt: 0 dB)"); | |
f37837c9 | 4224 | |
9f28ebc3 WYG |
4225 | module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO); |
4226 | MODULE_PARM_DESC(bt_ch_inhibition, | |
4227 | "Disable BT channel inhibition (default: enable)"); | |
b7977ffa SG |
4228 | |
4229 | module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO); | |
4230 | MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])"); | |
4231 | ||
4232 | module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO); | |
4233 | MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])"); |