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iwlwifi: Loading correct uCode again when fail to load
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY		 34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY		 38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY		 41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY		 45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY		 48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO		 52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
0de76736 60#include "iwl-agn-calib.h"
a1175124 61#include "iwl-agn.h"
5ed540ae 62#include "iwl-agn-led.h"
b481de9c 63
416e1438 64
b481de9c
ZY		 65/******************************************************************************
66 *
67 * module boiler plate
68 *
69 ******************************************************************************/
70
b481de9c
ZY		 71/*
72 * module name, copyright, version, etc.
b481de9c 73 */
d783b061 74#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 75
0a6857e7 76#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 77#define VD "d"
78#else
79#define VD
80#endif
81
81963d68 82#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 83
b481de9c
ZY		 84
85MODULE_DESCRIPTION(DRV_DESCRIPTION);
86MODULE_VERSION(DRV_VERSION);
a7b75207 87MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 88MODULE_LICENSE("GPL");
4fc22b21 89MODULE_ALIAS("iwl4965");
b481de9c 90
bee008b7 91static int iwlagn_ant_coupling;
f37837c9 92static bool iwlagn_bt_ch_announce = 1;
bee008b7 93
5b9f8cd3 94void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f 95{
246ed355 96 struct iwl_rxon_context *ctx;
5da4b55f 97
246ed355
JB		 98 if (priv->cfg->ops->hcmd->set_rxon_chain) {
99 for_each_context(priv, ctx) {
100 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
6163a373
SZ		 101 if (ctx->active.rx_chain != ctx->staging.rx_chain)
102 iwlcore_commit_rxon(priv, ctx);
246ed355
JB		 103 }
104 }
5da4b55f
MA		 105}
106
fcab423d 107static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 108{
109 struct list_head *element;
110
e1623446 111 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 112 priv->frames_count);
113
114 while (!list_empty(&priv->free_frames)) {
115 element = priv->free_frames.next;
116 list_del(element);
fcab423d 117 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 118 priv->frames_count--;
119 }
120
121 if (priv->frames_count) {
39aadf8c 122 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 123 priv->frames_count);
124 priv->frames_count = 0;
125 }
126}
127
fcab423d 128static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 129{
fcab423d 130 struct iwl_frame *frame;
b481de9c
ZY		 131 struct list_head *element;
132 if (list_empty(&priv->free_frames)) {
133 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
134 if (!frame) {
15b1687c 135 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 136 return NULL;
137 }
138
139 priv->frames_count++;
140 return frame;
141 }
142
143 element = priv->free_frames.next;
144 list_del(element);
fcab423d 145 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 146}
147
fcab423d 148static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 149{
150 memset(frame, 0, sizeof(*frame));
151 list_add(&frame->list, &priv->free_frames);
152}
153
47ff65c4 154static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
77834543
JB		 155 struct ieee80211_hdr *hdr,
156 int left)
b481de9c 157{
77834543
JB		 158 lockdep_assert_held(&priv->mutex);
159
12e934dc 160 if (!priv->beacon_skb)
b481de9c
ZY		 161 return 0;
162
12e934dc 163 if (priv->beacon_skb->len > left)
b481de9c
ZY		 164 return 0;
165
12e934dc 166 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
b481de9c 167
12e934dc 168 return priv->beacon_skb->len;
b481de9c
ZY		 169}
170
47ff65c4
DH		 171/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
172static void iwl_set_beacon_tim(struct iwl_priv *priv,
77834543
JB		 173 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
174 u8 *beacon, u32 frame_size)
47ff65c4
DH		 175{
176 u16 tim_idx;
177 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
178
179 /*
180 * The index is relative to frame start but we start looking at the
181 * variable-length part of the beacon.
182 */
183 tim_idx = mgmt->u.beacon.variable - beacon;
184
185 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
186 while ((tim_idx < (frame_size - 2)) &&
187 (beacon[tim_idx] != WLAN_EID_TIM))
188 tim_idx += beacon[tim_idx+1] + 2;
189
190 /* If TIM field was found, set variables */
191 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
192 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
193 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
194 } else
195 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
196}
197
5b9f8cd3 198static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 199 struct iwl_frame *frame)
4bf64efd
TW		 200{
201 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 202 u32 frame_size;
203 u32 rate_flags;
204 u32 rate;
205 /*
206 * We have to set up the TX command, the TX Beacon command, and the
207 * beacon contents.
208 */
4bf64efd 209
76d04815
JB		 210 lockdep_assert_held(&priv->mutex);
211
212 if (!priv->beacon_ctx) {
213 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
950094cb 214 return 0;
76d04815
JB		 215 }
216
47ff65c4 217 /* Initialize memory */
4bf64efd
TW		 218 tx_beacon_cmd = &frame->u.beacon;
219 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
220
47ff65c4 221 /* Set up TX beacon contents */
4bf64efd 222 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 223 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 224 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
225 return 0;
40bbfd4c
JB		 226 if (!frame_size)
227 return 0;
4bf64efd 228
47ff65c4 229 /* Set up TX command fields */
4bf64efd 230 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
76d04815 231 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
47ff65c4
DH		 232 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
233 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
234 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 235
47ff65c4
DH		 236 /* Set up TX beacon command fields */
237 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
77834543 238 frame_size);
4bf64efd 239
47ff65c4 240 /* Set up packet rate and flags */
76d04815 241 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
0e1654fa
JB		 242 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
243 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 244 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
245 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
246 rate_flags |= RATE_MCS_CCK_MSK;
247 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
248 rate_flags);
4bf64efd
TW		 249
250 return sizeof(*tx_beacon_cmd) + frame_size;
251}
2295c66b
JB		 252
253int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 254{
fcab423d 255 struct iwl_frame *frame;
b481de9c
ZY		 256 unsigned int frame_size;
257 int rc;
b481de9c 258
fcab423d 259 frame = iwl_get_free_frame(priv);
b481de9c 260 if (!frame) {
15b1687c 261 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 262 "command.\n");
263 return -ENOMEM;
264 }
265
47ff65c4
DH		 266 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
267 if (!frame_size) {
268 IWL_ERR(priv, "Error configuring the beacon command\n");
269 iwl_free_frame(priv, frame);
270 return -EINVAL;
271 }
b481de9c 272
857485c0 273 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 274 &frame->u.cmd[0]);
275
fcab423d 276 iwl_free_frame(priv, frame);
b481de9c
ZY		 277
278 return rc;
279}
280
7aaa1d79
SO		 281static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
282{
283 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
284
285 dma_addr_t addr = get_unaligned_le32(&tb->lo);
286 if (sizeof(dma_addr_t) > sizeof(u32))
287 addr |=
288 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
289
290 return addr;
291}
292
293static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
294{
295 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
296
297 return le16_to_cpu(tb->hi_n_len) >> 4;
298}
299
300static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
301 dma_addr_t addr, u16 len)
302{
303 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
304 u16 hi_n_len = len << 4;
305
306 put_unaligned_le32(addr, &tb->lo);
307 if (sizeof(dma_addr_t) > sizeof(u32))
308 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
309
310 tb->hi_n_len = cpu_to_le16(hi_n_len);
311
312 tfd->num_tbs = idx + 1;
313}
314
315static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
316{
317 return tfd->num_tbs & 0x1f;
318}
319
320/**
321 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
322 * @priv - driver private data
323 * @txq - tx queue
324 *
325 * Does NOT advance any TFD circular buffer read/write indexes
326 * Does NOT free the TFD itself (which is within circular buffer)
327 */
328void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
329{
59606ffa 330 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 331 struct iwl_tfd *tfd;
332 struct pci_dev *dev = priv->pci_dev;
333 int index = txq->q.read_ptr;
334 int i;
335 int num_tbs;
336
337 tfd = &tfd_tmp[index];
338
339 /* Sanity check on number of chunks */
340 num_tbs = iwl_tfd_get_num_tbs(tfd);
341
342 if (num_tbs >= IWL_NUM_OF_TBS) {
343 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
344 /* @todo issue fatal error, it is quite serious situation */
345 return;
346 }
347
348 /* Unmap tx_cmd */
349 if (num_tbs)
350 pci_unmap_single(dev,
2e724443
FT		 351 dma_unmap_addr(&txq->meta[index], mapping),
352 dma_unmap_len(&txq->meta[index], len),
96891cee 353 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 354
355 /* Unmap chunks, if any. */
ff0d91c3 356 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 357 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
358 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
359
ff0d91c3
JB		 360 /* free SKB */
361 if (txq->txb) {
362 struct sk_buff *skb;
6f80240e 363
ff0d91c3 364 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 365
ff0d91c3
JB		 366 /* can be called from irqs-disabled context */
367 if (skb) {
368 dev_kfree_skb_any(skb);
369 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 370 }
371 }
372}
373
374int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
375 struct iwl_tx_queue *txq,
376 dma_addr_t addr, u16 len,
377 u8 reset, u8 pad)
378{
379 struct iwl_queue *q;
59606ffa 380 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 381 u32 num_tbs;
382
383 q = &txq->q;
59606ffa
SO		 384 tfd_tmp = (struct iwl_tfd *)txq->tfds;
385 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 386
387 if (reset)
388 memset(tfd, 0, sizeof(*tfd));
389
390 num_tbs = iwl_tfd_get_num_tbs(tfd);
391
392 /* Each TFD can point to a maximum 20 Tx buffers */
393 if (num_tbs >= IWL_NUM_OF_TBS) {
394 IWL_ERR(priv, "Error can not send more than %d chunks\n",
395 IWL_NUM_OF_TBS);
396 return -EINVAL;
397 }
398
399 BUG_ON(addr & ~DMA_BIT_MASK(36));
400 if (unlikely(addr & ~IWL_TX_DMA_MASK))
401 IWL_ERR(priv, "Unaligned address = %llx\n",
402 (unsigned long long)addr);
403
404 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
405
406 return 0;
407}
408
a8e74e27
SO		 409/*
410 * Tell nic where to find circular buffer of Tx Frame Descriptors for
411 * given Tx queue, and enable the DMA channel used for that queue.
412 *
413 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
414 * channels supported in hardware.
415 */
416int iwl_hw_tx_queue_init(struct iwl_priv *priv,
417 struct iwl_tx_queue *txq)
418{
a8e74e27
SO		 419 int txq_id = txq->q.id;
420
a8e74e27
SO		 421 /* Circular buffer (TFD queue in DRAM) physical base address */
422 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
423 txq->q.dma_addr >> 8);
424
a8e74e27
SO		 425 return 0;
426}
427
b481de9c
ZY		 428/******************************************************************************
429 *
430 * Generic RX handler implementations
431 *
432 ******************************************************************************/
885ba202
TW		 433static void iwl_rx_reply_alive(struct iwl_priv *priv,
434 struct iwl_rx_mem_buffer *rxb)
b481de9c 435{
2f301227 436 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 437 struct iwl_alive_resp *palive;
b481de9c
ZY		 438 struct delayed_work *pwork;
439
440 palive = &pkt->u.alive_frame;
441
e1623446 442 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 443 "0x%01X 0x%01X\n",
444 palive->is_valid, palive->ver_type,
445 palive->ver_subtype);
446
447 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 448 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 449 memcpy(&priv->card_alive_init,
450 &pkt->u.alive_frame,
885ba202 451 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 452 pwork = &priv->init_alive_start;
453 } else {
e1623446 454 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 455 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 456 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 457 pwork = &priv->alive_start;
458 }
459
460 /* We delay the ALIVE response by 5ms to
461 * give the HW RF Kill time to activate... */
462 if (palive->is_valid == UCODE_VALID_OK)
463 queue_delayed_work(priv->workqueue, pwork,
464 msecs_to_jiffies(5));
10480b05
WYG		 465 else {
466 IWL_WARN(priv, "%s uCode did not respond OK.\n",
467 (palive->ver_subtype == INITIALIZE_SUBTYPE) ?
468 "init" : "runtime");
46d0637a
WYG		 469 /*
470 * If fail to load init uCode,
471 * let's try to load the init uCode again.
472 * We should not get into this situation, but if it
473 * does happen, we should not move on and loading "runtime"
474 * without proper calibrate the device.
475 */
476 if (palive->ver_subtype == INITIALIZE_SUBTYPE)
477 priv->ucode_type = UCODE_NONE;
10480b05
WYG		 478 queue_work(priv->workqueue, &priv->restart);
479 }
b481de9c
ZY		 480}
481
5b9f8cd3 482static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 483{
c79dd5b5
TW		 484 struct iwl_priv *priv =
485 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 486 struct sk_buff *beacon;
487
76d04815
JB		 488 mutex_lock(&priv->mutex);
489 if (!priv->beacon_ctx) {
490 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
491 goto out;
492 }
b481de9c 493
60744f62
JB		 494 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
495 /*
496 * The ucode will send beacon notifications even in
497 * IBSS mode, but we don't want to process them. But
498 * we need to defer the type check to here due to
499 * requiring locking around the beacon_ctx access.
500 */
501 goto out;
502 }
503
76d04815
JB		 504 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
505 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
b481de9c 506 if (!beacon) {
77834543 507 IWL_ERR(priv, "update beacon failed -- keeping old\n");
76d04815 508 goto out;
b481de9c
ZY		 509 }
510
b481de9c 511 /* new beacon skb is allocated every time; dispose previous.*/
77834543 512 dev_kfree_skb(priv->beacon_skb);
b481de9c 513
12e934dc 514 priv->beacon_skb = beacon;
b481de9c 515
2295c66b 516 iwlagn_send_beacon_cmd(priv);
76d04815
JB		 517 out:
518 mutex_unlock(&priv->mutex);
b481de9c
ZY		 519}
520
fbba9410
WYG		 521static void iwl_bg_bt_runtime_config(struct work_struct *work)
522{
523 struct iwl_priv *priv =
524 container_of(work, struct iwl_priv, bt_runtime_config);
525
526 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
527 return;
528
529 /* dont send host command if rf-kill is on */
530 if (!iwl_is_ready_rf(priv))
531 return;
532 priv->cfg->ops->hcmd->send_bt_config(priv);
533}
534
bee008b7
WYG		 535static void iwl_bg_bt_full_concurrency(struct work_struct *work)
536{
537 struct iwl_priv *priv =
538 container_of(work, struct iwl_priv, bt_full_concurrency);
246ed355 539 struct iwl_rxon_context *ctx;
bee008b7
WYG		 540
541 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
542 return;
543
544 /* dont send host command if rf-kill is on */
545 if (!iwl_is_ready_rf(priv))
546 return;
547
548 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
549 priv->bt_full_concurrent ?
550 "full concurrency" : "3-wire");
551
552 /*
553 * LQ & RXON updated cmds must be sent before BT Config cmd
554 * to avoid 3-wire collisions
555 */
246ed355
JB		 556 mutex_lock(&priv->mutex);
557 for_each_context(priv, ctx) {
558 if (priv->cfg->ops->hcmd->set_rxon_chain)
559 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
560 iwlcore_commit_rxon(priv, ctx);
561 }
562 mutex_unlock(&priv->mutex);
bee008b7
WYG		 563
564 priv->cfg->ops->hcmd->send_bt_config(priv);
565}
566
4e39317d 567/**
5b9f8cd3 568 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 569 *
570 * This callback is provided in order to send a statistics request.
571 *
572 * This timer function is continually reset to execute within
573 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
574 * was received. We need to ensure we receive the statistics in order
575 * to update the temperature used for calibrating the TXPOWER.
576 */
5b9f8cd3 577static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 578{
579 struct iwl_priv *priv = (struct iwl_priv *)data;
580
581 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
582 return;
583
61780ee3
MA		 584 /* dont send host command if rf-kill is on */
585 if (!iwl_is_ready_rf(priv))
586 return;
587
ef8d5529 588 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 589}
590
a9e1cb6a
WYG		 591
592static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
593 u32 start_idx, u32 num_events,
594 u32 mode)
595{
596 u32 i;
597 u32 ptr; /* SRAM byte address of log data */
598 u32 ev, time, data; /* event log data */
599 unsigned long reg_flags;
600
601 if (mode == 0)
602 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
603 else
604 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
605
606 /* Make sure device is powered up for SRAM reads */
607 spin_lock_irqsave(&priv->reg_lock, reg_flags);
608 if (iwl_grab_nic_access(priv)) {
609 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
610 return;
611 }
612
613 /* Set starting address; reads will auto-increment */
614 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
615 rmb();
616
617 /*
618 * "time" is actually "data" for mode 0 (no timestamp).
619 * place event id # at far right for easier visual parsing.
620 */
621 for (i = 0; i < num_events; i++) {
622 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
623 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
624 if (mode == 0) {
625 trace_iwlwifi_dev_ucode_cont_event(priv,
626 0, time, ev);
627 } else {
628 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
629 trace_iwlwifi_dev_ucode_cont_event(priv,
630 time, data, ev);
631 }
632 }
633 /* Allow device to power down */
634 iwl_release_nic_access(priv);
635 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
636}
637
875295f1 638static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 639{
640 u32 capacity; /* event log capacity in # entries */
641 u32 base; /* SRAM byte address of event log header */
642 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
643 u32 num_wraps; /* # times uCode wrapped to top of log */
644 u32 next_entry; /* index of next entry to be written by uCode */
645
646 if (priv->ucode_type == UCODE_INIT)
647 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
648 else
649 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
650 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
651 capacity = iwl_read_targ_mem(priv, base);
652 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
653 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
654 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
655 } else
656 return;
657
658 if (num_wraps == priv->event_log.num_wraps) {
659 iwl_print_cont_event_trace(priv,
660 base, priv->event_log.next_entry,
661 next_entry - priv->event_log.next_entry,
662 mode);
663 priv->event_log.non_wraps_count++;
664 } else {
665 if ((num_wraps - priv->event_log.num_wraps) > 1)
666 priv->event_log.wraps_more_count++;
667 else
668 priv->event_log.wraps_once_count++;
669 trace_iwlwifi_dev_ucode_wrap_event(priv,
670 num_wraps - priv->event_log.num_wraps,
671 next_entry, priv->event_log.next_entry);
672 if (next_entry < priv->event_log.next_entry) {
673 iwl_print_cont_event_trace(priv, base,
674 priv->event_log.next_entry,
675 capacity - priv->event_log.next_entry,
676 mode);
677
678 iwl_print_cont_event_trace(priv, base, 0,
679 next_entry, mode);
680 } else {
681 iwl_print_cont_event_trace(priv, base,
682 next_entry, capacity - next_entry,
683 mode);
684
685 iwl_print_cont_event_trace(priv, base, 0,
686 next_entry, mode);
687 }
688 }
689 priv->event_log.num_wraps = num_wraps;
690 priv->event_log.next_entry = next_entry;
691}
692
693/**
694 * iwl_bg_ucode_trace - Timer callback to log ucode event
695 *
696 * The timer is continually set to execute every
697 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
698 * this function is to perform continuous uCode event logging operation
699 * if enabled
700 */
701static void iwl_bg_ucode_trace(unsigned long data)
702{
703 struct iwl_priv *priv = (struct iwl_priv *)data;
704
705 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
706 return;
707
708 if (priv->event_log.ucode_trace) {
709 iwl_continuous_event_trace(priv);
710 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
711 mod_timer(&priv->ucode_trace,
712 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
713 }
714}
715
241887a2
JB		 716static void iwlagn_rx_beacon_notif(struct iwl_priv *priv,
717 struct iwl_rx_mem_buffer *rxb)
b481de9c 718{
2f301227 719 struct iwl_rx_packet *pkt = rxb_addr(rxb);
241887a2 720 struct iwlagn_beacon_notif *beacon = (void *)pkt->u.raw;
a85d7cca 721#ifdef CONFIG_IWLWIFI_DEBUG
241887a2 722 u16 status = le16_to_cpu(beacon->beacon_notify_hdr.status.status);
e7d326ac 723 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 724
241887a2
JB		 725 IWL_DEBUG_RX(priv, "beacon status %#x, retries:%d ibssmgr:%d "
726 "tsf:0x%.8x%.8x rate:%d\n",
727 status & TX_STATUS_MSK,
b481de9c
ZY		 728 beacon->beacon_notify_hdr.failure_frame,
729 le32_to_cpu(beacon->ibss_mgr_status),
730 le32_to_cpu(beacon->high_tsf),
731 le32_to_cpu(beacon->low_tsf), rate);
732#endif
733
a85d7cca
JB		 734 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
735
60744f62 736 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 737 queue_work(priv->workqueue, &priv->beacon_update);
738}
739
b481de9c
ZY		 740/* Handle notification from uCode that card's power state is changing
741 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 742static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 743 struct iwl_rx_mem_buffer *rxb)
b481de9c 744{
2f301227 745 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 746 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
747 unsigned long status = priv->status;
748
3a41bbd5 749 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 750 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 751 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
752 (flags & CT_CARD_DISABLED) ?
753 "Reached" : "Not reached");
b481de9c
ZY		 754
755 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 756 CT_CARD_DISABLED)) {
b481de9c 757
3395f6e9 758 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 759 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
760
a8b50a0a
MA		 761 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
762 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 763
764 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 765 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 766 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 767 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 768 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 769 }
3a41bbd5 770 if (flags & CT_CARD_DISABLED)
39b73fb1 771 iwl_tt_enter_ct_kill(priv);
b481de9c 772 }
3a41bbd5 773 if (!(flags & CT_CARD_DISABLED))
39b73fb1 774 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 775
776 if (flags & HW_CARD_DISABLED)
777 set_bit(STATUS_RF_KILL_HW, &priv->status);
778 else
779 clear_bit(STATUS_RF_KILL_HW, &priv->status);
780
781
b481de9c 782 if (!(flags & RXON_CARD_DISABLED))
2a421b91 783 iwl_scan_cancel(priv);
b481de9c
ZY		 784
785 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 786 test_bit(STATUS_RF_KILL_HW, &priv->status)))
787 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
788 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 789 else
790 wake_up_interruptible(&priv->wait_command_queue);
791}
792
65550636
WYG		 793static void iwl_bg_tx_flush(struct work_struct *work)
794{
795 struct iwl_priv *priv =
796 container_of(work, struct iwl_priv, tx_flush);
797
798 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
799 return;
800
801 /* do nothing if rf-kill is on */
802 if (!iwl_is_ready_rf(priv))
803 return;
804
805 if (priv->cfg->ops->lib->txfifo_flush) {
806 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
807 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
808 }
809}
810
b481de9c 811/**
5b9f8cd3 812 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 813 *
814 * Setup the RX handlers for each of the reply types sent from the uCode
815 * to the host.
816 *
817 * This function chains into the hardware specific files for them to setup
818 * any hardware specific handlers as well.
819 */
653fa4a0 820static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 821{
885ba202 822 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 823 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
824 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 825 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
826 iwl_rx_spectrum_measure_notif;
5b9f8cd3 827 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 828 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3 829 iwl_rx_pm_debug_statistics_notif;
241887a2 830 priv->rx_handlers[BEACON_NOTIFICATION] = iwlagn_rx_beacon_notif;
b481de9c 831
9fbab516
BC		 832 /*
833 * The same handler is used for both the REPLY to a discrete
834 * statistics request from the host as well as for the periodic
835 * statistics notifications (after received beacons) from the uCode.
b481de9c 836 */
ef8d5529 837 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 838 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 839
840 iwl_setup_rx_scan_handlers(priv);
841
37a44211 842 /* status change handler */
5b9f8cd3 843 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 844
c1354754
TW		 845 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
846 iwl_rx_missed_beacon_notif;
37a44211 847 /* Rx handlers */
8d801080
WYG		 848 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
849 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 850 /* block ack */
74bcdb33 851 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 852 /* Set up hardware specific Rx handlers */
d4789efe 853 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 854}
855
b481de9c 856/**
a55360e4 857 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 858 *
859 * Uses the priv->rx_handlers callback function array to invoke
860 * the appropriate handlers, including command responses,
861 * frame-received notifications, and other notifications.
862 */
f945f108 863static void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 864{
a55360e4 865 struct iwl_rx_mem_buffer *rxb;
db11d634 866 struct iwl_rx_packet *pkt;
a55360e4 867 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 868 u32 r, i;
869 int reclaim;
870 unsigned long flags;
5c0eef96 871 u8 fill_rx = 0;
d68ab680 872 u32 count = 8;
4752c93c 873 int total_empty;
b481de9c 874
6440adb5
CB		 875 /* uCode's read index (stored in shared DRAM) indicates the last Rx
876 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 877 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 878 i = rxq->read;
879
880 /* Rx interrupt, but nothing sent from uCode */
881 if (i == r)
e1623446 882 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 883
4752c93c 884 /* calculate total frames need to be restock after handling RX */
7300515d 885 total_empty = r - rxq->write_actual;
4752c93c
MA		 886 if (total_empty < 0)
887 total_empty += RX_QUEUE_SIZE;
888
889 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 890 fill_rx = 1;
891
b481de9c 892 while (i != r) {
f4989d9b
JB		 893 int len;
894
b481de9c
ZY		 895 rxb = rxq->queue[i];
896
9fbab516 897 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 898 * then a bug has been introduced in the queue refilling
899 * routines -- catch it here */
900 BUG_ON(rxb == NULL);
901
902 rxq->queue[i] = NULL;
903
2f301227
ZY		 904 pci_unmap_page(priv->pci_dev, rxb->page_dma,
905 PAGE_SIZE << priv->hw_params.rx_page_order,
906 PCI_DMA_FROMDEVICE);
907 pkt = rxb_addr(rxb);
b481de9c 908
f4989d9b
JB		 909 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
910 len += sizeof(u32); /* account for status word */
911 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 912
b481de9c
ZY		 913 /* Reclaim a command buffer only if this packet is a response
914 * to a (driver-originated) command.
915 * If the packet (e.g. Rx frame) originated from uCode,
916 * there is no command buffer to reclaim.
917 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
918 * but apparently a few don't get set; catch them here. */
919 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
920 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 921 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 922 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 923 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 924 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
925 (pkt->hdr.cmd != REPLY_TX);
926
7194207c
JB		 927 /*
928 * Do the notification wait before RX handlers so
929 * even if the RX handler consumes the RXB we have
930 * access to it in the notification wait entry.
931 */
932 if (!list_empty(&priv->_agn.notif_waits)) {
933 struct iwl_notification_wait *w;
934
935 spin_lock(&priv->_agn.notif_wait_lock);
936 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
937 if (w->cmd == pkt->hdr.cmd) {
938 w->triggered = true;
939 if (w->fn)
940 w->fn(priv, pkt);
941 }
942 }
943 spin_unlock(&priv->_agn.notif_wait_lock);
944
945 wake_up_all(&priv->_agn.notif_waitq);
946 }
947
b481de9c
ZY		 948 /* Based on type of command response or notification,
949 * handle those that need handling via function in
5b9f8cd3 950 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 951 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 952 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 953 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 954 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 955 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 956 } else {
957 /* No handling needed */
e1623446 958 IWL_DEBUG_RX(priv,
b481de9c
ZY		 959 "r %d i %d No handler needed for %s, 0x%02x\n",
960 r, i, get_cmd_string(pkt->hdr.cmd),
961 pkt->hdr.cmd);
962 }
963
29b1b268
ZY		 964 /*
965 * XXX: After here, we should always check rxb->page
966 * against NULL before touching it or its virtual
967 * memory (pkt). Because some rx_handler might have
968 * already taken or freed the pages.
969 */
970
b481de9c 971 if (reclaim) {
2f301227
ZY		 972 /* Invoke any callbacks, transfer the buffer to caller,
973 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 974 * as we reclaim the driver command queue */
29b1b268 975 if (rxb->page)
17b88929 976 iwl_tx_cmd_complete(priv, rxb);
b481de9c 977 else
39aadf8c 978 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 979 }
980
7300515d
ZY		 981 /* Reuse the page if possible. For notification packets and
982 * SKBs that fail to Rx correctly, add them back into the
983 * rx_free list for reuse later. */
984 spin_lock_irqsave(&rxq->lock, flags);
2f301227 985 if (rxb->page != NULL) {
7300515d
ZY		 986 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
987 0, PAGE_SIZE << priv->hw_params.rx_page_order,
988 PCI_DMA_FROMDEVICE);
989 list_add_tail(&rxb->list, &rxq->rx_free);
990 rxq->free_count++;
991 } else
992 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 993
b481de9c 994 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 995
b481de9c 996 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 997 /* If there are a lot of unused frames,
998 * restock the Rx queue so ucode wont assert. */
999 if (fill_rx) {
1000 count++;
1001 if (count >= 8) {
7300515d 1002 rxq->read = i;
54b81550 1003 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1004 count = 0;
1005 }
1006 }
b481de9c
ZY		 1007 }
1008
1009 /* Backtrack one entry */
7300515d 1010 rxq->read = i;
4752c93c 1011 if (fill_rx)
54b81550 1012 iwlagn_rx_replenish_now(priv);
4752c93c 1013 else
54b81550 1014 iwlagn_rx_queue_restock(priv);
a55360e4 1015}
a55360e4 1016
0359facc
MA		 1017/* call this function to flush any scheduled tasklet */
1018static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1019{
a96a27f9 1020 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1021 synchronize_irq(priv->pci_dev->irq);
1022 tasklet_kill(&priv->irq_tasklet);
1023}
1024
ef850d7c 1025static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1026{
1027 u32 inta, handled = 0;
1028 u32 inta_fh;
1029 unsigned long flags;
c2e61da2 1030 u32 i;
0a6857e7 1031#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1032 u32 inta_mask;
1033#endif
1034
1035 spin_lock_irqsave(&priv->lock, flags);
1036
1037 /* Ack/clear/reset pending uCode interrupts.
1038 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1039 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1040 inta = iwl_read32(priv, CSR_INT);
1041 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1042
1043 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1044 * Any new interrupts that happen after this, either while we're
1045 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1046 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1047 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1048
0a6857e7 1049#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1050 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1051 /* just for debug */
3395f6e9 1052 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1053 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1054 inta, inta_mask, inta_fh);
1055 }
1056#endif
1057
2f301227
ZY		 1058 spin_unlock_irqrestore(&priv->lock, flags);
1059
b481de9c
ZY		 1060 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1061 * atomic, make sure that inta covers all the interrupts that
1062 * we've discovered, even if FH interrupt came in just after
1063 * reading CSR_INT. */
6f83eaa1 1064 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1065 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1066 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1067 inta |= CSR_INT_BIT_FH_TX;
1068
1069 /* Now service all interrupt bits discovered above. */
1070 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1071 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1072
1073 /* Tell the device to stop sending interrupts */
5b9f8cd3 1074 iwl_disable_interrupts(priv);
b481de9c 1075
a83b9141 1076 priv->isr_stats.hw++;
5b9f8cd3 1077 iwl_irq_handle_error(priv);
b481de9c
ZY		 1078
1079 handled |= CSR_INT_BIT_HW_ERR;
1080
b481de9c
ZY		 1081 return;
1082 }
1083
0a6857e7 1084#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1085 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1086 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1087 if (inta & CSR_INT_BIT_SCD) {
e1623446 1088 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1089 "the frame/frames.\n");
a83b9141
WYG		 1090 priv->isr_stats.sch++;
1091 }
b481de9c
ZY		 1092
1093 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1094 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1095 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1096 priv->isr_stats.alive++;
1097 }
b481de9c
ZY		 1098 }
1099#endif
1100 /* Safely ignore these bits for debug checks below */
25c03d8e 1101 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1102
9fbab516 1103 /* HW RF KILL switch toggled */
b481de9c
ZY		 1104 if (inta & CSR_INT_BIT_RF_KILL) {
1105 int hw_rf_kill = 0;
3395f6e9 1106 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1107 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1108 hw_rf_kill = 1;
1109
4c423a2b 1110 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1111 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1112
a83b9141
WYG		 1113 priv->isr_stats.rfkill++;
1114
a9efa652 1115 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1116 * the driver allows loading the ucode even if the radio
1117 * is killed. Hence update the killswitch state here. The
1118 * rfkill handler will care about restarting if needed.
a9efa652 1119 */
6cd0b1cb
HS		 1120 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1121 if (hw_rf_kill)
1122 set_bit(STATUS_RF_KILL_HW, &priv->status);
1123 else
1124 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1125 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1126 }
b481de9c
ZY		 1127
1128 handled |= CSR_INT_BIT_RF_KILL;
1129 }
1130
9fbab516 1131 /* Chip got too hot and stopped itself */
b481de9c 1132 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1133 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1134 priv->isr_stats.ctkill++;
b481de9c
ZY		 1135 handled |= CSR_INT_BIT_CT_KILL;
1136 }
1137
1138 /* Error detected by uCode */
1139 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1140 IWL_ERR(priv, "Microcode SW error detected. "
1141 " Restarting 0x%X.\n", inta);
a83b9141 1142 priv->isr_stats.sw++;
5b9f8cd3 1143 iwl_irq_handle_error(priv);
b481de9c
ZY		 1144 handled |= CSR_INT_BIT_SW_ERR;
1145 }
1146
c2e61da2
BC		 1147 /*
1148 * uCode wakes up after power-down sleep.
1149 * Tell device about any new tx or host commands enqueued,
1150 * and about any Rx buffers made available while asleep.
1151 */
b481de9c 1152 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1153 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1154 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1155 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1156 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1157 priv->isr_stats.wakeup++;
b481de9c
ZY		 1158 handled |= CSR_INT_BIT_WAKEUP;
1159 }
1160
1161 /* All uCode command responses, including Tx command responses,
1162 * Rx "responses" (frame-received notification), and other
1163 * notifications from uCode come through here*/
1164 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1165 iwl_rx_handle(priv);
a83b9141 1166 priv->isr_stats.rx++;
b481de9c
ZY		 1167 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1168 }
1169
c72cd19f 1170 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1171 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1172 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1173 priv->isr_stats.tx++;
b481de9c 1174 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1175 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1176 priv->ucode_write_complete = 1;
1177 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1178 }
1179
a83b9141 1180 if (inta & ~handled) {
15b1687c 1181 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1182 priv->isr_stats.unhandled++;
1183 }
b481de9c 1184
40cefda9 1185 if (inta & ~(priv->inta_mask)) {
39aadf8c 1186 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1187 inta & ~priv->inta_mask);
39aadf8c 1188 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1189 }
1190
1191 /* Re-enable all interrupts */
62e45c14 1192 /* only Re-enable if disabled by irq */
0359facc 1193 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1194 iwl_enable_interrupts(priv);
3dd823e6
DF		 1195 /* Re-enable RF_KILL if it occurred */
1196 else if (handled & CSR_INT_BIT_RF_KILL)
1197 iwl_enable_rfkill_int(priv);
b481de9c 1198
0a6857e7 1199#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1200 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1201 inta = iwl_read32(priv, CSR_INT);
1202 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1203 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1204 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1205 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1206 }
1207#endif
b481de9c
ZY		 1208}
1209
ef850d7c
MA		 1210/* tasklet for iwlagn interrupt */
1211static void iwl_irq_tasklet(struct iwl_priv *priv)
1212{
1213 u32 inta = 0;
1214 u32 handled = 0;
1215 unsigned long flags;
8756990f 1216 u32 i;
ef850d7c
MA		 1217#ifdef CONFIG_IWLWIFI_DEBUG
1218 u32 inta_mask;
1219#endif
1220
1221 spin_lock_irqsave(&priv->lock, flags);
1222
1223 /* Ack/clear/reset pending uCode interrupts.
1224 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1225 */
48a6be6a
SZ		 1226 /* There is a hardware bug in the interrupt mask function that some
1227 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1228 * they are disabled in the CSR_INT_MASK register. Furthermore the
1229 * ICT interrupt handling mechanism has another bug that might cause
1230 * these unmasked interrupts fail to be detected. We workaround the
1231 * hardware bugs here by ACKing all the possible interrupts so that
1232 * interrupt coalescing can still be achieved.
1233 */
4a35ecf8 1234 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1235
a4c8b2a6 1236 inta = priv->_agn.inta;
ef850d7c
MA		 1237
1238#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1239 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1240 /* just for debug */
1241 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1242 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1243 inta, inta_mask);
1244 }
1245#endif
2f301227
ZY		 1246
1247 spin_unlock_irqrestore(&priv->lock, flags);
1248
a4c8b2a6
JB		 1249 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1250 priv->_agn.inta = 0;
ef850d7c
MA		 1251
1252 /* Now service all interrupt bits discovered above. */
1253 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1254 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1255
1256 /* Tell the device to stop sending interrupts */
1257 iwl_disable_interrupts(priv);
1258
1259 priv->isr_stats.hw++;
1260 iwl_irq_handle_error(priv);
1261
1262 handled |= CSR_INT_BIT_HW_ERR;
1263
ef850d7c
MA		 1264 return;
1265 }
1266
1267#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1268 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1269 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1270 if (inta & CSR_INT_BIT_SCD) {
1271 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1272 "the frame/frames.\n");
1273 priv->isr_stats.sch++;
1274 }
1275
1276 /* Alive notification via Rx interrupt will do the real work */
1277 if (inta & CSR_INT_BIT_ALIVE) {
1278 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1279 priv->isr_stats.alive++;
1280 }
1281 }
1282#endif
1283 /* Safely ignore these bits for debug checks below */
1284 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1285
1286 /* HW RF KILL switch toggled */
1287 if (inta & CSR_INT_BIT_RF_KILL) {
1288 int hw_rf_kill = 0;
1289 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1290 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1291 hw_rf_kill = 1;
1292
4c423a2b 1293 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1294 hw_rf_kill ? "disable radio" : "enable radio");
1295
1296 priv->isr_stats.rfkill++;
1297
1298 /* driver only loads ucode once setting the interface up.
1299 * the driver allows loading the ucode even if the radio
1300 * is killed. Hence update the killswitch state here. The
1301 * rfkill handler will care about restarting if needed.
1302 */
1303 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1304 if (hw_rf_kill)
1305 set_bit(STATUS_RF_KILL_HW, &priv->status);
1306 else
1307 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1308 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1309 }
1310
1311 handled |= CSR_INT_BIT_RF_KILL;
1312 }
1313
1314 /* Chip got too hot and stopped itself */
1315 if (inta & CSR_INT_BIT_CT_KILL) {
1316 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1317 priv->isr_stats.ctkill++;
1318 handled |= CSR_INT_BIT_CT_KILL;
1319 }
1320
1321 /* Error detected by uCode */
1322 if (inta & CSR_INT_BIT_SW_ERR) {
1323 IWL_ERR(priv, "Microcode SW error detected. "
1324 " Restarting 0x%X.\n", inta);
1325 priv->isr_stats.sw++;
ef850d7c
MA		 1326 iwl_irq_handle_error(priv);
1327 handled |= CSR_INT_BIT_SW_ERR;
1328 }
1329
1330 /* uCode wakes up after power-down sleep */
1331 if (inta & CSR_INT_BIT_WAKEUP) {
1332 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1333 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1334 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1335 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1336
1337 priv->isr_stats.wakeup++;
1338
1339 handled |= CSR_INT_BIT_WAKEUP;
1340 }
1341
1342 /* All uCode command responses, including Tx command responses,
1343 * Rx "responses" (frame-received notification), and other
1344 * notifications from uCode come through here*/
40cefda9
MA		 1345 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1346 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1347 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1348 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1349 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1350 iwl_write32(priv, CSR_FH_INT_STATUS,
1351 CSR49_FH_INT_RX_MASK);
1352 }
1353 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1354 handled |= CSR_INT_BIT_RX_PERIODIC;
1355 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1356 }
1357 /* Sending RX interrupt require many steps to be done in the
1358 * the device:
1359 * 1- write interrupt to current index in ICT table.
1360 * 2- dma RX frame.
1361 * 3- update RX shared data to indicate last write index.
1362 * 4- send interrupt.
1363 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1364 * but the shared data changes does not reflect this;
1365 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1366 */
74ba67ed
BC		 1367
1368 /* Disable periodic interrupt; we use it as just a one-shot. */
1369 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1370 CSR_INT_PERIODIC_DIS);
ef850d7c 1371 iwl_rx_handle(priv);
74ba67ed
BC		 1372
1373 /*
1374 * Enable periodic interrupt in 8 msec only if we received
1375 * real RX interrupt (instead of just periodic int), to catch
1376 * any dangling Rx interrupt. If it was just the periodic
1377 * interrupt, there was no dangling Rx activity, and no need
1378 * to extend the periodic interrupt; one-shot is enough.
1379 */
40cefda9 1380 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1381 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1382 CSR_INT_PERIODIC_ENA);
1383
ef850d7c 1384 priv->isr_stats.rx++;
ef850d7c
MA		 1385 }
1386
c72cd19f 1387 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1388 if (inta & CSR_INT_BIT_FH_TX) {
1389 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1390 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1391 priv->isr_stats.tx++;
1392 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1393 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1394 priv->ucode_write_complete = 1;
1395 wake_up_interruptible(&priv->wait_command_queue);
1396 }
1397
1398 if (inta & ~handled) {
1399 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1400 priv->isr_stats.unhandled++;
1401 }
1402
40cefda9 1403 if (inta & ~(priv->inta_mask)) {
ef850d7c 1404 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1405 inta & ~priv->inta_mask);
ef850d7c
MA		 1406 }
1407
ef850d7c 1408 /* Re-enable all interrupts */
62e45c14 1409 /* only Re-enable if disabled by irq */
ef850d7c
MA		 1410 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1411 iwl_enable_interrupts(priv);
3dd823e6
DF		 1412 /* Re-enable RF_KILL if it occurred */
1413 else if (handled & CSR_INT_BIT_RF_KILL)
1414 iwl_enable_rfkill_int(priv);
ef850d7c
MA		 1415}
1416
872c8ddc
WYG		 1417/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1418#define ACK_CNT_RATIO (50)
1419#define BA_TIMEOUT_CNT (5)
1420#define BA_TIMEOUT_MAX (16)
1421
1422/**
1423 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1424 *
f266526d 1425 * When the ACK count ratio is low and aggregated BA timeout retries exceeding
872c8ddc
WYG		 1426 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1427 * operation state.
1428 */
f266526d 1429bool iwl_good_ack_health(struct iwl_priv *priv, struct iwl_rx_packet *pkt)
872c8ddc 1430{
f266526d
SG		 1431 int actual_delta, expected_delta, ba_timeout_delta;
1432 struct statistics_tx *cur, *old;
1433
1434 if (priv->_agn.agg_tids_count)
1435 return true;
1436
67acad5f
SG		 1437 if (iwl_bt_statistics(priv)) {
1438 cur = &pkt->u.stats_bt.tx;
1439 old = &priv->_agn.statistics_bt.tx;
1440 } else {
1441 cur = &pkt->u.stats.tx;
1442 old = &priv->_agn.statistics.tx;
1443 }
f266526d
SG		 1444
1445 actual_delta = le32_to_cpu(cur->actual_ack_cnt) -
1446 le32_to_cpu(old->actual_ack_cnt);
1447 expected_delta = le32_to_cpu(cur->expected_ack_cnt) -
1448 le32_to_cpu(old->expected_ack_cnt);
1449
1450 /* Values should not be negative, but we do not trust the firmware */
1451 if (actual_delta <= 0 || expected_delta <= 0)
1452 return true;
1453
1454 ba_timeout_delta = le32_to_cpu(cur->agg.ba_timeout) -
1455 le32_to_cpu(old->agg.ba_timeout);
1456
1457 if ((actual_delta * 100 / expected_delta) < ACK_CNT_RATIO &&
1458 ba_timeout_delta > BA_TIMEOUT_CNT) {
1459 IWL_DEBUG_RADIO(priv, "deltas: actual %d expected %d ba_timeout %d\n",
1460 actual_delta, expected_delta, ba_timeout_delta);
872c8ddc 1461
d73e4923
JB		 1462#ifdef CONFIG_IWLWIFI_DEBUGFS
1463 /*
1464 * This is ifdef'ed on DEBUGFS because otherwise the
1465 * statistics aren't available. If DEBUGFS is set but
1466 * DEBUG is not, these will just compile out.
1467 */
f266526d 1468 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta %d\n",
f3aebeee 1469 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc 1470 IWL_DEBUG_RADIO(priv,
f266526d
SG		 1471 "ack_or_ba_timeout_collision delta %d\n",
1472 priv->_agn.delta_statistics.tx.ack_or_ba_timeout_collision);
872c8ddc 1473#endif
f266526d
SG		 1474
1475 if (ba_timeout_delta >= BA_TIMEOUT_MAX)
1476 return false;
872c8ddc 1477 }
f266526d
SG		 1478
1479 return true;
872c8ddc
WYG		 1480}
1481
a83b9141 1482
7d47618a
EG		 1483/*****************************************************************************
1484 *
1485 * sysfs attributes
1486 *
1487 *****************************************************************************/
1488
1489#ifdef CONFIG_IWLWIFI_DEBUG
1490
1491/*
1492 * The following adds a new attribute to the sysfs representation
1493 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1494 * used for controlling the debug level.
1495 *
1496 * See the level definitions in iwl for details.
1497 *
1498 * The debug_level being managed using sysfs below is a per device debug
1499 * level that is used instead of the global debug level if it (the per
1500 * device debug level) is set.
1501 */
1502static ssize_t show_debug_level(struct device *d,
1503 struct device_attribute *attr, char *buf)
1504{
1505 struct iwl_priv *priv = dev_get_drvdata(d);
1506 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1507}
1508static ssize_t store_debug_level(struct device *d,
1509 struct device_attribute *attr,
1510 const char *buf, size_t count)
1511{
1512 struct iwl_priv *priv = dev_get_drvdata(d);
1513 unsigned long val;
1514 int ret;
1515
1516 ret = strict_strtoul(buf, 0, &val);
1517 if (ret)
1518 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1519 else {
1520 priv->debug_level = val;
1521 if (iwl_alloc_traffic_mem(priv))
1522 IWL_ERR(priv,
1523 "Not enough memory to generate traffic log\n");
1524 }
1525 return strnlen(buf, count);
1526}
1527
1528static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1529 show_debug_level, store_debug_level);
1530
1531
1532#endif /* CONFIG_IWLWIFI_DEBUG */
1533
1534
1535static ssize_t show_temperature(struct device *d,
1536 struct device_attribute *attr, char *buf)
1537{
1538 struct iwl_priv *priv = dev_get_drvdata(d);
1539
1540 if (!iwl_is_alive(priv))
1541 return -EAGAIN;
1542
1543 return sprintf(buf, "%d\n", priv->temperature);
1544}
1545
1546static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1547
1548static ssize_t show_tx_power(struct device *d,
1549 struct device_attribute *attr, char *buf)
1550{
1551 struct iwl_priv *priv = dev_get_drvdata(d);
1552
1553 if (!iwl_is_ready_rf(priv))
1554 return sprintf(buf, "off\n");
1555 else
1556 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1557}
1558
1559static ssize_t store_tx_power(struct device *d,
1560 struct device_attribute *attr,
1561 const char *buf, size_t count)
1562{
1563 struct iwl_priv *priv = dev_get_drvdata(d);
1564 unsigned long val;
1565 int ret;
1566
1567 ret = strict_strtoul(buf, 10, &val);
1568 if (ret)
1569 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1570 else {
1571 ret = iwl_set_tx_power(priv, val, false);
1572 if (ret)
1573 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1574 ret);
1575 else
1576 ret = count;
1577 }
1578 return ret;
1579}
1580
1581static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1582
7d47618a
EG		 1583static struct attribute *iwl_sysfs_entries[] = {
1584 &dev_attr_temperature.attr,
1585 &dev_attr_tx_power.attr,
7d47618a
EG		 1586#ifdef CONFIG_IWLWIFI_DEBUG
1587 &dev_attr_debug_level.attr,
1588#endif
1589 NULL
1590};
1591
1592static struct attribute_group iwl_attribute_group = {
1593 .name = NULL, /* put in device directory */
1594 .attrs = iwl_sysfs_entries,
1595};
1596
b481de9c
ZY		 1597/******************************************************************************
1598 *
1599 * uCode download functions
1600 *
1601 ******************************************************************************/
1602
5b9f8cd3 1603static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1604{
98c92211
TW		 1605 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1606 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1607 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1608 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1609 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1610 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1611}
1612
5b9f8cd3 1613static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1614{
1615 /* Remove all resets to allow NIC to operate */
1616 iwl_write32(priv, CSR_RESET, 0);
1617}
1618
dd7a2509
JB		 1619struct iwlagn_ucode_capabilities {
1620 u32 max_probe_length;
6a822d06 1621 u32 standard_phy_calibration_size;
ece9c4ee 1622 bool pan;
dd7a2509 1623};
edcdf8b2 1624
b08dfd04 1625static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1626static int iwl_mac_setup_register(struct iwl_priv *priv,
1627 struct iwlagn_ucode_capabilities *capa);
b08dfd04 1628
39396085
JS		 1629#define UCODE_EXPERIMENTAL_INDEX 100
1630#define UCODE_EXPERIMENTAL_TAG "exp"
1631
b08dfd04
JB		 1632static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1633{
1634 const char *name_pre = priv->cfg->fw_name_pre;
39396085 1635 char tag[8];
b08dfd04 1636
39396085
JS		 1637 if (first) {
1638#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1639 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1640 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1641 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1642#endif
b08dfd04 1643 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS		 1644 sprintf(tag, "%d", priv->fw_index);
1645 } else {
b08dfd04 1646 priv->fw_index--;
39396085
JS		 1647 sprintf(tag, "%d", priv->fw_index);
1648 }
b08dfd04
JB		 1649
1650 if (priv->fw_index < priv->cfg->ucode_api_min) {
1651 IWL_ERR(priv, "no suitable firmware found!\n");
1652 return -ENOENT;
1653 }
1654
39396085 1655 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1656
39396085
JS		 1657 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1658 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1659 ? "EXPERIMENTAL " : "",
b08dfd04
JB		 1660 priv->firmware_name);
1661
1662 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1663 &priv->pci_dev->dev, GFP_KERNEL, priv,
1664 iwl_ucode_callback);
1665}
1666
0e9a44dc
JB		 1667struct iwlagn_firmware_pieces {
1668 const void *inst, *data, *init, *init_data, *boot;
1669 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1670
1671 u32 build;
b2e640d4
JB		 1672
1673 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1674 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1675};
1676
1677static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1678 const struct firmware *ucode_raw,
1679 struct iwlagn_firmware_pieces *pieces)
1680{
1681 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1682 u32 api_ver, hdr_size;
1683 const u8 *src;
1684
1685 priv->ucode_ver = le32_to_cpu(ucode->ver);
1686 api_ver = IWL_UCODE_API(priv->ucode_ver);
1687
1688 switch (api_ver) {
1689 default:
1690 /*
1691 * 4965 doesn't revision the firmware file format
1692 * along with the API version, it always uses v1
1693 * file format.
1694 */
1695 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1696 CSR_HW_REV_TYPE_4965) {
1697 hdr_size = 28;
1698 if (ucode_raw->size < hdr_size) {
1699 IWL_ERR(priv, "File size too small!\n");
1700 return -EINVAL;
1701 }
1702 pieces->build = le32_to_cpu(ucode->u.v2.build);
1703 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1704 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1705 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1706 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1707 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1708 src = ucode->u.v2.data;
1709 break;
1710 }
1711 /* fall through for 4965 */
1712 case 0:
1713 case 1:
1714 case 2:
1715 hdr_size = 24;
1716 if (ucode_raw->size < hdr_size) {
1717 IWL_ERR(priv, "File size too small!\n");
1718 return -EINVAL;
1719 }
1720 pieces->build = 0;
1721 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1722 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1723 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1724 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1725 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1726 src = ucode->u.v1.data;
1727 break;
1728 }
1729
1730 /* Verify size of file vs. image size info in file's header */
1731 if (ucode_raw->size != hdr_size + pieces->inst_size +
1732 pieces->data_size + pieces->init_size +
1733 pieces->init_data_size + pieces->boot_size) {
1734
1735 IWL_ERR(priv,
1736 "uCode file size %d does not match expected size\n",
1737 (int)ucode_raw->size);
1738 return -EINVAL;
1739 }
1740
1741 pieces->inst = src;
1742 src += pieces->inst_size;
1743 pieces->data = src;
1744 src += pieces->data_size;
1745 pieces->init = src;
1746 src += pieces->init_size;
1747 pieces->init_data = src;
1748 src += pieces->init_data_size;
1749 pieces->boot = src;
1750 src += pieces->boot_size;
1751
1752 return 0;
1753}
1754
dd7a2509
JB		 1755static int iwlagn_wanted_ucode_alternative = 1;
1756
1757static int iwlagn_load_firmware(struct iwl_priv *priv,
1758 const struct firmware *ucode_raw,
1759 struct iwlagn_firmware_pieces *pieces,
1760 struct iwlagn_ucode_capabilities *capa)
1761{
1762 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1763 struct iwl_ucode_tlv *tlv;
1764 size_t len = ucode_raw->size;
1765 const u8 *data;
1766 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1767 u64 alternatives;
ad8d8333
WYG		 1768 u32 tlv_len;
1769 enum iwl_ucode_tlv_type tlv_type;
1770 const u8 *tlv_data;
dd7a2509 1771
ad8d8333
WYG		 1772 if (len < sizeof(*ucode)) {
1773 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1774 return -EINVAL;
ad8d8333 1775 }
dd7a2509 1776
ad8d8333
WYG		 1777 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1778 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1779 le32_to_cpu(ucode->magic));
dd7a2509 1780 return -EINVAL;
ad8d8333 1781 }
dd7a2509
JB		 1782
1783 /*
1784 * Check which alternatives are present, and "downgrade"
1785 * when the chosen alternative is not present, warning
1786 * the user when that happens. Some files may not have
1787 * any alternatives, so don't warn in that case.
1788 */
1789 alternatives = le64_to_cpu(ucode->alternatives);
1790 tmp = wanted_alternative;
1791 if (wanted_alternative > 63)
1792 wanted_alternative = 63;
1793 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1794 wanted_alternative--;
1795 if (wanted_alternative && wanted_alternative != tmp)
1796 IWL_WARN(priv,
1797 "uCode alternative %d not available, choosing %d\n",
1798 tmp, wanted_alternative);
1799
1800 priv->ucode_ver = le32_to_cpu(ucode->ver);
1801 pieces->build = le32_to_cpu(ucode->build);
1802 data = ucode->data;
1803
1804 len -= sizeof(*ucode);
1805
704da534 1806 while (len >= sizeof(*tlv)) {
dd7a2509 1807 u16 tlv_alt;
dd7a2509
JB		 1808
1809 len -= sizeof(*tlv);
1810 tlv = (void *)data;
1811
1812 tlv_len = le32_to_cpu(tlv->length);
1813 tlv_type = le16_to_cpu(tlv->type);
1814 tlv_alt = le16_to_cpu(tlv->alternative);
1815 tlv_data = tlv->data;
1816
ad8d8333
WYG		 1817 if (len < tlv_len) {
1818 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1819 len, tlv_len);
dd7a2509 1820 return -EINVAL;
ad8d8333 1821 }
dd7a2509
JB		 1822 len -= ALIGN(tlv_len, 4);
1823 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1824
1825 /*
1826 * Alternative 0 is always valid.
1827 *
1828 * Skip alternative TLVs that are not selected.
1829 */
1830 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1831 continue;
1832
1833 switch (tlv_type) {
1834 case IWL_UCODE_TLV_INST:
1835 pieces->inst = tlv_data;
1836 pieces->inst_size = tlv_len;
1837 break;
1838 case IWL_UCODE_TLV_DATA:
1839 pieces->data = tlv_data;
1840 pieces->data_size = tlv_len;
1841 break;
1842 case IWL_UCODE_TLV_INIT:
1843 pieces->init = tlv_data;
1844 pieces->init_size = tlv_len;
1845 break;
1846 case IWL_UCODE_TLV_INIT_DATA:
1847 pieces->init_data = tlv_data;
1848 pieces->init_data_size = tlv_len;
1849 break;
1850 case IWL_UCODE_TLV_BOOT:
1851 pieces->boot = tlv_data;
1852 pieces->boot_size = tlv_len;
1853 break;
1854 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1855 if (tlv_len != sizeof(u32))
1856 goto invalid_tlv_len;
1857 capa->max_probe_length =
ad8d8333 1858 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1859 break;
ece9c4ee
JB		 1860 case IWL_UCODE_TLV_PAN:
1861 if (tlv_len)
1862 goto invalid_tlv_len;
1863 capa->pan = true;
1864 break;
b2e640d4 1865 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1866 if (tlv_len != sizeof(u32))
1867 goto invalid_tlv_len;
1868 pieces->init_evtlog_ptr =
ad8d8333 1869 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1870 break;
1871 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 1872 if (tlv_len != sizeof(u32))
1873 goto invalid_tlv_len;
1874 pieces->init_evtlog_size =
ad8d8333 1875 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1876 break;
1877 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 1878 if (tlv_len != sizeof(u32))
1879 goto invalid_tlv_len;
1880 pieces->init_errlog_ptr =
ad8d8333 1881 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1882 break;
1883 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 1884 if (tlv_len != sizeof(u32))
1885 goto invalid_tlv_len;
1886 pieces->inst_evtlog_ptr =
ad8d8333 1887 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1888 break;
1889 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 1890 if (tlv_len != sizeof(u32))
1891 goto invalid_tlv_len;
1892 pieces->inst_evtlog_size =
ad8d8333 1893 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1894 break;
1895 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 1896 if (tlv_len != sizeof(u32))
1897 goto invalid_tlv_len;
1898 pieces->inst_errlog_ptr =
ad8d8333 1899 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 1900 break;
c8312fac
WYG		 1901 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1902 if (tlv_len)
704da534
JB		 1903 goto invalid_tlv_len;
1904 priv->enhance_sensitivity_table = true;
c8312fac 1905 break;
6a822d06 1906 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 1907 if (tlv_len != sizeof(u32))
1908 goto invalid_tlv_len;
1909 capa->standard_phy_calibration_size =
6a822d06
WYG		 1910 le32_to_cpup((__le32 *)tlv_data);
1911 break;
dd7a2509 1912 default:
ad8d8333 1913 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 1914 break;
1915 }
1916 }
1917
ad8d8333
WYG		 1918 if (len) {
1919 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1920 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 1921 return -EINVAL;
ad8d8333 1922 }
dd7a2509 1923
704da534
JB		 1924 return 0;
1925
1926 invalid_tlv_len:
1927 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1928 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1929
1930 return -EINVAL;
dd7a2509
JB		 1931}
1932
b481de9c 1933/**
b08dfd04 1934 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1935 *
b08dfd04
JB		 1936 * If loaded successfully, copies the firmware into buffers
1937 * for the card to fetch (via DMA).
b481de9c 1938 */
b08dfd04 1939static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1940{
b08dfd04 1941 struct iwl_priv *priv = context;
cc0f555d 1942 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 1943 int err;
1944 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 1945 const unsigned int api_max = priv->cfg->ucode_api_max;
1946 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 1947 u32 api_ver;
3e4de761 1948 char buildstr[25];
0e9a44dc 1949 u32 build;
dd7a2509
JB		 1950 struct iwlagn_ucode_capabilities ucode_capa = {
1951 .max_probe_length = 200,
6a822d06 1952 .standard_phy_calibration_size =
642454cc 1953 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 1954 };
0e9a44dc
JB		 1955
1956 memset(&pieces, 0, sizeof(pieces));
b481de9c 1957
b08dfd04 1958 if (!ucode_raw) {
39396085
JS		 1959 if (priv->fw_index <= priv->cfg->ucode_api_max)
1960 IWL_ERR(priv,
1961 "request for firmware file '%s' failed.\n",
1962 priv->firmware_name);
b08dfd04 1963 goto try_again;
b481de9c
ZY		 1964 }
1965
b08dfd04
JB		 1966 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1967 priv->firmware_name, ucode_raw->size);
b481de9c 1968
22adba2a
JB		 1969 /* Make sure that we got at least the API version number */
1970 if (ucode_raw->size < 4) {
15b1687c 1971 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1972 goto try_again;
b481de9c
ZY		 1973 }
1974
1975 /* Data from ucode file: header followed by uCode images */
cc0f555d 1976 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1977
0e9a44dc
JB		 1978 if (ucode->ver)
1979 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1980 else
dd7a2509
JB		 1981 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1982 &ucode_capa);
22adba2a 1983
0e9a44dc
JB		 1984 if (err)
1985 goto try_again;
b481de9c 1986
a0987a8d 1987 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 1988 build = pieces.build;
a0987a8d 1989
0e9a44dc
JB		 1990 /*
1991 * api_ver should match the api version forming part of the
1992 * firmware filename ... but we don't check for that and only rely
1993 * on the API version read from firmware header from here on forward
1994 */
65cccfb0
WYG		 1995 /* no api version check required for experimental uCode */
1996 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1997 if (api_ver < api_min || api_ver > api_max) {
1998 IWL_ERR(priv,
1999 "Driver unable to support your firmware API. "
2000 "Driver supports v%u, firmware is v%u.\n",
2001 api_max, api_ver);
2002 goto try_again;
2003 }
b08dfd04 2004
65cccfb0
WYG		 2005 if (api_ver != api_max)
2006 IWL_ERR(priv,
2007 "Firmware has old API version. Expected v%u, "
2008 "got v%u. New firmware can be obtained "
2009 "from http://www.intellinuxwireless.org.\n",
2010 api_max, api_ver);
2011 }
a0987a8d 2012
3e4de761 2013 if (build)
39396085
JS		 2014 sprintf(buildstr, " build %u%s", build,
2015 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2016 ? " (EXP)" : "");
3e4de761
JB		 2017 else
2018 buildstr[0] = '\0';
2019
2020 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2021 IWL_UCODE_MAJOR(priv->ucode_ver),
2022 IWL_UCODE_MINOR(priv->ucode_ver),
2023 IWL_UCODE_API(priv->ucode_ver),
2024 IWL_UCODE_SERIAL(priv->ucode_ver),
2025 buildstr);
a0987a8d 2026
5ebeb5a6
RC		 2027 snprintf(priv->hw->wiphy->fw_version,
2028 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2029 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2030 IWL_UCODE_MAJOR(priv->ucode_ver),
2031 IWL_UCODE_MINOR(priv->ucode_ver),
2032 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2033 IWL_UCODE_SERIAL(priv->ucode_ver),
2034 buildstr);
b481de9c 2035
b08dfd04
JB		 2036 /*
2037 * For any of the failures below (before allocating pci memory)
2038 * we will try to load a version with a smaller API -- maybe the
2039 * user just got a corrupted version of the latest API.
2040 */
2041
0e9a44dc
JB		 2042 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2043 priv->ucode_ver);
2044 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2045 pieces.inst_size);
2046 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2047 pieces.data_size);
2048 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2049 pieces.init_size);
2050 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2051 pieces.init_data_size);
2052 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2053 pieces.boot_size);
b481de9c
ZY		 2054
2055 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2056 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2057 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2058 pieces.inst_size);
b08dfd04 2059 goto try_again;
b481de9c
ZY		 2060 }
2061
0e9a44dc
JB		 2062 if (pieces.data_size > priv->hw_params.max_data_size) {
2063 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2064 pieces.data_size);
b08dfd04 2065 goto try_again;
b481de9c 2066 }
0e9a44dc
JB		 2067
2068 if (pieces.init_size > priv->hw_params.max_inst_size) {
2069 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2070 pieces.init_size);
b08dfd04 2071 goto try_again;
b481de9c 2072 }
0e9a44dc
JB		 2073
2074 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2075 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2076 pieces.init_data_size);
b08dfd04 2077 goto try_again;
b481de9c 2078 }
0e9a44dc
JB		 2079
2080 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2081 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2082 pieces.boot_size);
b08dfd04 2083 goto try_again;
b481de9c
ZY		 2084 }
2085
2086 /* Allocate ucode buffers for card's bus-master loading ... */
2087
2088 /* Runtime instructions and 2 copies of data:
2089 * 1) unmodified from disk
2090 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2091 priv->ucode_code.len = pieces.inst_size;
98c92211 2092 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2093
0e9a44dc 2094 priv->ucode_data.len = pieces.data_size;
98c92211 2095 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2096
0e9a44dc 2097 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2098 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2099
1f304e4e
ZY		 2100 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2101 !priv->ucode_data_backup.v_addr)
2102 goto err_pci_alloc;
2103
b481de9c 2104 /* Initialization instructions and data */
0e9a44dc
JB		 2105 if (pieces.init_size && pieces.init_data_size) {
2106 priv->ucode_init.len = pieces.init_size;
98c92211 2107 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2108
0e9a44dc 2109 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2110 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2111
2112 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2113 goto err_pci_alloc;
2114 }
b481de9c
ZY		 2115
2116 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2117 if (pieces.boot_size) {
2118 priv->ucode_boot.len = pieces.boot_size;
98c92211 2119 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2120
90e759d1
TW		 2121 if (!priv->ucode_boot.v_addr)
2122 goto err_pci_alloc;
2123 }
b481de9c 2124
b2e640d4
JB		 2125 /* Now that we can no longer fail, copy information */
2126
2127 /*
2128 * The (size - 16) / 12 formula is based on the information recorded
2129 * for each event, which is of mode 1 (including timestamp) for all
2130 * new microcodes that include this information.
2131 */
2132 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2133 if (pieces.init_evtlog_size)
2134 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2135 else
7cb1b088
WYG		 2136 priv->_agn.init_evtlog_size =
2137 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2138 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2139 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2140 if (pieces.inst_evtlog_size)
2141 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2142 else
7cb1b088
WYG		 2143 priv->_agn.inst_evtlog_size =
2144 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2145 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2146
ece9c4ee
JB		 2147 if (ucode_capa.pan) {
2148 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
c10afb6e 2149 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
ece9c4ee
JB		 2150 } else
2151 priv->sta_key_max_num = STA_KEY_MAX_NUM;
c10afb6e 2152
b481de9c
ZY		 2153 /* Copy images into buffers for card's bus-master reads ... */
2154
2155 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2156 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2157 pieces.inst_size);
2158 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2159
e1623446 2160 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2161 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2162
0e9a44dc
JB		 2163 /*
2164 * Runtime data
2165 * NOTE: Copy into backup buffer will be done in iwl_up()
2166 */
2167 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2168 pieces.data_size);
2169 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2170 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2171
2172 /* Initialization instructions */
2173 if (pieces.init_size) {
e1623446 2174 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2175 pieces.init_size);
2176 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2177 }
2178
0e9a44dc
JB		 2179 /* Initialization data */
2180 if (pieces.init_data_size) {
e1623446 2181 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2182 pieces.init_data_size);
2183 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2184 pieces.init_data_size);
b481de9c
ZY		 2185 }
2186
0e9a44dc
JB		 2187 /* Bootstrap instructions */
2188 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2189 pieces.boot_size);
2190 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2191
6a822d06
WYG		 2192 /*
2193 * figure out the offset of chain noise reset and gain commands
2194 * base on the size of standard phy calibration commands table size
2195 */
2196 if (ucode_capa.standard_phy_calibration_size >
2197 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2198 ucode_capa.standard_phy_calibration_size =
2199 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2200
2201 priv->_agn.phy_calib_chain_noise_reset_cmd =
2202 ucode_capa.standard_phy_calibration_size;
2203 priv->_agn.phy_calib_chain_noise_gain_cmd =
2204 ucode_capa.standard_phy_calibration_size + 1;
2205
b08dfd04
JB		 2206 /**************************************************
2207 * This is still part of probe() in a sense...
2208 *
2209 * 9. Setup and register with mac80211 and debugfs
2210 **************************************************/
dd7a2509 2211 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2212 if (err)
2213 goto out_unbind;
2214
2215 err = iwl_dbgfs_register(priv, DRV_NAME);
2216 if (err)
2217 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2218
7d47618a
EG		 2219 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2220 &iwl_attribute_group);
2221 if (err) {
2222 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2223 goto out_unbind;
2224 }
2225
b481de9c
ZY		 2226 /* We have our copies now, allow OS release its copies */
2227 release_firmware(ucode_raw);
a15707d8 2228 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2229 return;
2230
2231 try_again:
2232 /* try next, if any */
2233 if (iwl_request_firmware(priv, false))
2234 goto out_unbind;
2235 release_firmware(ucode_raw);
2236 return;
b481de9c
ZY		 2237
2238 err_pci_alloc:
15b1687c 2239 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2240 iwl_dealloc_ucode_pci(priv);
b08dfd04 2241 out_unbind:
a15707d8 2242 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2243 device_release_driver(&priv->pci_dev->dev);
b481de9c 2244 release_firmware(ucode_raw);
b481de9c
ZY		 2245}
2246
b7a79404
RC		 2247static const char *desc_lookup_text[] = {
2248 "OK",
2249 "FAIL",
2250 "BAD_PARAM",
2251 "BAD_CHECKSUM",
2252 "NMI_INTERRUPT_WDG",
2253 "SYSASSERT",
2254 "FATAL_ERROR",
2255 "BAD_COMMAND",
2256 "HW_ERROR_TUNE_LOCK",
2257 "HW_ERROR_TEMPERATURE",
2258 "ILLEGAL_CHAN_FREQ",
2259 "VCC_NOT_STABLE",
2260 "FH_ERROR",
2261 "NMI_INTERRUPT_HOST",
2262 "NMI_INTERRUPT_ACTION_PT",
2263 "NMI_INTERRUPT_UNKNOWN",
2264 "UCODE_VERSION_MISMATCH",
2265 "HW_ERROR_ABS_LOCK",
2266 "HW_ERROR_CAL_LOCK_FAIL",
2267 "NMI_INTERRUPT_INST_ACTION_PT",
2268 "NMI_INTERRUPT_DATA_ACTION_PT",
2269 "NMI_TRM_HW_ER",
2270 "NMI_INTERRUPT_TRM",
2271 "NMI_INTERRUPT_BREAK_POINT"
2272 "DEBUG_0",
2273 "DEBUG_1",
2274 "DEBUG_2",
2275 "DEBUG_3",
b7a79404
RC		 2276};
2277
4b58645c
JS		 2278static struct { char *name; u8 num; } advanced_lookup[] = {
2279 { "NMI_INTERRUPT_WDG", 0x34 },
2280 { "SYSASSERT", 0x35 },
2281 { "UCODE_VERSION_MISMATCH", 0x37 },
2282 { "BAD_COMMAND", 0x38 },
2283 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2284 { "FATAL_ERROR", 0x3D },
2285 { "NMI_TRM_HW_ERR", 0x46 },
2286 { "NMI_INTERRUPT_TRM", 0x4C },
2287 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2288 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2289 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2290 { "NMI_INTERRUPT_HOST", 0x66 },
2291 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2292 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2293 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2294 { "ADVANCED_SYSASSERT", 0 },
2295};
2296
2297static const char *desc_lookup(u32 num)
b7a79404 2298{
4b58645c
JS		 2299 int i;
2300 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 2301
4b58645c
JS		 2302 if (num < max)
2303 return desc_lookup_text[num];
b7a79404 2304
4b58645c
JS		 2305 max = ARRAY_SIZE(advanced_lookup) - 1;
2306 for (i = 0; i < max; i++) {
2307 if (advanced_lookup[i].num == num)
2308 break;;
2309 }
2310 return advanced_lookup[i].name;
b7a79404
RC		 2311}
2312
2313#define ERROR_START_OFFSET (1 * sizeof(u32))
2314#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2315
2316void iwl_dump_nic_error_log(struct iwl_priv *priv)
2317{
2318 u32 data2, line;
2319 u32 desc, time, count, base, data1;
2320 u32 blink1, blink2, ilink1, ilink2;
461ef382 2321 u32 pc, hcmd;
b7a79404 2322
b2e640d4 2323 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2324 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2325 if (!base)
2326 base = priv->_agn.init_errlog_ptr;
2327 } else {
b7a79404 2328 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2329 if (!base)
2330 base = priv->_agn.inst_errlog_ptr;
2331 }
b7a79404
RC		 2332
2333 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2334 IWL_ERR(priv,
2335 "Not valid error log pointer 0x%08X for %s uCode\n",
2336 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2337 return;
2338 }
2339
2340 count = iwl_read_targ_mem(priv, base);
2341
2342 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2343 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2344 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2345 priv->status, count);
2346 }
2347
2348 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
6e6ebf4b 2349 priv->isr_stats.err_code = desc;
461ef382 2350 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2351 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2352 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2353 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2354 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2355 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2356 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2357 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2358 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2359 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2360
be1a71a1
JB		 2361 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2362 blink1, blink2, ilink1, ilink2);
2363
87563715 2364 IWL_ERR(priv, "Desc Time "
b7a79404 2365 "data1 data2 line\n");
87563715 2366 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2367 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2368 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2369 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2370 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2371}
2372
2373#define EVENT_START_OFFSET (4 * sizeof(u32))
2374
2375/**
2376 * iwl_print_event_log - Dump error event log to syslog
2377 *
2378 */
b03d7d0f
WYG		 2379static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2380 u32 num_events, u32 mode,
2381 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2382{
2383 u32 i;
2384 u32 base; /* SRAM byte address of event log header */
2385 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2386 u32 ptr; /* SRAM byte address of log data */
2387 u32 ev, time, data; /* event log data */
e5854471 2388 unsigned long reg_flags;
b7a79404
RC		 2389
2390 if (num_events == 0)
b03d7d0f 2391 return pos;
b2e640d4
JB		 2392
2393 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2394 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2395 if (!base)
2396 base = priv->_agn.init_evtlog_ptr;
2397 } else {
b7a79404 2398 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2399 if (!base)
2400 base = priv->_agn.inst_evtlog_ptr;
2401 }
b7a79404
RC		 2402
2403 if (mode == 0)
2404 event_size = 2 * sizeof(u32);
2405 else
2406 event_size = 3 * sizeof(u32);
2407
2408 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2409
e5854471
BC		 2410 /* Make sure device is powered up for SRAM reads */
2411 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2412 iwl_grab_nic_access(priv);
2413
2414 /* Set starting address; reads will auto-increment */
2415 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2416 rmb();
2417
b7a79404
RC		 2418 /* "time" is actually "data" for mode 0 (no timestamp).
2419 * place event id # at far right for easier visual parsing. */
2420 for (i = 0; i < num_events; i++) {
e5854471
BC		 2421 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2422 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2423 if (mode == 0) {
2424 /* data, ev */
b03d7d0f
WYG		 2425 if (bufsz) {
2426 pos += scnprintf(*buf + pos, bufsz - pos,
2427 "EVT_LOG:0x%08x:%04u\n",
2428 time, ev);
2429 } else {
2430 trace_iwlwifi_dev_ucode_event(priv, 0,
2431 time, ev);
2432 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2433 time, ev);
2434 }
b7a79404 2435 } else {
e5854471 2436 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2437 if (bufsz) {
2438 pos += scnprintf(*buf + pos, bufsz - pos,
2439 "EVT_LOGT:%010u:0x%08x:%04u\n",
2440 time, data, ev);
2441 } else {
2442 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2443 time, data, ev);
b03d7d0f
WYG		 2444 trace_iwlwifi_dev_ucode_event(priv, time,
2445 data, ev);
2446 }
b7a79404
RC		 2447 }
2448 }
e5854471
BC		 2449
2450 /* Allow device to power down */
2451 iwl_release_nic_access(priv);
2452 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2453 return pos;
b7a79404
RC		 2454}
2455
c341ddb2
WYG		 2456/**
2457 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2458 */
b03d7d0f
WYG		 2459static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2460 u32 num_wraps, u32 next_entry,
2461 u32 size, u32 mode,
2462 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2463{
2464 /*
2465 * display the newest DEFAULT_LOG_ENTRIES entries
2466 * i.e the entries just before the next ont that uCode would fill.
2467 */
2468 if (num_wraps) {
2469 if (next_entry < size) {
b03d7d0f
WYG		 2470 pos = iwl_print_event_log(priv,
2471 capacity - (size - next_entry),
2472 size - next_entry, mode,
2473 pos, buf, bufsz);
2474 pos = iwl_print_event_log(priv, 0,
2475 next_entry, mode,
2476 pos, buf, bufsz);
c341ddb2 2477 } else
b03d7d0f
WYG		 2478 pos = iwl_print_event_log(priv, next_entry - size,
2479 size, mode, pos, buf, bufsz);
c341ddb2 2480 } else {
b03d7d0f
WYG		 2481 if (next_entry < size) {
2482 pos = iwl_print_event_log(priv, 0, next_entry,
2483 mode, pos, buf, bufsz);
2484 } else {
2485 pos = iwl_print_event_log(priv, next_entry - size,
2486 size, mode, pos, buf, bufsz);
2487 }
c341ddb2 2488 }
b03d7d0f 2489 return pos;
c341ddb2
WYG		 2490}
2491
c341ddb2
WYG		 2492#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2493
b03d7d0f
WYG		 2494int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2495 char **buf, bool display)
b7a79404
RC		 2496{
2497 u32 base; /* SRAM byte address of event log header */
2498 u32 capacity; /* event log capacity in # entries */
2499 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2500 u32 num_wraps; /* # times uCode wrapped to top of log */
2501 u32 next_entry; /* index of next entry to be written by uCode */
2502 u32 size; /* # entries that we'll print */
b2e640d4 2503 u32 logsize;
b03d7d0f
WYG		 2504 int pos = 0;
2505 size_t bufsz = 0;
b7a79404 2506
b2e640d4 2507 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2508 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2509 logsize = priv->_agn.init_evtlog_size;
2510 if (!base)
2511 base = priv->_agn.init_evtlog_ptr;
2512 } else {
b7a79404 2513 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2514 logsize = priv->_agn.inst_evtlog_size;
2515 if (!base)
2516 base = priv->_agn.inst_evtlog_ptr;
2517 }
b7a79404
RC		 2518
2519 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2520 IWL_ERR(priv,
2521 "Invalid event log pointer 0x%08X for %s uCode\n",
2522 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2523 return -EINVAL;
b7a79404
RC		 2524 }
2525
2526 /* event log header */
2527 capacity = iwl_read_targ_mem(priv, base);
2528 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2529 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2530 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2531
b2e640d4 2532 if (capacity > logsize) {
84c40692 2533 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2534 capacity, logsize);
2535 capacity = logsize;
84c40692
BC		 2536 }
2537
b2e640d4 2538 if (next_entry > logsize) {
84c40692 2539 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2540 next_entry, logsize);
2541 next_entry = logsize;
84c40692
BC		 2542 }
2543
b7a79404
RC		 2544 size = num_wraps ? capacity : next_entry;
2545
2546 /* bail out if nothing in log */
2547 if (size == 0) {
2548 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2549 return pos;
b7a79404
RC		 2550 }
2551
9f28ebc3 2552 /* enable/disable bt channel inhibition */
f37837c9
WYG		 2553 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2554
c341ddb2 2555#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2556 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2557 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2558 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2559#else
2560 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2561 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2562#endif
2563 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2564 size);
b7a79404 2565
c341ddb2 2566#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2567 if (display) {
2568 if (full_log)
2569 bufsz = capacity * 48;
2570 else
2571 bufsz = size * 48;
2572 *buf = kmalloc(bufsz, GFP_KERNEL);
2573 if (!*buf)
937c397e 2574 return -ENOMEM;
b03d7d0f 2575 }
c341ddb2
WYG		 2576 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2577 /*
2578 * if uCode has wrapped back to top of log,
2579 * start at the oldest entry,
2580 * i.e the next one that uCode would fill.
2581 */
2582 if (num_wraps)
b03d7d0f
WYG		 2583 pos = iwl_print_event_log(priv, next_entry,
2584 capacity - next_entry, mode,
2585 pos, buf, bufsz);
c341ddb2 2586 /* (then/else) start at top of log */
b03d7d0f
WYG		 2587 pos = iwl_print_event_log(priv, 0,
2588 next_entry, mode, pos, buf, bufsz);
c341ddb2 2589 } else
b03d7d0f
WYG		 2590 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2591 next_entry, size, mode,
2592 pos, buf, bufsz);
c341ddb2 2593#else
b03d7d0f
WYG		 2594 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2595 next_entry, size, mode,
2596 pos, buf, bufsz);
b7a79404 2597#endif
b03d7d0f 2598 return pos;
c341ddb2 2599}
b7a79404 2600
0975cc8f
WYG		 2601static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2602{
2603 struct iwl_ct_kill_config cmd;
2604 struct iwl_ct_kill_throttling_config adv_cmd;
2605 unsigned long flags;
2606 int ret = 0;
2607
2608 spin_lock_irqsave(&priv->lock, flags);
2609 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2610 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2611 spin_unlock_irqrestore(&priv->lock, flags);
2612 priv->thermal_throttle.ct_kill_toggle = false;
2613
7cb1b088 2614 if (priv->cfg->base_params->support_ct_kill_exit) {
0975cc8f
WYG		 2615 adv_cmd.critical_temperature_enter =
2616 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2617 adv_cmd.critical_temperature_exit =
2618 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2619
2620 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2621 sizeof(adv_cmd), &adv_cmd);
2622 if (ret)
2623 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2624 else
2625 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2626 "succeeded, "
2627 "critical temperature enter is %d,"
2628 "exit is %d\n",
2629 priv->hw_params.ct_kill_threshold,
2630 priv->hw_params.ct_kill_exit_threshold);
2631 } else {
2632 cmd.critical_temperature_R =
2633 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2634
2635 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2636 sizeof(cmd), &cmd);
2637 if (ret)
2638 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2639 else
2640 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2641 "succeeded, "
2642 "critical temperature is %d\n",
2643 priv->hw_params.ct_kill_threshold);
2644 }
2645}
2646
6d6a1afd
SZ		 2647static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2648{
2649 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2650 struct iwl_host_cmd cmd = {
2651 .id = CALIBRATION_CFG_CMD,
2652 .len = sizeof(struct iwl_calib_cfg_cmd),
2653 .data = &calib_cfg_cmd,
2654 };
2655
2656 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2657 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
7cb1b088 2658 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
6d6a1afd
SZ		 2659
2660 return iwl_send_cmd(priv, &cmd);
2661}
2662
2663
b481de9c 2664/**
4a4a9e81 2665 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2666 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2667 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2668 */
4a4a9e81 2669static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2670{
57aab75a 2671 int ret = 0;
246ed355 2672 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 2673
e1623446 2674 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 2675
b481de9c
ZY		 2676 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2677 * This is a paranoid check, because we would not have gotten the
2678 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2679 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2680 /* Runtime instruction load was bad;
2681 * take it all the way back down so we can try again */
e1623446 2682 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2683 goto restart;
2684 }
2685
57aab75a
TW		 2686 ret = priv->cfg->ops->lib->alive_notify(priv);
2687 if (ret) {
39aadf8c
WT		 2688 IWL_WARN(priv,
2689 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2690 goto restart;
2691 }
2692
6d6a1afd 2693
5b9f8cd3 2694 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2695 set_bit(STATUS_ALIVE, &priv->status);
2696
22de94de
SG		 2697 /* Enable watchdog to monitor the driver tx queues */
2698 iwl_setup_watchdog(priv);
b74e31a9 2699
fee1247a 2700 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2701 return;
2702
bc795df1 2703 /* download priority table before any calibration request */
7cb1b088
WYG		 2704 if (priv->cfg->bt_params &&
2705 priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f
WYG		 2706 /* Configure Bluetooth device coexistence support */
2707 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2708 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2709 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2710 priv->cfg->ops->hcmd->send_bt_config(priv);
2711 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
a5901cbb 2712 iwlagn_send_prio_tbl(priv);
f7322f8f
WYG		 2713
2714 /* FIXME: w/a to force change uCode BT state machine */
2715 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2716 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2717 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2718 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2719 }
bc795df1
WYG		 2720 if (priv->hw_params.calib_rt_cfg)
2721 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2722
36d6825b 2723 ieee80211_wake_queues(priv->hw);
b481de9c 2724
470ab2dd 2725 priv->active_rate = IWL_RATES_MASK;
b481de9c 2726
2f748dec
WYG		 2727 /* Configure Tx antenna selection based on H/W config */
2728 if (priv->cfg->ops->hcmd->set_tx_ant)
2729 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2730
246ed355 2731 if (iwl_is_associated_ctx(ctx)) {
c1adf9fb 2732 struct iwl_rxon_cmd *active_rxon =
246ed355 2733 (struct iwl_rxon_cmd *)&ctx->active;
019fb97d 2734 /* apply any changes in staging */
246ed355 2735 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2736 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2737 } else {
d0fe478c 2738 struct iwl_rxon_context *tmp;
b481de9c 2739 /* Initialize our rx_config data */
d0fe478c
JB		 2740 for_each_context(priv, tmp)
2741 iwl_connection_init_rx_config(priv, tmp);
45823531
AK		 2742
2743 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 2744 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c
ZY		 2745 }
2746
7cb1b088
WYG		 2747 if (priv->cfg->bt_params &&
2748 !priv->cfg->bt_params->advanced_bt_coexist) {
aeb4a2ee
WYG		 2749 /* Configure Bluetooth device coexistence support */
2750 priv->cfg->ops->hcmd->send_bt_config(priv);
2751 }
b481de9c 2752
4a4a9e81
TW		 2753 iwl_reset_run_time_calib(priv);
2754
9e2e7422
WYG		 2755 set_bit(STATUS_READY, &priv->status);
2756
b481de9c 2757 /* Configure the adapter for unassociated operation */
246ed355 2758 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 2759
2760 /* At this point, the NIC is initialized and operational */
47f4a587 2761 iwl_rf_kill_ct_config(priv);
5a66926a 2762
e1623446 2763 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
5a66926a 2764 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2765
e312c24c 2766 iwl_power_update_mode(priv, true);
7e246191
RC		 2767 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2768
c46fbefa 2769
b481de9c
ZY		 2770 return;
2771
2772 restart:
2773 queue_work(priv->workqueue, &priv->restart);
2774}
2775
4e39317d 2776static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2777
5b9f8cd3 2778static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2779{
2780 unsigned long flags;
2781 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2782
e1623446 2783 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2784
d745d472
SG		 2785 iwl_scan_cancel_timeout(priv, 200);
2786
2787 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2788
b62177a0
SG		 2789 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2790 * to prevent rearm timer */
22de94de 2791 del_timer_sync(&priv->watchdog);
b62177a0 2792
dcef732c 2793 iwl_clear_ucode_stations(priv, NULL);
a194e324 2794 iwl_dealloc_bcast_stations(priv);
db125c78 2795 iwl_clear_driver_stations(priv);
b481de9c 2796
a1174138 2797 /* reset BT coex data */
da5dbb97 2798 priv->bt_status = 0;
7cb1b088
WYG		 2799 if (priv->cfg->bt_params)
2800 priv->bt_traffic_load =
2801 priv->cfg->bt_params->bt_init_traffic_load;
2802 else
2803 priv->bt_traffic_load = 0;
bee008b7
WYG		 2804 priv->bt_full_concurrent = false;
2805 priv->bt_ci_compliance = 0;
a1174138 2806
b481de9c
ZY		 2807 /* Unblock any waiting calls */
2808 wake_up_interruptible_all(&priv->wait_command_queue);
2809
b481de9c
ZY		 2810 /* Wipe out the EXIT_PENDING status bit if we are not actually
2811 * exiting the module */
2812 if (!exit_pending)
2813 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2814
2815 /* stop and reset the on-board processor */
3395f6e9 2816 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2817
2818 /* tell the device to stop sending interrupts */
0359facc 2819 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2820 iwl_disable_interrupts(priv);
0359facc
MA		 2821 spin_unlock_irqrestore(&priv->lock, flags);
2822 iwl_synchronize_irq(priv);
b481de9c
ZY		 2823
2824 if (priv->mac80211_registered)
2825 ieee80211_stop_queues(priv->hw);
2826
5b9f8cd3 2827 /* If we have not previously called iwl_init() then
a60e77e5 2828 * clear all bits but the RF Kill bit and return */
fee1247a 2829 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2830 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2831 STATUS_RF_KILL_HW |
9788864e
RC		 2832 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2833 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2834 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2835 STATUS_EXIT_PENDING;
b481de9c
ZY		 2836 goto exit;
2837 }
2838
6da3a13e 2839 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2840 * bit and continue taking the NIC down. */
b481de9c
ZY		 2841 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2842 STATUS_RF_KILL_HW |
9788864e
RC		 2843 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2844 STATUS_GEO_CONFIGURED |
b481de9c 2845 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2846 STATUS_FW_ERROR |
2847 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2848 STATUS_EXIT_PENDING;
b481de9c 2849
ef850d7c 2850 /* device going down, Stop using ICT table */
e39fdee1
WYG		 2851 if (priv->cfg->ops->lib->isr_ops.disable)
2852 priv->cfg->ops->lib->isr_ops.disable(priv);
b481de9c 2853
74bcdb33 2854 iwlagn_txq_ctx_stop(priv);
54b81550 2855 iwlagn_rxq_stop(priv);
b481de9c 2856
309e731a
BC		 2857 /* Power-down device's busmaster DMA clocks */
2858 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2859 udelay(5);
2860
309e731a
BC		 2861 /* Make sure (redundant) we've released our request to stay awake */
2862 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2863
4d2ccdb9 2864 /* Stop the device, and put it in low power state */
14e8e4af 2865 iwl_apm_stop(priv);
4d2ccdb9 2866
b481de9c 2867 exit:
885ba202 2868 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c 2869
77834543 2870 dev_kfree_skb(priv->beacon_skb);
12e934dc 2871 priv->beacon_skb = NULL;
b481de9c
ZY		 2872
2873 /* clear out any free frames */
fcab423d 2874 iwl_clear_free_frames(priv);
b481de9c
ZY		 2875}
2876
5b9f8cd3 2877static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2878{
2879 mutex_lock(&priv->mutex);
5b9f8cd3 2880 __iwl_down(priv);
b481de9c 2881 mutex_unlock(&priv->mutex);
b24d22b1 2882
4e39317d 2883 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2884}
2885
086ed117
MA		 2886#define HW_READY_TIMEOUT (50)
2887
2888static int iwl_set_hw_ready(struct iwl_priv *priv)
2889{
2890 int ret = 0;
2891
2892 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2893 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2894
2895 /* See if we got it */
2896 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2897 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2898 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2899 HW_READY_TIMEOUT);
2900 if (ret != -ETIMEDOUT)
2901 priv->hw_ready = true;
2902 else
2903 priv->hw_ready = false;
2904
2905 IWL_DEBUG_INFO(priv, "hardware %s\n",
2906 (priv->hw_ready == 1) ? "ready" : "not ready");
2907 return ret;
2908}
2909
2910static int iwl_prepare_card_hw(struct iwl_priv *priv)
2911{
2912 int ret = 0;
2913
91dd6c27 2914 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2915
3354a0f6
MA		 2916 ret = iwl_set_hw_ready(priv);
2917 if (priv->hw_ready)
2918 return ret;
2919
2920 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 2921 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2922 CSR_HW_IF_CONFIG_REG_PREPARE);
2923
2924 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2925 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2926 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2927
3354a0f6 2928 /* HW should be ready by now, check again. */
086ed117
MA		 2929 if (ret != -ETIMEDOUT)
2930 iwl_set_hw_ready(priv);
2931
2932 return ret;
2933}
2934
b481de9c
ZY		 2935#define MAX_HW_RESTARTS 5
2936
5b9f8cd3 2937static int __iwl_up(struct iwl_priv *priv)
b481de9c 2938{
a194e324 2939 struct iwl_rxon_context *ctx;
57aab75a
TW		 2940 int i;
2941 int ret;
b481de9c
ZY		 2942
2943 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2944 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 2945 return -EIO;
2946 }
2947
e903fbd4 2948 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2949 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 2950 return -EIO;
2951 }
2952
a194e324 2953 for_each_context(priv, ctx) {
a30e3112 2954 ret = iwlagn_alloc_bcast_station(priv, ctx);
a194e324
JB		 2955 if (ret) {
2956 iwl_dealloc_bcast_stations(priv);
2957 return ret;
2958 }
2959 }
2c810ccd 2960
086ed117
MA		 2961 iwl_prepare_card_hw(priv);
2962
2963 if (!priv->hw_ready) {
2964 IWL_WARN(priv, "Exit HW not ready\n");
2965 return -EIO;
2966 }
2967
e655b9f0 2968 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2969 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2970 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2971 else
e655b9f0 2972 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2973
c1842d61 2974 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 2975 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2976
5b9f8cd3 2977 iwl_enable_interrupts(priv);
a60e77e5 2978 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2979 return 0;
b481de9c
ZY		 2980 }
2981
3395f6e9 2982 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2983
13bb9483 2984 /* must be initialised before iwl_hw_nic_init */
751ca305
JB		 2985 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2986 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2987 else
2988 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
13bb9483 2989
74bcdb33 2990 ret = iwlagn_hw_nic_init(priv);
57aab75a 2991 if (ret) {
15b1687c 2992 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2993 return ret;
b481de9c
ZY		 2994 }
2995
2996 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 2997 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2998 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 2999 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3000
3001 /* clear (again), then enable host interrupts */
3395f6e9 3002 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 3003 iwl_enable_interrupts(priv);
b481de9c
ZY		 3004
3005 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3006 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3007 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3008
3009 /* Copy original ucode data image from disk into backup cache.
3010 * This will be used to initialize the on-board processor's
3011 * data SRAM for a clean start when the runtime program first loads. */
3012 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 3013 priv->ucode_data.len);
b481de9c 3014
b481de9c
ZY		 3015 for (i = 0; i < MAX_HW_RESTARTS; i++) {
3016
b481de9c
ZY		 3017 /* load bootstrap state machine,
3018 * load bootstrap program into processor's memory,
3019 * prepare to load the "initialize" uCode */
57aab75a 3020 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 3021
57aab75a 3022 if (ret) {
15b1687c
WT		 3023 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3024 ret);
b481de9c
ZY		 3025 continue;
3026 }
3027
3028 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 3029 iwl_nic_start(priv);
b481de9c 3030
e1623446 3031 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 3032
3033 return 0;
3034 }
3035
3036 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 3037 __iwl_down(priv);
64e72c3e 3038 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 3039
3040 /* tried to restart and config the device for as long as our
3041 * patience could withstand */
15b1687c 3042 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 3043 return -EIO;
3044}
3045
3046
3047/*****************************************************************************
3048 *
3049 * Workqueue callbacks
3050 *
3051 *****************************************************************************/
3052
4a4a9e81 3053static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 3054{
c79dd5b5
TW		 3055 struct iwl_priv *priv =
3056 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 3057
3058 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3059 return;
3060
3061 mutex_lock(&priv->mutex);
f3ccc08c 3062 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 3063 mutex_unlock(&priv->mutex);
3064}
3065
4a4a9e81 3066static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 3067{
c79dd5b5
TW		 3068 struct iwl_priv *priv =
3069 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 3070
3071 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3072 return;
3073
258c44a0 3074 /* enable dram interrupt */
e39fdee1
WYG		 3075 if (priv->cfg->ops->lib->isr_ops.reset)
3076 priv->cfg->ops->lib->isr_ops.reset(priv);
258c44a0 3077
b481de9c 3078 mutex_lock(&priv->mutex);
4a4a9e81 3079 iwl_alive_start(priv);
b481de9c
ZY		 3080 mutex_unlock(&priv->mutex);
3081}
3082
16e727e8
EG		 3083static void iwl_bg_run_time_calib_work(struct work_struct *work)
3084{
3085 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3086 run_time_calib_work);
3087
3088 mutex_lock(&priv->mutex);
3089
3090 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3091 test_bit(STATUS_SCANNING, &priv->status)) {
3092 mutex_unlock(&priv->mutex);
3093 return;
3094 }
3095
3096 if (priv->start_calib) {
9f60e7ee 3097 if (iwl_bt_statistics(priv)) {
7980fba5
WYG		 3098 iwl_chain_noise_calibration(priv,
3099 (void *)&priv->_agn.statistics_bt);
3100 iwl_sensitivity_calibration(priv,
3101 (void *)&priv->_agn.statistics_bt);
3102 } else {
3103 iwl_chain_noise_calibration(priv,
3104 (void *)&priv->_agn.statistics);
3105 iwl_sensitivity_calibration(priv,
3106 (void *)&priv->_agn.statistics);
3107 }
16e727e8
EG		 3108 }
3109
3110 mutex_unlock(&priv->mutex);
16e727e8
EG		 3111}
3112
5b9f8cd3 3113static void iwl_bg_restart(struct work_struct *data)
b481de9c 3114{
c79dd5b5 3115 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 3116
3117 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3118 return;
3119
19cc1087 3120 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
8bd413e6 3121 struct iwl_rxon_context *ctx;
187bc4f6 3122 bool bt_full_concurrent;
bee008b7 3123 u8 bt_ci_compliance;
511b082d 3124 u8 bt_load;
da5dbb97 3125 u8 bt_status;
511b082d 3126
19cc1087 3127 mutex_lock(&priv->mutex);
8bd413e6
JB		 3128 for_each_context(priv, ctx)
3129 ctx->vif = NULL;
19cc1087 3130 priv->is_open = 0;
511b082d
JB		 3131
3132 /*
3133 * __iwl_down() will clear the BT status variables,
3134 * which is correct, but when we restart we really
3135 * want to keep them so restore them afterwards.
3136 *
3137 * The restart process will later pick them up and
3138 * re-configure the hw when we reconfigure the BT
3139 * command.
3140 */
bee008b7
WYG		 3141 bt_full_concurrent = priv->bt_full_concurrent;
3142 bt_ci_compliance = priv->bt_ci_compliance;
511b082d 3143 bt_load = priv->bt_traffic_load;
da5dbb97 3144 bt_status = priv->bt_status;
511b082d 3145
a1174138 3146 __iwl_down(priv);
511b082d 3147
bee008b7
WYG		 3148 priv->bt_full_concurrent = bt_full_concurrent;
3149 priv->bt_ci_compliance = bt_ci_compliance;
511b082d 3150 priv->bt_traffic_load = bt_load;
da5dbb97 3151 priv->bt_status = bt_status;
511b082d 3152
19cc1087 3153 mutex_unlock(&priv->mutex);
a1174138 3154 iwl_cancel_deferred_work(priv);
19cc1087
JB		 3155 ieee80211_restart_hw(priv->hw);
3156 } else {
3157 iwl_down(priv);
80676518
JB		 3158
3159 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3160 return;
3161
3162 mutex_lock(&priv->mutex);
3163 __iwl_up(priv);
3164 mutex_unlock(&priv->mutex);
19cc1087 3165 }
b481de9c
ZY		 3166}
3167
5b9f8cd3 3168static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3169{
c79dd5b5
TW		 3170 struct iwl_priv *priv =
3171 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3172
3173 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3174 return;
3175
3176 mutex_lock(&priv->mutex);
54b81550 3177 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3178 mutex_unlock(&priv->mutex);
3179}
3180
b481de9c
ZY		 3181/*****************************************************************************
3182 *
3183 * mac80211 entry point functions
3184 *
3185 *****************************************************************************/
3186
154b25ce 3187#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3188
f0b6e2e8
RC		 3189/*
3190 * Not a mac80211 entry point function, but it fits in with all the
3191 * other mac80211 functions grouped here.
3192 */
dd7a2509
JB		 3193static int iwl_mac_setup_register(struct iwl_priv *priv,
3194 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3195{
3196 int ret;
3197 struct ieee80211_hw *hw = priv->hw;
d0fe478c
JB		 3198 struct iwl_rxon_context *ctx;
3199
f0b6e2e8
RC		 3200 hw->rate_control_algorithm = "iwl-agn-rs";
3201
3202 /* Tell mac80211 our characteristics */
3203 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8 3204 IEEE80211_HW_AMPDU_AGGREGATION |
2491fa42 3205 IEEE80211_HW_NEED_DTIM_PERIOD |
6fb5511a
JB		 3206 IEEE80211_HW_SPECTRUM_MGMT |
3207 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
f0b6e2e8 3208
9b768832
JB		 3209 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3210
7cb1b088 3211 if (!priv->cfg->base_params->broken_powersave)
f0b6e2e8
RC		 3212 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3213 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3214
ba37a3d0
JB		 3215 if (priv->cfg->sku & IWL_SKU_N)
3216 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3217 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3218
8d9698b3 3219 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3220 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3221
d0fe478c
JB		 3222 for_each_context(priv, ctx) {
3223 hw->wiphy->interface_modes |= ctx->interface_modes;
3224 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3225 }
f0b6e2e8 3226
9b9190d9
JB		 3227 hw->wiphy->max_remain_on_channel_duration = 1000;
3228
f6c8f152 3229 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
274102a8
JB		 3230 WIPHY_FLAG_DISABLE_BEACON_HINTS |
3231 WIPHY_FLAG_IBSS_RSN;
f0b6e2e8
RC		 3232
3233 /*
3234 * For now, disable PS by default because it affects
3235 * RX performance significantly.
3236 */
5be83de5 3237 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3238
1382c71c 3239 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3240 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3241 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3242
3243 /* Default value; 4 EDCA QOS priorities */
3244 hw->queues = 4;
3245
3246 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3247
3248 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3249 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3250 &priv->bands[IEEE80211_BAND_2GHZ];
3251 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3252 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3253 &priv->bands[IEEE80211_BAND_5GHZ];
3254
5ed540ae
WYG		 3255 iwl_leds_init(priv);
3256
f0b6e2e8
RC		 3257 ret = ieee80211_register_hw(priv->hw);
3258 if (ret) {
3259 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3260 return ret;
3261 }
3262 priv->mac80211_registered = 1;
3263
3264 return 0;
3265}
3266
3267
2295c66b 3268int iwlagn_mac_start(struct ieee80211_hw *hw)
b481de9c 3269{
c79dd5b5 3270 struct iwl_priv *priv = hw->priv;
5a66926a 3271 int ret;
b481de9c 3272
e1623446 3273 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3274
3275 /* we should be verifying the device is ready to be opened */
3276 mutex_lock(&priv->mutex);
5b9f8cd3 3277 ret = __iwl_up(priv);
b481de9c 3278 mutex_unlock(&priv->mutex);
5a66926a 3279
e655b9f0 3280 if (ret)
6cd0b1cb 3281 return ret;
e655b9f0 3282
c1842d61
TW		 3283 if (iwl_is_rfkill(priv))
3284 goto out;
3285
e1623446 3286 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3287
fe9b6b72 3288 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3289 * mac80211 will not be run successfully. */
154b25ce
EG		 3290 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3291 test_bit(STATUS_READY, &priv->status),
3292 UCODE_READY_TIMEOUT);
3293 if (!ret) {
3294 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3295 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3296 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3297 return -ETIMEDOUT;
5a66926a 3298 }
fe9b6b72 3299 }
0a078ffa 3300
5ed540ae 3301 iwlagn_led_enable(priv);
e932a609 3302
c1842d61 3303out:
0a078ffa 3304 priv->is_open = 1;
e1623446 3305 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3306 return 0;
3307}
3308
2295c66b 3309void iwlagn_mac_stop(struct ieee80211_hw *hw)
b481de9c 3310{
c79dd5b5 3311 struct iwl_priv *priv = hw->priv;
b481de9c 3312
e1623446 3313 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3314
19cc1087 3315 if (!priv->is_open)
e655b9f0 3316 return;
e655b9f0 3317
b481de9c 3318 priv->is_open = 0;
5a66926a 3319
5b9f8cd3 3320 iwl_down(priv);
5a66926a
ZY		 3321
3322 flush_workqueue(priv->workqueue);
6cd0b1cb 3323
554d1d02
SG		 3324 /* User space software may expect getting rfkill changes
3325 * even if interface is down */
6cd0b1cb 3326 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
554d1d02 3327 iwl_enable_rfkill_int(priv);
948c171c 3328
e1623446 3329 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3330}
3331
2295c66b 3332int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3333{
c79dd5b5 3334 struct iwl_priv *priv = hw->priv;
b481de9c 3335
e1623446 3336 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3337
e1623446 3338 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3339 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3340
74bcdb33 3341 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3342 dev_kfree_skb_any(skb);
3343
e1623446 3344 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3345 return NETDEV_TX_OK;
b481de9c
ZY		 3346}
3347
2295c66b
JB		 3348void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3349 struct ieee80211_vif *vif,
3350 struct ieee80211_key_conf *keyconf,
3351 struct ieee80211_sta *sta,
3352 u32 iv32, u16 *phase1key)
ab885f8c 3353{
9f58671e 3354 struct iwl_priv *priv = hw->priv;
a194e324
JB		 3355 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3356
e1623446 3357 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3358
a194e324 3359 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
b3fbdcf4 3360 iv32, phase1key);
ab885f8c 3361
e1623446 3362 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3363}
3364
2295c66b
JB		 3365int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3366 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3367 struct ieee80211_key_conf *key)
b481de9c 3368{
c79dd5b5 3369 struct iwl_priv *priv = hw->priv;
a194e324 3370 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
c10afb6e 3371 struct iwl_rxon_context *ctx = vif_priv->ctx;
42986796
WT		 3372 int ret;
3373 u8 sta_id;
3374 bool is_default_wep_key = false;
b481de9c 3375
e1623446 3376 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3377
90e8e424 3378 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3379 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3380 return -EOPNOTSUPP;
3381 }
b481de9c 3382
274102a8
JB		 3383 /*
3384 * To support IBSS RSN, don't program group keys in IBSS, the
3385 * hardware will then not attempt to decrypt the frames.
3386 */
3387 if (vif->type == NL80211_IFTYPE_ADHOC &&
3388 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3389 return -EOPNOTSUPP;
3390
a194e324 3391 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
0af8bcae
JB		 3392 if (sta_id == IWL_INVALID_STATION)
3393 return -EINVAL;
b481de9c 3394
6974e363 3395 mutex_lock(&priv->mutex);
2a421b91 3396 iwl_scan_cancel_timeout(priv, 100);
6974e363 3397
a90178fa
JB		 3398 /*
3399 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3400 * so far, we are in legacy wep mode (group key only), otherwise we are
3401 * in 1X mode.
a90178fa
JB		 3402 * In legacy wep mode, we use another host command to the uCode.
3403 */
97359d12
JB		 3404 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3405 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 3406 !sta) {
6974e363 3407 if (cmd == SET_KEY)
c10afb6e 3408 is_default_wep_key = !ctx->key_mapping_keys;
6974e363 3409 else
ccc038ab
EG		 3410 is_default_wep_key =
3411 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3412 }
052c4b9f 3413
b481de9c 3414 switch (cmd) {
deb09c43 3415 case SET_KEY:
6974e363 3416 if (is_default_wep_key)
2995bafa 3417 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
deb09c43 3418 else
a194e324
JB		 3419 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3420 key, sta_id);
deb09c43 3421
e1623446 3422 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3423 break;
3424 case DISABLE_KEY:
6974e363 3425 if (is_default_wep_key)
c10afb6e 3426 ret = iwl_remove_default_wep_key(priv, ctx, key);
deb09c43 3427 else
c10afb6e 3428 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
deb09c43 3429
e1623446 3430 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3431 break;
3432 default:
deb09c43 3433 ret = -EINVAL;
b481de9c
ZY		 3434 }
3435
72e15d71 3436 mutex_unlock(&priv->mutex);
e1623446 3437 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3438
deb09c43 3439 return ret;
b481de9c
ZY		 3440}
3441
2295c66b
JB		 3442int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3443 struct ieee80211_vif *vif,
3444 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 3445 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3446 u8 buf_size)
d783b061
TW		 3447{
3448 struct iwl_priv *priv = hw->priv;
4620fefa 3449 int ret = -EINVAL;
7b090687 3450 struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
d783b061 3451
e1623446 3452 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3453 sta->addr, tid);
d783b061
TW		 3454
3455 if (!(priv->cfg->sku & IWL_SKU_N))
3456 return -EACCES;
3457
4620fefa
JB		 3458 mutex_lock(&priv->mutex);
3459
d783b061
TW		 3460 switch (action) {
3461 case IEEE80211_AMPDU_RX_START:
e1623446 3462 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3463 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3464 break;
d783b061 3465 case IEEE80211_AMPDU_RX_STOP:
e1623446 3466 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3467 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3468 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3469 ret = 0;
3470 break;
d783b061 3471 case IEEE80211_AMPDU_TX_START:
e1623446 3472 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3473 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3474 if (ret == 0) {
3475 priv->_agn.agg_tids_count++;
3476 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3477 priv->_agn.agg_tids_count);
3478 }
4620fefa 3479 break;
d783b061 3480 case IEEE80211_AMPDU_TX_STOP:
e1623446 3481 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3482 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3483 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3484 priv->_agn.agg_tids_count--;
3485 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3486 priv->_agn.agg_tids_count);
3487 }
5c2207c6 3488 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 3489 ret = 0;
7cb1b088
WYG		 3490 if (priv->cfg->ht_params &&
3491 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 3492 struct iwl_station_priv *sta_priv =
3493 (void *) sta->drv_priv;
3494 /*
3495 * switch off RTS/CTS if it was previously enabled
3496 */
3497
3498 sta_priv->lq_sta.lq.general_params.flags &=
3499 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3500 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3501 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
94597ab2 3502 }
4620fefa 3503 break;
f0527971 3504 case IEEE80211_AMPDU_TX_OPERATIONAL:
7b090687
JB		 3505 /*
3506 * If the limit is 0, then it wasn't initialised yet,
3507 * use the default. We can do that since we take the
3508 * minimum below, and we don't want to go above our
3509 * default due to hardware restrictions.
3510 */
3511 if (sta_priv->max_agg_bufsize == 0)
3512 sta_priv->max_agg_bufsize =
3513 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3514
3515 /*
3516 * Even though in theory the peer could have different
3517 * aggregation reorder buffer sizes for different sessions,
3518 * our ucode doesn't allow for that and has a global limit
3519 * for each station. Therefore, use the minimum of all the
3520 * aggregation sessions and our default value.
3521 */
3522 sta_priv->max_agg_bufsize =
3523 min(sta_priv->max_agg_bufsize, buf_size);
3524
7cb1b088
WYG		 3525 if (priv->cfg->ht_params &&
3526 priv->cfg->ht_params->use_rts_for_aggregation) {
cfecc6b4
WYG		 3527 /*
3528 * switch to RTS/CTS if it is the prefer protection
3529 * method for HT traffic
3530 */
94597ab2
JB		 3531
3532 sta_priv->lq_sta.lq.general_params.flags |=
3533 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
cfecc6b4 3534 }
7b090687
JB		 3535
3536 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3537 sta_priv->max_agg_bufsize;
3538
3539 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3540 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
cfecc6b4 3541 ret = 0;
d783b061
TW		 3542 break;
3543 }
4620fefa
JB		 3544 mutex_unlock(&priv->mutex);
3545
3546 return ret;
d783b061 3547}
9f58671e 3548
2295c66b
JB		 3549int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3550 struct ieee80211_vif *vif,
3551 struct ieee80211_sta *sta)
fe6b23dd
RC		 3552{
3553 struct iwl_priv *priv = hw->priv;
3554 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
a194e324 3555 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
eafdfbd3 3556 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3557 int ret;
3558 u8 sta_id;
3559
3560 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3561 sta->addr);
da5ae1cf
RC		 3562 mutex_lock(&priv->mutex);
3563 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3564 sta->addr);
3565 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3566
3567 atomic_set(&sta_priv->pending_frames, 0);
3568 if (vif->type == NL80211_IFTYPE_AP)
3569 sta_priv->client = true;
3570
a194e324 3571 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
238d781d 3572 is_ap, sta, &sta_id);
fe6b23dd
RC		 3573 if (ret) {
3574 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3575 sta->addr, ret);
3576 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3577 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3578 return ret;
3579 }
3580
fd1af15d
JB		 3581 sta_priv->common.sta_id = sta_id;
3582
fe6b23dd 3583 /* Initialize rate scaling */
91dd6c27 3584 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3585 sta->addr);
3586 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3587 mutex_unlock(&priv->mutex);
fe6b23dd 3588
fd1af15d 3589 return 0;
fe6b23dd
RC		 3590}
3591
2295c66b
JB		 3592void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3593 struct ieee80211_channel_switch *ch_switch)
79d07325
WYG		 3594{
3595 struct iwl_priv *priv = hw->priv;
3596 const struct iwl_channel_info *ch_info;
3597 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 3598 struct ieee80211_channel *channel = ch_switch->channel;
79d07325 3599 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
246ed355
JB		 3600 /*
3601 * MULTI-FIXME
3602 * When we add support for multiple interfaces, we need to
3603 * revisit this. The channel switch command in the device
3604 * only affects the BSS context, but what does that really
3605 * mean? And what if we get a CSA on the second interface?
3606 * This needs a lot of work.
3607 */
3608 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
79d07325
WYG		 3609 u16 ch;
3610 unsigned long flags = 0;
3611
3612 IWL_DEBUG_MAC80211(priv, "enter\n");
3613
3614 if (iwl_is_rfkill(priv))
3615 goto out_exit;
3616
3617 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3618 test_bit(STATUS_SCANNING, &priv->status))
3619 goto out_exit;
3620
246ed355 3621 if (!iwl_is_associated_ctx(ctx))
79d07325
WYG		 3622 goto out_exit;
3623
3624 /* channel switch in progress */
3625 if (priv->switch_rxon.switch_in_progress == true)
3626 goto out_exit;
3627
3628 mutex_lock(&priv->mutex);
3629 if (priv->cfg->ops->lib->set_channel_switch) {
3630
aa2dc6b5 3631 ch = channel->hw_value;
246ed355 3632 if (le16_to_cpu(ctx->active.channel) != ch) {
79d07325 3633 ch_info = iwl_get_channel_info(priv,
aa2dc6b5 3634 channel->band,
79d07325
WYG		 3635 ch);
3636 if (!is_channel_valid(ch_info)) {
3637 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3638 goto out;
3639 }
3640 spin_lock_irqsave(&priv->lock, flags);
3641
3642 priv->current_ht_config.smps = conf->smps_mode;
3643
3644 /* Configure HT40 channels */
7e6a5886
JB		 3645 ctx->ht.enabled = conf_is_ht(conf);
3646 if (ctx->ht.enabled) {
79d07325 3647 if (conf_is_ht40_minus(conf)) {
7e6a5886 3648 ctx->ht.extension_chan_offset =
79d07325 3649 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
7e6a5886 3650 ctx->ht.is_40mhz = true;
79d07325 3651 } else if (conf_is_ht40_plus(conf)) {
7e6a5886 3652 ctx->ht.extension_chan_offset =
79d07325 3653 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
7e6a5886 3654 ctx->ht.is_40mhz = true;
79d07325 3655 } else {
7e6a5886 3656 ctx->ht.extension_chan_offset =
79d07325 3657 IEEE80211_HT_PARAM_CHA_SEC_NONE;
7e6a5886 3658 ctx->ht.is_40mhz = false;
79d07325
WYG		 3659 }
3660 } else
7e6a5886 3661 ctx->ht.is_40mhz = false;
79d07325 3662
246ed355
JB		 3663 if ((le16_to_cpu(ctx->staging.channel) != ch))
3664 ctx->staging.flags = 0;
79d07325 3665
246ed355 3666 iwl_set_rxon_channel(priv, channel, ctx);
79d07325 3667 iwl_set_rxon_ht(priv, ht_conf);
246ed355 3668 iwl_set_flags_for_band(priv, ctx, channel->band,
8bd413e6 3669 ctx->vif);
79d07325
WYG		 3670 spin_unlock_irqrestore(&priv->lock, flags);
3671
3672 iwl_set_rate(priv);
3673 /*
3674 * at this point, staging_rxon has the
3675 * configuration for channel switch
3676 */
3677 if (priv->cfg->ops->lib->set_channel_switch(priv,
3678 ch_switch))
3679 priv->switch_rxon.switch_in_progress = false;
3680 }
3681 }
3682out:
3683 mutex_unlock(&priv->mutex);
3684out_exit:
3685 if (!priv->switch_rxon.switch_in_progress)
8bd413e6 3686 ieee80211_chswitch_done(ctx->vif, false);
79d07325
WYG		 3687 IWL_DEBUG_MAC80211(priv, "leave\n");
3688}
3689
2295c66b
JB		 3690void iwlagn_configure_filter(struct ieee80211_hw *hw,
3691 unsigned int changed_flags,
3692 unsigned int *total_flags,
3693 u64 multicast)
8b8ab9d5
JB		 3694{
3695 struct iwl_priv *priv = hw->priv;
3696 __le32 filter_or = 0, filter_nand = 0;
246ed355 3697 struct iwl_rxon_context *ctx;
8b8ab9d5
JB		 3698
3699#define CHK(test, flag) do { \
3700 if (*total_flags & (test)) \
3701 filter_or |= (flag); \
3702 else \
3703 filter_nand |= (flag); \
3704 } while (0)
3705
3706 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3707 changed_flags, *total_flags);
3708
3709 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
bdb84fec
JB		 3710 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3711 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
8b8ab9d5
JB		 3712 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3713
3714#undef CHK
3715
3716 mutex_lock(&priv->mutex);
3717
246ed355
JB		 3718 for_each_context(priv, ctx) {
3719 ctx->staging.filter_flags &= ~filter_nand;
3720 ctx->staging.filter_flags |= filter_or;
749ff4ef
SG		 3721
3722 /*
3723 * Not committing directly because hardware can perform a scan,
3724 * but we'll eventually commit the filter flags change anyway.
3725 */
246ed355 3726 }
8b8ab9d5
JB		 3727
3728 mutex_unlock(&priv->mutex);
3729
3730 /*
3731 * Receiving all multicast frames is always enabled by the
3732 * default flags setup in iwl_connection_init_rx_config()
3733 * since we currently do not support programming multicast
3734 * filters into the device.
3735 */
3736 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3737 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3738}
3739
2295c66b 3740void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
716c74b0
WYG		 3741{
3742 struct iwl_priv *priv = hw->priv;
3743
3744 mutex_lock(&priv->mutex);
3745 IWL_DEBUG_MAC80211(priv, "enter\n");
3746
3747 /* do not support "flush" */
3748 if (!priv->cfg->ops->lib->txfifo_flush)
3749 goto done;
3750
3751 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3752 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3753 goto done;
3754 }
3755 if (iwl_is_rfkill(priv)) {
3756 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3757 goto done;
3758 }
3759
3760 /*
3761 * mac80211 will not push any more frames for transmit
3762 * until the flush is completed
3763 */
3764 if (drop) {
3765 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3766 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3767 IWL_ERR(priv, "flush request fail\n");
3768 goto done;
3769 }
3770 }
3771 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3772 iwlagn_wait_tx_queue_empty(priv);
3773done:
3774 mutex_unlock(&priv->mutex);
3775 IWL_DEBUG_MAC80211(priv, "leave\n");
3776}
3777
9b9190d9
JB		 3778static void iwlagn_disable_roc(struct iwl_priv *priv)
3779{
3780 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3781 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3782
3783 lockdep_assert_held(&priv->mutex);
3784
3785 if (!ctx->is_active)
3786 return;
3787
3788 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3789 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3790 iwl_set_rxon_channel(priv, chan, ctx);
3791 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3792
3793 priv->_agn.hw_roc_channel = NULL;
3794
80b38fff 3795 iwlcore_commit_rxon(priv, ctx);
9b9190d9
JB		 3796
3797 ctx->is_active = false;
3798}
3799
3800static void iwlagn_bg_roc_done(struct work_struct *work)
3801{
3802 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3803 _agn.hw_roc_work.work);
3804
3805 mutex_lock(&priv->mutex);
3806 ieee80211_remain_on_channel_expired(priv->hw);
3807 iwlagn_disable_roc(priv);
3808 mutex_unlock(&priv->mutex);
3809}
3810
80b38fff 3811#ifdef CONFIG_IWL5000
9b9190d9
JB		 3812static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3813 struct ieee80211_channel *channel,
3814 enum nl80211_channel_type channel_type,
3815 int duration)
3816{
3817 struct iwl_priv *priv = hw->priv;
3818 int err = 0;
3819
3820 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3821 return -EOPNOTSUPP;
3822
3823 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3824 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3825 return -EOPNOTSUPP;
3826
3827 mutex_lock(&priv->mutex);
3828
3829 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3830 test_bit(STATUS_SCAN_HW, &priv->status)) {
3831 err = -EBUSY;
3832 goto out;
3833 }
3834
3835 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3836 priv->_agn.hw_roc_channel = channel;
3837 priv->_agn.hw_roc_chantype = channel_type;
3838 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
80b38fff 3839 iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
9b9190d9
JB		 3840 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3841 msecs_to_jiffies(duration + 20));
3842
94073919 3843 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
9b9190d9
JB		 3844 ieee80211_ready_on_channel(priv->hw);
3845
3846 out:
3847 mutex_unlock(&priv->mutex);
3848
3849 return err;
3850}
3851
3852static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3853{
3854 struct iwl_priv *priv = hw->priv;
3855
3856 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3857 return -EOPNOTSUPP;
3858
3859 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3860
3861 mutex_lock(&priv->mutex);
3862 iwlagn_disable_roc(priv);
3863 mutex_unlock(&priv->mutex);
3864
3865 return 0;
3866}
80b38fff 3867#endif
9b9190d9 3868
b481de9c
ZY		 3869/*****************************************************************************
3870 *
3871 * driver setup and teardown
3872 *
3873 *****************************************************************************/
3874
4e39317d 3875static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3876{
d21050c7 3877 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 3878
3879 init_waitqueue_head(&priv->wait_command_queue);
3880
5b9f8cd3
EG		 3881 INIT_WORK(&priv->restart, iwl_bg_restart);
3882 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3883 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3884 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 3885 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 3886 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 3887 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4a4a9e81
TW		 3888 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3889 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
9b9190d9 3890 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
2a421b91 3891
2a421b91 3892 iwl_setup_scan_deferred_work(priv);
bb8c093b 3893
4e39317d
EG		 3894 if (priv->cfg->ops->lib->setup_deferred_work)
3895 priv->cfg->ops->lib->setup_deferred_work(priv);
3896
3897 init_timer(&priv->statistics_periodic);
3898 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3899 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3900
a9e1cb6a
WYG		 3901 init_timer(&priv->ucode_trace);
3902 priv->ucode_trace.data = (unsigned long)priv;
3903 priv->ucode_trace.function = iwl_bg_ucode_trace;
3904
22de94de
SG		 3905 init_timer(&priv->watchdog);
3906 priv->watchdog.data = (unsigned long)priv;
3907 priv->watchdog.function = iwl_bg_watchdog;
b74e31a9 3908
7cb1b088 3909 if (!priv->cfg->base_params->use_isr_legacy)
ef850d7c
MA		 3910 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3911 iwl_irq_tasklet, (unsigned long)priv);
3912 else
3913 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3914 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 3915}
3916
4e39317d 3917static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3918{
4e39317d
EG		 3919 if (priv->cfg->ops->lib->cancel_deferred_work)
3920 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3921
3ae6a054 3922 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 3923 cancel_delayed_work(&priv->alive_start);
815e629b 3924 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 3925 cancel_work_sync(&priv->beacon_update);
e7e16b90
SG		 3926
3927 iwl_cancel_scan_deferred_work(priv);
3928
bee008b7 3929 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 3930 cancel_work_sync(&priv->bt_runtime_config);
e7e16b90 3931
4e39317d 3932 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3933 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY		 3934}
3935
89f186a8
RC		 3936static void iwl_init_hw_rates(struct iwl_priv *priv,
3937 struct ieee80211_rate *rates)
3938{
3939 int i;
3940
3941 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3942 rates[i].bitrate = iwl_rates[i].ieee * 5;
3943 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3944 rates[i].hw_value_short = i;
3945 rates[i].flags = 0;
3946 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3947 /*
3948 * If CCK != 1M then set short preamble rate flag.
3949 */
3950 rates[i].flags |=
3951 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3952 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3953 }
3954 }
3955}
3956
3957static int iwl_init_drv(struct iwl_priv *priv)
3958{
3959 int ret;
3960
89f186a8
RC		 3961 spin_lock_init(&priv->sta_lock);
3962 spin_lock_init(&priv->hcmd_lock);
3963
3964 INIT_LIST_HEAD(&priv->free_frames);
3965
3966 mutex_init(&priv->mutex);
d2dfe6df 3967 mutex_init(&priv->sync_cmd_mutex);
89f186a8 3968
89f186a8
RC		 3969 priv->ieee_channels = NULL;
3970 priv->ieee_rates = NULL;
3971 priv->band = IEEE80211_BAND_2GHZ;
3972
3973 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3974 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3975 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3976 priv->_agn.agg_tids_count = 0;
89f186a8 3977
8a472da4
WYG		 3978 /* initialize force reset */
3979 priv->force_reset[IWL_RF_RESET].reset_duration =
3980 IWL_DELAY_NEXT_FORCE_RF_RESET;
3981 priv->force_reset[IWL_FW_RESET].reset_duration =
3982 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 3983
3984 /* Choose which receivers/antennas to use */
3985 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355
JB		 3986 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3987 &priv->contexts[IWL_RXON_CTX_BSS]);
89f186a8
RC		 3988
3989 iwl_init_scan_params(priv);
3990
22bf59a0 3991 /* init bt coex */
7cb1b088
WYG		 3992 if (priv->cfg->bt_params &&
3993 priv->cfg->bt_params->advanced_bt_coexist) {
b6e116e8
WYG		 3994 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3995 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3996 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG		 3997 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3998 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3999 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
22bf59a0
WYG		 4000 }
4001
89f186a8
RC		 4002 /* Set the tx_power_user_lmt to the lowest power level
4003 * this value will get overwritten by channel max power avg
4004 * from eeprom */
b744cb79 4005 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
a25a66ac 4006 priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 4007
4008 ret = iwl_init_channel_map(priv);
4009 if (ret) {
4010 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4011 goto err;
4012 }
4013
4014 ret = iwlcore_init_geos(priv);
4015 if (ret) {
4016 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4017 goto err_free_channel_map;
4018 }
4019 iwl_init_hw_rates(priv, priv->ieee_rates);
4020
4021 return 0;
4022
4023err_free_channel_map:
4024 iwl_free_channel_map(priv);
4025err:
4026 return ret;
4027}
4028
4029static void iwl_uninit_drv(struct iwl_priv *priv)
4030{
4031 iwl_calib_free_results(priv);
4032 iwlcore_free_geos(priv);
4033 iwl_free_channel_map(priv);
811ecc99 4034 kfree(priv->scan_cmd);
89f186a8
RC		 4035}
4036
ae79d23d 4037#ifdef CONFIG_IWL5000
dc21b545 4038struct ieee80211_ops iwlagn_hw_ops = {
2295c66b
JB		 4039 .tx = iwlagn_mac_tx,
4040 .start = iwlagn_mac_start,
4041 .stop = iwlagn_mac_stop,
5b9f8cd3
EG		 4042 .add_interface = iwl_mac_add_interface,
4043 .remove_interface = iwl_mac_remove_interface,
d4daaea6 4044 .change_interface = iwl_mac_change_interface,
2295c66b 4045 .config = iwlagn_mac_config,
8b8ab9d5 4046 .configure_filter = iwlagn_configure_filter,
2295c66b
JB		 4047 .set_key = iwlagn_mac_set_key,
4048 .update_tkip_key = iwlagn_mac_update_tkip_key,
5b9f8cd3 4049 .conf_tx = iwl_mac_conf_tx,
2295c66b
JB		 4050 .bss_info_changed = iwlagn_bss_info_changed,
4051 .ampdu_action = iwlagn_mac_ampdu_action,
6ab10ff8 4052 .hw_scan = iwl_mac_hw_scan,
2295c66b 4053 .sta_notify = iwlagn_mac_sta_notify,
fe6b23dd
RC		 4054 .sta_add = iwlagn_mac_sta_add,
4055 .sta_remove = iwl_mac_sta_remove,
2295c66b
JB		 4056 .channel_switch = iwlagn_mac_channel_switch,
4057 .flush = iwlagn_mac_flush,
a85d7cca 4058 .tx_last_beacon = iwl_mac_tx_last_beacon,
9b9190d9
JB		 4059 .remain_on_channel = iwl_mac_remain_on_channel,
4060 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
b481de9c 4061};
ae79d23d 4062#endif
b481de9c 4063
3867fe04
WYG		 4064static void iwl_hw_detect(struct iwl_priv *priv)
4065{
4066 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4067 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4068 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
49ded76b 4069 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3867fe04
WYG		 4070}
4071
07d4f1ad
WYG		 4072static int iwl_set_hw_params(struct iwl_priv *priv)
4073{
4074 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4075 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4076 if (priv->cfg->mod_params->amsdu_size_8K)
4077 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4078 else
4079 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4080
4081 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4082
4083 if (priv->cfg->mod_params->disable_11n)
4084 priv->cfg->sku &= ~IWL_SKU_N;
4085
4086 /* Device-specific setup */
4087 return priv->cfg->ops->lib->set_hw_params(priv);
4088}
4089
e72f368b
JB		 4090static const u8 iwlagn_bss_ac_to_fifo[] = {
4091 IWL_TX_FIFO_VO,
4092 IWL_TX_FIFO_VI,
4093 IWL_TX_FIFO_BE,
4094 IWL_TX_FIFO_BK,
4095};
4096
4097static const u8 iwlagn_bss_ac_to_queue[] = {
4098 0, 1, 2, 3,
4099};
4100
4101static const u8 iwlagn_pan_ac_to_fifo[] = {
4102 IWL_TX_FIFO_VO_IPAN,
4103 IWL_TX_FIFO_VI_IPAN,
4104 IWL_TX_FIFO_BE_IPAN,
4105 IWL_TX_FIFO_BK_IPAN,
4106};
4107
4108static const u8 iwlagn_pan_ac_to_queue[] = {
4109 7, 6, 5, 4,
4110};
4111
5b9f8cd3 4112static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c 4113{
246ed355 4114 int err = 0, i;
c79dd5b5 4115 struct iwl_priv *priv;
b481de9c 4116 struct ieee80211_hw *hw;
82b9a121 4117 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 4118 unsigned long flags;
c6fa17ed 4119 u16 pci_cmd, num_mac;
b481de9c 4120
316c30d9
AK		 4121 /************************
4122 * 1. Allocating HW data
4123 ************************/
4124
6440adb5
CB		 4125 /* Disabling hardware scan means that mac80211 will perform scans
4126 * "the hard way", rather than using device's scan. */
1ea87396 4127 if (cfg->mod_params->disable_hw_scan) {
72645eff
WYG		 4128 dev_printk(KERN_DEBUG, &(pdev->dev),
4129 "sw scan support is deprecated\n");
ae79d23d 4130#ifdef CONFIG_IWL5000
dc21b545 4131 iwlagn_hw_ops.hw_scan = NULL;
ae79d23d 4132#endif
2295c66b
JB		 4133#ifdef CONFIG_IWL4965
4134 iwl4965_hw_ops.hw_scan = NULL;
4135#endif
b481de9c
ZY		 4136 }
4137
dc21b545 4138 hw = iwl_alloc_all(cfg);
1d0a082d 4139 if (!hw) {
b481de9c
ZY		 4140 err = -ENOMEM;
4141 goto out;
4142 }
1d0a082d
AK		 4143 priv = hw->priv;
4144 /* At this point both hw and priv are allocated. */
4145
246ed355
JB		 4146 /*
4147 * The default context is always valid,
4148 * more may be discovered when firmware
4149 * is loaded.
4150 */
4151 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4152
4153 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4154 priv->contexts[i].ctxid = i;
4155
763cc3bf
JB		 4156 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4157 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
8f2d3d2a
JB		 4158 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4159 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4160 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 4161 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 4162 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
c10afb6e 4163 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
e72f368b
JB		 4164 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4165 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
d0fe478c
JB		 4166 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4167 BIT(NL80211_IFTYPE_ADHOC);
4168 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4169 BIT(NL80211_IFTYPE_STATION);
2295c66b 4170 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
d0fe478c
JB		 4171 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4172 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4173 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
ece9c4ee
JB		 4174
4175 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4176 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4177 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4178 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4179 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4180 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4181 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4182 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
e72f368b
JB		 4183 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4184 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4185 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
d0fe478c
JB		 4186 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4187 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
f35c0c56
WYG		 4188#ifdef CONFIG_IWL_P2P
4189 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
4190 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
4191#endif
d0fe478c
JB		 4192 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4193 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4194 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
ece9c4ee
JB		 4195
4196 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
8f2d3d2a 4197
b481de9c
ZY		 4198 SET_IEEE80211_DEV(hw, &pdev->dev);
4199
e1623446 4200 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 4201 priv->cfg = cfg;
b481de9c 4202 priv->pci_dev = pdev;
40cefda9 4203 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 4204
bee008b7
WYG		 4205 /* is antenna coupling more than 35dB ? */
4206 priv->bt_ant_couple_ok =
4207 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4208 true : false;
4209
9f28ebc3 4210 /* enable/disable bt channel inhibition */
f37837c9 4211 priv->bt_ch_announce = iwlagn_bt_ch_announce;
9f28ebc3
WYG		 4212 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4213 (priv->bt_ch_announce) ? "On" : "Off");
f37837c9 4214
20594eb0
WYG		 4215 if (iwl_alloc_traffic_mem(priv))
4216 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4217
316c30d9
AK		 4218 /**************************
4219 * 2. Initializing PCI bus
4220 **************************/
1a7123cd
JL		 4221 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4222 PCIE_LINK_STATE_CLKPM);
4223
316c30d9
AK		 4224 if (pci_enable_device(pdev)) {
4225 err = -ENODEV;
4226 goto out_ieee80211_free_hw;
4227 }
4228
4229 pci_set_master(pdev);
4230
093d874c 4231 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 4232 if (!err)
093d874c 4233 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 4234 if (err) {
093d874c 4235 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4236 if (!err)
093d874c 4237 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4238 /* both attempts failed: */
316c30d9 4239 if (err) {
978785a3 4240 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 4241 goto out_pci_disable_device;
cc2a8ea8 4242 }
316c30d9
AK		 4243 }
4244
4245 err = pci_request_regions(pdev, DRV_NAME);
4246 if (err)
4247 goto out_pci_disable_device;
4248
4249 pci_set_drvdata(pdev, priv);
4250
316c30d9
AK		 4251
4252 /***********************
4253 * 3. Read REV register
4254 ***********************/
4255 priv->hw_base = pci_iomap(pdev, 0, 0);
4256 if (!priv->hw_base) {
4257 err = -ENODEV;
4258 goto out_pci_release_regions;
4259 }
4260
e1623446 4261 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 4262 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4263 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 4264
731a29b7 4265 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 4266 * we should init now
4267 */
4268 spin_lock_init(&priv->reg_lock);
731a29b7 4269 spin_lock_init(&priv->lock);
4843b5a7
RC		 4270
4271 /*
4272 * stop and reset the on-board processor just in case it is in a
4273 * strange state ... like being left stranded by a primary kernel
4274 * and this is now the kdump kernel trying to start up
4275 */
4276 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4277
b661c819 4278 iwl_hw_detect(priv);
c11362c0 4279 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 4280 priv->cfg->name, priv->hw_rev);
316c30d9 4281
e7b63581
TW		 4282 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4283 * PCI Tx retries from interfering with C3 CPU state */
4284 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4285
086ed117
MA		 4286 iwl_prepare_card_hw(priv);
4287 if (!priv->hw_ready) {
4288 IWL_WARN(priv, "Failed, HW not ready\n");
4289 goto out_iounmap;
4290 }
4291
91238714
TW		 4292 /*****************
4293 * 4. Read EEPROM
4294 *****************/
316c30d9
AK		 4295 /* Read the EEPROM */
4296 err = iwl_eeprom_init(priv);
4297 if (err) {
15b1687c 4298 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4299 goto out_iounmap;
4300 }
8614f360
TW		 4301 err = iwl_eeprom_check_version(priv);
4302 if (err)
c8f16138 4303 goto out_free_eeprom;
8614f360 4304
21a5b3c6
WYG		 4305 err = iwl_eeprom_check_sku(priv);
4306 if (err)
4307 goto out_free_eeprom;
4308
02883017 4309 /* extract MAC Address */
c6fa17ed
WYG		 4310 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4311 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4312 priv->hw->wiphy->addresses = priv->addresses;
4313 priv->hw->wiphy->n_addresses = 1;
4314 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4315 if (num_mac > 1) {
4316 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4317 ETH_ALEN);
4318 priv->addresses[1].addr[5]++;
4319 priv->hw->wiphy->n_addresses++;
4320 }
316c30d9
AK		 4321
4322 /************************
4323 * 5. Setup HW constants
4324 ************************/
da154e30 4325 if (iwl_set_hw_params(priv)) {
15b1687c 4326 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4327 goto out_free_eeprom;
316c30d9
AK		 4328 }
4329
4330 /*******************
6ba87956 4331 * 6. Setup priv
316c30d9 4332 *******************/
b481de9c 4333
6ba87956 4334 err = iwl_init_drv(priv);
bf85ea4f 4335 if (err)
399f4900 4336 goto out_free_eeprom;
bf85ea4f 4337 /* At this point both hw and priv are initialized. */
316c30d9 4338
316c30d9 4339 /********************
09f9bf79 4340 * 7. Setup services
316c30d9 4341 ********************/
0359facc 4342 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4343 iwl_disable_interrupts(priv);
0359facc 4344 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4345
6cd0b1cb
HS		 4346 pci_enable_msi(priv->pci_dev);
4347
e39fdee1
WYG		 4348 if (priv->cfg->ops->lib->isr_ops.alloc)
4349 priv->cfg->ops->lib->isr_ops.alloc(priv);
4350
4351 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
ef850d7c 4352 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4353 if (err) {
4354 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4355 goto out_disable_msi;
4356 }
316c30d9 4357
4e39317d 4358 iwl_setup_deferred_work(priv);
653fa4a0 4359 iwl_setup_rx_handlers(priv);
316c30d9 4360
158bea07
JB		 4361 /*********************************************
4362 * 8. Enable interrupts and read RFKILL state
4363 *********************************************/
6ba87956 4364
554d1d02 4365 /* enable rfkill interrupt: hw bug w/a */
6cd0b1cb
HS		 4366 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4367 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4368 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4369 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4370 }
4371
554d1d02 4372 iwl_enable_rfkill_int(priv);
6cd0b1cb 4373
6cd0b1cb
HS		 4374 /* If platform's RF_KILL switch is NOT set to KILL */
4375 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4376 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4377 else
4378 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4379
a60e77e5
JB		 4380 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4381 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4382
58d0f361 4383 iwl_power_initialize(priv);
39b73fb1 4384 iwl_tt_initialize(priv);
158bea07 4385
a15707d8 4386 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4387
b08dfd04 4388 err = iwl_request_firmware(priv, true);
158bea07 4389 if (err)
7d47618a 4390 goto out_destroy_workqueue;
158bea07 4391
b481de9c
ZY		 4392 return 0;
4393
7d47618a 4394 out_destroy_workqueue:
c8f16138
RC		 4395 destroy_workqueue(priv->workqueue);
4396 priv->workqueue = NULL;
795cc0ad 4397 free_irq(priv->pci_dev->irq, priv);
e39fdee1
WYG		 4398 if (priv->cfg->ops->lib->isr_ops.free)
4399 priv->cfg->ops->lib->isr_ops.free(priv);
6cd0b1cb
HS		 4400 out_disable_msi:
4401 pci_disable_msi(priv->pci_dev);
6ba87956 4402 iwl_uninit_drv(priv);
073d3f5f
TW		 4403 out_free_eeprom:
4404 iwl_eeprom_free(priv);
b481de9c
ZY		 4405 out_iounmap:
4406 pci_iounmap(pdev, priv->hw_base);
4407 out_pci_release_regions:
316c30d9 4408 pci_set_drvdata(pdev, NULL);
623d563e 4409 pci_release_regions(pdev);
b481de9c
ZY		 4410 out_pci_disable_device:
4411 pci_disable_device(pdev);
b481de9c 4412 out_ieee80211_free_hw:
20594eb0 4413 iwl_free_traffic_mem(priv);
d7c76f4c 4414 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4415 out:
4416 return err;
4417}
4418
5b9f8cd3 4419static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4420{
c79dd5b5 4421 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4422 unsigned long flags;
b481de9c
ZY		 4423
4424 if (!priv)
4425 return;
4426
a15707d8 4427 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4428
e1623446 4429 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4430
67249625 4431 iwl_dbgfs_unregister(priv);
5b9f8cd3 4432 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4433
5b9f8cd3
EG		 4434 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4435 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4436 * we need to set STATUS_EXIT_PENDING bit.
4437 */
4438 set_bit(STATUS_EXIT_PENDING, &priv->status);
5ed540ae
WYG		 4439
4440 iwl_leds_exit(priv);
4441
c4f55232
RR		 4442 if (priv->mac80211_registered) {
4443 ieee80211_unregister_hw(priv->hw);
4444 priv->mac80211_registered = 0;
0b124c31 4445 } else {
5b9f8cd3 4446 iwl_down(priv);
c4f55232
RR		 4447 }
4448
c166b25a
BC		 4449 /*
4450 * Make sure device is reset to low power before unloading driver.
4451 * This may be redundant with iwl_down(), but there are paths to
4452 * run iwl_down() without calling apm_ops.stop(), and there are
4453 * paths to avoid running iwl_down() at all before leaving driver.
4454 * This (inexpensive) call *makes sure* device is reset.
4455 */
14e8e4af 4456 iwl_apm_stop(priv);
c166b25a 4457
39b73fb1
WYG		 4458 iwl_tt_exit(priv);
4459
0359facc
MA		 4460 /* make sure we flush any pending irq or
4461 * tasklet for the driver
4462 */
4463 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4464 iwl_disable_interrupts(priv);
0359facc
MA		 4465 spin_unlock_irqrestore(&priv->lock, flags);
4466
4467 iwl_synchronize_irq(priv);
4468
5b9f8cd3 4469 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4470
4471 if (priv->rxq.bd)
54b81550 4472 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4473 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4474
073d3f5f 4475 iwl_eeprom_free(priv);
b481de9c 4476
b481de9c 4477
948c171c
MA		 4478 /*netif_stop_queue(dev); */
4479 flush_workqueue(priv->workqueue);
4480
5b9f8cd3 4481 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4482 * priv->workqueue... so we can't take down the workqueue
4483 * until now... */
4484 destroy_workqueue(priv->workqueue);
4485 priv->workqueue = NULL;
20594eb0 4486 iwl_free_traffic_mem(priv);
b481de9c 4487
6cd0b1cb
HS		 4488 free_irq(priv->pci_dev->irq, priv);
4489 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4490 pci_iounmap(pdev, priv->hw_base);
4491 pci_release_regions(pdev);
4492 pci_disable_device(pdev);
4493 pci_set_drvdata(pdev, NULL);
4494
6ba87956 4495 iwl_uninit_drv(priv);
b481de9c 4496
e39fdee1
WYG		 4497 if (priv->cfg->ops->lib->isr_ops.free)
4498 priv->cfg->ops->lib->isr_ops.free(priv);
ef850d7c 4499
77834543 4500 dev_kfree_skb(priv->beacon_skb);
b481de9c
ZY		 4501
4502 ieee80211_free_hw(priv->hw);
4503}
4504
b481de9c
ZY		 4505
4506/*****************************************************************************
4507 *
4508 * driver and module entry point
4509 *
4510 *****************************************************************************/
4511
fed9017e 4512/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4513static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4514#ifdef CONFIG_IWL4965
fed9017e
RR		 4515 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4516 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4517#endif /* CONFIG_IWL4965 */
5a6a256e 4518#ifdef CONFIG_IWL5000
ac592574
WYG		 4519/* 5100 Series WiFi */
4520 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4521 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4522 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4523 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4524 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4525 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4526 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4527 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4528 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4529 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4530 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4531 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4532 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4533 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4534 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4535 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4536 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4537 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4538 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4539 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4540 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4541 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4542 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4543 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4544
4545/* 5300 Series WiFi */
4546 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4547 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4548 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4549 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4550 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4551 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4552 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4553 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4554 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4555 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4556 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4557 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4558
4559/* 5350 Series WiFi/WiMax */
4560 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4561 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4562 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4563
4564/* 5150 Series Wifi/WiMax */
4565 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4566 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4567 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4568 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4569 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4570 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4571
4572 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4573 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4574 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4575 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4576
4577/* 6x00 Series */
5953a62e
WYG		 4578 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4579 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4580 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4581 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4582 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4583 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4584 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4585 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4586 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4587 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4588
003ea981 4589/* 6x05 Series */
8b3ee296
WYG		 4590 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4591 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4592 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4593 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4594 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4595 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4596 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
1808972f 4597
003ea981 4598/* 6x30 Series */
8b3ee296
WYG		 4599 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4600 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4601 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4602 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4603 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4604 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4605 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4606 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4607 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4608 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4609 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4610 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4611 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4612 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4613 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4614 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
5953a62e
WYG		 4615
4616/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4617 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4618 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4619 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4620 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4621 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4622 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4623
003ea981 4624/* 6150 WiFi/WiMax Series */
8b3ee296
WYG		 4625 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4626 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4627 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4628 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4629 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4630 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
03264339 4631
77dcb6a9 4632/* 1000 Series WiFi */
4bd0914f
WYG		 4633 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4634 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4635 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4636 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4637 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4638 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4639 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4640 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4641 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4642 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4643 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4644 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
1de19ecc 4645
58a39090 4646/* 100 Series WiFi */
1de19ecc 4647 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
2a21ff44 4648 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
1de19ecc 4649 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
2a21ff44 4650 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
1de19ecc 4651 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
2a21ff44 4652 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
58a39090
WYG		 4653
4654/* 130 Series WiFi */
4655 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4656 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4657 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4658 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4659 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4660 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4661
04b8e751
WYG		 4662/* 2x00 Series */
4663 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4664 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4665 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4666 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4667 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4668 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4669
4670/* 2x30 Series */
4671 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4672 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4673 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4674 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4675 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4676 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4677
4678/* 6x35 Series */
4679 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4680 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4681 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4682 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4683 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4684 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4685 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4686 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4687 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4688
4689/* 200 Series */
4690 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4691 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4692 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4693 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4694 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4695 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4696
4697/* 230 Series */
4698 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4699 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4700 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4701 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4702 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4703 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4704
5a6a256e 4705#endif /* CONFIG_IWL5000 */
7100e924 4706
fed9017e
RR		 4707 {0}
4708};
4709MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4710
4711static struct pci_driver iwl_driver = {
b481de9c 4712 .name = DRV_NAME,
fed9017e 4713 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4714 .probe = iwl_pci_probe,
4715 .remove = __devexit_p(iwl_pci_remove),
f60dc013 4716 .driver.pm = IWL_PM_OPS,
b481de9c
ZY		 4717};
4718
5b9f8cd3 4719static int __init iwl_init(void)
b481de9c
ZY		 4720{
4721
4722 int ret;
c96c31e4
JP		 4723 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4724 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4725
e227ceac 4726 ret = iwlagn_rate_control_register();
897e1cf2 4727 if (ret) {
c96c31e4 4728 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4729 return ret;
4730 }
4731
fed9017e 4732 ret = pci_register_driver(&iwl_driver);
b481de9c 4733 if (ret) {
c96c31e4 4734 pr_err("Unable to initialize PCI module\n");
897e1cf2 4735 goto error_register;
b481de9c 4736 }
b481de9c
ZY		 4737
4738 return ret;
897e1cf2 4739
897e1cf2 4740error_register:
e227ceac 4741 iwlagn_rate_control_unregister();
897e1cf2 4742 return ret;
b481de9c
ZY		 4743}
4744
5b9f8cd3 4745static void __exit iwl_exit(void)
b481de9c 4746{
fed9017e 4747 pci_unregister_driver(&iwl_driver);
e227ceac 4748 iwlagn_rate_control_unregister();
b481de9c
ZY		 4749}
4750
5b9f8cd3
EG		 4751module_exit(iwl_exit);
4752module_init(iwl_init);
a562a9dd
RC		 4753
4754#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4755module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4756MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4757module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4758MODULE_PARM_DESC(debug, "debug output mask");
4759#endif
4760
2b068618
WYG		 4761module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4762MODULE_PARM_DESC(swcrypto50,
4763 "using crypto in software (default 0 [hardware]) (deprecated)");
4764module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4765MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4766module_param_named(queues_num50,
4767 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4768MODULE_PARM_DESC(queues_num50,
4769 "number of hw queues in 50xx series (deprecated)");
4770module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4771MODULE_PARM_DESC(queues_num, "number of hw queues.");
4772module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4773MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4774module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4775MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4776module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4777 int, S_IRUGO);
4778MODULE_PARM_DESC(amsdu_size_8K50,
4779 "enable 8K amsdu size in 50XX series (deprecated)");
4780module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4781 int, S_IRUGO);
4782MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4783module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4784MODULE_PARM_DESC(fw_restart50,
4785 "restart firmware in case of error (deprecated)");
4786module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4787MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4788module_param_named(
4789 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
72645eff
WYG		 4790MODULE_PARM_DESC(disable_hw_scan,
4791 "disable hardware scanning (default 0) (deprecated)");
dd7a2509
JB		 4792
4793module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4794 S_IRUGO);
4795MODULE_PARM_DESC(ucode_alternative,
4796 "specify ucode alternative to use from ucode file");
bee008b7
WYG		 4797
4798module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4799MODULE_PARM_DESC(antenna_coupling,
4800 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9 4801
9f28ebc3
WYG		 4802module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4803MODULE_PARM_DESC(bt_ch_inhibition,
4804 "Disable BT channel inhibition (default: enable)");
Linux kernel - Deliverables
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