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iwlagn: move Tx datapath to transport layer
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c 34#include <linux/init.h>
5a0e3ad6 35#include <linux/slab.h>
b481de9c
ZY		 36#include <linux/dma-mapping.h>
37#include <linux/delay.h>
d43c36dc 38#include <linux/sched.h>
b481de9c
ZY		 39#include <linux/skbuff.h>
40#include <linux/netdevice.h>
41#include <linux/wireless.h>
42#include <linux/firmware.h>
b481de9c
ZY		 43#include <linux/etherdevice.h>
44#include <linux/if_arp.h>
45
b481de9c
ZY		 46#include <net/mac80211.h>
47
48#include <asm/div64.h>
49
6bc913bd 50#include "iwl-eeprom.h"
3e0d4cb1 51#include "iwl-dev.h"
fee1247a 52#include "iwl-core.h"
3395f6e9 53#include "iwl-io.h"
b481de9c 54#include "iwl-helpers.h"
6974e363 55#include "iwl-sta.h"
0de76736 56#include "iwl-agn-calib.h"
a1175124 57#include "iwl-agn.h"
48d1a211 58#include "iwl-pci.h"
c85eb619 59#include "iwl-trans.h"
416e1438 60
b481de9c
ZY		 61/******************************************************************************
62 *
63 * module boiler plate
64 *
65 ******************************************************************************/
66
b481de9c
ZY		 67/*
68 * module name, copyright, version, etc.
b481de9c 69 */
d783b061 70#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 71
0a6857e7 72#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 73#define VD "d"
74#else
75#define VD
76#endif
77
81963d68 78#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 79
b481de9c
ZY		 80
81MODULE_DESCRIPTION(DRV_DESCRIPTION);
82MODULE_VERSION(DRV_VERSION);
a7b75207 83MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
ZY		 84MODULE_LICENSE("GPL");
85
bee008b7 86static int iwlagn_ant_coupling;
f37837c9 87static bool iwlagn_bt_ch_announce = 1;
bee008b7 88
5b9f8cd3 89void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f 90{
246ed355 91 struct iwl_rxon_context *ctx;
5da4b55f 92
e3f10cea
WYG		 93 for_each_context(priv, ctx) {
94 iwlagn_set_rxon_chain(priv, ctx);
95 if (ctx->active.rx_chain != ctx->staging.rx_chain)
96 iwlagn_commit_rxon(priv, ctx);
246ed355 97 }
5da4b55f
MA		 98}
99
47ff65c4
DH		 100/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
101static void iwl_set_beacon_tim(struct iwl_priv *priv,
77834543
JB		 102 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
103 u8 *beacon, u32 frame_size)
47ff65c4
DH		 104{
105 u16 tim_idx;
106 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
107
108 /*
109 * The index is relative to frame start but we start looking at the
110 * variable-length part of the beacon.
111 */
112 tim_idx = mgmt->u.beacon.variable - beacon;
113
114 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
115 while ((tim_idx < (frame_size - 2)) &&
116 (beacon[tim_idx] != WLAN_EID_TIM))
117 tim_idx += beacon[tim_idx+1] + 2;
118
119 /* If TIM field was found, set variables */
120 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
121 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
122 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
123 } else
124 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
125}
126
8a98d49e 127int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
4bf64efd
TW		 128{
129 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
8a98d49e
JB		 130 struct iwl_host_cmd cmd = {
131 .id = REPLY_TX_BEACON,
e419d62d 132 .flags = CMD_SYNC,
8a98d49e 133 };
0b5b3ff1 134 struct ieee80211_tx_info *info;
47ff65c4
DH		 135 u32 frame_size;
136 u32 rate_flags;
137 u32 rate;
8a98d49e 138
47ff65c4
DH		 139 /*
140 * We have to set up the TX command, the TX Beacon command, and the
141 * beacon contents.
142 */
4bf64efd 143
76d04815
JB		 144 lockdep_assert_held(&priv->mutex);
145
146 if (!priv->beacon_ctx) {
147 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
950094cb 148 return 0;
76d04815
JB		 149 }
150
8a98d49e
JB		 151 if (WARN_ON(!priv->beacon_skb))
152 return -EINVAL;
153
4ce7cc2b
JB		 154 /* Allocate beacon command */
155 if (!priv->beacon_cmd)
156 priv->beacon_cmd = kzalloc(sizeof(*tx_beacon_cmd), GFP_KERNEL);
157 tx_beacon_cmd = priv->beacon_cmd;
8a98d49e
JB		 158 if (!tx_beacon_cmd)
159 return -ENOMEM;
160
161 frame_size = priv->beacon_skb->len;
4bf64efd 162
47ff65c4 163 /* Set up TX command fields */
4bf64efd 164 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
76d04815 165 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
47ff65c4
DH		 166 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
167 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
168 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 169
47ff65c4 170 /* Set up TX beacon command fields */
4ce7cc2b 171 iwl_set_beacon_tim(priv, tx_beacon_cmd, priv->beacon_skb->data,
77834543 172 frame_size);
4bf64efd 173
47ff65c4 174 /* Set up packet rate and flags */
0b5b3ff1
JB		 175 info = IEEE80211_SKB_CB(priv->beacon_skb);
176
177 /*
178 * Let's set up the rate at least somewhat correctly;
179 * it will currently not actually be used by the uCode,
180 * it uses the broadcast station's rate instead.
181 */
182 if (info->control.rates[0].idx < 0 ||
183 info->control.rates[0].flags & IEEE80211_TX_RC_MCS)
184 rate = 0;
185 else
186 rate = info->control.rates[0].idx;
187
0e1654fa
JB		 188 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
189 priv->hw_params.valid_tx_ant);
47ff65c4 190 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
0b5b3ff1
JB		 191
192 /* In mac80211, rates for 5 GHz start at 0 */
193 if (info->band == IEEE80211_BAND_5GHZ)
194 rate += IWL_FIRST_OFDM_RATE;
195 else if (rate >= IWL_FIRST_CCK_RATE && rate <= IWL_LAST_CCK_RATE)
47ff65c4 196 rate_flags |= RATE_MCS_CCK_MSK;
0b5b3ff1
JB		 197
198 tx_beacon_cmd->tx.rate_n_flags =
199 iwl_hw_set_rate_n_flags(rate, rate_flags);
4bf64efd 200
8a98d49e 201 /* Submit command */
4ce7cc2b 202 cmd.len[0] = sizeof(*tx_beacon_cmd);
3fa50738 203 cmd.data[0] = tx_beacon_cmd;
4ce7cc2b
JB		 204 cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
205 cmd.len[1] = frame_size;
206 cmd.data[1] = priv->beacon_skb->data;
207 cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
7aaa1d79 208
bdfbf092 209 return trans_send_cmd(priv, &cmd);
a8e74e27
SO		 210}
211
5b9f8cd3 212static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 213{
c79dd5b5
TW		 214 struct iwl_priv *priv =
215 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 216 struct sk_buff *beacon;
217
76d04815
JB		 218 mutex_lock(&priv->mutex);
219 if (!priv->beacon_ctx) {
220 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
221 goto out;
222 }
b481de9c 223
60744f62
JB		 224 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
225 /*
226 * The ucode will send beacon notifications even in
227 * IBSS mode, but we don't want to process them. But
228 * we need to defer the type check to here due to
229 * requiring locking around the beacon_ctx access.
230 */
231 goto out;
232 }
233
76d04815
JB		 234 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
235 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
b481de9c 236 if (!beacon) {
77834543 237 IWL_ERR(priv, "update beacon failed -- keeping old\n");
76d04815 238 goto out;
b481de9c
ZY		 239 }
240
b481de9c 241 /* new beacon skb is allocated every time; dispose previous.*/
77834543 242 dev_kfree_skb(priv->beacon_skb);
b481de9c 243
12e934dc 244 priv->beacon_skb = beacon;
b481de9c 245
2295c66b 246 iwlagn_send_beacon_cmd(priv);
76d04815
JB		 247 out:
248 mutex_unlock(&priv->mutex);
b481de9c
ZY		 249}
250
fbba9410
WYG		 251static void iwl_bg_bt_runtime_config(struct work_struct *work)
252{
253 struct iwl_priv *priv =
254 container_of(work, struct iwl_priv, bt_runtime_config);
255
256 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
257 return;
258
259 /* dont send host command if rf-kill is on */
260 if (!iwl_is_ready_rf(priv))
261 return;
e55b517c 262 iwlagn_send_advance_bt_config(priv);
fbba9410
WYG		 263}
264
bee008b7
WYG		 265static void iwl_bg_bt_full_concurrency(struct work_struct *work)
266{
267 struct iwl_priv *priv =
268 container_of(work, struct iwl_priv, bt_full_concurrency);
246ed355 269 struct iwl_rxon_context *ctx;
bee008b7 270
dc1a4068
SG		 271 mutex_lock(&priv->mutex);
272
bee008b7 273 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
dc1a4068 274 goto out;
bee008b7
WYG		 275
276 /* dont send host command if rf-kill is on */
277 if (!iwl_is_ready_rf(priv))
dc1a4068 278 goto out;
bee008b7
WYG		 279
280 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
281 priv->bt_full_concurrent ?
282 "full concurrency" : "3-wire");
283
284 /*
285 * LQ & RXON updated cmds must be sent before BT Config cmd
286 * to avoid 3-wire collisions
287 */
246ed355 288 for_each_context(priv, ctx) {
e3f10cea 289 iwlagn_set_rxon_chain(priv, ctx);
805a3b81 290 iwlagn_commit_rxon(priv, ctx);
246ed355 291 }
bee008b7 292
e55b517c 293 iwlagn_send_advance_bt_config(priv);
dc1a4068
SG		 294out:
295 mutex_unlock(&priv->mutex);
bee008b7
WYG		 296}
297
4e39317d 298/**
5b9f8cd3 299 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 300 *
301 * This callback is provided in order to send a statistics request.
302 *
303 * This timer function is continually reset to execute within
304 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
305 * was received. We need to ensure we receive the statistics in order
306 * to update the temperature used for calibrating the TXPOWER.
307 */
5b9f8cd3 308static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 309{
310 struct iwl_priv *priv = (struct iwl_priv *)data;
311
312 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
313 return;
314
61780ee3
MA		 315 /* dont send host command if rf-kill is on */
316 if (!iwl_is_ready_rf(priv))
317 return;
318
ef8d5529 319 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 320}
321
a9e1cb6a
WYG		 322
323static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
324 u32 start_idx, u32 num_events,
325 u32 mode)
326{
327 u32 i;
328 u32 ptr; /* SRAM byte address of log data */
329 u32 ev, time, data; /* event log data */
330 unsigned long reg_flags;
331
332 if (mode == 0)
333 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
334 else
335 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
336
337 /* Make sure device is powered up for SRAM reads */
338 spin_lock_irqsave(&priv->reg_lock, reg_flags);
339 if (iwl_grab_nic_access(priv)) {
340 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
341 return;
342 }
343
344 /* Set starting address; reads will auto-increment */
02a7fa00 345 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
a9e1cb6a
WYG		 346 rmb();
347
348 /*
349 * "time" is actually "data" for mode 0 (no timestamp).
350 * place event id # at far right for easier visual parsing.
351 */
352 for (i = 0; i < num_events; i++) {
02a7fa00
JB		 353 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
354 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
a9e1cb6a
WYG		 355 if (mode == 0) {
356 trace_iwlwifi_dev_ucode_cont_event(priv,
357 0, time, ev);
358 } else {
02a7fa00 359 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
a9e1cb6a
WYG		 360 trace_iwlwifi_dev_ucode_cont_event(priv,
361 time, data, ev);
362 }
363 }
364 /* Allow device to power down */
365 iwl_release_nic_access(priv);
366 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
367}
368
875295f1 369static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 370{
371 u32 capacity; /* event log capacity in # entries */
372 u32 base; /* SRAM byte address of event log header */
373 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
374 u32 num_wraps; /* # times uCode wrapped to top of log */
375 u32 next_entry; /* index of next entry to be written by uCode */
376
d7d5783c 377 base = priv->device_pointers.error_event_table;
a9e1cb6a
WYG		 378 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
379 capacity = iwl_read_targ_mem(priv, base);
380 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
381 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
382 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
383 } else
384 return;
385
386 if (num_wraps == priv->event_log.num_wraps) {
387 iwl_print_cont_event_trace(priv,
388 base, priv->event_log.next_entry,
389 next_entry - priv->event_log.next_entry,
390 mode);
391 priv->event_log.non_wraps_count++;
392 } else {
393 if ((num_wraps - priv->event_log.num_wraps) > 1)
394 priv->event_log.wraps_more_count++;
395 else
396 priv->event_log.wraps_once_count++;
397 trace_iwlwifi_dev_ucode_wrap_event(priv,
398 num_wraps - priv->event_log.num_wraps,
399 next_entry, priv->event_log.next_entry);
400 if (next_entry < priv->event_log.next_entry) {
401 iwl_print_cont_event_trace(priv, base,
402 priv->event_log.next_entry,
403 capacity - priv->event_log.next_entry,
404 mode);
405
406 iwl_print_cont_event_trace(priv, base, 0,
407 next_entry, mode);
408 } else {
409 iwl_print_cont_event_trace(priv, base,
410 next_entry, capacity - next_entry,
411 mode);
412
413 iwl_print_cont_event_trace(priv, base, 0,
414 next_entry, mode);
415 }
416 }
417 priv->event_log.num_wraps = num_wraps;
418 priv->event_log.next_entry = next_entry;
419}
420
421/**
422 * iwl_bg_ucode_trace - Timer callback to log ucode event
423 *
424 * The timer is continually set to execute every
425 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
426 * this function is to perform continuous uCode event logging operation
427 * if enabled
428 */
429static void iwl_bg_ucode_trace(unsigned long data)
430{
431 struct iwl_priv *priv = (struct iwl_priv *)data;
432
433 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
434 return;
435
436 if (priv->event_log.ucode_trace) {
437 iwl_continuous_event_trace(priv);
438 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
439 mod_timer(&priv->ucode_trace,
440 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
441 }
442}
443
65550636
WYG		 444static void iwl_bg_tx_flush(struct work_struct *work)
445{
446 struct iwl_priv *priv =
447 container_of(work, struct iwl_priv, tx_flush);
448
449 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
450 return;
451
452 /* do nothing if rf-kill is on */
453 if (!iwl_is_ready_rf(priv))
454 return;
455
c68744fb
WYG		 456 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
457 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
65550636
WYG		 458}
459
b481de9c 460/**
a55360e4 461 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 462 *
463 * Uses the priv->rx_handlers callback function array to invoke
464 * the appropriate handlers, including command responses,
465 * frame-received notifications, and other notifications.
466 */
f945f108 467static void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 468{
a55360e4 469 struct iwl_rx_mem_buffer *rxb;
db11d634 470 struct iwl_rx_packet *pkt;
a55360e4 471 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 472 u32 r, i;
473 int reclaim;
474 unsigned long flags;
5c0eef96 475 u8 fill_rx = 0;
d68ab680 476 u32 count = 8;
4752c93c 477 int total_empty;
b481de9c 478
6440adb5
CB		 479 /* uCode's read index (stored in shared DRAM) indicates the last Rx
480 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 481 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 482 i = rxq->read;
483
484 /* Rx interrupt, but nothing sent from uCode */
485 if (i == r)
e1623446 486 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 487
4752c93c 488 /* calculate total frames need to be restock after handling RX */
7300515d 489 total_empty = r - rxq->write_actual;
4752c93c
MA		 490 if (total_empty < 0)
491 total_empty += RX_QUEUE_SIZE;
492
493 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 494 fill_rx = 1;
495
b481de9c 496 while (i != r) {
f4989d9b
JB		 497 int len;
498
b481de9c
ZY		 499 rxb = rxq->queue[i];
500
9fbab516 501 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 502 * then a bug has been introduced in the queue refilling
503 * routines -- catch it here */
3e41ace5
JB		 504 if (WARN_ON(rxb == NULL)) {
505 i = (i + 1) & RX_QUEUE_MASK;
506 continue;
507 }
b481de9c
ZY		 508
509 rxq->queue[i] = NULL;
510
795414db 511 dma_unmap_page(priv->bus.dev, rxb->page_dma,
2f301227 512 PAGE_SIZE << priv->hw_params.rx_page_order,
795414db 513 DMA_FROM_DEVICE);
2f301227 514 pkt = rxb_addr(rxb);
b481de9c 515
f4989d9b
JB		 516 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
517 len += sizeof(u32); /* account for status word */
518 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 519
b481de9c
ZY		 520 /* Reclaim a command buffer only if this packet is a response
521 * to a (driver-originated) command.
522 * If the packet (e.g. Rx frame) originated from uCode,
523 * there is no command buffer to reclaim.
524 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
525 * but apparently a few don't get set; catch them here. */
526 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
527 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 528 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 529 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 530 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 531 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
532 (pkt->hdr.cmd != REPLY_TX);
533
7194207c
JB		 534 /*
535 * Do the notification wait before RX handlers so
536 * even if the RX handler consumes the RXB we have
537 * access to it in the notification wait entry.
538 */
539 if (!list_empty(&priv->_agn.notif_waits)) {
540 struct iwl_notification_wait *w;
541
542 spin_lock(&priv->_agn.notif_wait_lock);
543 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
544 if (w->cmd == pkt->hdr.cmd) {
545 w->triggered = true;
546 if (w->fn)
09f18afe 547 w->fn(priv, pkt, w->fn_data);
7194207c
JB		 548 }
549 }
550 spin_unlock(&priv->_agn.notif_wait_lock);
551
552 wake_up_all(&priv->_agn.notif_waitq);
553 }
4613e72d
CK		 554 if (priv->pre_rx_handler)
555 priv->pre_rx_handler(priv, rxb);
7194207c 556
b481de9c
ZY		 557 /* Based on type of command response or notification,
558 * handle those that need handling via function in
5b9f8cd3 559 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 560 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 561 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 562 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 563 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 564 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 565 } else {
566 /* No handling needed */
e1623446 567 IWL_DEBUG_RX(priv,
b481de9c
ZY		 568 "r %d i %d No handler needed for %s, 0x%02x\n",
569 r, i, get_cmd_string(pkt->hdr.cmd),
570 pkt->hdr.cmd);
571 }
572
29b1b268
ZY		 573 /*
574 * XXX: After here, we should always check rxb->page
575 * against NULL before touching it or its virtual
576 * memory (pkt). Because some rx_handler might have
577 * already taken or freed the pages.
578 */
579
b481de9c 580 if (reclaim) {
2f301227 581 /* Invoke any callbacks, transfer the buffer to caller,
e419d62d 582 * and fire off the (possibly) blocking
bdfbf092 583 * trans_send_cmd()
b481de9c 584 * as we reclaim the driver command queue */
29b1b268 585 if (rxb->page)
17b88929 586 iwl_tx_cmd_complete(priv, rxb);
b481de9c 587 else
39aadf8c 588 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 589 }
590
7300515d
ZY		 591 /* Reuse the page if possible. For notification packets and
592 * SKBs that fail to Rx correctly, add them back into the
593 * rx_free list for reuse later. */
594 spin_lock_irqsave(&rxq->lock, flags);
2f301227 595 if (rxb->page != NULL) {
795414db 596 rxb->page_dma = dma_map_page(priv->bus.dev, rxb->page,
7300515d 597 0, PAGE_SIZE << priv->hw_params.rx_page_order,
795414db 598 DMA_FROM_DEVICE);
7300515d
ZY		 599 list_add_tail(&rxb->list, &rxq->rx_free);
600 rxq->free_count++;
601 } else
602 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 603
b481de9c 604 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 605
b481de9c 606 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 607 /* If there are a lot of unused frames,
608 * restock the Rx queue so ucode wont assert. */
609 if (fill_rx) {
610 count++;
611 if (count >= 8) {
7300515d 612 rxq->read = i;
54b81550 613 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 614 count = 0;
615 }
616 }
b481de9c
ZY		 617 }
618
619 /* Backtrack one entry */
7300515d 620 rxq->read = i;
4752c93c 621 if (fill_rx)
54b81550 622 iwlagn_rx_replenish_now(priv);
4752c93c 623 else
54b81550 624 iwlagn_rx_queue_restock(priv);
a55360e4 625}
a55360e4 626
ef850d7c
MA		 627/* tasklet for iwlagn interrupt */
628static void iwl_irq_tasklet(struct iwl_priv *priv)
629{
630 u32 inta = 0;
631 u32 handled = 0;
632 unsigned long flags;
8756990f 633 u32 i;
ef850d7c
MA		 634#ifdef CONFIG_IWLWIFI_DEBUG
635 u32 inta_mask;
636#endif
637
638 spin_lock_irqsave(&priv->lock, flags);
639
640 /* Ack/clear/reset pending uCode interrupts.
641 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
642 */
48a6be6a
SZ		 643 /* There is a hardware bug in the interrupt mask function that some
644 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
645 * they are disabled in the CSR_INT_MASK register. Furthermore the
646 * ICT interrupt handling mechanism has another bug that might cause
647 * these unmasked interrupts fail to be detected. We workaround the
648 * hardware bugs here by ACKing all the possible interrupts so that
649 * interrupt coalescing can still be achieved.
650 */
4a35ecf8 651 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 652
a4c8b2a6 653 inta = priv->_agn.inta;
ef850d7c
MA		 654
655#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 656 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 657 /* just for debug */
658 inta_mask = iwl_read32(priv, CSR_INT_MASK);
659 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
660 inta, inta_mask);
661 }
662#endif
2f301227
ZY		 663
664 spin_unlock_irqrestore(&priv->lock, flags);
665
a4c8b2a6
JB		 666 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
667 priv->_agn.inta = 0;
ef850d7c
MA		 668
669 /* Now service all interrupt bits discovered above. */
670 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 671 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 672
673 /* Tell the device to stop sending interrupts */
674 iwl_disable_interrupts(priv);
675
676 priv->isr_stats.hw++;
677 iwl_irq_handle_error(priv);
678
679 handled |= CSR_INT_BIT_HW_ERR;
680
ef850d7c
MA		 681 return;
682 }
683
684#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 685 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 686 /* NIC fires this, but we don't use it, redundant with WAKEUP */
687 if (inta & CSR_INT_BIT_SCD) {
688 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
689 "the frame/frames.\n");
690 priv->isr_stats.sch++;
691 }
692
693 /* Alive notification via Rx interrupt will do the real work */
694 if (inta & CSR_INT_BIT_ALIVE) {
695 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
696 priv->isr_stats.alive++;
697 }
698 }
699#endif
700 /* Safely ignore these bits for debug checks below */
701 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
702
703 /* HW RF KILL switch toggled */
704 if (inta & CSR_INT_BIT_RF_KILL) {
705 int hw_rf_kill = 0;
706 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
707 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
708 hw_rf_kill = 1;
709
4c423a2b 710 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 711 hw_rf_kill ? "disable radio" : "enable radio");
712
713 priv->isr_stats.rfkill++;
714
715 /* driver only loads ucode once setting the interface up.
716 * the driver allows loading the ucode even if the radio
717 * is killed. Hence update the killswitch state here. The
718 * rfkill handler will care about restarting if needed.
719 */
720 if (!test_bit(STATUS_ALIVE, &priv->status)) {
721 if (hw_rf_kill)
722 set_bit(STATUS_RF_KILL_HW, &priv->status);
723 else
724 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 725 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 726 }
727
728 handled |= CSR_INT_BIT_RF_KILL;
729 }
730
731 /* Chip got too hot and stopped itself */
732 if (inta & CSR_INT_BIT_CT_KILL) {
733 IWL_ERR(priv, "Microcode CT kill error detected.\n");
734 priv->isr_stats.ctkill++;
735 handled |= CSR_INT_BIT_CT_KILL;
736 }
737
738 /* Error detected by uCode */
739 if (inta & CSR_INT_BIT_SW_ERR) {
740 IWL_ERR(priv, "Microcode SW error detected. "
741 " Restarting 0x%X.\n", inta);
742 priv->isr_stats.sw++;
ef850d7c
MA		 743 iwl_irq_handle_error(priv);
744 handled |= CSR_INT_BIT_SW_ERR;
745 }
746
747 /* uCode wakes up after power-down sleep */
748 if (inta & CSR_INT_BIT_WAKEUP) {
749 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
750 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 751 for (i = 0; i < priv->hw_params.max_txq_num; i++)
752 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 753
754 priv->isr_stats.wakeup++;
755
756 handled |= CSR_INT_BIT_WAKEUP;
757 }
758
759 /* All uCode command responses, including Tx command responses,
760 * Rx "responses" (frame-received notification), and other
761 * notifications from uCode come through here*/
40cefda9
MA		 762 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
763 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 764 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 765 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
766 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
767 iwl_write32(priv, CSR_FH_INT_STATUS,
f7d046f9 768 CSR_FH_INT_RX_MASK);
40cefda9
MA		 769 }
770 if (inta & CSR_INT_BIT_RX_PERIODIC) {
771 handled |= CSR_INT_BIT_RX_PERIODIC;
772 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
773 }
774 /* Sending RX interrupt require many steps to be done in the
775 * the device:
776 * 1- write interrupt to current index in ICT table.
777 * 2- dma RX frame.
778 * 3- update RX shared data to indicate last write index.
779 * 4- send interrupt.
780 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 781 * but the shared data changes does not reflect this;
782 * periodic interrupt will detect any dangling Rx activity.
40cefda9 783 */
74ba67ed
BC		 784
785 /* Disable periodic interrupt; we use it as just a one-shot. */
786 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 787 CSR_INT_PERIODIC_DIS);
ef850d7c 788 iwl_rx_handle(priv);
74ba67ed
BC		 789
790 /*
791 * Enable periodic interrupt in 8 msec only if we received
792 * real RX interrupt (instead of just periodic int), to catch
793 * any dangling Rx interrupt. If it was just the periodic
794 * interrupt, there was no dangling Rx activity, and no need
795 * to extend the periodic interrupt; one-shot is enough.
796 */
40cefda9 797 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 798 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 799 CSR_INT_PERIODIC_ENA);
800
ef850d7c 801 priv->isr_stats.rx++;
ef850d7c
MA		 802 }
803
c72cd19f 804 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c 805 if (inta & CSR_INT_BIT_FH_TX) {
f7d046f9 806 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
c72cd19f 807 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 808 priv->isr_stats.tx++;
809 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 810 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 811 priv->ucode_write_complete = 1;
812 wake_up_interruptible(&priv->wait_command_queue);
813 }
814
815 if (inta & ~handled) {
816 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
817 priv->isr_stats.unhandled++;
818 }
819
40cefda9 820 if (inta & ~(priv->inta_mask)) {
ef850d7c 821 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 822 inta & ~priv->inta_mask);
ef850d7c
MA		 823 }
824
ef850d7c 825 /* Re-enable all interrupts */
62e45c14 826 /* only Re-enable if disabled by irq */
ef850d7c
MA		 827 if (test_bit(STATUS_INT_ENABLED, &priv->status))
828 iwl_enable_interrupts(priv);
3dd823e6
DF		 829 /* Re-enable RF_KILL if it occurred */
830 else if (handled & CSR_INT_BIT_RF_KILL)
831 iwl_enable_rfkill_int(priv);
ef850d7c
MA		 832}
833
7d47618a
EG		 834/*****************************************************************************
835 *
836 * sysfs attributes
837 *
838 *****************************************************************************/
839
840#ifdef CONFIG_IWLWIFI_DEBUG
841
842/*
843 * The following adds a new attribute to the sysfs representation
844 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
845 * used for controlling the debug level.
846 *
847 * See the level definitions in iwl for details.
848 *
849 * The debug_level being managed using sysfs below is a per device debug
850 * level that is used instead of the global debug level if it (the per
851 * device debug level) is set.
852 */
853static ssize_t show_debug_level(struct device *d,
854 struct device_attribute *attr, char *buf)
855{
856 struct iwl_priv *priv = dev_get_drvdata(d);
857 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
858}
859static ssize_t store_debug_level(struct device *d,
860 struct device_attribute *attr,
861 const char *buf, size_t count)
862{
863 struct iwl_priv *priv = dev_get_drvdata(d);
864 unsigned long val;
865 int ret;
866
867 ret = strict_strtoul(buf, 0, &val);
868 if (ret)
869 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
870 else {
871 priv->debug_level = val;
872 if (iwl_alloc_traffic_mem(priv))
873 IWL_ERR(priv,
874 "Not enough memory to generate traffic log\n");
875 }
876 return strnlen(buf, count);
877}
878
879static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
880 show_debug_level, store_debug_level);
881
882
883#endif /* CONFIG_IWLWIFI_DEBUG */
884
885
886static ssize_t show_temperature(struct device *d,
887 struct device_attribute *attr, char *buf)
888{
889 struct iwl_priv *priv = dev_get_drvdata(d);
890
891 if (!iwl_is_alive(priv))
892 return -EAGAIN;
893
894 return sprintf(buf, "%d\n", priv->temperature);
895}
896
897static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
898
899static ssize_t show_tx_power(struct device *d,
900 struct device_attribute *attr, char *buf)
901{
902 struct iwl_priv *priv = dev_get_drvdata(d);
903
904 if (!iwl_is_ready_rf(priv))
905 return sprintf(buf, "off\n");
906 else
907 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
908}
909
910static ssize_t store_tx_power(struct device *d,
911 struct device_attribute *attr,
912 const char *buf, size_t count)
913{
914 struct iwl_priv *priv = dev_get_drvdata(d);
915 unsigned long val;
916 int ret;
917
918 ret = strict_strtoul(buf, 10, &val);
919 if (ret)
920 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
921 else {
922 ret = iwl_set_tx_power(priv, val, false);
923 if (ret)
924 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
925 ret);
926 else
927 ret = count;
928 }
929 return ret;
930}
931
932static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
933
7d47618a
EG		 934static struct attribute *iwl_sysfs_entries[] = {
935 &dev_attr_temperature.attr,
936 &dev_attr_tx_power.attr,
7d47618a
EG		 937#ifdef CONFIG_IWLWIFI_DEBUG
938 &dev_attr_debug_level.attr,
939#endif
940 NULL
941};
942
943static struct attribute_group iwl_attribute_group = {
944 .name = NULL, /* put in device directory */
945 .attrs = iwl_sysfs_entries,
946};
947
b481de9c
ZY		 948/******************************************************************************
949 *
950 * uCode download functions
951 *
952 ******************************************************************************/
953
3599d39a 954static void iwl_free_fw_desc(struct iwl_priv *priv, struct fw_desc *desc)
dbf28e21
JB		 955{
956 if (desc->v_addr)
3599d39a 957 dma_free_coherent(priv->bus.dev, desc->len,
dbf28e21
JB		 958 desc->v_addr, desc->p_addr);
959 desc->v_addr = NULL;
960 desc->len = 0;
961}
962
3599d39a 963static void iwl_free_fw_img(struct iwl_priv *priv, struct fw_img *img)
dbf28e21 964{
3599d39a
EG		 965 iwl_free_fw_desc(priv, &img->code);
966 iwl_free_fw_desc(priv, &img->data);
dbf28e21
JB		 967}
968
3599d39a
EG		 969static void iwl_dealloc_ucode(struct iwl_priv *priv)
970{
971 iwl_free_fw_img(priv, &priv->ucode_rt);
972 iwl_free_fw_img(priv, &priv->ucode_init);
973}
974
975static int iwl_alloc_fw_desc(struct iwl_priv *priv, struct fw_desc *desc,
dbf28e21
JB		 976 const void *data, size_t len)
977{
978 if (!len) {
979 desc->v_addr = NULL;
980 return -EINVAL;
981 }
982
3599d39a 983 desc->v_addr = dma_alloc_coherent(priv->bus.dev, len,
dbf28e21
JB		 984 &desc->p_addr, GFP_KERNEL);
985 if (!desc->v_addr)
986 return -ENOMEM;
3599d39a 987
dbf28e21
JB		 988 desc->len = len;
989 memcpy(desc->v_addr, data, len);
990 return 0;
991}
992
dd7a2509
JB		 993struct iwlagn_ucode_capabilities {
994 u32 max_probe_length;
6a822d06 995 u32 standard_phy_calibration_size;
3997ff39 996 u32 flags;
dd7a2509 997};
edcdf8b2 998
b08dfd04 999static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1000static int iwl_mac_setup_register(struct iwl_priv *priv,
1001 struct iwlagn_ucode_capabilities *capa);
b08dfd04 1002
39396085
JS		 1003#define UCODE_EXPERIMENTAL_INDEX 100
1004#define UCODE_EXPERIMENTAL_TAG "exp"
1005
b08dfd04
JB		 1006static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1007{
1008 const char *name_pre = priv->cfg->fw_name_pre;
39396085 1009 char tag[8];
b08dfd04 1010
39396085
JS		 1011 if (first) {
1012#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1013 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1014 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1015 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1016#endif
b08dfd04 1017 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS		 1018 sprintf(tag, "%d", priv->fw_index);
1019 } else {
b08dfd04 1020 priv->fw_index--;
39396085
JS		 1021 sprintf(tag, "%d", priv->fw_index);
1022 }
b08dfd04
JB		 1023
1024 if (priv->fw_index < priv->cfg->ucode_api_min) {
1025 IWL_ERR(priv, "no suitable firmware found!\n");
1026 return -ENOENT;
1027 }
1028
39396085 1029 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1030
39396085
JS		 1031 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1032 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1033 ? "EXPERIMENTAL " : "",
b08dfd04
JB		 1034 priv->firmware_name);
1035
1036 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
3599d39a
EG		 1037 priv->bus.dev,
1038 GFP_KERNEL, priv, iwl_ucode_callback);
b08dfd04
JB		 1039}
1040
0e9a44dc 1041struct iwlagn_firmware_pieces {
1fc35276
JB		 1042 const void *inst, *data, *init, *init_data;
1043 size_t inst_size, data_size, init_size, init_data_size;
0e9a44dc
JB		 1044
1045 u32 build;
b2e640d4
JB		 1046
1047 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1048 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1049};
1050
1051static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1052 const struct firmware *ucode_raw,
1053 struct iwlagn_firmware_pieces *pieces)
1054{
1055 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1056 u32 api_ver, hdr_size;
1057 const u8 *src;
1058
1059 priv->ucode_ver = le32_to_cpu(ucode->ver);
1060 api_ver = IWL_UCODE_API(priv->ucode_ver);
1061
1062 switch (api_ver) {
1063 default:
f7d046f9
WYG		 1064 hdr_size = 28;
1065 if (ucode_raw->size < hdr_size) {
1066 IWL_ERR(priv, "File size too small!\n");
1067 return -EINVAL;
0e9a44dc 1068 }
f7d046f9
WYG		 1069 pieces->build = le32_to_cpu(ucode->u.v2.build);
1070 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1071 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1072 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1073 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
f7d046f9
WYG		 1074 src = ucode->u.v2.data;
1075 break;
0e9a44dc
JB		 1076 case 0:
1077 case 1:
1078 case 2:
1079 hdr_size = 24;
1080 if (ucode_raw->size < hdr_size) {
1081 IWL_ERR(priv, "File size too small!\n");
1082 return -EINVAL;
1083 }
1084 pieces->build = 0;
1085 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1086 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1087 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1088 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
0e9a44dc
JB		 1089 src = ucode->u.v1.data;
1090 break;
1091 }
1092
1093 /* Verify size of file vs. image size info in file's header */
1094 if (ucode_raw->size != hdr_size + pieces->inst_size +
1095 pieces->data_size + pieces->init_size +
1fc35276 1096 pieces->init_data_size) {
0e9a44dc
JB		 1097
1098 IWL_ERR(priv,
1099 "uCode file size %d does not match expected size\n",
1100 (int)ucode_raw->size);
1101 return -EINVAL;
1102 }
1103
1104 pieces->inst = src;
1105 src += pieces->inst_size;
1106 pieces->data = src;
1107 src += pieces->data_size;
1108 pieces->init = src;
1109 src += pieces->init_size;
1110 pieces->init_data = src;
1111 src += pieces->init_data_size;
0e9a44dc
JB		 1112
1113 return 0;
1114}
1115
dd7a2509
JB		 1116static int iwlagn_wanted_ucode_alternative = 1;
1117
1118static int iwlagn_load_firmware(struct iwl_priv *priv,
1119 const struct firmware *ucode_raw,
1120 struct iwlagn_firmware_pieces *pieces,
1121 struct iwlagn_ucode_capabilities *capa)
1122{
1123 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1124 struct iwl_ucode_tlv *tlv;
1125 size_t len = ucode_raw->size;
1126 const u8 *data;
1127 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1128 u64 alternatives;
ad8d8333
WYG		 1129 u32 tlv_len;
1130 enum iwl_ucode_tlv_type tlv_type;
1131 const u8 *tlv_data;
dd7a2509 1132
ad8d8333
WYG		 1133 if (len < sizeof(*ucode)) {
1134 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1135 return -EINVAL;
ad8d8333 1136 }
dd7a2509 1137
ad8d8333
WYG		 1138 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1139 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1140 le32_to_cpu(ucode->magic));
dd7a2509 1141 return -EINVAL;
ad8d8333 1142 }
dd7a2509
JB		 1143
1144 /*
1145 * Check which alternatives are present, and "downgrade"
1146 * when the chosen alternative is not present, warning
1147 * the user when that happens. Some files may not have
1148 * any alternatives, so don't warn in that case.
1149 */
1150 alternatives = le64_to_cpu(ucode->alternatives);
1151 tmp = wanted_alternative;
1152 if (wanted_alternative > 63)
1153 wanted_alternative = 63;
1154 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1155 wanted_alternative--;
1156 if (wanted_alternative && wanted_alternative != tmp)
1157 IWL_WARN(priv,
1158 "uCode alternative %d not available, choosing %d\n",
1159 tmp, wanted_alternative);
1160
1161 priv->ucode_ver = le32_to_cpu(ucode->ver);
1162 pieces->build = le32_to_cpu(ucode->build);
1163 data = ucode->data;
1164
1165 len -= sizeof(*ucode);
1166
704da534 1167 while (len >= sizeof(*tlv)) {
dd7a2509 1168 u16 tlv_alt;
dd7a2509
JB		 1169
1170 len -= sizeof(*tlv);
1171 tlv = (void *)data;
1172
1173 tlv_len = le32_to_cpu(tlv->length);
1174 tlv_type = le16_to_cpu(tlv->type);
1175 tlv_alt = le16_to_cpu(tlv->alternative);
1176 tlv_data = tlv->data;
1177
ad8d8333
WYG		 1178 if (len < tlv_len) {
1179 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1180 len, tlv_len);
dd7a2509 1181 return -EINVAL;
ad8d8333 1182 }
dd7a2509
JB		 1183 len -= ALIGN(tlv_len, 4);
1184 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1185
1186 /*
1187 * Alternative 0 is always valid.
1188 *
1189 * Skip alternative TLVs that are not selected.
1190 */
1191 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1192 continue;
1193
1194 switch (tlv_type) {
1195 case IWL_UCODE_TLV_INST:
1196 pieces->inst = tlv_data;
1197 pieces->inst_size = tlv_len;
1198 break;
1199 case IWL_UCODE_TLV_DATA:
1200 pieces->data = tlv_data;
1201 pieces->data_size = tlv_len;
1202 break;
1203 case IWL_UCODE_TLV_INIT:
1204 pieces->init = tlv_data;
1205 pieces->init_size = tlv_len;
1206 break;
1207 case IWL_UCODE_TLV_INIT_DATA:
1208 pieces->init_data = tlv_data;
1209 pieces->init_data_size = tlv_len;
1210 break;
1211 case IWL_UCODE_TLV_BOOT:
1fc35276 1212 IWL_ERR(priv, "Found unexpected BOOT ucode\n");
dd7a2509
JB		 1213 break;
1214 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1215 if (tlv_len != sizeof(u32))
1216 goto invalid_tlv_len;
1217 capa->max_probe_length =
ad8d8333 1218 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1219 break;
ece9c4ee
JB		 1220 case IWL_UCODE_TLV_PAN:
1221 if (tlv_len)
1222 goto invalid_tlv_len;
3997ff39
JB		 1223 capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1224 break;
1225 case IWL_UCODE_TLV_FLAGS:
1226 /* must be at least one u32 */
1227 if (tlv_len < sizeof(u32))
1228 goto invalid_tlv_len;
1229 /* and a proper number of u32s */
1230 if (tlv_len % sizeof(u32))
1231 goto invalid_tlv_len;
1232 /*
1233 * This driver only reads the first u32 as
1234 * right now no more features are defined,
1235 * if that changes then either the driver
1236 * will not work with the new firmware, or
1237 * it'll not take advantage of new features.
1238 */
1239 capa->flags = le32_to_cpup((__le32 *)tlv_data);
ece9c4ee 1240 break;
b2e640d4 1241 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1242 if (tlv_len != sizeof(u32))
1243 goto invalid_tlv_len;
1244 pieces->init_evtlog_ptr =
ad8d8333 1245 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1246 break;
1247 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 1248 if (tlv_len != sizeof(u32))
1249 goto invalid_tlv_len;
1250 pieces->init_evtlog_size =
ad8d8333 1251 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1252 break;
1253 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 1254 if (tlv_len != sizeof(u32))
1255 goto invalid_tlv_len;
1256 pieces->init_errlog_ptr =
ad8d8333 1257 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1258 break;
1259 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 1260 if (tlv_len != sizeof(u32))
1261 goto invalid_tlv_len;
1262 pieces->inst_evtlog_ptr =
ad8d8333 1263 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1264 break;
1265 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 1266 if (tlv_len != sizeof(u32))
1267 goto invalid_tlv_len;
1268 pieces->inst_evtlog_size =
ad8d8333 1269 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1270 break;
1271 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 1272 if (tlv_len != sizeof(u32))
1273 goto invalid_tlv_len;
1274 pieces->inst_errlog_ptr =
ad8d8333 1275 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 1276 break;
c8312fac
WYG		 1277 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1278 if (tlv_len)
704da534
JB		 1279 goto invalid_tlv_len;
1280 priv->enhance_sensitivity_table = true;
c8312fac 1281 break;
6a822d06 1282 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 1283 if (tlv_len != sizeof(u32))
1284 goto invalid_tlv_len;
1285 capa->standard_phy_calibration_size =
6a822d06
WYG		 1286 le32_to_cpup((__le32 *)tlv_data);
1287 break;
dd7a2509 1288 default:
6fc3ba99 1289 IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 1290 break;
1291 }
1292 }
1293
ad8d8333
WYG		 1294 if (len) {
1295 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1296 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 1297 return -EINVAL;
ad8d8333 1298 }
dd7a2509 1299
704da534
JB		 1300 return 0;
1301
1302 invalid_tlv_len:
1303 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1304 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1305
1306 return -EINVAL;
dd7a2509
JB		 1307}
1308
b481de9c 1309/**
b08dfd04 1310 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1311 *
b08dfd04
JB		 1312 * If loaded successfully, copies the firmware into buffers
1313 * for the card to fetch (via DMA).
b481de9c 1314 */
b08dfd04 1315static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1316{
b08dfd04 1317 struct iwl_priv *priv = context;
cc0f555d 1318 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 1319 int err;
1320 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 1321 const unsigned int api_max = priv->cfg->ucode_api_max;
1322 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 1323 u32 api_ver;
3e4de761 1324 char buildstr[25];
0e9a44dc 1325 u32 build;
dd7a2509
JB		 1326 struct iwlagn_ucode_capabilities ucode_capa = {
1327 .max_probe_length = 200,
6a822d06 1328 .standard_phy_calibration_size =
642454cc 1329 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 1330 };
0e9a44dc
JB		 1331
1332 memset(&pieces, 0, sizeof(pieces));
b481de9c 1333
b08dfd04 1334 if (!ucode_raw) {
39396085
JS		 1335 if (priv->fw_index <= priv->cfg->ucode_api_max)
1336 IWL_ERR(priv,
1337 "request for firmware file '%s' failed.\n",
1338 priv->firmware_name);
b08dfd04 1339 goto try_again;
b481de9c
ZY		 1340 }
1341
b08dfd04
JB		 1342 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1343 priv->firmware_name, ucode_raw->size);
b481de9c 1344
22adba2a
JB		 1345 /* Make sure that we got at least the API version number */
1346 if (ucode_raw->size < 4) {
15b1687c 1347 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1348 goto try_again;
b481de9c
ZY		 1349 }
1350
1351 /* Data from ucode file: header followed by uCode images */
cc0f555d 1352 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1353
0e9a44dc
JB		 1354 if (ucode->ver)
1355 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1356 else
dd7a2509
JB		 1357 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1358 &ucode_capa);
22adba2a 1359
0e9a44dc
JB		 1360 if (err)
1361 goto try_again;
b481de9c 1362
a0987a8d 1363 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 1364 build = pieces.build;
a0987a8d 1365
0e9a44dc
JB		 1366 /*
1367 * api_ver should match the api version forming part of the
1368 * firmware filename ... but we don't check for that and only rely
1369 * on the API version read from firmware header from here on forward
1370 */
65cccfb0
WYG		 1371 /* no api version check required for experimental uCode */
1372 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1373 if (api_ver < api_min || api_ver > api_max) {
1374 IWL_ERR(priv,
1375 "Driver unable to support your firmware API. "
1376 "Driver supports v%u, firmware is v%u.\n",
1377 api_max, api_ver);
1378 goto try_again;
1379 }
b08dfd04 1380
65cccfb0
WYG		 1381 if (api_ver != api_max)
1382 IWL_ERR(priv,
1383 "Firmware has old API version. Expected v%u, "
1384 "got v%u. New firmware can be obtained "
1385 "from http://www.intellinuxwireless.org.\n",
1386 api_max, api_ver);
1387 }
a0987a8d 1388
3e4de761 1389 if (build)
39396085
JS		 1390 sprintf(buildstr, " build %u%s", build,
1391 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1392 ? " (EXP)" : "");
3e4de761
JB		 1393 else
1394 buildstr[0] = '\0';
1395
1396 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1397 IWL_UCODE_MAJOR(priv->ucode_ver),
1398 IWL_UCODE_MINOR(priv->ucode_ver),
1399 IWL_UCODE_API(priv->ucode_ver),
1400 IWL_UCODE_SERIAL(priv->ucode_ver),
1401 buildstr);
a0987a8d 1402
5ebeb5a6
RC		 1403 snprintf(priv->hw->wiphy->fw_version,
1404 sizeof(priv->hw->wiphy->fw_version),
3e4de761 1405 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 1406 IWL_UCODE_MAJOR(priv->ucode_ver),
1407 IWL_UCODE_MINOR(priv->ucode_ver),
1408 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 1409 IWL_UCODE_SERIAL(priv->ucode_ver),
1410 buildstr);
b481de9c 1411
b08dfd04
JB		 1412 /*
1413 * For any of the failures below (before allocating pci memory)
1414 * we will try to load a version with a smaller API -- maybe the
1415 * user just got a corrupted version of the latest API.
1416 */
1417
0e9a44dc
JB		 1418 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1419 priv->ucode_ver);
1420 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1421 pieces.inst_size);
1422 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1423 pieces.data_size);
1424 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1425 pieces.init_size);
1426 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1427 pieces.init_data_size);
b481de9c
ZY		 1428
1429 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 1430 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1431 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1432 pieces.inst_size);
b08dfd04 1433 goto try_again;
b481de9c
ZY		 1434 }
1435
0e9a44dc
JB		 1436 if (pieces.data_size > priv->hw_params.max_data_size) {
1437 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1438 pieces.data_size);
b08dfd04 1439 goto try_again;
b481de9c 1440 }
0e9a44dc
JB		 1441
1442 if (pieces.init_size > priv->hw_params.max_inst_size) {
1443 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1444 pieces.init_size);
b08dfd04 1445 goto try_again;
b481de9c 1446 }
0e9a44dc
JB		 1447
1448 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1449 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1450 pieces.init_data_size);
b08dfd04 1451 goto try_again;
b481de9c 1452 }
0e9a44dc 1453
b481de9c
ZY		 1454 /* Allocate ucode buffers for card's bus-master loading ... */
1455
1456 /* Runtime instructions and 2 copies of data:
1457 * 1) unmodified from disk
1458 * 2) backup cache for save/restore during power-downs */
3599d39a 1459 if (iwl_alloc_fw_desc(priv, &priv->ucode_rt.code,
dbf28e21
JB		 1460 pieces.inst, pieces.inst_size))
1461 goto err_pci_alloc;
3599d39a 1462 if (iwl_alloc_fw_desc(priv, &priv->ucode_rt.data,
dbf28e21 1463 pieces.data, pieces.data_size))
1f304e4e
ZY		 1464 goto err_pci_alloc;
1465
b481de9c 1466 /* Initialization instructions and data */
0e9a44dc 1467 if (pieces.init_size && pieces.init_data_size) {
3599d39a 1468 if (iwl_alloc_fw_desc(priv, &priv->ucode_init.code,
dbf28e21
JB		 1469 pieces.init, pieces.init_size))
1470 goto err_pci_alloc;
3599d39a 1471 if (iwl_alloc_fw_desc(priv, &priv->ucode_init.data,
dbf28e21 1472 pieces.init_data, pieces.init_data_size))
90e759d1
TW		 1473 goto err_pci_alloc;
1474 }
b481de9c 1475
b2e640d4
JB		 1476 /* Now that we can no longer fail, copy information */
1477
1478 /*
1479 * The (size - 16) / 12 formula is based on the information recorded
1480 * for each event, which is of mode 1 (including timestamp) for all
1481 * new microcodes that include this information.
1482 */
1483 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1484 if (pieces.init_evtlog_size)
1485 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1486 else
7cb1b088
WYG		 1487 priv->_agn.init_evtlog_size =
1488 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 1489 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1490 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1491 if (pieces.inst_evtlog_size)
1492 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1493 else
7cb1b088
WYG		 1494 priv->_agn.inst_evtlog_size =
1495 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 1496 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1497
d2690c0d
JB		 1498 priv->new_scan_threshold_behaviour =
1499 !!(ucode_capa.flags & IWL_UCODE_TLV_FLAGS_NEWSCAN);
1500
b2ea345e
WYG		 1501 if ((priv->cfg->sku & EEPROM_SKU_CAP_IPAN_ENABLE) &&
1502 (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN)) {
ece9c4ee 1503 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
c10afb6e 1504 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
ece9c4ee
JB		 1505 } else
1506 priv->sta_key_max_num = STA_KEY_MAX_NUM;
c10afb6e 1507
17445b8c
JB		 1508 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1509 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1510 else
1511 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1512
6a822d06
WYG		 1513 /*
1514 * figure out the offset of chain noise reset and gain commands
1515 * base on the size of standard phy calibration commands table size
1516 */
1517 if (ucode_capa.standard_phy_calibration_size >
1518 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1519 ucode_capa.standard_phy_calibration_size =
1520 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1521
1522 priv->_agn.phy_calib_chain_noise_reset_cmd =
1523 ucode_capa.standard_phy_calibration_size;
1524 priv->_agn.phy_calib_chain_noise_gain_cmd =
1525 ucode_capa.standard_phy_calibration_size + 1;
1526
b08dfd04
JB		 1527 /**************************************************
1528 * This is still part of probe() in a sense...
1529 *
1530 * 9. Setup and register with mac80211 and debugfs
1531 **************************************************/
dd7a2509 1532 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 1533 if (err)
1534 goto out_unbind;
1535
1536 err = iwl_dbgfs_register(priv, DRV_NAME);
1537 if (err)
1538 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1539
3599d39a 1540 err = sysfs_create_group(&(priv->bus.dev->kobj),
7d47618a
EG		 1541 &iwl_attribute_group);
1542 if (err) {
1543 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1544 goto out_unbind;
1545 }
1546
b481de9c
ZY		 1547 /* We have our copies now, allow OS release its copies */
1548 release_firmware(ucode_raw);
a15707d8 1549 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 1550 return;
1551
1552 try_again:
1553 /* try next, if any */
1554 if (iwl_request_firmware(priv, false))
1555 goto out_unbind;
1556 release_firmware(ucode_raw);
1557 return;
b481de9c
ZY		 1558
1559 err_pci_alloc:
15b1687c 1560 IWL_ERR(priv, "failed to allocate pci memory\n");
3599d39a 1561 iwl_dealloc_ucode(priv);
b08dfd04 1562 out_unbind:
a15707d8 1563 complete(&priv->_agn.firmware_loading_complete);
3599d39a 1564 device_release_driver(priv->bus.dev);
b481de9c 1565 release_firmware(ucode_raw);
b481de9c
ZY		 1566}
1567
2a897d41 1568static const char * const desc_lookup_text[] = {
b7a79404
RC		 1569 "OK",
1570 "FAIL",
1571 "BAD_PARAM",
1572 "BAD_CHECKSUM",
1573 "NMI_INTERRUPT_WDG",
1574 "SYSASSERT",
1575 "FATAL_ERROR",
1576 "BAD_COMMAND",
1577 "HW_ERROR_TUNE_LOCK",
1578 "HW_ERROR_TEMPERATURE",
1579 "ILLEGAL_CHAN_FREQ",
1580 "VCC_NOT_STABLE",
1581 "FH_ERROR",
1582 "NMI_INTERRUPT_HOST",
1583 "NMI_INTERRUPT_ACTION_PT",
1584 "NMI_INTERRUPT_UNKNOWN",
1585 "UCODE_VERSION_MISMATCH",
1586 "HW_ERROR_ABS_LOCK",
1587 "HW_ERROR_CAL_LOCK_FAIL",
1588 "NMI_INTERRUPT_INST_ACTION_PT",
1589 "NMI_INTERRUPT_DATA_ACTION_PT",
1590 "NMI_TRM_HW_ER",
1591 "NMI_INTERRUPT_TRM",
2a897d41 1592 "NMI_INTERRUPT_BREAK_POINT",
b7a79404
RC		 1593 "DEBUG_0",
1594 "DEBUG_1",
1595 "DEBUG_2",
1596 "DEBUG_3",
b7a79404
RC		 1597};
1598
4b58645c
JS		 1599static struct { char *name; u8 num; } advanced_lookup[] = {
1600 { "NMI_INTERRUPT_WDG", 0x34 },
1601 { "SYSASSERT", 0x35 },
1602 { "UCODE_VERSION_MISMATCH", 0x37 },
1603 { "BAD_COMMAND", 0x38 },
1604 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1605 { "FATAL_ERROR", 0x3D },
1606 { "NMI_TRM_HW_ERR", 0x46 },
1607 { "NMI_INTERRUPT_TRM", 0x4C },
1608 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1609 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1610 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1611 { "NMI_INTERRUPT_HOST", 0x66 },
1612 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1613 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1614 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1615 { "ADVANCED_SYSASSERT", 0 },
1616};
1617
1618static const char *desc_lookup(u32 num)
b7a79404 1619{
4b58645c
JS		 1620 int i;
1621 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 1622
4b58645c
JS		 1623 if (num < max)
1624 return desc_lookup_text[num];
b7a79404 1625
4b58645c
JS		 1626 max = ARRAY_SIZE(advanced_lookup) - 1;
1627 for (i = 0; i < max; i++) {
1628 if (advanced_lookup[i].num == num)
6eab04a8 1629 break;
4b58645c
JS		 1630 }
1631 return advanced_lookup[i].name;
b7a79404
RC		 1632}
1633
1634#define ERROR_START_OFFSET (1 * sizeof(u32))
1635#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1636
1637void iwl_dump_nic_error_log(struct iwl_priv *priv)
1638{
50650547 1639 u32 base;
e46f6538 1640 struct iwl_error_event_table table;
b7a79404 1641
d7d5783c 1642 base = priv->device_pointers.error_event_table;
872907bb 1643 if (priv->ucode_type == IWL_UCODE_INIT) {
b2e640d4
JB		 1644 if (!base)
1645 base = priv->_agn.init_errlog_ptr;
1646 } else {
b2e640d4
JB		 1647 if (!base)
1648 base = priv->_agn.inst_errlog_ptr;
1649 }
b7a79404
RC		 1650
1651 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 1652 IWL_ERR(priv,
1653 "Not valid error log pointer 0x%08X for %s uCode\n",
ca7966c8 1654 base,
872907bb 1655 (priv->ucode_type == IWL_UCODE_INIT)
ca7966c8 1656 ? "Init" : "RT");
b7a79404
RC		 1657 return;
1658 }
1659
e46f6538
JB		 1660 iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
1661
50650547 1662 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
b7a79404
RC		 1663 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1664 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
50650547 1665 priv->status, table.valid);
b7a79404
RC		 1666 }
1667
50650547
WYG		 1668 priv->isr_stats.err_code = table.error_id;
1669
1670 trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
1671 table.data1, table.data2, table.line,
1672 table.blink1, table.blink2, table.ilink1,
1673 table.ilink2, table.bcon_time, table.gp1,
1674 table.gp2, table.gp3, table.ucode_ver,
1675 table.hw_ver, table.brd_ver);
1676 IWL_ERR(priv, "0x%08X | %-28s\n", table.error_id,
1677 desc_lookup(table.error_id));
1678 IWL_ERR(priv, "0x%08X | uPc\n", table.pc);
1679 IWL_ERR(priv, "0x%08X | branchlink1\n", table.blink1);
1680 IWL_ERR(priv, "0x%08X | branchlink2\n", table.blink2);
1681 IWL_ERR(priv, "0x%08X | interruptlink1\n", table.ilink1);
1682 IWL_ERR(priv, "0x%08X | interruptlink2\n", table.ilink2);
1683 IWL_ERR(priv, "0x%08X | data1\n", table.data1);
1684 IWL_ERR(priv, "0x%08X | data2\n", table.data2);
1685 IWL_ERR(priv, "0x%08X | line\n", table.line);
1686 IWL_ERR(priv, "0x%08X | beacon time\n", table.bcon_time);
1687 IWL_ERR(priv, "0x%08X | tsf low\n", table.tsf_low);
1688 IWL_ERR(priv, "0x%08X | tsf hi\n", table.tsf_hi);
1689 IWL_ERR(priv, "0x%08X | time gp1\n", table.gp1);
1690 IWL_ERR(priv, "0x%08X | time gp2\n", table.gp2);
1691 IWL_ERR(priv, "0x%08X | time gp3\n", table.gp3);
1692 IWL_ERR(priv, "0x%08X | uCode version\n", table.ucode_ver);
1693 IWL_ERR(priv, "0x%08X | hw version\n", table.hw_ver);
1694 IWL_ERR(priv, "0x%08X | board version\n", table.brd_ver);
1695 IWL_ERR(priv, "0x%08X | hcmd\n", table.hcmd);
b7a79404
RC		 1696}
1697
1698#define EVENT_START_OFFSET (4 * sizeof(u32))
1699
1700/**
1701 * iwl_print_event_log - Dump error event log to syslog
1702 *
1703 */
b03d7d0f
WYG		 1704static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1705 u32 num_events, u32 mode,
1706 int pos, char **buf, size_t bufsz)
b7a79404
RC		 1707{
1708 u32 i;
1709 u32 base; /* SRAM byte address of event log header */
1710 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1711 u32 ptr; /* SRAM byte address of log data */
1712 u32 ev, time, data; /* event log data */
e5854471 1713 unsigned long reg_flags;
b7a79404
RC		 1714
1715 if (num_events == 0)
b03d7d0f 1716 return pos;
b2e640d4 1717
d7d5783c 1718 base = priv->device_pointers.log_event_table;
872907bb 1719 if (priv->ucode_type == IWL_UCODE_INIT) {
b2e640d4
JB		 1720 if (!base)
1721 base = priv->_agn.init_evtlog_ptr;
1722 } else {
b2e640d4
JB		 1723 if (!base)
1724 base = priv->_agn.inst_evtlog_ptr;
1725 }
b7a79404
RC		 1726
1727 if (mode == 0)
1728 event_size = 2 * sizeof(u32);
1729 else
1730 event_size = 3 * sizeof(u32);
1731
1732 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1733
e5854471
BC		 1734 /* Make sure device is powered up for SRAM reads */
1735 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1736 iwl_grab_nic_access(priv);
1737
1738 /* Set starting address; reads will auto-increment */
02a7fa00 1739 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
e5854471
BC		 1740 rmb();
1741
b7a79404
RC		 1742 /* "time" is actually "data" for mode 0 (no timestamp).
1743 * place event id # at far right for easier visual parsing. */
1744 for (i = 0; i < num_events; i++) {
02a7fa00
JB		 1745 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1746 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 1747 if (mode == 0) {
1748 /* data, ev */
b03d7d0f
WYG		 1749 if (bufsz) {
1750 pos += scnprintf(*buf + pos, bufsz - pos,
1751 "EVT_LOG:0x%08x:%04u\n",
1752 time, ev);
1753 } else {
1754 trace_iwlwifi_dev_ucode_event(priv, 0,
1755 time, ev);
1756 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1757 time, ev);
1758 }
b7a79404 1759 } else {
02a7fa00 1760 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 1761 if (bufsz) {
1762 pos += scnprintf(*buf + pos, bufsz - pos,
1763 "EVT_LOGT:%010u:0x%08x:%04u\n",
1764 time, data, ev);
1765 } else {
1766 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 1767 time, data, ev);
b03d7d0f
WYG		 1768 trace_iwlwifi_dev_ucode_event(priv, time,
1769 data, ev);
1770 }
b7a79404
RC		 1771 }
1772 }
e5854471
BC		 1773
1774 /* Allow device to power down */
1775 iwl_release_nic_access(priv);
1776 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1777 return pos;
b7a79404
RC		 1778}
1779
c341ddb2
WYG		 1780/**
1781 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1782 */
b03d7d0f
WYG		 1783static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1784 u32 num_wraps, u32 next_entry,
1785 u32 size, u32 mode,
1786 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 1787{
1788 /*
1789 * display the newest DEFAULT_LOG_ENTRIES entries
1790 * i.e the entries just before the next ont that uCode would fill.
1791 */
1792 if (num_wraps) {
1793 if (next_entry < size) {
b03d7d0f
WYG		 1794 pos = iwl_print_event_log(priv,
1795 capacity - (size - next_entry),
1796 size - next_entry, mode,
1797 pos, buf, bufsz);
1798 pos = iwl_print_event_log(priv, 0,
1799 next_entry, mode,
1800 pos, buf, bufsz);
c341ddb2 1801 } else
b03d7d0f
WYG		 1802 pos = iwl_print_event_log(priv, next_entry - size,
1803 size, mode, pos, buf, bufsz);
c341ddb2 1804 } else {
b03d7d0f
WYG		 1805 if (next_entry < size) {
1806 pos = iwl_print_event_log(priv, 0, next_entry,
1807 mode, pos, buf, bufsz);
1808 } else {
1809 pos = iwl_print_event_log(priv, next_entry - size,
1810 size, mode, pos, buf, bufsz);
1811 }
c341ddb2 1812 }
b03d7d0f 1813 return pos;
c341ddb2
WYG		 1814}
1815
c341ddb2
WYG		 1816#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
1817
b03d7d0f
WYG		 1818int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1819 char **buf, bool display)
b7a79404
RC		 1820{
1821 u32 base; /* SRAM byte address of event log header */
1822 u32 capacity; /* event log capacity in # entries */
1823 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1824 u32 num_wraps; /* # times uCode wrapped to top of log */
1825 u32 next_entry; /* index of next entry to be written by uCode */
1826 u32 size; /* # entries that we'll print */
b2e640d4 1827 u32 logsize;
b03d7d0f
WYG		 1828 int pos = 0;
1829 size_t bufsz = 0;
b7a79404 1830
d7d5783c 1831 base = priv->device_pointers.log_event_table;
872907bb 1832 if (priv->ucode_type == IWL_UCODE_INIT) {
b2e640d4
JB		 1833 logsize = priv->_agn.init_evtlog_size;
1834 if (!base)
1835 base = priv->_agn.init_evtlog_ptr;
1836 } else {
b2e640d4
JB		 1837 logsize = priv->_agn.inst_evtlog_size;
1838 if (!base)
1839 base = priv->_agn.inst_evtlog_ptr;
1840 }
b7a79404
RC		 1841
1842 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 1843 IWL_ERR(priv,
1844 "Invalid event log pointer 0x%08X for %s uCode\n",
ca7966c8 1845 base,
872907bb 1846 (priv->ucode_type == IWL_UCODE_INIT)
ca7966c8 1847 ? "Init" : "RT");
937c397e 1848 return -EINVAL;
b7a79404
RC		 1849 }
1850
1851 /* event log header */
1852 capacity = iwl_read_targ_mem(priv, base);
1853 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1854 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1855 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1856
b2e640d4 1857 if (capacity > logsize) {
84c40692 1858 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 1859 capacity, logsize);
1860 capacity = logsize;
84c40692
BC		 1861 }
1862
b2e640d4 1863 if (next_entry > logsize) {
84c40692 1864 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 1865 next_entry, logsize);
1866 next_entry = logsize;
84c40692
BC		 1867 }
1868
b7a79404
RC		 1869 size = num_wraps ? capacity : next_entry;
1870
1871 /* bail out if nothing in log */
1872 if (size == 0) {
1873 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 1874 return pos;
b7a79404
RC		 1875 }
1876
9f28ebc3 1877 /* enable/disable bt channel inhibition */
f37837c9
WYG		 1878 priv->bt_ch_announce = iwlagn_bt_ch_announce;
1879
c341ddb2 1880#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 1881 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 1882 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1883 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1884#else
1885 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1886 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1887#endif
1888 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
1889 size);
b7a79404 1890
c341ddb2 1891#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 1892 if (display) {
1893 if (full_log)
1894 bufsz = capacity * 48;
1895 else
1896 bufsz = size * 48;
1897 *buf = kmalloc(bufsz, GFP_KERNEL);
1898 if (!*buf)
937c397e 1899 return -ENOMEM;
b03d7d0f 1900 }
c341ddb2
WYG		 1901 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1902 /*
1903 * if uCode has wrapped back to top of log,
1904 * start at the oldest entry,
1905 * i.e the next one that uCode would fill.
1906 */
1907 if (num_wraps)
b03d7d0f
WYG		 1908 pos = iwl_print_event_log(priv, next_entry,
1909 capacity - next_entry, mode,
1910 pos, buf, bufsz);
c341ddb2 1911 /* (then/else) start at top of log */
b03d7d0f
WYG		 1912 pos = iwl_print_event_log(priv, 0,
1913 next_entry, mode, pos, buf, bufsz);
c341ddb2 1914 } else
b03d7d0f
WYG		 1915 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
1916 next_entry, size, mode,
1917 pos, buf, bufsz);
c341ddb2 1918#else
b03d7d0f
WYG		 1919 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
1920 next_entry, size, mode,
1921 pos, buf, bufsz);
b7a79404 1922#endif
b03d7d0f 1923 return pos;
c341ddb2 1924}
b7a79404 1925
0975cc8f
WYG		 1926static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1927{
1928 struct iwl_ct_kill_config cmd;
1929 struct iwl_ct_kill_throttling_config adv_cmd;
1930 unsigned long flags;
1931 int ret = 0;
1932
1933 spin_lock_irqsave(&priv->lock, flags);
1934 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1935 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1936 spin_unlock_irqrestore(&priv->lock, flags);
1937 priv->thermal_throttle.ct_kill_toggle = false;
1938
7cb1b088 1939 if (priv->cfg->base_params->support_ct_kill_exit) {
0975cc8f
WYG		 1940 adv_cmd.critical_temperature_enter =
1941 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1942 adv_cmd.critical_temperature_exit =
1943 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
1944
bdfbf092 1945 ret = trans_send_cmd_pdu(priv,
e419d62d
EG		 1946 REPLY_CT_KILL_CONFIG_CMD,
1947 CMD_SYNC, sizeof(adv_cmd), &adv_cmd);
0975cc8f
WYG		 1948 if (ret)
1949 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
1950 else
1951 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
1952 "succeeded, "
1953 "critical temperature enter is %d,"
1954 "exit is %d\n",
1955 priv->hw_params.ct_kill_threshold,
1956 priv->hw_params.ct_kill_exit_threshold);
1957 } else {
1958 cmd.critical_temperature_R =
1959 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1960
bdfbf092 1961 ret = trans_send_cmd_pdu(priv,
e419d62d
EG		 1962 REPLY_CT_KILL_CONFIG_CMD,
1963 CMD_SYNC, sizeof(cmd), &cmd);
0975cc8f
WYG		 1964 if (ret)
1965 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
1966 else
1967 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
1968 "succeeded, "
1969 "critical temperature is %d\n",
1970 priv->hw_params.ct_kill_threshold);
1971 }
1972}
1973
6d6a1afd
SZ		 1974static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
1975{
1976 struct iwl_calib_cfg_cmd calib_cfg_cmd;
1977 struct iwl_host_cmd cmd = {
1978 .id = CALIBRATION_CFG_CMD,
3fa50738
JB		 1979 .len = { sizeof(struct iwl_calib_cfg_cmd), },
1980 .data = { &calib_cfg_cmd, },
6d6a1afd
SZ		 1981 };
1982
1983 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
1984 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
7cb1b088 1985 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
6d6a1afd 1986
bdfbf092 1987 return trans_send_cmd(priv, &cmd);
6d6a1afd
SZ		 1988}
1989
1990
b481de9c 1991/**
4a4a9e81 1992 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1993 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1994 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1995 */
4613e72d 1996int iwl_alive_start(struct iwl_priv *priv)
b481de9c 1997{
57aab75a 1998 int ret = 0;
246ed355 1999 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 2000
ca7966c8 2001 iwl_reset_ict(priv);
b481de9c 2002
ca7966c8 2003 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
6d6a1afd 2004
5b9f8cd3 2005 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2006 set_bit(STATUS_ALIVE, &priv->status);
2007
22de94de
SG		 2008 /* Enable watchdog to monitor the driver tx queues */
2009 iwl_setup_watchdog(priv);
b74e31a9 2010
fee1247a 2011 if (iwl_is_rfkill(priv))
ca7966c8 2012 return -ERFKILL;
b481de9c 2013
bc795df1 2014 /* download priority table before any calibration request */
7cb1b088
WYG		 2015 if (priv->cfg->bt_params &&
2016 priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f 2017 /* Configure Bluetooth device coexistence support */
207ecc5e
MV		 2018 if (priv->cfg->bt_params->bt_sco_disable)
2019 priv->bt_enable_pspoll = false;
2020 else
2021 priv->bt_enable_pspoll = true;
2022
f7322f8f
WYG		 2023 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2024 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2025 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
e55b517c 2026 iwlagn_send_advance_bt_config(priv);
f7322f8f 2027 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
207ecc5e
MV		 2028 priv->cur_rssi_ctx = NULL;
2029
a5901cbb 2030 iwlagn_send_prio_tbl(priv);
f7322f8f
WYG		 2031
2032 /* FIXME: w/a to force change uCode BT state machine */
ca7966c8
JB		 2033 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2034 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2035 if (ret)
2036 return ret;
2037 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2038 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2039 if (ret)
2040 return ret;
e55b517c
WYG		 2041 } else {
2042 /*
2043 * default is 2-wire BT coexexistence support
2044 */
2045 iwl_send_bt_config(priv);
f7322f8f 2046 }
e55b517c 2047
bc795df1
WYG		 2048 if (priv->hw_params.calib_rt_cfg)
2049 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2050
36d6825b 2051 ieee80211_wake_queues(priv->hw);
b481de9c 2052
470ab2dd 2053 priv->active_rate = IWL_RATES_MASK;
b481de9c 2054
2f748dec 2055 /* Configure Tx antenna selection based on H/W config */
e3f10cea 2056 iwlagn_send_tx_ant_config(priv, priv->cfg->valid_tx_ant);
2f748dec 2057
246ed355 2058 if (iwl_is_associated_ctx(ctx)) {
c1adf9fb 2059 struct iwl_rxon_cmd *active_rxon =
246ed355 2060 (struct iwl_rxon_cmd *)&ctx->active;
019fb97d 2061 /* apply any changes in staging */
246ed355 2062 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2063 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2064 } else {
d0fe478c 2065 struct iwl_rxon_context *tmp;
b481de9c 2066 /* Initialize our rx_config data */
d0fe478c
JB		 2067 for_each_context(priv, tmp)
2068 iwl_connection_init_rx_config(priv, tmp);
45823531 2069
e3f10cea 2070 iwlagn_set_rxon_chain(priv, ctx);
b481de9c
ZY		 2071 }
2072
4a4a9e81
TW		 2073 iwl_reset_run_time_calib(priv);
2074
9e2e7422
WYG		 2075 set_bit(STATUS_READY, &priv->status);
2076
b481de9c 2077 /* Configure the adapter for unassociated operation */
805a3b81 2078 ret = iwlagn_commit_rxon(priv, ctx);
ca7966c8
JB		 2079 if (ret)
2080 return ret;
b481de9c
ZY		 2081
2082 /* At this point, the NIC is initialized and operational */
47f4a587 2083 iwl_rf_kill_ct_config(priv);
5a66926a 2084
e1623446 2085 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
c46fbefa 2086
ca7966c8 2087 return iwl_power_update_mode(priv, true);
b481de9c
ZY		 2088}
2089
4e39317d 2090static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2091
5b9f8cd3 2092static void __iwl_down(struct iwl_priv *priv)
b481de9c 2093{
22dd2fd2 2094 int exit_pending;
b481de9c 2095
e1623446 2096 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2097
d745d472
SG		 2098 iwl_scan_cancel_timeout(priv, 200);
2099
2100 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2101
b62177a0
SG		 2102 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2103 * to prevent rearm timer */
22de94de 2104 del_timer_sync(&priv->watchdog);
b62177a0 2105
dcef732c 2106 iwl_clear_ucode_stations(priv, NULL);
a194e324 2107 iwl_dealloc_bcast_stations(priv);
db125c78 2108 iwl_clear_driver_stations(priv);
b481de9c 2109
a1174138 2110 /* reset BT coex data */
da5dbb97 2111 priv->bt_status = 0;
207ecc5e
MV		 2112 priv->cur_rssi_ctx = NULL;
2113 priv->bt_is_sco = 0;
7cb1b088
WYG		 2114 if (priv->cfg->bt_params)
2115 priv->bt_traffic_load =
2116 priv->cfg->bt_params->bt_init_traffic_load;
2117 else
2118 priv->bt_traffic_load = 0;
bee008b7
WYG		 2119 priv->bt_full_concurrent = false;
2120 priv->bt_ci_compliance = 0;
a1174138 2121
b481de9c
ZY		 2122 /* Wipe out the EXIT_PENDING status bit if we are not actually
2123 * exiting the module */
2124 if (!exit_pending)
2125 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2126
b481de9c
ZY		 2127 if (priv->mac80211_registered)
2128 ieee80211_stop_queues(priv->hw);
2129
1a10f433 2130 /* Clear out all status bits but a few that are stable across reset */
b481de9c
ZY		 2131 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2132 STATUS_RF_KILL_HW |
9788864e
RC		 2133 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2134 STATUS_GEO_CONFIGURED |
b481de9c 2135 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2136 STATUS_FW_ERROR |
2137 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2138 STATUS_EXIT_PENDING;
b481de9c 2139
bc4f8ada 2140 iwlagn_stop_device(priv);
4d2ccdb9 2141
77834543 2142 dev_kfree_skb(priv->beacon_skb);
12e934dc 2143 priv->beacon_skb = NULL;
b481de9c
ZY		 2144}
2145
5b9f8cd3 2146static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2147{
2148 mutex_lock(&priv->mutex);
5b9f8cd3 2149 __iwl_down(priv);
b481de9c 2150 mutex_unlock(&priv->mutex);
b24d22b1 2151
4e39317d 2152 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 2153}
2154
086ed117
MA		 2155#define HW_READY_TIMEOUT (50)
2156
4cd2bf76 2157/* Note: returns poll_bit return value, which is >= 0 if success */
086ed117
MA		 2158static int iwl_set_hw_ready(struct iwl_priv *priv)
2159{
4cd2bf76 2160 int ret;
086ed117
MA		 2161
2162 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2163 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2164
2165 /* See if we got it */
2166 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2167 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2168 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2169 HW_READY_TIMEOUT);
086ed117 2170
4cd2bf76 2171 IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
086ed117
MA		 2172 return ret;
2173}
2174
4cd2bf76 2175/* Note: returns standard 0/-ERROR code */
3e14c1fd 2176int iwl_prepare_card_hw(struct iwl_priv *priv)
086ed117 2177{
4cd2bf76 2178 int ret;
086ed117 2179
91dd6c27 2180 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2181
3354a0f6 2182 ret = iwl_set_hw_ready(priv);
4cd2bf76
JB		 2183 if (ret >= 0)
2184 return 0;
3354a0f6
MA		 2185
2186 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 2187 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2188 CSR_HW_IF_CONFIG_REG_PREPARE);
2189
2190 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2191 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2192 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2193
4cd2bf76
JB		 2194 if (ret < 0)
2195 return ret;
086ed117 2196
4cd2bf76
JB		 2197 /* HW should be ready by now, check again. */
2198 ret = iwl_set_hw_ready(priv);
2199 if (ret >= 0)
2200 return 0;
086ed117
MA		 2201 return ret;
2202}
2203
b481de9c
ZY		 2204#define MAX_HW_RESTARTS 5
2205
5b9f8cd3 2206static int __iwl_up(struct iwl_priv *priv)
b481de9c 2207{
a194e324 2208 struct iwl_rxon_context *ctx;
57aab75a 2209 int ret;
b481de9c 2210
ca7966c8
JB		 2211 lockdep_assert_held(&priv->mutex);
2212
b481de9c 2213 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2214 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 2215 return -EIO;
2216 }
2217
a194e324 2218 for_each_context(priv, ctx) {
a30e3112 2219 ret = iwlagn_alloc_bcast_station(priv, ctx);
a194e324
JB		 2220 if (ret) {
2221 iwl_dealloc_bcast_stations(priv);
2222 return ret;
2223 }
2224 }
2c810ccd 2225
ca7966c8
JB		 2226 ret = iwlagn_run_init_ucode(priv);
2227 if (ret) {
2228 IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret);
2229 goto error;
2230 }
b481de9c 2231
ca7966c8 2232 ret = iwlagn_load_ucode_wait_alive(priv,
dbf28e21 2233 &priv->ucode_rt,
872907bb 2234 IWL_UCODE_REGULAR);
ca7966c8
JB		 2235 if (ret) {
2236 IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
2237 goto error;
b481de9c
ZY		 2238 }
2239
ca7966c8
JB		 2240 ret = iwl_alive_start(priv);
2241 if (ret)
2242 goto error;
2243 return 0;
2244
2245 error:
b481de9c 2246 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2247 __iwl_down(priv);
64e72c3e 2248 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2249
ca7966c8
JB		 2250 IWL_ERR(priv, "Unable to initialize device.\n");
2251 return ret;
b481de9c
ZY		 2252}
2253
2254
2255/*****************************************************************************
2256 *
2257 * Workqueue callbacks
2258 *
2259 *****************************************************************************/
2260
16e727e8
EG		 2261static void iwl_bg_run_time_calib_work(struct work_struct *work)
2262{
2263 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2264 run_time_calib_work);
2265
2266 mutex_lock(&priv->mutex);
2267
2268 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2269 test_bit(STATUS_SCANNING, &priv->status)) {
2270 mutex_unlock(&priv->mutex);
2271 return;
2272 }
2273
2274 if (priv->start_calib) {
0da0e5bf
JB		 2275 iwl_chain_noise_calibration(priv);
2276 iwl_sensitivity_calibration(priv);
16e727e8
EG		 2277 }
2278
2279 mutex_unlock(&priv->mutex);
16e727e8
EG		 2280}
2281
e43e85c4
JB		 2282static void iwlagn_prepare_restart(struct iwl_priv *priv)
2283{
2284 struct iwl_rxon_context *ctx;
2285 bool bt_full_concurrent;
2286 u8 bt_ci_compliance;
2287 u8 bt_load;
2288 u8 bt_status;
207ecc5e 2289 bool bt_is_sco;
e43e85c4
JB		 2290
2291 lockdep_assert_held(&priv->mutex);
2292
2293 for_each_context(priv, ctx)
2294 ctx->vif = NULL;
2295 priv->is_open = 0;
2296
2297 /*
2298 * __iwl_down() will clear the BT status variables,
2299 * which is correct, but when we restart we really
2300 * want to keep them so restore them afterwards.
2301 *
2302 * The restart process will later pick them up and
2303 * re-configure the hw when we reconfigure the BT
2304 * command.
2305 */
2306 bt_full_concurrent = priv->bt_full_concurrent;
2307 bt_ci_compliance = priv->bt_ci_compliance;
2308 bt_load = priv->bt_traffic_load;
2309 bt_status = priv->bt_status;
207ecc5e 2310 bt_is_sco = priv->bt_is_sco;
e43e85c4
JB		 2311
2312 __iwl_down(priv);
2313
2314 priv->bt_full_concurrent = bt_full_concurrent;
2315 priv->bt_ci_compliance = bt_ci_compliance;
2316 priv->bt_traffic_load = bt_load;
2317 priv->bt_status = bt_status;
207ecc5e 2318 priv->bt_is_sco = bt_is_sco;
e43e85c4
JB		 2319}
2320
5b9f8cd3 2321static void iwl_bg_restart(struct work_struct *data)
b481de9c 2322{
c79dd5b5 2323 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 2324
2325 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2326 return;
2327
19cc1087
JB		 2328 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2329 mutex_lock(&priv->mutex);
e43e85c4 2330 iwlagn_prepare_restart(priv);
19cc1087 2331 mutex_unlock(&priv->mutex);
a1174138 2332 iwl_cancel_deferred_work(priv);
19cc1087
JB		 2333 ieee80211_restart_hw(priv->hw);
2334 } else {
ca7966c8 2335 WARN_ON(1);
19cc1087 2336 }
b481de9c
ZY		 2337}
2338
5b9f8cd3 2339static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2340{
c79dd5b5
TW		 2341 struct iwl_priv *priv =
2342 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 2343
2344 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2345 return;
2346
2347 mutex_lock(&priv->mutex);
54b81550 2348 iwlagn_rx_replenish(priv);
b481de9c
ZY		 2349 mutex_unlock(&priv->mutex);
2350}
2351
266af4c7
JB		 2352static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2353 struct ieee80211_channel *chan,
2354 enum nl80211_channel_type channel_type,
2355 unsigned int wait)
2356{
2357 struct iwl_priv *priv = hw->priv;
2358 int ret;
2359
2360 /* Not supported if we don't have PAN */
2361 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2362 ret = -EOPNOTSUPP;
2363 goto free;
2364 }
2365
2366 /* Not supported on pre-P2P firmware */
2367 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2368 BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2369 ret = -EOPNOTSUPP;
2370 goto free;
2371 }
2372
2373 mutex_lock(&priv->mutex);
2374
2375 if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2376 /*
2377 * If the PAN context is free, use the normal
2378 * way of doing remain-on-channel offload + TX.
2379 */
2380 ret = 1;
2381 goto out;
2382 }
2383
2384 /* TODO: queue up if scanning? */
2385 if (test_bit(STATUS_SCANNING, &priv->status) ||
2386 priv->_agn.offchan_tx_skb) {
2387 ret = -EBUSY;
2388 goto out;
2389 }
2390
2391 /*
2392 * max_scan_ie_len doesn't include the blank SSID or the header,
2393 * so need to add that again here.
2394 */
2395 if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2396 ret = -ENOBUFS;
2397 goto out;
2398 }
2399
2400 priv->_agn.offchan_tx_skb = skb;
2401 priv->_agn.offchan_tx_timeout = wait;
2402 priv->_agn.offchan_tx_chan = chan;
2403
2404 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2405 IWL_SCAN_OFFCH_TX, chan->band);
2406 if (ret)
2407 priv->_agn.offchan_tx_skb = NULL;
2408 out:
2409 mutex_unlock(&priv->mutex);
2410 free:
2411 if (ret < 0)
2412 kfree_skb(skb);
2413
2414 return ret;
2415}
2416
2417static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2418{
2419 struct iwl_priv *priv = hw->priv;
2420 int ret;
2421
2422 mutex_lock(&priv->mutex);
2423
f8a22a2b
DC		 2424 if (!priv->_agn.offchan_tx_skb) {
2425 ret = -EINVAL;
2426 goto unlock;
2427 }
266af4c7
JB		 2428
2429 priv->_agn.offchan_tx_skb = NULL;
2430
2431 ret = iwl_scan_cancel_timeout(priv, 200);
2432 if (ret)
2433 ret = -EIO;
f8a22a2b 2434unlock:
266af4c7
JB		 2435 mutex_unlock(&priv->mutex);
2436
2437 return ret;
2438}
2439
b481de9c
ZY		 2440/*****************************************************************************
2441 *
2442 * mac80211 entry point functions
2443 *
2444 *****************************************************************************/
2445
0fd09502
JB		 2446static const struct ieee80211_iface_limit iwlagn_sta_ap_limits[] = {
2447 {
2448 .max = 1,
2449 .types = BIT(NL80211_IFTYPE_STATION),
2450 },
2451 {
2452 .max = 1,
2453 .types = BIT(NL80211_IFTYPE_AP),
2454 },
2455};
2456
2457static const struct ieee80211_iface_limit iwlagn_2sta_limits[] = {
2458 {
2459 .max = 2,
2460 .types = BIT(NL80211_IFTYPE_STATION),
2461 },
2462};
2463
2464static const struct ieee80211_iface_limit iwlagn_p2p_sta_go_limits[] = {
2465 {
2466 .max = 1,
2467 .types = BIT(NL80211_IFTYPE_STATION),
2468 },
2469 {
2470 .max = 1,
2471 .types = BIT(NL80211_IFTYPE_P2P_GO) |
2472 BIT(NL80211_IFTYPE_AP),
2473 },
2474};
2475
2476static const struct ieee80211_iface_limit iwlagn_p2p_2sta_limits[] = {
2477 {
2478 .max = 2,
2479 .types = BIT(NL80211_IFTYPE_STATION),
2480 },
2481 {
2482 .max = 1,
2483 .types = BIT(NL80211_IFTYPE_P2P_CLIENT),
2484 },
2485};
2486
2487static const struct ieee80211_iface_combination
2488iwlagn_iface_combinations_dualmode[] = {
2489 { .num_different_channels = 1,
2490 .max_interfaces = 2,
2491 .beacon_int_infra_match = true,
2492 .limits = iwlagn_sta_ap_limits,
2493 .n_limits = ARRAY_SIZE(iwlagn_sta_ap_limits),
2494 },
2495 { .num_different_channels = 1,
2496 .max_interfaces = 2,
2497 .limits = iwlagn_2sta_limits,
2498 .n_limits = ARRAY_SIZE(iwlagn_2sta_limits),
2499 },
2500};
2501
2502static const struct ieee80211_iface_combination
2503iwlagn_iface_combinations_p2p[] = {
2504 { .num_different_channels = 1,
2505 .max_interfaces = 2,
2506 .beacon_int_infra_match = true,
2507 .limits = iwlagn_p2p_sta_go_limits,
2508 .n_limits = ARRAY_SIZE(iwlagn_p2p_sta_go_limits),
2509 },
2510 { .num_different_channels = 1,
2511 .max_interfaces = 2,
2512 .limits = iwlagn_p2p_2sta_limits,
2513 .n_limits = ARRAY_SIZE(iwlagn_p2p_2sta_limits),
2514 },
2515};
2516
f0b6e2e8
RC		 2517/*
2518 * Not a mac80211 entry point function, but it fits in with all the
2519 * other mac80211 functions grouped here.
2520 */
dd7a2509
JB		 2521static int iwl_mac_setup_register(struct iwl_priv *priv,
2522 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 2523{
2524 int ret;
2525 struct ieee80211_hw *hw = priv->hw;
d0fe478c
JB		 2526 struct iwl_rxon_context *ctx;
2527
f0b6e2e8
RC		 2528 hw->rate_control_algorithm = "iwl-agn-rs";
2529
2530 /* Tell mac80211 our characteristics */
2531 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8 2532 IEEE80211_HW_AMPDU_AGGREGATION |
2491fa42 2533 IEEE80211_HW_NEED_DTIM_PERIOD |
6fb5511a
JB		 2534 IEEE80211_HW_SPECTRUM_MGMT |
2535 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
f0b6e2e8 2536
9b768832
JB		 2537 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2538
23c0fcc6
WYG		 2539 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2540 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
f0b6e2e8 2541
88950758 2542 if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
ba37a3d0
JB		 2543 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2544 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2545
3997ff39
JB		 2546 if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2547 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2548
8d9698b3 2549 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 2550 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2551
d0fe478c
JB		 2552 for_each_context(priv, ctx) {
2553 hw->wiphy->interface_modes |= ctx->interface_modes;
2554 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2555 }
f0b6e2e8 2556
0fd09502
JB		 2557 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
2558
f35490f9 2559 if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_P2P_CLIENT)) {
0fd09502
JB		 2560 hw->wiphy->iface_combinations = iwlagn_iface_combinations_p2p;
2561 hw->wiphy->n_iface_combinations =
2562 ARRAY_SIZE(iwlagn_iface_combinations_p2p);
f35490f9 2563 } else if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_AP)) {
0fd09502
JB		 2564 hw->wiphy->iface_combinations = iwlagn_iface_combinations_dualmode;
2565 hw->wiphy->n_iface_combinations =
2566 ARRAY_SIZE(iwlagn_iface_combinations_dualmode);
2567 }
2568
9b9190d9
JB		 2569 hw->wiphy->max_remain_on_channel_duration = 1000;
2570
f6c8f152 2571 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
274102a8
JB		 2572 WIPHY_FLAG_DISABLE_BEACON_HINTS |
2573 WIPHY_FLAG_IBSS_RSN;
f0b6e2e8 2574
0172b029
WYG		 2575 if (iwlagn_mod_params.power_save)
2576 hw->wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT;
2577 else
2578 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 2579
1382c71c 2580 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 2581 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 2582 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 2583
2584 /* Default value; 4 EDCA QOS priorities */
2585 hw->queues = 4;
2586
2587 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2588
2589 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2590 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2591 &priv->bands[IEEE80211_BAND_2GHZ];
2592 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2593 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2594 &priv->bands[IEEE80211_BAND_5GHZ];
2595
5ed540ae
WYG		 2596 iwl_leds_init(priv);
2597
f0b6e2e8
RC		 2598 ret = ieee80211_register_hw(priv->hw);
2599 if (ret) {
2600 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2601 return ret;
2602 }
2603 priv->mac80211_registered = 1;
2604
2605 return 0;
2606}
2607
2608
2dedbf58 2609static int iwlagn_mac_start(struct ieee80211_hw *hw)
b481de9c 2610{
c79dd5b5 2611 struct iwl_priv *priv = hw->priv;
5a66926a 2612 int ret;
b481de9c 2613
e1623446 2614 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 2615
2616 /* we should be verifying the device is ready to be opened */
2617 mutex_lock(&priv->mutex);
5b9f8cd3 2618 ret = __iwl_up(priv);
b481de9c 2619 mutex_unlock(&priv->mutex);
e655b9f0 2620 if (ret)
6cd0b1cb 2621 return ret;
e655b9f0 2622
e1623446 2623 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2624
ca7966c8
JB		 2625 /* Now we should be done, and the READY bit should be set. */
2626 if (WARN_ON(!test_bit(STATUS_READY, &priv->status)))
2627 ret = -EIO;
0a078ffa 2628
5ed540ae 2629 iwlagn_led_enable(priv);
e932a609 2630
0a078ffa 2631 priv->is_open = 1;
e1623446 2632 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2633 return 0;
2634}
2635
2dedbf58 2636static void iwlagn_mac_stop(struct ieee80211_hw *hw)
b481de9c 2637{
c79dd5b5 2638 struct iwl_priv *priv = hw->priv;
b481de9c 2639
e1623446 2640 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2641
19cc1087 2642 if (!priv->is_open)
e655b9f0 2643 return;
e655b9f0 2644
b481de9c 2645 priv->is_open = 0;
5a66926a 2646
5b9f8cd3 2647 iwl_down(priv);
5a66926a
ZY		 2648
2649 flush_workqueue(priv->workqueue);
6cd0b1cb 2650
554d1d02
SG		 2651 /* User space software may expect getting rfkill changes
2652 * even if interface is down */
6cd0b1cb 2653 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
554d1d02 2654 iwl_enable_rfkill_int(priv);
948c171c 2655
e1623446 2656 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 2657}
2658
2dedbf58 2659static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2660{
c79dd5b5 2661 struct iwl_priv *priv = hw->priv;
b481de9c 2662
e1623446 2663 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2664
e1623446 2665 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2666 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2667
74bcdb33 2668 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 2669 dev_kfree_skb_any(skb);
2670
e1623446 2671 IWL_DEBUG_MACDUMP(priv, "leave\n");
b481de9c
ZY		 2672}
2673
2dedbf58
JB		 2674static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2675 struct ieee80211_vif *vif,
2676 struct ieee80211_key_conf *keyconf,
2677 struct ieee80211_sta *sta,
2678 u32 iv32, u16 *phase1key)
ab885f8c 2679{
9f58671e 2680 struct iwl_priv *priv = hw->priv;
a194e324
JB		 2681 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2682
e1623446 2683 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2684
a194e324 2685 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
b3fbdcf4 2686 iv32, phase1key);
ab885f8c 2687
e1623446 2688 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 2689}
2690
2dedbf58
JB		 2691static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2692 struct ieee80211_vif *vif,
2693 struct ieee80211_sta *sta,
2694 struct ieee80211_key_conf *key)
b481de9c 2695{
c79dd5b5 2696 struct iwl_priv *priv = hw->priv;
a194e324 2697 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
c10afb6e 2698 struct iwl_rxon_context *ctx = vif_priv->ctx;
42986796
WT		 2699 int ret;
2700 u8 sta_id;
2701 bool is_default_wep_key = false;
b481de9c 2702
e1623446 2703 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2704
9d143e9a 2705 if (iwlagn_mod_params.sw_crypto) {
e1623446 2706 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 2707 return -EOPNOTSUPP;
2708 }
b481de9c 2709
274102a8
JB		 2710 /*
2711 * To support IBSS RSN, don't program group keys in IBSS, the
2712 * hardware will then not attempt to decrypt the frames.
2713 */
2714 if (vif->type == NL80211_IFTYPE_ADHOC &&
2715 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
2716 return -EOPNOTSUPP;
2717
a194e324 2718 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
0af8bcae
JB		 2719 if (sta_id == IWL_INVALID_STATION)
2720 return -EINVAL;
b481de9c 2721
6974e363 2722 mutex_lock(&priv->mutex);
2a421b91 2723 iwl_scan_cancel_timeout(priv, 100);
6974e363 2724
a90178fa
JB		 2725 /*
2726 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 2727 * so far, we are in legacy wep mode (group key only), otherwise we are
2728 * in 1X mode.
a90178fa
JB		 2729 * In legacy wep mode, we use another host command to the uCode.
2730 */
97359d12
JB		 2731 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2732 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 2733 !sta) {
6974e363 2734 if (cmd == SET_KEY)
c10afb6e 2735 is_default_wep_key = !ctx->key_mapping_keys;
6974e363 2736 else
ccc038ab
EG		 2737 is_default_wep_key =
2738 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2739 }
052c4b9f 2740
b481de9c 2741 switch (cmd) {
deb09c43 2742 case SET_KEY:
6974e363 2743 if (is_default_wep_key)
2995bafa 2744 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
deb09c43 2745 else
a194e324
JB		 2746 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
2747 key, sta_id);
deb09c43 2748
e1623446 2749 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 2750 break;
2751 case DISABLE_KEY:
6974e363 2752 if (is_default_wep_key)
c10afb6e 2753 ret = iwl_remove_default_wep_key(priv, ctx, key);
deb09c43 2754 else
c10afb6e 2755 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
deb09c43 2756
e1623446 2757 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 2758 break;
2759 default:
deb09c43 2760 ret = -EINVAL;
b481de9c
ZY		 2761 }
2762
72e15d71 2763 mutex_unlock(&priv->mutex);
e1623446 2764 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2765
deb09c43 2766 return ret;
b481de9c
ZY		 2767}
2768
2dedbf58
JB		 2769static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2770 struct ieee80211_vif *vif,
2771 enum ieee80211_ampdu_mlme_action action,
2772 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
2773 u8 buf_size)
d783b061
TW		 2774{
2775 struct iwl_priv *priv = hw->priv;
4620fefa 2776 int ret = -EINVAL;
7b090687 2777 struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
d783b061 2778
e1623446 2779 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2780 sta->addr, tid);
d783b061 2781
88950758 2782 if (!(priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE))
d783b061
TW		 2783 return -EACCES;
2784
4620fefa
JB		 2785 mutex_lock(&priv->mutex);
2786
d783b061
TW		 2787 switch (action) {
2788 case IEEE80211_AMPDU_RX_START:
e1623446 2789 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 2790 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
2791 break;
d783b061 2792 case IEEE80211_AMPDU_RX_STOP:
e1623446 2793 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 2794 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 2795 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 2796 ret = 0;
2797 break;
d783b061 2798 case IEEE80211_AMPDU_TX_START:
e1623446 2799 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 2800 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 2801 if (ret == 0) {
2802 priv->_agn.agg_tids_count++;
2803 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2804 priv->_agn.agg_tids_count);
2805 }
4620fefa 2806 break;
d783b061 2807 case IEEE80211_AMPDU_TX_STOP:
e1623446 2808 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 2809 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 2810 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
2811 priv->_agn.agg_tids_count--;
2812 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2813 priv->_agn.agg_tids_count);
2814 }
5c2207c6 2815 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 2816 ret = 0;
7cb1b088
WYG		 2817 if (priv->cfg->ht_params &&
2818 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 2819 /*
2820 * switch off RTS/CTS if it was previously enabled
2821 */
94597ab2
JB		 2822 sta_priv->lq_sta.lq.general_params.flags &=
2823 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 2824 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2825 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
94597ab2 2826 }
4620fefa 2827 break;
f0527971 2828 case IEEE80211_AMPDU_TX_OPERATIONAL:
c8823ec1
JB		 2829 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
2830
2831 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
2832
7b090687
JB		 2833 /*
2834 * If the limit is 0, then it wasn't initialised yet,
2835 * use the default. We can do that since we take the
2836 * minimum below, and we don't want to go above our
2837 * default due to hardware restrictions.
2838 */
2839 if (sta_priv->max_agg_bufsize == 0)
2840 sta_priv->max_agg_bufsize =
2841 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2842
2843 /*
2844 * Even though in theory the peer could have different
2845 * aggregation reorder buffer sizes for different sessions,
2846 * our ucode doesn't allow for that and has a global limit
2847 * for each station. Therefore, use the minimum of all the
2848 * aggregation sessions and our default value.
2849 */
2850 sta_priv->max_agg_bufsize =
2851 min(sta_priv->max_agg_bufsize, buf_size);
2852
7cb1b088
WYG		 2853 if (priv->cfg->ht_params &&
2854 priv->cfg->ht_params->use_rts_for_aggregation) {
cfecc6b4
WYG		 2855 /*
2856 * switch to RTS/CTS if it is the prefer protection
2857 * method for HT traffic
2858 */
94597ab2
JB		 2859
2860 sta_priv->lq_sta.lq.general_params.flags |=
2861 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
cfecc6b4 2862 }
7b090687
JB		 2863
2864 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
2865 sta_priv->max_agg_bufsize;
2866
2867 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2868 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
5bc9890f
WYG		 2869
2870 IWL_INFO(priv, "Tx aggregation enabled on ra = %pM tid = %d\n",
2871 sta->addr, tid);
cfecc6b4 2872 ret = 0;
d783b061
TW		 2873 break;
2874 }
4620fefa
JB		 2875 mutex_unlock(&priv->mutex);
2876
2877 return ret;
d783b061 2878}
9f58671e 2879
2dedbf58
JB		 2880static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
2881 struct ieee80211_vif *vif,
2882 struct ieee80211_sta *sta)
fe6b23dd
RC		 2883{
2884 struct iwl_priv *priv = hw->priv;
2885 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
a194e324 2886 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
eafdfbd3 2887 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 2888 int ret;
2889 u8 sta_id;
2890
2891 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
2892 sta->addr);
da5ae1cf
RC		 2893 mutex_lock(&priv->mutex);
2894 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
2895 sta->addr);
2896 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 2897
2898 atomic_set(&sta_priv->pending_frames, 0);
2899 if (vif->type == NL80211_IFTYPE_AP)
2900 sta_priv->client = true;
2901
a194e324 2902 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
238d781d 2903 is_ap, sta, &sta_id);
fe6b23dd
RC		 2904 if (ret) {
2905 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
2906 sta->addr, ret);
2907 /* Should we return success if return code is EEXIST ? */
da5ae1cf 2908 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 2909 return ret;
2910 }
2911
fd1af15d
JB		 2912 sta_priv->common.sta_id = sta_id;
2913
fe6b23dd 2914 /* Initialize rate scaling */
91dd6c27 2915 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 2916 sta->addr);
2917 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 2918 mutex_unlock(&priv->mutex);
fe6b23dd 2919
fd1af15d 2920 return 0;
fe6b23dd
RC		 2921}
2922
2dedbf58
JB		 2923static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
2924 struct ieee80211_channel_switch *ch_switch)
79d07325
WYG		 2925{
2926 struct iwl_priv *priv = hw->priv;
2927 const struct iwl_channel_info *ch_info;
2928 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 2929 struct ieee80211_channel *channel = ch_switch->channel;
79d07325 2930 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
246ed355
JB		 2931 /*
2932 * MULTI-FIXME
2933 * When we add support for multiple interfaces, we need to
2934 * revisit this. The channel switch command in the device
2935 * only affects the BSS context, but what does that really
2936 * mean? And what if we get a CSA on the second interface?
2937 * This needs a lot of work.
2938 */
2939 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
79d07325 2940 u16 ch;
79d07325
WYG		 2941
2942 IWL_DEBUG_MAC80211(priv, "enter\n");
2943
dc1a4068
SG		 2944 mutex_lock(&priv->mutex);
2945
79d07325 2946 if (iwl_is_rfkill(priv))
dc1a4068 2947 goto out;
79d07325
WYG		 2948
2949 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
6f213ff1
SG		 2950 test_bit(STATUS_SCANNING, &priv->status) ||
2951 test_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status))
dc1a4068 2952 goto out;
79d07325 2953
246ed355 2954 if (!iwl_is_associated_ctx(ctx))
dc1a4068 2955 goto out;
79d07325 2956
f973f87e
SG		 2957 if (!priv->cfg->ops->lib->set_channel_switch)
2958 goto out;
79d07325 2959
f973f87e
SG		 2960 ch = channel->hw_value;
2961 if (le16_to_cpu(ctx->active.channel) == ch)
2962 goto out;
2963
2964 ch_info = iwl_get_channel_info(priv, channel->band, ch);
2965 if (!is_channel_valid(ch_info)) {
2966 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
2967 goto out;
2968 }
79d07325 2969
f973f87e 2970 spin_lock_irq(&priv->lock);
79d07325 2971
f973f87e 2972 priv->current_ht_config.smps = conf->smps_mode;
79d07325 2973
f973f87e
SG		 2974 /* Configure HT40 channels */
2975 ctx->ht.enabled = conf_is_ht(conf);
2976 if (ctx->ht.enabled) {
2977 if (conf_is_ht40_minus(conf)) {
2978 ctx->ht.extension_chan_offset =
2979 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
2980 ctx->ht.is_40mhz = true;
2981 } else if (conf_is_ht40_plus(conf)) {
2982 ctx->ht.extension_chan_offset =
2983 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
2984 ctx->ht.is_40mhz = true;
2985 } else {
2986 ctx->ht.extension_chan_offset =
2987 IEEE80211_HT_PARAM_CHA_SEC_NONE;
2988 ctx->ht.is_40mhz = false;
79d07325 2989 }
f973f87e
SG		 2990 } else
2991 ctx->ht.is_40mhz = false;
2992
2993 if ((le16_to_cpu(ctx->staging.channel) != ch))
2994 ctx->staging.flags = 0;
2995
2996 iwl_set_rxon_channel(priv, channel, ctx);
2997 iwl_set_rxon_ht(priv, ht_conf);
2998 iwl_set_flags_for_band(priv, ctx, channel->band, ctx->vif);
2999
3000 spin_unlock_irq(&priv->lock);
3001
3002 iwl_set_rate(priv);
3003 /*
3004 * at this point, staging_rxon has the
3005 * configuration for channel switch
3006 */
3007 set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
3008 priv->switch_channel = cpu_to_le16(ch);
3009 if (priv->cfg->ops->lib->set_channel_switch(priv, ch_switch)) {
3010 clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
3011 priv->switch_channel = 0;
3012 ieee80211_chswitch_done(ctx->vif, false);
79d07325 3013 }
f973f87e 3014
79d07325
WYG		 3015out:
3016 mutex_unlock(&priv->mutex);
79d07325
WYG		 3017 IWL_DEBUG_MAC80211(priv, "leave\n");
3018}
3019
2dedbf58
JB		 3020static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3021 unsigned int changed_flags,
3022 unsigned int *total_flags,
3023 u64 multicast)
8b8ab9d5
JB		 3024{
3025 struct iwl_priv *priv = hw->priv;
3026 __le32 filter_or = 0, filter_nand = 0;
246ed355 3027 struct iwl_rxon_context *ctx;
8b8ab9d5
JB		 3028
3029#define CHK(test, flag) do { \
3030 if (*total_flags & (test)) \
3031 filter_or |= (flag); \
3032 else \
3033 filter_nand |= (flag); \
3034 } while (0)
3035
3036 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3037 changed_flags, *total_flags);
3038
3039 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
bdb84fec
JB		 3040 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3041 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
8b8ab9d5
JB		 3042 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3043
3044#undef CHK
3045
3046 mutex_lock(&priv->mutex);
3047
246ed355
JB		 3048 for_each_context(priv, ctx) {
3049 ctx->staging.filter_flags &= ~filter_nand;
3050 ctx->staging.filter_flags |= filter_or;
749ff4ef
SG		 3051
3052 /*
3053 * Not committing directly because hardware can perform a scan,
3054 * but we'll eventually commit the filter flags change anyway.
3055 */
246ed355 3056 }
8b8ab9d5
JB		 3057
3058 mutex_unlock(&priv->mutex);
3059
3060 /*
3061 * Receiving all multicast frames is always enabled by the
3062 * default flags setup in iwl_connection_init_rx_config()
3063 * since we currently do not support programming multicast
3064 * filters into the device.
3065 */
3066 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3067 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3068}
3069
2dedbf58 3070static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
716c74b0
WYG		 3071{
3072 struct iwl_priv *priv = hw->priv;
3073
3074 mutex_lock(&priv->mutex);
3075 IWL_DEBUG_MAC80211(priv, "enter\n");
3076
716c74b0
WYG		 3077 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3078 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3079 goto done;
3080 }
3081 if (iwl_is_rfkill(priv)) {
3082 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3083 goto done;
3084 }
3085
3086 /*
3087 * mac80211 will not push any more frames for transmit
3088 * until the flush is completed
3089 */
3090 if (drop) {
3091 IWL_DEBUG_MAC80211(priv, "send flush command\n");
c68744fb 3092 if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) {
716c74b0
WYG		 3093 IWL_ERR(priv, "flush request fail\n");
3094 goto done;
3095 }
3096 }
3097 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3098 iwlagn_wait_tx_queue_empty(priv);
3099done:
3100 mutex_unlock(&priv->mutex);
3101 IWL_DEBUG_MAC80211(priv, "leave\n");
3102}
3103
9b9190d9
JB		 3104static void iwlagn_disable_roc(struct iwl_priv *priv)
3105{
3106 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3107 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3108
3109 lockdep_assert_held(&priv->mutex);
3110
3111 if (!ctx->is_active)
3112 return;
3113
3114 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3115 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3116 iwl_set_rxon_channel(priv, chan, ctx);
3117 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3118
3119 priv->_agn.hw_roc_channel = NULL;
3120
805a3b81 3121 iwlagn_commit_rxon(priv, ctx);
9b9190d9
JB		 3122
3123 ctx->is_active = false;
3124}
3125
3126static void iwlagn_bg_roc_done(struct work_struct *work)
3127{
3128 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3129 _agn.hw_roc_work.work);
3130
3131 mutex_lock(&priv->mutex);
3132 ieee80211_remain_on_channel_expired(priv->hw);
3133 iwlagn_disable_roc(priv);
3134 mutex_unlock(&priv->mutex);
3135}
3136
3137static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3138 struct ieee80211_channel *channel,
3139 enum nl80211_channel_type channel_type,
3140 int duration)
3141{
3142 struct iwl_priv *priv = hw->priv;
3143 int err = 0;
3144
3145 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3146 return -EOPNOTSUPP;
3147
3148 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3149 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3150 return -EOPNOTSUPP;
3151
3152 mutex_lock(&priv->mutex);
3153
3154 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3155 test_bit(STATUS_SCAN_HW, &priv->status)) {
3156 err = -EBUSY;
3157 goto out;
3158 }
3159
3160 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3161 priv->_agn.hw_roc_channel = channel;
3162 priv->_agn.hw_roc_chantype = channel_type;
3163 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
805a3b81 3164 iwlagn_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
9b9190d9
JB		 3165 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3166 msecs_to_jiffies(duration + 20));
3167
94073919 3168 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
9b9190d9
JB		 3169 ieee80211_ready_on_channel(priv->hw);
3170
3171 out:
3172 mutex_unlock(&priv->mutex);
3173
3174 return err;
3175}
3176
3177static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3178{
3179 struct iwl_priv *priv = hw->priv;
3180
3181 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3182 return -EOPNOTSUPP;
3183
3184 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3185
3186 mutex_lock(&priv->mutex);
3187 iwlagn_disable_roc(priv);
3188 mutex_unlock(&priv->mutex);
3189
3190 return 0;
3191}
3192
b481de9c
ZY		 3193/*****************************************************************************
3194 *
3195 * driver setup and teardown
3196 *
3197 *****************************************************************************/
3198
4e39317d 3199static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3200{
d21050c7 3201 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 3202
3203 init_waitqueue_head(&priv->wait_command_queue);
3204
5b9f8cd3
EG		 3205 INIT_WORK(&priv->restart, iwl_bg_restart);
3206 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3207 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3208 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 3209 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 3210 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 3211 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
9b9190d9 3212 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
2a421b91 3213
2a421b91 3214 iwl_setup_scan_deferred_work(priv);
bb8c093b 3215
4e39317d
EG		 3216 if (priv->cfg->ops->lib->setup_deferred_work)
3217 priv->cfg->ops->lib->setup_deferred_work(priv);
3218
3219 init_timer(&priv->statistics_periodic);
3220 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3221 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3222
a9e1cb6a
WYG		 3223 init_timer(&priv->ucode_trace);
3224 priv->ucode_trace.data = (unsigned long)priv;
3225 priv->ucode_trace.function = iwl_bg_ucode_trace;
3226
22de94de
SG		 3227 init_timer(&priv->watchdog);
3228 priv->watchdog.data = (unsigned long)priv;
3229 priv->watchdog.function = iwl_bg_watchdog;
b74e31a9 3230
d6b80618
WYG		 3231 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3232 iwl_irq_tasklet, (unsigned long)priv);
b481de9c
ZY		 3233}
3234
4e39317d 3235static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3236{
4e39317d
EG		 3237 if (priv->cfg->ops->lib->cancel_deferred_work)
3238 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3239
815e629b 3240 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 3241 cancel_work_sync(&priv->beacon_update);
e7e16b90
SG		 3242
3243 iwl_cancel_scan_deferred_work(priv);
3244
bee008b7 3245 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 3246 cancel_work_sync(&priv->bt_runtime_config);
e7e16b90 3247
4e39317d 3248 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3249 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY		 3250}
3251
89f186a8
RC		 3252static void iwl_init_hw_rates(struct iwl_priv *priv,
3253 struct ieee80211_rate *rates)
3254{
3255 int i;
3256
3257 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3258 rates[i].bitrate = iwl_rates[i].ieee * 5;
3259 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3260 rates[i].hw_value_short = i;
3261 rates[i].flags = 0;
3262 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3263 /*
3264 * If CCK != 1M then set short preamble rate flag.
3265 */
3266 rates[i].flags |=
3267 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3268 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3269 }
3270 }
3271}
3272
3273static int iwl_init_drv(struct iwl_priv *priv)
3274{
3275 int ret;
3276
89f186a8
RC		 3277 spin_lock_init(&priv->sta_lock);
3278 spin_lock_init(&priv->hcmd_lock);
3279
89f186a8
RC		 3280 mutex_init(&priv->mutex);
3281
89f186a8
RC		 3282 priv->ieee_channels = NULL;
3283 priv->ieee_rates = NULL;
3284 priv->band = IEEE80211_BAND_2GHZ;
3285
3286 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3287 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3288 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3289 priv->_agn.agg_tids_count = 0;
89f186a8 3290
8a472da4
WYG		 3291 /* initialize force reset */
3292 priv->force_reset[IWL_RF_RESET].reset_duration =
3293 IWL_DELAY_NEXT_FORCE_RF_RESET;
3294 priv->force_reset[IWL_FW_RESET].reset_duration =
3295 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8 3296
410f2bb3
SG		 3297 priv->rx_statistics_jiffies = jiffies;
3298
89f186a8 3299 /* Choose which receivers/antennas to use */
e3f10cea 3300 iwlagn_set_rxon_chain(priv, &priv->contexts[IWL_RXON_CTX_BSS]);
89f186a8
RC		 3301
3302 iwl_init_scan_params(priv);
3303
22bf59a0 3304 /* init bt coex */
7cb1b088
WYG		 3305 if (priv->cfg->bt_params &&
3306 priv->cfg->bt_params->advanced_bt_coexist) {
b6e116e8
WYG		 3307 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3308 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3309 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG		 3310 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3311 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3312 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
22bf59a0
WYG		 3313 }
3314
89f186a8
RC		 3315 ret = iwl_init_channel_map(priv);
3316 if (ret) {
3317 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3318 goto err;
3319 }
3320
3321 ret = iwlcore_init_geos(priv);
3322 if (ret) {
3323 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3324 goto err_free_channel_map;
3325 }
3326 iwl_init_hw_rates(priv, priv->ieee_rates);
3327
3328 return 0;
3329
3330err_free_channel_map:
3331 iwl_free_channel_map(priv);
3332err:
3333 return ret;
3334}
3335
3336static void iwl_uninit_drv(struct iwl_priv *priv)
3337{
3338 iwl_calib_free_results(priv);
3339 iwlcore_free_geos(priv);
3340 iwl_free_channel_map(priv);
811ecc99 3341 kfree(priv->scan_cmd);
4ce7cc2b 3342 kfree(priv->beacon_cmd);
89f186a8
RC		 3343}
3344
3a3b14c2 3345static void iwl_mac_rssi_callback(struct ieee80211_hw *hw,
207ecc5e
MV		 3346 enum ieee80211_rssi_event rssi_event)
3347{
3348 struct iwl_priv *priv = hw->priv;
3349
3350 mutex_lock(&priv->mutex);
3351
3352 if (priv->cfg->bt_params &&
3353 priv->cfg->bt_params->advanced_bt_coexist) {
3354 if (rssi_event == RSSI_EVENT_LOW)
3355 priv->bt_enable_pspoll = true;
3356 else if (rssi_event == RSSI_EVENT_HIGH)
3357 priv->bt_enable_pspoll = false;
3358
3359 iwlagn_send_advance_bt_config(priv);
3360 } else {
3361 IWL_DEBUG_MAC80211(priv, "Advanced BT coex disabled,"
3362 "ignoring RSSI callback\n");
3363 }
3364
3365 mutex_unlock(&priv->mutex);
3366}
3367
dc21b545 3368struct ieee80211_ops iwlagn_hw_ops = {
2295c66b
JB		 3369 .tx = iwlagn_mac_tx,
3370 .start = iwlagn_mac_start,
3371 .stop = iwlagn_mac_stop,
5b9f8cd3
EG		 3372 .add_interface = iwl_mac_add_interface,
3373 .remove_interface = iwl_mac_remove_interface,
d4daaea6 3374 .change_interface = iwl_mac_change_interface,
2295c66b 3375 .config = iwlagn_mac_config,
8b8ab9d5 3376 .configure_filter = iwlagn_configure_filter,
2295c66b
JB		 3377 .set_key = iwlagn_mac_set_key,
3378 .update_tkip_key = iwlagn_mac_update_tkip_key,
5b9f8cd3 3379 .conf_tx = iwl_mac_conf_tx,
2295c66b
JB		 3380 .bss_info_changed = iwlagn_bss_info_changed,
3381 .ampdu_action = iwlagn_mac_ampdu_action,
6ab10ff8 3382 .hw_scan = iwl_mac_hw_scan,
2295c66b 3383 .sta_notify = iwlagn_mac_sta_notify,
fe6b23dd
RC		 3384 .sta_add = iwlagn_mac_sta_add,
3385 .sta_remove = iwl_mac_sta_remove,
2295c66b
JB		 3386 .channel_switch = iwlagn_mac_channel_switch,
3387 .flush = iwlagn_mac_flush,
a85d7cca 3388 .tx_last_beacon = iwl_mac_tx_last_beacon,
9b9190d9
JB		 3389 .remain_on_channel = iwl_mac_remain_on_channel,
3390 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
266af4c7
JB		 3391 .offchannel_tx = iwl_mac_offchannel_tx,
3392 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
207ecc5e 3393 .rssi_callback = iwl_mac_rssi_callback,
4613e72d 3394 CFG80211_TESTMODE_CMD(iwl_testmode_cmd)
eb64dca0 3395 CFG80211_TESTMODE_DUMP(iwl_testmode_dump)
b481de9c
ZY		 3396};
3397
e98a1302 3398static u32 iwl_hw_detect(struct iwl_priv *priv)
3867fe04 3399{
02a7fa00 3400 return iwl_read32(priv, CSR_HW_REV);
3867fe04
WYG		 3401}
3402
07d4f1ad
WYG		 3403static int iwl_set_hw_params(struct iwl_priv *priv)
3404{
3405 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3406 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
9d143e9a 3407 if (iwlagn_mod_params.amsdu_size_8K)
07d4f1ad
WYG		 3408 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3409 else
3410 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3411
3412 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3413
9d143e9a 3414 if (iwlagn_mod_params.disable_11n)
88950758 3415 priv->cfg->sku &= ~EEPROM_SKU_CAP_11N_ENABLE;
07d4f1ad
WYG		 3416
3417 /* Device-specific setup */
3418 return priv->cfg->ops->lib->set_hw_params(priv);
3419}
3420
e72f368b
JB		 3421static const u8 iwlagn_bss_ac_to_fifo[] = {
3422 IWL_TX_FIFO_VO,
3423 IWL_TX_FIFO_VI,
3424 IWL_TX_FIFO_BE,
3425 IWL_TX_FIFO_BK,
3426};
3427
3428static const u8 iwlagn_bss_ac_to_queue[] = {
3429 0, 1, 2, 3,
3430};
3431
3432static const u8 iwlagn_pan_ac_to_fifo[] = {
3433 IWL_TX_FIFO_VO_IPAN,
3434 IWL_TX_FIFO_VI_IPAN,
3435 IWL_TX_FIFO_BE_IPAN,
3436 IWL_TX_FIFO_BK_IPAN,
3437};
3438
3439static const u8 iwlagn_pan_ac_to_queue[] = {
3440 7, 6, 5, 4,
3441};
3442
119ea186
WYG		 3443/* This function both allocates and initializes hw and priv. */
3444static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
3445{
3446 struct iwl_priv *priv;
3447 /* mac80211 allocates memory for this device instance, including
3448 * space for this driver's private structure */
3449 struct ieee80211_hw *hw;
3450
3451 hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops);
3452 if (hw == NULL) {
3453 pr_err("%s: Can not allocate network device\n",
3454 cfg->name);
3455 goto out;
3456 }
3457
3458 priv = hw->priv;
3459 priv->hw = hw;
3460
3461out:
3462 return hw;
3463}
3464
b2ea345e 3465static void iwl_init_context(struct iwl_priv *priv)
b481de9c 3466{
b2ea345e 3467 int i;
1d0a082d 3468
246ed355
JB		 3469 /*
3470 * The default context is always valid,
3471 * more may be discovered when firmware
3472 * is loaded.
3473 */
3474 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3475
3476 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3477 priv->contexts[i].ctxid = i;
3478
763cc3bf
JB		 3479 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3480 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
8f2d3d2a
JB		 3481 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3482 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3483 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 3484 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 3485 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
c10afb6e 3486 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
e72f368b
JB		 3487 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3488 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
d0fe478c
JB		 3489 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3490 BIT(NL80211_IFTYPE_ADHOC);
3491 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3492 BIT(NL80211_IFTYPE_STATION);
2295c66b 3493 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
d0fe478c
JB		 3494 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3495 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3496 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
ece9c4ee
JB		 3497
3498 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
b2ea345e
WYG		 3499 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd =
3500 REPLY_WIPAN_RXON_TIMING;
3501 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd =
3502 REPLY_WIPAN_RXON_ASSOC;
ece9c4ee
JB		 3503 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3504 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3505 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3506 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3507 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
e72f368b
JB		 3508 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3509 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3510 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
d0fe478c
JB		 3511 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3512 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
f35c0c56
WYG		 3513#ifdef CONFIG_IWL_P2P
3514 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3515 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3516#endif
d0fe478c
JB		 3517 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3518 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3519 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
ece9c4ee
JB		 3520
3521 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
b2ea345e
WYG		 3522}
3523
a48709c5
EG		 3524int iwl_probe(void *bus_specific, struct iwl_bus_ops *bus_ops,
3525 struct iwl_cfg *cfg)
b2ea345e
WYG		 3526{
3527 int err = 0;
3528 struct iwl_priv *priv;
3529 struct ieee80211_hw *hw;
084dd791 3530 u16 num_mac;
b2ea345e
WYG		 3531 u32 hw_rev;
3532
3533 /************************
3534 * 1. Allocating HW data
3535 ************************/
b2ea345e
WYG		 3536 hw = iwl_alloc_all(cfg);
3537 if (!hw) {
3538 err = -ENOMEM;
807caf26
EG		 3539 goto out;
3540 }
3541
b2ea345e 3542 priv = hw->priv;
a48709c5
EG		 3543
3544 priv->bus.priv = priv;
3545 priv->bus.bus_specific = bus_specific;
3546 priv->bus.ops = bus_ops;
705cd451 3547 priv->bus.irq = priv->bus.ops->get_irq(&priv->bus);
a48709c5 3548 priv->bus.ops->set_drv_data(&priv->bus, priv);
3599d39a 3549 priv->bus.dev = priv->bus.ops->get_dev(&priv->bus);
a48709c5 3550
c85eb619
EG		 3551 iwl_trans_register(&priv->trans);
3552
b2ea345e 3553 /* At this point both hw and priv are allocated. */
8f2d3d2a 3554
3599d39a 3555 SET_IEEE80211_DEV(hw, priv->bus.dev);
b481de9c 3556
e1623446 3557 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3558 priv->cfg = cfg;
40cefda9 3559 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3560
bee008b7
WYG		 3561 /* is antenna coupling more than 35dB ? */
3562 priv->bt_ant_couple_ok =
3563 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3564 true : false;
3565
9f28ebc3 3566 /* enable/disable bt channel inhibition */
f37837c9 3567 priv->bt_ch_announce = iwlagn_bt_ch_announce;
9f28ebc3
WYG		 3568 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3569 (priv->bt_ch_announce) ? "On" : "Off");
f37837c9 3570
20594eb0
WYG		 3571 if (iwl_alloc_traffic_mem(priv))
3572 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3573
316c30d9 3574
731a29b7 3575 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 3576 * we should init now
3577 */
3578 spin_lock_init(&priv->reg_lock);
731a29b7 3579 spin_lock_init(&priv->lock);
4843b5a7
RC		 3580
3581 /*
3582 * stop and reset the on-board processor just in case it is in a
3583 * strange state ... like being left stranded by a primary kernel
3584 * and this is now the kdump kernel trying to start up
3585 */
3586 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3587
084dd791
EG		 3588 /***********************
3589 * 3. Read REV register
3590 ***********************/
e98a1302 3591 hw_rev = iwl_hw_detect(priv);
c11362c0 3592 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
e98a1302 3593 priv->cfg->name, hw_rev);
316c30d9 3594
4cd2bf76 3595 if (iwl_prepare_card_hw(priv)) {
bcd4fe2f 3596 err = -EIO;
086ed117 3597 IWL_WARN(priv, "Failed, HW not ready\n");
084dd791 3598 goto out_free_traffic_mem;
086ed117
MA		 3599 }
3600
91238714
TW		 3601 /*****************
3602 * 4. Read EEPROM
3603 *****************/
316c30d9 3604 /* Read the EEPROM */
e98a1302 3605 err = iwl_eeprom_init(priv, hw_rev);
316c30d9 3606 if (err) {
15b1687c 3607 IWL_ERR(priv, "Unable to init EEPROM\n");
084dd791 3608 goto out_free_traffic_mem;
316c30d9 3609 }
8614f360
TW		 3610 err = iwl_eeprom_check_version(priv);
3611 if (err)
c8f16138 3612 goto out_free_eeprom;
8614f360 3613
21a5b3c6
WYG		 3614 err = iwl_eeprom_check_sku(priv);
3615 if (err)
3616 goto out_free_eeprom;
3617
02883017 3618 /* extract MAC Address */
c6fa17ed
WYG		 3619 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3620 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3621 priv->hw->wiphy->addresses = priv->addresses;
3622 priv->hw->wiphy->n_addresses = 1;
3623 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3624 if (num_mac > 1) {
3625 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3626 ETH_ALEN);
3627 priv->addresses[1].addr[5]++;
3628 priv->hw->wiphy->n_addresses++;
3629 }
316c30d9 3630
b2ea345e
WYG		 3631 /* initialize all valid contexts */
3632 iwl_init_context(priv);
3633
316c30d9
AK		 3634 /************************
3635 * 5. Setup HW constants
3636 ************************/
da154e30 3637 if (iwl_set_hw_params(priv)) {
084dd791 3638 err = -ENOENT;
15b1687c 3639 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3640 goto out_free_eeprom;
316c30d9
AK		 3641 }
3642
3643 /*******************
6ba87956 3644 * 6. Setup priv
316c30d9 3645 *******************/
b481de9c 3646
6ba87956 3647 err = iwl_init_drv(priv);
bf85ea4f 3648 if (err)
399f4900 3649 goto out_free_eeprom;
bf85ea4f 3650 /* At this point both hw and priv are initialized. */
316c30d9 3651
316c30d9 3652 /********************
09f9bf79 3653 * 7. Setup services
316c30d9 3654 ********************/
519d8abd 3655 iwl_alloc_isr_ict(priv);
e39fdee1 3656
705cd451
EG		 3657 err = request_irq(priv->bus.irq, iwl_isr_ict, IRQF_SHARED,
3658 DRV_NAME, priv);
6cd0b1cb 3659 if (err) {
705cd451 3660 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->bus.irq);
084dd791 3661 goto out_uninit_drv;
6cd0b1cb 3662 }
316c30d9 3663
4e39317d 3664 iwl_setup_deferred_work(priv);
653fa4a0 3665 iwl_setup_rx_handlers(priv);
4613e72d 3666 iwl_testmode_init(priv);
316c30d9 3667
158bea07 3668 /*********************************************
084dd791 3669 * 8. Enable interrupts
158bea07 3670 *********************************************/
6ba87956 3671
554d1d02 3672 iwl_enable_rfkill_int(priv);
6cd0b1cb 3673
6cd0b1cb
HS		 3674 /* If platform's RF_KILL switch is NOT set to KILL */
3675 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3676 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3677 else
3678 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3679
a60e77e5
JB		 3680 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3681 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3682
58d0f361 3683 iwl_power_initialize(priv);
39b73fb1 3684 iwl_tt_initialize(priv);
158bea07 3685
a15707d8 3686 init_completion(&priv->_agn.firmware_loading_complete);
562db532 3687
b08dfd04 3688 err = iwl_request_firmware(priv, true);
158bea07 3689 if (err)
7d47618a 3690 goto out_destroy_workqueue;
158bea07 3691
b481de9c
ZY		 3692 return 0;
3693
7d47618a 3694 out_destroy_workqueue:
c8f16138
RC		 3695 destroy_workqueue(priv->workqueue);
3696 priv->workqueue = NULL;
705cd451 3697 free_irq(priv->bus.irq, priv);
93cce6f0 3698 iwl_free_isr_ict(priv);
084dd791 3699 out_uninit_drv:
6ba87956 3700 iwl_uninit_drv(priv);
073d3f5f
TW		 3701 out_free_eeprom:
3702 iwl_eeprom_free(priv);
084dd791 3703 out_free_traffic_mem:
20594eb0 3704 iwl_free_traffic_mem(priv);
d7c76f4c 3705 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 3706 out:
3707 return err;
3708}
3709
a48709c5 3710void __devexit iwl_remove(struct iwl_priv * priv)
b481de9c 3711{
0359facc 3712 unsigned long flags;
b481de9c 3713
a15707d8 3714 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 3715
e1623446 3716 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3717
67249625 3718 iwl_dbgfs_unregister(priv);
3599d39a
EG		 3719 sysfs_remove_group(&priv->bus.dev->kobj,
3720 &iwl_attribute_group);
67249625 3721
5b9f8cd3
EG		 3722 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3723 * to be called and iwl_down since we are removing the device
0b124c31
GG		 3724 * we need to set STATUS_EXIT_PENDING bit.
3725 */
3726 set_bit(STATUS_EXIT_PENDING, &priv->status);
5ed540ae 3727
7a4e5281 3728 iwl_testmode_cleanup(priv);
5ed540ae
WYG		 3729 iwl_leds_exit(priv);
3730
c4f55232
RR		 3731 if (priv->mac80211_registered) {
3732 ieee80211_unregister_hw(priv->hw);
3733 priv->mac80211_registered = 0;
3734 }
3735
1a10f433 3736 /* Reset to low power before unloading driver. */
14e8e4af 3737 iwl_apm_stop(priv);
c166b25a 3738
39b73fb1
WYG		 3739 iwl_tt_exit(priv);
3740
0359facc
MA		 3741 /* make sure we flush any pending irq or
3742 * tasklet for the driver
3743 */
3744 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3745 iwl_disable_interrupts(priv);
0359facc
MA		 3746 spin_unlock_irqrestore(&priv->lock, flags);
3747
3748 iwl_synchronize_irq(priv);
3749
3599d39a 3750 iwl_dealloc_ucode(priv);
b481de9c 3751
bdfbf092
EG		 3752 trans_rx_free(priv);
3753 trans_tx_free(priv);
b481de9c 3754
073d3f5f 3755 iwl_eeprom_free(priv);
b481de9c 3756
b481de9c 3757
948c171c
MA		 3758 /*netif_stop_queue(dev); */
3759 flush_workqueue(priv->workqueue);
3760
5b9f8cd3 3761 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 3762 * priv->workqueue... so we can't take down the workqueue
3763 * until now... */
3764 destroy_workqueue(priv->workqueue);
3765 priv->workqueue = NULL;
20594eb0 3766 iwl_free_traffic_mem(priv);
b481de9c 3767
705cd451 3768 free_irq(priv->bus.irq, priv);
a48709c5 3769 priv->bus.ops->set_drv_data(&priv->bus, NULL);
b481de9c 3770
6ba87956 3771 iwl_uninit_drv(priv);
b481de9c 3772
519d8abd 3773 iwl_free_isr_ict(priv);
ef850d7c 3774
77834543 3775 dev_kfree_skb(priv->beacon_skb);
b481de9c
ZY		 3776
3777 ieee80211_free_hw(priv->hw);
3778}
3779
b481de9c
ZY		 3780
3781/*****************************************************************************
3782 *
3783 * driver and module entry point
3784 *
3785 *****************************************************************************/
5b9f8cd3 3786static int __init iwl_init(void)
b481de9c
ZY		 3787{
3788
3789 int ret;
c96c31e4
JP		 3790 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
3791 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 3792
e227ceac 3793 ret = iwlagn_rate_control_register();
897e1cf2 3794 if (ret) {
c96c31e4 3795 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 3796 return ret;
3797 }
3798
48d1a211 3799 ret = iwl_pci_register_driver();
b481de9c 3800
48d1a211
EG		 3801 if (ret)
3802 goto error_register;
b481de9c 3803 return ret;
897e1cf2 3804
897e1cf2 3805error_register:
e227ceac 3806 iwlagn_rate_control_unregister();
897e1cf2 3807 return ret;
b481de9c
ZY		 3808}
3809
5b9f8cd3 3810static void __exit iwl_exit(void)
b481de9c 3811{
48d1a211 3812 iwl_pci_unregister_driver();
e227ceac 3813 iwlagn_rate_control_unregister();
b481de9c
ZY		 3814}
3815
5b9f8cd3
EG		 3816module_exit(iwl_exit);
3817module_init(iwl_init);
a562a9dd
RC		 3818
3819#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3820module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 3821MODULE_PARM_DESC(debug, "debug output mask");
3822#endif
3823
2b068618
WYG		 3824module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
3825MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
2b068618
WYG		 3826module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
3827MODULE_PARM_DESC(queues_num, "number of hw queues.");
2b068618
WYG		 3828module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
3829MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
2b068618
WYG		 3830module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
3831 int, S_IRUGO);
3832MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
2b068618
WYG		 3833module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
3834MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
dd7a2509
JB		 3835
3836module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
3837 S_IRUGO);
3838MODULE_PARM_DESC(ucode_alternative,
3839 "specify ucode alternative to use from ucode file");
bee008b7
WYG		 3840
3841module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
3842MODULE_PARM_DESC(antenna_coupling,
3843 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9 3844
9f28ebc3
WYG		 3845module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
3846MODULE_PARM_DESC(bt_ch_inhibition,
3847 "Disable BT channel inhibition (default: enable)");
b7977ffa
SG		 3848
3849module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
3850MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
3851
3852module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
3853MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
b60eec9b 3854
300d0834
WYG		 3855module_param_named(wd_disable, iwlagn_mod_params.wd_disable, bool, S_IRUGO);
3856MODULE_PARM_DESC(wd_disable,
3857 "Disable stuck queue watchdog timer (default: 0 [enabled])");
3858
b60eec9b
WYG		 3859/*
3860 * set bt_coex_active to true, uCode will do kill/defer
3861 * every time the priority line is asserted (BT is sending signals on the
3862 * priority line in the PCIx).
3863 * set bt_coex_active to false, uCode will ignore the BT activity and
3864 * perform the normal operation
3865 *
3866 * User might experience transmit issue on some platform due to WiFi/BT
3867 * co-exist problem. The possible behaviors are:
3868 * Able to scan and finding all the available AP
3869 * Not able to associate with any AP
3870 * On those platforms, WiFi communication can be restored by set
3871 * "bt_coex_active" module parameter to "false"
3872 *
3873 * default: bt_coex_active = true (BT_COEX_ENABLE)
3874 */
3875module_param_named(bt_coex_active, iwlagn_mod_params.bt_coex_active,
3876 bool, S_IRUGO);
3877MODULE_PARM_DESC(bt_coex_active, "enable wifi/bt co-exist (default: enable)");
6b0184c4
WYG		 3878
3879module_param_named(led_mode, iwlagn_mod_params.led_mode, int, S_IRUGO);
3880MODULE_PARM_DESC(led_mode, "0=system default, "
3881 "1=On(RF On)/Off(RF Off), 2=blinking (default: 0)");
3f1e5f4a 3882
0172b029
WYG		 3883module_param_named(power_save, iwlagn_mod_params.power_save,
3884 bool, S_IRUGO);
3885MODULE_PARM_DESC(power_save,
3886 "enable WiFi power management (default: disable)");
3887
f7538168
WYG		 3888module_param_named(power_level, iwlagn_mod_params.power_level,
3889 int, S_IRUGO);
3890MODULE_PARM_DESC(power_level,
3891 "default power save level (range from 1 - 5, default: 1)");
3892
3f1e5f4a
WYG		 3893/*
3894 * For now, keep using power level 1 instead of automatically
3895 * adjusting ...
3896 */
3897module_param_named(no_sleep_autoadjust, iwlagn_mod_params.no_sleep_autoadjust,
3898 bool, S_IRUGO);
3899MODULE_PARM_DESC(no_sleep_autoadjust,
3900 "don't automatically adjust sleep level "
3901 "according to maximum network latency (default: true)");
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