iwlagn: change log to better represent the state of aggregation process
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY
1/******************************************************************************
2 *
901069c7 3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
b481de9c
ZY
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP
30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY
32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY
34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY
41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY
45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY
48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO
52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
0de76736 60#include "iwl-agn-calib.h"
a1175124 61#include "iwl-agn.h"
b481de9c 62
416e1438 63
b481de9c
ZY
64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
b481de9c
ZY
70/*
71 * module name, copyright, version, etc.
b481de9c 72 */
d783b061 73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 74
0a6857e7 75#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
76#define VD "d"
77#else
78#define VD
79#endif
80
81963d68 81#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 82
b481de9c
ZY
83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c
ZY
87MODULE_LICENSE("GPL");
88
bee008b7 89static int iwlagn_ant_coupling;
f37837c9 90static bool iwlagn_bt_ch_announce = 1;
bee008b7 91
5b9f8cd3 92void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f 93{
246ed355 94 struct iwl_rxon_context *ctx;
5da4b55f 95
246ed355
JB
96 if (priv->cfg->ops->hcmd->set_rxon_chain) {
97 for_each_context(priv, ctx) {
98 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
6163a373
SZ
99 if (ctx->active.rx_chain != ctx->staging.rx_chain)
100 iwlcore_commit_rxon(priv, ctx);
246ed355
JB
101 }
102 }
5da4b55f
MA
103}
104
47ff65c4
DH
105/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
106static void iwl_set_beacon_tim(struct iwl_priv *priv,
77834543
JB
107 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
108 u8 *beacon, u32 frame_size)
47ff65c4
DH
109{
110 u16 tim_idx;
111 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
112
113 /*
114 * The index is relative to frame start but we start looking at the
115 * variable-length part of the beacon.
116 */
117 tim_idx = mgmt->u.beacon.variable - beacon;
118
119 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
120 while ((tim_idx < (frame_size - 2)) &&
121 (beacon[tim_idx] != WLAN_EID_TIM))
122 tim_idx += beacon[tim_idx+1] + 2;
123
124 /* If TIM field was found, set variables */
125 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
126 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
127 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
128 } else
129 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
130}
131
8a98d49e 132int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
4bf64efd
TW
133{
134 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
8a98d49e
JB
135 struct iwl_host_cmd cmd = {
136 .id = REPLY_TX_BEACON,
8a98d49e 137 };
47ff65c4
DH
138 u32 frame_size;
139 u32 rate_flags;
140 u32 rate;
8a98d49e 141
47ff65c4
DH
142 /*
143 * We have to set up the TX command, the TX Beacon command, and the
144 * beacon contents.
145 */
4bf64efd 146
76d04815
JB
147 lockdep_assert_held(&priv->mutex);
148
149 if (!priv->beacon_ctx) {
150 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
950094cb 151 return 0;
76d04815
JB
152 }
153
8a98d49e
JB
154 if (WARN_ON(!priv->beacon_skb))
155 return -EINVAL;
156
4ce7cc2b
JB
157 /* Allocate beacon command */
158 if (!priv->beacon_cmd)
159 priv->beacon_cmd = kzalloc(sizeof(*tx_beacon_cmd), GFP_KERNEL);
160 tx_beacon_cmd = priv->beacon_cmd;
8a98d49e
JB
161 if (!tx_beacon_cmd)
162 return -ENOMEM;
163
164 frame_size = priv->beacon_skb->len;
4bf64efd 165
47ff65c4 166 /* Set up TX command fields */
4bf64efd 167 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
76d04815 168 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
47ff65c4
DH
169 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
170 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
171 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 172
47ff65c4 173 /* Set up TX beacon command fields */
4ce7cc2b 174 iwl_set_beacon_tim(priv, tx_beacon_cmd, priv->beacon_skb->data,
77834543 175 frame_size);
4bf64efd 176
47ff65c4 177 /* Set up packet rate and flags */
76d04815 178 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
0e1654fa
JB
179 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
180 priv->hw_params.valid_tx_ant);
47ff65c4
DH
181 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
182 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
183 rate_flags |= RATE_MCS_CCK_MSK;
184 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
185 rate_flags);
4bf64efd 186
8a98d49e 187 /* Submit command */
4ce7cc2b 188 cmd.len[0] = sizeof(*tx_beacon_cmd);
3fa50738 189 cmd.data[0] = tx_beacon_cmd;
4ce7cc2b
JB
190 cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
191 cmd.len[1] = frame_size;
192 cmd.data[1] = priv->beacon_skb->data;
193 cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
7aaa1d79 194
4ce7cc2b 195 return iwl_send_cmd_sync(priv, &cmd);
a8e74e27
SO
196}
197
5b9f8cd3 198static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 199{
c79dd5b5
TW
200 struct iwl_priv *priv =
201 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
202 struct sk_buff *beacon;
203
76d04815
JB
204 mutex_lock(&priv->mutex);
205 if (!priv->beacon_ctx) {
206 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
207 goto out;
208 }
b481de9c 209
60744f62
JB
210 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
211 /*
212 * The ucode will send beacon notifications even in
213 * IBSS mode, but we don't want to process them. But
214 * we need to defer the type check to here due to
215 * requiring locking around the beacon_ctx access.
216 */
217 goto out;
218 }
219
76d04815
JB
220 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
221 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
b481de9c 222 if (!beacon) {
77834543 223 IWL_ERR(priv, "update beacon failed -- keeping old\n");
76d04815 224 goto out;
b481de9c
ZY
225 }
226
b481de9c 227 /* new beacon skb is allocated every time; dispose previous.*/
77834543 228 dev_kfree_skb(priv->beacon_skb);
b481de9c 229
12e934dc 230 priv->beacon_skb = beacon;
b481de9c 231
2295c66b 232 iwlagn_send_beacon_cmd(priv);
76d04815
JB
233 out:
234 mutex_unlock(&priv->mutex);
b481de9c
ZY
235}
236
fbba9410
WYG
237static void iwl_bg_bt_runtime_config(struct work_struct *work)
238{
239 struct iwl_priv *priv =
240 container_of(work, struct iwl_priv, bt_runtime_config);
241
242 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
243 return;
244
245 /* dont send host command if rf-kill is on */
246 if (!iwl_is_ready_rf(priv))
247 return;
248 priv->cfg->ops->hcmd->send_bt_config(priv);
249}
250
bee008b7
WYG
251static void iwl_bg_bt_full_concurrency(struct work_struct *work)
252{
253 struct iwl_priv *priv =
254 container_of(work, struct iwl_priv, bt_full_concurrency);
246ed355 255 struct iwl_rxon_context *ctx;
bee008b7 256
dc1a4068
SG
257 mutex_lock(&priv->mutex);
258
bee008b7 259 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
dc1a4068 260 goto out;
bee008b7
WYG
261
262 /* dont send host command if rf-kill is on */
263 if (!iwl_is_ready_rf(priv))
dc1a4068 264 goto out;
bee008b7
WYG
265
266 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
267 priv->bt_full_concurrent ?
268 "full concurrency" : "3-wire");
269
270 /*
271 * LQ & RXON updated cmds must be sent before BT Config cmd
272 * to avoid 3-wire collisions
273 */
246ed355
JB
274 for_each_context(priv, ctx) {
275 if (priv->cfg->ops->hcmd->set_rxon_chain)
276 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
277 iwlcore_commit_rxon(priv, ctx);
278 }
bee008b7
WYG
279
280 priv->cfg->ops->hcmd->send_bt_config(priv);
dc1a4068
SG
281out:
282 mutex_unlock(&priv->mutex);
bee008b7
WYG
283}
284
4e39317d 285/**
5b9f8cd3 286 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
287 *
288 * This callback is provided in order to send a statistics request.
289 *
290 * This timer function is continually reset to execute within
291 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
292 * was received. We need to ensure we receive the statistics in order
293 * to update the temperature used for calibrating the TXPOWER.
294 */
5b9f8cd3 295static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
296{
297 struct iwl_priv *priv = (struct iwl_priv *)data;
298
299 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
300 return;
301
61780ee3
MA
302 /* dont send host command if rf-kill is on */
303 if (!iwl_is_ready_rf(priv))
304 return;
305
ef8d5529 306 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG
307}
308
a9e1cb6a
WYG
309
310static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
311 u32 start_idx, u32 num_events,
312 u32 mode)
313{
314 u32 i;
315 u32 ptr; /* SRAM byte address of log data */
316 u32 ev, time, data; /* event log data */
317 unsigned long reg_flags;
318
319 if (mode == 0)
320 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
321 else
322 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
323
324 /* Make sure device is powered up for SRAM reads */
325 spin_lock_irqsave(&priv->reg_lock, reg_flags);
326 if (iwl_grab_nic_access(priv)) {
327 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
328 return;
329 }
330
331 /* Set starting address; reads will auto-increment */
02a7fa00 332 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
a9e1cb6a
WYG
333 rmb();
334
335 /*
336 * "time" is actually "data" for mode 0 (no timestamp).
337 * place event id # at far right for easier visual parsing.
338 */
339 for (i = 0; i < num_events; i++) {
02a7fa00
JB
340 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
341 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
a9e1cb6a
WYG
342 if (mode == 0) {
343 trace_iwlwifi_dev_ucode_cont_event(priv,
344 0, time, ev);
345 } else {
02a7fa00 346 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
a9e1cb6a
WYG
347 trace_iwlwifi_dev_ucode_cont_event(priv,
348 time, data, ev);
349 }
350 }
351 /* Allow device to power down */
352 iwl_release_nic_access(priv);
353 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
354}
355
875295f1 356static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG
357{
358 u32 capacity; /* event log capacity in # entries */
359 u32 base; /* SRAM byte address of event log header */
360 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
361 u32 num_wraps; /* # times uCode wrapped to top of log */
362 u32 next_entry; /* index of next entry to be written by uCode */
363
d7d5783c 364 base = priv->device_pointers.error_event_table;
a9e1cb6a
WYG
365 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
366 capacity = iwl_read_targ_mem(priv, base);
367 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
368 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
369 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
370 } else
371 return;
372
373 if (num_wraps == priv->event_log.num_wraps) {
374 iwl_print_cont_event_trace(priv,
375 base, priv->event_log.next_entry,
376 next_entry - priv->event_log.next_entry,
377 mode);
378 priv->event_log.non_wraps_count++;
379 } else {
380 if ((num_wraps - priv->event_log.num_wraps) > 1)
381 priv->event_log.wraps_more_count++;
382 else
383 priv->event_log.wraps_once_count++;
384 trace_iwlwifi_dev_ucode_wrap_event(priv,
385 num_wraps - priv->event_log.num_wraps,
386 next_entry, priv->event_log.next_entry);
387 if (next_entry < priv->event_log.next_entry) {
388 iwl_print_cont_event_trace(priv, base,
389 priv->event_log.next_entry,
390 capacity - priv->event_log.next_entry,
391 mode);
392
393 iwl_print_cont_event_trace(priv, base, 0,
394 next_entry, mode);
395 } else {
396 iwl_print_cont_event_trace(priv, base,
397 next_entry, capacity - next_entry,
398 mode);
399
400 iwl_print_cont_event_trace(priv, base, 0,
401 next_entry, mode);
402 }
403 }
404 priv->event_log.num_wraps = num_wraps;
405 priv->event_log.next_entry = next_entry;
406}
407
408/**
409 * iwl_bg_ucode_trace - Timer callback to log ucode event
410 *
411 * The timer is continually set to execute every
412 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
413 * this function is to perform continuous uCode event logging operation
414 * if enabled
415 */
416static void iwl_bg_ucode_trace(unsigned long data)
417{
418 struct iwl_priv *priv = (struct iwl_priv *)data;
419
420 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
421 return;
422
423 if (priv->event_log.ucode_trace) {
424 iwl_continuous_event_trace(priv);
425 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
426 mod_timer(&priv->ucode_trace,
427 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
428 }
429}
430
65550636
WYG
431static void iwl_bg_tx_flush(struct work_struct *work)
432{
433 struct iwl_priv *priv =
434 container_of(work, struct iwl_priv, tx_flush);
435
436 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
437 return;
438
439 /* do nothing if rf-kill is on */
440 if (!iwl_is_ready_rf(priv))
441 return;
442
443 if (priv->cfg->ops->lib->txfifo_flush) {
444 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
445 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
446 }
447}
448
b481de9c 449/**
a55360e4 450 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
451 *
452 * Uses the priv->rx_handlers callback function array to invoke
453 * the appropriate handlers, including command responses,
454 * frame-received notifications, and other notifications.
455 */
f945f108 456static void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 457{
a55360e4 458 struct iwl_rx_mem_buffer *rxb;
db11d634 459 struct iwl_rx_packet *pkt;
a55360e4 460 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
461 u32 r, i;
462 int reclaim;
463 unsigned long flags;
5c0eef96 464 u8 fill_rx = 0;
d68ab680 465 u32 count = 8;
4752c93c 466 int total_empty;
b481de9c 467
6440adb5
CB
468 /* uCode's read index (stored in shared DRAM) indicates the last Rx
469 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 470 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
471 i = rxq->read;
472
473 /* Rx interrupt, but nothing sent from uCode */
474 if (i == r)
e1623446 475 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 476
4752c93c 477 /* calculate total frames need to be restock after handling RX */
7300515d 478 total_empty = r - rxq->write_actual;
4752c93c
MA
479 if (total_empty < 0)
480 total_empty += RX_QUEUE_SIZE;
481
482 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
483 fill_rx = 1;
484
b481de9c 485 while (i != r) {
f4989d9b
JB
486 int len;
487
b481de9c
ZY
488 rxb = rxq->queue[i];
489
9fbab516 490 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
491 * then a bug has been introduced in the queue refilling
492 * routines -- catch it here */
3e41ace5
JB
493 if (WARN_ON(rxb == NULL)) {
494 i = (i + 1) & RX_QUEUE_MASK;
495 continue;
496 }
b481de9c
ZY
497
498 rxq->queue[i] = NULL;
499
2f301227
ZY
500 pci_unmap_page(priv->pci_dev, rxb->page_dma,
501 PAGE_SIZE << priv->hw_params.rx_page_order,
502 PCI_DMA_FROMDEVICE);
503 pkt = rxb_addr(rxb);
b481de9c 504
f4989d9b
JB
505 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
506 len += sizeof(u32); /* account for status word */
507 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 508
b481de9c
ZY
509 /* Reclaim a command buffer only if this packet is a response
510 * to a (driver-originated) command.
511 * If the packet (e.g. Rx frame) originated from uCode,
512 * there is no command buffer to reclaim.
513 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
514 * but apparently a few don't get set; catch them here. */
515 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
516 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 517 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 518 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 519 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
520 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
521 (pkt->hdr.cmd != REPLY_TX);
522
7194207c
JB
523 /*
524 * Do the notification wait before RX handlers so
525 * even if the RX handler consumes the RXB we have
526 * access to it in the notification wait entry.
527 */
528 if (!list_empty(&priv->_agn.notif_waits)) {
529 struct iwl_notification_wait *w;
530
531 spin_lock(&priv->_agn.notif_wait_lock);
532 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
533 if (w->cmd == pkt->hdr.cmd) {
534 w->triggered = true;
535 if (w->fn)
09f18afe 536 w->fn(priv, pkt, w->fn_data);
7194207c
JB
537 }
538 }
539 spin_unlock(&priv->_agn.notif_wait_lock);
540
541 wake_up_all(&priv->_agn.notif_waitq);
542 }
4613e72d
CK
543 if (priv->pre_rx_handler)
544 priv->pre_rx_handler(priv, rxb);
7194207c 545
b481de9c
ZY
546 /* Based on type of command response or notification,
547 * handle those that need handling via function in
5b9f8cd3 548 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 549 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 550 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 551 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 552 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 553 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
554 } else {
555 /* No handling needed */
e1623446 556 IWL_DEBUG_RX(priv,
b481de9c
ZY
557 "r %d i %d No handler needed for %s, 0x%02x\n",
558 r, i, get_cmd_string(pkt->hdr.cmd),
559 pkt->hdr.cmd);
560 }
561
29b1b268
ZY
562 /*
563 * XXX: After here, we should always check rxb->page
564 * against NULL before touching it or its virtual
565 * memory (pkt). Because some rx_handler might have
566 * already taken or freed the pages.
567 */
568
b481de9c 569 if (reclaim) {
2f301227
ZY
570 /* Invoke any callbacks, transfer the buffer to caller,
571 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 572 * as we reclaim the driver command queue */
29b1b268 573 if (rxb->page)
17b88929 574 iwl_tx_cmd_complete(priv, rxb);
b481de9c 575 else
39aadf8c 576 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
577 }
578
7300515d
ZY
579 /* Reuse the page if possible. For notification packets and
580 * SKBs that fail to Rx correctly, add them back into the
581 * rx_free list for reuse later. */
582 spin_lock_irqsave(&rxq->lock, flags);
2f301227 583 if (rxb->page != NULL) {
7300515d
ZY
584 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
585 0, PAGE_SIZE << priv->hw_params.rx_page_order,
586 PCI_DMA_FROMDEVICE);
587 list_add_tail(&rxb->list, &rxq->rx_free);
588 rxq->free_count++;
589 } else
590 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 591
b481de9c 592 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 593
b481de9c 594 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
595 /* If there are a lot of unused frames,
596 * restock the Rx queue so ucode wont assert. */
597 if (fill_rx) {
598 count++;
599 if (count >= 8) {
7300515d 600 rxq->read = i;
54b81550 601 iwlagn_rx_replenish_now(priv);
5c0eef96
MA
602 count = 0;
603 }
604 }
b481de9c
ZY
605 }
606
607 /* Backtrack one entry */
7300515d 608 rxq->read = i;
4752c93c 609 if (fill_rx)
54b81550 610 iwlagn_rx_replenish_now(priv);
4752c93c 611 else
54b81550 612 iwlagn_rx_queue_restock(priv);
a55360e4 613}
a55360e4 614
ef850d7c
MA
615/* tasklet for iwlagn interrupt */
616static void iwl_irq_tasklet(struct iwl_priv *priv)
617{
618 u32 inta = 0;
619 u32 handled = 0;
620 unsigned long flags;
8756990f 621 u32 i;
ef850d7c
MA
622#ifdef CONFIG_IWLWIFI_DEBUG
623 u32 inta_mask;
624#endif
625
626 spin_lock_irqsave(&priv->lock, flags);
627
628 /* Ack/clear/reset pending uCode interrupts.
629 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
630 */
48a6be6a
SZ
631 /* There is a hardware bug in the interrupt mask function that some
632 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
633 * they are disabled in the CSR_INT_MASK register. Furthermore the
634 * ICT interrupt handling mechanism has another bug that might cause
635 * these unmasked interrupts fail to be detected. We workaround the
636 * hardware bugs here by ACKing all the possible interrupts so that
637 * interrupt coalescing can still be achieved.
638 */
4a35ecf8 639 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 640
a4c8b2a6 641 inta = priv->_agn.inta;
ef850d7c
MA
642
643#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 644 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
645 /* just for debug */
646 inta_mask = iwl_read32(priv, CSR_INT_MASK);
647 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
648 inta, inta_mask);
649 }
650#endif
2f301227
ZY
651
652 spin_unlock_irqrestore(&priv->lock, flags);
653
a4c8b2a6
JB
654 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
655 priv->_agn.inta = 0;
ef850d7c
MA
656
657 /* Now service all interrupt bits discovered above. */
658 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 659 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
660
661 /* Tell the device to stop sending interrupts */
662 iwl_disable_interrupts(priv);
663
664 priv->isr_stats.hw++;
665 iwl_irq_handle_error(priv);
666
667 handled |= CSR_INT_BIT_HW_ERR;
668
ef850d7c
MA
669 return;
670 }
671
672#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 673 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
674 /* NIC fires this, but we don't use it, redundant with WAKEUP */
675 if (inta & CSR_INT_BIT_SCD) {
676 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
677 "the frame/frames.\n");
678 priv->isr_stats.sch++;
679 }
680
681 /* Alive notification via Rx interrupt will do the real work */
682 if (inta & CSR_INT_BIT_ALIVE) {
683 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
684 priv->isr_stats.alive++;
685 }
686 }
687#endif
688 /* Safely ignore these bits for debug checks below */
689 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
690
691 /* HW RF KILL switch toggled */
692 if (inta & CSR_INT_BIT_RF_KILL) {
693 int hw_rf_kill = 0;
694 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
695 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
696 hw_rf_kill = 1;
697
4c423a2b 698 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
699 hw_rf_kill ? "disable radio" : "enable radio");
700
701 priv->isr_stats.rfkill++;
702
703 /* driver only loads ucode once setting the interface up.
704 * the driver allows loading the ucode even if the radio
705 * is killed. Hence update the killswitch state here. The
706 * rfkill handler will care about restarting if needed.
707 */
708 if (!test_bit(STATUS_ALIVE, &priv->status)) {
709 if (hw_rf_kill)
710 set_bit(STATUS_RF_KILL_HW, &priv->status);
711 else
712 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 713 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
714 }
715
716 handled |= CSR_INT_BIT_RF_KILL;
717 }
718
719 /* Chip got too hot and stopped itself */
720 if (inta & CSR_INT_BIT_CT_KILL) {
721 IWL_ERR(priv, "Microcode CT kill error detected.\n");
722 priv->isr_stats.ctkill++;
723 handled |= CSR_INT_BIT_CT_KILL;
724 }
725
726 /* Error detected by uCode */
727 if (inta & CSR_INT_BIT_SW_ERR) {
728 IWL_ERR(priv, "Microcode SW error detected. "
729 " Restarting 0x%X.\n", inta);
730 priv->isr_stats.sw++;
ef850d7c
MA
731 iwl_irq_handle_error(priv);
732 handled |= CSR_INT_BIT_SW_ERR;
733 }
734
735 /* uCode wakes up after power-down sleep */
736 if (inta & CSR_INT_BIT_WAKEUP) {
737 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
738 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC
739 for (i = 0; i < priv->hw_params.max_txq_num; i++)
740 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA
741
742 priv->isr_stats.wakeup++;
743
744 handled |= CSR_INT_BIT_WAKEUP;
745 }
746
747 /* All uCode command responses, including Tx command responses,
748 * Rx "responses" (frame-received notification), and other
749 * notifications from uCode come through here*/
40cefda9
MA
750 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
751 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 752 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
753 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
754 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
755 iwl_write32(priv, CSR_FH_INT_STATUS,
f7d046f9 756 CSR_FH_INT_RX_MASK);
40cefda9
MA
757 }
758 if (inta & CSR_INT_BIT_RX_PERIODIC) {
759 handled |= CSR_INT_BIT_RX_PERIODIC;
760 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
761 }
762 /* Sending RX interrupt require many steps to be done in the
763 * the device:
764 * 1- write interrupt to current index in ICT table.
765 * 2- dma RX frame.
766 * 3- update RX shared data to indicate last write index.
767 * 4- send interrupt.
768 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC
769 * but the shared data changes does not reflect this;
770 * periodic interrupt will detect any dangling Rx activity.
40cefda9 771 */
74ba67ed
BC
772
773 /* Disable periodic interrupt; we use it as just a one-shot. */
774 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 775 CSR_INT_PERIODIC_DIS);
ef850d7c 776 iwl_rx_handle(priv);
74ba67ed
BC
777
778 /*
779 * Enable periodic interrupt in 8 msec only if we received
780 * real RX interrupt (instead of just periodic int), to catch
781 * any dangling Rx interrupt. If it was just the periodic
782 * interrupt, there was no dangling Rx activity, and no need
783 * to extend the periodic interrupt; one-shot is enough.
784 */
40cefda9 785 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 786 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA
787 CSR_INT_PERIODIC_ENA);
788
ef850d7c 789 priv->isr_stats.rx++;
ef850d7c
MA
790 }
791
c72cd19f 792 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c 793 if (inta & CSR_INT_BIT_FH_TX) {
f7d046f9 794 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
c72cd19f 795 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
796 priv->isr_stats.tx++;
797 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 798 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
799 priv->ucode_write_complete = 1;
800 wake_up_interruptible(&priv->wait_command_queue);
801 }
802
803 if (inta & ~handled) {
804 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
805 priv->isr_stats.unhandled++;
806 }
807
40cefda9 808 if (inta & ~(priv->inta_mask)) {
ef850d7c 809 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 810 inta & ~priv->inta_mask);
ef850d7c
MA
811 }
812
ef850d7c 813 /* Re-enable all interrupts */
62e45c14 814 /* only Re-enable if disabled by irq */
ef850d7c
MA
815 if (test_bit(STATUS_INT_ENABLED, &priv->status))
816 iwl_enable_interrupts(priv);
3dd823e6
DF
817 /* Re-enable RF_KILL if it occurred */
818 else if (handled & CSR_INT_BIT_RF_KILL)
819 iwl_enable_rfkill_int(priv);
ef850d7c
MA
820}
821
7d47618a
EG
822/*****************************************************************************
823 *
824 * sysfs attributes
825 *
826 *****************************************************************************/
827
828#ifdef CONFIG_IWLWIFI_DEBUG
829
830/*
831 * The following adds a new attribute to the sysfs representation
832 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
833 * used for controlling the debug level.
834 *
835 * See the level definitions in iwl for details.
836 *
837 * The debug_level being managed using sysfs below is a per device debug
838 * level that is used instead of the global debug level if it (the per
839 * device debug level) is set.
840 */
841static ssize_t show_debug_level(struct device *d,
842 struct device_attribute *attr, char *buf)
843{
844 struct iwl_priv *priv = dev_get_drvdata(d);
845 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
846}
847static ssize_t store_debug_level(struct device *d,
848 struct device_attribute *attr,
849 const char *buf, size_t count)
850{
851 struct iwl_priv *priv = dev_get_drvdata(d);
852 unsigned long val;
853 int ret;
854
855 ret = strict_strtoul(buf, 0, &val);
856 if (ret)
857 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
858 else {
859 priv->debug_level = val;
860 if (iwl_alloc_traffic_mem(priv))
861 IWL_ERR(priv,
862 "Not enough memory to generate traffic log\n");
863 }
864 return strnlen(buf, count);
865}
866
867static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
868 show_debug_level, store_debug_level);
869
870
871#endif /* CONFIG_IWLWIFI_DEBUG */
872
873
874static ssize_t show_temperature(struct device *d,
875 struct device_attribute *attr, char *buf)
876{
877 struct iwl_priv *priv = dev_get_drvdata(d);
878
879 if (!iwl_is_alive(priv))
880 return -EAGAIN;
881
882 return sprintf(buf, "%d\n", priv->temperature);
883}
884
885static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
886
887static ssize_t show_tx_power(struct device *d,
888 struct device_attribute *attr, char *buf)
889{
890 struct iwl_priv *priv = dev_get_drvdata(d);
891
892 if (!iwl_is_ready_rf(priv))
893 return sprintf(buf, "off\n");
894 else
895 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
896}
897
898static ssize_t store_tx_power(struct device *d,
899 struct device_attribute *attr,
900 const char *buf, size_t count)
901{
902 struct iwl_priv *priv = dev_get_drvdata(d);
903 unsigned long val;
904 int ret;
905
906 ret = strict_strtoul(buf, 10, &val);
907 if (ret)
908 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
909 else {
910 ret = iwl_set_tx_power(priv, val, false);
911 if (ret)
912 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
913 ret);
914 else
915 ret = count;
916 }
917 return ret;
918}
919
920static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
921
7d47618a
EG
922static struct attribute *iwl_sysfs_entries[] = {
923 &dev_attr_temperature.attr,
924 &dev_attr_tx_power.attr,
7d47618a
EG
925#ifdef CONFIG_IWLWIFI_DEBUG
926 &dev_attr_debug_level.attr,
927#endif
928 NULL
929};
930
931static struct attribute_group iwl_attribute_group = {
932 .name = NULL, /* put in device directory */
933 .attrs = iwl_sysfs_entries,
934};
935
b481de9c
ZY
936/******************************************************************************
937 *
938 * uCode download functions
939 *
940 ******************************************************************************/
941
dbf28e21
JB
942static void iwl_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
943{
944 if (desc->v_addr)
945 dma_free_coherent(&pci_dev->dev, desc->len,
946 desc->v_addr, desc->p_addr);
947 desc->v_addr = NULL;
948 desc->len = 0;
949}
950
951static void iwl_free_fw_img(struct pci_dev *pci_dev, struct fw_img *img)
952{
953 iwl_free_fw_desc(pci_dev, &img->code);
954 iwl_free_fw_desc(pci_dev, &img->data);
955}
956
957static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc,
958 const void *data, size_t len)
959{
960 if (!len) {
961 desc->v_addr = NULL;
962 return -EINVAL;
963 }
964
965 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, len,
966 &desc->p_addr, GFP_KERNEL);
967 if (!desc->v_addr)
968 return -ENOMEM;
969 desc->len = len;
970 memcpy(desc->v_addr, data, len);
971 return 0;
972}
973
5b9f8cd3 974static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 975{
dbf28e21
JB
976 iwl_free_fw_img(priv->pci_dev, &priv->ucode_rt);
977 iwl_free_fw_img(priv->pci_dev, &priv->ucode_init);
b481de9c
ZY
978}
979
dd7a2509
JB
980struct iwlagn_ucode_capabilities {
981 u32 max_probe_length;
6a822d06 982 u32 standard_phy_calibration_size;
3997ff39 983 u32 flags;
dd7a2509 984};
edcdf8b2 985
b08dfd04 986static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB
987static int iwl_mac_setup_register(struct iwl_priv *priv,
988 struct iwlagn_ucode_capabilities *capa);
b08dfd04 989
39396085
JS
990#define UCODE_EXPERIMENTAL_INDEX 100
991#define UCODE_EXPERIMENTAL_TAG "exp"
992
b08dfd04
JB
993static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
994{
995 const char *name_pre = priv->cfg->fw_name_pre;
39396085 996 char tag[8];
b08dfd04 997
39396085
JS
998 if (first) {
999#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1000 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1001 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1002 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1003#endif
b08dfd04 1004 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS
1005 sprintf(tag, "%d", priv->fw_index);
1006 } else {
b08dfd04 1007 priv->fw_index--;
39396085
JS
1008 sprintf(tag, "%d", priv->fw_index);
1009 }
b08dfd04
JB
1010
1011 if (priv->fw_index < priv->cfg->ucode_api_min) {
1012 IWL_ERR(priv, "no suitable firmware found!\n");
1013 return -ENOENT;
1014 }
1015
39396085 1016 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1017
39396085
JS
1018 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1019 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1020 ? "EXPERIMENTAL " : "",
b08dfd04
JB
1021 priv->firmware_name);
1022
1023 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1024 &priv->pci_dev->dev, GFP_KERNEL, priv,
1025 iwl_ucode_callback);
1026}
1027
0e9a44dc 1028struct iwlagn_firmware_pieces {
1fc35276
JB
1029 const void *inst, *data, *init, *init_data;
1030 size_t inst_size, data_size, init_size, init_data_size;
0e9a44dc
JB
1031
1032 u32 build;
b2e640d4
JB
1033
1034 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1035 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB
1036};
1037
1038static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1039 const struct firmware *ucode_raw,
1040 struct iwlagn_firmware_pieces *pieces)
1041{
1042 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1043 u32 api_ver, hdr_size;
1044 const u8 *src;
1045
1046 priv->ucode_ver = le32_to_cpu(ucode->ver);
1047 api_ver = IWL_UCODE_API(priv->ucode_ver);
1048
1049 switch (api_ver) {
1050 default:
f7d046f9
WYG
1051 hdr_size = 28;
1052 if (ucode_raw->size < hdr_size) {
1053 IWL_ERR(priv, "File size too small!\n");
1054 return -EINVAL;
0e9a44dc 1055 }
f7d046f9
WYG
1056 pieces->build = le32_to_cpu(ucode->u.v2.build);
1057 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1058 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1059 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1060 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
f7d046f9
WYG
1061 src = ucode->u.v2.data;
1062 break;
0e9a44dc
JB
1063 case 0:
1064 case 1:
1065 case 2:
1066 hdr_size = 24;
1067 if (ucode_raw->size < hdr_size) {
1068 IWL_ERR(priv, "File size too small!\n");
1069 return -EINVAL;
1070 }
1071 pieces->build = 0;
1072 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1073 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1074 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1075 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
0e9a44dc
JB
1076 src = ucode->u.v1.data;
1077 break;
1078 }
1079
1080 /* Verify size of file vs. image size info in file's header */
1081 if (ucode_raw->size != hdr_size + pieces->inst_size +
1082 pieces->data_size + pieces->init_size +
1fc35276 1083 pieces->init_data_size) {
0e9a44dc
JB
1084
1085 IWL_ERR(priv,
1086 "uCode file size %d does not match expected size\n",
1087 (int)ucode_raw->size);
1088 return -EINVAL;
1089 }
1090
1091 pieces->inst = src;
1092 src += pieces->inst_size;
1093 pieces->data = src;
1094 src += pieces->data_size;
1095 pieces->init = src;
1096 src += pieces->init_size;
1097 pieces->init_data = src;
1098 src += pieces->init_data_size;
0e9a44dc
JB
1099
1100 return 0;
1101}
1102
dd7a2509
JB
1103static int iwlagn_wanted_ucode_alternative = 1;
1104
1105static int iwlagn_load_firmware(struct iwl_priv *priv,
1106 const struct firmware *ucode_raw,
1107 struct iwlagn_firmware_pieces *pieces,
1108 struct iwlagn_ucode_capabilities *capa)
1109{
1110 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1111 struct iwl_ucode_tlv *tlv;
1112 size_t len = ucode_raw->size;
1113 const u8 *data;
1114 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1115 u64 alternatives;
ad8d8333
WYG
1116 u32 tlv_len;
1117 enum iwl_ucode_tlv_type tlv_type;
1118 const u8 *tlv_data;
dd7a2509 1119
ad8d8333
WYG
1120 if (len < sizeof(*ucode)) {
1121 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1122 return -EINVAL;
ad8d8333 1123 }
dd7a2509 1124
ad8d8333
WYG
1125 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1126 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1127 le32_to_cpu(ucode->magic));
dd7a2509 1128 return -EINVAL;
ad8d8333 1129 }
dd7a2509
JB
1130
1131 /*
1132 * Check which alternatives are present, and "downgrade"
1133 * when the chosen alternative is not present, warning
1134 * the user when that happens. Some files may not have
1135 * any alternatives, so don't warn in that case.
1136 */
1137 alternatives = le64_to_cpu(ucode->alternatives);
1138 tmp = wanted_alternative;
1139 if (wanted_alternative > 63)
1140 wanted_alternative = 63;
1141 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1142 wanted_alternative--;
1143 if (wanted_alternative && wanted_alternative != tmp)
1144 IWL_WARN(priv,
1145 "uCode alternative %d not available, choosing %d\n",
1146 tmp, wanted_alternative);
1147
1148 priv->ucode_ver = le32_to_cpu(ucode->ver);
1149 pieces->build = le32_to_cpu(ucode->build);
1150 data = ucode->data;
1151
1152 len -= sizeof(*ucode);
1153
704da534 1154 while (len >= sizeof(*tlv)) {
dd7a2509 1155 u16 tlv_alt;
dd7a2509
JB
1156
1157 len -= sizeof(*tlv);
1158 tlv = (void *)data;
1159
1160 tlv_len = le32_to_cpu(tlv->length);
1161 tlv_type = le16_to_cpu(tlv->type);
1162 tlv_alt = le16_to_cpu(tlv->alternative);
1163 tlv_data = tlv->data;
1164
ad8d8333
WYG
1165 if (len < tlv_len) {
1166 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1167 len, tlv_len);
dd7a2509 1168 return -EINVAL;
ad8d8333 1169 }
dd7a2509
JB
1170 len -= ALIGN(tlv_len, 4);
1171 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1172
1173 /*
1174 * Alternative 0 is always valid.
1175 *
1176 * Skip alternative TLVs that are not selected.
1177 */
1178 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1179 continue;
1180
1181 switch (tlv_type) {
1182 case IWL_UCODE_TLV_INST:
1183 pieces->inst = tlv_data;
1184 pieces->inst_size = tlv_len;
1185 break;
1186 case IWL_UCODE_TLV_DATA:
1187 pieces->data = tlv_data;
1188 pieces->data_size = tlv_len;
1189 break;
1190 case IWL_UCODE_TLV_INIT:
1191 pieces->init = tlv_data;
1192 pieces->init_size = tlv_len;
1193 break;
1194 case IWL_UCODE_TLV_INIT_DATA:
1195 pieces->init_data = tlv_data;
1196 pieces->init_data_size = tlv_len;
1197 break;
1198 case IWL_UCODE_TLV_BOOT:
1fc35276 1199 IWL_ERR(priv, "Found unexpected BOOT ucode\n");
dd7a2509
JB
1200 break;
1201 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB
1202 if (tlv_len != sizeof(u32))
1203 goto invalid_tlv_len;
1204 capa->max_probe_length =
ad8d8333 1205 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1206 break;
ece9c4ee
JB
1207 case IWL_UCODE_TLV_PAN:
1208 if (tlv_len)
1209 goto invalid_tlv_len;
3997ff39
JB
1210 capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1211 break;
1212 case IWL_UCODE_TLV_FLAGS:
1213 /* must be at least one u32 */
1214 if (tlv_len < sizeof(u32))
1215 goto invalid_tlv_len;
1216 /* and a proper number of u32s */
1217 if (tlv_len % sizeof(u32))
1218 goto invalid_tlv_len;
1219 /*
1220 * This driver only reads the first u32 as
1221 * right now no more features are defined,
1222 * if that changes then either the driver
1223 * will not work with the new firmware, or
1224 * it'll not take advantage of new features.
1225 */
1226 capa->flags = le32_to_cpup((__le32 *)tlv_data);
ece9c4ee 1227 break;
b2e640d4 1228 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB
1229 if (tlv_len != sizeof(u32))
1230 goto invalid_tlv_len;
1231 pieces->init_evtlog_ptr =
ad8d8333 1232 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB
1233 break;
1234 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB
1235 if (tlv_len != sizeof(u32))
1236 goto invalid_tlv_len;
1237 pieces->init_evtlog_size =
ad8d8333 1238 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB
1239 break;
1240 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB
1241 if (tlv_len != sizeof(u32))
1242 goto invalid_tlv_len;
1243 pieces->init_errlog_ptr =
ad8d8333 1244 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB
1245 break;
1246 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB
1247 if (tlv_len != sizeof(u32))
1248 goto invalid_tlv_len;
1249 pieces->inst_evtlog_ptr =
ad8d8333 1250 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB
1251 break;
1252 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB
1253 if (tlv_len != sizeof(u32))
1254 goto invalid_tlv_len;
1255 pieces->inst_evtlog_size =
ad8d8333 1256 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB
1257 break;
1258 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB
1259 if (tlv_len != sizeof(u32))
1260 goto invalid_tlv_len;
1261 pieces->inst_errlog_ptr =
ad8d8333 1262 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 1263 break;
c8312fac
WYG
1264 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1265 if (tlv_len)
704da534
JB
1266 goto invalid_tlv_len;
1267 priv->enhance_sensitivity_table = true;
c8312fac 1268 break;
6a822d06 1269 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB
1270 if (tlv_len != sizeof(u32))
1271 goto invalid_tlv_len;
1272 capa->standard_phy_calibration_size =
6a822d06
WYG
1273 le32_to_cpup((__le32 *)tlv_data);
1274 break;
dd7a2509 1275 default:
6fc3ba99 1276 IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB
1277 break;
1278 }
1279 }
1280
ad8d8333
WYG
1281 if (len) {
1282 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1283 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 1284 return -EINVAL;
ad8d8333 1285 }
dd7a2509 1286
704da534
JB
1287 return 0;
1288
1289 invalid_tlv_len:
1290 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1291 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1292
1293 return -EINVAL;
dd7a2509
JB
1294}
1295
b481de9c 1296/**
b08dfd04 1297 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 1298 *
b08dfd04
JB
1299 * If loaded successfully, copies the firmware into buffers
1300 * for the card to fetch (via DMA).
b481de9c 1301 */
b08dfd04 1302static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 1303{
b08dfd04 1304 struct iwl_priv *priv = context;
cc0f555d 1305 struct iwl_ucode_header *ucode;
0e9a44dc
JB
1306 int err;
1307 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC
1308 const unsigned int api_max = priv->cfg->ucode_api_max;
1309 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 1310 u32 api_ver;
3e4de761 1311 char buildstr[25];
0e9a44dc 1312 u32 build;
dd7a2509
JB
1313 struct iwlagn_ucode_capabilities ucode_capa = {
1314 .max_probe_length = 200,
6a822d06 1315 .standard_phy_calibration_size =
642454cc 1316 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 1317 };
0e9a44dc
JB
1318
1319 memset(&pieces, 0, sizeof(pieces));
b481de9c 1320
b08dfd04 1321 if (!ucode_raw) {
39396085
JS
1322 if (priv->fw_index <= priv->cfg->ucode_api_max)
1323 IWL_ERR(priv,
1324 "request for firmware file '%s' failed.\n",
1325 priv->firmware_name);
b08dfd04 1326 goto try_again;
b481de9c
ZY
1327 }
1328
b08dfd04
JB
1329 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1330 priv->firmware_name, ucode_raw->size);
b481de9c 1331
22adba2a
JB
1332 /* Make sure that we got at least the API version number */
1333 if (ucode_raw->size < 4) {
15b1687c 1334 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 1335 goto try_again;
b481de9c
ZY
1336 }
1337
1338 /* Data from ucode file: header followed by uCode images */
cc0f555d 1339 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1340
0e9a44dc
JB
1341 if (ucode->ver)
1342 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1343 else
dd7a2509
JB
1344 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1345 &ucode_capa);
22adba2a 1346
0e9a44dc
JB
1347 if (err)
1348 goto try_again;
b481de9c 1349
a0987a8d 1350 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 1351 build = pieces.build;
a0987a8d 1352
0e9a44dc
JB
1353 /*
1354 * api_ver should match the api version forming part of the
1355 * firmware filename ... but we don't check for that and only rely
1356 * on the API version read from firmware header from here on forward
1357 */
65cccfb0
WYG
1358 /* no api version check required for experimental uCode */
1359 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1360 if (api_ver < api_min || api_ver > api_max) {
1361 IWL_ERR(priv,
1362 "Driver unable to support your firmware API. "
1363 "Driver supports v%u, firmware is v%u.\n",
1364 api_max, api_ver);
1365 goto try_again;
1366 }
b08dfd04 1367
65cccfb0
WYG
1368 if (api_ver != api_max)
1369 IWL_ERR(priv,
1370 "Firmware has old API version. Expected v%u, "
1371 "got v%u. New firmware can be obtained "
1372 "from http://www.intellinuxwireless.org.\n",
1373 api_max, api_ver);
1374 }
a0987a8d 1375
3e4de761 1376 if (build)
39396085
JS
1377 sprintf(buildstr, " build %u%s", build,
1378 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1379 ? " (EXP)" : "");
3e4de761
JB
1380 else
1381 buildstr[0] = '\0';
1382
1383 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1384 IWL_UCODE_MAJOR(priv->ucode_ver),
1385 IWL_UCODE_MINOR(priv->ucode_ver),
1386 IWL_UCODE_API(priv->ucode_ver),
1387 IWL_UCODE_SERIAL(priv->ucode_ver),
1388 buildstr);
a0987a8d 1389
5ebeb5a6
RC
1390 snprintf(priv->hw->wiphy->fw_version,
1391 sizeof(priv->hw->wiphy->fw_version),
3e4de761 1392 "%u.%u.%u.%u%s",
5ebeb5a6
RC
1393 IWL_UCODE_MAJOR(priv->ucode_ver),
1394 IWL_UCODE_MINOR(priv->ucode_ver),
1395 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB
1396 IWL_UCODE_SERIAL(priv->ucode_ver),
1397 buildstr);
b481de9c 1398
b08dfd04
JB
1399 /*
1400 * For any of the failures below (before allocating pci memory)
1401 * we will try to load a version with a smaller API -- maybe the
1402 * user just got a corrupted version of the latest API.
1403 */
1404
0e9a44dc
JB
1405 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1406 priv->ucode_ver);
1407 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1408 pieces.inst_size);
1409 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1410 pieces.data_size);
1411 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1412 pieces.init_size);
1413 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1414 pieces.init_data_size);
b481de9c
ZY
1415
1416 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB
1417 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1418 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1419 pieces.inst_size);
b08dfd04 1420 goto try_again;
b481de9c
ZY
1421 }
1422
0e9a44dc
JB
1423 if (pieces.data_size > priv->hw_params.max_data_size) {
1424 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1425 pieces.data_size);
b08dfd04 1426 goto try_again;
b481de9c 1427 }
0e9a44dc
JB
1428
1429 if (pieces.init_size > priv->hw_params.max_inst_size) {
1430 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1431 pieces.init_size);
b08dfd04 1432 goto try_again;
b481de9c 1433 }
0e9a44dc
JB
1434
1435 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1436 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1437 pieces.init_data_size);
b08dfd04 1438 goto try_again;
b481de9c 1439 }
0e9a44dc 1440
b481de9c
ZY
1441 /* Allocate ucode buffers for card's bus-master loading ... */
1442
1443 /* Runtime instructions and 2 copies of data:
1444 * 1) unmodified from disk
1445 * 2) backup cache for save/restore during power-downs */
dbf28e21
JB
1446 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.code,
1447 pieces.inst, pieces.inst_size))
1448 goto err_pci_alloc;
1449 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.data,
1450 pieces.data, pieces.data_size))
1f304e4e
ZY
1451 goto err_pci_alloc;
1452
b481de9c 1453 /* Initialization instructions and data */
0e9a44dc 1454 if (pieces.init_size && pieces.init_data_size) {
dbf28e21
JB
1455 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.code,
1456 pieces.init, pieces.init_size))
1457 goto err_pci_alloc;
1458 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.data,
1459 pieces.init_data, pieces.init_data_size))
90e759d1
TW
1460 goto err_pci_alloc;
1461 }
b481de9c 1462
b2e640d4
JB
1463 /* Now that we can no longer fail, copy information */
1464
1465 /*
1466 * The (size - 16) / 12 formula is based on the information recorded
1467 * for each event, which is of mode 1 (including timestamp) for all
1468 * new microcodes that include this information.
1469 */
1470 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1471 if (pieces.init_evtlog_size)
1472 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1473 else
7cb1b088
WYG
1474 priv->_agn.init_evtlog_size =
1475 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB
1476 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1477 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1478 if (pieces.inst_evtlog_size)
1479 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1480 else
7cb1b088
WYG
1481 priv->_agn.inst_evtlog_size =
1482 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB
1483 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1484
d2690c0d
JB
1485 priv->new_scan_threshold_behaviour =
1486 !!(ucode_capa.flags & IWL_UCODE_TLV_FLAGS_NEWSCAN);
1487
3997ff39 1488 if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
ece9c4ee 1489 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
c10afb6e 1490 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
ece9c4ee
JB
1491 } else
1492 priv->sta_key_max_num = STA_KEY_MAX_NUM;
c10afb6e 1493
17445b8c
JB
1494 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1495 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1496 else
1497 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1498
6a822d06
WYG
1499 /*
1500 * figure out the offset of chain noise reset and gain commands
1501 * base on the size of standard phy calibration commands table size
1502 */
1503 if (ucode_capa.standard_phy_calibration_size >
1504 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1505 ucode_capa.standard_phy_calibration_size =
1506 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1507
1508 priv->_agn.phy_calib_chain_noise_reset_cmd =
1509 ucode_capa.standard_phy_calibration_size;
1510 priv->_agn.phy_calib_chain_noise_gain_cmd =
1511 ucode_capa.standard_phy_calibration_size + 1;
1512
b08dfd04
JB
1513 /**************************************************
1514 * This is still part of probe() in a sense...
1515 *
1516 * 9. Setup and register with mac80211 and debugfs
1517 **************************************************/
dd7a2509 1518 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB
1519 if (err)
1520 goto out_unbind;
1521
1522 err = iwl_dbgfs_register(priv, DRV_NAME);
1523 if (err)
1524 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1525
7d47618a
EG
1526 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1527 &iwl_attribute_group);
1528 if (err) {
1529 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1530 goto out_unbind;
1531 }
1532
b481de9c
ZY
1533 /* We have our copies now, allow OS release its copies */
1534 release_firmware(ucode_raw);
a15707d8 1535 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB
1536 return;
1537
1538 try_again:
1539 /* try next, if any */
1540 if (iwl_request_firmware(priv, false))
1541 goto out_unbind;
1542 release_firmware(ucode_raw);
1543 return;
b481de9c
ZY
1544
1545 err_pci_alloc:
15b1687c 1546 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 1547 iwl_dealloc_ucode_pci(priv);
b08dfd04 1548 out_unbind:
a15707d8 1549 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 1550 device_release_driver(&priv->pci_dev->dev);
b481de9c 1551 release_firmware(ucode_raw);
b481de9c
ZY
1552}
1553
b7a79404
RC
1554static const char *desc_lookup_text[] = {
1555 "OK",
1556 "FAIL",
1557 "BAD_PARAM",
1558 "BAD_CHECKSUM",
1559 "NMI_INTERRUPT_WDG",
1560 "SYSASSERT",
1561 "FATAL_ERROR",
1562 "BAD_COMMAND",
1563 "HW_ERROR_TUNE_LOCK",
1564 "HW_ERROR_TEMPERATURE",
1565 "ILLEGAL_CHAN_FREQ",
1566 "VCC_NOT_STABLE",
1567 "FH_ERROR",
1568 "NMI_INTERRUPT_HOST",
1569 "NMI_INTERRUPT_ACTION_PT",
1570 "NMI_INTERRUPT_UNKNOWN",
1571 "UCODE_VERSION_MISMATCH",
1572 "HW_ERROR_ABS_LOCK",
1573 "HW_ERROR_CAL_LOCK_FAIL",
1574 "NMI_INTERRUPT_INST_ACTION_PT",
1575 "NMI_INTERRUPT_DATA_ACTION_PT",
1576 "NMI_TRM_HW_ER",
1577 "NMI_INTERRUPT_TRM",
1578 "NMI_INTERRUPT_BREAK_POINT"
1579 "DEBUG_0",
1580 "DEBUG_1",
1581 "DEBUG_2",
1582 "DEBUG_3",
b7a79404
RC
1583};
1584
4b58645c
JS
1585static struct { char *name; u8 num; } advanced_lookup[] = {
1586 { "NMI_INTERRUPT_WDG", 0x34 },
1587 { "SYSASSERT", 0x35 },
1588 { "UCODE_VERSION_MISMATCH", 0x37 },
1589 { "BAD_COMMAND", 0x38 },
1590 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1591 { "FATAL_ERROR", 0x3D },
1592 { "NMI_TRM_HW_ERR", 0x46 },
1593 { "NMI_INTERRUPT_TRM", 0x4C },
1594 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1595 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1596 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1597 { "NMI_INTERRUPT_HOST", 0x66 },
1598 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1599 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1600 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1601 { "ADVANCED_SYSASSERT", 0 },
1602};
1603
1604static const char *desc_lookup(u32 num)
b7a79404 1605{
4b58645c
JS
1606 int i;
1607 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 1608
4b58645c
JS
1609 if (num < max)
1610 return desc_lookup_text[num];
b7a79404 1611
4b58645c
JS
1612 max = ARRAY_SIZE(advanced_lookup) - 1;
1613 for (i = 0; i < max; i++) {
1614 if (advanced_lookup[i].num == num)
6eab04a8 1615 break;
4b58645c
JS
1616 }
1617 return advanced_lookup[i].name;
b7a79404
RC
1618}
1619
1620#define ERROR_START_OFFSET (1 * sizeof(u32))
1621#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1622
1623void iwl_dump_nic_error_log(struct iwl_priv *priv)
1624{
50650547 1625 u32 base;
e46f6538 1626 struct iwl_error_event_table table;
b7a79404 1627
d7d5783c 1628 base = priv->device_pointers.error_event_table;
ca7966c8 1629 if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
b2e640d4
JB
1630 if (!base)
1631 base = priv->_agn.init_errlog_ptr;
1632 } else {
b2e640d4
JB
1633 if (!base)
1634 base = priv->_agn.inst_errlog_ptr;
1635 }
b7a79404
RC
1636
1637 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1638 IWL_ERR(priv,
1639 "Not valid error log pointer 0x%08X for %s uCode\n",
ca7966c8
JB
1640 base,
1641 (priv->ucode_type == UCODE_SUBTYPE_INIT)
1642 ? "Init" : "RT");
b7a79404
RC
1643 return;
1644 }
1645
e46f6538
JB
1646 iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
1647
50650547 1648 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
b7a79404
RC
1649 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1650 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
50650547 1651 priv->status, table.valid);
b7a79404
RC
1652 }
1653
50650547
WYG
1654 priv->isr_stats.err_code = table.error_id;
1655
1656 trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
1657 table.data1, table.data2, table.line,
1658 table.blink1, table.blink2, table.ilink1,
1659 table.ilink2, table.bcon_time, table.gp1,
1660 table.gp2, table.gp3, table.ucode_ver,
1661 table.hw_ver, table.brd_ver);
1662 IWL_ERR(priv, "0x%08X | %-28s\n", table.error_id,
1663 desc_lookup(table.error_id));
1664 IWL_ERR(priv, "0x%08X | uPc\n", table.pc);
1665 IWL_ERR(priv, "0x%08X | branchlink1\n", table.blink1);
1666 IWL_ERR(priv, "0x%08X | branchlink2\n", table.blink2);
1667 IWL_ERR(priv, "0x%08X | interruptlink1\n", table.ilink1);
1668 IWL_ERR(priv, "0x%08X | interruptlink2\n", table.ilink2);
1669 IWL_ERR(priv, "0x%08X | data1\n", table.data1);
1670 IWL_ERR(priv, "0x%08X | data2\n", table.data2);
1671 IWL_ERR(priv, "0x%08X | line\n", table.line);
1672 IWL_ERR(priv, "0x%08X | beacon time\n", table.bcon_time);
1673 IWL_ERR(priv, "0x%08X | tsf low\n", table.tsf_low);
1674 IWL_ERR(priv, "0x%08X | tsf hi\n", table.tsf_hi);
1675 IWL_ERR(priv, "0x%08X | time gp1\n", table.gp1);
1676 IWL_ERR(priv, "0x%08X | time gp2\n", table.gp2);
1677 IWL_ERR(priv, "0x%08X | time gp3\n", table.gp3);
1678 IWL_ERR(priv, "0x%08X | uCode version\n", table.ucode_ver);
1679 IWL_ERR(priv, "0x%08X | hw version\n", table.hw_ver);
1680 IWL_ERR(priv, "0x%08X | board version\n", table.brd_ver);
1681 IWL_ERR(priv, "0x%08X | hcmd\n", table.hcmd);
b7a79404
RC
1682}
1683
1684#define EVENT_START_OFFSET (4 * sizeof(u32))
1685
1686/**
1687 * iwl_print_event_log - Dump error event log to syslog
1688 *
1689 */
b03d7d0f
WYG
1690static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1691 u32 num_events, u32 mode,
1692 int pos, char **buf, size_t bufsz)
b7a79404
RC
1693{
1694 u32 i;
1695 u32 base; /* SRAM byte address of event log header */
1696 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1697 u32 ptr; /* SRAM byte address of log data */
1698 u32 ev, time, data; /* event log data */
e5854471 1699 unsigned long reg_flags;
b7a79404
RC
1700
1701 if (num_events == 0)
b03d7d0f 1702 return pos;
b2e640d4 1703
d7d5783c 1704 base = priv->device_pointers.log_event_table;
ca7966c8 1705 if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
b2e640d4
JB
1706 if (!base)
1707 base = priv->_agn.init_evtlog_ptr;
1708 } else {
b2e640d4
JB
1709 if (!base)
1710 base = priv->_agn.inst_evtlog_ptr;
1711 }
b7a79404
RC
1712
1713 if (mode == 0)
1714 event_size = 2 * sizeof(u32);
1715 else
1716 event_size = 3 * sizeof(u32);
1717
1718 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1719
e5854471
BC
1720 /* Make sure device is powered up for SRAM reads */
1721 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1722 iwl_grab_nic_access(priv);
1723
1724 /* Set starting address; reads will auto-increment */
02a7fa00 1725 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
e5854471
BC
1726 rmb();
1727
b7a79404
RC
1728 /* "time" is actually "data" for mode 0 (no timestamp).
1729 * place event id # at far right for easier visual parsing. */
1730 for (i = 0; i < num_events; i++) {
02a7fa00
JB
1731 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1732 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1733 if (mode == 0) {
1734 /* data, ev */
b03d7d0f
WYG
1735 if (bufsz) {
1736 pos += scnprintf(*buf + pos, bufsz - pos,
1737 "EVT_LOG:0x%08x:%04u\n",
1738 time, ev);
1739 } else {
1740 trace_iwlwifi_dev_ucode_event(priv, 0,
1741 time, ev);
1742 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1743 time, ev);
1744 }
b7a79404 1745 } else {
02a7fa00 1746 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG
1747 if (bufsz) {
1748 pos += scnprintf(*buf + pos, bufsz - pos,
1749 "EVT_LOGT:%010u:0x%08x:%04u\n",
1750 time, data, ev);
1751 } else {
1752 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 1753 time, data, ev);
b03d7d0f
WYG
1754 trace_iwlwifi_dev_ucode_event(priv, time,
1755 data, ev);
1756 }
b7a79404
RC
1757 }
1758 }
e5854471
BC
1759
1760 /* Allow device to power down */
1761 iwl_release_nic_access(priv);
1762 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 1763 return pos;
b7a79404
RC
1764}
1765
c341ddb2
WYG
1766/**
1767 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1768 */
b03d7d0f
WYG
1769static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
1770 u32 num_wraps, u32 next_entry,
1771 u32 size, u32 mode,
1772 int pos, char **buf, size_t bufsz)
c341ddb2
WYG
1773{
1774 /*
1775 * display the newest DEFAULT_LOG_ENTRIES entries
1776 * i.e the entries just before the next ont that uCode would fill.
1777 */
1778 if (num_wraps) {
1779 if (next_entry < size) {
b03d7d0f
WYG
1780 pos = iwl_print_event_log(priv,
1781 capacity - (size - next_entry),
1782 size - next_entry, mode,
1783 pos, buf, bufsz);
1784 pos = iwl_print_event_log(priv, 0,
1785 next_entry, mode,
1786 pos, buf, bufsz);
c341ddb2 1787 } else
b03d7d0f
WYG
1788 pos = iwl_print_event_log(priv, next_entry - size,
1789 size, mode, pos, buf, bufsz);
c341ddb2 1790 } else {
b03d7d0f
WYG
1791 if (next_entry < size) {
1792 pos = iwl_print_event_log(priv, 0, next_entry,
1793 mode, pos, buf, bufsz);
1794 } else {
1795 pos = iwl_print_event_log(priv, next_entry - size,
1796 size, mode, pos, buf, bufsz);
1797 }
c341ddb2 1798 }
b03d7d0f 1799 return pos;
c341ddb2
WYG
1800}
1801
c341ddb2
WYG
1802#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
1803
b03d7d0f
WYG
1804int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
1805 char **buf, bool display)
b7a79404
RC
1806{
1807 u32 base; /* SRAM byte address of event log header */
1808 u32 capacity; /* event log capacity in # entries */
1809 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1810 u32 num_wraps; /* # times uCode wrapped to top of log */
1811 u32 next_entry; /* index of next entry to be written by uCode */
1812 u32 size; /* # entries that we'll print */
b2e640d4 1813 u32 logsize;
b03d7d0f
WYG
1814 int pos = 0;
1815 size_t bufsz = 0;
b7a79404 1816
d7d5783c 1817 base = priv->device_pointers.log_event_table;
ca7966c8 1818 if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
b2e640d4
JB
1819 logsize = priv->_agn.init_evtlog_size;
1820 if (!base)
1821 base = priv->_agn.init_evtlog_ptr;
1822 } else {
b2e640d4
JB
1823 logsize = priv->_agn.inst_evtlog_size;
1824 if (!base)
1825 base = priv->_agn.inst_evtlog_ptr;
1826 }
b7a79404
RC
1827
1828 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG
1829 IWL_ERR(priv,
1830 "Invalid event log pointer 0x%08X for %s uCode\n",
ca7966c8
JB
1831 base,
1832 (priv->ucode_type == UCODE_SUBTYPE_INIT)
1833 ? "Init" : "RT");
937c397e 1834 return -EINVAL;
b7a79404
RC
1835 }
1836
1837 /* event log header */
1838 capacity = iwl_read_targ_mem(priv, base);
1839 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1840 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1841 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1842
b2e640d4 1843 if (capacity > logsize) {
84c40692 1844 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB
1845 capacity, logsize);
1846 capacity = logsize;
84c40692
BC
1847 }
1848
b2e640d4 1849 if (next_entry > logsize) {
84c40692 1850 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB
1851 next_entry, logsize);
1852 next_entry = logsize;
84c40692
BC
1853 }
1854
b7a79404
RC
1855 size = num_wraps ? capacity : next_entry;
1856
1857 /* bail out if nothing in log */
1858 if (size == 0) {
1859 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 1860 return pos;
b7a79404
RC
1861 }
1862
9f28ebc3 1863 /* enable/disable bt channel inhibition */
f37837c9
WYG
1864 priv->bt_ch_announce = iwlagn_bt_ch_announce;
1865
c341ddb2 1866#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 1867 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG
1868 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1869 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1870#else
1871 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
1872 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
1873#endif
1874 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
1875 size);
b7a79404 1876
c341ddb2 1877#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG
1878 if (display) {
1879 if (full_log)
1880 bufsz = capacity * 48;
1881 else
1882 bufsz = size * 48;
1883 *buf = kmalloc(bufsz, GFP_KERNEL);
1884 if (!*buf)
937c397e 1885 return -ENOMEM;
b03d7d0f 1886 }
c341ddb2
WYG
1887 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
1888 /*
1889 * if uCode has wrapped back to top of log,
1890 * start at the oldest entry,
1891 * i.e the next one that uCode would fill.
1892 */
1893 if (num_wraps)
b03d7d0f
WYG
1894 pos = iwl_print_event_log(priv, next_entry,
1895 capacity - next_entry, mode,
1896 pos, buf, bufsz);
c341ddb2 1897 /* (then/else) start at top of log */
b03d7d0f
WYG
1898 pos = iwl_print_event_log(priv, 0,
1899 next_entry, mode, pos, buf, bufsz);
c341ddb2 1900 } else
b03d7d0f
WYG
1901 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
1902 next_entry, size, mode,
1903 pos, buf, bufsz);
c341ddb2 1904#else
b03d7d0f
WYG
1905 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
1906 next_entry, size, mode,
1907 pos, buf, bufsz);
b7a79404 1908#endif
b03d7d0f 1909 return pos;
c341ddb2 1910}
b7a79404 1911
0975cc8f
WYG
1912static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1913{
1914 struct iwl_ct_kill_config cmd;
1915 struct iwl_ct_kill_throttling_config adv_cmd;
1916 unsigned long flags;
1917 int ret = 0;
1918
1919 spin_lock_irqsave(&priv->lock, flags);
1920 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1921 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1922 spin_unlock_irqrestore(&priv->lock, flags);
1923 priv->thermal_throttle.ct_kill_toggle = false;
1924
7cb1b088 1925 if (priv->cfg->base_params->support_ct_kill_exit) {
0975cc8f
WYG
1926 adv_cmd.critical_temperature_enter =
1927 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1928 adv_cmd.critical_temperature_exit =
1929 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
1930
1931 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1932 sizeof(adv_cmd), &adv_cmd);
1933 if (ret)
1934 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
1935 else
1936 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
1937 "succeeded, "
1938 "critical temperature enter is %d,"
1939 "exit is %d\n",
1940 priv->hw_params.ct_kill_threshold,
1941 priv->hw_params.ct_kill_exit_threshold);
1942 } else {
1943 cmd.critical_temperature_R =
1944 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1945
1946 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1947 sizeof(cmd), &cmd);
1948 if (ret)
1949 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
1950 else
1951 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
1952 "succeeded, "
1953 "critical temperature is %d\n",
1954 priv->hw_params.ct_kill_threshold);
1955 }
1956}
1957
6d6a1afd
SZ
1958static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
1959{
1960 struct iwl_calib_cfg_cmd calib_cfg_cmd;
1961 struct iwl_host_cmd cmd = {
1962 .id = CALIBRATION_CFG_CMD,
3fa50738
JB
1963 .len = { sizeof(struct iwl_calib_cfg_cmd), },
1964 .data = { &calib_cfg_cmd, },
6d6a1afd
SZ
1965 };
1966
1967 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
1968 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
7cb1b088 1969 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
6d6a1afd
SZ
1970
1971 return iwl_send_cmd(priv, &cmd);
1972}
1973
1974
b481de9c 1975/**
4a4a9e81 1976 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1977 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1978 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1979 */
4613e72d 1980int iwl_alive_start(struct iwl_priv *priv)
b481de9c 1981{
57aab75a 1982 int ret = 0;
246ed355 1983 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 1984
ca7966c8 1985 iwl_reset_ict(priv);
b481de9c 1986
ca7966c8 1987 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
6d6a1afd 1988
5b9f8cd3 1989 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1990 set_bit(STATUS_ALIVE, &priv->status);
1991
22de94de
SG
1992 /* Enable watchdog to monitor the driver tx queues */
1993 iwl_setup_watchdog(priv);
b74e31a9 1994
fee1247a 1995 if (iwl_is_rfkill(priv))
ca7966c8 1996 return -ERFKILL;
b481de9c 1997
bc795df1 1998 /* download priority table before any calibration request */
7cb1b088
WYG
1999 if (priv->cfg->bt_params &&
2000 priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f
WYG
2001 /* Configure Bluetooth device coexistence support */
2002 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2003 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2004 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2005 priv->cfg->ops->hcmd->send_bt_config(priv);
2006 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
a5901cbb 2007 iwlagn_send_prio_tbl(priv);
f7322f8f
WYG
2008
2009 /* FIXME: w/a to force change uCode BT state machine */
ca7966c8
JB
2010 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2011 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2012 if (ret)
2013 return ret;
2014 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2015 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2016 if (ret)
2017 return ret;
f7322f8f 2018 }
bc795df1
WYG
2019 if (priv->hw_params.calib_rt_cfg)
2020 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2021
36d6825b 2022 ieee80211_wake_queues(priv->hw);
b481de9c 2023
470ab2dd 2024 priv->active_rate = IWL_RATES_MASK;
b481de9c 2025
2f748dec
WYG
2026 /* Configure Tx antenna selection based on H/W config */
2027 if (priv->cfg->ops->hcmd->set_tx_ant)
2028 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2029
246ed355 2030 if (iwl_is_associated_ctx(ctx)) {
c1adf9fb 2031 struct iwl_rxon_cmd *active_rxon =
246ed355 2032 (struct iwl_rxon_cmd *)&ctx->active;
019fb97d 2033 /* apply any changes in staging */
246ed355 2034 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
2035 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2036 } else {
d0fe478c 2037 struct iwl_rxon_context *tmp;
b481de9c 2038 /* Initialize our rx_config data */
d0fe478c
JB
2039 for_each_context(priv, tmp)
2040 iwl_connection_init_rx_config(priv, tmp);
45823531
AK
2041
2042 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 2043 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c
ZY
2044 }
2045
73b78a22
WYG
2046 if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2047 !priv->cfg->bt_params->advanced_bt_coexist)) {
2048 /*
2049 * default is 2-wire BT coexexistence support
2050 */
aeb4a2ee
WYG
2051 priv->cfg->ops->hcmd->send_bt_config(priv);
2052 }
b481de9c 2053
4a4a9e81
TW
2054 iwl_reset_run_time_calib(priv);
2055
9e2e7422
WYG
2056 set_bit(STATUS_READY, &priv->status);
2057
b481de9c 2058 /* Configure the adapter for unassociated operation */
ca7966c8
JB
2059 ret = iwlcore_commit_rxon(priv, ctx);
2060 if (ret)
2061 return ret;
b481de9c
ZY
2062
2063 /* At this point, the NIC is initialized and operational */
47f4a587 2064 iwl_rf_kill_ct_config(priv);
5a66926a 2065
e1623446 2066 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
c46fbefa 2067
ca7966c8 2068 return iwl_power_update_mode(priv, true);
b481de9c
ZY
2069}
2070
4e39317d 2071static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2072
5b9f8cd3 2073static void __iwl_down(struct iwl_priv *priv)
b481de9c 2074{
22dd2fd2 2075 int exit_pending;
b481de9c 2076
e1623446 2077 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2078
d745d472
SG
2079 iwl_scan_cancel_timeout(priv, 200);
2080
2081 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2082
b62177a0
SG
2083 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2084 * to prevent rearm timer */
22de94de 2085 del_timer_sync(&priv->watchdog);
b62177a0 2086
dcef732c 2087 iwl_clear_ucode_stations(priv, NULL);
a194e324 2088 iwl_dealloc_bcast_stations(priv);
db125c78 2089 iwl_clear_driver_stations(priv);
b481de9c 2090
a1174138 2091 /* reset BT coex data */
da5dbb97 2092 priv->bt_status = 0;
7cb1b088
WYG
2093 if (priv->cfg->bt_params)
2094 priv->bt_traffic_load =
2095 priv->cfg->bt_params->bt_init_traffic_load;
2096 else
2097 priv->bt_traffic_load = 0;
bee008b7
WYG
2098 priv->bt_full_concurrent = false;
2099 priv->bt_ci_compliance = 0;
a1174138 2100
b481de9c
ZY
2101 /* Wipe out the EXIT_PENDING status bit if we are not actually
2102 * exiting the module */
2103 if (!exit_pending)
2104 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2105
b481de9c
ZY
2106 if (priv->mac80211_registered)
2107 ieee80211_stop_queues(priv->hw);
2108
1a10f433 2109 /* Clear out all status bits but a few that are stable across reset */
b481de9c
ZY
2110 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2111 STATUS_RF_KILL_HW |
9788864e
RC
2112 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2113 STATUS_GEO_CONFIGURED |
b481de9c 2114 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
2115 STATUS_FW_ERROR |
2116 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2117 STATUS_EXIT_PENDING;
b481de9c 2118
bc4f8ada 2119 iwlagn_stop_device(priv);
4d2ccdb9 2120
77834543 2121 dev_kfree_skb(priv->beacon_skb);
12e934dc 2122 priv->beacon_skb = NULL;
b481de9c
ZY
2123}
2124
5b9f8cd3 2125static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
2126{
2127 mutex_lock(&priv->mutex);
5b9f8cd3 2128 __iwl_down(priv);
b481de9c 2129 mutex_unlock(&priv->mutex);
b24d22b1 2130
4e39317d 2131 iwl_cancel_deferred_work(priv);
b481de9c
ZY
2132}
2133
086ed117
MA
2134#define HW_READY_TIMEOUT (50)
2135
4cd2bf76 2136/* Note: returns poll_bit return value, which is >= 0 if success */
086ed117
MA
2137static int iwl_set_hw_ready(struct iwl_priv *priv)
2138{
4cd2bf76 2139 int ret;
086ed117
MA
2140
2141 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2142 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2143
2144 /* See if we got it */
2145 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2146 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2147 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2148 HW_READY_TIMEOUT);
086ed117 2149
4cd2bf76 2150 IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
086ed117
MA
2151 return ret;
2152}
2153
4cd2bf76 2154/* Note: returns standard 0/-ERROR code */
3e14c1fd 2155int iwl_prepare_card_hw(struct iwl_priv *priv)
086ed117 2156{
4cd2bf76 2157 int ret;
086ed117 2158
91dd6c27 2159 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 2160
3354a0f6 2161 ret = iwl_set_hw_ready(priv);
4cd2bf76
JB
2162 if (ret >= 0)
2163 return 0;
3354a0f6
MA
2164
2165 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2166 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2167 CSR_HW_IF_CONFIG_REG_PREPARE);
2168
2169 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2170 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2171 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2172
4cd2bf76
JB
2173 if (ret < 0)
2174 return ret;
086ed117 2175
4cd2bf76
JB
2176 /* HW should be ready by now, check again. */
2177 ret = iwl_set_hw_ready(priv);
2178 if (ret >= 0)
2179 return 0;
086ed117
MA
2180 return ret;
2181}
2182
b481de9c
ZY
2183#define MAX_HW_RESTARTS 5
2184
5b9f8cd3 2185static int __iwl_up(struct iwl_priv *priv)
b481de9c 2186{
a194e324 2187 struct iwl_rxon_context *ctx;
57aab75a 2188 int ret;
b481de9c 2189
ca7966c8
JB
2190 lockdep_assert_held(&priv->mutex);
2191
b481de9c 2192 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2193 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2194 return -EIO;
2195 }
2196
a194e324 2197 for_each_context(priv, ctx) {
a30e3112 2198 ret = iwlagn_alloc_bcast_station(priv, ctx);
a194e324
JB
2199 if (ret) {
2200 iwl_dealloc_bcast_stations(priv);
2201 return ret;
2202 }
2203 }
2c810ccd 2204
ca7966c8
JB
2205 ret = iwlagn_run_init_ucode(priv);
2206 if (ret) {
2207 IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret);
2208 goto error;
2209 }
b481de9c 2210
ca7966c8 2211 ret = iwlagn_load_ucode_wait_alive(priv,
dbf28e21 2212 &priv->ucode_rt,
ca7966c8
JB
2213 UCODE_SUBTYPE_REGULAR,
2214 UCODE_SUBTYPE_REGULAR_NEW);
2215 if (ret) {
2216 IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
2217 goto error;
b481de9c
ZY
2218 }
2219
ca7966c8
JB
2220 ret = iwl_alive_start(priv);
2221 if (ret)
2222 goto error;
2223 return 0;
2224
2225 error:
b481de9c 2226 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2227 __iwl_down(priv);
64e72c3e 2228 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2229
ca7966c8
JB
2230 IWL_ERR(priv, "Unable to initialize device.\n");
2231 return ret;
b481de9c
ZY
2232}
2233
2234
2235/*****************************************************************************
2236 *
2237 * Workqueue callbacks
2238 *
2239 *****************************************************************************/
2240
16e727e8
EG
2241static void iwl_bg_run_time_calib_work(struct work_struct *work)
2242{
2243 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2244 run_time_calib_work);
2245
2246 mutex_lock(&priv->mutex);
2247
2248 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2249 test_bit(STATUS_SCANNING, &priv->status)) {
2250 mutex_unlock(&priv->mutex);
2251 return;
2252 }
2253
2254 if (priv->start_calib) {
0da0e5bf
JB
2255 iwl_chain_noise_calibration(priv);
2256 iwl_sensitivity_calibration(priv);
16e727e8
EG
2257 }
2258
2259 mutex_unlock(&priv->mutex);
16e727e8
EG
2260}
2261
e43e85c4
JB
2262static void iwlagn_prepare_restart(struct iwl_priv *priv)
2263{
2264 struct iwl_rxon_context *ctx;
2265 bool bt_full_concurrent;
2266 u8 bt_ci_compliance;
2267 u8 bt_load;
2268 u8 bt_status;
2269
2270 lockdep_assert_held(&priv->mutex);
2271
2272 for_each_context(priv, ctx)
2273 ctx->vif = NULL;
2274 priv->is_open = 0;
2275
2276 /*
2277 * __iwl_down() will clear the BT status variables,
2278 * which is correct, but when we restart we really
2279 * want to keep them so restore them afterwards.
2280 *
2281 * The restart process will later pick them up and
2282 * re-configure the hw when we reconfigure the BT
2283 * command.
2284 */
2285 bt_full_concurrent = priv->bt_full_concurrent;
2286 bt_ci_compliance = priv->bt_ci_compliance;
2287 bt_load = priv->bt_traffic_load;
2288 bt_status = priv->bt_status;
2289
2290 __iwl_down(priv);
2291
2292 priv->bt_full_concurrent = bt_full_concurrent;
2293 priv->bt_ci_compliance = bt_ci_compliance;
2294 priv->bt_traffic_load = bt_load;
2295 priv->bt_status = bt_status;
2296}
2297
5b9f8cd3 2298static void iwl_bg_restart(struct work_struct *data)
b481de9c 2299{
c79dd5b5 2300 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2301
2302 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2303 return;
2304
19cc1087
JB
2305 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2306 mutex_lock(&priv->mutex);
e43e85c4 2307 iwlagn_prepare_restart(priv);
19cc1087 2308 mutex_unlock(&priv->mutex);
a1174138 2309 iwl_cancel_deferred_work(priv);
19cc1087
JB
2310 ieee80211_restart_hw(priv->hw);
2311 } else {
ca7966c8 2312 WARN_ON(1);
19cc1087 2313 }
b481de9c
ZY
2314}
2315
5b9f8cd3 2316static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2317{
c79dd5b5
TW
2318 struct iwl_priv *priv =
2319 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2320
2321 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2322 return;
2323
2324 mutex_lock(&priv->mutex);
54b81550 2325 iwlagn_rx_replenish(priv);
b481de9c
ZY
2326 mutex_unlock(&priv->mutex);
2327}
2328
266af4c7
JB
2329static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2330 struct ieee80211_channel *chan,
2331 enum nl80211_channel_type channel_type,
2332 unsigned int wait)
2333{
2334 struct iwl_priv *priv = hw->priv;
2335 int ret;
2336
2337 /* Not supported if we don't have PAN */
2338 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2339 ret = -EOPNOTSUPP;
2340 goto free;
2341 }
2342
2343 /* Not supported on pre-P2P firmware */
2344 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2345 BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2346 ret = -EOPNOTSUPP;
2347 goto free;
2348 }
2349
2350 mutex_lock(&priv->mutex);
2351
2352 if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2353 /*
2354 * If the PAN context is free, use the normal
2355 * way of doing remain-on-channel offload + TX.
2356 */
2357 ret = 1;
2358 goto out;
2359 }
2360
2361 /* TODO: queue up if scanning? */
2362 if (test_bit(STATUS_SCANNING, &priv->status) ||
2363 priv->_agn.offchan_tx_skb) {
2364 ret = -EBUSY;
2365 goto out;
2366 }
2367
2368 /*
2369 * max_scan_ie_len doesn't include the blank SSID or the header,
2370 * so need to add that again here.
2371 */
2372 if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2373 ret = -ENOBUFS;
2374 goto out;
2375 }
2376
2377 priv->_agn.offchan_tx_skb = skb;
2378 priv->_agn.offchan_tx_timeout = wait;
2379 priv->_agn.offchan_tx_chan = chan;
2380
2381 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2382 IWL_SCAN_OFFCH_TX, chan->band);
2383 if (ret)
2384 priv->_agn.offchan_tx_skb = NULL;
2385 out:
2386 mutex_unlock(&priv->mutex);
2387 free:
2388 if (ret < 0)
2389 kfree_skb(skb);
2390
2391 return ret;
2392}
2393
2394static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2395{
2396 struct iwl_priv *priv = hw->priv;
2397 int ret;
2398
2399 mutex_lock(&priv->mutex);
2400
f8a22a2b
DC
2401 if (!priv->_agn.offchan_tx_skb) {
2402 ret = -EINVAL;
2403 goto unlock;
2404 }
266af4c7
JB
2405
2406 priv->_agn.offchan_tx_skb = NULL;
2407
2408 ret = iwl_scan_cancel_timeout(priv, 200);
2409 if (ret)
2410 ret = -EIO;
f8a22a2b 2411unlock:
266af4c7
JB
2412 mutex_unlock(&priv->mutex);
2413
2414 return ret;
2415}
2416
b481de9c
ZY
2417/*****************************************************************************
2418 *
2419 * mac80211 entry point functions
2420 *
2421 *****************************************************************************/
2422
0fd09502
JB
2423static const struct ieee80211_iface_limit iwlagn_sta_ap_limits[] = {
2424 {
2425 .max = 1,
2426 .types = BIT(NL80211_IFTYPE_STATION),
2427 },
2428 {
2429 .max = 1,
2430 .types = BIT(NL80211_IFTYPE_AP),
2431 },
2432};
2433
2434static const struct ieee80211_iface_limit iwlagn_2sta_limits[] = {
2435 {
2436 .max = 2,
2437 .types = BIT(NL80211_IFTYPE_STATION),
2438 },
2439};
2440
2441static const struct ieee80211_iface_limit iwlagn_p2p_sta_go_limits[] = {
2442 {
2443 .max = 1,
2444 .types = BIT(NL80211_IFTYPE_STATION),
2445 },
2446 {
2447 .max = 1,
2448 .types = BIT(NL80211_IFTYPE_P2P_GO) |
2449 BIT(NL80211_IFTYPE_AP),
2450 },
2451};
2452
2453static const struct ieee80211_iface_limit iwlagn_p2p_2sta_limits[] = {
2454 {
2455 .max = 2,
2456 .types = BIT(NL80211_IFTYPE_STATION),
2457 },
2458 {
2459 .max = 1,
2460 .types = BIT(NL80211_IFTYPE_P2P_CLIENT),
2461 },
2462};
2463
2464static const struct ieee80211_iface_combination
2465iwlagn_iface_combinations_dualmode[] = {
2466 { .num_different_channels = 1,
2467 .max_interfaces = 2,
2468 .beacon_int_infra_match = true,
2469 .limits = iwlagn_sta_ap_limits,
2470 .n_limits = ARRAY_SIZE(iwlagn_sta_ap_limits),
2471 },
2472 { .num_different_channels = 1,
2473 .max_interfaces = 2,
2474 .limits = iwlagn_2sta_limits,
2475 .n_limits = ARRAY_SIZE(iwlagn_2sta_limits),
2476 },
2477};
2478
2479static const struct ieee80211_iface_combination
2480iwlagn_iface_combinations_p2p[] = {
2481 { .num_different_channels = 1,
2482 .max_interfaces = 2,
2483 .beacon_int_infra_match = true,
2484 .limits = iwlagn_p2p_sta_go_limits,
2485 .n_limits = ARRAY_SIZE(iwlagn_p2p_sta_go_limits),
2486 },
2487 { .num_different_channels = 1,
2488 .max_interfaces = 2,
2489 .limits = iwlagn_p2p_2sta_limits,
2490 .n_limits = ARRAY_SIZE(iwlagn_p2p_2sta_limits),
2491 },
2492};
2493
f0b6e2e8
RC
2494/*
2495 * Not a mac80211 entry point function, but it fits in with all the
2496 * other mac80211 functions grouped here.
2497 */
dd7a2509
JB
2498static int iwl_mac_setup_register(struct iwl_priv *priv,
2499 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC
2500{
2501 int ret;
2502 struct ieee80211_hw *hw = priv->hw;
d0fe478c
JB
2503 struct iwl_rxon_context *ctx;
2504
f0b6e2e8
RC
2505 hw->rate_control_algorithm = "iwl-agn-rs";
2506
2507 /* Tell mac80211 our characteristics */
2508 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8 2509 IEEE80211_HW_AMPDU_AGGREGATION |
2491fa42 2510 IEEE80211_HW_NEED_DTIM_PERIOD |
6fb5511a
JB
2511 IEEE80211_HW_SPECTRUM_MGMT |
2512 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
f0b6e2e8 2513
9b768832
JB
2514 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2515
23c0fcc6
WYG
2516 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2517 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
f0b6e2e8 2518
ba37a3d0
JB
2519 if (priv->cfg->sku & IWL_SKU_N)
2520 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2521 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2522
3997ff39
JB
2523 if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2524 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2525
8d9698b3 2526 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB
2527 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2528
d0fe478c
JB
2529 for_each_context(priv, ctx) {
2530 hw->wiphy->interface_modes |= ctx->interface_modes;
2531 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2532 }
f0b6e2e8 2533
0fd09502
JB
2534 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
2535
2536 if (hw->wiphy->interface_modes & NL80211_IFTYPE_P2P_CLIENT) {
2537 hw->wiphy->iface_combinations = iwlagn_iface_combinations_p2p;
2538 hw->wiphy->n_iface_combinations =
2539 ARRAY_SIZE(iwlagn_iface_combinations_p2p);
2540 } else if (hw->wiphy->interface_modes & NL80211_IFTYPE_AP) {
2541 hw->wiphy->iface_combinations = iwlagn_iface_combinations_dualmode;
2542 hw->wiphy->n_iface_combinations =
2543 ARRAY_SIZE(iwlagn_iface_combinations_dualmode);
2544 }
2545
9b9190d9
JB
2546 hw->wiphy->max_remain_on_channel_duration = 1000;
2547
f6c8f152 2548 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
274102a8
JB
2549 WIPHY_FLAG_DISABLE_BEACON_HINTS |
2550 WIPHY_FLAG_IBSS_RSN;
f0b6e2e8
RC
2551
2552 /*
2553 * For now, disable PS by default because it affects
2554 * RX performance significantly.
2555 */
5be83de5 2556 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 2557
1382c71c 2558 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 2559 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 2560 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC
2561
2562 /* Default value; 4 EDCA QOS priorities */
2563 hw->queues = 4;
2564
2565 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2566
2567 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2568 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2569 &priv->bands[IEEE80211_BAND_2GHZ];
2570 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2571 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2572 &priv->bands[IEEE80211_BAND_5GHZ];
2573
5ed540ae
WYG
2574 iwl_leds_init(priv);
2575
f0b6e2e8
RC
2576 ret = ieee80211_register_hw(priv->hw);
2577 if (ret) {
2578 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2579 return ret;
2580 }
2581 priv->mac80211_registered = 1;
2582
2583 return 0;
2584}
2585
2586
2dedbf58 2587static int iwlagn_mac_start(struct ieee80211_hw *hw)
b481de9c 2588{
c79dd5b5 2589 struct iwl_priv *priv = hw->priv;
5a66926a 2590 int ret;
b481de9c 2591
e1623446 2592 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2593
2594 /* we should be verifying the device is ready to be opened */
2595 mutex_lock(&priv->mutex);
5b9f8cd3 2596 ret = __iwl_up(priv);
b481de9c 2597 mutex_unlock(&priv->mutex);
e655b9f0 2598 if (ret)
6cd0b1cb 2599 return ret;
e655b9f0 2600
e1623446 2601 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2602
ca7966c8
JB
2603 /* Now we should be done, and the READY bit should be set. */
2604 if (WARN_ON(!test_bit(STATUS_READY, &priv->status)))
2605 ret = -EIO;
0a078ffa 2606
5ed540ae 2607 iwlagn_led_enable(priv);
e932a609 2608
0a078ffa 2609 priv->is_open = 1;
e1623446 2610 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2611 return 0;
2612}
2613
2dedbf58 2614static void iwlagn_mac_stop(struct ieee80211_hw *hw)
b481de9c 2615{
c79dd5b5 2616 struct iwl_priv *priv = hw->priv;
b481de9c 2617
e1623446 2618 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2619
19cc1087 2620 if (!priv->is_open)
e655b9f0 2621 return;
e655b9f0 2622
b481de9c 2623 priv->is_open = 0;
5a66926a 2624
5b9f8cd3 2625 iwl_down(priv);
5a66926a
ZY
2626
2627 flush_workqueue(priv->workqueue);
6cd0b1cb 2628
554d1d02
SG
2629 /* User space software may expect getting rfkill changes
2630 * even if interface is down */
6cd0b1cb 2631 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
554d1d02 2632 iwl_enable_rfkill_int(priv);
948c171c 2633
e1623446 2634 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2635}
2636
2dedbf58 2637static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2638{
c79dd5b5 2639 struct iwl_priv *priv = hw->priv;
b481de9c 2640
e1623446 2641 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2642
e1623446 2643 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2644 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2645
74bcdb33 2646 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY
2647 dev_kfree_skb_any(skb);
2648
e1623446 2649 IWL_DEBUG_MACDUMP(priv, "leave\n");
b481de9c
ZY
2650}
2651
2dedbf58
JB
2652static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2653 struct ieee80211_vif *vif,
2654 struct ieee80211_key_conf *keyconf,
2655 struct ieee80211_sta *sta,
2656 u32 iv32, u16 *phase1key)
ab885f8c 2657{
9f58671e 2658 struct iwl_priv *priv = hw->priv;
a194e324
JB
2659 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2660
e1623446 2661 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2662
a194e324 2663 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
b3fbdcf4 2664 iv32, phase1key);
ab885f8c 2665
e1623446 2666 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2667}
2668
2dedbf58
JB
2669static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2670 struct ieee80211_vif *vif,
2671 struct ieee80211_sta *sta,
2672 struct ieee80211_key_conf *key)
b481de9c 2673{
c79dd5b5 2674 struct iwl_priv *priv = hw->priv;
a194e324 2675 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
c10afb6e 2676 struct iwl_rxon_context *ctx = vif_priv->ctx;
42986796
WT
2677 int ret;
2678 u8 sta_id;
2679 bool is_default_wep_key = false;
b481de9c 2680
e1623446 2681 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2682
9d143e9a 2683 if (iwlagn_mod_params.sw_crypto) {
e1623446 2684 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2685 return -EOPNOTSUPP;
2686 }
b481de9c 2687
274102a8
JB
2688 /*
2689 * To support IBSS RSN, don't program group keys in IBSS, the
2690 * hardware will then not attempt to decrypt the frames.
2691 */
2692 if (vif->type == NL80211_IFTYPE_ADHOC &&
2693 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
2694 return -EOPNOTSUPP;
2695
a194e324 2696 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
0af8bcae
JB
2697 if (sta_id == IWL_INVALID_STATION)
2698 return -EINVAL;
b481de9c 2699
6974e363 2700 mutex_lock(&priv->mutex);
2a421b91 2701 iwl_scan_cancel_timeout(priv, 100);
6974e363 2702
a90178fa
JB
2703 /*
2704 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG
2705 * so far, we are in legacy wep mode (group key only), otherwise we are
2706 * in 1X mode.
a90178fa
JB
2707 * In legacy wep mode, we use another host command to the uCode.
2708 */
97359d12
JB
2709 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2710 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 2711 !sta) {
6974e363 2712 if (cmd == SET_KEY)
c10afb6e 2713 is_default_wep_key = !ctx->key_mapping_keys;
6974e363 2714 else
ccc038ab
EG
2715 is_default_wep_key =
2716 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2717 }
052c4b9f 2718
b481de9c 2719 switch (cmd) {
deb09c43 2720 case SET_KEY:
6974e363 2721 if (is_default_wep_key)
2995bafa 2722 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
deb09c43 2723 else
a194e324
JB
2724 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
2725 key, sta_id);
deb09c43 2726
e1623446 2727 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2728 break;
2729 case DISABLE_KEY:
6974e363 2730 if (is_default_wep_key)
c10afb6e 2731 ret = iwl_remove_default_wep_key(priv, ctx, key);
deb09c43 2732 else
c10afb6e 2733 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
deb09c43 2734
e1623446 2735 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2736 break;
2737 default:
deb09c43 2738 ret = -EINVAL;
b481de9c
ZY
2739 }
2740
72e15d71 2741 mutex_unlock(&priv->mutex);
e1623446 2742 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2743
deb09c43 2744 return ret;
b481de9c
ZY
2745}
2746
2dedbf58
JB
2747static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2748 struct ieee80211_vif *vif,
2749 enum ieee80211_ampdu_mlme_action action,
2750 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
2751 u8 buf_size)
d783b061
TW
2752{
2753 struct iwl_priv *priv = hw->priv;
4620fefa 2754 int ret = -EINVAL;
7b090687 2755 struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
d783b061 2756
e1623446 2757 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2758 sta->addr, tid);
d783b061
TW
2759
2760 if (!(priv->cfg->sku & IWL_SKU_N))
2761 return -EACCES;
2762
4620fefa
JB
2763 mutex_lock(&priv->mutex);
2764
d783b061
TW
2765 switch (action) {
2766 case IEEE80211_AMPDU_RX_START:
e1623446 2767 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB
2768 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
2769 break;
d783b061 2770 case IEEE80211_AMPDU_RX_STOP:
e1623446 2771 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 2772 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 2773 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB
2774 ret = 0;
2775 break;
d783b061 2776 case IEEE80211_AMPDU_TX_START:
e1623446 2777 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 2778 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG
2779 if (ret == 0) {
2780 priv->_agn.agg_tids_count++;
2781 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2782 priv->_agn.agg_tids_count);
2783 }
4620fefa 2784 break;
d783b061 2785 case IEEE80211_AMPDU_TX_STOP:
e1623446 2786 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 2787 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG
2788 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
2789 priv->_agn.agg_tids_count--;
2790 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2791 priv->_agn.agg_tids_count);
2792 }
5c2207c6 2793 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 2794 ret = 0;
7cb1b088
WYG
2795 if (priv->cfg->ht_params &&
2796 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB
2797 /*
2798 * switch off RTS/CTS if it was previously enabled
2799 */
94597ab2
JB
2800 sta_priv->lq_sta.lq.general_params.flags &=
2801 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB
2802 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2803 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
94597ab2 2804 }
4620fefa 2805 break;
f0527971 2806 case IEEE80211_AMPDU_TX_OPERATIONAL:
c8823ec1
JB
2807 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
2808
2809 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
2810
7b090687
JB
2811 /*
2812 * If the limit is 0, then it wasn't initialised yet,
2813 * use the default. We can do that since we take the
2814 * minimum below, and we don't want to go above our
2815 * default due to hardware restrictions.
2816 */
2817 if (sta_priv->max_agg_bufsize == 0)
2818 sta_priv->max_agg_bufsize =
2819 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2820
2821 /*
2822 * Even though in theory the peer could have different
2823 * aggregation reorder buffer sizes for different sessions,
2824 * our ucode doesn't allow for that and has a global limit
2825 * for each station. Therefore, use the minimum of all the
2826 * aggregation sessions and our default value.
2827 */
2828 sta_priv->max_agg_bufsize =
2829 min(sta_priv->max_agg_bufsize, buf_size);
2830
7cb1b088
WYG
2831 if (priv->cfg->ht_params &&
2832 priv->cfg->ht_params->use_rts_for_aggregation) {
cfecc6b4
WYG
2833 /*
2834 * switch to RTS/CTS if it is the prefer protection
2835 * method for HT traffic
2836 */
94597ab2
JB
2837
2838 sta_priv->lq_sta.lq.general_params.flags |=
2839 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
cfecc6b4 2840 }
7b090687
JB
2841
2842 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
2843 sta_priv->max_agg_bufsize;
2844
2845 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2846 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
5bc9890f
WYG
2847
2848 IWL_INFO(priv, "Tx aggregation enabled on ra = %pM tid = %d\n",
2849 sta->addr, tid);
cfecc6b4 2850 ret = 0;
d783b061
TW
2851 break;
2852 }
4620fefa
JB
2853 mutex_unlock(&priv->mutex);
2854
2855 return ret;
d783b061 2856}
9f58671e 2857
2dedbf58
JB
2858static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
2859 struct ieee80211_vif *vif,
2860 struct ieee80211_sta *sta)
fe6b23dd
RC
2861{
2862 struct iwl_priv *priv = hw->priv;
2863 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
a194e324 2864 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
eafdfbd3 2865 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC
2866 int ret;
2867 u8 sta_id;
2868
2869 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
2870 sta->addr);
da5ae1cf
RC
2871 mutex_lock(&priv->mutex);
2872 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
2873 sta->addr);
2874 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC
2875
2876 atomic_set(&sta_priv->pending_frames, 0);
2877 if (vif->type == NL80211_IFTYPE_AP)
2878 sta_priv->client = true;
2879
a194e324 2880 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
238d781d 2881 is_ap, sta, &sta_id);
fe6b23dd
RC
2882 if (ret) {
2883 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
2884 sta->addr, ret);
2885 /* Should we return success if return code is EEXIST ? */
da5ae1cf 2886 mutex_unlock(&priv->mutex);
fe6b23dd
RC
2887 return ret;
2888 }
2889
fd1af15d
JB
2890 sta_priv->common.sta_id = sta_id;
2891
fe6b23dd 2892 /* Initialize rate scaling */
91dd6c27 2893 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC
2894 sta->addr);
2895 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 2896 mutex_unlock(&priv->mutex);
fe6b23dd 2897
fd1af15d 2898 return 0;
fe6b23dd
RC
2899}
2900
2dedbf58
JB
2901static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
2902 struct ieee80211_channel_switch *ch_switch)
79d07325
WYG
2903{
2904 struct iwl_priv *priv = hw->priv;
2905 const struct iwl_channel_info *ch_info;
2906 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 2907 struct ieee80211_channel *channel = ch_switch->channel;
79d07325 2908 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
246ed355
JB
2909 /*
2910 * MULTI-FIXME
2911 * When we add support for multiple interfaces, we need to
2912 * revisit this. The channel switch command in the device
2913 * only affects the BSS context, but what does that really
2914 * mean? And what if we get a CSA on the second interface?
2915 * This needs a lot of work.
2916 */
2917 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
79d07325
WYG
2918 u16 ch;
2919 unsigned long flags = 0;
2920
2921 IWL_DEBUG_MAC80211(priv, "enter\n");
2922
dc1a4068
SG
2923 mutex_lock(&priv->mutex);
2924
79d07325 2925 if (iwl_is_rfkill(priv))
dc1a4068 2926 goto out;
79d07325
WYG
2927
2928 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2929 test_bit(STATUS_SCANNING, &priv->status))
dc1a4068 2930 goto out;
79d07325 2931
246ed355 2932 if (!iwl_is_associated_ctx(ctx))
dc1a4068 2933 goto out;
79d07325
WYG
2934
2935 /* channel switch in progress */
2936 if (priv->switch_rxon.switch_in_progress == true)
dc1a4068 2937 goto out;
79d07325 2938
79d07325
WYG
2939 if (priv->cfg->ops->lib->set_channel_switch) {
2940
aa2dc6b5 2941 ch = channel->hw_value;
246ed355 2942 if (le16_to_cpu(ctx->active.channel) != ch) {
79d07325 2943 ch_info = iwl_get_channel_info(priv,
aa2dc6b5 2944 channel->band,
79d07325
WYG
2945 ch);
2946 if (!is_channel_valid(ch_info)) {
2947 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
2948 goto out;
2949 }
2950 spin_lock_irqsave(&priv->lock, flags);
2951
2952 priv->current_ht_config.smps = conf->smps_mode;
2953
2954 /* Configure HT40 channels */
7e6a5886
JB
2955 ctx->ht.enabled = conf_is_ht(conf);
2956 if (ctx->ht.enabled) {
79d07325 2957 if (conf_is_ht40_minus(conf)) {
7e6a5886 2958 ctx->ht.extension_chan_offset =
79d07325 2959 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
7e6a5886 2960 ctx->ht.is_40mhz = true;
79d07325 2961 } else if (conf_is_ht40_plus(conf)) {
7e6a5886 2962 ctx->ht.extension_chan_offset =
79d07325 2963 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
7e6a5886 2964 ctx->ht.is_40mhz = true;
79d07325 2965 } else {
7e6a5886 2966 ctx->ht.extension_chan_offset =
79d07325 2967 IEEE80211_HT_PARAM_CHA_SEC_NONE;
7e6a5886 2968 ctx->ht.is_40mhz = false;
79d07325
WYG
2969 }
2970 } else
7e6a5886 2971 ctx->ht.is_40mhz = false;
79d07325 2972
246ed355
JB
2973 if ((le16_to_cpu(ctx->staging.channel) != ch))
2974 ctx->staging.flags = 0;
79d07325 2975
246ed355 2976 iwl_set_rxon_channel(priv, channel, ctx);
79d07325 2977 iwl_set_rxon_ht(priv, ht_conf);
246ed355 2978 iwl_set_flags_for_band(priv, ctx, channel->band,
8bd413e6 2979 ctx->vif);
79d07325
WYG
2980 spin_unlock_irqrestore(&priv->lock, flags);
2981
2982 iwl_set_rate(priv);
2983 /*
2984 * at this point, staging_rxon has the
2985 * configuration for channel switch
2986 */
2987 if (priv->cfg->ops->lib->set_channel_switch(priv,
2988 ch_switch))
2989 priv->switch_rxon.switch_in_progress = false;
2990 }
2991 }
2992out:
2993 mutex_unlock(&priv->mutex);
79d07325 2994 if (!priv->switch_rxon.switch_in_progress)
8bd413e6 2995 ieee80211_chswitch_done(ctx->vif, false);
79d07325
WYG
2996 IWL_DEBUG_MAC80211(priv, "leave\n");
2997}
2998
2dedbf58
JB
2999static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3000 unsigned int changed_flags,
3001 unsigned int *total_flags,
3002 u64 multicast)
8b8ab9d5
JB
3003{
3004 struct iwl_priv *priv = hw->priv;
3005 __le32 filter_or = 0, filter_nand = 0;
246ed355 3006 struct iwl_rxon_context *ctx;
8b8ab9d5
JB
3007
3008#define CHK(test, flag) do { \
3009 if (*total_flags & (test)) \
3010 filter_or |= (flag); \
3011 else \
3012 filter_nand |= (flag); \
3013 } while (0)
3014
3015 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3016 changed_flags, *total_flags);
3017
3018 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
bdb84fec
JB
3019 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3020 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
8b8ab9d5
JB
3021 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3022
3023#undef CHK
3024
3025 mutex_lock(&priv->mutex);
3026
246ed355
JB
3027 for_each_context(priv, ctx) {
3028 ctx->staging.filter_flags &= ~filter_nand;
3029 ctx->staging.filter_flags |= filter_or;
749ff4ef
SG
3030
3031 /*
3032 * Not committing directly because hardware can perform a scan,
3033 * but we'll eventually commit the filter flags change anyway.
3034 */
246ed355 3035 }
8b8ab9d5
JB
3036
3037 mutex_unlock(&priv->mutex);
3038
3039 /*
3040 * Receiving all multicast frames is always enabled by the
3041 * default flags setup in iwl_connection_init_rx_config()
3042 * since we currently do not support programming multicast
3043 * filters into the device.
3044 */
3045 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3046 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3047}
3048
2dedbf58 3049static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
716c74b0
WYG
3050{
3051 struct iwl_priv *priv = hw->priv;
3052
3053 mutex_lock(&priv->mutex);
3054 IWL_DEBUG_MAC80211(priv, "enter\n");
3055
3056 /* do not support "flush" */
3057 if (!priv->cfg->ops->lib->txfifo_flush)
3058 goto done;
3059
3060 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3061 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3062 goto done;
3063 }
3064 if (iwl_is_rfkill(priv)) {
3065 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3066 goto done;
3067 }
3068
3069 /*
3070 * mac80211 will not push any more frames for transmit
3071 * until the flush is completed
3072 */
3073 if (drop) {
3074 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3075 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3076 IWL_ERR(priv, "flush request fail\n");
3077 goto done;
3078 }
3079 }
3080 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3081 iwlagn_wait_tx_queue_empty(priv);
3082done:
3083 mutex_unlock(&priv->mutex);
3084 IWL_DEBUG_MAC80211(priv, "leave\n");
3085}
3086
9b9190d9
JB
3087static void iwlagn_disable_roc(struct iwl_priv *priv)
3088{
3089 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3090 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3091
3092 lockdep_assert_held(&priv->mutex);
3093
3094 if (!ctx->is_active)
3095 return;
3096
3097 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3098 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3099 iwl_set_rxon_channel(priv, chan, ctx);
3100 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3101
3102 priv->_agn.hw_roc_channel = NULL;
3103
80b38fff 3104 iwlcore_commit_rxon(priv, ctx);
9b9190d9
JB
3105
3106 ctx->is_active = false;
3107}
3108
3109static void iwlagn_bg_roc_done(struct work_struct *work)
3110{
3111 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3112 _agn.hw_roc_work.work);
3113
3114 mutex_lock(&priv->mutex);
3115 ieee80211_remain_on_channel_expired(priv->hw);
3116 iwlagn_disable_roc(priv);
3117 mutex_unlock(&priv->mutex);
3118}
3119
3120static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3121 struct ieee80211_channel *channel,
3122 enum nl80211_channel_type channel_type,
3123 int duration)
3124{
3125 struct iwl_priv *priv = hw->priv;
3126 int err = 0;
3127
3128 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3129 return -EOPNOTSUPP;
3130
3131 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3132 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3133 return -EOPNOTSUPP;
3134
3135 mutex_lock(&priv->mutex);
3136
3137 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3138 test_bit(STATUS_SCAN_HW, &priv->status)) {
3139 err = -EBUSY;
3140 goto out;
3141 }
3142
3143 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3144 priv->_agn.hw_roc_channel = channel;
3145 priv->_agn.hw_roc_chantype = channel_type;
3146 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
80b38fff 3147 iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
9b9190d9
JB
3148 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3149 msecs_to_jiffies(duration + 20));
3150
94073919 3151 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
9b9190d9
JB
3152 ieee80211_ready_on_channel(priv->hw);
3153
3154 out:
3155 mutex_unlock(&priv->mutex);
3156
3157 return err;
3158}
3159
3160static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3161{
3162 struct iwl_priv *priv = hw->priv;
3163
3164 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3165 return -EOPNOTSUPP;
3166
3167 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3168
3169 mutex_lock(&priv->mutex);
3170 iwlagn_disable_roc(priv);
3171 mutex_unlock(&priv->mutex);
3172
3173 return 0;
3174}
3175
b481de9c
ZY
3176/*****************************************************************************
3177 *
3178 * driver setup and teardown
3179 *
3180 *****************************************************************************/
3181
4e39317d 3182static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 3183{
d21050c7 3184 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
3185
3186 init_waitqueue_head(&priv->wait_command_queue);
3187
5b9f8cd3
EG
3188 INIT_WORK(&priv->restart, iwl_bg_restart);
3189 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 3190 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 3191 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 3192 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 3193 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 3194 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
9b9190d9 3195 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
2a421b91 3196
2a421b91 3197 iwl_setup_scan_deferred_work(priv);
bb8c093b 3198
4e39317d
EG
3199 if (priv->cfg->ops->lib->setup_deferred_work)
3200 priv->cfg->ops->lib->setup_deferred_work(priv);
3201
3202 init_timer(&priv->statistics_periodic);
3203 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 3204 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 3205
a9e1cb6a
WYG
3206 init_timer(&priv->ucode_trace);
3207 priv->ucode_trace.data = (unsigned long)priv;
3208 priv->ucode_trace.function = iwl_bg_ucode_trace;
3209
22de94de
SG
3210 init_timer(&priv->watchdog);
3211 priv->watchdog.data = (unsigned long)priv;
3212 priv->watchdog.function = iwl_bg_watchdog;
b74e31a9 3213
d6b80618
WYG
3214 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3215 iwl_irq_tasklet, (unsigned long)priv);
b481de9c
ZY
3216}
3217
4e39317d 3218static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 3219{
4e39317d
EG
3220 if (priv->cfg->ops->lib->cancel_deferred_work)
3221 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3222
815e629b 3223 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 3224 cancel_work_sync(&priv->beacon_update);
e7e16b90
SG
3225
3226 iwl_cancel_scan_deferred_work(priv);
3227
bee008b7 3228 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 3229 cancel_work_sync(&priv->bt_runtime_config);
e7e16b90 3230
4e39317d 3231 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 3232 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY
3233}
3234
89f186a8
RC
3235static void iwl_init_hw_rates(struct iwl_priv *priv,
3236 struct ieee80211_rate *rates)
3237{
3238 int i;
3239
3240 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3241 rates[i].bitrate = iwl_rates[i].ieee * 5;
3242 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3243 rates[i].hw_value_short = i;
3244 rates[i].flags = 0;
3245 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3246 /*
3247 * If CCK != 1M then set short preamble rate flag.
3248 */
3249 rates[i].flags |=
3250 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3251 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3252 }
3253 }
3254}
3255
3256static int iwl_init_drv(struct iwl_priv *priv)
3257{
3258 int ret;
3259
89f186a8
RC
3260 spin_lock_init(&priv->sta_lock);
3261 spin_lock_init(&priv->hcmd_lock);
3262
89f186a8
RC
3263 mutex_init(&priv->mutex);
3264
89f186a8
RC
3265 priv->ieee_channels = NULL;
3266 priv->ieee_rates = NULL;
3267 priv->band = IEEE80211_BAND_2GHZ;
3268
3269 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 3270 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 3271 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 3272 priv->_agn.agg_tids_count = 0;
89f186a8 3273
8a472da4
WYG
3274 /* initialize force reset */
3275 priv->force_reset[IWL_RF_RESET].reset_duration =
3276 IWL_DELAY_NEXT_FORCE_RF_RESET;
3277 priv->force_reset[IWL_FW_RESET].reset_duration =
3278 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8 3279
410f2bb3
SG
3280 priv->rx_statistics_jiffies = jiffies;
3281
89f186a8
RC
3282 /* Choose which receivers/antennas to use */
3283 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355
JB
3284 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3285 &priv->contexts[IWL_RXON_CTX_BSS]);
89f186a8
RC
3286
3287 iwl_init_scan_params(priv);
3288
22bf59a0 3289 /* init bt coex */
7cb1b088
WYG
3290 if (priv->cfg->bt_params &&
3291 priv->cfg->bt_params->advanced_bt_coexist) {
b6e116e8
WYG
3292 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3293 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3294 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG
3295 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3296 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3297 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
22bf59a0
WYG
3298 }
3299
89f186a8
RC
3300 ret = iwl_init_channel_map(priv);
3301 if (ret) {
3302 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3303 goto err;
3304 }
3305
3306 ret = iwlcore_init_geos(priv);
3307 if (ret) {
3308 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3309 goto err_free_channel_map;
3310 }
3311 iwl_init_hw_rates(priv, priv->ieee_rates);
3312
3313 return 0;
3314
3315err_free_channel_map:
3316 iwl_free_channel_map(priv);
3317err:
3318 return ret;
3319}
3320
3321static void iwl_uninit_drv(struct iwl_priv *priv)
3322{
3323 iwl_calib_free_results(priv);
3324 iwlcore_free_geos(priv);
3325 iwl_free_channel_map(priv);
811ecc99 3326 kfree(priv->scan_cmd);
4ce7cc2b 3327 kfree(priv->beacon_cmd);
89f186a8
RC
3328}
3329
dc21b545 3330struct ieee80211_ops iwlagn_hw_ops = {
2295c66b
JB
3331 .tx = iwlagn_mac_tx,
3332 .start = iwlagn_mac_start,
3333 .stop = iwlagn_mac_stop,
5b9f8cd3
EG
3334 .add_interface = iwl_mac_add_interface,
3335 .remove_interface = iwl_mac_remove_interface,
d4daaea6 3336 .change_interface = iwl_mac_change_interface,
2295c66b 3337 .config = iwlagn_mac_config,
8b8ab9d5 3338 .configure_filter = iwlagn_configure_filter,
2295c66b
JB
3339 .set_key = iwlagn_mac_set_key,
3340 .update_tkip_key = iwlagn_mac_update_tkip_key,
5b9f8cd3 3341 .conf_tx = iwl_mac_conf_tx,
2295c66b
JB
3342 .bss_info_changed = iwlagn_bss_info_changed,
3343 .ampdu_action = iwlagn_mac_ampdu_action,
6ab10ff8 3344 .hw_scan = iwl_mac_hw_scan,
2295c66b 3345 .sta_notify = iwlagn_mac_sta_notify,
fe6b23dd
RC
3346 .sta_add = iwlagn_mac_sta_add,
3347 .sta_remove = iwl_mac_sta_remove,
2295c66b
JB
3348 .channel_switch = iwlagn_mac_channel_switch,
3349 .flush = iwlagn_mac_flush,
a85d7cca 3350 .tx_last_beacon = iwl_mac_tx_last_beacon,
9b9190d9
JB
3351 .remain_on_channel = iwl_mac_remain_on_channel,
3352 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
266af4c7
JB
3353 .offchannel_tx = iwl_mac_offchannel_tx,
3354 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
4613e72d 3355 CFG80211_TESTMODE_CMD(iwl_testmode_cmd)
b481de9c
ZY
3356};
3357
e98a1302 3358static u32 iwl_hw_detect(struct iwl_priv *priv)
3867fe04 3359{
c2974a1d
JB
3360 u8 rev_id;
3361
3362 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3363 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
02a7fa00 3364 return iwl_read32(priv, CSR_HW_REV);
3867fe04
WYG
3365}
3366
07d4f1ad
WYG
3367static int iwl_set_hw_params(struct iwl_priv *priv)
3368{
3369 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3370 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
9d143e9a 3371 if (iwlagn_mod_params.amsdu_size_8K)
07d4f1ad
WYG
3372 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3373 else
3374 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3375
3376 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3377
9d143e9a 3378 if (iwlagn_mod_params.disable_11n)
07d4f1ad
WYG
3379 priv->cfg->sku &= ~IWL_SKU_N;
3380
3381 /* Device-specific setup */
3382 return priv->cfg->ops->lib->set_hw_params(priv);
3383}
3384
e72f368b
JB
3385static const u8 iwlagn_bss_ac_to_fifo[] = {
3386 IWL_TX_FIFO_VO,
3387 IWL_TX_FIFO_VI,
3388 IWL_TX_FIFO_BE,
3389 IWL_TX_FIFO_BK,
3390};
3391
3392static const u8 iwlagn_bss_ac_to_queue[] = {
3393 0, 1, 2, 3,
3394};
3395
3396static const u8 iwlagn_pan_ac_to_fifo[] = {
3397 IWL_TX_FIFO_VO_IPAN,
3398 IWL_TX_FIFO_VI_IPAN,
3399 IWL_TX_FIFO_BE_IPAN,
3400 IWL_TX_FIFO_BK_IPAN,
3401};
3402
3403static const u8 iwlagn_pan_ac_to_queue[] = {
3404 7, 6, 5, 4,
3405};
3406
119ea186
WYG
3407/* This function both allocates and initializes hw and priv. */
3408static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
3409{
3410 struct iwl_priv *priv;
3411 /* mac80211 allocates memory for this device instance, including
3412 * space for this driver's private structure */
3413 struct ieee80211_hw *hw;
3414
3415 hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops);
3416 if (hw == NULL) {
3417 pr_err("%s: Can not allocate network device\n",
3418 cfg->name);
3419 goto out;
3420 }
3421
3422 priv = hw->priv;
3423 priv->hw = hw;
3424
3425out:
3426 return hw;
3427}
3428
5b9f8cd3 3429static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c 3430{
246ed355 3431 int err = 0, i;
c79dd5b5 3432 struct iwl_priv *priv;
b481de9c 3433 struct ieee80211_hw *hw;
82b9a121 3434 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3435 unsigned long flags;
c6fa17ed 3436 u16 pci_cmd, num_mac;
e98a1302 3437 u32 hw_rev;
b481de9c 3438
316c30d9
AK
3439 /************************
3440 * 1. Allocating HW data
3441 ************************/
3442
dc21b545 3443 hw = iwl_alloc_all(cfg);
1d0a082d 3444 if (!hw) {
b481de9c
ZY
3445 err = -ENOMEM;
3446 goto out;
3447 }
1d0a082d
AK
3448 priv = hw->priv;
3449 /* At this point both hw and priv are allocated. */
3450
ca7966c8
JB
3451 priv->ucode_type = UCODE_SUBTYPE_NONE_LOADED;
3452
246ed355
JB
3453 /*
3454 * The default context is always valid,
3455 * more may be discovered when firmware
3456 * is loaded.
3457 */
3458 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3459
3460 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3461 priv->contexts[i].ctxid = i;
3462
763cc3bf
JB
3463 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3464 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
8f2d3d2a
JB
3465 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3466 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3467 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 3468 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 3469 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
c10afb6e 3470 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
e72f368b
JB
3471 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3472 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
d0fe478c
JB
3473 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3474 BIT(NL80211_IFTYPE_ADHOC);
3475 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3476 BIT(NL80211_IFTYPE_STATION);
2295c66b 3477 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
d0fe478c
JB
3478 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3479 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3480 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
ece9c4ee
JB
3481
3482 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3483 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3484 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3485 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3486 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3487 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3488 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3489 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
e72f368b
JB
3490 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3491 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3492 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
d0fe478c
JB
3493 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3494 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
f35c0c56
WYG
3495#ifdef CONFIG_IWL_P2P
3496 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3497 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3498#endif
d0fe478c
JB
3499 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3500 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3501 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
ece9c4ee
JB
3502
3503 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
8f2d3d2a 3504
b481de9c
ZY
3505 SET_IEEE80211_DEV(hw, &pdev->dev);
3506
e1623446 3507 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3508 priv->cfg = cfg;
b481de9c 3509 priv->pci_dev = pdev;
40cefda9 3510 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3511
bee008b7
WYG
3512 /* is antenna coupling more than 35dB ? */
3513 priv->bt_ant_couple_ok =
3514 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3515 true : false;
3516
9f28ebc3 3517 /* enable/disable bt channel inhibition */
f37837c9 3518 priv->bt_ch_announce = iwlagn_bt_ch_announce;
9f28ebc3
WYG
3519 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3520 (priv->bt_ch_announce) ? "On" : "Off");
f37837c9 3521
20594eb0
WYG
3522 if (iwl_alloc_traffic_mem(priv))
3523 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3524
316c30d9
AK
3525 /**************************
3526 * 2. Initializing PCI bus
3527 **************************/
1a7123cd
JL
3528 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3529 PCIE_LINK_STATE_CLKPM);
3530
316c30d9
AK
3531 if (pci_enable_device(pdev)) {
3532 err = -ENODEV;
3533 goto out_ieee80211_free_hw;
3534 }
3535
3536 pci_set_master(pdev);
3537
093d874c 3538 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3539 if (!err)
093d874c 3540 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3541 if (err) {
093d874c 3542 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3543 if (!err)
093d874c 3544 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3545 /* both attempts failed: */
316c30d9 3546 if (err) {
978785a3 3547 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3548 goto out_pci_disable_device;
cc2a8ea8 3549 }
316c30d9
AK
3550 }
3551
3552 err = pci_request_regions(pdev, DRV_NAME);
3553 if (err)
3554 goto out_pci_disable_device;
3555
3556 pci_set_drvdata(pdev, priv);
3557
316c30d9
AK
3558
3559 /***********************
3560 * 3. Read REV register
3561 ***********************/
3562 priv->hw_base = pci_iomap(pdev, 0, 0);
3563 if (!priv->hw_base) {
3564 err = -ENODEV;
3565 goto out_pci_release_regions;
3566 }
3567
e1623446 3568 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3569 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3570 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3571
731a29b7 3572 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA
3573 * we should init now
3574 */
3575 spin_lock_init(&priv->reg_lock);
731a29b7 3576 spin_lock_init(&priv->lock);
4843b5a7
RC
3577
3578 /*
3579 * stop and reset the on-board processor just in case it is in a
3580 * strange state ... like being left stranded by a primary kernel
3581 * and this is now the kdump kernel trying to start up
3582 */
3583 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3584
e98a1302 3585 hw_rev = iwl_hw_detect(priv);
c11362c0 3586 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
e98a1302 3587 priv->cfg->name, hw_rev);
316c30d9 3588
e7b63581
TW
3589 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3590 * PCI Tx retries from interfering with C3 CPU state */
3591 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3592
4cd2bf76 3593 if (iwl_prepare_card_hw(priv)) {
086ed117
MA
3594 IWL_WARN(priv, "Failed, HW not ready\n");
3595 goto out_iounmap;
3596 }
3597
91238714
TW
3598 /*****************
3599 * 4. Read EEPROM
3600 *****************/
316c30d9 3601 /* Read the EEPROM */
e98a1302 3602 err = iwl_eeprom_init(priv, hw_rev);
316c30d9 3603 if (err) {
15b1687c 3604 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3605 goto out_iounmap;
3606 }
8614f360
TW
3607 err = iwl_eeprom_check_version(priv);
3608 if (err)
c8f16138 3609 goto out_free_eeprom;
8614f360 3610
21a5b3c6
WYG
3611 err = iwl_eeprom_check_sku(priv);
3612 if (err)
3613 goto out_free_eeprom;
3614
02883017 3615 /* extract MAC Address */
c6fa17ed
WYG
3616 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3617 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3618 priv->hw->wiphy->addresses = priv->addresses;
3619 priv->hw->wiphy->n_addresses = 1;
3620 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3621 if (num_mac > 1) {
3622 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3623 ETH_ALEN);
3624 priv->addresses[1].addr[5]++;
3625 priv->hw->wiphy->n_addresses++;
3626 }
316c30d9
AK
3627
3628 /************************
3629 * 5. Setup HW constants
3630 ************************/
da154e30 3631 if (iwl_set_hw_params(priv)) {
15b1687c 3632 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3633 goto out_free_eeprom;
316c30d9
AK
3634 }
3635
3636 /*******************
6ba87956 3637 * 6. Setup priv
316c30d9 3638 *******************/
b481de9c 3639
6ba87956 3640 err = iwl_init_drv(priv);
bf85ea4f 3641 if (err)
399f4900 3642 goto out_free_eeprom;
bf85ea4f 3643 /* At this point both hw and priv are initialized. */
316c30d9 3644
316c30d9 3645 /********************
09f9bf79 3646 * 7. Setup services
316c30d9 3647 ********************/
0359facc 3648 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3649 iwl_disable_interrupts(priv);
0359facc 3650 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3651
6cd0b1cb
HS
3652 pci_enable_msi(priv->pci_dev);
3653
519d8abd 3654 iwl_alloc_isr_ict(priv);
e39fdee1 3655
519d8abd 3656 err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
ef850d7c 3657 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3658 if (err) {
3659 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3660 goto out_disable_msi;
3661 }
316c30d9 3662
4e39317d 3663 iwl_setup_deferred_work(priv);
653fa4a0 3664 iwl_setup_rx_handlers(priv);
4613e72d 3665 iwl_testmode_init(priv);
316c30d9 3666
158bea07
JB
3667 /*********************************************
3668 * 8. Enable interrupts and read RFKILL state
3669 *********************************************/
6ba87956 3670
554d1d02 3671 /* enable rfkill interrupt: hw bug w/a */
6cd0b1cb
HS
3672 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3673 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3674 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3675 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3676 }
3677
554d1d02 3678 iwl_enable_rfkill_int(priv);
6cd0b1cb 3679
6cd0b1cb
HS
3680 /* If platform's RF_KILL switch is NOT set to KILL */
3681 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3682 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3683 else
3684 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3685
a60e77e5
JB
3686 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3687 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3688
58d0f361 3689 iwl_power_initialize(priv);
39b73fb1 3690 iwl_tt_initialize(priv);
158bea07 3691
a15707d8 3692 init_completion(&priv->_agn.firmware_loading_complete);
562db532 3693
b08dfd04 3694 err = iwl_request_firmware(priv, true);
158bea07 3695 if (err)
7d47618a 3696 goto out_destroy_workqueue;
158bea07 3697
b481de9c
ZY
3698 return 0;
3699
7d47618a 3700 out_destroy_workqueue:
c8f16138
RC
3701 destroy_workqueue(priv->workqueue);
3702 priv->workqueue = NULL;
795cc0ad 3703 free_irq(priv->pci_dev->irq, priv);
6cd0b1cb 3704 out_disable_msi:
93cce6f0 3705 iwl_free_isr_ict(priv);
6cd0b1cb 3706 pci_disable_msi(priv->pci_dev);
6ba87956 3707 iwl_uninit_drv(priv);
073d3f5f
TW
3708 out_free_eeprom:
3709 iwl_eeprom_free(priv);
b481de9c
ZY
3710 out_iounmap:
3711 pci_iounmap(pdev, priv->hw_base);
3712 out_pci_release_regions:
316c30d9 3713 pci_set_drvdata(pdev, NULL);
623d563e 3714 pci_release_regions(pdev);
b481de9c
ZY
3715 out_pci_disable_device:
3716 pci_disable_device(pdev);
b481de9c 3717 out_ieee80211_free_hw:
20594eb0 3718 iwl_free_traffic_mem(priv);
d7c76f4c 3719 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3720 out:
3721 return err;
3722}
3723
5b9f8cd3 3724static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3725{
c79dd5b5 3726 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3727 unsigned long flags;
b481de9c
ZY
3728
3729 if (!priv)
3730 return;
3731
a15707d8 3732 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 3733
e1623446 3734 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3735
67249625 3736 iwl_dbgfs_unregister(priv);
5b9f8cd3 3737 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3738
5b9f8cd3
EG
3739 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3740 * to be called and iwl_down since we are removing the device
0b124c31
GG
3741 * we need to set STATUS_EXIT_PENDING bit.
3742 */
3743 set_bit(STATUS_EXIT_PENDING, &priv->status);
5ed540ae 3744
7a4e5281 3745 iwl_testmode_cleanup(priv);
5ed540ae
WYG
3746 iwl_leds_exit(priv);
3747
c4f55232
RR
3748 if (priv->mac80211_registered) {
3749 ieee80211_unregister_hw(priv->hw);
3750 priv->mac80211_registered = 0;
3751 }
3752
1a10f433 3753 /* Reset to low power before unloading driver. */
14e8e4af 3754 iwl_apm_stop(priv);
c166b25a 3755
39b73fb1
WYG
3756 iwl_tt_exit(priv);
3757
0359facc
MA
3758 /* make sure we flush any pending irq or
3759 * tasklet for the driver
3760 */
3761 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3762 iwl_disable_interrupts(priv);
0359facc
MA
3763 spin_unlock_irqrestore(&priv->lock, flags);
3764
3765 iwl_synchronize_irq(priv);
3766
5b9f8cd3 3767 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3768
3769 if (priv->rxq.bd)
54b81550 3770 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 3771 iwlagn_hw_txq_ctx_free(priv);
b481de9c 3772
073d3f5f 3773 iwl_eeprom_free(priv);
b481de9c 3774
b481de9c 3775
948c171c
MA
3776 /*netif_stop_queue(dev); */
3777 flush_workqueue(priv->workqueue);
3778
5b9f8cd3 3779 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3780 * priv->workqueue... so we can't take down the workqueue
3781 * until now... */
3782 destroy_workqueue(priv->workqueue);
3783 priv->workqueue = NULL;
20594eb0 3784 iwl_free_traffic_mem(priv);
b481de9c 3785
6cd0b1cb
HS
3786 free_irq(priv->pci_dev->irq, priv);
3787 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3788 pci_iounmap(pdev, priv->hw_base);
3789 pci_release_regions(pdev);
3790 pci_disable_device(pdev);
3791 pci_set_drvdata(pdev, NULL);
3792
6ba87956 3793 iwl_uninit_drv(priv);
b481de9c 3794
519d8abd 3795 iwl_free_isr_ict(priv);
ef850d7c 3796
77834543 3797 dev_kfree_skb(priv->beacon_skb);
b481de9c
ZY
3798
3799 ieee80211_free_hw(priv->hw);
3800}
3801
b481de9c
ZY
3802
3803/*****************************************************************************
3804 *
3805 * driver and module entry point
3806 *
3807 *****************************************************************************/
3808
fed9017e 3809/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 3810static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
ac592574
WYG
3811 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3812 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3813 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3814 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3815 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3816 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3817 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3818 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3819 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3820 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3821 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3822 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3823 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3824 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3825 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3826 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3827 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3828 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3829 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3830 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3831 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3832 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3833 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3834 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3835
3836/* 5300 Series WiFi */
3837 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3838 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3839 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3840 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3841 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3842 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3843 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3844 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3845 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3846 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3847 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3848 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3849
3850/* 5350 Series WiFi/WiMax */
3851 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3852 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3853 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3854
3855/* 5150 Series Wifi/WiMax */
3856 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
3857 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
3858 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
3859 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
3860 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
3861 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
3862
3863 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
3864 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
3865 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
3866 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG
3867
3868/* 6x00 Series */
5953a62e
WYG
3869 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3870 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3871 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3872 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3873 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3874 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3875 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3876 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3877 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3878 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 3879
003ea981 3880/* 6x05 Series */
8b3ee296
WYG
3881 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
3882 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
3883 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
3884 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
3885 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
3886 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
3887 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
1808972f 3888
003ea981 3889/* 6x30 Series */
8b3ee296
WYG
3890 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
3891 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
3892 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
3893 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
3894 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
3895 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
3896 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
3897 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
3898 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
3899 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
3900 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
3901 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
3902 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
3903 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
3904 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
3905 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
5953a62e
WYG
3906
3907/* 6x50 WiFi/WiMax Series */
5953a62e
WYG
3908 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3909 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3910 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3911 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG
3912 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3913 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3914
003ea981 3915/* 6150 WiFi/WiMax Series */
8b3ee296
WYG
3916 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
3917 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
3918 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
3919 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
3920 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
3921 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
03264339 3922
77dcb6a9 3923/* 1000 Series WiFi */
4bd0914f
WYG
3924 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3925 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3926 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3927 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3928 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3929 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3930 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3931 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3932 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3933 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3934 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3935 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
1de19ecc 3936
58a39090 3937/* 100 Series WiFi */
1de19ecc 3938 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
2a21ff44 3939 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
1de19ecc 3940 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
2a21ff44 3941 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
1de19ecc 3942 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
2a21ff44 3943 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
58a39090
WYG
3944
3945/* 130 Series WiFi */
3946 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
3947 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
3948 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
3949 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
3950 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
3951 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
3952
04b8e751
WYG
3953/* 2x00 Series */
3954 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
3955 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
3956 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
3957 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
3958 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
3959 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
3960
3961/* 2x30 Series */
3962 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
3963 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
3964 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
3965 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
3966 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
3967 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
3968
3969/* 6x35 Series */
3970 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
3971 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
3972 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
3973 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
3974 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
3975 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
3976 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
3977 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
3978 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
3979
b4ed221d
WYG
3980/* 105 Series */
3981 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
3982 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
3983 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
3984 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)},
3985 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)},
3986 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)},
3987
3988/* 135 Series */
3989 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
3990 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
3991 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
3992 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)},
3993 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)},
3994 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)},
04b8e751 3995
fed9017e
RR
3996 {0}
3997};
3998MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3999
4000static struct pci_driver iwl_driver = {
b481de9c 4001 .name = DRV_NAME,
fed9017e 4002 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
4003 .probe = iwl_pci_probe,
4004 .remove = __devexit_p(iwl_pci_remove),
f60dc013 4005 .driver.pm = IWL_PM_OPS,
b481de9c
ZY
4006};
4007
5b9f8cd3 4008static int __init iwl_init(void)
b481de9c
ZY
4009{
4010
4011 int ret;
c96c31e4
JP
4012 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4013 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4014
e227ceac 4015 ret = iwlagn_rate_control_register();
897e1cf2 4016 if (ret) {
c96c31e4 4017 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
4018 return ret;
4019 }
4020
fed9017e 4021 ret = pci_register_driver(&iwl_driver);
b481de9c 4022 if (ret) {
c96c31e4 4023 pr_err("Unable to initialize PCI module\n");
897e1cf2 4024 goto error_register;
b481de9c 4025 }
b481de9c
ZY
4026
4027 return ret;
897e1cf2 4028
897e1cf2 4029error_register:
e227ceac 4030 iwlagn_rate_control_unregister();
897e1cf2 4031 return ret;
b481de9c
ZY
4032}
4033
5b9f8cd3 4034static void __exit iwl_exit(void)
b481de9c 4035{
fed9017e 4036 pci_unregister_driver(&iwl_driver);
e227ceac 4037 iwlagn_rate_control_unregister();
b481de9c
ZY
4038}
4039
5b9f8cd3
EG
4040module_exit(iwl_exit);
4041module_init(iwl_init);
a562a9dd
RC
4042
4043#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4044module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
4045MODULE_PARM_DESC(debug, "debug output mask");
4046#endif
4047
2b068618
WYG
4048module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4049MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
2b068618
WYG
4050module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4051MODULE_PARM_DESC(queues_num, "number of hw queues.");
2b068618
WYG
4052module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4053MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
2b068618
WYG
4054module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4055 int, S_IRUGO);
4056MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
2b068618
WYG
4057module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4058MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
dd7a2509
JB
4059
4060module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4061 S_IRUGO);
4062MODULE_PARM_DESC(ucode_alternative,
4063 "specify ucode alternative to use from ucode file");
bee008b7
WYG
4064
4065module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4066MODULE_PARM_DESC(antenna_coupling,
4067 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9 4068
9f28ebc3
WYG
4069module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4070MODULE_PARM_DESC(bt_ch_inhibition,
4071 "Disable BT channel inhibition (default: enable)");
b7977ffa
SG
4072
4073module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4074MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4075
4076module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4077MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
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