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iwlagn: rename iwl5000_tx_resp
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
c96c31e4
JP		 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
b481de9c
ZY		 32#include <linux/kernel.h>
33#include <linux/module.h>
b481de9c
ZY		 34#include <linux/init.h>
35#include <linux/pci.h>
1a7123cd 36#include <linux/pci-aspm.h>
5a0e3ad6 37#include <linux/slab.h>
b481de9c
ZY		 38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
d43c36dc 40#include <linux/sched.h>
b481de9c
ZY		 41#include <linux/skbuff.h>
42#include <linux/netdevice.h>
43#include <linux/wireless.h>
44#include <linux/firmware.h>
b481de9c
ZY		 45#include <linux/etherdevice.h>
46#include <linux/if_arp.h>
47
b481de9c
ZY		 48#include <net/mac80211.h>
49
50#include <asm/div64.h>
51
a3139c59
SO		 52#define DRV_NAME "iwlagn"
53
6bc913bd 54#include "iwl-eeprom.h"
3e0d4cb1 55#include "iwl-dev.h"
fee1247a 56#include "iwl-core.h"
3395f6e9 57#include "iwl-io.h"
b481de9c 58#include "iwl-helpers.h"
6974e363 59#include "iwl-sta.h"
f0832f13 60#include "iwl-calib.h"
a1175124 61#include "iwl-agn.h"
b481de9c 62
416e1438 63
b481de9c
ZY		 64/******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
b481de9c
ZY		 70/*
71 * module name, copyright, version, etc.
b481de9c 72 */
d783b061 73#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 74
0a6857e7 75#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 76#define VD "d"
77#else
78#define VD
79#endif
80
81963d68 81#define DRV_VERSION IWLWIFI_VERSION VD
b481de9c 82
b481de9c
ZY		 83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
bee008b7 90static int iwlagn_ant_coupling;
f37837c9 91static bool iwlagn_bt_ch_announce = 1;
bee008b7 92
b481de9c 93/**
5b9f8cd3 94 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 95 *
01ebd063 96 * The RXON command in staging_rxon is committed to the hardware and
b481de9c
ZY		 97 * the active_rxon structure is updated with the new data. This
98 * function correctly transitions out of the RXON_ASSOC_MSK state if
99 * a HW tune is required based on the RXON structure changes.
100 */
246ed355 101int iwl_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
b481de9c
ZY		 102{
103 /* cast away the const for active_rxon in this function */
246ed355 104 struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
43d59b32
EG		 105 int ret;
106 bool new_assoc =
246ed355 107 !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
b01efe43 108 bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 109
fee1247a 110 if (!iwl_is_alive(priv))
43d59b32 111 return -EBUSY;
b481de9c 112
763cc3bf
JB		 113 if (!ctx->is_active)
114 return 0;
115
b481de9c 116 /* always get timestamp with Rx frame */
246ed355 117 ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
b481de9c 118
246ed355 119 ret = iwl_check_rxon_cmd(priv, ctx);
43d59b32 120 if (ret) {
15b1687c 121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
b481de9c
ZY		 122 return -EINVAL;
123 }
124
0924e519
WYG		 125 /*
126 * receive commit_rxon request
127 * abort any previous channel switch if still in process
128 */
129 if (priv->switch_rxon.switch_in_progress &&
246ed355 130 (priv->switch_rxon.channel != ctx->staging.channel)) {
0924e519
WYG		 131 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
132 le16_to_cpu(priv->switch_rxon.channel));
79d07325 133 iwl_chswitch_done(priv, false);
0924e519
WYG		 134 }
135
b481de9c 136 /* If we don't need to send a full RXON, we can use
5b9f8cd3 137 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 138 * and other flags for the current radio configuration. */
246ed355
JB		 139 if (!iwl_full_rxon_required(priv, ctx)) {
140 ret = iwl_send_rxon_assoc(priv, ctx);
43d59b32 141 if (ret) {
15b1687c 142 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 143 return ret;
b481de9c
ZY		 144 }
145
246ed355
JB		 146 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
147 iwl_print_rx_config_cmd(priv, ctx);
b481de9c
ZY		 148 return 0;
149 }
150
b481de9c
ZY		 151 /* If we are currently associated and the new config requires
152 * an RXON_ASSOC and the new config wants the associated mask enabled,
153 * we must clear the associated from the active configuration
154 * before we apply the new config */
246ed355 155 if (iwl_is_associated_ctx(ctx) && new_assoc) {
e1623446 156 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
b481de9c
ZY		 157 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
158
8f2d3d2a 159 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355
JB		 160 sizeof(struct iwl_rxon_cmd),
161 active_rxon);
b481de9c
ZY		 162
163 /* If the mask clearing failed then we set
164 * active_rxon back to what it was previously */
43d59b32 165 if (ret) {
b481de9c 166 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 167 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 168 return ret;
b481de9c 169 }
dcef732c
JB		 170 iwl_clear_ucode_stations(priv, ctx);
171 iwl_restore_stations(priv, ctx);
c10afb6e 172 ret = iwl_restore_default_wep_keys(priv, ctx);
335348b1
JB		 173 if (ret) {
174 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
175 return ret;
176 }
b481de9c
ZY		 177 }
178
e1623446 179 IWL_DEBUG_INFO(priv, "Sending RXON\n"
b481de9c
ZY		 180 "* with%s RXON_FILTER_ASSOC_MSK\n"
181 "* channel = %d\n"
e174961c 182 "* bssid = %pM\n",
43d59b32 183 (new_assoc ? "" : "out"),
246ed355
JB		 184 le16_to_cpu(ctx->staging.channel),
185 ctx->staging.bssid_addr);
b481de9c 186
246ed355 187 iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
43d59b32 188
b01efe43 189 if (!old_assoc) {
2491fa42
JB		 190 /*
191 * First of all, before setting associated, we need to
192 * send RXON timing so the device knows about the DTIM
193 * period and other timing values
194 */
47313e34 195 ret = iwl_send_rxon_timing(priv, ctx);
2491fa42
JB		 196 if (ret) {
197 IWL_ERR(priv, "Error setting RXON timing!\n");
198 return ret;
199 }
200 }
201
52a02d15
JB		 202 if (priv->cfg->ops->hcmd->set_pan_params) {
203 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
204 if (ret)
205 return ret;
206 }
207
43d59b32 208 /* Apply the new configuration
7e246191
RC		 209 * RXON unassoc clears the station table in uCode so restoration of
210 * stations is needed after it (the RXON command) completes
43d59b32
EG		 211 */
212 if (!new_assoc) {
8f2d3d2a 213 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 214 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 215 if (ret) {
15b1687c 216 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 217 return ret;
218 }
91dd6c27 219 IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
246ed355 220 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
dcef732c
JB		 221 iwl_clear_ucode_stations(priv, ctx);
222 iwl_restore_stations(priv, ctx);
c10afb6e 223 ret = iwl_restore_default_wep_keys(priv, ctx);
335348b1
JB		 224 if (ret) {
225 IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
226 return ret;
227 }
b481de9c 228 }
9185159d 229 if (new_assoc) {
8f1d9687 230 priv->start_calib = 0;
43d59b32
EG		 231 /* Apply the new configuration
232 * RXON assoc doesn't clear the station table in uCode,
233 */
8f2d3d2a 234 ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
246ed355 235 sizeof(struct iwl_rxon_cmd), &ctx->staging);
43d59b32 236 if (ret) {
15b1687c 237 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG		 238 return ret;
239 }
246ed355 240 memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
b481de9c 241 }
246ed355 242 iwl_print_rx_config_cmd(priv, ctx);
b481de9c 243
36da7d70
ZY		 244 iwl_init_sensitivity(priv);
245
246 /* If we issue a new RXON command which required a tune then we must
247 * send a new TXPOWER command or we won't be able to Tx any frames */
248 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
249 if (ret) {
15b1687c 250 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
ZY		 251 return ret;
252 }
253
b481de9c
ZY		 254 return 0;
255}
256
5b9f8cd3 257void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f 258{
246ed355 259 struct iwl_rxon_context *ctx;
5da4b55f 260
246ed355
JB		 261 if (priv->cfg->ops->hcmd->set_rxon_chain) {
262 for_each_context(priv, ctx) {
263 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
264 iwlcore_commit_rxon(priv, ctx);
265 }
266 }
5da4b55f
MA		 267}
268
fcab423d 269static void iwl_clear_free_frames(struct iwl_priv *priv)
b481de9c
ZY		 270{
271 struct list_head *element;
272
e1623446 273 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
ZY		 274 priv->frames_count);
275
276 while (!list_empty(&priv->free_frames)) {
277 element = priv->free_frames.next;
278 list_del(element);
fcab423d 279 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
ZY		 280 priv->frames_count--;
281 }
282
283 if (priv->frames_count) {
39aadf8c 284 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
ZY		 285 priv->frames_count);
286 priv->frames_count = 0;
287 }
288}
289
fcab423d 290static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 291{
fcab423d 292 struct iwl_frame *frame;
b481de9c
ZY		 293 struct list_head *element;
294 if (list_empty(&priv->free_frames)) {
295 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
296 if (!frame) {
15b1687c 297 IWL_ERR(priv, "Could not allocate frame!\n");
b481de9c
ZY		 298 return NULL;
299 }
300
301 priv->frames_count++;
302 return frame;
303 }
304
305 element = priv->free_frames.next;
306 list_del(element);
fcab423d 307 return list_entry(element, struct iwl_frame, list);
b481de9c
ZY		 308}
309
fcab423d 310static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
ZY		 311{
312 memset(frame, 0, sizeof(*frame));
313 list_add(&frame->list, &priv->free_frames);
314}
315
47ff65c4 316static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
4bf64efd 317 struct ieee80211_hdr *hdr,
73ec1cc2 318 int left)
b481de9c 319{
6abbe554 320 if (!priv->ibss_beacon)
b481de9c
ZY		 321 return 0;
322
323 if (priv->ibss_beacon->len > left)
324 return 0;
325
326 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
327
328 return priv->ibss_beacon->len;
329}
330
47ff65c4
DH		 331/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
332static void iwl_set_beacon_tim(struct iwl_priv *priv,
333 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
334 u8 *beacon, u32 frame_size)
335{
336 u16 tim_idx;
337 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
338
339 /*
340 * The index is relative to frame start but we start looking at the
341 * variable-length part of the beacon.
342 */
343 tim_idx = mgmt->u.beacon.variable - beacon;
344
345 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
346 while ((tim_idx < (frame_size - 2)) &&
347 (beacon[tim_idx] != WLAN_EID_TIM))
348 tim_idx += beacon[tim_idx+1] + 2;
349
350 /* If TIM field was found, set variables */
351 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
352 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
353 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
354 } else
355 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
356}
357
5b9f8cd3 358static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
47ff65c4 359 struct iwl_frame *frame)
4bf64efd
TW		 360{
361 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
47ff65c4
DH		 362 u32 frame_size;
363 u32 rate_flags;
364 u32 rate;
365 /*
366 * We have to set up the TX command, the TX Beacon command, and the
367 * beacon contents.
368 */
4bf64efd 369
76d04815
JB		 370 lockdep_assert_held(&priv->mutex);
371
372 if (!priv->beacon_ctx) {
373 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
950094cb 374 return 0;
76d04815
JB		 375 }
376
47ff65c4 377 /* Initialize memory */
4bf64efd
TW		 378 tx_beacon_cmd = &frame->u.beacon;
379 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
380
47ff65c4 381 /* Set up TX beacon contents */
4bf64efd 382 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd 383 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
47ff65c4
DH		 384 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
385 return 0;
4bf64efd 386
47ff65c4 387 /* Set up TX command fields */
4bf64efd 388 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
76d04815 389 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
47ff65c4
DH		 390 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
391 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
392 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
4bf64efd 393
47ff65c4
DH		 394 /* Set up TX beacon command fields */
395 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
396 frame_size);
4bf64efd 397
47ff65c4 398 /* Set up packet rate and flags */
76d04815 399 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
0e1654fa
JB		 400 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
401 priv->hw_params.valid_tx_ant);
47ff65c4
DH		 402 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
403 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
404 rate_flags |= RATE_MCS_CCK_MSK;
405 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
406 rate_flags);
4bf64efd
TW		 407
408 return sizeof(*tx_beacon_cmd) + frame_size;
409}
5b9f8cd3 410static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 411{
fcab423d 412 struct iwl_frame *frame;
b481de9c
ZY		 413 unsigned int frame_size;
414 int rc;
b481de9c 415
fcab423d 416 frame = iwl_get_free_frame(priv);
b481de9c 417 if (!frame) {
15b1687c 418 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
ZY		 419 "command.\n");
420 return -ENOMEM;
421 }
422
47ff65c4
DH		 423 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
424 if (!frame_size) {
425 IWL_ERR(priv, "Error configuring the beacon command\n");
426 iwl_free_frame(priv, frame);
427 return -EINVAL;
428 }
b481de9c 429
857485c0 430 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
ZY		 431 &frame->u.cmd[0]);
432
fcab423d 433 iwl_free_frame(priv, frame);
b481de9c
ZY		 434
435 return rc;
436}
437
7aaa1d79
SO		 438static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
439{
440 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
441
442 dma_addr_t addr = get_unaligned_le32(&tb->lo);
443 if (sizeof(dma_addr_t) > sizeof(u32))
444 addr |=
445 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
446
447 return addr;
448}
449
450static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
451{
452 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
453
454 return le16_to_cpu(tb->hi_n_len) >> 4;
455}
456
457static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
458 dma_addr_t addr, u16 len)
459{
460 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
461 u16 hi_n_len = len << 4;
462
463 put_unaligned_le32(addr, &tb->lo);
464 if (sizeof(dma_addr_t) > sizeof(u32))
465 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
466
467 tb->hi_n_len = cpu_to_le16(hi_n_len);
468
469 tfd->num_tbs = idx + 1;
470}
471
472static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
473{
474 return tfd->num_tbs & 0x1f;
475}
476
477/**
478 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
479 * @priv - driver private data
480 * @txq - tx queue
481 *
482 * Does NOT advance any TFD circular buffer read/write indexes
483 * Does NOT free the TFD itself (which is within circular buffer)
484 */
485void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
486{
59606ffa 487 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO		 488 struct iwl_tfd *tfd;
489 struct pci_dev *dev = priv->pci_dev;
490 int index = txq->q.read_ptr;
491 int i;
492 int num_tbs;
493
494 tfd = &tfd_tmp[index];
495
496 /* Sanity check on number of chunks */
497 num_tbs = iwl_tfd_get_num_tbs(tfd);
498
499 if (num_tbs >= IWL_NUM_OF_TBS) {
500 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
501 /* @todo issue fatal error, it is quite serious situation */
502 return;
503 }
504
505 /* Unmap tx_cmd */
506 if (num_tbs)
507 pci_unmap_single(dev,
2e724443
FT		 508 dma_unmap_addr(&txq->meta[index], mapping),
509 dma_unmap_len(&txq->meta[index], len),
96891cee 510 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO		 511
512 /* Unmap chunks, if any. */
ff0d91c3 513 for (i = 1; i < num_tbs; i++)
7aaa1d79
SO		 514 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
515 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
516
ff0d91c3
JB		 517 /* free SKB */
518 if (txq->txb) {
519 struct sk_buff *skb;
6f80240e 520
ff0d91c3 521 skb = txq->txb[txq->q.read_ptr].skb;
6f80240e 522
ff0d91c3
JB		 523 /* can be called from irqs-disabled context */
524 if (skb) {
525 dev_kfree_skb_any(skb);
526 txq->txb[txq->q.read_ptr].skb = NULL;
7aaa1d79
SO		 527 }
528 }
529}
530
531int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
532 struct iwl_tx_queue *txq,
533 dma_addr_t addr, u16 len,
534 u8 reset, u8 pad)
535{
536 struct iwl_queue *q;
59606ffa 537 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 538 u32 num_tbs;
539
540 q = &txq->q;
59606ffa
SO		 541 tfd_tmp = (struct iwl_tfd *)txq->tfds;
542 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 543
544 if (reset)
545 memset(tfd, 0, sizeof(*tfd));
546
547 num_tbs = iwl_tfd_get_num_tbs(tfd);
548
549 /* Each TFD can point to a maximum 20 Tx buffers */
550 if (num_tbs >= IWL_NUM_OF_TBS) {
551 IWL_ERR(priv, "Error can not send more than %d chunks\n",
552 IWL_NUM_OF_TBS);
553 return -EINVAL;
554 }
555
556 BUG_ON(addr & ~DMA_BIT_MASK(36));
557 if (unlikely(addr & ~IWL_TX_DMA_MASK))
558 IWL_ERR(priv, "Unaligned address = %llx\n",
559 (unsigned long long)addr);
560
561 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
562
563 return 0;
564}
565
a8e74e27
SO		 566/*
567 * Tell nic where to find circular buffer of Tx Frame Descriptors for
568 * given Tx queue, and enable the DMA channel used for that queue.
569 *
570 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
571 * channels supported in hardware.
572 */
573int iwl_hw_tx_queue_init(struct iwl_priv *priv,
574 struct iwl_tx_queue *txq)
575{
a8e74e27
SO		 576 int txq_id = txq->q.id;
577
a8e74e27
SO		 578 /* Circular buffer (TFD queue in DRAM) physical base address */
579 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
580 txq->q.dma_addr >> 8);
581
a8e74e27
SO		 582 return 0;
583}
584
b481de9c
ZY		 585/******************************************************************************
586 *
587 * Generic RX handler implementations
588 *
589 ******************************************************************************/
885ba202
TW		 590static void iwl_rx_reply_alive(struct iwl_priv *priv,
591 struct iwl_rx_mem_buffer *rxb)
b481de9c 592{
2f301227 593 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 594 struct iwl_alive_resp *palive;
b481de9c
ZY		 595 struct delayed_work *pwork;
596
597 palive = &pkt->u.alive_frame;
598
e1623446 599 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY		 600 "0x%01X 0x%01X\n",
601 palive->is_valid, palive->ver_type,
602 palive->ver_subtype);
603
604 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 605 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY		 606 memcpy(&priv->card_alive_init,
607 &pkt->u.alive_frame,
885ba202 608 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY		 609 pwork = &priv->init_alive_start;
610 } else {
e1623446 611 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 612 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 613 sizeof(struct iwl_alive_resp));
b481de9c
ZY		 614 pwork = &priv->alive_start;
615 }
616
617 /* We delay the ALIVE response by 5ms to
618 * give the HW RF Kill time to activate... */
619 if (palive->is_valid == UCODE_VALID_OK)
620 queue_delayed_work(priv->workqueue, pwork,
621 msecs_to_jiffies(5));
622 else
39aadf8c 623 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY		 624}
625
5b9f8cd3 626static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 627{
c79dd5b5
TW		 628 struct iwl_priv *priv =
629 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY		 630 struct sk_buff *beacon;
631
76d04815
JB		 632 mutex_lock(&priv->mutex);
633 if (!priv->beacon_ctx) {
634 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
635 goto out;
636 }
b481de9c 637
60744f62
JB		 638 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
639 /*
640 * The ucode will send beacon notifications even in
641 * IBSS mode, but we don't want to process them. But
642 * we need to defer the type check to here due to
643 * requiring locking around the beacon_ctx access.
644 */
645 goto out;
646 }
647
76d04815
JB		 648 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
649 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
b481de9c 650 if (!beacon) {
15b1687c 651 IWL_ERR(priv, "update beacon failed\n");
76d04815 652 goto out;
b481de9c
ZY		 653 }
654
b481de9c
ZY		 655 /* new beacon skb is allocated every time; dispose previous.*/
656 if (priv->ibss_beacon)
657 dev_kfree_skb(priv->ibss_beacon);
658
659 priv->ibss_beacon = beacon;
b481de9c 660
5b9f8cd3 661 iwl_send_beacon_cmd(priv);
76d04815
JB		 662 out:
663 mutex_unlock(&priv->mutex);
b481de9c
ZY		 664}
665
fbba9410
WYG		 666static void iwl_bg_bt_runtime_config(struct work_struct *work)
667{
668 struct iwl_priv *priv =
669 container_of(work, struct iwl_priv, bt_runtime_config);
670
671 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
672 return;
673
674 /* dont send host command if rf-kill is on */
675 if (!iwl_is_ready_rf(priv))
676 return;
677 priv->cfg->ops->hcmd->send_bt_config(priv);
678}
679
bee008b7
WYG		 680static void iwl_bg_bt_full_concurrency(struct work_struct *work)
681{
682 struct iwl_priv *priv =
683 container_of(work, struct iwl_priv, bt_full_concurrency);
246ed355 684 struct iwl_rxon_context *ctx;
bee008b7
WYG		 685
686 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
687 return;
688
689 /* dont send host command if rf-kill is on */
690 if (!iwl_is_ready_rf(priv))
691 return;
692
693 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
694 priv->bt_full_concurrent ?
695 "full concurrency" : "3-wire");
696
697 /*
698 * LQ & RXON updated cmds must be sent before BT Config cmd
699 * to avoid 3-wire collisions
700 */
246ed355
JB		 701 mutex_lock(&priv->mutex);
702 for_each_context(priv, ctx) {
703 if (priv->cfg->ops->hcmd->set_rxon_chain)
704 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
705 iwlcore_commit_rxon(priv, ctx);
706 }
707 mutex_unlock(&priv->mutex);
bee008b7
WYG		 708
709 priv->cfg->ops->hcmd->send_bt_config(priv);
710}
711
4e39317d 712/**
5b9f8cd3 713 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG		 714 *
715 * This callback is provided in order to send a statistics request.
716 *
717 * This timer function is continually reset to execute within
718 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
719 * was received. We need to ensure we receive the statistics in order
720 * to update the temperature used for calibrating the TXPOWER.
721 */
5b9f8cd3 722static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG		 723{
724 struct iwl_priv *priv = (struct iwl_priv *)data;
725
726 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
727 return;
728
61780ee3
MA		 729 /* dont send host command if rf-kill is on */
730 if (!iwl_is_ready_rf(priv))
731 return;
732
ef8d5529 733 iwl_send_statistics_request(priv, CMD_ASYNC, false);
4e39317d
EG		 734}
735
a9e1cb6a
WYG		 736
737static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
738 u32 start_idx, u32 num_events,
739 u32 mode)
740{
741 u32 i;
742 u32 ptr; /* SRAM byte address of log data */
743 u32 ev, time, data; /* event log data */
744 unsigned long reg_flags;
745
746 if (mode == 0)
747 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
748 else
749 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
750
751 /* Make sure device is powered up for SRAM reads */
752 spin_lock_irqsave(&priv->reg_lock, reg_flags);
753 if (iwl_grab_nic_access(priv)) {
754 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
755 return;
756 }
757
758 /* Set starting address; reads will auto-increment */
759 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
760 rmb();
761
762 /*
763 * "time" is actually "data" for mode 0 (no timestamp).
764 * place event id # at far right for easier visual parsing.
765 */
766 for (i = 0; i < num_events; i++) {
767 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
768 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
769 if (mode == 0) {
770 trace_iwlwifi_dev_ucode_cont_event(priv,
771 0, time, ev);
772 } else {
773 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
774 trace_iwlwifi_dev_ucode_cont_event(priv,
775 time, data, ev);
776 }
777 }
778 /* Allow device to power down */
779 iwl_release_nic_access(priv);
780 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
781}
782
875295f1 783static void iwl_continuous_event_trace(struct iwl_priv *priv)
a9e1cb6a
WYG		 784{
785 u32 capacity; /* event log capacity in # entries */
786 u32 base; /* SRAM byte address of event log header */
787 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
788 u32 num_wraps; /* # times uCode wrapped to top of log */
789 u32 next_entry; /* index of next entry to be written by uCode */
790
791 if (priv->ucode_type == UCODE_INIT)
792 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
793 else
794 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
795 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
796 capacity = iwl_read_targ_mem(priv, base);
797 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
798 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
799 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
800 } else
801 return;
802
803 if (num_wraps == priv->event_log.num_wraps) {
804 iwl_print_cont_event_trace(priv,
805 base, priv->event_log.next_entry,
806 next_entry - priv->event_log.next_entry,
807 mode);
808 priv->event_log.non_wraps_count++;
809 } else {
810 if ((num_wraps - priv->event_log.num_wraps) > 1)
811 priv->event_log.wraps_more_count++;
812 else
813 priv->event_log.wraps_once_count++;
814 trace_iwlwifi_dev_ucode_wrap_event(priv,
815 num_wraps - priv->event_log.num_wraps,
816 next_entry, priv->event_log.next_entry);
817 if (next_entry < priv->event_log.next_entry) {
818 iwl_print_cont_event_trace(priv, base,
819 priv->event_log.next_entry,
820 capacity - priv->event_log.next_entry,
821 mode);
822
823 iwl_print_cont_event_trace(priv, base, 0,
824 next_entry, mode);
825 } else {
826 iwl_print_cont_event_trace(priv, base,
827 next_entry, capacity - next_entry,
828 mode);
829
830 iwl_print_cont_event_trace(priv, base, 0,
831 next_entry, mode);
832 }
833 }
834 priv->event_log.num_wraps = num_wraps;
835 priv->event_log.next_entry = next_entry;
836}
837
838/**
839 * iwl_bg_ucode_trace - Timer callback to log ucode event
840 *
841 * The timer is continually set to execute every
842 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
843 * this function is to perform continuous uCode event logging operation
844 * if enabled
845 */
846static void iwl_bg_ucode_trace(unsigned long data)
847{
848 struct iwl_priv *priv = (struct iwl_priv *)data;
849
850 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
851 return;
852
853 if (priv->event_log.ucode_trace) {
854 iwl_continuous_event_trace(priv);
855 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
856 mod_timer(&priv->ucode_trace,
857 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
858 }
859}
860
5b9f8cd3 861static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 862 struct iwl_rx_mem_buffer *rxb)
b481de9c 863{
2f301227 864 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW		 865 struct iwl4965_beacon_notif *beacon =
866 (struct iwl4965_beacon_notif *)pkt->u.raw;
a85d7cca 867#ifdef CONFIG_IWLWIFI_DEBUG
e7d326ac 868 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 869
e1623446 870 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 871 "tsf %d %d rate %d\n",
25a6572c 872 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY		 873 beacon->beacon_notify_hdr.failure_frame,
874 le32_to_cpu(beacon->ibss_mgr_status),
875 le32_to_cpu(beacon->high_tsf),
876 le32_to_cpu(beacon->low_tsf), rate);
877#endif
878
a85d7cca
JB		 879 priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
880
60744f62 881 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 882 queue_work(priv->workqueue, &priv->beacon_update);
883}
884
b481de9c
ZY		 885/* Handle notification from uCode that card's power state is changing
886 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 887static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 888 struct iwl_rx_mem_buffer *rxb)
b481de9c 889{
2f301227 890 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY		 891 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
892 unsigned long status = priv->status;
893
3a41bbd5 894 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
b481de9c 895 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
3a41bbd5
WYG		 896 (flags & SW_CARD_DISABLED) ? "Kill" : "On",
897 (flags & CT_CARD_DISABLED) ?
898 "Reached" : "Not reached");
b481de9c
ZY		 899
900 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
3a41bbd5 901 CT_CARD_DISABLED)) {
b481de9c 902
3395f6e9 903 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY		 904 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
905
a8b50a0a
MA		 906 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
907 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY		 908
909 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 910 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 911 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 912 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 913 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 914 }
3a41bbd5 915 if (flags & CT_CARD_DISABLED)
39b73fb1 916 iwl_tt_enter_ct_kill(priv);
b481de9c 917 }
3a41bbd5 918 if (!(flags & CT_CARD_DISABLED))
39b73fb1 919 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY		 920
921 if (flags & HW_CARD_DISABLED)
922 set_bit(STATUS_RF_KILL_HW, &priv->status);
923 else
924 clear_bit(STATUS_RF_KILL_HW, &priv->status);
925
926
b481de9c 927 if (!(flags & RXON_CARD_DISABLED))
2a421b91 928 iwl_scan_cancel(priv);
b481de9c
ZY		 929
930 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB		 931 test_bit(STATUS_RF_KILL_HW, &priv->status)))
932 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
933 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY		 934 else
935 wake_up_interruptible(&priv->wait_command_queue);
936}
937
5b9f8cd3 938int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 939{
e2e3c57b 940 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 941 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW		 942 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
943 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
944 ~APMG_PS_CTRL_MSK_PWR_SRC);
945 } else {
946 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
947 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
948 ~APMG_PS_CTRL_MSK_PWR_SRC);
949 }
950
a8b50a0a 951 return 0;
e2e3c57b
TW		 952}
953
65550636
WYG		 954static void iwl_bg_tx_flush(struct work_struct *work)
955{
956 struct iwl_priv *priv =
957 container_of(work, struct iwl_priv, tx_flush);
958
959 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
960 return;
961
962 /* do nothing if rf-kill is on */
963 if (!iwl_is_ready_rf(priv))
964 return;
965
966 if (priv->cfg->ops->lib->txfifo_flush) {
967 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
968 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
969 }
970}
971
b481de9c 972/**
5b9f8cd3 973 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY		 974 *
975 * Setup the RX handlers for each of the reply types sent from the uCode
976 * to the host.
977 *
978 * This function chains into the hardware specific files for them to setup
979 * any hardware specific handlers as well.
980 */
653fa4a0 981static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 982{
885ba202 983 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG		 984 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
985 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
81963d68
RC		 986 priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
987 iwl_rx_spectrum_measure_notif;
5b9f8cd3 988 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 989 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG		 990 iwl_rx_pm_debug_statistics_notif;
991 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 992
9fbab516
BC		 993 /*
994 * The same handler is used for both the REPLY to a discrete
995 * statistics request from the host as well as for the periodic
996 * statistics notifications (after received beacons) from the uCode.
b481de9c 997 */
ef8d5529 998 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
8f91aecb 999 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91
TW		 1000
1001 iwl_setup_rx_scan_handlers(priv);
1002
37a44211 1003 /* status change handler */
5b9f8cd3 1004 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 1005
c1354754
TW		 1006 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
1007 iwl_rx_missed_beacon_notif;
37a44211 1008 /* Rx handlers */
8d801080
WYG		 1009 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
1010 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
653fa4a0 1011 /* block ack */
74bcdb33 1012 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
9fbab516 1013 /* Set up hardware specific Rx handlers */
d4789efe 1014 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY		 1015}
1016
b481de9c 1017/**
a55360e4 1018 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY		 1019 *
1020 * Uses the priv->rx_handlers callback function array to invoke
1021 * the appropriate handlers, including command responses,
1022 * frame-received notifications, and other notifications.
1023 */
a55360e4 1024void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 1025{
a55360e4 1026 struct iwl_rx_mem_buffer *rxb;
db11d634 1027 struct iwl_rx_packet *pkt;
a55360e4 1028 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 1029 u32 r, i;
1030 int reclaim;
1031 unsigned long flags;
5c0eef96 1032 u8 fill_rx = 0;
d68ab680 1033 u32 count = 8;
4752c93c 1034 int total_empty;
b481de9c 1035
6440adb5
CB		 1036 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1037 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 1038 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY		 1039 i = rxq->read;
1040
1041 /* Rx interrupt, but nothing sent from uCode */
1042 if (i == r)
e1623446 1043 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 1044
4752c93c 1045 /* calculate total frames need to be restock after handling RX */
7300515d 1046 total_empty = r - rxq->write_actual;
4752c93c
MA		 1047 if (total_empty < 0)
1048 total_empty += RX_QUEUE_SIZE;
1049
1050 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA		 1051 fill_rx = 1;
1052
b481de9c 1053 while (i != r) {
f4989d9b
JB		 1054 int len;
1055
b481de9c
ZY		 1056 rxb = rxq->queue[i];
1057
9fbab516 1058 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY		 1059 * then a bug has been introduced in the queue refilling
1060 * routines -- catch it here */
1061 BUG_ON(rxb == NULL);
1062
1063 rxq->queue[i] = NULL;
1064
2f301227
ZY		 1065 pci_unmap_page(priv->pci_dev, rxb->page_dma,
1066 PAGE_SIZE << priv->hw_params.rx_page_order,
1067 PCI_DMA_FROMDEVICE);
1068 pkt = rxb_addr(rxb);
b481de9c 1069
f4989d9b
JB		 1070 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
1071 len += sizeof(u32); /* account for status word */
1072 trace_iwlwifi_dev_rx(priv, pkt, len);
be1a71a1 1073
b481de9c
ZY		 1074 /* Reclaim a command buffer only if this packet is a response
1075 * to a (driver-originated) command.
1076 * If the packet (e.g. Rx frame) originated from uCode,
1077 * there is no command buffer to reclaim.
1078 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1079 * but apparently a few don't get set; catch them here. */
1080 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1081 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 1082 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 1083 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 1084 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY		 1085 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
1086 (pkt->hdr.cmd != REPLY_TX);
1087
1088 /* Based on type of command response or notification,
1089 * handle those that need handling via function in
5b9f8cd3 1090 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 1091 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 1092 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 1093 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 1094 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 1095 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY		 1096 } else {
1097 /* No handling needed */
e1623446 1098 IWL_DEBUG_RX(priv,
b481de9c
ZY		 1099 "r %d i %d No handler needed for %s, 0x%02x\n",
1100 r, i, get_cmd_string(pkt->hdr.cmd),
1101 pkt->hdr.cmd);
1102 }
1103
29b1b268
ZY		 1104 /*
1105 * XXX: After here, we should always check rxb->page
1106 * against NULL before touching it or its virtual
1107 * memory (pkt). Because some rx_handler might have
1108 * already taken or freed the pages.
1109 */
1110
b481de9c 1111 if (reclaim) {
2f301227
ZY		 1112 /* Invoke any callbacks, transfer the buffer to caller,
1113 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 1114 * as we reclaim the driver command queue */
29b1b268 1115 if (rxb->page)
17b88929 1116 iwl_tx_cmd_complete(priv, rxb);
b481de9c 1117 else
39aadf8c 1118 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY		 1119 }
1120
7300515d
ZY		 1121 /* Reuse the page if possible. For notification packets and
1122 * SKBs that fail to Rx correctly, add them back into the
1123 * rx_free list for reuse later. */
1124 spin_lock_irqsave(&rxq->lock, flags);
2f301227 1125 if (rxb->page != NULL) {
7300515d
ZY		 1126 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
1127 0, PAGE_SIZE << priv->hw_params.rx_page_order,
1128 PCI_DMA_FROMDEVICE);
1129 list_add_tail(&rxb->list, &rxq->rx_free);
1130 rxq->free_count++;
1131 } else
1132 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 1133
b481de9c 1134 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 1135
b481de9c 1136 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA		 1137 /* If there are a lot of unused frames,
1138 * restock the Rx queue so ucode wont assert. */
1139 if (fill_rx) {
1140 count++;
1141 if (count >= 8) {
7300515d 1142 rxq->read = i;
54b81550 1143 iwlagn_rx_replenish_now(priv);
5c0eef96
MA		 1144 count = 0;
1145 }
1146 }
b481de9c
ZY		 1147 }
1148
1149 /* Backtrack one entry */
7300515d 1150 rxq->read = i;
4752c93c 1151 if (fill_rx)
54b81550 1152 iwlagn_rx_replenish_now(priv);
4752c93c 1153 else
54b81550 1154 iwlagn_rx_queue_restock(priv);
a55360e4 1155}
a55360e4 1156
0359facc
MA		 1157/* call this function to flush any scheduled tasklet */
1158static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1159{
a96a27f9 1160 /* wait to make sure we flush pending tasklet*/
0359facc
MA		 1161 synchronize_irq(priv->pci_dev->irq);
1162 tasklet_kill(&priv->irq_tasklet);
1163}
1164
ef850d7c 1165static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY		 1166{
1167 u32 inta, handled = 0;
1168 u32 inta_fh;
1169 unsigned long flags;
c2e61da2 1170 u32 i;
0a6857e7 1171#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY		 1172 u32 inta_mask;
1173#endif
1174
1175 spin_lock_irqsave(&priv->lock, flags);
1176
1177 /* Ack/clear/reset pending uCode interrupts.
1178 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1179 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW		 1180 inta = iwl_read32(priv, CSR_INT);
1181 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY		 1182
1183 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1184 * Any new interrupts that happen after this, either while we're
1185 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW		 1186 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1187 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 1188
0a6857e7 1189#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1190 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 1191 /* just for debug */
3395f6e9 1192 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 1193 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY		 1194 inta, inta_mask, inta_fh);
1195 }
1196#endif
1197
2f301227
ZY		 1198 spin_unlock_irqrestore(&priv->lock, flags);
1199
b481de9c
ZY		 1200 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1201 * atomic, make sure that inta covers all the interrupts that
1202 * we've discovered, even if FH interrupt came in just after
1203 * reading CSR_INT. */
6f83eaa1 1204 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 1205 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 1206 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY		 1207 inta |= CSR_INT_BIT_FH_TX;
1208
1209 /* Now service all interrupt bits discovered above. */
1210 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1211 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY		 1212
1213 /* Tell the device to stop sending interrupts */
5b9f8cd3 1214 iwl_disable_interrupts(priv);
b481de9c 1215
a83b9141 1216 priv->isr_stats.hw++;
5b9f8cd3 1217 iwl_irq_handle_error(priv);
b481de9c
ZY		 1218
1219 handled |= CSR_INT_BIT_HW_ERR;
1220
b481de9c
ZY		 1221 return;
1222 }
1223
0a6857e7 1224#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1225 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 1226 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 1227 if (inta & CSR_INT_BIT_SCD) {
e1623446 1228 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 1229 "the frame/frames.\n");
a83b9141
WYG		 1230 priv->isr_stats.sch++;
1231 }
b481de9c
ZY		 1232
1233 /* Alive notification via Rx interrupt will do the real work */
a83b9141 1234 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 1235 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG		 1236 priv->isr_stats.alive++;
1237 }
b481de9c
ZY		 1238 }
1239#endif
1240 /* Safely ignore these bits for debug checks below */
25c03d8e 1241 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 1242
9fbab516 1243 /* HW RF KILL switch toggled */
b481de9c
ZY		 1244 if (inta & CSR_INT_BIT_RF_KILL) {
1245 int hw_rf_kill = 0;
3395f6e9 1246 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY		 1247 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1248 hw_rf_kill = 1;
1249
4c423a2b 1250 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 1251 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 1252
a83b9141
WYG		 1253 priv->isr_stats.rfkill++;
1254
a9efa652 1255 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS		 1256 * the driver allows loading the ucode even if the radio
1257 * is killed. Hence update the killswitch state here. The
1258 * rfkill handler will care about restarting if needed.
a9efa652 1259 */
6cd0b1cb
HS		 1260 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1261 if (hw_rf_kill)
1262 set_bit(STATUS_RF_KILL_HW, &priv->status);
1263 else
1264 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1265 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 1266 }
b481de9c
ZY		 1267
1268 handled |= CSR_INT_BIT_RF_KILL;
1269 }
1270
9fbab516 1271 /* Chip got too hot and stopped itself */
b481de9c 1272 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1273 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1274 priv->isr_stats.ctkill++;
b481de9c
ZY		 1275 handled |= CSR_INT_BIT_CT_KILL;
1276 }
1277
1278 /* Error detected by uCode */
1279 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT		 1280 IWL_ERR(priv, "Microcode SW error detected. "
1281 " Restarting 0x%X.\n", inta);
a83b9141 1282 priv->isr_stats.sw++;
5b9f8cd3 1283 iwl_irq_handle_error(priv);
b481de9c
ZY		 1284 handled |= CSR_INT_BIT_SW_ERR;
1285 }
1286
c2e61da2
BC		 1287 /*
1288 * uCode wakes up after power-down sleep.
1289 * Tell device about any new tx or host commands enqueued,
1290 * and about any Rx buffers made available while asleep.
1291 */
b481de9c 1292 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1293 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1294 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC		 1295 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1296 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1297 priv->isr_stats.wakeup++;
b481de9c
ZY		 1298 handled |= CSR_INT_BIT_WAKEUP;
1299 }
1300
1301 /* All uCode command responses, including Tx command responses,
1302 * Rx "responses" (frame-received notification), and other
1303 * notifications from uCode come through here*/
1304 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1305 iwl_rx_handle(priv);
a83b9141 1306 priv->isr_stats.rx++;
b481de9c
ZY		 1307 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1308 }
1309
c72cd19f 1310 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1311 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1312 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1313 priv->isr_stats.tx++;
b481de9c 1314 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1315 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR		 1316 priv->ucode_write_complete = 1;
1317 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY		 1318 }
1319
a83b9141 1320 if (inta & ~handled) {
15b1687c 1321 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG		 1322 priv->isr_stats.unhandled++;
1323 }
b481de9c 1324
40cefda9 1325 if (inta & ~(priv->inta_mask)) {
39aadf8c 1326 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1327 inta & ~priv->inta_mask);
39aadf8c 1328 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY		 1329 }
1330
1331 /* Re-enable all interrupts */
0359facc
MA		 1332 /* only Re-enable if diabled by irq */
1333 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1334 iwl_enable_interrupts(priv);
b481de9c 1335
0a6857e7 1336#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1337 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW		 1338 inta = iwl_read32(priv, CSR_INT);
1339 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1340 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1341 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY		 1342 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1343 }
1344#endif
b481de9c
ZY		 1345}
1346
ef850d7c
MA		 1347/* tasklet for iwlagn interrupt */
1348static void iwl_irq_tasklet(struct iwl_priv *priv)
1349{
1350 u32 inta = 0;
1351 u32 handled = 0;
1352 unsigned long flags;
8756990f 1353 u32 i;
ef850d7c
MA		 1354#ifdef CONFIG_IWLWIFI_DEBUG
1355 u32 inta_mask;
1356#endif
1357
1358 spin_lock_irqsave(&priv->lock, flags);
1359
1360 /* Ack/clear/reset pending uCode interrupts.
1361 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1362 */
48a6be6a
SZ		 1363 /* There is a hardware bug in the interrupt mask function that some
1364 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1365 * they are disabled in the CSR_INT_MASK register. Furthermore the
1366 * ICT interrupt handling mechanism has another bug that might cause
1367 * these unmasked interrupts fail to be detected. We workaround the
1368 * hardware bugs here by ACKing all the possible interrupts so that
1369 * interrupt coalescing can still be achieved.
1370 */
4a35ecf8 1371 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
ef850d7c 1372
a4c8b2a6 1373 inta = priv->_agn.inta;
ef850d7c
MA		 1374
1375#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1376 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA		 1377 /* just for debug */
1378 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1379 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1380 inta, inta_mask);
1381 }
1382#endif
2f301227
ZY		 1383
1384 spin_unlock_irqrestore(&priv->lock, flags);
1385
a4c8b2a6
JB		 1386 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1387 priv->_agn.inta = 0;
ef850d7c
MA		 1388
1389 /* Now service all interrupt bits discovered above. */
1390 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1391 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA		 1392
1393 /* Tell the device to stop sending interrupts */
1394 iwl_disable_interrupts(priv);
1395
1396 priv->isr_stats.hw++;
1397 iwl_irq_handle_error(priv);
1398
1399 handled |= CSR_INT_BIT_HW_ERR;
1400
ef850d7c
MA		 1401 return;
1402 }
1403
1404#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1405 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA		 1406 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1407 if (inta & CSR_INT_BIT_SCD) {
1408 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1409 "the frame/frames.\n");
1410 priv->isr_stats.sch++;
1411 }
1412
1413 /* Alive notification via Rx interrupt will do the real work */
1414 if (inta & CSR_INT_BIT_ALIVE) {
1415 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1416 priv->isr_stats.alive++;
1417 }
1418 }
1419#endif
1420 /* Safely ignore these bits for debug checks below */
1421 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1422
1423 /* HW RF KILL switch toggled */
1424 if (inta & CSR_INT_BIT_RF_KILL) {
1425 int hw_rf_kill = 0;
1426 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1427 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1428 hw_rf_kill = 1;
1429
4c423a2b 1430 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA		 1431 hw_rf_kill ? "disable radio" : "enable radio");
1432
1433 priv->isr_stats.rfkill++;
1434
1435 /* driver only loads ucode once setting the interface up.
1436 * the driver allows loading the ucode even if the radio
1437 * is killed. Hence update the killswitch state here. The
1438 * rfkill handler will care about restarting if needed.
1439 */
1440 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1441 if (hw_rf_kill)
1442 set_bit(STATUS_RF_KILL_HW, &priv->status);
1443 else
1444 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1445 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA		 1446 }
1447
1448 handled |= CSR_INT_BIT_RF_KILL;
1449 }
1450
1451 /* Chip got too hot and stopped itself */
1452 if (inta & CSR_INT_BIT_CT_KILL) {
1453 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1454 priv->isr_stats.ctkill++;
1455 handled |= CSR_INT_BIT_CT_KILL;
1456 }
1457
1458 /* Error detected by uCode */
1459 if (inta & CSR_INT_BIT_SW_ERR) {
1460 IWL_ERR(priv, "Microcode SW error detected. "
1461 " Restarting 0x%X.\n", inta);
1462 priv->isr_stats.sw++;
ef850d7c
MA		 1463 iwl_irq_handle_error(priv);
1464 handled |= CSR_INT_BIT_SW_ERR;
1465 }
1466
1467 /* uCode wakes up after power-down sleep */
1468 if (inta & CSR_INT_BIT_WAKEUP) {
1469 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1470 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
8756990f
BC		 1471 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1472 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
ef850d7c
MA		 1473
1474 priv->isr_stats.wakeup++;
1475
1476 handled |= CSR_INT_BIT_WAKEUP;
1477 }
1478
1479 /* All uCode command responses, including Tx command responses,
1480 * Rx "responses" (frame-received notification), and other
1481 * notifications from uCode come through here*/
40cefda9
MA		 1482 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1483 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1484 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA		 1485 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1486 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1487 iwl_write32(priv, CSR_FH_INT_STATUS,
1488 CSR49_FH_INT_RX_MASK);
1489 }
1490 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1491 handled |= CSR_INT_BIT_RX_PERIODIC;
1492 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1493 }
1494 /* Sending RX interrupt require many steps to be done in the
1495 * the device:
1496 * 1- write interrupt to current index in ICT table.
1497 * 2- dma RX frame.
1498 * 3- update RX shared data to indicate last write index.
1499 * 4- send interrupt.
1500 * This could lead to RX race, driver could receive RX interrupt
74ba67ed
BC		 1501 * but the shared data changes does not reflect this;
1502 * periodic interrupt will detect any dangling Rx activity.
40cefda9 1503 */
74ba67ed
BC		 1504
1505 /* Disable periodic interrupt; we use it as just a one-shot. */
1506 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9 1507 CSR_INT_PERIODIC_DIS);
ef850d7c 1508 iwl_rx_handle(priv);
74ba67ed
BC		 1509
1510 /*
1511 * Enable periodic interrupt in 8 msec only if we received
1512 * real RX interrupt (instead of just periodic int), to catch
1513 * any dangling Rx interrupt. If it was just the periodic
1514 * interrupt, there was no dangling Rx activity, and no need
1515 * to extend the periodic interrupt; one-shot is enough.
1516 */
40cefda9 1517 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
74ba67ed 1518 iwl_write8(priv, CSR_INT_PERIODIC_REG,
40cefda9
MA		 1519 CSR_INT_PERIODIC_ENA);
1520
ef850d7c 1521 priv->isr_stats.rx++;
ef850d7c
MA		 1522 }
1523
c72cd19f 1524 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA		 1525 if (inta & CSR_INT_BIT_FH_TX) {
1526 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1527 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA		 1528 priv->isr_stats.tx++;
1529 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1530 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA		 1531 priv->ucode_write_complete = 1;
1532 wake_up_interruptible(&priv->wait_command_queue);
1533 }
1534
1535 if (inta & ~handled) {
1536 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1537 priv->isr_stats.unhandled++;
1538 }
1539
40cefda9 1540 if (inta & ~(priv->inta_mask)) {
ef850d7c 1541 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1542 inta & ~priv->inta_mask);
ef850d7c
MA		 1543 }
1544
ef850d7c
MA		 1545 /* Re-enable all interrupts */
1546 /* only Re-enable if diabled by irq */
1547 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1548 iwl_enable_interrupts(priv);
ef850d7c
MA		 1549}
1550
872c8ddc
WYG		 1551/* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
1552#define ACK_CNT_RATIO (50)
1553#define BA_TIMEOUT_CNT (5)
1554#define BA_TIMEOUT_MAX (16)
1555
1556/**
1557 * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
1558 *
1559 * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
1560 * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
1561 * operation state.
1562 */
1563bool iwl_good_ack_health(struct iwl_priv *priv,
1564 struct iwl_rx_packet *pkt)
1565{
1566 bool rc = true;
1567 int actual_ack_cnt_delta, expected_ack_cnt_delta;
1568 int ba_timeout_delta;
1569
1570 actual_ack_cnt_delta =
1571 le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
f3aebeee 1572 le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt);
872c8ddc
WYG		 1573 expected_ack_cnt_delta =
1574 le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
f3aebeee 1575 le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt);
872c8ddc
WYG		 1576 ba_timeout_delta =
1577 le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
f3aebeee 1578 le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout);
872c8ddc
WYG		 1579 if ((priv->_agn.agg_tids_count > 0) &&
1580 (expected_ack_cnt_delta > 0) &&
1581 (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
1582 < ACK_CNT_RATIO) &&
1583 (ba_timeout_delta > BA_TIMEOUT_CNT)) {
1584 IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
1585 " expected_ack_cnt = %d\n",
1586 actual_ack_cnt_delta, expected_ack_cnt_delta);
1587
d73e4923
JB		 1588#ifdef CONFIG_IWLWIFI_DEBUGFS
1589 /*
1590 * This is ifdef'ed on DEBUGFS because otherwise the
1591 * statistics aren't available. If DEBUGFS is set but
1592 * DEBUG is not, these will just compile out.
1593 */
872c8ddc 1594 IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
f3aebeee 1595 priv->_agn.delta_statistics.tx.rx_detected_cnt);
872c8ddc
WYG		 1596 IWL_DEBUG_RADIO(priv,
1597 "ack_or_ba_timeout_collision delta = %d\n",
f3aebeee 1598 priv->_agn.delta_statistics.tx.
872c8ddc
WYG		 1599 ack_or_ba_timeout_collision);
1600#endif
1601 IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
1602 ba_timeout_delta);
1603 if (!actual_ack_cnt_delta &&
1604 (ba_timeout_delta >= BA_TIMEOUT_MAX))
1605 rc = false;
1606 }
1607 return rc;
1608}
1609
a83b9141 1610
7d47618a
EG		 1611/*****************************************************************************
1612 *
1613 * sysfs attributes
1614 *
1615 *****************************************************************************/
1616
1617#ifdef CONFIG_IWLWIFI_DEBUG
1618
1619/*
1620 * The following adds a new attribute to the sysfs representation
1621 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1622 * used for controlling the debug level.
1623 *
1624 * See the level definitions in iwl for details.
1625 *
1626 * The debug_level being managed using sysfs below is a per device debug
1627 * level that is used instead of the global debug level if it (the per
1628 * device debug level) is set.
1629 */
1630static ssize_t show_debug_level(struct device *d,
1631 struct device_attribute *attr, char *buf)
1632{
1633 struct iwl_priv *priv = dev_get_drvdata(d);
1634 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1635}
1636static ssize_t store_debug_level(struct device *d,
1637 struct device_attribute *attr,
1638 const char *buf, size_t count)
1639{
1640 struct iwl_priv *priv = dev_get_drvdata(d);
1641 unsigned long val;
1642 int ret;
1643
1644 ret = strict_strtoul(buf, 0, &val);
1645 if (ret)
1646 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1647 else {
1648 priv->debug_level = val;
1649 if (iwl_alloc_traffic_mem(priv))
1650 IWL_ERR(priv,
1651 "Not enough memory to generate traffic log\n");
1652 }
1653 return strnlen(buf, count);
1654}
1655
1656static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1657 show_debug_level, store_debug_level);
1658
1659
1660#endif /* CONFIG_IWLWIFI_DEBUG */
1661
1662
1663static ssize_t show_temperature(struct device *d,
1664 struct device_attribute *attr, char *buf)
1665{
1666 struct iwl_priv *priv = dev_get_drvdata(d);
1667
1668 if (!iwl_is_alive(priv))
1669 return -EAGAIN;
1670
1671 return sprintf(buf, "%d\n", priv->temperature);
1672}
1673
1674static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1675
1676static ssize_t show_tx_power(struct device *d,
1677 struct device_attribute *attr, char *buf)
1678{
1679 struct iwl_priv *priv = dev_get_drvdata(d);
1680
1681 if (!iwl_is_ready_rf(priv))
1682 return sprintf(buf, "off\n");
1683 else
1684 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1685}
1686
1687static ssize_t store_tx_power(struct device *d,
1688 struct device_attribute *attr,
1689 const char *buf, size_t count)
1690{
1691 struct iwl_priv *priv = dev_get_drvdata(d);
1692 unsigned long val;
1693 int ret;
1694
1695 ret = strict_strtoul(buf, 10, &val);
1696 if (ret)
1697 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1698 else {
1699 ret = iwl_set_tx_power(priv, val, false);
1700 if (ret)
1701 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1702 ret);
1703 else
1704 ret = count;
1705 }
1706 return ret;
1707}
1708
1709static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1710
7d47618a
EG		 1711static struct attribute *iwl_sysfs_entries[] = {
1712 &dev_attr_temperature.attr,
1713 &dev_attr_tx_power.attr,
7d47618a
EG		 1714#ifdef CONFIG_IWLWIFI_DEBUG
1715 &dev_attr_debug_level.attr,
1716#endif
1717 NULL
1718};
1719
1720static struct attribute_group iwl_attribute_group = {
1721 .name = NULL, /* put in device directory */
1722 .attrs = iwl_sysfs_entries,
1723};
1724
b481de9c
ZY		 1725/******************************************************************************
1726 *
1727 * uCode download functions
1728 *
1729 ******************************************************************************/
1730
5b9f8cd3 1731static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1732{
98c92211
TW		 1733 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1734 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1735 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1736 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1737 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1738 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY		 1739}
1740
5b9f8cd3 1741static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR		 1742{
1743 /* Remove all resets to allow NIC to operate */
1744 iwl_write32(priv, CSR_RESET, 0);
1745}
1746
dd7a2509
JB		 1747struct iwlagn_ucode_capabilities {
1748 u32 max_probe_length;
6a822d06 1749 u32 standard_phy_calibration_size;
ece9c4ee 1750 bool pan;
dd7a2509 1751};
edcdf8b2 1752
b08dfd04 1753static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
dd7a2509
JB		 1754static int iwl_mac_setup_register(struct iwl_priv *priv,
1755 struct iwlagn_ucode_capabilities *capa);
b08dfd04 1756
39396085
JS		 1757#define UCODE_EXPERIMENTAL_INDEX 100
1758#define UCODE_EXPERIMENTAL_TAG "exp"
1759
b08dfd04
JB		 1760static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1761{
1762 const char *name_pre = priv->cfg->fw_name_pre;
39396085 1763 char tag[8];
b08dfd04 1764
39396085
JS		 1765 if (first) {
1766#ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1767 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1768 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1769 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1770#endif
b08dfd04 1771 priv->fw_index = priv->cfg->ucode_api_max;
39396085
JS		 1772 sprintf(tag, "%d", priv->fw_index);
1773 } else {
b08dfd04 1774 priv->fw_index--;
39396085
JS		 1775 sprintf(tag, "%d", priv->fw_index);
1776 }
b08dfd04
JB		 1777
1778 if (priv->fw_index < priv->cfg->ucode_api_min) {
1779 IWL_ERR(priv, "no suitable firmware found!\n");
1780 return -ENOENT;
1781 }
1782
39396085 1783 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
b08dfd04 1784
39396085
JS		 1785 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1786 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1787 ? "EXPERIMENTAL " : "",
b08dfd04
JB		 1788 priv->firmware_name);
1789
1790 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1791 &priv->pci_dev->dev, GFP_KERNEL, priv,
1792 iwl_ucode_callback);
1793}
1794
0e9a44dc
JB		 1795struct iwlagn_firmware_pieces {
1796 const void *inst, *data, *init, *init_data, *boot;
1797 size_t inst_size, data_size, init_size, init_data_size, boot_size;
1798
1799 u32 build;
b2e640d4
JB		 1800
1801 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1802 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
0e9a44dc
JB		 1803};
1804
1805static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1806 const struct firmware *ucode_raw,
1807 struct iwlagn_firmware_pieces *pieces)
1808{
1809 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1810 u32 api_ver, hdr_size;
1811 const u8 *src;
1812
1813 priv->ucode_ver = le32_to_cpu(ucode->ver);
1814 api_ver = IWL_UCODE_API(priv->ucode_ver);
1815
1816 switch (api_ver) {
1817 default:
1818 /*
1819 * 4965 doesn't revision the firmware file format
1820 * along with the API version, it always uses v1
1821 * file format.
1822 */
1823 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1824 CSR_HW_REV_TYPE_4965) {
1825 hdr_size = 28;
1826 if (ucode_raw->size < hdr_size) {
1827 IWL_ERR(priv, "File size too small!\n");
1828 return -EINVAL;
1829 }
1830 pieces->build = le32_to_cpu(ucode->u.v2.build);
1831 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1832 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1833 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1834 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1835 pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1836 src = ucode->u.v2.data;
1837 break;
1838 }
1839 /* fall through for 4965 */
1840 case 0:
1841 case 1:
1842 case 2:
1843 hdr_size = 24;
1844 if (ucode_raw->size < hdr_size) {
1845 IWL_ERR(priv, "File size too small!\n");
1846 return -EINVAL;
1847 }
1848 pieces->build = 0;
1849 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1850 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1851 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1852 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1853 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1854 src = ucode->u.v1.data;
1855 break;
1856 }
1857
1858 /* Verify size of file vs. image size info in file's header */
1859 if (ucode_raw->size != hdr_size + pieces->inst_size +
1860 pieces->data_size + pieces->init_size +
1861 pieces->init_data_size + pieces->boot_size) {
1862
1863 IWL_ERR(priv,
1864 "uCode file size %d does not match expected size\n",
1865 (int)ucode_raw->size);
1866 return -EINVAL;
1867 }
1868
1869 pieces->inst = src;
1870 src += pieces->inst_size;
1871 pieces->data = src;
1872 src += pieces->data_size;
1873 pieces->init = src;
1874 src += pieces->init_size;
1875 pieces->init_data = src;
1876 src += pieces->init_data_size;
1877 pieces->boot = src;
1878 src += pieces->boot_size;
1879
1880 return 0;
1881}
1882
dd7a2509
JB		 1883static int iwlagn_wanted_ucode_alternative = 1;
1884
1885static int iwlagn_load_firmware(struct iwl_priv *priv,
1886 const struct firmware *ucode_raw,
1887 struct iwlagn_firmware_pieces *pieces,
1888 struct iwlagn_ucode_capabilities *capa)
1889{
1890 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1891 struct iwl_ucode_tlv *tlv;
1892 size_t len = ucode_raw->size;
1893 const u8 *data;
1894 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1895 u64 alternatives;
ad8d8333
WYG		 1896 u32 tlv_len;
1897 enum iwl_ucode_tlv_type tlv_type;
1898 const u8 *tlv_data;
dd7a2509 1899
ad8d8333
WYG		 1900 if (len < sizeof(*ucode)) {
1901 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
dd7a2509 1902 return -EINVAL;
ad8d8333 1903 }
dd7a2509 1904
ad8d8333
WYG		 1905 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1906 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1907 le32_to_cpu(ucode->magic));
dd7a2509 1908 return -EINVAL;
ad8d8333 1909 }
dd7a2509
JB		 1910
1911 /*
1912 * Check which alternatives are present, and "downgrade"
1913 * when the chosen alternative is not present, warning
1914 * the user when that happens. Some files may not have
1915 * any alternatives, so don't warn in that case.
1916 */
1917 alternatives = le64_to_cpu(ucode->alternatives);
1918 tmp = wanted_alternative;
1919 if (wanted_alternative > 63)
1920 wanted_alternative = 63;
1921 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1922 wanted_alternative--;
1923 if (wanted_alternative && wanted_alternative != tmp)
1924 IWL_WARN(priv,
1925 "uCode alternative %d not available, choosing %d\n",
1926 tmp, wanted_alternative);
1927
1928 priv->ucode_ver = le32_to_cpu(ucode->ver);
1929 pieces->build = le32_to_cpu(ucode->build);
1930 data = ucode->data;
1931
1932 len -= sizeof(*ucode);
1933
704da534 1934 while (len >= sizeof(*tlv)) {
dd7a2509 1935 u16 tlv_alt;
dd7a2509
JB		 1936
1937 len -= sizeof(*tlv);
1938 tlv = (void *)data;
1939
1940 tlv_len = le32_to_cpu(tlv->length);
1941 tlv_type = le16_to_cpu(tlv->type);
1942 tlv_alt = le16_to_cpu(tlv->alternative);
1943 tlv_data = tlv->data;
1944
ad8d8333
WYG		 1945 if (len < tlv_len) {
1946 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1947 len, tlv_len);
dd7a2509 1948 return -EINVAL;
ad8d8333 1949 }
dd7a2509
JB		 1950 len -= ALIGN(tlv_len, 4);
1951 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1952
1953 /*
1954 * Alternative 0 is always valid.
1955 *
1956 * Skip alternative TLVs that are not selected.
1957 */
1958 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1959 continue;
1960
1961 switch (tlv_type) {
1962 case IWL_UCODE_TLV_INST:
1963 pieces->inst = tlv_data;
1964 pieces->inst_size = tlv_len;
1965 break;
1966 case IWL_UCODE_TLV_DATA:
1967 pieces->data = tlv_data;
1968 pieces->data_size = tlv_len;
1969 break;
1970 case IWL_UCODE_TLV_INIT:
1971 pieces->init = tlv_data;
1972 pieces->init_size = tlv_len;
1973 break;
1974 case IWL_UCODE_TLV_INIT_DATA:
1975 pieces->init_data = tlv_data;
1976 pieces->init_data_size = tlv_len;
1977 break;
1978 case IWL_UCODE_TLV_BOOT:
1979 pieces->boot = tlv_data;
1980 pieces->boot_size = tlv_len;
1981 break;
1982 case IWL_UCODE_TLV_PROBE_MAX_LEN:
704da534
JB		 1983 if (tlv_len != sizeof(u32))
1984 goto invalid_tlv_len;
1985 capa->max_probe_length =
ad8d8333 1986 le32_to_cpup((__le32 *)tlv_data);
dd7a2509 1987 break;
ece9c4ee
JB		 1988 case IWL_UCODE_TLV_PAN:
1989 if (tlv_len)
1990 goto invalid_tlv_len;
1991 capa->pan = true;
1992 break;
b2e640d4 1993 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
704da534
JB		 1994 if (tlv_len != sizeof(u32))
1995 goto invalid_tlv_len;
1996 pieces->init_evtlog_ptr =
ad8d8333 1997 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 1998 break;
1999 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
704da534
JB		 2000 if (tlv_len != sizeof(u32))
2001 goto invalid_tlv_len;
2002 pieces->init_evtlog_size =
ad8d8333 2003 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2004 break;
2005 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
704da534
JB		 2006 if (tlv_len != sizeof(u32))
2007 goto invalid_tlv_len;
2008 pieces->init_errlog_ptr =
ad8d8333 2009 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2010 break;
2011 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
704da534
JB		 2012 if (tlv_len != sizeof(u32))
2013 goto invalid_tlv_len;
2014 pieces->inst_evtlog_ptr =
ad8d8333 2015 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2016 break;
2017 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
704da534
JB		 2018 if (tlv_len != sizeof(u32))
2019 goto invalid_tlv_len;
2020 pieces->inst_evtlog_size =
ad8d8333 2021 le32_to_cpup((__le32 *)tlv_data);
b2e640d4
JB		 2022 break;
2023 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
704da534
JB		 2024 if (tlv_len != sizeof(u32))
2025 goto invalid_tlv_len;
2026 pieces->inst_errlog_ptr =
ad8d8333 2027 le32_to_cpup((__le32 *)tlv_data);
b2e640d4 2028 break;
c8312fac
WYG		 2029 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
2030 if (tlv_len)
704da534
JB		 2031 goto invalid_tlv_len;
2032 priv->enhance_sensitivity_table = true;
c8312fac 2033 break;
6a822d06 2034 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
704da534
JB		 2035 if (tlv_len != sizeof(u32))
2036 goto invalid_tlv_len;
2037 capa->standard_phy_calibration_size =
6a822d06
WYG		 2038 le32_to_cpup((__le32 *)tlv_data);
2039 break;
dd7a2509 2040 default:
ad8d8333 2041 IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
dd7a2509
JB		 2042 break;
2043 }
2044 }
2045
ad8d8333
WYG		 2046 if (len) {
2047 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
2048 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
704da534 2049 return -EINVAL;
ad8d8333 2050 }
dd7a2509 2051
704da534
JB		 2052 return 0;
2053
2054 invalid_tlv_len:
2055 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
2056 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
2057
2058 return -EINVAL;
dd7a2509
JB		 2059}
2060
b481de9c 2061/**
b08dfd04 2062 * iwl_ucode_callback - callback when firmware was loaded
b481de9c 2063 *
b08dfd04
JB		 2064 * If loaded successfully, copies the firmware into buffers
2065 * for the card to fetch (via DMA).
b481de9c 2066 */
b08dfd04 2067static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
b481de9c 2068{
b08dfd04 2069 struct iwl_priv *priv = context;
cc0f555d 2070 struct iwl_ucode_header *ucode;
0e9a44dc
JB		 2071 int err;
2072 struct iwlagn_firmware_pieces pieces;
a0987a8d
RC		 2073 const unsigned int api_max = priv->cfg->ucode_api_max;
2074 const unsigned int api_min = priv->cfg->ucode_api_min;
0e9a44dc 2075 u32 api_ver;
3e4de761 2076 char buildstr[25];
0e9a44dc 2077 u32 build;
dd7a2509
JB		 2078 struct iwlagn_ucode_capabilities ucode_capa = {
2079 .max_probe_length = 200,
6a822d06
WYG		 2080 .standard_phy_calibration_size =
2081 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE,
dd7a2509 2082 };
0e9a44dc
JB		 2083
2084 memset(&pieces, 0, sizeof(pieces));
b481de9c 2085
b08dfd04 2086 if (!ucode_raw) {
39396085
JS		 2087 if (priv->fw_index <= priv->cfg->ucode_api_max)
2088 IWL_ERR(priv,
2089 "request for firmware file '%s' failed.\n",
2090 priv->firmware_name);
b08dfd04 2091 goto try_again;
b481de9c
ZY		 2092 }
2093
b08dfd04
JB		 2094 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
2095 priv->firmware_name, ucode_raw->size);
b481de9c 2096
22adba2a
JB		 2097 /* Make sure that we got at least the API version number */
2098 if (ucode_raw->size < 4) {
15b1687c 2099 IWL_ERR(priv, "File size way too small!\n");
b08dfd04 2100 goto try_again;
b481de9c
ZY		 2101 }
2102
2103 /* Data from ucode file: header followed by uCode images */
cc0f555d 2104 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 2105
0e9a44dc
JB		 2106 if (ucode->ver)
2107 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
2108 else
dd7a2509
JB		 2109 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
2110 &ucode_capa);
22adba2a 2111
0e9a44dc
JB		 2112 if (err)
2113 goto try_again;
b481de9c 2114
a0987a8d 2115 api_ver = IWL_UCODE_API(priv->ucode_ver);
0e9a44dc 2116 build = pieces.build;
a0987a8d 2117
0e9a44dc
JB		 2118 /*
2119 * api_ver should match the api version forming part of the
2120 * firmware filename ... but we don't check for that and only rely
2121 * on the API version read from firmware header from here on forward
2122 */
a0987a8d 2123 if (api_ver < api_min || api_ver > api_max) {
15b1687c 2124 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC		 2125 "Driver supports v%u, firmware is v%u.\n",
2126 api_max, api_ver);
b08dfd04 2127 goto try_again;
a0987a8d 2128 }
b08dfd04 2129
a0987a8d 2130 if (api_ver != api_max)
978785a3 2131 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC		 2132 "got v%u. New firmware can be obtained "
2133 "from http://www.intellinuxwireless.org.\n",
2134 api_max, api_ver);
2135
3e4de761 2136 if (build)
39396085
JS		 2137 sprintf(buildstr, " build %u%s", build,
2138 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
2139 ? " (EXP)" : "");
3e4de761
JB		 2140 else
2141 buildstr[0] = '\0';
2142
2143 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
2144 IWL_UCODE_MAJOR(priv->ucode_ver),
2145 IWL_UCODE_MINOR(priv->ucode_ver),
2146 IWL_UCODE_API(priv->ucode_ver),
2147 IWL_UCODE_SERIAL(priv->ucode_ver),
2148 buildstr);
a0987a8d 2149
5ebeb5a6
RC		 2150 snprintf(priv->hw->wiphy->fw_version,
2151 sizeof(priv->hw->wiphy->fw_version),
3e4de761 2152 "%u.%u.%u.%u%s",
5ebeb5a6
RC		 2153 IWL_UCODE_MAJOR(priv->ucode_ver),
2154 IWL_UCODE_MINOR(priv->ucode_ver),
2155 IWL_UCODE_API(priv->ucode_ver),
3e4de761
JB		 2156 IWL_UCODE_SERIAL(priv->ucode_ver),
2157 buildstr);
b481de9c 2158
b08dfd04
JB		 2159 /*
2160 * For any of the failures below (before allocating pci memory)
2161 * we will try to load a version with a smaller API -- maybe the
2162 * user just got a corrupted version of the latest API.
2163 */
2164
0e9a44dc
JB		 2165 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
2166 priv->ucode_ver);
2167 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
2168 pieces.inst_size);
2169 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
2170 pieces.data_size);
2171 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
2172 pieces.init_size);
2173 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
2174 pieces.init_data_size);
2175 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
2176 pieces.boot_size);
b481de9c
ZY		 2177
2178 /* Verify that uCode images will fit in card's SRAM */
0e9a44dc
JB		 2179 if (pieces.inst_size > priv->hw_params.max_inst_size) {
2180 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
2181 pieces.inst_size);
b08dfd04 2182 goto try_again;
b481de9c
ZY		 2183 }
2184
0e9a44dc
JB		 2185 if (pieces.data_size > priv->hw_params.max_data_size) {
2186 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
2187 pieces.data_size);
b08dfd04 2188 goto try_again;
b481de9c 2189 }
0e9a44dc
JB		 2190
2191 if (pieces.init_size > priv->hw_params.max_inst_size) {
2192 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2193 pieces.init_size);
b08dfd04 2194 goto try_again;
b481de9c 2195 }
0e9a44dc
JB		 2196
2197 if (pieces.init_data_size > priv->hw_params.max_data_size) {
2198 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2199 pieces.init_data_size);
b08dfd04 2200 goto try_again;
b481de9c 2201 }
0e9a44dc
JB		 2202
2203 if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2204 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2205 pieces.boot_size);
b08dfd04 2206 goto try_again;
b481de9c
ZY		 2207 }
2208
2209 /* Allocate ucode buffers for card's bus-master loading ... */
2210
2211 /* Runtime instructions and 2 copies of data:
2212 * 1) unmodified from disk
2213 * 2) backup cache for save/restore during power-downs */
0e9a44dc 2214 priv->ucode_code.len = pieces.inst_size;
98c92211 2215 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c 2216
0e9a44dc 2217 priv->ucode_data.len = pieces.data_size;
98c92211 2218 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c 2219
0e9a44dc 2220 priv->ucode_data_backup.len = pieces.data_size;
98c92211 2221 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 2222
1f304e4e
ZY		 2223 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2224 !priv->ucode_data_backup.v_addr)
2225 goto err_pci_alloc;
2226
b481de9c 2227 /* Initialization instructions and data */
0e9a44dc
JB		 2228 if (pieces.init_size && pieces.init_data_size) {
2229 priv->ucode_init.len = pieces.init_size;
98c92211 2230 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1 2231
0e9a44dc 2232 priv->ucode_init_data.len = pieces.init_data_size;
98c92211 2233 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW		 2234
2235 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2236 goto err_pci_alloc;
2237 }
b481de9c
ZY		 2238
2239 /* Bootstrap (instructions only, no data) */
0e9a44dc
JB		 2240 if (pieces.boot_size) {
2241 priv->ucode_boot.len = pieces.boot_size;
98c92211 2242 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 2243
90e759d1
TW		 2244 if (!priv->ucode_boot.v_addr)
2245 goto err_pci_alloc;
2246 }
b481de9c 2247
b2e640d4
JB		 2248 /* Now that we can no longer fail, copy information */
2249
2250 /*
2251 * The (size - 16) / 12 formula is based on the information recorded
2252 * for each event, which is of mode 1 (including timestamp) for all
2253 * new microcodes that include this information.
2254 */
2255 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2256 if (pieces.init_evtlog_size)
2257 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2258 else
7cb1b088
WYG		 2259 priv->_agn.init_evtlog_size =
2260 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2261 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2262 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2263 if (pieces.inst_evtlog_size)
2264 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2265 else
7cb1b088
WYG		 2266 priv->_agn.inst_evtlog_size =
2267 priv->cfg->base_params->max_event_log_size;
b2e640d4
JB		 2268 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2269
ece9c4ee
JB		 2270 if (ucode_capa.pan) {
2271 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
c10afb6e 2272 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
ece9c4ee
JB		 2273 } else
2274 priv->sta_key_max_num = STA_KEY_MAX_NUM;
c10afb6e 2275
b481de9c
ZY		 2276 /* Copy images into buffers for card's bus-master reads ... */
2277
2278 /* Runtime instructions (first block of data in file) */
0e9a44dc
JB		 2279 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2280 pieces.inst_size);
2281 memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
cc0f555d 2282
e1623446 2283 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY		 2284 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2285
0e9a44dc
JB		 2286 /*
2287 * Runtime data
2288 * NOTE: Copy into backup buffer will be done in iwl_up()
2289 */
2290 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2291 pieces.data_size);
2292 memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2293 memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2294
2295 /* Initialization instructions */
2296 if (pieces.init_size) {
e1623446 2297 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
0e9a44dc
JB		 2298 pieces.init_size);
2299 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
b481de9c
ZY		 2300 }
2301
0e9a44dc
JB		 2302 /* Initialization data */
2303 if (pieces.init_data_size) {
e1623446 2304 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
0e9a44dc
JB		 2305 pieces.init_data_size);
2306 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2307 pieces.init_data_size);
b481de9c
ZY		 2308 }
2309
0e9a44dc
JB		 2310 /* Bootstrap instructions */
2311 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2312 pieces.boot_size);
2313 memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
b481de9c 2314
6a822d06
WYG		 2315 /*
2316 * figure out the offset of chain noise reset and gain commands
2317 * base on the size of standard phy calibration commands table size
2318 */
2319 if (ucode_capa.standard_phy_calibration_size >
2320 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2321 ucode_capa.standard_phy_calibration_size =
2322 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2323
2324 priv->_agn.phy_calib_chain_noise_reset_cmd =
2325 ucode_capa.standard_phy_calibration_size;
2326 priv->_agn.phy_calib_chain_noise_gain_cmd =
2327 ucode_capa.standard_phy_calibration_size + 1;
2328
b08dfd04
JB		 2329 /**************************************************
2330 * This is still part of probe() in a sense...
2331 *
2332 * 9. Setup and register with mac80211 and debugfs
2333 **************************************************/
dd7a2509 2334 err = iwl_mac_setup_register(priv, &ucode_capa);
b08dfd04
JB		 2335 if (err)
2336 goto out_unbind;
2337
2338 err = iwl_dbgfs_register(priv, DRV_NAME);
2339 if (err)
2340 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2341
7d47618a
EG		 2342 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2343 &iwl_attribute_group);
2344 if (err) {
2345 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2346 goto out_unbind;
2347 }
2348
b481de9c
ZY		 2349 /* We have our copies now, allow OS release its copies */
2350 release_firmware(ucode_raw);
a15707d8 2351 complete(&priv->_agn.firmware_loading_complete);
b08dfd04
JB		 2352 return;
2353
2354 try_again:
2355 /* try next, if any */
2356 if (iwl_request_firmware(priv, false))
2357 goto out_unbind;
2358 release_firmware(ucode_raw);
2359 return;
b481de9c
ZY		 2360
2361 err_pci_alloc:
15b1687c 2362 IWL_ERR(priv, "failed to allocate pci memory\n");
5b9f8cd3 2363 iwl_dealloc_ucode_pci(priv);
b08dfd04 2364 out_unbind:
a15707d8 2365 complete(&priv->_agn.firmware_loading_complete);
b08dfd04 2366 device_release_driver(&priv->pci_dev->dev);
b481de9c 2367 release_firmware(ucode_raw);
b481de9c
ZY		 2368}
2369
b7a79404
RC		 2370static const char *desc_lookup_text[] = {
2371 "OK",
2372 "FAIL",
2373 "BAD_PARAM",
2374 "BAD_CHECKSUM",
2375 "NMI_INTERRUPT_WDG",
2376 "SYSASSERT",
2377 "FATAL_ERROR",
2378 "BAD_COMMAND",
2379 "HW_ERROR_TUNE_LOCK",
2380 "HW_ERROR_TEMPERATURE",
2381 "ILLEGAL_CHAN_FREQ",
2382 "VCC_NOT_STABLE",
2383 "FH_ERROR",
2384 "NMI_INTERRUPT_HOST",
2385 "NMI_INTERRUPT_ACTION_PT",
2386 "NMI_INTERRUPT_UNKNOWN",
2387 "UCODE_VERSION_MISMATCH",
2388 "HW_ERROR_ABS_LOCK",
2389 "HW_ERROR_CAL_LOCK_FAIL",
2390 "NMI_INTERRUPT_INST_ACTION_PT",
2391 "NMI_INTERRUPT_DATA_ACTION_PT",
2392 "NMI_TRM_HW_ER",
2393 "NMI_INTERRUPT_TRM",
2394 "NMI_INTERRUPT_BREAK_POINT"
2395 "DEBUG_0",
2396 "DEBUG_1",
2397 "DEBUG_2",
2398 "DEBUG_3",
b7a79404
RC		 2399};
2400
4b58645c
JS		 2401static struct { char *name; u8 num; } advanced_lookup[] = {
2402 { "NMI_INTERRUPT_WDG", 0x34 },
2403 { "SYSASSERT", 0x35 },
2404 { "UCODE_VERSION_MISMATCH", 0x37 },
2405 { "BAD_COMMAND", 0x38 },
2406 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2407 { "FATAL_ERROR", 0x3D },
2408 { "NMI_TRM_HW_ERR", 0x46 },
2409 { "NMI_INTERRUPT_TRM", 0x4C },
2410 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2411 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2412 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2413 { "NMI_INTERRUPT_HOST", 0x66 },
2414 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2415 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2416 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2417 { "ADVANCED_SYSASSERT", 0 },
2418};
2419
2420static const char *desc_lookup(u32 num)
b7a79404 2421{
4b58645c
JS		 2422 int i;
2423 int max = ARRAY_SIZE(desc_lookup_text);
b7a79404 2424
4b58645c
JS		 2425 if (num < max)
2426 return desc_lookup_text[num];
b7a79404 2427
4b58645c
JS		 2428 max = ARRAY_SIZE(advanced_lookup) - 1;
2429 for (i = 0; i < max; i++) {
2430 if (advanced_lookup[i].num == num)
2431 break;;
2432 }
2433 return advanced_lookup[i].name;
b7a79404
RC		 2434}
2435
2436#define ERROR_START_OFFSET (1 * sizeof(u32))
2437#define ERROR_ELEM_SIZE (7 * sizeof(u32))
2438
2439void iwl_dump_nic_error_log(struct iwl_priv *priv)
2440{
2441 u32 data2, line;
2442 u32 desc, time, count, base, data1;
2443 u32 blink1, blink2, ilink1, ilink2;
461ef382 2444 u32 pc, hcmd;
b7a79404 2445
b2e640d4 2446 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2447 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
b2e640d4
JB		 2448 if (!base)
2449 base = priv->_agn.init_errlog_ptr;
2450 } else {
b7a79404 2451 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
b2e640d4
JB		 2452 if (!base)
2453 base = priv->_agn.inst_errlog_ptr;
2454 }
b7a79404
RC		 2455
2456 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2457 IWL_ERR(priv,
2458 "Not valid error log pointer 0x%08X for %s uCode\n",
2459 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
b7a79404
RC		 2460 return;
2461 }
2462
2463 count = iwl_read_targ_mem(priv, base);
2464
2465 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2466 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2467 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2468 priv->status, count);
2469 }
2470
2471 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
6e6ebf4b 2472 priv->isr_stats.err_code = desc;
461ef382 2473 pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
b7a79404
RC		 2474 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2475 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2476 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2477 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2478 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2479 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2480 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2481 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
461ef382 2482 hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
b7a79404 2483
be1a71a1
JB		 2484 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2485 blink1, blink2, ilink1, ilink2);
2486
87563715 2487 IWL_ERR(priv, "Desc Time "
b7a79404 2488 "data1 data2 line\n");
87563715 2489 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
b7a79404 2490 desc_lookup(desc), desc, time, data1, data2, line);
461ef382
WYG		 2491 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
2492 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2493 pc, blink1, blink2, ilink1, ilink2, hcmd);
b7a79404
RC		 2494}
2495
2496#define EVENT_START_OFFSET (4 * sizeof(u32))
2497
2498/**
2499 * iwl_print_event_log - Dump error event log to syslog
2500 *
2501 */
b03d7d0f
WYG		 2502static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2503 u32 num_events, u32 mode,
2504 int pos, char **buf, size_t bufsz)
b7a79404
RC		 2505{
2506 u32 i;
2507 u32 base; /* SRAM byte address of event log header */
2508 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2509 u32 ptr; /* SRAM byte address of log data */
2510 u32 ev, time, data; /* event log data */
e5854471 2511 unsigned long reg_flags;
b7a79404
RC		 2512
2513 if (num_events == 0)
b03d7d0f 2514 return pos;
b2e640d4
JB		 2515
2516 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2517 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2518 if (!base)
2519 base = priv->_agn.init_evtlog_ptr;
2520 } else {
b7a79404 2521 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2522 if (!base)
2523 base = priv->_agn.inst_evtlog_ptr;
2524 }
b7a79404
RC		 2525
2526 if (mode == 0)
2527 event_size = 2 * sizeof(u32);
2528 else
2529 event_size = 3 * sizeof(u32);
2530
2531 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2532
e5854471
BC		 2533 /* Make sure device is powered up for SRAM reads */
2534 spin_lock_irqsave(&priv->reg_lock, reg_flags);
2535 iwl_grab_nic_access(priv);
2536
2537 /* Set starting address; reads will auto-increment */
2538 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2539 rmb();
2540
b7a79404
RC		 2541 /* "time" is actually "data" for mode 0 (no timestamp).
2542 * place event id # at far right for easier visual parsing. */
2543 for (i = 0; i < num_events; i++) {
e5854471
BC		 2544 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2545 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC		 2546 if (mode == 0) {
2547 /* data, ev */
b03d7d0f
WYG		 2548 if (bufsz) {
2549 pos += scnprintf(*buf + pos, bufsz - pos,
2550 "EVT_LOG:0x%08x:%04u\n",
2551 time, ev);
2552 } else {
2553 trace_iwlwifi_dev_ucode_event(priv, 0,
2554 time, ev);
2555 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2556 time, ev);
2557 }
b7a79404 2558 } else {
e5854471 2559 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b03d7d0f
WYG		 2560 if (bufsz) {
2561 pos += scnprintf(*buf + pos, bufsz - pos,
2562 "EVT_LOGT:%010u:0x%08x:%04u\n",
2563 time, data, ev);
2564 } else {
2565 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
b7a79404 2566 time, data, ev);
b03d7d0f
WYG		 2567 trace_iwlwifi_dev_ucode_event(priv, time,
2568 data, ev);
2569 }
b7a79404
RC		 2570 }
2571 }
e5854471
BC		 2572
2573 /* Allow device to power down */
2574 iwl_release_nic_access(priv);
2575 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b03d7d0f 2576 return pos;
b7a79404
RC		 2577}
2578
c341ddb2
WYG		 2579/**
2580 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2581 */
b03d7d0f
WYG		 2582static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2583 u32 num_wraps, u32 next_entry,
2584 u32 size, u32 mode,
2585 int pos, char **buf, size_t bufsz)
c341ddb2
WYG		 2586{
2587 /*
2588 * display the newest DEFAULT_LOG_ENTRIES entries
2589 * i.e the entries just before the next ont that uCode would fill.
2590 */
2591 if (num_wraps) {
2592 if (next_entry < size) {
b03d7d0f
WYG		 2593 pos = iwl_print_event_log(priv,
2594 capacity - (size - next_entry),
2595 size - next_entry, mode,
2596 pos, buf, bufsz);
2597 pos = iwl_print_event_log(priv, 0,
2598 next_entry, mode,
2599 pos, buf, bufsz);
c341ddb2 2600 } else
b03d7d0f
WYG		 2601 pos = iwl_print_event_log(priv, next_entry - size,
2602 size, mode, pos, buf, bufsz);
c341ddb2 2603 } else {
b03d7d0f
WYG		 2604 if (next_entry < size) {
2605 pos = iwl_print_event_log(priv, 0, next_entry,
2606 mode, pos, buf, bufsz);
2607 } else {
2608 pos = iwl_print_event_log(priv, next_entry - size,
2609 size, mode, pos, buf, bufsz);
2610 }
c341ddb2 2611 }
b03d7d0f 2612 return pos;
c341ddb2
WYG		 2613}
2614
c341ddb2
WYG		 2615#define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2616
b03d7d0f
WYG		 2617int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2618 char **buf, bool display)
b7a79404
RC		 2619{
2620 u32 base; /* SRAM byte address of event log header */
2621 u32 capacity; /* event log capacity in # entries */
2622 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2623 u32 num_wraps; /* # times uCode wrapped to top of log */
2624 u32 next_entry; /* index of next entry to be written by uCode */
2625 u32 size; /* # entries that we'll print */
b2e640d4 2626 u32 logsize;
b03d7d0f
WYG		 2627 int pos = 0;
2628 size_t bufsz = 0;
b7a79404 2629
b2e640d4 2630 if (priv->ucode_type == UCODE_INIT) {
b7a79404 2631 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
b2e640d4
JB		 2632 logsize = priv->_agn.init_evtlog_size;
2633 if (!base)
2634 base = priv->_agn.init_evtlog_ptr;
2635 } else {
b7a79404 2636 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
b2e640d4
JB		 2637 logsize = priv->_agn.inst_evtlog_size;
2638 if (!base)
2639 base = priv->_agn.inst_evtlog_ptr;
2640 }
b7a79404
RC		 2641
2642 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
212fb575
WYG		 2643 IWL_ERR(priv,
2644 "Invalid event log pointer 0x%08X for %s uCode\n",
2645 base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
937c397e 2646 return -EINVAL;
b7a79404
RC		 2647 }
2648
2649 /* event log header */
2650 capacity = iwl_read_targ_mem(priv, base);
2651 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2652 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2653 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2654
b2e640d4 2655 if (capacity > logsize) {
84c40692 2656 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
b2e640d4
JB		 2657 capacity, logsize);
2658 capacity = logsize;
84c40692
BC		 2659 }
2660
b2e640d4 2661 if (next_entry > logsize) {
84c40692 2662 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
b2e640d4
JB		 2663 next_entry, logsize);
2664 next_entry = logsize;
84c40692
BC		 2665 }
2666
b7a79404
RC		 2667 size = num_wraps ? capacity : next_entry;
2668
2669 /* bail out if nothing in log */
2670 if (size == 0) {
2671 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
b03d7d0f 2672 return pos;
b7a79404
RC		 2673 }
2674
f37837c9
WYG		 2675 /* enable/disable bt channel announcement */
2676 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2677
c341ddb2 2678#ifdef CONFIG_IWLWIFI_DEBUG
521d9bce 2679 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
c341ddb2
WYG		 2680 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2681 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2682#else
2683 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2684 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2685#endif
2686 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2687 size);
b7a79404 2688
c341ddb2 2689#ifdef CONFIG_IWLWIFI_DEBUG
b03d7d0f
WYG		 2690 if (display) {
2691 if (full_log)
2692 bufsz = capacity * 48;
2693 else
2694 bufsz = size * 48;
2695 *buf = kmalloc(bufsz, GFP_KERNEL);
2696 if (!*buf)
937c397e 2697 return -ENOMEM;
b03d7d0f 2698 }
c341ddb2
WYG		 2699 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2700 /*
2701 * if uCode has wrapped back to top of log,
2702 * start at the oldest entry,
2703 * i.e the next one that uCode would fill.
2704 */
2705 if (num_wraps)
b03d7d0f
WYG		 2706 pos = iwl_print_event_log(priv, next_entry,
2707 capacity - next_entry, mode,
2708 pos, buf, bufsz);
c341ddb2 2709 /* (then/else) start at top of log */
b03d7d0f
WYG		 2710 pos = iwl_print_event_log(priv, 0,
2711 next_entry, mode, pos, buf, bufsz);
c341ddb2 2712 } else
b03d7d0f
WYG		 2713 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2714 next_entry, size, mode,
2715 pos, buf, bufsz);
c341ddb2 2716#else
b03d7d0f
WYG		 2717 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2718 next_entry, size, mode,
2719 pos, buf, bufsz);
b7a79404 2720#endif
b03d7d0f 2721 return pos;
c341ddb2 2722}
b7a79404 2723
0975cc8f
WYG		 2724static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2725{
2726 struct iwl_ct_kill_config cmd;
2727 struct iwl_ct_kill_throttling_config adv_cmd;
2728 unsigned long flags;
2729 int ret = 0;
2730
2731 spin_lock_irqsave(&priv->lock, flags);
2732 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2733 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2734 spin_unlock_irqrestore(&priv->lock, flags);
2735 priv->thermal_throttle.ct_kill_toggle = false;
2736
7cb1b088 2737 if (priv->cfg->base_params->support_ct_kill_exit) {
0975cc8f
WYG		 2738 adv_cmd.critical_temperature_enter =
2739 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2740 adv_cmd.critical_temperature_exit =
2741 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2742
2743 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2744 sizeof(adv_cmd), &adv_cmd);
2745 if (ret)
2746 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2747 else
2748 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2749 "succeeded, "
2750 "critical temperature enter is %d,"
2751 "exit is %d\n",
2752 priv->hw_params.ct_kill_threshold,
2753 priv->hw_params.ct_kill_exit_threshold);
2754 } else {
2755 cmd.critical_temperature_R =
2756 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2757
2758 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2759 sizeof(cmd), &cmd);
2760 if (ret)
2761 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2762 else
2763 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2764 "succeeded, "
2765 "critical temperature is %d\n",
2766 priv->hw_params.ct_kill_threshold);
2767 }
2768}
2769
6d6a1afd
SZ		 2770static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2771{
2772 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2773 struct iwl_host_cmd cmd = {
2774 .id = CALIBRATION_CFG_CMD,
2775 .len = sizeof(struct iwl_calib_cfg_cmd),
2776 .data = &calib_cfg_cmd,
2777 };
2778
2779 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2780 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
7cb1b088 2781 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
6d6a1afd
SZ		 2782
2783 return iwl_send_cmd(priv, &cmd);
2784}
2785
2786
b481de9c 2787/**
4a4a9e81 2788 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 2789 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 2790 * Alive gets handled by iwl_init_alive_start()).
b481de9c 2791 */
4a4a9e81 2792static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 2793{
57aab75a 2794 int ret = 0;
246ed355 2795 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
b481de9c 2796
e1623446 2797 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY		 2798
2799 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
2800 /* We had an error bringing up the hardware, so take it
2801 * all the way back down so we can try again */
e1623446 2802 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY		 2803 goto restart;
2804 }
2805
2806 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2807 * This is a paranoid check, because we would not have gotten the
2808 * "runtime" alive if code weren't properly loaded. */
b0692f2f 2809 if (iwl_verify_ucode(priv)) {
b481de9c
ZY		 2810 /* Runtime instruction load was bad;
2811 * take it all the way back down so we can try again */
e1623446 2812 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY		 2813 goto restart;
2814 }
2815
57aab75a
TW		 2816 ret = priv->cfg->ops->lib->alive_notify(priv);
2817 if (ret) {
39aadf8c
WT		 2818 IWL_WARN(priv,
2819 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY		 2820 goto restart;
2821 }
2822
6d6a1afd
SZ		 2823 if (priv->hw_params.calib_rt_cfg)
2824 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2825
2826
5b9f8cd3 2827 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY		 2828 set_bit(STATUS_ALIVE, &priv->status);
2829
b74e31a9
WYG		 2830 if (priv->cfg->ops->lib->recover_from_tx_stall) {
2831 /* Enable timer to monitor the driver queues */
2832 mod_timer(&priv->monitor_recover,
2833 jiffies +
7cb1b088
WYG		 2834 msecs_to_jiffies(
2835 priv->cfg->base_params->monitor_recover_period));
b74e31a9
WYG		 2836 }
2837
fee1247a 2838 if (iwl_is_rfkill(priv))
b481de9c
ZY		 2839 return;
2840
7cb1b088
WYG		 2841 if (priv->cfg->bt_params &&
2842 priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f
WYG		 2843 /* Configure Bluetooth device coexistence support */
2844 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2845 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2846 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2847 priv->cfg->ops->hcmd->send_bt_config(priv);
2848 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2849 if (bt_coex_active && priv->iw_mode != NL80211_IFTYPE_ADHOC)
2850 iwlagn_send_prio_tbl(priv);
2851
2852 /* FIXME: w/a to force change uCode BT state machine */
2853 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2854 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2855 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2856 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2857 }
36d6825b 2858 ieee80211_wake_queues(priv->hw);
b481de9c 2859
470ab2dd 2860 priv->active_rate = IWL_RATES_MASK;
b481de9c 2861
2f748dec
WYG		 2862 /* Configure Tx antenna selection based on H/W config */
2863 if (priv->cfg->ops->hcmd->set_tx_ant)
2864 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2865
246ed355 2866 if (iwl_is_associated_ctx(ctx)) {
c1adf9fb 2867 struct iwl_rxon_cmd *active_rxon =
246ed355 2868 (struct iwl_rxon_cmd *)&ctx->active;
019fb97d 2869 /* apply any changes in staging */
246ed355 2870 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY		 2871 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2872 } else {
d0fe478c 2873 struct iwl_rxon_context *tmp;
b481de9c 2874 /* Initialize our rx_config data */
d0fe478c
JB		 2875 for_each_context(priv, tmp)
2876 iwl_connection_init_rx_config(priv, tmp);
45823531
AK		 2877
2878 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 2879 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c
ZY		 2880 }
2881
7cb1b088
WYG		 2882 if (priv->cfg->bt_params &&
2883 !priv->cfg->bt_params->advanced_bt_coexist) {
aeb4a2ee
WYG		 2884 /* Configure Bluetooth device coexistence support */
2885 priv->cfg->ops->hcmd->send_bt_config(priv);
2886 }
b481de9c 2887
4a4a9e81
TW		 2888 iwl_reset_run_time_calib(priv);
2889
b481de9c 2890 /* Configure the adapter for unassociated operation */
246ed355 2891 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 2892
2893 /* At this point, the NIC is initialized and operational */
47f4a587 2894 iwl_rf_kill_ct_config(priv);
5a66926a 2895
e932a609 2896 iwl_leds_init(priv);
fe00b5a5 2897
e1623446 2898 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 2899 set_bit(STATUS_READY, &priv->status);
5a66926a 2900 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 2901
e312c24c 2902 iwl_power_update_mode(priv, true);
7e246191
RC		 2903 IWL_DEBUG_INFO(priv, "Updated power mode\n");
2904
c46fbefa 2905
b481de9c
ZY		 2906 return;
2907
2908 restart:
2909 queue_work(priv->workqueue, &priv->restart);
2910}
2911
4e39317d 2912static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 2913
5b9f8cd3 2914static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 2915{
2916 unsigned long flags;
2917 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2918
e1623446 2919 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 2920
d745d472
SG		 2921 iwl_scan_cancel_timeout(priv, 200);
2922
2923 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 2924
b62177a0
SG		 2925 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2926 * to prevent rearm timer */
2927 if (priv->cfg->ops->lib->recover_from_tx_stall)
2928 del_timer_sync(&priv->monitor_recover);
2929
dcef732c 2930 iwl_clear_ucode_stations(priv, NULL);
a194e324 2931 iwl_dealloc_bcast_stations(priv);
db125c78 2932 iwl_clear_driver_stations(priv);
b481de9c 2933
a1174138 2934 /* reset BT coex data */
da5dbb97 2935 priv->bt_status = 0;
7cb1b088
WYG		 2936 if (priv->cfg->bt_params)
2937 priv->bt_traffic_load =
2938 priv->cfg->bt_params->bt_init_traffic_load;
2939 else
2940 priv->bt_traffic_load = 0;
a1174138 2941 priv->bt_sco_active = false;
bee008b7
WYG		 2942 priv->bt_full_concurrent = false;
2943 priv->bt_ci_compliance = 0;
a1174138 2944
b481de9c
ZY		 2945 /* Unblock any waiting calls */
2946 wake_up_interruptible_all(&priv->wait_command_queue);
2947
b481de9c
ZY		 2948 /* Wipe out the EXIT_PENDING status bit if we are not actually
2949 * exiting the module */
2950 if (!exit_pending)
2951 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2952
2953 /* stop and reset the on-board processor */
3395f6e9 2954 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY		 2955
2956 /* tell the device to stop sending interrupts */
0359facc 2957 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2958 iwl_disable_interrupts(priv);
0359facc
MA		 2959 spin_unlock_irqrestore(&priv->lock, flags);
2960 iwl_synchronize_irq(priv);
b481de9c
ZY		 2961
2962 if (priv->mac80211_registered)
2963 ieee80211_stop_queues(priv->hw);
2964
5b9f8cd3 2965 /* If we have not previously called iwl_init() then
a60e77e5 2966 * clear all bits but the RF Kill bit and return */
fee1247a 2967 if (!iwl_is_init(priv)) {
b481de9c
ZY		 2968 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2969 STATUS_RF_KILL_HW |
9788864e
RC		 2970 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2971 STATUS_GEO_CONFIGURED |
052ec3f1
MA		 2972 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2973 STATUS_EXIT_PENDING;
b481de9c
ZY		 2974 goto exit;
2975 }
2976
6da3a13e 2977 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 2978 * bit and continue taking the NIC down. */
b481de9c
ZY		 2979 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2980 STATUS_RF_KILL_HW |
9788864e
RC		 2981 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2982 STATUS_GEO_CONFIGURED |
b481de9c 2983 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA		 2984 STATUS_FW_ERROR |
2985 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2986 STATUS_EXIT_PENDING;
b481de9c 2987
ef850d7c
MA		 2988 /* device going down, Stop using ICT table */
2989 iwl_disable_ict(priv);
b481de9c 2990
74bcdb33 2991 iwlagn_txq_ctx_stop(priv);
54b81550 2992 iwlagn_rxq_stop(priv);
b481de9c 2993
309e731a
BC		 2994 /* Power-down device's busmaster DMA clocks */
2995 iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY		 2996 udelay(5);
2997
309e731a
BC		 2998 /* Make sure (redundant) we've released our request to stay awake */
2999 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
3000
4d2ccdb9
BC		 3001 /* Stop the device, and put it in low power state */
3002 priv->cfg->ops->lib->apm_ops.stop(priv);
3003
b481de9c 3004 exit:
885ba202 3005 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY		 3006
3007 if (priv->ibss_beacon)
3008 dev_kfree_skb(priv->ibss_beacon);
3009 priv->ibss_beacon = NULL;
3010
3011 /* clear out any free frames */
fcab423d 3012 iwl_clear_free_frames(priv);
b481de9c
ZY		 3013}
3014
5b9f8cd3 3015static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY		 3016{
3017 mutex_lock(&priv->mutex);
5b9f8cd3 3018 __iwl_down(priv);
b481de9c 3019 mutex_unlock(&priv->mutex);
b24d22b1 3020
4e39317d 3021 iwl_cancel_deferred_work(priv);
b481de9c
ZY		 3022}
3023
086ed117
MA		 3024#define HW_READY_TIMEOUT (50)
3025
3026static int iwl_set_hw_ready(struct iwl_priv *priv)
3027{
3028 int ret = 0;
3029
3030 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3031 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
3032
3033 /* See if we got it */
3034 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3035 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3036 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
3037 HW_READY_TIMEOUT);
3038 if (ret != -ETIMEDOUT)
3039 priv->hw_ready = true;
3040 else
3041 priv->hw_ready = false;
3042
3043 IWL_DEBUG_INFO(priv, "hardware %s\n",
3044 (priv->hw_ready == 1) ? "ready" : "not ready");
3045 return ret;
3046}
3047
3048static int iwl_prepare_card_hw(struct iwl_priv *priv)
3049{
3050 int ret = 0;
3051
91dd6c27 3052 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
086ed117 3053
3354a0f6
MA		 3054 ret = iwl_set_hw_ready(priv);
3055 if (priv->hw_ready)
3056 return ret;
3057
3058 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA		 3059 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
3060 CSR_HW_IF_CONFIG_REG_PREPARE);
3061
3062 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
3063 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
3064 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
3065
3354a0f6 3066 /* HW should be ready by now, check again. */
086ed117
MA		 3067 if (ret != -ETIMEDOUT)
3068 iwl_set_hw_ready(priv);
3069
3070 return ret;
3071}
3072
b481de9c
ZY		 3073#define MAX_HW_RESTARTS 5
3074
5b9f8cd3 3075static int __iwl_up(struct iwl_priv *priv)
b481de9c 3076{
a194e324 3077 struct iwl_rxon_context *ctx;
57aab75a
TW		 3078 int i;
3079 int ret;
b481de9c
ZY		 3080
3081 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 3082 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY		 3083 return -EIO;
3084 }
3085
e903fbd4 3086 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 3087 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC		 3088 return -EIO;
3089 }
3090
a194e324
JB		 3091 for_each_context(priv, ctx) {
3092 ret = iwl_alloc_bcast_station(priv, ctx, true);
3093 if (ret) {
3094 iwl_dealloc_bcast_stations(priv);
3095 return ret;
3096 }
3097 }
2c810ccd 3098
086ed117
MA		 3099 iwl_prepare_card_hw(priv);
3100
3101 if (!priv->hw_ready) {
3102 IWL_WARN(priv, "Exit HW not ready\n");
3103 return -EIO;
3104 }
3105
e655b9f0 3106 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 3107 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 3108 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3109 else
e655b9f0 3110 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 3111
c1842d61 3112 if (iwl_is_rfkill(priv)) {
a60e77e5
JB		 3113 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
3114
5b9f8cd3 3115 iwl_enable_interrupts(priv);
a60e77e5 3116 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 3117 return 0;
b481de9c
ZY		 3118 }
3119
3395f6e9 3120 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 3121
13bb9483 3122 /* must be initialised before iwl_hw_nic_init */
751ca305
JB		 3123 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
3124 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
3125 else
3126 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
13bb9483 3127
74bcdb33 3128 ret = iwlagn_hw_nic_init(priv);
57aab75a 3129 if (ret) {
15b1687c 3130 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 3131 return ret;
b481de9c
ZY		 3132 }
3133
3134 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3135 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3136 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 3137 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
3138
3139 /* clear (again), then enable host interrupts */
3395f6e9 3140 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 3141 iwl_enable_interrupts(priv);
b481de9c
ZY		 3142
3143 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW		 3144 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
3145 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY		 3146
3147 /* Copy original ucode data image from disk into backup cache.
3148 * This will be used to initialize the on-board processor's
3149 * data SRAM for a clean start when the runtime program first loads. */
3150 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 3151 priv->ucode_data.len);
b481de9c 3152
b481de9c
ZY		 3153 for (i = 0; i < MAX_HW_RESTARTS; i++) {
3154
b481de9c
ZY		 3155 /* load bootstrap state machine,
3156 * load bootstrap program into processor's memory,
3157 * prepare to load the "initialize" uCode */
57aab75a 3158 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 3159
57aab75a 3160 if (ret) {
15b1687c
WT		 3161 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
3162 ret);
b481de9c
ZY		 3163 continue;
3164 }
3165
3166 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 3167 iwl_nic_start(priv);
b481de9c 3168
e1623446 3169 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY		 3170
3171 return 0;
3172 }
3173
3174 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 3175 __iwl_down(priv);
64e72c3e 3176 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY		 3177
3178 /* tried to restart and config the device for as long as our
3179 * patience could withstand */
15b1687c 3180 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY		 3181 return -EIO;
3182}
3183
3184
3185/*****************************************************************************
3186 *
3187 * Workqueue callbacks
3188 *
3189 *****************************************************************************/
3190
4a4a9e81 3191static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 3192{
c79dd5b5
TW		 3193 struct iwl_priv *priv =
3194 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY		 3195
3196 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3197 return;
3198
3199 mutex_lock(&priv->mutex);
f3ccc08c 3200 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY		 3201 mutex_unlock(&priv->mutex);
3202}
3203
4a4a9e81 3204static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 3205{
c79dd5b5
TW		 3206 struct iwl_priv *priv =
3207 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY		 3208
3209 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3210 return;
3211
258c44a0
MA		 3212 /* enable dram interrupt */
3213 iwl_reset_ict(priv);
3214
b481de9c 3215 mutex_lock(&priv->mutex);
4a4a9e81 3216 iwl_alive_start(priv);
b481de9c
ZY		 3217 mutex_unlock(&priv->mutex);
3218}
3219
16e727e8
EG		 3220static void iwl_bg_run_time_calib_work(struct work_struct *work)
3221{
3222 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3223 run_time_calib_work);
3224
3225 mutex_lock(&priv->mutex);
3226
3227 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3228 test_bit(STATUS_SCANNING, &priv->status)) {
3229 mutex_unlock(&priv->mutex);
3230 return;
3231 }
3232
3233 if (priv->start_calib) {
7cb1b088
WYG		 3234 if (priv->cfg->bt_params &&
3235 priv->cfg->bt_params->bt_statistics) {
7980fba5
WYG		 3236 iwl_chain_noise_calibration(priv,
3237 (void *)&priv->_agn.statistics_bt);
3238 iwl_sensitivity_calibration(priv,
3239 (void *)&priv->_agn.statistics_bt);
3240 } else {
3241 iwl_chain_noise_calibration(priv,
3242 (void *)&priv->_agn.statistics);
3243 iwl_sensitivity_calibration(priv,
3244 (void *)&priv->_agn.statistics);
3245 }
16e727e8
EG		 3246 }
3247
3248 mutex_unlock(&priv->mutex);
16e727e8
EG		 3249}
3250
5b9f8cd3 3251static void iwl_bg_restart(struct work_struct *data)
b481de9c 3252{
c79dd5b5 3253 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY		 3254
3255 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3256 return;
3257
19cc1087 3258 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
8bd413e6 3259 struct iwl_rxon_context *ctx;
bee008b7
WYG		 3260 bool bt_sco, bt_full_concurrent;
3261 u8 bt_ci_compliance;
511b082d 3262 u8 bt_load;
da5dbb97 3263 u8 bt_status;
511b082d 3264
19cc1087 3265 mutex_lock(&priv->mutex);
8bd413e6
JB		 3266 for_each_context(priv, ctx)
3267 ctx->vif = NULL;
19cc1087 3268 priv->is_open = 0;
511b082d
JB		 3269
3270 /*
3271 * __iwl_down() will clear the BT status variables,
3272 * which is correct, but when we restart we really
3273 * want to keep them so restore them afterwards.
3274 *
3275 * The restart process will later pick them up and
3276 * re-configure the hw when we reconfigure the BT
3277 * command.
3278 */
3279 bt_sco = priv->bt_sco_active;
bee008b7
WYG		 3280 bt_full_concurrent = priv->bt_full_concurrent;
3281 bt_ci_compliance = priv->bt_ci_compliance;
511b082d 3282 bt_load = priv->bt_traffic_load;
da5dbb97 3283 bt_status = priv->bt_status;
511b082d 3284
a1174138 3285 __iwl_down(priv);
511b082d
JB		 3286
3287 priv->bt_sco_active = bt_sco;
bee008b7
WYG		 3288 priv->bt_full_concurrent = bt_full_concurrent;
3289 priv->bt_ci_compliance = bt_ci_compliance;
511b082d 3290 priv->bt_traffic_load = bt_load;
da5dbb97 3291 priv->bt_status = bt_status;
511b082d 3292
19cc1087 3293 mutex_unlock(&priv->mutex);
a1174138 3294 iwl_cancel_deferred_work(priv);
19cc1087
JB		 3295 ieee80211_restart_hw(priv->hw);
3296 } else {
3297 iwl_down(priv);
80676518
JB		 3298
3299 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3300 return;
3301
3302 mutex_lock(&priv->mutex);
3303 __iwl_up(priv);
3304 mutex_unlock(&priv->mutex);
19cc1087 3305 }
b481de9c
ZY		 3306}
3307
5b9f8cd3 3308static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 3309{
c79dd5b5
TW		 3310 struct iwl_priv *priv =
3311 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY		 3312
3313 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3314 return;
3315
3316 mutex_lock(&priv->mutex);
54b81550 3317 iwlagn_rx_replenish(priv);
b481de9c
ZY		 3318 mutex_unlock(&priv->mutex);
3319}
3320
7878a5a4
MA		 3321#define IWL_DELAY_NEXT_SCAN (HZ*2)
3322
1dda6d28 3323void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3324{
246ed355 3325 struct iwl_rxon_context *ctx;
b481de9c 3326 struct ieee80211_conf *conf = NULL;
857485c0 3327 int ret = 0;
b481de9c 3328
1dda6d28
JB		 3329 if (!vif || !priv->is_open)
3330 return;
3331
246ed355
JB		 3332 ctx = iwl_rxon_ctx_from_vif(vif);
3333
1dda6d28 3334 if (vif->type == NL80211_IFTYPE_AP) {
15b1687c 3335 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY		 3336 return;
3337 }
3338
b481de9c
ZY		 3339 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3340 return;
3341
2a421b91 3342 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 3343
b481de9c
ZY		 3344 conf = ieee80211_get_hw_conf(priv->hw);
3345
246ed355
JB		 3346 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3347 iwlcore_commit_rxon(priv, ctx);
b481de9c 3348
47313e34 3349 ret = iwl_send_rxon_timing(priv, ctx);
857485c0 3350 if (ret)
8f2d3d2a 3351 IWL_WARN(priv, "RXON timing - "
b481de9c
ZY		 3352 "Attempting to continue.\n");
3353
246ed355 3354 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c 3355
42eb7c64 3356 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 3357
45823531 3358 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3359 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
45823531 3360
246ed355 3361 ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
b481de9c 3362
e1623446 3363 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
1dda6d28 3364 vif->bss_conf.aid, vif->bss_conf.beacon_int);
b481de9c 3365
c213d745 3366 if (vif->bss_conf.use_short_preamble)
246ed355 3367 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3368 else
246ed355 3369 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
b481de9c 3370
246ed355 3371 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3372 if (vif->bss_conf.use_short_slot)
246ed355 3373 ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3374 else
246ed355 3375 ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c
ZY		 3376 }
3377
246ed355 3378 iwlcore_commit_rxon(priv, ctx);
b481de9c 3379
fe6b23dd 3380 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
246ed355 3381 vif->bss_conf.aid, ctx->active.bssid_addr);
fe6b23dd 3382
1dda6d28 3383 switch (vif->type) {
05c914fe 3384 case NL80211_IFTYPE_STATION:
b481de9c 3385 break;
05c914fe 3386 case NL80211_IFTYPE_ADHOC:
5b9f8cd3 3387 iwl_send_beacon_cmd(priv);
b481de9c 3388 break;
b481de9c 3389 default:
15b1687c 3390 IWL_ERR(priv, "%s Should not be called in %d mode\n",
1dda6d28 3391 __func__, vif->type);
b481de9c
ZY		 3392 break;
3393 }
3394
04816448
GE		 3395 /* the chain noise calibration will enabled PM upon completion
3396 * If chain noise has already been run, then we need to enable
3397 * power management here */
3398 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 3399 iwl_power_update_mode(priv, false);
c90a74ba
EG		 3400
3401 /* Enable Rx differential gain and sensitivity calibrations */
3402 iwl_chain_noise_reset(priv);
3403 priv->start_calib = 1;
3404
508e32e1
RC		 3405}
3406
b481de9c
ZY		 3407/*****************************************************************************
3408 *
3409 * mac80211 entry point functions
3410 *
3411 *****************************************************************************/
3412
154b25ce 3413#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 3414
f0b6e2e8
RC		 3415/*
3416 * Not a mac80211 entry point function, but it fits in with all the
3417 * other mac80211 functions grouped here.
3418 */
dd7a2509
JB		 3419static int iwl_mac_setup_register(struct iwl_priv *priv,
3420 struct iwlagn_ucode_capabilities *capa)
f0b6e2e8
RC		 3421{
3422 int ret;
3423 struct ieee80211_hw *hw = priv->hw;
d0fe478c
JB		 3424 struct iwl_rxon_context *ctx;
3425
f0b6e2e8
RC		 3426 hw->rate_control_algorithm = "iwl-agn-rs";
3427
3428 /* Tell mac80211 our characteristics */
3429 hw->flags = IEEE80211_HW_SIGNAL_DBM |
f0b6e2e8 3430 IEEE80211_HW_AMPDU_AGGREGATION |
2491fa42 3431 IEEE80211_HW_NEED_DTIM_PERIOD |
f0b6e2e8
RC		 3432 IEEE80211_HW_SPECTRUM_MGMT;
3433
7cb1b088 3434 if (!priv->cfg->base_params->broken_powersave)
f0b6e2e8
RC		 3435 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3436 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3437
ba37a3d0
JB		 3438 if (priv->cfg->sku & IWL_SKU_N)
3439 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3440 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3441
8d9698b3 3442 hw->sta_data_size = sizeof(struct iwl_station_priv);
fd1af15d
JB		 3443 hw->vif_data_size = sizeof(struct iwl_vif_priv);
3444
d0fe478c
JB		 3445 for_each_context(priv, ctx) {
3446 hw->wiphy->interface_modes |= ctx->interface_modes;
3447 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3448 }
f0b6e2e8 3449
f6c8f152 3450 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
5be83de5 3451 WIPHY_FLAG_DISABLE_BEACON_HINTS;
f0b6e2e8
RC		 3452
3453 /*
3454 * For now, disable PS by default because it affects
3455 * RX performance significantly.
3456 */
5be83de5 3457 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
f0b6e2e8 3458
1382c71c 3459 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
f0b6e2e8 3460 /* we create the 802.11 header and a zero-length SSID element */
dd7a2509 3461 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
f0b6e2e8
RC		 3462
3463 /* Default value; 4 EDCA QOS priorities */
3464 hw->queues = 4;
3465
3466 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3467
3468 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3469 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3470 &priv->bands[IEEE80211_BAND_2GHZ];
3471 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3472 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3473 &priv->bands[IEEE80211_BAND_5GHZ];
3474
3475 ret = ieee80211_register_hw(priv->hw);
3476 if (ret) {
3477 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3478 return ret;
3479 }
3480 priv->mac80211_registered = 1;
3481
3482 return 0;
3483}
3484
3485
5b9f8cd3 3486static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 3487{
c79dd5b5 3488 struct iwl_priv *priv = hw->priv;
5a66926a 3489 int ret;
b481de9c 3490
e1623446 3491 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY		 3492
3493 /* we should be verifying the device is ready to be opened */
3494 mutex_lock(&priv->mutex);
5b9f8cd3 3495 ret = __iwl_up(priv);
b481de9c 3496 mutex_unlock(&priv->mutex);
5a66926a 3497
e655b9f0 3498 if (ret)
6cd0b1cb 3499 return ret;
e655b9f0 3500
c1842d61
TW		 3501 if (iwl_is_rfkill(priv))
3502 goto out;
3503
e1623446 3504 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 3505
fe9b6b72 3506 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 3507 * mac80211 will not be run successfully. */
154b25ce
EG		 3508 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3509 test_bit(STATUS_READY, &priv->status),
3510 UCODE_READY_TIMEOUT);
3511 if (!ret) {
3512 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 3513 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 3514 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 3515 return -ETIMEDOUT;
5a66926a 3516 }
fe9b6b72 3517 }
0a078ffa 3518
e932a609
JB		 3519 iwl_led_start(priv);
3520
c1842d61 3521out:
0a078ffa 3522 priv->is_open = 1;
e1623446 3523 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3524 return 0;
3525}
3526
5b9f8cd3 3527static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 3528{
c79dd5b5 3529 struct iwl_priv *priv = hw->priv;
b481de9c 3530
e1623446 3531 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 3532
19cc1087 3533 if (!priv->is_open)
e655b9f0 3534 return;
e655b9f0 3535
b481de9c 3536 priv->is_open = 0;
5a66926a 3537
5b9f8cd3 3538 iwl_down(priv);
5a66926a
ZY		 3539
3540 flush_workqueue(priv->workqueue);
6cd0b1cb
HS		 3541
3542 /* enable interrupts again in order to receive rfkill changes */
3543 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3544 iwl_enable_interrupts(priv);
948c171c 3545
e1623446 3546 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY		 3547}
3548
5b9f8cd3 3549static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 3550{
c79dd5b5 3551 struct iwl_priv *priv = hw->priv;
b481de9c 3552
e1623446 3553 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 3554
e1623446 3555 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 3556 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 3557
74bcdb33 3558 if (iwlagn_tx_skb(priv, skb))
b481de9c
ZY		 3559 dev_kfree_skb_any(skb);
3560
e1623446 3561 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 3562 return NETDEV_TX_OK;
b481de9c
ZY		 3563}
3564
1dda6d28 3565void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
b481de9c 3566{
246ed355 3567 struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
857485c0 3568 int ret = 0;
b481de9c 3569
76d04815
JB		 3570 lockdep_assert_held(&priv->mutex);
3571
d986bcd1 3572 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY		 3573 return;
3574
3575 /* The following should be done only at AP bring up */
246ed355 3576 if (!iwl_is_associated_ctx(ctx)) {
b481de9c
ZY		 3577
3578 /* RXON - unassoc (to set timing command) */
246ed355
JB		 3579 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3580 iwlcore_commit_rxon(priv, ctx);
b481de9c
ZY		 3581
3582 /* RXON Timing */
47313e34 3583 ret = iwl_send_rxon_timing(priv, ctx);
857485c0 3584 if (ret)
8f2d3d2a 3585 IWL_WARN(priv, "RXON timing failed - "
b481de9c
ZY		 3586 "Attempting to continue.\n");
3587
f513dfff
DH		 3588 /* AP has all antennas */
3589 priv->chain_noise_data.active_chains =
3590 priv->hw_params.valid_rx_ant;
3591 iwl_set_rxon_ht(priv, &priv->current_ht_config);
45823531 3592 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355 3593 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
b481de9c 3594
246ed355 3595 ctx->staging.assoc_id = 0;
1dda6d28 3596
c213d745 3597 if (vif->bss_conf.use_short_preamble)
246ed355 3598 ctx->staging.flags |=
b481de9c
ZY		 3599 RXON_FLG_SHORT_PREAMBLE_MSK;
3600 else
246ed355 3601 ctx->staging.flags &=
b481de9c
ZY		 3602 ~RXON_FLG_SHORT_PREAMBLE_MSK;
3603
246ed355 3604 if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
c213d745 3605 if (vif->bss_conf.use_short_slot)
246ed355 3606 ctx->staging.flags |=
b481de9c
ZY		 3607 RXON_FLG_SHORT_SLOT_MSK;
3608 else
246ed355 3609 ctx->staging.flags &=
b481de9c 3610 ~RXON_FLG_SHORT_SLOT_MSK;
b481de9c 3611 }
08abc53c
JB		 3612 /* need to send beacon cmd before committing assoc RXON! */
3613 iwl_send_beacon_cmd(priv);
b481de9c 3614 /* restore RXON assoc */
246ed355
JB		 3615 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
3616 iwlcore_commit_rxon(priv, ctx);
e1493deb 3617 }
5b9f8cd3 3618 iwl_send_beacon_cmd(priv);
b481de9c
ZY		 3619
3620 /* FIXME - we need to add code here to detect a totally new
3621 * configuration, reset the AP, unassoc, rxon timing, assoc,
3622 * clear sta table, add BCAST sta... */
3623}
3624
5b9f8cd3 3625static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 3626 struct ieee80211_vif *vif,
3627 struct ieee80211_key_conf *keyconf,
3628 struct ieee80211_sta *sta,
3629 u32 iv32, u16 *phase1key)
ab885f8c 3630{
ab885f8c 3631
9f58671e 3632 struct iwl_priv *priv = hw->priv;
a194e324
JB		 3633 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3634
e1623446 3635 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 3636
a194e324 3637 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
b3fbdcf4 3638 iv32, phase1key);
ab885f8c 3639
e1623446 3640 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG		 3641}
3642
5b9f8cd3 3643static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3644 struct ieee80211_vif *vif,
3645 struct ieee80211_sta *sta,
b481de9c
ZY		 3646 struct ieee80211_key_conf *key)
3647{
c79dd5b5 3648 struct iwl_priv *priv = hw->priv;
a194e324 3649 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
c10afb6e 3650 struct iwl_rxon_context *ctx = vif_priv->ctx;
42986796
WT		 3651 int ret;
3652 u8 sta_id;
3653 bool is_default_wep_key = false;
b481de9c 3654
e1623446 3655 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 3656
90e8e424 3657 if (priv->cfg->mod_params->sw_crypto) {
e1623446 3658 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY		 3659 return -EOPNOTSUPP;
3660 }
b481de9c 3661
a194e324 3662 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
0af8bcae
JB		 3663 if (sta_id == IWL_INVALID_STATION)
3664 return -EINVAL;
b481de9c 3665
6974e363 3666 mutex_lock(&priv->mutex);
2a421b91 3667 iwl_scan_cancel_timeout(priv, 100);
6974e363 3668
a90178fa
JB		 3669 /*
3670 * If we are getting WEP group key and we didn't receive any key mapping
6974e363
EG		 3671 * so far, we are in legacy wep mode (group key only), otherwise we are
3672 * in 1X mode.
a90178fa
JB		 3673 * In legacy wep mode, we use another host command to the uCode.
3674 */
97359d12
JB		 3675 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3676 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
54c8067a 3677 !sta) {
6974e363 3678 if (cmd == SET_KEY)
c10afb6e 3679 is_default_wep_key = !ctx->key_mapping_keys;
6974e363 3680 else
ccc038ab
EG		 3681 is_default_wep_key =
3682 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 3683 }
052c4b9f 3684
b481de9c 3685 switch (cmd) {
deb09c43 3686 case SET_KEY:
6974e363 3687 if (is_default_wep_key)
2995bafa 3688 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
deb09c43 3689 else
a194e324
JB		 3690 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3691 key, sta_id);
deb09c43 3692
e1623446 3693 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY		 3694 break;
3695 case DISABLE_KEY:
6974e363 3696 if (is_default_wep_key)
c10afb6e 3697 ret = iwl_remove_default_wep_key(priv, ctx, key);
deb09c43 3698 else
c10afb6e 3699 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
deb09c43 3700
e1623446 3701 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY		 3702 break;
3703 default:
deb09c43 3704 ret = -EINVAL;
b481de9c
ZY		 3705 }
3706
72e15d71 3707 mutex_unlock(&priv->mutex);
e1623446 3708 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 3709
deb09c43 3710 return ret;
b481de9c
ZY		 3711}
3712
5b9f8cd3 3713static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
c951ad35 3714 struct ieee80211_vif *vif,
832f47e3
JB		 3715 enum ieee80211_ampdu_mlme_action action,
3716 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW		 3717{
3718 struct iwl_priv *priv = hw->priv;
4620fefa 3719 int ret = -EINVAL;
d783b061 3720
e1623446 3721 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 3722 sta->addr, tid);
d783b061
TW		 3723
3724 if (!(priv->cfg->sku & IWL_SKU_N))
3725 return -EACCES;
3726
4620fefa
JB		 3727 mutex_lock(&priv->mutex);
3728
d783b061
TW		 3729 switch (action) {
3730 case IEEE80211_AMPDU_RX_START:
e1623446 3731 IWL_DEBUG_HT(priv, "start Rx\n");
4620fefa
JB		 3732 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3733 break;
d783b061 3734 case IEEE80211_AMPDU_RX_STOP:
e1623446 3735 IWL_DEBUG_HT(priv, "stop Rx\n");
619753ff 3736 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
5c2207c6 3737 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa
JB		 3738 ret = 0;
3739 break;
d783b061 3740 case IEEE80211_AMPDU_TX_START:
e1623446 3741 IWL_DEBUG_HT(priv, "start Tx\n");
619753ff 3742 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
d5a0ffa3
WYG		 3743 if (ret == 0) {
3744 priv->_agn.agg_tids_count++;
3745 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3746 priv->_agn.agg_tids_count);
3747 }
4620fefa 3748 break;
d783b061 3749 case IEEE80211_AMPDU_TX_STOP:
e1623446 3750 IWL_DEBUG_HT(priv, "stop Tx\n");
619753ff 3751 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
d5a0ffa3
WYG		 3752 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3753 priv->_agn.agg_tids_count--;
3754 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3755 priv->_agn.agg_tids_count);
3756 }
5c2207c6 3757 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
4620fefa 3758 ret = 0;
7cb1b088
WYG		 3759 if (priv->cfg->ht_params &&
3760 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 3761 struct iwl_station_priv *sta_priv =
3762 (void *) sta->drv_priv;
3763 /*
3764 * switch off RTS/CTS if it was previously enabled
3765 */
3766
3767 sta_priv->lq_sta.lq.general_params.flags &=
3768 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3769 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3770 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
94597ab2 3771 }
4620fefa 3772 break;
f0527971 3773 case IEEE80211_AMPDU_TX_OPERATIONAL:
7cb1b088
WYG		 3774 if (priv->cfg->ht_params &&
3775 priv->cfg->ht_params->use_rts_for_aggregation) {
94597ab2
JB		 3776 struct iwl_station_priv *sta_priv =
3777 (void *) sta->drv_priv;
3778
cfecc6b4
WYG		 3779 /*
3780 * switch to RTS/CTS if it is the prefer protection
3781 * method for HT traffic
3782 */
94597ab2
JB		 3783
3784 sta_priv->lq_sta.lq.general_params.flags |=
3785 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
7e6a5886
JB		 3786 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3787 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
cfecc6b4
WYG		 3788 }
3789 ret = 0;
d783b061
TW		 3790 break;
3791 }
4620fefa
JB		 3792 mutex_unlock(&priv->mutex);
3793
3794 return ret;
d783b061 3795}
9f58671e 3796
6ab10ff8
JB		 3797static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
3798 struct ieee80211_vif *vif,
3799 enum sta_notify_cmd cmd,
3800 struct ieee80211_sta *sta)
3801{
3802 struct iwl_priv *priv = hw->priv;
3803 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3804 int sta_id;
3805
6ab10ff8 3806 switch (cmd) {
6ab10ff8
JB		 3807 case STA_NOTIFY_SLEEP:
3808 WARN_ON(!sta_priv->client);
3809 sta_priv->asleep = true;
3810 if (atomic_read(&sta_priv->pending_frames) > 0)
3811 ieee80211_sta_block_awake(hw, sta, true);
3812 break;
3813 case STA_NOTIFY_AWAKE:
3814 WARN_ON(!sta_priv->client);
49dcc819
DH		 3815 if (!sta_priv->asleep)
3816 break;
6ab10ff8 3817 sta_priv->asleep = false;
2a87c26b 3818 sta_id = iwl_sta_id(sta);
6ab10ff8
JB		 3819 if (sta_id != IWL_INVALID_STATION)
3820 iwl_sta_modify_ps_wake(priv, sta_id);
3821 break;
3822 default:
3823 break;
3824 }
3825}
3826
fe6b23dd
RC		 3827static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3828 struct ieee80211_vif *vif,
3829 struct ieee80211_sta *sta)
3830{
3831 struct iwl_priv *priv = hw->priv;
3832 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
a194e324 3833 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
eafdfbd3 3834 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
fe6b23dd
RC		 3835 int ret;
3836 u8 sta_id;
3837
3838 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3839 sta->addr);
da5ae1cf
RC		 3840 mutex_lock(&priv->mutex);
3841 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3842 sta->addr);
3843 sta_priv->common.sta_id = IWL_INVALID_STATION;
fe6b23dd
RC		 3844
3845 atomic_set(&sta_priv->pending_frames, 0);
3846 if (vif->type == NL80211_IFTYPE_AP)
3847 sta_priv->client = true;
3848
a194e324 3849 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
238d781d 3850 is_ap, sta, &sta_id);
fe6b23dd
RC		 3851 if (ret) {
3852 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3853 sta->addr, ret);
3854 /* Should we return success if return code is EEXIST ? */
da5ae1cf 3855 mutex_unlock(&priv->mutex);
fe6b23dd
RC		 3856 return ret;
3857 }
3858
fd1af15d
JB		 3859 sta_priv->common.sta_id = sta_id;
3860
fe6b23dd 3861 /* Initialize rate scaling */
91dd6c27 3862 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
fe6b23dd
RC		 3863 sta->addr);
3864 iwl_rs_rate_init(priv, sta, sta_id);
da5ae1cf 3865 mutex_unlock(&priv->mutex);
fe6b23dd 3866
fd1af15d 3867 return 0;
fe6b23dd
RC		 3868}
3869
79d07325
WYG		 3870static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
3871 struct ieee80211_channel_switch *ch_switch)
3872{
3873 struct iwl_priv *priv = hw->priv;
3874 const struct iwl_channel_info *ch_info;
3875 struct ieee80211_conf *conf = &hw->conf;
aa2dc6b5 3876 struct ieee80211_channel *channel = ch_switch->channel;
79d07325 3877 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
246ed355
JB		 3878 /*
3879 * MULTI-FIXME
3880 * When we add support for multiple interfaces, we need to
3881 * revisit this. The channel switch command in the device
3882 * only affects the BSS context, but what does that really
3883 * mean? And what if we get a CSA on the second interface?
3884 * This needs a lot of work.
3885 */
3886 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
79d07325
WYG		 3887 u16 ch;
3888 unsigned long flags = 0;
3889
3890 IWL_DEBUG_MAC80211(priv, "enter\n");
3891
3892 if (iwl_is_rfkill(priv))
3893 goto out_exit;
3894
3895 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3896 test_bit(STATUS_SCANNING, &priv->status))
3897 goto out_exit;
3898
246ed355 3899 if (!iwl_is_associated_ctx(ctx))
79d07325
WYG		 3900 goto out_exit;
3901
3902 /* channel switch in progress */
3903 if (priv->switch_rxon.switch_in_progress == true)
3904 goto out_exit;
3905
3906 mutex_lock(&priv->mutex);
3907 if (priv->cfg->ops->lib->set_channel_switch) {
3908
aa2dc6b5 3909 ch = channel->hw_value;
246ed355 3910 if (le16_to_cpu(ctx->active.channel) != ch) {
79d07325 3911 ch_info = iwl_get_channel_info(priv,
aa2dc6b5 3912 channel->band,
79d07325
WYG		 3913 ch);
3914 if (!is_channel_valid(ch_info)) {
3915 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3916 goto out;
3917 }
3918 spin_lock_irqsave(&priv->lock, flags);
3919
3920 priv->current_ht_config.smps = conf->smps_mode;
3921
3922 /* Configure HT40 channels */
7e6a5886
JB		 3923 ctx->ht.enabled = conf_is_ht(conf);
3924 if (ctx->ht.enabled) {
79d07325 3925 if (conf_is_ht40_minus(conf)) {
7e6a5886 3926 ctx->ht.extension_chan_offset =
79d07325 3927 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
7e6a5886 3928 ctx->ht.is_40mhz = true;
79d07325 3929 } else if (conf_is_ht40_plus(conf)) {
7e6a5886 3930 ctx->ht.extension_chan_offset =
79d07325 3931 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
7e6a5886 3932 ctx->ht.is_40mhz = true;
79d07325 3933 } else {
7e6a5886 3934 ctx->ht.extension_chan_offset =
79d07325 3935 IEEE80211_HT_PARAM_CHA_SEC_NONE;
7e6a5886 3936 ctx->ht.is_40mhz = false;
79d07325
WYG		 3937 }
3938 } else
7e6a5886 3939 ctx->ht.is_40mhz = false;
79d07325 3940
246ed355
JB		 3941 if ((le16_to_cpu(ctx->staging.channel) != ch))
3942 ctx->staging.flags = 0;
79d07325 3943
246ed355 3944 iwl_set_rxon_channel(priv, channel, ctx);
79d07325 3945 iwl_set_rxon_ht(priv, ht_conf);
246ed355 3946 iwl_set_flags_for_band(priv, ctx, channel->band,
8bd413e6 3947 ctx->vif);
79d07325
WYG		 3948 spin_unlock_irqrestore(&priv->lock, flags);
3949
3950 iwl_set_rate(priv);
3951 /*
3952 * at this point, staging_rxon has the
3953 * configuration for channel switch
3954 */
3955 if (priv->cfg->ops->lib->set_channel_switch(priv,
3956 ch_switch))
3957 priv->switch_rxon.switch_in_progress = false;
3958 }
3959 }
3960out:
3961 mutex_unlock(&priv->mutex);
3962out_exit:
3963 if (!priv->switch_rxon.switch_in_progress)
8bd413e6 3964 ieee80211_chswitch_done(ctx->vif, false);
79d07325
WYG		 3965 IWL_DEBUG_MAC80211(priv, "leave\n");
3966}
3967
8b8ab9d5
JB		 3968static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3969 unsigned int changed_flags,
3970 unsigned int *total_flags,
3971 u64 multicast)
3972{
3973 struct iwl_priv *priv = hw->priv;
3974 __le32 filter_or = 0, filter_nand = 0;
246ed355 3975 struct iwl_rxon_context *ctx;
8b8ab9d5
JB		 3976
3977#define CHK(test, flag) do { \
3978 if (*total_flags & (test)) \
3979 filter_or |= (flag); \
3980 else \
3981 filter_nand |= (flag); \
3982 } while (0)
3983
3984 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3985 changed_flags, *total_flags);
3986
3987 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3988 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
3989 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3990
3991#undef CHK
3992
3993 mutex_lock(&priv->mutex);
3994
246ed355
JB		 3995 for_each_context(priv, ctx) {
3996 ctx->staging.filter_flags &= ~filter_nand;
3997 ctx->staging.filter_flags |= filter_or;
3998 iwlcore_commit_rxon(priv, ctx);
3999 }
8b8ab9d5
JB		 4000
4001 mutex_unlock(&priv->mutex);
4002
4003 /*
4004 * Receiving all multicast frames is always enabled by the
4005 * default flags setup in iwl_connection_init_rx_config()
4006 * since we currently do not support programming multicast
4007 * filters into the device.
4008 */
4009 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
4010 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
4011}
4012
716c74b0
WYG		 4013static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
4014{
4015 struct iwl_priv *priv = hw->priv;
4016
4017 mutex_lock(&priv->mutex);
4018 IWL_DEBUG_MAC80211(priv, "enter\n");
4019
4020 /* do not support "flush" */
4021 if (!priv->cfg->ops->lib->txfifo_flush)
4022 goto done;
4023
4024 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
4025 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
4026 goto done;
4027 }
4028 if (iwl_is_rfkill(priv)) {
4029 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
4030 goto done;
4031 }
4032
4033 /*
4034 * mac80211 will not push any more frames for transmit
4035 * until the flush is completed
4036 */
4037 if (drop) {
4038 IWL_DEBUG_MAC80211(priv, "send flush command\n");
4039 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
4040 IWL_ERR(priv, "flush request fail\n");
4041 goto done;
4042 }
4043 }
4044 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
4045 iwlagn_wait_tx_queue_empty(priv);
4046done:
4047 mutex_unlock(&priv->mutex);
4048 IWL_DEBUG_MAC80211(priv, "leave\n");
4049}
4050
b481de9c
ZY		 4051/*****************************************************************************
4052 *
4053 * driver setup and teardown
4054 *
4055 *****************************************************************************/
4056
4e39317d 4057static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 4058{
d21050c7 4059 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY		 4060
4061 init_waitqueue_head(&priv->wait_command_queue);
4062
5b9f8cd3
EG		 4063 INIT_WORK(&priv->restart, iwl_bg_restart);
4064 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 4065 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 4066 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
65550636 4067 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
bee008b7 4068 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
fbba9410 4069 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
4a4a9e81
TW		 4070 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
4071 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 4072
2a421b91 4073 iwl_setup_scan_deferred_work(priv);
bb8c093b 4074
4e39317d
EG		 4075 if (priv->cfg->ops->lib->setup_deferred_work)
4076 priv->cfg->ops->lib->setup_deferred_work(priv);
4077
4078 init_timer(&priv->statistics_periodic);
4079 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 4080 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 4081
a9e1cb6a
WYG		 4082 init_timer(&priv->ucode_trace);
4083 priv->ucode_trace.data = (unsigned long)priv;
4084 priv->ucode_trace.function = iwl_bg_ucode_trace;
4085
b74e31a9
WYG		 4086 if (priv->cfg->ops->lib->recover_from_tx_stall) {
4087 init_timer(&priv->monitor_recover);
4088 priv->monitor_recover.data = (unsigned long)priv;
4089 priv->monitor_recover.function =
4090 priv->cfg->ops->lib->recover_from_tx_stall;
4091 }
4092
7cb1b088 4093 if (!priv->cfg->base_params->use_isr_legacy)
ef850d7c
MA		 4094 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4095 iwl_irq_tasklet, (unsigned long)priv);
4096 else
4097 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
4098 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY		 4099}
4100
4e39317d 4101static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 4102{
4e39317d
EG		 4103 if (priv->cfg->ops->lib->cancel_deferred_work)
4104 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 4105
3ae6a054 4106 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c 4107 cancel_delayed_work(&priv->alive_start);
815e629b 4108 cancel_work_sync(&priv->run_time_calib_work);
b481de9c 4109 cancel_work_sync(&priv->beacon_update);
e7e16b90
SG		 4110
4111 iwl_cancel_scan_deferred_work(priv);
4112
bee008b7 4113 cancel_work_sync(&priv->bt_full_concurrency);
fbba9410 4114 cancel_work_sync(&priv->bt_runtime_config);
e7e16b90 4115
4e39317d 4116 del_timer_sync(&priv->statistics_periodic);
a9e1cb6a 4117 del_timer_sync(&priv->ucode_trace);
b481de9c
ZY		 4118}
4119
89f186a8
RC		 4120static void iwl_init_hw_rates(struct iwl_priv *priv,
4121 struct ieee80211_rate *rates)
4122{
4123 int i;
4124
4125 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
4126 rates[i].bitrate = iwl_rates[i].ieee * 5;
4127 rates[i].hw_value = i; /* Rate scaling will work on indexes */
4128 rates[i].hw_value_short = i;
4129 rates[i].flags = 0;
4130 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
4131 /*
4132 * If CCK != 1M then set short preamble rate flag.
4133 */
4134 rates[i].flags |=
4135 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
4136 0 : IEEE80211_RATE_SHORT_PREAMBLE;
4137 }
4138 }
4139}
4140
4141static int iwl_init_drv(struct iwl_priv *priv)
4142{
4143 int ret;
4144
4145 priv->ibss_beacon = NULL;
4146
89f186a8
RC		 4147 spin_lock_init(&priv->sta_lock);
4148 spin_lock_init(&priv->hcmd_lock);
4149
4150 INIT_LIST_HEAD(&priv->free_frames);
4151
4152 mutex_init(&priv->mutex);
d2dfe6df 4153 mutex_init(&priv->sync_cmd_mutex);
89f186a8 4154
89f186a8
RC		 4155 priv->ieee_channels = NULL;
4156 priv->ieee_rates = NULL;
4157 priv->band = IEEE80211_BAND_2GHZ;
4158
4159 priv->iw_mode = NL80211_IFTYPE_STATION;
ba37a3d0 4160 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
a13d276f 4161 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
d5a0ffa3 4162 priv->_agn.agg_tids_count = 0;
89f186a8 4163
8a472da4
WYG		 4164 /* initialize force reset */
4165 priv->force_reset[IWL_RF_RESET].reset_duration =
4166 IWL_DELAY_NEXT_FORCE_RF_RESET;
4167 priv->force_reset[IWL_FW_RESET].reset_duration =
4168 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
89f186a8
RC		 4169
4170 /* Choose which receivers/antennas to use */
4171 if (priv->cfg->ops->hcmd->set_rxon_chain)
246ed355
JB		 4172 priv->cfg->ops->hcmd->set_rxon_chain(priv,
4173 &priv->contexts[IWL_RXON_CTX_BSS]);
89f186a8
RC		 4174
4175 iwl_init_scan_params(priv);
4176
22bf59a0 4177 /* init bt coex */
7cb1b088
WYG		 4178 if (priv->cfg->bt_params &&
4179 priv->cfg->bt_params->advanced_bt_coexist) {
b6e116e8
WYG		 4180 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
4181 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
4182 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
22bf59a0
WYG		 4183 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
4184 priv->bt_duration = BT_DURATION_LIMIT_DEF;
4185 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
4186 priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
4187 }
4188
89f186a8
RC		 4189 /* Set the tx_power_user_lmt to the lowest power level
4190 * this value will get overwritten by channel max power avg
4191 * from eeprom */
b744cb79 4192 priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
89f186a8
RC		 4193
4194 ret = iwl_init_channel_map(priv);
4195 if (ret) {
4196 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
4197 goto err;
4198 }
4199
4200 ret = iwlcore_init_geos(priv);
4201 if (ret) {
4202 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
4203 goto err_free_channel_map;
4204 }
4205 iwl_init_hw_rates(priv, priv->ieee_rates);
4206
4207 return 0;
4208
4209err_free_channel_map:
4210 iwl_free_channel_map(priv);
4211err:
4212 return ret;
4213}
4214
4215static void iwl_uninit_drv(struct iwl_priv *priv)
4216{
4217 iwl_calib_free_results(priv);
4218 iwlcore_free_geos(priv);
4219 iwl_free_channel_map(priv);
811ecc99 4220 kfree(priv->scan_cmd);
89f186a8
RC		 4221}
4222
5b9f8cd3
EG		 4223static struct ieee80211_ops iwl_hw_ops = {
4224 .tx = iwl_mac_tx,
4225 .start = iwl_mac_start,
4226 .stop = iwl_mac_stop,
4227 .add_interface = iwl_mac_add_interface,
4228 .remove_interface = iwl_mac_remove_interface,
4229 .config = iwl_mac_config,
8b8ab9d5 4230 .configure_filter = iwlagn_configure_filter,
5b9f8cd3
EG		 4231 .set_key = iwl_mac_set_key,
4232 .update_tkip_key = iwl_mac_update_tkip_key,
5b9f8cd3
EG		 4233 .conf_tx = iwl_mac_conf_tx,
4234 .reset_tsf = iwl_mac_reset_tsf,
4235 .bss_info_changed = iwl_bss_info_changed,
4236 .ampdu_action = iwl_mac_ampdu_action,
6ab10ff8
JB		 4237 .hw_scan = iwl_mac_hw_scan,
4238 .sta_notify = iwl_mac_sta_notify,
fe6b23dd
RC		 4239 .sta_add = iwlagn_mac_sta_add,
4240 .sta_remove = iwl_mac_sta_remove,
79d07325 4241 .channel_switch = iwl_mac_channel_switch,
716c74b0 4242 .flush = iwl_mac_flush,
a85d7cca 4243 .tx_last_beacon = iwl_mac_tx_last_beacon,
b481de9c
ZY		 4244};
4245
3867fe04
WYG		 4246static void iwl_hw_detect(struct iwl_priv *priv)
4247{
4248 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
4249 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
4250 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
49ded76b 4251 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
3867fe04
WYG		 4252}
4253
07d4f1ad
WYG		 4254static int iwl_set_hw_params(struct iwl_priv *priv)
4255{
4256 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4257 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4258 if (priv->cfg->mod_params->amsdu_size_8K)
4259 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4260 else
4261 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4262
4263 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4264
4265 if (priv->cfg->mod_params->disable_11n)
4266 priv->cfg->sku &= ~IWL_SKU_N;
4267
4268 /* Device-specific setup */
4269 return priv->cfg->ops->lib->set_hw_params(priv);
4270}
4271
e72f368b
JB		 4272static const u8 iwlagn_bss_ac_to_fifo[] = {
4273 IWL_TX_FIFO_VO,
4274 IWL_TX_FIFO_VI,
4275 IWL_TX_FIFO_BE,
4276 IWL_TX_FIFO_BK,
4277};
4278
4279static const u8 iwlagn_bss_ac_to_queue[] = {
4280 0, 1, 2, 3,
4281};
4282
4283static const u8 iwlagn_pan_ac_to_fifo[] = {
4284 IWL_TX_FIFO_VO_IPAN,
4285 IWL_TX_FIFO_VI_IPAN,
4286 IWL_TX_FIFO_BE_IPAN,
4287 IWL_TX_FIFO_BK_IPAN,
4288};
4289
4290static const u8 iwlagn_pan_ac_to_queue[] = {
4291 7, 6, 5, 4,
4292};
4293
5b9f8cd3 4294static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c 4295{
246ed355 4296 int err = 0, i;
c79dd5b5 4297 struct iwl_priv *priv;
b481de9c 4298 struct ieee80211_hw *hw;
82b9a121 4299 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 4300 unsigned long flags;
c6fa17ed 4301 u16 pci_cmd, num_mac;
b481de9c 4302
316c30d9
AK		 4303 /************************
4304 * 1. Allocating HW data
4305 ************************/
4306
6440adb5
CB		 4307 /* Disabling hardware scan means that mac80211 will perform scans
4308 * "the hard way", rather than using device's scan. */
1ea87396 4309 if (cfg->mod_params->disable_hw_scan) {
72645eff
WYG		 4310 dev_printk(KERN_DEBUG, &(pdev->dev),
4311 "sw scan support is deprecated\n");
5b9f8cd3 4312 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY		 4313 }
4314
5b9f8cd3 4315 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 4316 if (!hw) {
b481de9c
ZY		 4317 err = -ENOMEM;
4318 goto out;
4319 }
1d0a082d
AK		 4320 priv = hw->priv;
4321 /* At this point both hw and priv are allocated. */
4322
246ed355
JB		 4323 /*
4324 * The default context is always valid,
4325 * more may be discovered when firmware
4326 * is loaded.
4327 */
4328 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4329
4330 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4331 priv->contexts[i].ctxid = i;
4332
763cc3bf
JB		 4333 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4334 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
8f2d3d2a
JB		 4335 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4336 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4337 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
8dfdb9d5 4338 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
2995bafa 4339 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
c10afb6e 4340 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
e72f368b
JB		 4341 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4342 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
d0fe478c
JB		 4343 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4344 BIT(NL80211_IFTYPE_ADHOC);
4345 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4346 BIT(NL80211_IFTYPE_STATION);
4347 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4348 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4349 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
ece9c4ee
JB		 4350
4351 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4352 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4353 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4354 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4355 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4356 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4357 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4358 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
e72f368b
JB		 4359 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4360 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4361 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
d0fe478c
JB		 4362 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4363 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4364 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4365 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4366 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
ece9c4ee
JB		 4367
4368 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
8f2d3d2a 4369
b481de9c
ZY		 4370 SET_IEEE80211_DEV(hw, &pdev->dev);
4371
e1623446 4372 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 4373 priv->cfg = cfg;
b481de9c 4374 priv->pci_dev = pdev;
40cefda9 4375 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 4376
bee008b7
WYG		 4377 /* is antenna coupling more than 35dB ? */
4378 priv->bt_ant_couple_ok =
4379 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4380 true : false;
4381
f37837c9
WYG		 4382 /* enable/disable bt channel announcement */
4383 priv->bt_ch_announce = iwlagn_bt_ch_announce;
4384
20594eb0
WYG		 4385 if (iwl_alloc_traffic_mem(priv))
4386 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 4387
316c30d9
AK		 4388 /**************************
4389 * 2. Initializing PCI bus
4390 **************************/
1a7123cd
JL		 4391 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4392 PCIE_LINK_STATE_CLKPM);
4393
316c30d9
AK		 4394 if (pci_enable_device(pdev)) {
4395 err = -ENODEV;
4396 goto out_ieee80211_free_hw;
4397 }
4398
4399 pci_set_master(pdev);
4400
093d874c 4401 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 4402 if (!err)
093d874c 4403 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 4404 if (err) {
093d874c 4405 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4406 if (!err)
093d874c 4407 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 4408 /* both attempts failed: */
316c30d9 4409 if (err) {
978785a3 4410 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 4411 goto out_pci_disable_device;
cc2a8ea8 4412 }
316c30d9
AK		 4413 }
4414
4415 err = pci_request_regions(pdev, DRV_NAME);
4416 if (err)
4417 goto out_pci_disable_device;
4418
4419 pci_set_drvdata(pdev, priv);
4420
316c30d9
AK		 4421
4422 /***********************
4423 * 3. Read REV register
4424 ***********************/
4425 priv->hw_base = pci_iomap(pdev, 0, 0);
4426 if (!priv->hw_base) {
4427 err = -ENODEV;
4428 goto out_pci_release_regions;
4429 }
4430
e1623446 4431 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 4432 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 4433 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 4434
731a29b7 4435 /* these spin locks will be used in apm_ops.init and EEPROM access
a8b50a0a
MA		 4436 * we should init now
4437 */
4438 spin_lock_init(&priv->reg_lock);
731a29b7 4439 spin_lock_init(&priv->lock);
4843b5a7
RC		 4440
4441 /*
4442 * stop and reset the on-board processor just in case it is in a
4443 * strange state ... like being left stranded by a primary kernel
4444 * and this is now the kdump kernel trying to start up
4445 */
4446 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4447
b661c819 4448 iwl_hw_detect(priv);
c11362c0 4449 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
b661c819 4450 priv->cfg->name, priv->hw_rev);
316c30d9 4451
e7b63581
TW		 4452 /* We disable the RETRY_TIMEOUT register (0x41) to keep
4453 * PCI Tx retries from interfering with C3 CPU state */
4454 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4455
086ed117
MA		 4456 iwl_prepare_card_hw(priv);
4457 if (!priv->hw_ready) {
4458 IWL_WARN(priv, "Failed, HW not ready\n");
4459 goto out_iounmap;
4460 }
4461
91238714
TW		 4462 /*****************
4463 * 4. Read EEPROM
4464 *****************/
316c30d9
AK		 4465 /* Read the EEPROM */
4466 err = iwl_eeprom_init(priv);
4467 if (err) {
15b1687c 4468 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK		 4469 goto out_iounmap;
4470 }
8614f360
TW		 4471 err = iwl_eeprom_check_version(priv);
4472 if (err)
c8f16138 4473 goto out_free_eeprom;
8614f360 4474
02883017 4475 /* extract MAC Address */
c6fa17ed
WYG		 4476 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4477 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4478 priv->hw->wiphy->addresses = priv->addresses;
4479 priv->hw->wiphy->n_addresses = 1;
4480 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4481 if (num_mac > 1) {
4482 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4483 ETH_ALEN);
4484 priv->addresses[1].addr[5]++;
4485 priv->hw->wiphy->n_addresses++;
4486 }
316c30d9
AK		 4487
4488 /************************
4489 * 5. Setup HW constants
4490 ************************/
da154e30 4491 if (iwl_set_hw_params(priv)) {
15b1687c 4492 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 4493 goto out_free_eeprom;
316c30d9
AK		 4494 }
4495
4496 /*******************
6ba87956 4497 * 6. Setup priv
316c30d9 4498 *******************/
b481de9c 4499
6ba87956 4500 err = iwl_init_drv(priv);
bf85ea4f 4501 if (err)
399f4900 4502 goto out_free_eeprom;
bf85ea4f 4503 /* At this point both hw and priv are initialized. */
316c30d9 4504
316c30d9 4505 /********************
09f9bf79 4506 * 7. Setup services
316c30d9 4507 ********************/
0359facc 4508 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4509 iwl_disable_interrupts(priv);
0359facc 4510 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 4511
6cd0b1cb
HS		 4512 pci_enable_msi(priv->pci_dev);
4513
ef850d7c
MA		 4514 iwl_alloc_isr_ict(priv);
4515 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
4516 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS		 4517 if (err) {
4518 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4519 goto out_disable_msi;
4520 }
316c30d9 4521
4e39317d 4522 iwl_setup_deferred_work(priv);
653fa4a0 4523 iwl_setup_rx_handlers(priv);
316c30d9 4524
158bea07
JB		 4525 /*********************************************
4526 * 8. Enable interrupts and read RFKILL state
4527 *********************************************/
6ba87956 4528
6cd0b1cb
HS		 4529 /* enable interrupts if needed: hw bug w/a */
4530 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4531 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4532 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4533 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4534 }
4535
4536 iwl_enable_interrupts(priv);
4537
6cd0b1cb
HS		 4538 /* If platform's RF_KILL switch is NOT set to KILL */
4539 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4540 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4541 else
4542 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 4543
a60e77e5
JB		 4544 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4545 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 4546
58d0f361 4547 iwl_power_initialize(priv);
39b73fb1 4548 iwl_tt_initialize(priv);
158bea07 4549
a15707d8 4550 init_completion(&priv->_agn.firmware_loading_complete);
562db532 4551
b08dfd04 4552 err = iwl_request_firmware(priv, true);
158bea07 4553 if (err)
7d47618a 4554 goto out_destroy_workqueue;
158bea07 4555
b481de9c
ZY		 4556 return 0;
4557
7d47618a 4558 out_destroy_workqueue:
c8f16138
RC		 4559 destroy_workqueue(priv->workqueue);
4560 priv->workqueue = NULL;
795cc0ad 4561 free_irq(priv->pci_dev->irq, priv);
ef850d7c 4562 iwl_free_isr_ict(priv);
6cd0b1cb
HS		 4563 out_disable_msi:
4564 pci_disable_msi(priv->pci_dev);
6ba87956 4565 iwl_uninit_drv(priv);
073d3f5f
TW		 4566 out_free_eeprom:
4567 iwl_eeprom_free(priv);
b481de9c
ZY		 4568 out_iounmap:
4569 pci_iounmap(pdev, priv->hw_base);
4570 out_pci_release_regions:
316c30d9 4571 pci_set_drvdata(pdev, NULL);
623d563e 4572 pci_release_regions(pdev);
b481de9c
ZY		 4573 out_pci_disable_device:
4574 pci_disable_device(pdev);
b481de9c 4575 out_ieee80211_free_hw:
20594eb0 4576 iwl_free_traffic_mem(priv);
d7c76f4c 4577 ieee80211_free_hw(priv->hw);
b481de9c
ZY		 4578 out:
4579 return err;
4580}
4581
5b9f8cd3 4582static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 4583{
c79dd5b5 4584 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 4585 unsigned long flags;
b481de9c
ZY		 4586
4587 if (!priv)
4588 return;
4589
a15707d8 4590 wait_for_completion(&priv->_agn.firmware_loading_complete);
562db532 4591
e1623446 4592 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 4593
67249625 4594 iwl_dbgfs_unregister(priv);
5b9f8cd3 4595 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 4596
5b9f8cd3
EG		 4597 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4598 * to be called and iwl_down since we are removing the device
0b124c31
GG		 4599 * we need to set STATUS_EXIT_PENDING bit.
4600 */
4601 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR		 4602 if (priv->mac80211_registered) {
4603 ieee80211_unregister_hw(priv->hw);
4604 priv->mac80211_registered = 0;
0b124c31 4605 } else {
5b9f8cd3 4606 iwl_down(priv);
c4f55232
RR		 4607 }
4608
c166b25a
BC		 4609 /*
4610 * Make sure device is reset to low power before unloading driver.
4611 * This may be redundant with iwl_down(), but there are paths to
4612 * run iwl_down() without calling apm_ops.stop(), and there are
4613 * paths to avoid running iwl_down() at all before leaving driver.
4614 * This (inexpensive) call *makes sure* device is reset.
4615 */
4616 priv->cfg->ops->lib->apm_ops.stop(priv);
4617
39b73fb1
WYG		 4618 iwl_tt_exit(priv);
4619
0359facc
MA		 4620 /* make sure we flush any pending irq or
4621 * tasklet for the driver
4622 */
4623 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 4624 iwl_disable_interrupts(priv);
0359facc
MA		 4625 spin_unlock_irqrestore(&priv->lock, flags);
4626
4627 iwl_synchronize_irq(priv);
4628
5b9f8cd3 4629 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY		 4630
4631 if (priv->rxq.bd)
54b81550 4632 iwlagn_rx_queue_free(priv, &priv->rxq);
74bcdb33 4633 iwlagn_hw_txq_ctx_free(priv);
b481de9c 4634
073d3f5f 4635 iwl_eeprom_free(priv);
b481de9c 4636
b481de9c 4637
948c171c
MA		 4638 /*netif_stop_queue(dev); */
4639 flush_workqueue(priv->workqueue);
4640
5b9f8cd3 4641 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY		 4642 * priv->workqueue... so we can't take down the workqueue
4643 * until now... */
4644 destroy_workqueue(priv->workqueue);
4645 priv->workqueue = NULL;
20594eb0 4646 iwl_free_traffic_mem(priv);
b481de9c 4647
6cd0b1cb
HS		 4648 free_irq(priv->pci_dev->irq, priv);
4649 pci_disable_msi(priv->pci_dev);
b481de9c
ZY		 4650 pci_iounmap(pdev, priv->hw_base);
4651 pci_release_regions(pdev);
4652 pci_disable_device(pdev);
4653 pci_set_drvdata(pdev, NULL);
4654
6ba87956 4655 iwl_uninit_drv(priv);
b481de9c 4656
ef850d7c
MA		 4657 iwl_free_isr_ict(priv);
4658
b481de9c
ZY		 4659 if (priv->ibss_beacon)
4660 dev_kfree_skb(priv->ibss_beacon);
4661
4662 ieee80211_free_hw(priv->hw);
4663}
4664
b481de9c
ZY		 4665
4666/*****************************************************************************
4667 *
4668 * driver and module entry point
4669 *
4670 *****************************************************************************/
4671
fed9017e 4672/* Hardware specific file defines the PCI IDs table for that hardware module */
a3aa1884 4673static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4fc22b21 4674#ifdef CONFIG_IWL4965
fed9017e
RR		 4675 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4676 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 4677#endif /* CONFIG_IWL4965 */
5a6a256e 4678#ifdef CONFIG_IWL5000
ac592574
WYG		 4679/* 5100 Series WiFi */
4680 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4681 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4682 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4683 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4684 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4685 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4686 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4687 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4688 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4689 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4690 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4691 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4692 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4693 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4694 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4695 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4696 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4697 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4698 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4699 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4700 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4701 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4702 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4703 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4704
4705/* 5300 Series WiFi */
4706 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4707 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4708 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4709 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4710 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4711 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4712 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4713 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4714 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4715 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4716 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4717 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4718
4719/* 5350 Series WiFi/WiMax */
4720 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4721 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4722 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4723
4724/* 5150 Series Wifi/WiMax */
4725 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4726 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4727 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4728 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4729 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4730 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4731
4732 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4733 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4734 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4735 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
5953a62e
WYG		 4736
4737/* 6x00 Series */
5953a62e
WYG		 4738 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4739 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4740 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4741 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4742 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4743 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4744 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4745 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4746 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4747 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4b3e8062 4748
95b13014
SZ		 4749/* 6x00 Series Gen2a */
4750 {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
4751 {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
4752 {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
1808972f
SZ		 4753 {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
4754 {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
4755 {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
4756 {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
9f6e1baf
SZ		 4757 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
4758 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
4759 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
4760 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
4761 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
4762 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
4763 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
1808972f
SZ		 4764
4765/* 6x00 Series Gen2b */
4766 {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
4767 {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
4768 {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
4769 {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
4770 {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
4771 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4772 {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
4773 {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
4774 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4775 {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
4776 {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
9f6e1baf
SZ		 4777 {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
4778 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
4779 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
4780 {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
4781 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
4782 {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
4783 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
4784 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
4785 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
4786 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
4787 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
4788 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
4789 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
4790 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
4791 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
4792 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
4793 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
5953a62e
WYG		 4794
4795/* 6x50 WiFi/WiMax Series */
5953a62e
WYG		 4796 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4797 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4798 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4799 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
5953a62e
WYG		 4800 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4801 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4802
03264339
SZ		 4803/* 6x50 WiFi/WiMax Series Gen2 */
4804 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
4805 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
4806 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
4807 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
4808 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
4809 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
4810
77dcb6a9 4811/* 1000 Series WiFi */
4bd0914f
WYG		 4812 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4813 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4814 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4815 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4816 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4817 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4818 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4819 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4820 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4821 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4822 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4823 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
1de19ecc
JS		 4824
4825 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4826 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4827 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4828 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4829 {IWL_PCI_DEVICE(0x08AE, 0x1017, iwl100_bg_cfg)},
5a6a256e 4830#endif /* CONFIG_IWL5000 */
7100e924 4831
fed9017e
RR		 4832 {0}
4833};
4834MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4835
4836static struct pci_driver iwl_driver = {
b481de9c 4837 .name = DRV_NAME,
fed9017e 4838 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG		 4839 .probe = iwl_pci_probe,
4840 .remove = __devexit_p(iwl_pci_remove),
b481de9c 4841#ifdef CONFIG_PM
5b9f8cd3
EG		 4842 .suspend = iwl_pci_suspend,
4843 .resume = iwl_pci_resume,
b481de9c
ZY		 4844#endif
4845};
4846
5b9f8cd3 4847static int __init iwl_init(void)
b481de9c
ZY		 4848{
4849
4850 int ret;
c96c31e4
JP		 4851 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4852 pr_info(DRV_COPYRIGHT "\n");
897e1cf2 4853
e227ceac 4854 ret = iwlagn_rate_control_register();
897e1cf2 4855 if (ret) {
c96c31e4 4856 pr_err("Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC		 4857 return ret;
4858 }
4859
fed9017e 4860 ret = pci_register_driver(&iwl_driver);
b481de9c 4861 if (ret) {
c96c31e4 4862 pr_err("Unable to initialize PCI module\n");
897e1cf2 4863 goto error_register;
b481de9c 4864 }
b481de9c
ZY		 4865
4866 return ret;
897e1cf2 4867
897e1cf2 4868error_register:
e227ceac 4869 iwlagn_rate_control_unregister();
897e1cf2 4870 return ret;
b481de9c
ZY		 4871}
4872
5b9f8cd3 4873static void __exit iwl_exit(void)
b481de9c 4874{
fed9017e 4875 pci_unregister_driver(&iwl_driver);
e227ceac 4876 iwlagn_rate_control_unregister();
b481de9c
ZY		 4877}
4878
5b9f8cd3
EG		 4879module_exit(iwl_exit);
4880module_init(iwl_init);
a562a9dd
RC		 4881
4882#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 4883module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 4884MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 4885module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC		 4886MODULE_PARM_DESC(debug, "debug output mask");
4887#endif
4888
2b068618
WYG		 4889module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4890MODULE_PARM_DESC(swcrypto50,
4891 "using crypto in software (default 0 [hardware]) (deprecated)");
4892module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4893MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4894module_param_named(queues_num50,
4895 iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4896MODULE_PARM_DESC(queues_num50,
4897 "number of hw queues in 50xx series (deprecated)");
4898module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4899MODULE_PARM_DESC(queues_num, "number of hw queues.");
4900module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4901MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4902module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4903MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4904module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4905 int, S_IRUGO);
4906MODULE_PARM_DESC(amsdu_size_8K50,
4907 "enable 8K amsdu size in 50XX series (deprecated)");
4908module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4909 int, S_IRUGO);
4910MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4911module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4912MODULE_PARM_DESC(fw_restart50,
4913 "restart firmware in case of error (deprecated)");
4914module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4915MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4916module_param_named(
4917 disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
72645eff
WYG		 4918MODULE_PARM_DESC(disable_hw_scan,
4919 "disable hardware scanning (default 0) (deprecated)");
dd7a2509
JB		 4920
4921module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4922 S_IRUGO);
4923MODULE_PARM_DESC(ucode_alternative,
4924 "specify ucode alternative to use from ucode file");
bee008b7
WYG		 4925
4926module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4927MODULE_PARM_DESC(antenna_coupling,
4928 "specify antenna coupling in dB (defualt: 0 dB)");
f37837c9
WYG		 4929
4930module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
4931MODULE_PARM_DESC(bt_ch_announce,
4932 "Enable BT channel announcement mode (default: enable)");
Linux kernel - Deliverables
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