Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
c96c31e4 JP |
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
31 | ||
b481de9c ZY |
32 | #include <linux/kernel.h> |
33 | #include <linux/module.h> | |
b481de9c ZY |
34 | #include <linux/init.h> |
35 | #include <linux/pci.h> | |
1a7123cd | 36 | #include <linux/pci-aspm.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
b481de9c ZY |
38 | #include <linux/dma-mapping.h> |
39 | #include <linux/delay.h> | |
d43c36dc | 40 | #include <linux/sched.h> |
b481de9c ZY |
41 | #include <linux/skbuff.h> |
42 | #include <linux/netdevice.h> | |
43 | #include <linux/wireless.h> | |
44 | #include <linux/firmware.h> | |
b481de9c ZY |
45 | #include <linux/etherdevice.h> |
46 | #include <linux/if_arp.h> | |
47 | ||
b481de9c ZY |
48 | #include <net/mac80211.h> |
49 | ||
50 | #include <asm/div64.h> | |
51 | ||
a3139c59 SO |
52 | #define DRV_NAME "iwlagn" |
53 | ||
6bc913bd | 54 | #include "iwl-eeprom.h" |
3e0d4cb1 | 55 | #include "iwl-dev.h" |
fee1247a | 56 | #include "iwl-core.h" |
3395f6e9 | 57 | #include "iwl-io.h" |
b481de9c | 58 | #include "iwl-helpers.h" |
6974e363 | 59 | #include "iwl-sta.h" |
0de76736 | 60 | #include "iwl-agn-calib.h" |
a1175124 | 61 | #include "iwl-agn.h" |
5ed540ae | 62 | #include "iwl-agn-led.h" |
b481de9c | 63 | |
416e1438 | 64 | |
b481de9c ZY |
65 | /****************************************************************************** |
66 | * | |
67 | * module boiler plate | |
68 | * | |
69 | ******************************************************************************/ | |
70 | ||
b481de9c ZY |
71 | /* |
72 | * module name, copyright, version, etc. | |
b481de9c | 73 | */ |
d783b061 | 74 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 75 | |
0a6857e7 | 76 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
77 | #define VD "d" |
78 | #else | |
79 | #define VD | |
80 | #endif | |
81 | ||
81963d68 | 82 | #define DRV_VERSION IWLWIFI_VERSION VD |
b481de9c | 83 | |
b481de9c ZY |
84 | |
85 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
86 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 87 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 88 | MODULE_LICENSE("GPL"); |
4fc22b21 | 89 | MODULE_ALIAS("iwl4965"); |
b481de9c | 90 | |
bee008b7 | 91 | static int iwlagn_ant_coupling; |
f37837c9 | 92 | static bool iwlagn_bt_ch_announce = 1; |
bee008b7 | 93 | |
5b9f8cd3 | 94 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f | 95 | { |
246ed355 | 96 | struct iwl_rxon_context *ctx; |
5da4b55f | 97 | |
246ed355 JB |
98 | if (priv->cfg->ops->hcmd->set_rxon_chain) { |
99 | for_each_context(priv, ctx) { | |
100 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
6163a373 SZ |
101 | if (ctx->active.rx_chain != ctx->staging.rx_chain) |
102 | iwlcore_commit_rxon(priv, ctx); | |
246ed355 JB |
103 | } |
104 | } | |
5da4b55f MA |
105 | } |
106 | ||
fcab423d | 107 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
108 | { |
109 | struct list_head *element; | |
110 | ||
e1623446 | 111 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
112 | priv->frames_count); |
113 | ||
114 | while (!list_empty(&priv->free_frames)) { | |
115 | element = priv->free_frames.next; | |
116 | list_del(element); | |
fcab423d | 117 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
118 | priv->frames_count--; |
119 | } | |
120 | ||
121 | if (priv->frames_count) { | |
39aadf8c | 122 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
123 | priv->frames_count); |
124 | priv->frames_count = 0; | |
125 | } | |
126 | } | |
127 | ||
fcab423d | 128 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 129 | { |
fcab423d | 130 | struct iwl_frame *frame; |
b481de9c ZY |
131 | struct list_head *element; |
132 | if (list_empty(&priv->free_frames)) { | |
133 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
134 | if (!frame) { | |
15b1687c | 135 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
136 | return NULL; |
137 | } | |
138 | ||
139 | priv->frames_count++; | |
140 | return frame; | |
141 | } | |
142 | ||
143 | element = priv->free_frames.next; | |
144 | list_del(element); | |
fcab423d | 145 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
146 | } |
147 | ||
fcab423d | 148 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
149 | { |
150 | memset(frame, 0, sizeof(*frame)); | |
151 | list_add(&frame->list, &priv->free_frames); | |
152 | } | |
153 | ||
47ff65c4 | 154 | static u32 iwl_fill_beacon_frame(struct iwl_priv *priv, |
77834543 JB |
155 | struct ieee80211_hdr *hdr, |
156 | int left) | |
b481de9c | 157 | { |
77834543 JB |
158 | lockdep_assert_held(&priv->mutex); |
159 | ||
12e934dc | 160 | if (!priv->beacon_skb) |
b481de9c ZY |
161 | return 0; |
162 | ||
12e934dc | 163 | if (priv->beacon_skb->len > left) |
b481de9c ZY |
164 | return 0; |
165 | ||
12e934dc | 166 | memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len); |
b481de9c | 167 | |
12e934dc | 168 | return priv->beacon_skb->len; |
b481de9c ZY |
169 | } |
170 | ||
47ff65c4 DH |
171 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ |
172 | static void iwl_set_beacon_tim(struct iwl_priv *priv, | |
77834543 JB |
173 | struct iwl_tx_beacon_cmd *tx_beacon_cmd, |
174 | u8 *beacon, u32 frame_size) | |
47ff65c4 DH |
175 | { |
176 | u16 tim_idx; | |
177 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
178 | ||
179 | /* | |
180 | * The index is relative to frame start but we start looking at the | |
181 | * variable-length part of the beacon. | |
182 | */ | |
183 | tim_idx = mgmt->u.beacon.variable - beacon; | |
184 | ||
185 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
186 | while ((tim_idx < (frame_size - 2)) && | |
187 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
188 | tim_idx += beacon[tim_idx+1] + 2; | |
189 | ||
190 | /* If TIM field was found, set variables */ | |
191 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
192 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
193 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
194 | } else | |
195 | IWL_WARN(priv, "Unable to find TIM Element in beacon\n"); | |
196 | } | |
197 | ||
5b9f8cd3 | 198 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
47ff65c4 | 199 | struct iwl_frame *frame) |
4bf64efd TW |
200 | { |
201 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
47ff65c4 DH |
202 | u32 frame_size; |
203 | u32 rate_flags; | |
204 | u32 rate; | |
205 | /* | |
206 | * We have to set up the TX command, the TX Beacon command, and the | |
207 | * beacon contents. | |
208 | */ | |
4bf64efd | 209 | |
76d04815 JB |
210 | lockdep_assert_held(&priv->mutex); |
211 | ||
212 | if (!priv->beacon_ctx) { | |
213 | IWL_ERR(priv, "trying to build beacon w/o beacon context!\n"); | |
950094cb | 214 | return 0; |
76d04815 JB |
215 | } |
216 | ||
47ff65c4 | 217 | /* Initialize memory */ |
4bf64efd TW |
218 | tx_beacon_cmd = &frame->u.beacon; |
219 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
220 | ||
47ff65c4 | 221 | /* Set up TX beacon contents */ |
4bf64efd | 222 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, |
4bf64efd | 223 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
47ff65c4 DH |
224 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) |
225 | return 0; | |
40bbfd4c JB |
226 | if (!frame_size) |
227 | return 0; | |
4bf64efd | 228 | |
47ff65c4 | 229 | /* Set up TX command fields */ |
4bf64efd | 230 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); |
76d04815 | 231 | tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id; |
47ff65c4 DH |
232 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
233 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
234 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
4bf64efd | 235 | |
47ff65c4 DH |
236 | /* Set up TX beacon command fields */ |
237 | iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame, | |
77834543 | 238 | frame_size); |
4bf64efd | 239 | |
47ff65c4 | 240 | /* Set up packet rate and flags */ |
76d04815 | 241 | rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx); |
0e1654fa JB |
242 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant, |
243 | priv->hw_params.valid_tx_ant); | |
47ff65c4 DH |
244 | rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); |
245 | if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) | |
246 | rate_flags |= RATE_MCS_CCK_MSK; | |
247 | tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, | |
248 | rate_flags); | |
4bf64efd TW |
249 | |
250 | return sizeof(*tx_beacon_cmd) + frame_size; | |
251 | } | |
2295c66b JB |
252 | |
253 | int iwlagn_send_beacon_cmd(struct iwl_priv *priv) | |
b481de9c | 254 | { |
fcab423d | 255 | struct iwl_frame *frame; |
b481de9c ZY |
256 | unsigned int frame_size; |
257 | int rc; | |
b481de9c | 258 | |
fcab423d | 259 | frame = iwl_get_free_frame(priv); |
b481de9c | 260 | if (!frame) { |
15b1687c | 261 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
262 | "command.\n"); |
263 | return -ENOMEM; | |
264 | } | |
265 | ||
47ff65c4 DH |
266 | frame_size = iwl_hw_get_beacon_cmd(priv, frame); |
267 | if (!frame_size) { | |
268 | IWL_ERR(priv, "Error configuring the beacon command\n"); | |
269 | iwl_free_frame(priv, frame); | |
270 | return -EINVAL; | |
271 | } | |
b481de9c | 272 | |
857485c0 | 273 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
274 | &frame->u.cmd[0]); |
275 | ||
fcab423d | 276 | iwl_free_frame(priv, frame); |
b481de9c ZY |
277 | |
278 | return rc; | |
279 | } | |
280 | ||
7aaa1d79 SO |
281 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
282 | { | |
283 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
284 | ||
285 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
286 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
287 | addr |= | |
288 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
289 | ||
290 | return addr; | |
291 | } | |
292 | ||
293 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
294 | { | |
295 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
296 | ||
297 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
298 | } | |
299 | ||
300 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
301 | dma_addr_t addr, u16 len) | |
302 | { | |
303 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
304 | u16 hi_n_len = len << 4; | |
305 | ||
306 | put_unaligned_le32(addr, &tb->lo); | |
307 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
308 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
309 | ||
310 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
311 | ||
312 | tfd->num_tbs = idx + 1; | |
313 | } | |
314 | ||
315 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
316 | { | |
317 | return tfd->num_tbs & 0x1f; | |
318 | } | |
319 | ||
320 | /** | |
321 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
322 | * @priv - driver private data | |
323 | * @txq - tx queue | |
324 | * | |
325 | * Does NOT advance any TFD circular buffer read/write indexes | |
326 | * Does NOT free the TFD itself (which is within circular buffer) | |
327 | */ | |
328 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
329 | { | |
59606ffa | 330 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
331 | struct iwl_tfd *tfd; |
332 | struct pci_dev *dev = priv->pci_dev; | |
333 | int index = txq->q.read_ptr; | |
334 | int i; | |
335 | int num_tbs; | |
336 | ||
337 | tfd = &tfd_tmp[index]; | |
338 | ||
339 | /* Sanity check on number of chunks */ | |
340 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
341 | ||
342 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
343 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
344 | /* @todo issue fatal error, it is quite serious situation */ | |
345 | return; | |
346 | } | |
347 | ||
348 | /* Unmap tx_cmd */ | |
349 | if (num_tbs) | |
350 | pci_unmap_single(dev, | |
2e724443 FT |
351 | dma_unmap_addr(&txq->meta[index], mapping), |
352 | dma_unmap_len(&txq->meta[index], len), | |
96891cee | 353 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
354 | |
355 | /* Unmap chunks, if any. */ | |
ff0d91c3 | 356 | for (i = 1; i < num_tbs; i++) |
7aaa1d79 SO |
357 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), |
358 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
359 | ||
ff0d91c3 JB |
360 | /* free SKB */ |
361 | if (txq->txb) { | |
362 | struct sk_buff *skb; | |
6f80240e | 363 | |
ff0d91c3 | 364 | skb = txq->txb[txq->q.read_ptr].skb; |
6f80240e | 365 | |
ff0d91c3 JB |
366 | /* can be called from irqs-disabled context */ |
367 | if (skb) { | |
368 | dev_kfree_skb_any(skb); | |
369 | txq->txb[txq->q.read_ptr].skb = NULL; | |
7aaa1d79 SO |
370 | } |
371 | } | |
372 | } | |
373 | ||
374 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
375 | struct iwl_tx_queue *txq, | |
376 | dma_addr_t addr, u16 len, | |
377 | u8 reset, u8 pad) | |
378 | { | |
379 | struct iwl_queue *q; | |
59606ffa | 380 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
381 | u32 num_tbs; |
382 | ||
383 | q = &txq->q; | |
59606ffa SO |
384 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
385 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
386 | |
387 | if (reset) | |
388 | memset(tfd, 0, sizeof(*tfd)); | |
389 | ||
390 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
391 | ||
392 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
393 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
394 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
395 | IWL_NUM_OF_TBS); | |
396 | return -EINVAL; | |
397 | } | |
398 | ||
399 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
400 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
401 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
402 | (unsigned long long)addr); | |
403 | ||
404 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
a8e74e27 SO |
409 | /* |
410 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
411 | * given Tx queue, and enable the DMA channel used for that queue. | |
412 | * | |
413 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
414 | * channels supported in hardware. | |
415 | */ | |
416 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
417 | struct iwl_tx_queue *txq) | |
418 | { | |
a8e74e27 SO |
419 | int txq_id = txq->q.id; |
420 | ||
a8e74e27 SO |
421 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
422 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
423 | txq->q.dma_addr >> 8); | |
424 | ||
a8e74e27 SO |
425 | return 0; |
426 | } | |
427 | ||
b481de9c ZY |
428 | /****************************************************************************** |
429 | * | |
430 | * Generic RX handler implementations | |
431 | * | |
432 | ******************************************************************************/ | |
885ba202 TW |
433 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
434 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 435 | { |
2f301227 | 436 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
885ba202 | 437 | struct iwl_alive_resp *palive; |
b481de9c ZY |
438 | struct delayed_work *pwork; |
439 | ||
440 | palive = &pkt->u.alive_frame; | |
441 | ||
e1623446 | 442 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
443 | "0x%01X 0x%01X\n", |
444 | palive->is_valid, palive->ver_type, | |
445 | palive->ver_subtype); | |
446 | ||
447 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 448 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
449 | memcpy(&priv->card_alive_init, |
450 | &pkt->u.alive_frame, | |
885ba202 | 451 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
452 | pwork = &priv->init_alive_start; |
453 | } else { | |
e1623446 | 454 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 455 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 456 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
457 | pwork = &priv->alive_start; |
458 | } | |
459 | ||
460 | /* We delay the ALIVE response by 5ms to | |
461 | * give the HW RF Kill time to activate... */ | |
462 | if (palive->is_valid == UCODE_VALID_OK) | |
463 | queue_delayed_work(priv->workqueue, pwork, | |
464 | msecs_to_jiffies(5)); | |
10480b05 WYG |
465 | else { |
466 | IWL_WARN(priv, "%s uCode did not respond OK.\n", | |
467 | (palive->ver_subtype == INITIALIZE_SUBTYPE) ? | |
468 | "init" : "runtime"); | |
469 | queue_work(priv->workqueue, &priv->restart); | |
470 | } | |
b481de9c ZY |
471 | } |
472 | ||
5b9f8cd3 | 473 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 474 | { |
c79dd5b5 TW |
475 | struct iwl_priv *priv = |
476 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
477 | struct sk_buff *beacon; |
478 | ||
76d04815 JB |
479 | mutex_lock(&priv->mutex); |
480 | if (!priv->beacon_ctx) { | |
481 | IWL_ERR(priv, "updating beacon w/o beacon context!\n"); | |
482 | goto out; | |
483 | } | |
b481de9c | 484 | |
60744f62 JB |
485 | if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) { |
486 | /* | |
487 | * The ucode will send beacon notifications even in | |
488 | * IBSS mode, but we don't want to process them. But | |
489 | * we need to defer the type check to here due to | |
490 | * requiring locking around the beacon_ctx access. | |
491 | */ | |
492 | goto out; | |
493 | } | |
494 | ||
76d04815 JB |
495 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ |
496 | beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif); | |
b481de9c | 497 | if (!beacon) { |
77834543 | 498 | IWL_ERR(priv, "update beacon failed -- keeping old\n"); |
76d04815 | 499 | goto out; |
b481de9c ZY |
500 | } |
501 | ||
b481de9c | 502 | /* new beacon skb is allocated every time; dispose previous.*/ |
77834543 | 503 | dev_kfree_skb(priv->beacon_skb); |
b481de9c | 504 | |
12e934dc | 505 | priv->beacon_skb = beacon; |
b481de9c | 506 | |
2295c66b | 507 | iwlagn_send_beacon_cmd(priv); |
76d04815 JB |
508 | out: |
509 | mutex_unlock(&priv->mutex); | |
b481de9c ZY |
510 | } |
511 | ||
fbba9410 WYG |
512 | static void iwl_bg_bt_runtime_config(struct work_struct *work) |
513 | { | |
514 | struct iwl_priv *priv = | |
515 | container_of(work, struct iwl_priv, bt_runtime_config); | |
516 | ||
517 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
518 | return; | |
519 | ||
520 | /* dont send host command if rf-kill is on */ | |
521 | if (!iwl_is_ready_rf(priv)) | |
522 | return; | |
523 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
524 | } | |
525 | ||
bee008b7 WYG |
526 | static void iwl_bg_bt_full_concurrency(struct work_struct *work) |
527 | { | |
528 | struct iwl_priv *priv = | |
529 | container_of(work, struct iwl_priv, bt_full_concurrency); | |
246ed355 | 530 | struct iwl_rxon_context *ctx; |
bee008b7 WYG |
531 | |
532 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
533 | return; | |
534 | ||
535 | /* dont send host command if rf-kill is on */ | |
536 | if (!iwl_is_ready_rf(priv)) | |
537 | return; | |
538 | ||
539 | IWL_DEBUG_INFO(priv, "BT coex in %s mode\n", | |
540 | priv->bt_full_concurrent ? | |
541 | "full concurrency" : "3-wire"); | |
542 | ||
543 | /* | |
544 | * LQ & RXON updated cmds must be sent before BT Config cmd | |
545 | * to avoid 3-wire collisions | |
546 | */ | |
246ed355 JB |
547 | mutex_lock(&priv->mutex); |
548 | for_each_context(priv, ctx) { | |
549 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
550 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); | |
551 | iwlcore_commit_rxon(priv, ctx); | |
552 | } | |
553 | mutex_unlock(&priv->mutex); | |
bee008b7 WYG |
554 | |
555 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
556 | } | |
557 | ||
4e39317d | 558 | /** |
5b9f8cd3 | 559 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
560 | * |
561 | * This callback is provided in order to send a statistics request. | |
562 | * | |
563 | * This timer function is continually reset to execute within | |
564 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
565 | * was received. We need to ensure we receive the statistics in order | |
566 | * to update the temperature used for calibrating the TXPOWER. | |
567 | */ | |
5b9f8cd3 | 568 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
569 | { |
570 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
571 | ||
572 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
573 | return; | |
574 | ||
61780ee3 MA |
575 | /* dont send host command if rf-kill is on */ |
576 | if (!iwl_is_ready_rf(priv)) | |
577 | return; | |
578 | ||
ef8d5529 | 579 | iwl_send_statistics_request(priv, CMD_ASYNC, false); |
4e39317d EG |
580 | } |
581 | ||
a9e1cb6a WYG |
582 | |
583 | static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |
584 | u32 start_idx, u32 num_events, | |
585 | u32 mode) | |
586 | { | |
587 | u32 i; | |
588 | u32 ptr; /* SRAM byte address of log data */ | |
589 | u32 ev, time, data; /* event log data */ | |
590 | unsigned long reg_flags; | |
591 | ||
592 | if (mode == 0) | |
593 | ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); | |
594 | else | |
595 | ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); | |
596 | ||
597 | /* Make sure device is powered up for SRAM reads */ | |
598 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
599 | if (iwl_grab_nic_access(priv)) { | |
600 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
601 | return; | |
602 | } | |
603 | ||
604 | /* Set starting address; reads will auto-increment */ | |
605 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
606 | rmb(); | |
607 | ||
608 | /* | |
609 | * "time" is actually "data" for mode 0 (no timestamp). | |
610 | * place event id # at far right for easier visual parsing. | |
611 | */ | |
612 | for (i = 0; i < num_events; i++) { | |
613 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
614 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
615 | if (mode == 0) { | |
616 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
617 | 0, time, ev); | |
618 | } else { | |
619 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
620 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
621 | time, data, ev); | |
622 | } | |
623 | } | |
624 | /* Allow device to power down */ | |
625 | iwl_release_nic_access(priv); | |
626 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
627 | } | |
628 | ||
875295f1 | 629 | static void iwl_continuous_event_trace(struct iwl_priv *priv) |
a9e1cb6a WYG |
630 | { |
631 | u32 capacity; /* event log capacity in # entries */ | |
632 | u32 base; /* SRAM byte address of event log header */ | |
633 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
634 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
635 | u32 next_entry; /* index of next entry to be written by uCode */ | |
636 | ||
637 | if (priv->ucode_type == UCODE_INIT) | |
638 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
639 | else | |
640 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
641 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
642 | capacity = iwl_read_targ_mem(priv, base); | |
643 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
644 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
645 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
646 | } else | |
647 | return; | |
648 | ||
649 | if (num_wraps == priv->event_log.num_wraps) { | |
650 | iwl_print_cont_event_trace(priv, | |
651 | base, priv->event_log.next_entry, | |
652 | next_entry - priv->event_log.next_entry, | |
653 | mode); | |
654 | priv->event_log.non_wraps_count++; | |
655 | } else { | |
656 | if ((num_wraps - priv->event_log.num_wraps) > 1) | |
657 | priv->event_log.wraps_more_count++; | |
658 | else | |
659 | priv->event_log.wraps_once_count++; | |
660 | trace_iwlwifi_dev_ucode_wrap_event(priv, | |
661 | num_wraps - priv->event_log.num_wraps, | |
662 | next_entry, priv->event_log.next_entry); | |
663 | if (next_entry < priv->event_log.next_entry) { | |
664 | iwl_print_cont_event_trace(priv, base, | |
665 | priv->event_log.next_entry, | |
666 | capacity - priv->event_log.next_entry, | |
667 | mode); | |
668 | ||
669 | iwl_print_cont_event_trace(priv, base, 0, | |
670 | next_entry, mode); | |
671 | } else { | |
672 | iwl_print_cont_event_trace(priv, base, | |
673 | next_entry, capacity - next_entry, | |
674 | mode); | |
675 | ||
676 | iwl_print_cont_event_trace(priv, base, 0, | |
677 | next_entry, mode); | |
678 | } | |
679 | } | |
680 | priv->event_log.num_wraps = num_wraps; | |
681 | priv->event_log.next_entry = next_entry; | |
682 | } | |
683 | ||
684 | /** | |
685 | * iwl_bg_ucode_trace - Timer callback to log ucode event | |
686 | * | |
687 | * The timer is continually set to execute every | |
688 | * UCODE_TRACE_PERIOD milliseconds after the last timer expired | |
689 | * this function is to perform continuous uCode event logging operation | |
690 | * if enabled | |
691 | */ | |
692 | static void iwl_bg_ucode_trace(unsigned long data) | |
693 | { | |
694 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
695 | ||
696 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
697 | return; | |
698 | ||
699 | if (priv->event_log.ucode_trace) { | |
700 | iwl_continuous_event_trace(priv); | |
701 | /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */ | |
702 | mod_timer(&priv->ucode_trace, | |
703 | jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD)); | |
704 | } | |
705 | } | |
706 | ||
241887a2 JB |
707 | static void iwlagn_rx_beacon_notif(struct iwl_priv *priv, |
708 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 709 | { |
2f301227 | 710 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
241887a2 | 711 | struct iwlagn_beacon_notif *beacon = (void *)pkt->u.raw; |
a85d7cca | 712 | #ifdef CONFIG_IWLWIFI_DEBUG |
241887a2 | 713 | u16 status = le16_to_cpu(beacon->beacon_notify_hdr.status.status); |
e7d326ac | 714 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 715 | |
241887a2 JB |
716 | IWL_DEBUG_RX(priv, "beacon status %#x, retries:%d ibssmgr:%d " |
717 | "tsf:0x%.8x%.8x rate:%d\n", | |
718 | status & TX_STATUS_MSK, | |
b481de9c ZY |
719 | beacon->beacon_notify_hdr.failure_frame, |
720 | le32_to_cpu(beacon->ibss_mgr_status), | |
721 | le32_to_cpu(beacon->high_tsf), | |
722 | le32_to_cpu(beacon->low_tsf), rate); | |
723 | #endif | |
724 | ||
a85d7cca JB |
725 | priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); |
726 | ||
60744f62 | 727 | if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
728 | queue_work(priv->workqueue, &priv->beacon_update); |
729 | } | |
730 | ||
b481de9c ZY |
731 | /* Handle notification from uCode that card's power state is changing |
732 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 733 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 734 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 735 | { |
2f301227 | 736 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
b481de9c ZY |
737 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
738 | unsigned long status = priv->status; | |
739 | ||
3a41bbd5 | 740 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n", |
b481de9c | 741 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
3a41bbd5 WYG |
742 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", |
743 | (flags & CT_CARD_DISABLED) ? | |
744 | "Reached" : "Not reached"); | |
b481de9c ZY |
745 | |
746 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
3a41bbd5 | 747 | CT_CARD_DISABLED)) { |
b481de9c | 748 | |
3395f6e9 | 749 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
750 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
751 | ||
a8b50a0a MA |
752 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
753 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
754 | |
755 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 756 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 757 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 758 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c | 759 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
b481de9c | 760 | } |
3a41bbd5 | 761 | if (flags & CT_CARD_DISABLED) |
39b73fb1 | 762 | iwl_tt_enter_ct_kill(priv); |
b481de9c | 763 | } |
3a41bbd5 | 764 | if (!(flags & CT_CARD_DISABLED)) |
39b73fb1 | 765 | iwl_tt_exit_ct_kill(priv); |
b481de9c ZY |
766 | |
767 | if (flags & HW_CARD_DISABLED) | |
768 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
769 | else | |
770 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
771 | ||
772 | ||
b481de9c | 773 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 774 | iwl_scan_cancel(priv); |
b481de9c ZY |
775 | |
776 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
777 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
778 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
779 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
780 | else |
781 | wake_up_interruptible(&priv->wait_command_queue); | |
782 | } | |
783 | ||
65550636 WYG |
784 | static void iwl_bg_tx_flush(struct work_struct *work) |
785 | { | |
786 | struct iwl_priv *priv = | |
787 | container_of(work, struct iwl_priv, tx_flush); | |
788 | ||
789 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
790 | return; | |
791 | ||
792 | /* do nothing if rf-kill is on */ | |
793 | if (!iwl_is_ready_rf(priv)) | |
794 | return; | |
795 | ||
796 | if (priv->cfg->ops->lib->txfifo_flush) { | |
797 | IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n"); | |
798 | iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL); | |
799 | } | |
800 | } | |
801 | ||
b481de9c | 802 | /** |
5b9f8cd3 | 803 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
804 | * |
805 | * Setup the RX handlers for each of the reply types sent from the uCode | |
806 | * to the host. | |
807 | * | |
808 | * This function chains into the hardware specific files for them to setup | |
809 | * any hardware specific handlers as well. | |
810 | */ | |
653fa4a0 | 811 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 812 | { |
885ba202 | 813 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
814 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
815 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
81963d68 RC |
816 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
817 | iwl_rx_spectrum_measure_notif; | |
5b9f8cd3 | 818 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 819 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 | 820 | iwl_rx_pm_debug_statistics_notif; |
241887a2 | 821 | priv->rx_handlers[BEACON_NOTIFICATION] = iwlagn_rx_beacon_notif; |
b481de9c | 822 | |
9fbab516 BC |
823 | /* |
824 | * The same handler is used for both the REPLY to a discrete | |
825 | * statistics request from the host as well as for the periodic | |
826 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 827 | */ |
ef8d5529 | 828 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics; |
8f91aecb | 829 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; |
2a421b91 TW |
830 | |
831 | iwl_setup_rx_scan_handlers(priv); | |
832 | ||
37a44211 | 833 | /* status change handler */ |
5b9f8cd3 | 834 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 835 | |
c1354754 TW |
836 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
837 | iwl_rx_missed_beacon_notif; | |
37a44211 | 838 | /* Rx handlers */ |
8d801080 WYG |
839 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy; |
840 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx; | |
653fa4a0 | 841 | /* block ack */ |
74bcdb33 | 842 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba; |
9fbab516 | 843 | /* Set up hardware specific Rx handlers */ |
d4789efe | 844 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
845 | } |
846 | ||
b481de9c | 847 | /** |
a55360e4 | 848 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
849 | * |
850 | * Uses the priv->rx_handlers callback function array to invoke | |
851 | * the appropriate handlers, including command responses, | |
852 | * frame-received notifications, and other notifications. | |
853 | */ | |
f945f108 | 854 | static void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 855 | { |
a55360e4 | 856 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 857 | struct iwl_rx_packet *pkt; |
a55360e4 | 858 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
859 | u32 r, i; |
860 | int reclaim; | |
861 | unsigned long flags; | |
5c0eef96 | 862 | u8 fill_rx = 0; |
d68ab680 | 863 | u32 count = 8; |
4752c93c | 864 | int total_empty; |
b481de9c | 865 | |
6440adb5 CB |
866 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
867 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 868 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
869 | i = rxq->read; |
870 | ||
871 | /* Rx interrupt, but nothing sent from uCode */ | |
872 | if (i == r) | |
e1623446 | 873 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 874 | |
4752c93c | 875 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 876 | total_empty = r - rxq->write_actual; |
4752c93c MA |
877 | if (total_empty < 0) |
878 | total_empty += RX_QUEUE_SIZE; | |
879 | ||
880 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
881 | fill_rx = 1; |
882 | ||
b481de9c | 883 | while (i != r) { |
f4989d9b JB |
884 | int len; |
885 | ||
b481de9c ZY |
886 | rxb = rxq->queue[i]; |
887 | ||
9fbab516 | 888 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
889 | * then a bug has been introduced in the queue refilling |
890 | * routines -- catch it here */ | |
891 | BUG_ON(rxb == NULL); | |
892 | ||
893 | rxq->queue[i] = NULL; | |
894 | ||
2f301227 ZY |
895 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
896 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
897 | PCI_DMA_FROMDEVICE); | |
898 | pkt = rxb_addr(rxb); | |
b481de9c | 899 | |
f4989d9b JB |
900 | len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
901 | len += sizeof(u32); /* account for status word */ | |
902 | trace_iwlwifi_dev_rx(priv, pkt, len); | |
be1a71a1 | 903 | |
b481de9c ZY |
904 | /* Reclaim a command buffer only if this packet is a response |
905 | * to a (driver-originated) command. | |
906 | * If the packet (e.g. Rx frame) originated from uCode, | |
907 | * there is no command buffer to reclaim. | |
908 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
909 | * but apparently a few don't get set; catch them here. */ | |
910 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
911 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 912 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 913 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 914 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
915 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
916 | (pkt->hdr.cmd != REPLY_TX); | |
917 | ||
7194207c JB |
918 | /* |
919 | * Do the notification wait before RX handlers so | |
920 | * even if the RX handler consumes the RXB we have | |
921 | * access to it in the notification wait entry. | |
922 | */ | |
923 | if (!list_empty(&priv->_agn.notif_waits)) { | |
924 | struct iwl_notification_wait *w; | |
925 | ||
926 | spin_lock(&priv->_agn.notif_wait_lock); | |
927 | list_for_each_entry(w, &priv->_agn.notif_waits, list) { | |
928 | if (w->cmd == pkt->hdr.cmd) { | |
929 | w->triggered = true; | |
930 | if (w->fn) | |
931 | w->fn(priv, pkt); | |
932 | } | |
933 | } | |
934 | spin_unlock(&priv->_agn.notif_wait_lock); | |
935 | ||
936 | wake_up_all(&priv->_agn.notif_waitq); | |
937 | } | |
938 | ||
b481de9c ZY |
939 | /* Based on type of command response or notification, |
940 | * handle those that need handling via function in | |
5b9f8cd3 | 941 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 942 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 943 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 944 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
a83b9141 | 945 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 946 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
947 | } else { |
948 | /* No handling needed */ | |
e1623446 | 949 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
950 | "r %d i %d No handler needed for %s, 0x%02x\n", |
951 | r, i, get_cmd_string(pkt->hdr.cmd), | |
952 | pkt->hdr.cmd); | |
953 | } | |
954 | ||
29b1b268 ZY |
955 | /* |
956 | * XXX: After here, we should always check rxb->page | |
957 | * against NULL before touching it or its virtual | |
958 | * memory (pkt). Because some rx_handler might have | |
959 | * already taken or freed the pages. | |
960 | */ | |
961 | ||
b481de9c | 962 | if (reclaim) { |
2f301227 ZY |
963 | /* Invoke any callbacks, transfer the buffer to caller, |
964 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 965 | * as we reclaim the driver command queue */ |
29b1b268 | 966 | if (rxb->page) |
17b88929 | 967 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 968 | else |
39aadf8c | 969 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
970 | } |
971 | ||
7300515d ZY |
972 | /* Reuse the page if possible. For notification packets and |
973 | * SKBs that fail to Rx correctly, add them back into the | |
974 | * rx_free list for reuse later. */ | |
975 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 976 | if (rxb->page != NULL) { |
7300515d ZY |
977 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
978 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
979 | PCI_DMA_FROMDEVICE); | |
980 | list_add_tail(&rxb->list, &rxq->rx_free); | |
981 | rxq->free_count++; | |
982 | } else | |
983 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 984 | |
b481de9c | 985 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 986 | |
b481de9c | 987 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
988 | /* If there are a lot of unused frames, |
989 | * restock the Rx queue so ucode wont assert. */ | |
990 | if (fill_rx) { | |
991 | count++; | |
992 | if (count >= 8) { | |
7300515d | 993 | rxq->read = i; |
54b81550 | 994 | iwlagn_rx_replenish_now(priv); |
5c0eef96 MA |
995 | count = 0; |
996 | } | |
997 | } | |
b481de9c ZY |
998 | } |
999 | ||
1000 | /* Backtrack one entry */ | |
7300515d | 1001 | rxq->read = i; |
4752c93c | 1002 | if (fill_rx) |
54b81550 | 1003 | iwlagn_rx_replenish_now(priv); |
4752c93c | 1004 | else |
54b81550 | 1005 | iwlagn_rx_queue_restock(priv); |
a55360e4 | 1006 | } |
a55360e4 | 1007 | |
0359facc MA |
1008 | /* call this function to flush any scheduled tasklet */ |
1009 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
1010 | { | |
a96a27f9 | 1011 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1012 | synchronize_irq(priv->pci_dev->irq); |
1013 | tasklet_kill(&priv->irq_tasklet); | |
1014 | } | |
1015 | ||
ef850d7c | 1016 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
1017 | { |
1018 | u32 inta, handled = 0; | |
1019 | u32 inta_fh; | |
1020 | unsigned long flags; | |
c2e61da2 | 1021 | u32 i; |
0a6857e7 | 1022 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1023 | u32 inta_mask; |
1024 | #endif | |
1025 | ||
1026 | spin_lock_irqsave(&priv->lock, flags); | |
1027 | ||
1028 | /* Ack/clear/reset pending uCode interrupts. | |
1029 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1030 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
1031 | inta = iwl_read32(priv, CSR_INT); |
1032 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1033 | |
1034 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1035 | * Any new interrupts that happen after this, either while we're | |
1036 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
1037 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1038 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1039 | |
0a6857e7 | 1040 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1041 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1042 | /* just for debug */ |
3395f6e9 | 1043 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1044 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1045 | inta, inta_mask, inta_fh); |
1046 | } | |
1047 | #endif | |
1048 | ||
2f301227 ZY |
1049 | spin_unlock_irqrestore(&priv->lock, flags); |
1050 | ||
b481de9c ZY |
1051 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not |
1052 | * atomic, make sure that inta covers all the interrupts that | |
1053 | * we've discovered, even if FH interrupt came in just after | |
1054 | * reading CSR_INT. */ | |
6f83eaa1 | 1055 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 1056 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1057 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
1058 | inta |= CSR_INT_BIT_FH_TX; |
1059 | ||
1060 | /* Now service all interrupt bits discovered above. */ | |
1061 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1062 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1063 | |
1064 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 1065 | iwl_disable_interrupts(priv); |
b481de9c | 1066 | |
a83b9141 | 1067 | priv->isr_stats.hw++; |
5b9f8cd3 | 1068 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1069 | |
1070 | handled |= CSR_INT_BIT_HW_ERR; | |
1071 | ||
b481de9c ZY |
1072 | return; |
1073 | } | |
1074 | ||
0a6857e7 | 1075 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1076 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1077 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 1078 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1079 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1080 | "the frame/frames.\n"); |
a83b9141 WYG |
1081 | priv->isr_stats.sch++; |
1082 | } | |
b481de9c ZY |
1083 | |
1084 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 1085 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1086 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
1087 | priv->isr_stats.alive++; |
1088 | } | |
b481de9c ZY |
1089 | } |
1090 | #endif | |
1091 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1092 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1093 | |
9fbab516 | 1094 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
1095 | if (inta & CSR_INT_BIT_RF_KILL) { |
1096 | int hw_rf_kill = 0; | |
3395f6e9 | 1097 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
1098 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1099 | hw_rf_kill = 1; | |
1100 | ||
4c423a2b | 1101 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 1102 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 1103 | |
a83b9141 WYG |
1104 | priv->isr_stats.rfkill++; |
1105 | ||
a9efa652 | 1106 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
1107 | * the driver allows loading the ucode even if the radio |
1108 | * is killed. Hence update the killswitch state here. The | |
1109 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 1110 | */ |
6cd0b1cb HS |
1111 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
1112 | if (hw_rf_kill) | |
1113 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1114 | else | |
1115 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1116 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 1117 | } |
b481de9c ZY |
1118 | |
1119 | handled |= CSR_INT_BIT_RF_KILL; | |
1120 | } | |
1121 | ||
9fbab516 | 1122 | /* Chip got too hot and stopped itself */ |
b481de9c | 1123 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 1124 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 1125 | priv->isr_stats.ctkill++; |
b481de9c ZY |
1126 | handled |= CSR_INT_BIT_CT_KILL; |
1127 | } | |
1128 | ||
1129 | /* Error detected by uCode */ | |
1130 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1131 | IWL_ERR(priv, "Microcode SW error detected. " |
1132 | " Restarting 0x%X.\n", inta); | |
a83b9141 | 1133 | priv->isr_stats.sw++; |
5b9f8cd3 | 1134 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1135 | handled |= CSR_INT_BIT_SW_ERR; |
1136 | } | |
1137 | ||
c2e61da2 BC |
1138 | /* |
1139 | * uCode wakes up after power-down sleep. | |
1140 | * Tell device about any new tx or host commands enqueued, | |
1141 | * and about any Rx buffers made available while asleep. | |
1142 | */ | |
b481de9c | 1143 | if (inta & CSR_INT_BIT_WAKEUP) { |
e1623446 | 1144 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1145 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
c2e61da2 BC |
1146 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1147 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
a83b9141 | 1148 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1149 | handled |= CSR_INT_BIT_WAKEUP; |
1150 | } | |
1151 | ||
1152 | /* All uCode command responses, including Tx command responses, | |
1153 | * Rx "responses" (frame-received notification), and other | |
1154 | * notifications from uCode come through here*/ | |
1155 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1156 | iwl_rx_handle(priv); |
a83b9141 | 1157 | priv->isr_stats.rx++; |
b481de9c ZY |
1158 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1159 | } | |
1160 | ||
c72cd19f | 1161 | /* This "Tx" DMA channel is used only for loading uCode */ |
b481de9c | 1162 | if (inta & CSR_INT_BIT_FH_TX) { |
c72cd19f | 1163 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
a83b9141 | 1164 | priv->isr_stats.tx++; |
b481de9c | 1165 | handled |= CSR_INT_BIT_FH_TX; |
c72cd19f | 1166 | /* Wake up uCode load routine, now that load is complete */ |
dbb983b7 RR |
1167 | priv->ucode_write_complete = 1; |
1168 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1169 | } |
1170 | ||
a83b9141 | 1171 | if (inta & ~handled) { |
15b1687c | 1172 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1173 | priv->isr_stats.unhandled++; |
1174 | } | |
b481de9c | 1175 | |
40cefda9 | 1176 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1177 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1178 | inta & ~priv->inta_mask); |
39aadf8c | 1179 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1180 | } |
1181 | ||
1182 | /* Re-enable all interrupts */ | |
62e45c14 | 1183 | /* only Re-enable if disabled by irq */ |
0359facc | 1184 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) |
5b9f8cd3 | 1185 | iwl_enable_interrupts(priv); |
b481de9c | 1186 | |
0a6857e7 | 1187 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1188 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
3395f6e9 TW |
1189 | inta = iwl_read32(priv, CSR_INT); |
1190 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1191 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1192 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1193 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1194 | } | |
1195 | #endif | |
b481de9c ZY |
1196 | } |
1197 | ||
ef850d7c MA |
1198 | /* tasklet for iwlagn interrupt */ |
1199 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1200 | { | |
1201 | u32 inta = 0; | |
1202 | u32 handled = 0; | |
1203 | unsigned long flags; | |
8756990f | 1204 | u32 i; |
ef850d7c MA |
1205 | #ifdef CONFIG_IWLWIFI_DEBUG |
1206 | u32 inta_mask; | |
1207 | #endif | |
1208 | ||
1209 | spin_lock_irqsave(&priv->lock, flags); | |
1210 | ||
1211 | /* Ack/clear/reset pending uCode interrupts. | |
1212 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1213 | */ | |
48a6be6a SZ |
1214 | /* There is a hardware bug in the interrupt mask function that some |
1215 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
1216 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
1217 | * ICT interrupt handling mechanism has another bug that might cause | |
1218 | * these unmasked interrupts fail to be detected. We workaround the | |
1219 | * hardware bugs here by ACKing all the possible interrupts so that | |
1220 | * interrupt coalescing can still be achieved. | |
1221 | */ | |
4a35ecf8 | 1222 | iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask); |
ef850d7c | 1223 | |
a4c8b2a6 | 1224 | inta = priv->_agn.inta; |
ef850d7c MA |
1225 | |
1226 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1227 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
1228 | /* just for debug */ |
1229 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1230 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1231 | inta, inta_mask); | |
1232 | } | |
1233 | #endif | |
2f301227 ZY |
1234 | |
1235 | spin_unlock_irqrestore(&priv->lock, flags); | |
1236 | ||
a4c8b2a6 JB |
1237 | /* saved interrupt in inta variable now we can reset priv->_agn.inta */ |
1238 | priv->_agn.inta = 0; | |
ef850d7c MA |
1239 | |
1240 | /* Now service all interrupt bits discovered above. */ | |
1241 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1242 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
1243 | |
1244 | /* Tell the device to stop sending interrupts */ | |
1245 | iwl_disable_interrupts(priv); | |
1246 | ||
1247 | priv->isr_stats.hw++; | |
1248 | iwl_irq_handle_error(priv); | |
1249 | ||
1250 | handled |= CSR_INT_BIT_HW_ERR; | |
1251 | ||
ef850d7c MA |
1252 | return; |
1253 | } | |
1254 | ||
1255 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1256 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1257 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1258 | if (inta & CSR_INT_BIT_SCD) { | |
1259 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1260 | "the frame/frames.\n"); | |
1261 | priv->isr_stats.sch++; | |
1262 | } | |
1263 | ||
1264 | /* Alive notification via Rx interrupt will do the real work */ | |
1265 | if (inta & CSR_INT_BIT_ALIVE) { | |
1266 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1267 | priv->isr_stats.alive++; | |
1268 | } | |
1269 | } | |
1270 | #endif | |
1271 | /* Safely ignore these bits for debug checks below */ | |
1272 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1273 | ||
1274 | /* HW RF KILL switch toggled */ | |
1275 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1276 | int hw_rf_kill = 0; | |
1277 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1278 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1279 | hw_rf_kill = 1; | |
1280 | ||
4c423a2b | 1281 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
1282 | hw_rf_kill ? "disable radio" : "enable radio"); |
1283 | ||
1284 | priv->isr_stats.rfkill++; | |
1285 | ||
1286 | /* driver only loads ucode once setting the interface up. | |
1287 | * the driver allows loading the ucode even if the radio | |
1288 | * is killed. Hence update the killswitch state here. The | |
1289 | * rfkill handler will care about restarting if needed. | |
1290 | */ | |
1291 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1292 | if (hw_rf_kill) | |
1293 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1294 | else | |
1295 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1296 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1297 | } |
1298 | ||
1299 | handled |= CSR_INT_BIT_RF_KILL; | |
1300 | } | |
1301 | ||
1302 | /* Chip got too hot and stopped itself */ | |
1303 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1304 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1305 | priv->isr_stats.ctkill++; | |
1306 | handled |= CSR_INT_BIT_CT_KILL; | |
1307 | } | |
1308 | ||
1309 | /* Error detected by uCode */ | |
1310 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1311 | IWL_ERR(priv, "Microcode SW error detected. " | |
1312 | " Restarting 0x%X.\n", inta); | |
1313 | priv->isr_stats.sw++; | |
ef850d7c MA |
1314 | iwl_irq_handle_error(priv); |
1315 | handled |= CSR_INT_BIT_SW_ERR; | |
1316 | } | |
1317 | ||
1318 | /* uCode wakes up after power-down sleep */ | |
1319 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1320 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1321 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
8756990f BC |
1322 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1323 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
ef850d7c MA |
1324 | |
1325 | priv->isr_stats.wakeup++; | |
1326 | ||
1327 | handled |= CSR_INT_BIT_WAKEUP; | |
1328 | } | |
1329 | ||
1330 | /* All uCode command responses, including Tx command responses, | |
1331 | * Rx "responses" (frame-received notification), and other | |
1332 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1333 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1334 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1335 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1336 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1337 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1338 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1339 | CSR49_FH_INT_RX_MASK); | |
1340 | } | |
1341 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1342 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1343 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1344 | } | |
1345 | /* Sending RX interrupt require many steps to be done in the | |
1346 | * the device: | |
1347 | * 1- write interrupt to current index in ICT table. | |
1348 | * 2- dma RX frame. | |
1349 | * 3- update RX shared data to indicate last write index. | |
1350 | * 4- send interrupt. | |
1351 | * This could lead to RX race, driver could receive RX interrupt | |
74ba67ed BC |
1352 | * but the shared data changes does not reflect this; |
1353 | * periodic interrupt will detect any dangling Rx activity. | |
40cefda9 | 1354 | */ |
74ba67ed BC |
1355 | |
1356 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1357 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
40cefda9 | 1358 | CSR_INT_PERIODIC_DIS); |
ef850d7c | 1359 | iwl_rx_handle(priv); |
74ba67ed BC |
1360 | |
1361 | /* | |
1362 | * Enable periodic interrupt in 8 msec only if we received | |
1363 | * real RX interrupt (instead of just periodic int), to catch | |
1364 | * any dangling Rx interrupt. If it was just the periodic | |
1365 | * interrupt, there was no dangling Rx activity, and no need | |
1366 | * to extend the periodic interrupt; one-shot is enough. | |
1367 | */ | |
40cefda9 | 1368 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) |
74ba67ed | 1369 | iwl_write8(priv, CSR_INT_PERIODIC_REG, |
40cefda9 MA |
1370 | CSR_INT_PERIODIC_ENA); |
1371 | ||
ef850d7c | 1372 | priv->isr_stats.rx++; |
ef850d7c MA |
1373 | } |
1374 | ||
c72cd19f | 1375 | /* This "Tx" DMA channel is used only for loading uCode */ |
ef850d7c MA |
1376 | if (inta & CSR_INT_BIT_FH_TX) { |
1377 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
c72cd19f | 1378 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
ef850d7c MA |
1379 | priv->isr_stats.tx++; |
1380 | handled |= CSR_INT_BIT_FH_TX; | |
c72cd19f | 1381 | /* Wake up uCode load routine, now that load is complete */ |
ef850d7c MA |
1382 | priv->ucode_write_complete = 1; |
1383 | wake_up_interruptible(&priv->wait_command_queue); | |
1384 | } | |
1385 | ||
1386 | if (inta & ~handled) { | |
1387 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1388 | priv->isr_stats.unhandled++; | |
1389 | } | |
1390 | ||
40cefda9 | 1391 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1392 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1393 | inta & ~priv->inta_mask); |
ef850d7c MA |
1394 | } |
1395 | ||
ef850d7c | 1396 | /* Re-enable all interrupts */ |
62e45c14 | 1397 | /* only Re-enable if disabled by irq */ |
ef850d7c MA |
1398 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) |
1399 | iwl_enable_interrupts(priv); | |
ef850d7c MA |
1400 | } |
1401 | ||
872c8ddc WYG |
1402 | /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */ |
1403 | #define ACK_CNT_RATIO (50) | |
1404 | #define BA_TIMEOUT_CNT (5) | |
1405 | #define BA_TIMEOUT_MAX (16) | |
1406 | ||
1407 | /** | |
1408 | * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries. | |
1409 | * | |
1410 | * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding | |
1411 | * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal | |
1412 | * operation state. | |
1413 | */ | |
1414 | bool iwl_good_ack_health(struct iwl_priv *priv, | |
1415 | struct iwl_rx_packet *pkt) | |
1416 | { | |
1417 | bool rc = true; | |
1418 | int actual_ack_cnt_delta, expected_ack_cnt_delta; | |
1419 | int ba_timeout_delta; | |
1420 | ||
1421 | actual_ack_cnt_delta = | |
1422 | le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) - | |
f3aebeee | 1423 | le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt); |
872c8ddc WYG |
1424 | expected_ack_cnt_delta = |
1425 | le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) - | |
f3aebeee | 1426 | le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt); |
872c8ddc WYG |
1427 | ba_timeout_delta = |
1428 | le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) - | |
f3aebeee | 1429 | le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout); |
872c8ddc WYG |
1430 | if ((priv->_agn.agg_tids_count > 0) && |
1431 | (expected_ack_cnt_delta > 0) && | |
1432 | (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta) | |
1433 | < ACK_CNT_RATIO) && | |
1434 | (ba_timeout_delta > BA_TIMEOUT_CNT)) { | |
1435 | IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d," | |
1436 | " expected_ack_cnt = %d\n", | |
1437 | actual_ack_cnt_delta, expected_ack_cnt_delta); | |
1438 | ||
d73e4923 JB |
1439 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
1440 | /* | |
1441 | * This is ifdef'ed on DEBUGFS because otherwise the | |
1442 | * statistics aren't available. If DEBUGFS is set but | |
1443 | * DEBUG is not, these will just compile out. | |
1444 | */ | |
872c8ddc | 1445 | IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n", |
f3aebeee | 1446 | priv->_agn.delta_statistics.tx.rx_detected_cnt); |
872c8ddc WYG |
1447 | IWL_DEBUG_RADIO(priv, |
1448 | "ack_or_ba_timeout_collision delta = %d\n", | |
f3aebeee | 1449 | priv->_agn.delta_statistics.tx. |
872c8ddc WYG |
1450 | ack_or_ba_timeout_collision); |
1451 | #endif | |
1452 | IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n", | |
1453 | ba_timeout_delta); | |
1454 | if (!actual_ack_cnt_delta && | |
1455 | (ba_timeout_delta >= BA_TIMEOUT_MAX)) | |
1456 | rc = false; | |
1457 | } | |
1458 | return rc; | |
1459 | } | |
1460 | ||
a83b9141 | 1461 | |
7d47618a EG |
1462 | /***************************************************************************** |
1463 | * | |
1464 | * sysfs attributes | |
1465 | * | |
1466 | *****************************************************************************/ | |
1467 | ||
1468 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1469 | ||
1470 | /* | |
1471 | * The following adds a new attribute to the sysfs representation | |
1472 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) | |
1473 | * used for controlling the debug level. | |
1474 | * | |
1475 | * See the level definitions in iwl for details. | |
1476 | * | |
1477 | * The debug_level being managed using sysfs below is a per device debug | |
1478 | * level that is used instead of the global debug level if it (the per | |
1479 | * device debug level) is set. | |
1480 | */ | |
1481 | static ssize_t show_debug_level(struct device *d, | |
1482 | struct device_attribute *attr, char *buf) | |
1483 | { | |
1484 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1485 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
1486 | } | |
1487 | static ssize_t store_debug_level(struct device *d, | |
1488 | struct device_attribute *attr, | |
1489 | const char *buf, size_t count) | |
1490 | { | |
1491 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1492 | unsigned long val; | |
1493 | int ret; | |
1494 | ||
1495 | ret = strict_strtoul(buf, 0, &val); | |
1496 | if (ret) | |
1497 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); | |
1498 | else { | |
1499 | priv->debug_level = val; | |
1500 | if (iwl_alloc_traffic_mem(priv)) | |
1501 | IWL_ERR(priv, | |
1502 | "Not enough memory to generate traffic log\n"); | |
1503 | } | |
1504 | return strnlen(buf, count); | |
1505 | } | |
1506 | ||
1507 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, | |
1508 | show_debug_level, store_debug_level); | |
1509 | ||
1510 | ||
1511 | #endif /* CONFIG_IWLWIFI_DEBUG */ | |
1512 | ||
1513 | ||
1514 | static ssize_t show_temperature(struct device *d, | |
1515 | struct device_attribute *attr, char *buf) | |
1516 | { | |
1517 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1518 | ||
1519 | if (!iwl_is_alive(priv)) | |
1520 | return -EAGAIN; | |
1521 | ||
1522 | return sprintf(buf, "%d\n", priv->temperature); | |
1523 | } | |
1524 | ||
1525 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
1526 | ||
1527 | static ssize_t show_tx_power(struct device *d, | |
1528 | struct device_attribute *attr, char *buf) | |
1529 | { | |
1530 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1531 | ||
1532 | if (!iwl_is_ready_rf(priv)) | |
1533 | return sprintf(buf, "off\n"); | |
1534 | else | |
1535 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
1536 | } | |
1537 | ||
1538 | static ssize_t store_tx_power(struct device *d, | |
1539 | struct device_attribute *attr, | |
1540 | const char *buf, size_t count) | |
1541 | { | |
1542 | struct iwl_priv *priv = dev_get_drvdata(d); | |
1543 | unsigned long val; | |
1544 | int ret; | |
1545 | ||
1546 | ret = strict_strtoul(buf, 10, &val); | |
1547 | if (ret) | |
1548 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); | |
1549 | else { | |
1550 | ret = iwl_set_tx_power(priv, val, false); | |
1551 | if (ret) | |
1552 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
1553 | ret); | |
1554 | else | |
1555 | ret = count; | |
1556 | } | |
1557 | return ret; | |
1558 | } | |
1559 | ||
1560 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
1561 | ||
7d47618a EG |
1562 | static struct attribute *iwl_sysfs_entries[] = { |
1563 | &dev_attr_temperature.attr, | |
1564 | &dev_attr_tx_power.attr, | |
7d47618a EG |
1565 | #ifdef CONFIG_IWLWIFI_DEBUG |
1566 | &dev_attr_debug_level.attr, | |
1567 | #endif | |
1568 | NULL | |
1569 | }; | |
1570 | ||
1571 | static struct attribute_group iwl_attribute_group = { | |
1572 | .name = NULL, /* put in device directory */ | |
1573 | .attrs = iwl_sysfs_entries, | |
1574 | }; | |
1575 | ||
b481de9c ZY |
1576 | /****************************************************************************** |
1577 | * | |
1578 | * uCode download functions | |
1579 | * | |
1580 | ******************************************************************************/ | |
1581 | ||
5b9f8cd3 | 1582 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1583 | { |
98c92211 TW |
1584 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1585 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1586 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1587 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1588 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1589 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1590 | } |
1591 | ||
5b9f8cd3 | 1592 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1593 | { |
1594 | /* Remove all resets to allow NIC to operate */ | |
1595 | iwl_write32(priv, CSR_RESET, 0); | |
1596 | } | |
1597 | ||
dd7a2509 JB |
1598 | struct iwlagn_ucode_capabilities { |
1599 | u32 max_probe_length; | |
6a822d06 | 1600 | u32 standard_phy_calibration_size; |
ece9c4ee | 1601 | bool pan; |
dd7a2509 | 1602 | }; |
edcdf8b2 | 1603 | |
b08dfd04 | 1604 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
dd7a2509 JB |
1605 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
1606 | struct iwlagn_ucode_capabilities *capa); | |
b08dfd04 | 1607 | |
39396085 JS |
1608 | #define UCODE_EXPERIMENTAL_INDEX 100 |
1609 | #define UCODE_EXPERIMENTAL_TAG "exp" | |
1610 | ||
b08dfd04 JB |
1611 | static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) |
1612 | { | |
1613 | const char *name_pre = priv->cfg->fw_name_pre; | |
39396085 | 1614 | char tag[8]; |
b08dfd04 | 1615 | |
39396085 JS |
1616 | if (first) { |
1617 | #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE | |
1618 | priv->fw_index = UCODE_EXPERIMENTAL_INDEX; | |
1619 | strcpy(tag, UCODE_EXPERIMENTAL_TAG); | |
1620 | } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) { | |
1621 | #endif | |
b08dfd04 | 1622 | priv->fw_index = priv->cfg->ucode_api_max; |
39396085 JS |
1623 | sprintf(tag, "%d", priv->fw_index); |
1624 | } else { | |
b08dfd04 | 1625 | priv->fw_index--; |
39396085 JS |
1626 | sprintf(tag, "%d", priv->fw_index); |
1627 | } | |
b08dfd04 JB |
1628 | |
1629 | if (priv->fw_index < priv->cfg->ucode_api_min) { | |
1630 | IWL_ERR(priv, "no suitable firmware found!\n"); | |
1631 | return -ENOENT; | |
1632 | } | |
1633 | ||
39396085 | 1634 | sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); |
b08dfd04 | 1635 | |
39396085 JS |
1636 | IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n", |
1637 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
1638 | ? "EXPERIMENTAL " : "", | |
b08dfd04 JB |
1639 | priv->firmware_name); |
1640 | ||
1641 | return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, | |
1642 | &priv->pci_dev->dev, GFP_KERNEL, priv, | |
1643 | iwl_ucode_callback); | |
1644 | } | |
1645 | ||
0e9a44dc JB |
1646 | struct iwlagn_firmware_pieces { |
1647 | const void *inst, *data, *init, *init_data, *boot; | |
1648 | size_t inst_size, data_size, init_size, init_data_size, boot_size; | |
1649 | ||
1650 | u32 build; | |
b2e640d4 JB |
1651 | |
1652 | u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; | |
1653 | u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; | |
0e9a44dc JB |
1654 | }; |
1655 | ||
1656 | static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |
1657 | const struct firmware *ucode_raw, | |
1658 | struct iwlagn_firmware_pieces *pieces) | |
1659 | { | |
1660 | struct iwl_ucode_header *ucode = (void *)ucode_raw->data; | |
1661 | u32 api_ver, hdr_size; | |
1662 | const u8 *src; | |
1663 | ||
1664 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1665 | api_ver = IWL_UCODE_API(priv->ucode_ver); | |
1666 | ||
1667 | switch (api_ver) { | |
1668 | default: | |
1669 | /* | |
1670 | * 4965 doesn't revision the firmware file format | |
1671 | * along with the API version, it always uses v1 | |
1672 | * file format. | |
1673 | */ | |
1674 | if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) != | |
1675 | CSR_HW_REV_TYPE_4965) { | |
1676 | hdr_size = 28; | |
1677 | if (ucode_raw->size < hdr_size) { | |
1678 | IWL_ERR(priv, "File size too small!\n"); | |
1679 | return -EINVAL; | |
1680 | } | |
1681 | pieces->build = le32_to_cpu(ucode->u.v2.build); | |
1682 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | |
1683 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | |
1684 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | |
1685 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | |
1686 | pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size); | |
1687 | src = ucode->u.v2.data; | |
1688 | break; | |
1689 | } | |
1690 | /* fall through for 4965 */ | |
1691 | case 0: | |
1692 | case 1: | |
1693 | case 2: | |
1694 | hdr_size = 24; | |
1695 | if (ucode_raw->size < hdr_size) { | |
1696 | IWL_ERR(priv, "File size too small!\n"); | |
1697 | return -EINVAL; | |
1698 | } | |
1699 | pieces->build = 0; | |
1700 | pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size); | |
1701 | pieces->data_size = le32_to_cpu(ucode->u.v1.data_size); | |
1702 | pieces->init_size = le32_to_cpu(ucode->u.v1.init_size); | |
1703 | pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size); | |
1704 | pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size); | |
1705 | src = ucode->u.v1.data; | |
1706 | break; | |
1707 | } | |
1708 | ||
1709 | /* Verify size of file vs. image size info in file's header */ | |
1710 | if (ucode_raw->size != hdr_size + pieces->inst_size + | |
1711 | pieces->data_size + pieces->init_size + | |
1712 | pieces->init_data_size + pieces->boot_size) { | |
1713 | ||
1714 | IWL_ERR(priv, | |
1715 | "uCode file size %d does not match expected size\n", | |
1716 | (int)ucode_raw->size); | |
1717 | return -EINVAL; | |
1718 | } | |
1719 | ||
1720 | pieces->inst = src; | |
1721 | src += pieces->inst_size; | |
1722 | pieces->data = src; | |
1723 | src += pieces->data_size; | |
1724 | pieces->init = src; | |
1725 | src += pieces->init_size; | |
1726 | pieces->init_data = src; | |
1727 | src += pieces->init_data_size; | |
1728 | pieces->boot = src; | |
1729 | src += pieces->boot_size; | |
1730 | ||
1731 | return 0; | |
1732 | } | |
1733 | ||
dd7a2509 JB |
1734 | static int iwlagn_wanted_ucode_alternative = 1; |
1735 | ||
1736 | static int iwlagn_load_firmware(struct iwl_priv *priv, | |
1737 | const struct firmware *ucode_raw, | |
1738 | struct iwlagn_firmware_pieces *pieces, | |
1739 | struct iwlagn_ucode_capabilities *capa) | |
1740 | { | |
1741 | struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data; | |
1742 | struct iwl_ucode_tlv *tlv; | |
1743 | size_t len = ucode_raw->size; | |
1744 | const u8 *data; | |
1745 | int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp; | |
1746 | u64 alternatives; | |
ad8d8333 WYG |
1747 | u32 tlv_len; |
1748 | enum iwl_ucode_tlv_type tlv_type; | |
1749 | const u8 *tlv_data; | |
dd7a2509 | 1750 | |
ad8d8333 WYG |
1751 | if (len < sizeof(*ucode)) { |
1752 | IWL_ERR(priv, "uCode has invalid length: %zd\n", len); | |
dd7a2509 | 1753 | return -EINVAL; |
ad8d8333 | 1754 | } |
dd7a2509 | 1755 | |
ad8d8333 WYG |
1756 | if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) { |
1757 | IWL_ERR(priv, "invalid uCode magic: 0X%x\n", | |
1758 | le32_to_cpu(ucode->magic)); | |
dd7a2509 | 1759 | return -EINVAL; |
ad8d8333 | 1760 | } |
dd7a2509 JB |
1761 | |
1762 | /* | |
1763 | * Check which alternatives are present, and "downgrade" | |
1764 | * when the chosen alternative is not present, warning | |
1765 | * the user when that happens. Some files may not have | |
1766 | * any alternatives, so don't warn in that case. | |
1767 | */ | |
1768 | alternatives = le64_to_cpu(ucode->alternatives); | |
1769 | tmp = wanted_alternative; | |
1770 | if (wanted_alternative > 63) | |
1771 | wanted_alternative = 63; | |
1772 | while (wanted_alternative && !(alternatives & BIT(wanted_alternative))) | |
1773 | wanted_alternative--; | |
1774 | if (wanted_alternative && wanted_alternative != tmp) | |
1775 | IWL_WARN(priv, | |
1776 | "uCode alternative %d not available, choosing %d\n", | |
1777 | tmp, wanted_alternative); | |
1778 | ||
1779 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1780 | pieces->build = le32_to_cpu(ucode->build); | |
1781 | data = ucode->data; | |
1782 | ||
1783 | len -= sizeof(*ucode); | |
1784 | ||
704da534 | 1785 | while (len >= sizeof(*tlv)) { |
dd7a2509 | 1786 | u16 tlv_alt; |
dd7a2509 JB |
1787 | |
1788 | len -= sizeof(*tlv); | |
1789 | tlv = (void *)data; | |
1790 | ||
1791 | tlv_len = le32_to_cpu(tlv->length); | |
1792 | tlv_type = le16_to_cpu(tlv->type); | |
1793 | tlv_alt = le16_to_cpu(tlv->alternative); | |
1794 | tlv_data = tlv->data; | |
1795 | ||
ad8d8333 WYG |
1796 | if (len < tlv_len) { |
1797 | IWL_ERR(priv, "invalid TLV len: %zd/%u\n", | |
1798 | len, tlv_len); | |
dd7a2509 | 1799 | return -EINVAL; |
ad8d8333 | 1800 | } |
dd7a2509 JB |
1801 | len -= ALIGN(tlv_len, 4); |
1802 | data += sizeof(*tlv) + ALIGN(tlv_len, 4); | |
1803 | ||
1804 | /* | |
1805 | * Alternative 0 is always valid. | |
1806 | * | |
1807 | * Skip alternative TLVs that are not selected. | |
1808 | */ | |
1809 | if (tlv_alt != 0 && tlv_alt != wanted_alternative) | |
1810 | continue; | |
1811 | ||
1812 | switch (tlv_type) { | |
1813 | case IWL_UCODE_TLV_INST: | |
1814 | pieces->inst = tlv_data; | |
1815 | pieces->inst_size = tlv_len; | |
1816 | break; | |
1817 | case IWL_UCODE_TLV_DATA: | |
1818 | pieces->data = tlv_data; | |
1819 | pieces->data_size = tlv_len; | |
1820 | break; | |
1821 | case IWL_UCODE_TLV_INIT: | |
1822 | pieces->init = tlv_data; | |
1823 | pieces->init_size = tlv_len; | |
1824 | break; | |
1825 | case IWL_UCODE_TLV_INIT_DATA: | |
1826 | pieces->init_data = tlv_data; | |
1827 | pieces->init_data_size = tlv_len; | |
1828 | break; | |
1829 | case IWL_UCODE_TLV_BOOT: | |
1830 | pieces->boot = tlv_data; | |
1831 | pieces->boot_size = tlv_len; | |
1832 | break; | |
1833 | case IWL_UCODE_TLV_PROBE_MAX_LEN: | |
704da534 JB |
1834 | if (tlv_len != sizeof(u32)) |
1835 | goto invalid_tlv_len; | |
1836 | capa->max_probe_length = | |
ad8d8333 | 1837 | le32_to_cpup((__le32 *)tlv_data); |
dd7a2509 | 1838 | break; |
ece9c4ee JB |
1839 | case IWL_UCODE_TLV_PAN: |
1840 | if (tlv_len) | |
1841 | goto invalid_tlv_len; | |
1842 | capa->pan = true; | |
1843 | break; | |
b2e640d4 | 1844 | case IWL_UCODE_TLV_INIT_EVTLOG_PTR: |
704da534 JB |
1845 | if (tlv_len != sizeof(u32)) |
1846 | goto invalid_tlv_len; | |
1847 | pieces->init_evtlog_ptr = | |
ad8d8333 | 1848 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1849 | break; |
1850 | case IWL_UCODE_TLV_INIT_EVTLOG_SIZE: | |
704da534 JB |
1851 | if (tlv_len != sizeof(u32)) |
1852 | goto invalid_tlv_len; | |
1853 | pieces->init_evtlog_size = | |
ad8d8333 | 1854 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1855 | break; |
1856 | case IWL_UCODE_TLV_INIT_ERRLOG_PTR: | |
704da534 JB |
1857 | if (tlv_len != sizeof(u32)) |
1858 | goto invalid_tlv_len; | |
1859 | pieces->init_errlog_ptr = | |
ad8d8333 | 1860 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1861 | break; |
1862 | case IWL_UCODE_TLV_RUNT_EVTLOG_PTR: | |
704da534 JB |
1863 | if (tlv_len != sizeof(u32)) |
1864 | goto invalid_tlv_len; | |
1865 | pieces->inst_evtlog_ptr = | |
ad8d8333 | 1866 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1867 | break; |
1868 | case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE: | |
704da534 JB |
1869 | if (tlv_len != sizeof(u32)) |
1870 | goto invalid_tlv_len; | |
1871 | pieces->inst_evtlog_size = | |
ad8d8333 | 1872 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 JB |
1873 | break; |
1874 | case IWL_UCODE_TLV_RUNT_ERRLOG_PTR: | |
704da534 JB |
1875 | if (tlv_len != sizeof(u32)) |
1876 | goto invalid_tlv_len; | |
1877 | pieces->inst_errlog_ptr = | |
ad8d8333 | 1878 | le32_to_cpup((__le32 *)tlv_data); |
b2e640d4 | 1879 | break; |
c8312fac WYG |
1880 | case IWL_UCODE_TLV_ENHANCE_SENS_TBL: |
1881 | if (tlv_len) | |
704da534 JB |
1882 | goto invalid_tlv_len; |
1883 | priv->enhance_sensitivity_table = true; | |
c8312fac | 1884 | break; |
6a822d06 | 1885 | case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE: |
704da534 JB |
1886 | if (tlv_len != sizeof(u32)) |
1887 | goto invalid_tlv_len; | |
1888 | capa->standard_phy_calibration_size = | |
6a822d06 WYG |
1889 | le32_to_cpup((__le32 *)tlv_data); |
1890 | break; | |
dd7a2509 | 1891 | default: |
ad8d8333 | 1892 | IWL_WARN(priv, "unknown TLV: %d\n", tlv_type); |
dd7a2509 JB |
1893 | break; |
1894 | } | |
1895 | } | |
1896 | ||
ad8d8333 WYG |
1897 | if (len) { |
1898 | IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len); | |
1899 | iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len); | |
704da534 | 1900 | return -EINVAL; |
ad8d8333 | 1901 | } |
dd7a2509 | 1902 | |
704da534 JB |
1903 | return 0; |
1904 | ||
1905 | invalid_tlv_len: | |
1906 | IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len); | |
1907 | iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len); | |
1908 | ||
1909 | return -EINVAL; | |
dd7a2509 JB |
1910 | } |
1911 | ||
b481de9c | 1912 | /** |
b08dfd04 | 1913 | * iwl_ucode_callback - callback when firmware was loaded |
b481de9c | 1914 | * |
b08dfd04 JB |
1915 | * If loaded successfully, copies the firmware into buffers |
1916 | * for the card to fetch (via DMA). | |
b481de9c | 1917 | */ |
b08dfd04 | 1918 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) |
b481de9c | 1919 | { |
b08dfd04 | 1920 | struct iwl_priv *priv = context; |
cc0f555d | 1921 | struct iwl_ucode_header *ucode; |
0e9a44dc JB |
1922 | int err; |
1923 | struct iwlagn_firmware_pieces pieces; | |
a0987a8d RC |
1924 | const unsigned int api_max = priv->cfg->ucode_api_max; |
1925 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
0e9a44dc | 1926 | u32 api_ver; |
3e4de761 | 1927 | char buildstr[25]; |
0e9a44dc | 1928 | u32 build; |
dd7a2509 JB |
1929 | struct iwlagn_ucode_capabilities ucode_capa = { |
1930 | .max_probe_length = 200, | |
6a822d06 | 1931 | .standard_phy_calibration_size = |
642454cc | 1932 | IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE, |
dd7a2509 | 1933 | }; |
0e9a44dc JB |
1934 | |
1935 | memset(&pieces, 0, sizeof(pieces)); | |
b481de9c | 1936 | |
b08dfd04 | 1937 | if (!ucode_raw) { |
39396085 JS |
1938 | if (priv->fw_index <= priv->cfg->ucode_api_max) |
1939 | IWL_ERR(priv, | |
1940 | "request for firmware file '%s' failed.\n", | |
1941 | priv->firmware_name); | |
b08dfd04 | 1942 | goto try_again; |
b481de9c ZY |
1943 | } |
1944 | ||
b08dfd04 JB |
1945 | IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", |
1946 | priv->firmware_name, ucode_raw->size); | |
b481de9c | 1947 | |
22adba2a JB |
1948 | /* Make sure that we got at least the API version number */ |
1949 | if (ucode_raw->size < 4) { | |
15b1687c | 1950 | IWL_ERR(priv, "File size way too small!\n"); |
b08dfd04 | 1951 | goto try_again; |
b481de9c ZY |
1952 | } |
1953 | ||
1954 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1955 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1956 | |
0e9a44dc JB |
1957 | if (ucode->ver) |
1958 | err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces); | |
1959 | else | |
dd7a2509 JB |
1960 | err = iwlagn_load_firmware(priv, ucode_raw, &pieces, |
1961 | &ucode_capa); | |
22adba2a | 1962 | |
0e9a44dc JB |
1963 | if (err) |
1964 | goto try_again; | |
b481de9c | 1965 | |
a0987a8d | 1966 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
0e9a44dc | 1967 | build = pieces.build; |
a0987a8d | 1968 | |
0e9a44dc JB |
1969 | /* |
1970 | * api_ver should match the api version forming part of the | |
1971 | * firmware filename ... but we don't check for that and only rely | |
1972 | * on the API version read from firmware header from here on forward | |
1973 | */ | |
65cccfb0 WYG |
1974 | /* no api version check required for experimental uCode */ |
1975 | if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) { | |
1976 | if (api_ver < api_min || api_ver > api_max) { | |
1977 | IWL_ERR(priv, | |
1978 | "Driver unable to support your firmware API. " | |
1979 | "Driver supports v%u, firmware is v%u.\n", | |
1980 | api_max, api_ver); | |
1981 | goto try_again; | |
1982 | } | |
b08dfd04 | 1983 | |
65cccfb0 WYG |
1984 | if (api_ver != api_max) |
1985 | IWL_ERR(priv, | |
1986 | "Firmware has old API version. Expected v%u, " | |
1987 | "got v%u. New firmware can be obtained " | |
1988 | "from http://www.intellinuxwireless.org.\n", | |
1989 | api_max, api_ver); | |
1990 | } | |
a0987a8d | 1991 | |
3e4de761 | 1992 | if (build) |
39396085 JS |
1993 | sprintf(buildstr, " build %u%s", build, |
1994 | (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) | |
1995 | ? " (EXP)" : ""); | |
3e4de761 JB |
1996 | else |
1997 | buildstr[0] = '\0'; | |
1998 | ||
1999 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n", | |
2000 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
2001 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2002 | IWL_UCODE_API(priv->ucode_ver), | |
2003 | IWL_UCODE_SERIAL(priv->ucode_ver), | |
2004 | buildstr); | |
a0987a8d | 2005 | |
5ebeb5a6 RC |
2006 | snprintf(priv->hw->wiphy->fw_version, |
2007 | sizeof(priv->hw->wiphy->fw_version), | |
3e4de761 | 2008 | "%u.%u.%u.%u%s", |
5ebeb5a6 RC |
2009 | IWL_UCODE_MAJOR(priv->ucode_ver), |
2010 | IWL_UCODE_MINOR(priv->ucode_ver), | |
2011 | IWL_UCODE_API(priv->ucode_ver), | |
3e4de761 JB |
2012 | IWL_UCODE_SERIAL(priv->ucode_ver), |
2013 | buildstr); | |
b481de9c | 2014 | |
b08dfd04 JB |
2015 | /* |
2016 | * For any of the failures below (before allocating pci memory) | |
2017 | * we will try to load a version with a smaller API -- maybe the | |
2018 | * user just got a corrupted version of the latest API. | |
2019 | */ | |
2020 | ||
0e9a44dc JB |
2021 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
2022 | priv->ucode_ver); | |
2023 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n", | |
2024 | pieces.inst_size); | |
2025 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n", | |
2026 | pieces.data_size); | |
2027 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n", | |
2028 | pieces.init_size); | |
2029 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n", | |
2030 | pieces.init_data_size); | |
2031 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n", | |
2032 | pieces.boot_size); | |
b481de9c ZY |
2033 | |
2034 | /* Verify that uCode images will fit in card's SRAM */ | |
0e9a44dc JB |
2035 | if (pieces.inst_size > priv->hw_params.max_inst_size) { |
2036 | IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n", | |
2037 | pieces.inst_size); | |
b08dfd04 | 2038 | goto try_again; |
b481de9c ZY |
2039 | } |
2040 | ||
0e9a44dc JB |
2041 | if (pieces.data_size > priv->hw_params.max_data_size) { |
2042 | IWL_ERR(priv, "uCode data len %Zd too large to fit in\n", | |
2043 | pieces.data_size); | |
b08dfd04 | 2044 | goto try_again; |
b481de9c | 2045 | } |
0e9a44dc JB |
2046 | |
2047 | if (pieces.init_size > priv->hw_params.max_inst_size) { | |
2048 | IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n", | |
2049 | pieces.init_size); | |
b08dfd04 | 2050 | goto try_again; |
b481de9c | 2051 | } |
0e9a44dc JB |
2052 | |
2053 | if (pieces.init_data_size > priv->hw_params.max_data_size) { | |
2054 | IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n", | |
2055 | pieces.init_data_size); | |
b08dfd04 | 2056 | goto try_again; |
b481de9c | 2057 | } |
0e9a44dc JB |
2058 | |
2059 | if (pieces.boot_size > priv->hw_params.max_bsm_size) { | |
2060 | IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n", | |
2061 | pieces.boot_size); | |
b08dfd04 | 2062 | goto try_again; |
b481de9c ZY |
2063 | } |
2064 | ||
2065 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
2066 | ||
2067 | /* Runtime instructions and 2 copies of data: | |
2068 | * 1) unmodified from disk | |
2069 | * 2) backup cache for save/restore during power-downs */ | |
0e9a44dc | 2070 | priv->ucode_code.len = pieces.inst_size; |
98c92211 | 2071 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c | 2072 | |
0e9a44dc | 2073 | priv->ucode_data.len = pieces.data_size; |
98c92211 | 2074 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c | 2075 | |
0e9a44dc | 2076 | priv->ucode_data_backup.len = pieces.data_size; |
98c92211 | 2077 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 2078 | |
1f304e4e ZY |
2079 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
2080 | !priv->ucode_data_backup.v_addr) | |
2081 | goto err_pci_alloc; | |
2082 | ||
b481de9c | 2083 | /* Initialization instructions and data */ |
0e9a44dc JB |
2084 | if (pieces.init_size && pieces.init_data_size) { |
2085 | priv->ucode_init.len = pieces.init_size; | |
98c92211 | 2086 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 | 2087 | |
0e9a44dc | 2088 | priv->ucode_init_data.len = pieces.init_data_size; |
98c92211 | 2089 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
2090 | |
2091 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
2092 | goto err_pci_alloc; | |
2093 | } | |
b481de9c ZY |
2094 | |
2095 | /* Bootstrap (instructions only, no data) */ | |
0e9a44dc JB |
2096 | if (pieces.boot_size) { |
2097 | priv->ucode_boot.len = pieces.boot_size; | |
98c92211 | 2098 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 2099 | |
90e759d1 TW |
2100 | if (!priv->ucode_boot.v_addr) |
2101 | goto err_pci_alloc; | |
2102 | } | |
b481de9c | 2103 | |
b2e640d4 JB |
2104 | /* Now that we can no longer fail, copy information */ |
2105 | ||
2106 | /* | |
2107 | * The (size - 16) / 12 formula is based on the information recorded | |
2108 | * for each event, which is of mode 1 (including timestamp) for all | |
2109 | * new microcodes that include this information. | |
2110 | */ | |
2111 | priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr; | |
2112 | if (pieces.init_evtlog_size) | |
2113 | priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12; | |
2114 | else | |
7cb1b088 WYG |
2115 | priv->_agn.init_evtlog_size = |
2116 | priv->cfg->base_params->max_event_log_size; | |
b2e640d4 JB |
2117 | priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr; |
2118 | priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr; | |
2119 | if (pieces.inst_evtlog_size) | |
2120 | priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12; | |
2121 | else | |
7cb1b088 WYG |
2122 | priv->_agn.inst_evtlog_size = |
2123 | priv->cfg->base_params->max_event_log_size; | |
b2e640d4 JB |
2124 | priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; |
2125 | ||
ece9c4ee JB |
2126 | if (ucode_capa.pan) { |
2127 | priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN); | |
c10afb6e | 2128 | priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN; |
ece9c4ee JB |
2129 | } else |
2130 | priv->sta_key_max_num = STA_KEY_MAX_NUM; | |
c10afb6e | 2131 | |
b481de9c ZY |
2132 | /* Copy images into buffers for card's bus-master reads ... */ |
2133 | ||
2134 | /* Runtime instructions (first block of data in file) */ | |
0e9a44dc JB |
2135 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", |
2136 | pieces.inst_size); | |
2137 | memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size); | |
cc0f555d | 2138 | |
e1623446 | 2139 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
2140 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
2141 | ||
0e9a44dc JB |
2142 | /* |
2143 | * Runtime data | |
2144 | * NOTE: Copy into backup buffer will be done in iwl_up() | |
2145 | */ | |
2146 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", | |
2147 | pieces.data_size); | |
2148 | memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size); | |
2149 | memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size); | |
2150 | ||
2151 | /* Initialization instructions */ | |
2152 | if (pieces.init_size) { | |
e1623446 | 2153 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
0e9a44dc JB |
2154 | pieces.init_size); |
2155 | memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size); | |
b481de9c ZY |
2156 | } |
2157 | ||
0e9a44dc JB |
2158 | /* Initialization data */ |
2159 | if (pieces.init_data_size) { | |
e1623446 | 2160 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
0e9a44dc JB |
2161 | pieces.init_data_size); |
2162 | memcpy(priv->ucode_init_data.v_addr, pieces.init_data, | |
2163 | pieces.init_data_size); | |
b481de9c ZY |
2164 | } |
2165 | ||
0e9a44dc JB |
2166 | /* Bootstrap instructions */ |
2167 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", | |
2168 | pieces.boot_size); | |
2169 | memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size); | |
b481de9c | 2170 | |
6a822d06 WYG |
2171 | /* |
2172 | * figure out the offset of chain noise reset and gain commands | |
2173 | * base on the size of standard phy calibration commands table size | |
2174 | */ | |
2175 | if (ucode_capa.standard_phy_calibration_size > | |
2176 | IWL_MAX_PHY_CALIBRATE_TBL_SIZE) | |
2177 | ucode_capa.standard_phy_calibration_size = | |
2178 | IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE; | |
2179 | ||
2180 | priv->_agn.phy_calib_chain_noise_reset_cmd = | |
2181 | ucode_capa.standard_phy_calibration_size; | |
2182 | priv->_agn.phy_calib_chain_noise_gain_cmd = | |
2183 | ucode_capa.standard_phy_calibration_size + 1; | |
2184 | ||
b08dfd04 JB |
2185 | /************************************************** |
2186 | * This is still part of probe() in a sense... | |
2187 | * | |
2188 | * 9. Setup and register with mac80211 and debugfs | |
2189 | **************************************************/ | |
dd7a2509 | 2190 | err = iwl_mac_setup_register(priv, &ucode_capa); |
b08dfd04 JB |
2191 | if (err) |
2192 | goto out_unbind; | |
2193 | ||
2194 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
2195 | if (err) | |
2196 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
2197 | ||
7d47618a EG |
2198 | err = sysfs_create_group(&priv->pci_dev->dev.kobj, |
2199 | &iwl_attribute_group); | |
2200 | if (err) { | |
2201 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); | |
2202 | goto out_unbind; | |
2203 | } | |
2204 | ||
b481de9c ZY |
2205 | /* We have our copies now, allow OS release its copies */ |
2206 | release_firmware(ucode_raw); | |
a15707d8 | 2207 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 JB |
2208 | return; |
2209 | ||
2210 | try_again: | |
2211 | /* try next, if any */ | |
2212 | if (iwl_request_firmware(priv, false)) | |
2213 | goto out_unbind; | |
2214 | release_firmware(ucode_raw); | |
2215 | return; | |
b481de9c ZY |
2216 | |
2217 | err_pci_alloc: | |
15b1687c | 2218 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
5b9f8cd3 | 2219 | iwl_dealloc_ucode_pci(priv); |
b08dfd04 | 2220 | out_unbind: |
a15707d8 | 2221 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 | 2222 | device_release_driver(&priv->pci_dev->dev); |
b481de9c | 2223 | release_firmware(ucode_raw); |
b481de9c ZY |
2224 | } |
2225 | ||
b7a79404 RC |
2226 | static const char *desc_lookup_text[] = { |
2227 | "OK", | |
2228 | "FAIL", | |
2229 | "BAD_PARAM", | |
2230 | "BAD_CHECKSUM", | |
2231 | "NMI_INTERRUPT_WDG", | |
2232 | "SYSASSERT", | |
2233 | "FATAL_ERROR", | |
2234 | "BAD_COMMAND", | |
2235 | "HW_ERROR_TUNE_LOCK", | |
2236 | "HW_ERROR_TEMPERATURE", | |
2237 | "ILLEGAL_CHAN_FREQ", | |
2238 | "VCC_NOT_STABLE", | |
2239 | "FH_ERROR", | |
2240 | "NMI_INTERRUPT_HOST", | |
2241 | "NMI_INTERRUPT_ACTION_PT", | |
2242 | "NMI_INTERRUPT_UNKNOWN", | |
2243 | "UCODE_VERSION_MISMATCH", | |
2244 | "HW_ERROR_ABS_LOCK", | |
2245 | "HW_ERROR_CAL_LOCK_FAIL", | |
2246 | "NMI_INTERRUPT_INST_ACTION_PT", | |
2247 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
2248 | "NMI_TRM_HW_ER", | |
2249 | "NMI_INTERRUPT_TRM", | |
2250 | "NMI_INTERRUPT_BREAK_POINT" | |
2251 | "DEBUG_0", | |
2252 | "DEBUG_1", | |
2253 | "DEBUG_2", | |
2254 | "DEBUG_3", | |
b7a79404 RC |
2255 | }; |
2256 | ||
4b58645c JS |
2257 | static struct { char *name; u8 num; } advanced_lookup[] = { |
2258 | { "NMI_INTERRUPT_WDG", 0x34 }, | |
2259 | { "SYSASSERT", 0x35 }, | |
2260 | { "UCODE_VERSION_MISMATCH", 0x37 }, | |
2261 | { "BAD_COMMAND", 0x38 }, | |
2262 | { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C }, | |
2263 | { "FATAL_ERROR", 0x3D }, | |
2264 | { "NMI_TRM_HW_ERR", 0x46 }, | |
2265 | { "NMI_INTERRUPT_TRM", 0x4C }, | |
2266 | { "NMI_INTERRUPT_BREAK_POINT", 0x54 }, | |
2267 | { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C }, | |
2268 | { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 }, | |
2269 | { "NMI_INTERRUPT_HOST", 0x66 }, | |
2270 | { "NMI_INTERRUPT_ACTION_PT", 0x7C }, | |
2271 | { "NMI_INTERRUPT_UNKNOWN", 0x84 }, | |
2272 | { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 }, | |
2273 | { "ADVANCED_SYSASSERT", 0 }, | |
2274 | }; | |
2275 | ||
2276 | static const char *desc_lookup(u32 num) | |
b7a79404 | 2277 | { |
4b58645c JS |
2278 | int i; |
2279 | int max = ARRAY_SIZE(desc_lookup_text); | |
b7a79404 | 2280 | |
4b58645c JS |
2281 | if (num < max) |
2282 | return desc_lookup_text[num]; | |
b7a79404 | 2283 | |
4b58645c JS |
2284 | max = ARRAY_SIZE(advanced_lookup) - 1; |
2285 | for (i = 0; i < max; i++) { | |
2286 | if (advanced_lookup[i].num == num) | |
2287 | break;; | |
2288 | } | |
2289 | return advanced_lookup[i].name; | |
b7a79404 RC |
2290 | } |
2291 | ||
2292 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
2293 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
2294 | ||
2295 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
2296 | { | |
2297 | u32 data2, line; | |
2298 | u32 desc, time, count, base, data1; | |
2299 | u32 blink1, blink2, ilink1, ilink2; | |
461ef382 | 2300 | u32 pc, hcmd; |
b7a79404 | 2301 | |
b2e640d4 | 2302 | if (priv->ucode_type == UCODE_INIT) { |
b7a79404 | 2303 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); |
b2e640d4 JB |
2304 | if (!base) |
2305 | base = priv->_agn.init_errlog_ptr; | |
2306 | } else { | |
b7a79404 | 2307 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); |
b2e640d4 JB |
2308 | if (!base) |
2309 | base = priv->_agn.inst_errlog_ptr; | |
2310 | } | |
b7a79404 RC |
2311 | |
2312 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2313 | IWL_ERR(priv, |
2314 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
2315 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
b7a79404 RC |
2316 | return; |
2317 | } | |
2318 | ||
2319 | count = iwl_read_targ_mem(priv, base); | |
2320 | ||
2321 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
2322 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
2323 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
2324 | priv->status, count); | |
2325 | } | |
2326 | ||
2327 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
6e6ebf4b | 2328 | priv->isr_stats.err_code = desc; |
461ef382 | 2329 | pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32)); |
b7a79404 RC |
2330 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); |
2331 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
2332 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
2333 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
2334 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
2335 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
2336 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
2337 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
461ef382 | 2338 | hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32)); |
b7a79404 | 2339 | |
be1a71a1 JB |
2340 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line, |
2341 | blink1, blink2, ilink1, ilink2); | |
2342 | ||
87563715 | 2343 | IWL_ERR(priv, "Desc Time " |
b7a79404 | 2344 | "data1 data2 line\n"); |
87563715 | 2345 | IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", |
b7a79404 | 2346 | desc_lookup(desc), desc, time, data1, data2, line); |
461ef382 WYG |
2347 | IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n"); |
2348 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", | |
2349 | pc, blink1, blink2, ilink1, ilink2, hcmd); | |
b7a79404 RC |
2350 | } |
2351 | ||
2352 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
2353 | ||
2354 | /** | |
2355 | * iwl_print_event_log - Dump error event log to syslog | |
2356 | * | |
2357 | */ | |
b03d7d0f WYG |
2358 | static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
2359 | u32 num_events, u32 mode, | |
2360 | int pos, char **buf, size_t bufsz) | |
b7a79404 RC |
2361 | { |
2362 | u32 i; | |
2363 | u32 base; /* SRAM byte address of event log header */ | |
2364 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
2365 | u32 ptr; /* SRAM byte address of log data */ | |
2366 | u32 ev, time, data; /* event log data */ | |
e5854471 | 2367 | unsigned long reg_flags; |
b7a79404 RC |
2368 | |
2369 | if (num_events == 0) | |
b03d7d0f | 2370 | return pos; |
b2e640d4 JB |
2371 | |
2372 | if (priv->ucode_type == UCODE_INIT) { | |
b7a79404 | 2373 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
b2e640d4 JB |
2374 | if (!base) |
2375 | base = priv->_agn.init_evtlog_ptr; | |
2376 | } else { | |
b7a79404 | 2377 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); |
b2e640d4 JB |
2378 | if (!base) |
2379 | base = priv->_agn.inst_evtlog_ptr; | |
2380 | } | |
b7a79404 RC |
2381 | |
2382 | if (mode == 0) | |
2383 | event_size = 2 * sizeof(u32); | |
2384 | else | |
2385 | event_size = 3 * sizeof(u32); | |
2386 | ||
2387 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
2388 | ||
e5854471 BC |
2389 | /* Make sure device is powered up for SRAM reads */ |
2390 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
2391 | iwl_grab_nic_access(priv); | |
2392 | ||
2393 | /* Set starting address; reads will auto-increment */ | |
2394 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
2395 | rmb(); | |
2396 | ||
b7a79404 RC |
2397 | /* "time" is actually "data" for mode 0 (no timestamp). |
2398 | * place event id # at far right for easier visual parsing. */ | |
2399 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
2400 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
2401 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
b7a79404 RC |
2402 | if (mode == 0) { |
2403 | /* data, ev */ | |
b03d7d0f WYG |
2404 | if (bufsz) { |
2405 | pos += scnprintf(*buf + pos, bufsz - pos, | |
2406 | "EVT_LOG:0x%08x:%04u\n", | |
2407 | time, ev); | |
2408 | } else { | |
2409 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
2410 | time, ev); | |
2411 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", | |
2412 | time, ev); | |
2413 | } | |
b7a79404 | 2414 | } else { |
e5854471 | 2415 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
2416 | if (bufsz) { |
2417 | pos += scnprintf(*buf + pos, bufsz - pos, | |
2418 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
2419 | time, data, ev); | |
2420 | } else { | |
2421 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
b7a79404 | 2422 | time, data, ev); |
b03d7d0f WYG |
2423 | trace_iwlwifi_dev_ucode_event(priv, time, |
2424 | data, ev); | |
2425 | } | |
b7a79404 RC |
2426 | } |
2427 | } | |
e5854471 BC |
2428 | |
2429 | /* Allow device to power down */ | |
2430 | iwl_release_nic_access(priv); | |
2431 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 2432 | return pos; |
b7a79404 RC |
2433 | } |
2434 | ||
c341ddb2 WYG |
2435 | /** |
2436 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
2437 | */ | |
b03d7d0f WYG |
2438 | static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
2439 | u32 num_wraps, u32 next_entry, | |
2440 | u32 size, u32 mode, | |
2441 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
2442 | { |
2443 | /* | |
2444 | * display the newest DEFAULT_LOG_ENTRIES entries | |
2445 | * i.e the entries just before the next ont that uCode would fill. | |
2446 | */ | |
2447 | if (num_wraps) { | |
2448 | if (next_entry < size) { | |
b03d7d0f WYG |
2449 | pos = iwl_print_event_log(priv, |
2450 | capacity - (size - next_entry), | |
2451 | size - next_entry, mode, | |
2452 | pos, buf, bufsz); | |
2453 | pos = iwl_print_event_log(priv, 0, | |
2454 | next_entry, mode, | |
2455 | pos, buf, bufsz); | |
c341ddb2 | 2456 | } else |
b03d7d0f WYG |
2457 | pos = iwl_print_event_log(priv, next_entry - size, |
2458 | size, mode, pos, buf, bufsz); | |
c341ddb2 | 2459 | } else { |
b03d7d0f WYG |
2460 | if (next_entry < size) { |
2461 | pos = iwl_print_event_log(priv, 0, next_entry, | |
2462 | mode, pos, buf, bufsz); | |
2463 | } else { | |
2464 | pos = iwl_print_event_log(priv, next_entry - size, | |
2465 | size, mode, pos, buf, bufsz); | |
2466 | } | |
c341ddb2 | 2467 | } |
b03d7d0f | 2468 | return pos; |
c341ddb2 WYG |
2469 | } |
2470 | ||
c341ddb2 WYG |
2471 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) |
2472 | ||
b03d7d0f WYG |
2473 | int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
2474 | char **buf, bool display) | |
b7a79404 RC |
2475 | { |
2476 | u32 base; /* SRAM byte address of event log header */ | |
2477 | u32 capacity; /* event log capacity in # entries */ | |
2478 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
2479 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
2480 | u32 next_entry; /* index of next entry to be written by uCode */ | |
2481 | u32 size; /* # entries that we'll print */ | |
b2e640d4 | 2482 | u32 logsize; |
b03d7d0f WYG |
2483 | int pos = 0; |
2484 | size_t bufsz = 0; | |
b7a79404 | 2485 | |
b2e640d4 | 2486 | if (priv->ucode_type == UCODE_INIT) { |
b7a79404 | 2487 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
b2e640d4 JB |
2488 | logsize = priv->_agn.init_evtlog_size; |
2489 | if (!base) | |
2490 | base = priv->_agn.init_evtlog_ptr; | |
2491 | } else { | |
b7a79404 | 2492 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); |
b2e640d4 JB |
2493 | logsize = priv->_agn.inst_evtlog_size; |
2494 | if (!base) | |
2495 | base = priv->_agn.inst_evtlog_ptr; | |
2496 | } | |
b7a79404 RC |
2497 | |
2498 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2499 | IWL_ERR(priv, |
2500 | "Invalid event log pointer 0x%08X for %s uCode\n", | |
2501 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
937c397e | 2502 | return -EINVAL; |
b7a79404 RC |
2503 | } |
2504 | ||
2505 | /* event log header */ | |
2506 | capacity = iwl_read_targ_mem(priv, base); | |
2507 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
2508 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
2509 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
2510 | ||
b2e640d4 | 2511 | if (capacity > logsize) { |
84c40692 | 2512 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", |
b2e640d4 JB |
2513 | capacity, logsize); |
2514 | capacity = logsize; | |
84c40692 BC |
2515 | } |
2516 | ||
b2e640d4 | 2517 | if (next_entry > logsize) { |
84c40692 | 2518 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", |
b2e640d4 JB |
2519 | next_entry, logsize); |
2520 | next_entry = logsize; | |
84c40692 BC |
2521 | } |
2522 | ||
b7a79404 RC |
2523 | size = num_wraps ? capacity : next_entry; |
2524 | ||
2525 | /* bail out if nothing in log */ | |
2526 | if (size == 0) { | |
2527 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
b03d7d0f | 2528 | return pos; |
b7a79404 RC |
2529 | } |
2530 | ||
9f28ebc3 | 2531 | /* enable/disable bt channel inhibition */ |
f37837c9 WYG |
2532 | priv->bt_ch_announce = iwlagn_bt_ch_announce; |
2533 | ||
c341ddb2 | 2534 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 2535 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
2536 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
2537 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2538 | #else | |
2539 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
2540 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2541 | #endif | |
2542 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n", | |
2543 | size); | |
b7a79404 | 2544 | |
c341ddb2 | 2545 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
2546 | if (display) { |
2547 | if (full_log) | |
2548 | bufsz = capacity * 48; | |
2549 | else | |
2550 | bufsz = size * 48; | |
2551 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
2552 | if (!*buf) | |
937c397e | 2553 | return -ENOMEM; |
b03d7d0f | 2554 | } |
c341ddb2 WYG |
2555 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
2556 | /* | |
2557 | * if uCode has wrapped back to top of log, | |
2558 | * start at the oldest entry, | |
2559 | * i.e the next one that uCode would fill. | |
2560 | */ | |
2561 | if (num_wraps) | |
b03d7d0f WYG |
2562 | pos = iwl_print_event_log(priv, next_entry, |
2563 | capacity - next_entry, mode, | |
2564 | pos, buf, bufsz); | |
c341ddb2 | 2565 | /* (then/else) start at top of log */ |
b03d7d0f WYG |
2566 | pos = iwl_print_event_log(priv, 0, |
2567 | next_entry, mode, pos, buf, bufsz); | |
c341ddb2 | 2568 | } else |
b03d7d0f WYG |
2569 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2570 | next_entry, size, mode, | |
2571 | pos, buf, bufsz); | |
c341ddb2 | 2572 | #else |
b03d7d0f WYG |
2573 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2574 | next_entry, size, mode, | |
2575 | pos, buf, bufsz); | |
b7a79404 | 2576 | #endif |
b03d7d0f | 2577 | return pos; |
c341ddb2 | 2578 | } |
b7a79404 | 2579 | |
0975cc8f WYG |
2580 | static void iwl_rf_kill_ct_config(struct iwl_priv *priv) |
2581 | { | |
2582 | struct iwl_ct_kill_config cmd; | |
2583 | struct iwl_ct_kill_throttling_config adv_cmd; | |
2584 | unsigned long flags; | |
2585 | int ret = 0; | |
2586 | ||
2587 | spin_lock_irqsave(&priv->lock, flags); | |
2588 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
2589 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); | |
2590 | spin_unlock_irqrestore(&priv->lock, flags); | |
2591 | priv->thermal_throttle.ct_kill_toggle = false; | |
2592 | ||
7cb1b088 | 2593 | if (priv->cfg->base_params->support_ct_kill_exit) { |
0975cc8f WYG |
2594 | adv_cmd.critical_temperature_enter = |
2595 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
2596 | adv_cmd.critical_temperature_exit = | |
2597 | cpu_to_le32(priv->hw_params.ct_kill_exit_threshold); | |
2598 | ||
2599 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
2600 | sizeof(adv_cmd), &adv_cmd); | |
2601 | if (ret) | |
2602 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2603 | else | |
2604 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2605 | "succeeded, " | |
2606 | "critical temperature enter is %d," | |
2607 | "exit is %d\n", | |
2608 | priv->hw_params.ct_kill_threshold, | |
2609 | priv->hw_params.ct_kill_exit_threshold); | |
2610 | } else { | |
2611 | cmd.critical_temperature_R = | |
2612 | cpu_to_le32(priv->hw_params.ct_kill_threshold); | |
2613 | ||
2614 | ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD, | |
2615 | sizeof(cmd), &cmd); | |
2616 | if (ret) | |
2617 | IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
2618 | else | |
2619 | IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD " | |
2620 | "succeeded, " | |
2621 | "critical temperature is %d\n", | |
2622 | priv->hw_params.ct_kill_threshold); | |
2623 | } | |
2624 | } | |
2625 | ||
6d6a1afd SZ |
2626 | static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg) |
2627 | { | |
2628 | struct iwl_calib_cfg_cmd calib_cfg_cmd; | |
2629 | struct iwl_host_cmd cmd = { | |
2630 | .id = CALIBRATION_CFG_CMD, | |
2631 | .len = sizeof(struct iwl_calib_cfg_cmd), | |
2632 | .data = &calib_cfg_cmd, | |
2633 | }; | |
2634 | ||
2635 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
2636 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
7cb1b088 | 2637 | calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg); |
6d6a1afd SZ |
2638 | |
2639 | return iwl_send_cmd(priv, &cmd); | |
2640 | } | |
2641 | ||
2642 | ||
b481de9c | 2643 | /** |
4a4a9e81 | 2644 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2645 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 2646 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 2647 | */ |
4a4a9e81 | 2648 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 2649 | { |
57aab75a | 2650 | int ret = 0; |
246ed355 | 2651 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; |
b481de9c | 2652 | |
e1623446 | 2653 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 2654 | |
b481de9c ZY |
2655 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. |
2656 | * This is a paranoid check, because we would not have gotten the | |
2657 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 2658 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
2659 | /* Runtime instruction load was bad; |
2660 | * take it all the way back down so we can try again */ | |
e1623446 | 2661 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2662 | goto restart; |
2663 | } | |
2664 | ||
57aab75a TW |
2665 | ret = priv->cfg->ops->lib->alive_notify(priv); |
2666 | if (ret) { | |
39aadf8c WT |
2667 | IWL_WARN(priv, |
2668 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
2669 | goto restart; |
2670 | } | |
2671 | ||
6d6a1afd | 2672 | |
5b9f8cd3 | 2673 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
2674 | set_bit(STATUS_ALIVE, &priv->status); |
2675 | ||
22de94de SG |
2676 | /* Enable watchdog to monitor the driver tx queues */ |
2677 | iwl_setup_watchdog(priv); | |
b74e31a9 | 2678 | |
fee1247a | 2679 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2680 | return; |
2681 | ||
bc795df1 | 2682 | /* download priority table before any calibration request */ |
7cb1b088 WYG |
2683 | if (priv->cfg->bt_params && |
2684 | priv->cfg->bt_params->advanced_bt_coexist) { | |
f7322f8f WYG |
2685 | /* Configure Bluetooth device coexistence support */ |
2686 | priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; | |
2687 | priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; | |
2688 | priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; | |
2689 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
2690 | priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS; | |
a5901cbb | 2691 | iwlagn_send_prio_tbl(priv); |
f7322f8f WYG |
2692 | |
2693 | /* FIXME: w/a to force change uCode BT state machine */ | |
2694 | iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN, | |
2695 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); | |
2696 | iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE, | |
2697 | BT_COEX_PRIO_TBL_EVT_INIT_CALIB2); | |
2698 | } | |
bc795df1 WYG |
2699 | if (priv->hw_params.calib_rt_cfg) |
2700 | iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg); | |
2701 | ||
36d6825b | 2702 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2703 | |
470ab2dd | 2704 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2705 | |
2f748dec WYG |
2706 | /* Configure Tx antenna selection based on H/W config */ |
2707 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
2708 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
2709 | ||
246ed355 | 2710 | if (iwl_is_associated_ctx(ctx)) { |
c1adf9fb | 2711 | struct iwl_rxon_cmd *active_rxon = |
246ed355 | 2712 | (struct iwl_rxon_cmd *)&ctx->active; |
019fb97d | 2713 | /* apply any changes in staging */ |
246ed355 | 2714 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
b481de9c ZY |
2715 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2716 | } else { | |
d0fe478c | 2717 | struct iwl_rxon_context *tmp; |
b481de9c | 2718 | /* Initialize our rx_config data */ |
d0fe478c JB |
2719 | for_each_context(priv, tmp) |
2720 | iwl_connection_init_rx_config(priv, tmp); | |
45823531 AK |
2721 | |
2722 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 | 2723 | priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx); |
b481de9c ZY |
2724 | } |
2725 | ||
7cb1b088 WYG |
2726 | if (priv->cfg->bt_params && |
2727 | !priv->cfg->bt_params->advanced_bt_coexist) { | |
aeb4a2ee WYG |
2728 | /* Configure Bluetooth device coexistence support */ |
2729 | priv->cfg->ops->hcmd->send_bt_config(priv); | |
2730 | } | |
b481de9c | 2731 | |
4a4a9e81 TW |
2732 | iwl_reset_run_time_calib(priv); |
2733 | ||
9e2e7422 WYG |
2734 | set_bit(STATUS_READY, &priv->status); |
2735 | ||
b481de9c | 2736 | /* Configure the adapter for unassociated operation */ |
246ed355 | 2737 | iwlcore_commit_rxon(priv, ctx); |
b481de9c ZY |
2738 | |
2739 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 2740 | iwl_rf_kill_ct_config(priv); |
5a66926a | 2741 | |
e1623446 | 2742 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
5a66926a | 2743 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2744 | |
e312c24c | 2745 | iwl_power_update_mode(priv, true); |
7e246191 RC |
2746 | IWL_DEBUG_INFO(priv, "Updated power mode\n"); |
2747 | ||
c46fbefa | 2748 | |
b481de9c ZY |
2749 | return; |
2750 | ||
2751 | restart: | |
2752 | queue_work(priv->workqueue, &priv->restart); | |
2753 | } | |
2754 | ||
4e39317d | 2755 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2756 | |
5b9f8cd3 | 2757 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2758 | { |
2759 | unsigned long flags; | |
2760 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2761 | |
e1623446 | 2762 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2763 | |
d745d472 SG |
2764 | iwl_scan_cancel_timeout(priv, 200); |
2765 | ||
2766 | exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2767 | |
b62177a0 SG |
2768 | /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set |
2769 | * to prevent rearm timer */ | |
22de94de | 2770 | del_timer_sync(&priv->watchdog); |
b62177a0 | 2771 | |
dcef732c | 2772 | iwl_clear_ucode_stations(priv, NULL); |
a194e324 | 2773 | iwl_dealloc_bcast_stations(priv); |
db125c78 | 2774 | iwl_clear_driver_stations(priv); |
b481de9c | 2775 | |
a1174138 | 2776 | /* reset BT coex data */ |
da5dbb97 | 2777 | priv->bt_status = 0; |
7cb1b088 WYG |
2778 | if (priv->cfg->bt_params) |
2779 | priv->bt_traffic_load = | |
2780 | priv->cfg->bt_params->bt_init_traffic_load; | |
2781 | else | |
2782 | priv->bt_traffic_load = 0; | |
a1174138 | 2783 | priv->bt_sco_active = false; |
bee008b7 WYG |
2784 | priv->bt_full_concurrent = false; |
2785 | priv->bt_ci_compliance = 0; | |
a1174138 | 2786 | |
b481de9c ZY |
2787 | /* Unblock any waiting calls */ |
2788 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2789 | ||
b481de9c ZY |
2790 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2791 | * exiting the module */ | |
2792 | if (!exit_pending) | |
2793 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2794 | ||
2795 | /* stop and reset the on-board processor */ | |
3395f6e9 | 2796 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2797 | |
2798 | /* tell the device to stop sending interrupts */ | |
0359facc | 2799 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2800 | iwl_disable_interrupts(priv); |
0359facc MA |
2801 | spin_unlock_irqrestore(&priv->lock, flags); |
2802 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2803 | |
2804 | if (priv->mac80211_registered) | |
2805 | ieee80211_stop_queues(priv->hw); | |
2806 | ||
5b9f8cd3 | 2807 | /* If we have not previously called iwl_init() then |
a60e77e5 | 2808 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 2809 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2810 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2811 | STATUS_RF_KILL_HW | | |
9788864e RC |
2812 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2813 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
2814 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2815 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2816 | goto exit; |
2817 | } | |
2818 | ||
6da3a13e | 2819 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2820 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2821 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2822 | STATUS_RF_KILL_HW | | |
9788864e RC |
2823 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2824 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2825 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
2826 | STATUS_FW_ERROR | |
2827 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2828 | STATUS_EXIT_PENDING; | |
b481de9c | 2829 | |
ef850d7c | 2830 | /* device going down, Stop using ICT table */ |
e39fdee1 WYG |
2831 | if (priv->cfg->ops->lib->isr_ops.disable) |
2832 | priv->cfg->ops->lib->isr_ops.disable(priv); | |
b481de9c | 2833 | |
74bcdb33 | 2834 | iwlagn_txq_ctx_stop(priv); |
54b81550 | 2835 | iwlagn_rxq_stop(priv); |
b481de9c | 2836 | |
309e731a BC |
2837 | /* Power-down device's busmaster DMA clocks */ |
2838 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2839 | udelay(5); |
2840 | ||
309e731a BC |
2841 | /* Make sure (redundant) we've released our request to stay awake */ |
2842 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
2843 | ||
4d2ccdb9 | 2844 | /* Stop the device, and put it in low power state */ |
14e8e4af | 2845 | iwl_apm_stop(priv); |
4d2ccdb9 | 2846 | |
b481de9c | 2847 | exit: |
885ba202 | 2848 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c | 2849 | |
77834543 | 2850 | dev_kfree_skb(priv->beacon_skb); |
12e934dc | 2851 | priv->beacon_skb = NULL; |
b481de9c ZY |
2852 | |
2853 | /* clear out any free frames */ | |
fcab423d | 2854 | iwl_clear_free_frames(priv); |
b481de9c ZY |
2855 | } |
2856 | ||
5b9f8cd3 | 2857 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2858 | { |
2859 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2860 | __iwl_down(priv); |
b481de9c | 2861 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2862 | |
4e39317d | 2863 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
2864 | } |
2865 | ||
086ed117 MA |
2866 | #define HW_READY_TIMEOUT (50) |
2867 | ||
2868 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
2869 | { | |
2870 | int ret = 0; | |
2871 | ||
2872 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2873 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
2874 | ||
2875 | /* See if we got it */ | |
2876 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2877 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2878 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2879 | HW_READY_TIMEOUT); | |
2880 | if (ret != -ETIMEDOUT) | |
2881 | priv->hw_ready = true; | |
2882 | else | |
2883 | priv->hw_ready = false; | |
2884 | ||
2885 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
2886 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
2887 | return ret; | |
2888 | } | |
2889 | ||
2890 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
2891 | { | |
2892 | int ret = 0; | |
2893 | ||
91dd6c27 | 2894 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n"); |
086ed117 | 2895 | |
3354a0f6 MA |
2896 | ret = iwl_set_hw_ready(priv); |
2897 | if (priv->hw_ready) | |
2898 | return ret; | |
2899 | ||
2900 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
2901 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
2902 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
2903 | ||
2904 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2905 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
2906 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
2907 | ||
3354a0f6 | 2908 | /* HW should be ready by now, check again. */ |
086ed117 MA |
2909 | if (ret != -ETIMEDOUT) |
2910 | iwl_set_hw_ready(priv); | |
2911 | ||
2912 | return ret; | |
2913 | } | |
2914 | ||
b481de9c ZY |
2915 | #define MAX_HW_RESTARTS 5 |
2916 | ||
5b9f8cd3 | 2917 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 2918 | { |
a194e324 | 2919 | struct iwl_rxon_context *ctx; |
57aab75a TW |
2920 | int i; |
2921 | int ret; | |
b481de9c ZY |
2922 | |
2923 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2924 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2925 | return -EIO; |
2926 | } | |
2927 | ||
e903fbd4 | 2928 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2929 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
2930 | return -EIO; |
2931 | } | |
2932 | ||
a194e324 | 2933 | for_each_context(priv, ctx) { |
a30e3112 | 2934 | ret = iwlagn_alloc_bcast_station(priv, ctx); |
a194e324 JB |
2935 | if (ret) { |
2936 | iwl_dealloc_bcast_stations(priv); | |
2937 | return ret; | |
2938 | } | |
2939 | } | |
2c810ccd | 2940 | |
086ed117 MA |
2941 | iwl_prepare_card_hw(priv); |
2942 | ||
2943 | if (!priv->hw_ready) { | |
2944 | IWL_WARN(priv, "Exit HW not ready\n"); | |
2945 | return -EIO; | |
2946 | } | |
2947 | ||
e655b9f0 | 2948 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 2949 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 2950 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2951 | else |
e655b9f0 | 2952 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2953 | |
c1842d61 | 2954 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
2955 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
2956 | ||
5b9f8cd3 | 2957 | iwl_enable_interrupts(priv); |
a60e77e5 | 2958 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 2959 | return 0; |
b481de9c ZY |
2960 | } |
2961 | ||
3395f6e9 | 2962 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2963 | |
13bb9483 | 2964 | /* must be initialised before iwl_hw_nic_init */ |
751ca305 JB |
2965 | if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS)) |
2966 | priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM; | |
2967 | else | |
2968 | priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM; | |
13bb9483 | 2969 | |
74bcdb33 | 2970 | ret = iwlagn_hw_nic_init(priv); |
57aab75a | 2971 | if (ret) { |
15b1687c | 2972 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 2973 | return ret; |
b481de9c ZY |
2974 | } |
2975 | ||
2976 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2977 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2978 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2979 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2980 | ||
2981 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 2982 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 2983 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2984 | |
2985 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2986 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2987 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2988 | |
2989 | /* Copy original ucode data image from disk into backup cache. | |
2990 | * This will be used to initialize the on-board processor's | |
2991 | * data SRAM for a clean start when the runtime program first loads. */ | |
2992 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2993 | priv->ucode_data.len); |
b481de9c | 2994 | |
b481de9c ZY |
2995 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2996 | ||
b481de9c ZY |
2997 | /* load bootstrap state machine, |
2998 | * load bootstrap program into processor's memory, | |
2999 | * prepare to load the "initialize" uCode */ | |
57aab75a | 3000 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 3001 | |
57aab75a | 3002 | if (ret) { |
15b1687c WT |
3003 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
3004 | ret); | |
b481de9c ZY |
3005 | continue; |
3006 | } | |
3007 | ||
3008 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 3009 | iwl_nic_start(priv); |
b481de9c | 3010 | |
e1623446 | 3011 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
3012 | |
3013 | return 0; | |
3014 | } | |
3015 | ||
3016 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 3017 | __iwl_down(priv); |
64e72c3e | 3018 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
3019 | |
3020 | /* tried to restart and config the device for as long as our | |
3021 | * patience could withstand */ | |
15b1687c | 3022 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
3023 | return -EIO; |
3024 | } | |
3025 | ||
3026 | ||
3027 | /***************************************************************************** | |
3028 | * | |
3029 | * Workqueue callbacks | |
3030 | * | |
3031 | *****************************************************************************/ | |
3032 | ||
4a4a9e81 | 3033 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 3034 | { |
c79dd5b5 TW |
3035 | struct iwl_priv *priv = |
3036 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
3037 | |
3038 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3039 | return; | |
3040 | ||
3041 | mutex_lock(&priv->mutex); | |
f3ccc08c | 3042 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
3043 | mutex_unlock(&priv->mutex); |
3044 | } | |
3045 | ||
4a4a9e81 | 3046 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 3047 | { |
c79dd5b5 TW |
3048 | struct iwl_priv *priv = |
3049 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
3050 | |
3051 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3052 | return; | |
3053 | ||
258c44a0 | 3054 | /* enable dram interrupt */ |
e39fdee1 WYG |
3055 | if (priv->cfg->ops->lib->isr_ops.reset) |
3056 | priv->cfg->ops->lib->isr_ops.reset(priv); | |
258c44a0 | 3057 | |
b481de9c | 3058 | mutex_lock(&priv->mutex); |
4a4a9e81 | 3059 | iwl_alive_start(priv); |
b481de9c ZY |
3060 | mutex_unlock(&priv->mutex); |
3061 | } | |
3062 | ||
16e727e8 EG |
3063 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
3064 | { | |
3065 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
3066 | run_time_calib_work); | |
3067 | ||
3068 | mutex_lock(&priv->mutex); | |
3069 | ||
3070 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
3071 | test_bit(STATUS_SCANNING, &priv->status)) { | |
3072 | mutex_unlock(&priv->mutex); | |
3073 | return; | |
3074 | } | |
3075 | ||
3076 | if (priv->start_calib) { | |
9f60e7ee | 3077 | if (iwl_bt_statistics(priv)) { |
7980fba5 WYG |
3078 | iwl_chain_noise_calibration(priv, |
3079 | (void *)&priv->_agn.statistics_bt); | |
3080 | iwl_sensitivity_calibration(priv, | |
3081 | (void *)&priv->_agn.statistics_bt); | |
3082 | } else { | |
3083 | iwl_chain_noise_calibration(priv, | |
3084 | (void *)&priv->_agn.statistics); | |
3085 | iwl_sensitivity_calibration(priv, | |
3086 | (void *)&priv->_agn.statistics); | |
3087 | } | |
16e727e8 EG |
3088 | } |
3089 | ||
3090 | mutex_unlock(&priv->mutex); | |
16e727e8 EG |
3091 | } |
3092 | ||
5b9f8cd3 | 3093 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 3094 | { |
c79dd5b5 | 3095 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
3096 | |
3097 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3098 | return; | |
3099 | ||
19cc1087 | 3100 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
8bd413e6 | 3101 | struct iwl_rxon_context *ctx; |
bee008b7 WYG |
3102 | bool bt_sco, bt_full_concurrent; |
3103 | u8 bt_ci_compliance; | |
511b082d | 3104 | u8 bt_load; |
da5dbb97 | 3105 | u8 bt_status; |
511b082d | 3106 | |
19cc1087 | 3107 | mutex_lock(&priv->mutex); |
8bd413e6 JB |
3108 | for_each_context(priv, ctx) |
3109 | ctx->vif = NULL; | |
19cc1087 | 3110 | priv->is_open = 0; |
511b082d JB |
3111 | |
3112 | /* | |
3113 | * __iwl_down() will clear the BT status variables, | |
3114 | * which is correct, but when we restart we really | |
3115 | * want to keep them so restore them afterwards. | |
3116 | * | |
3117 | * The restart process will later pick them up and | |
3118 | * re-configure the hw when we reconfigure the BT | |
3119 | * command. | |
3120 | */ | |
3121 | bt_sco = priv->bt_sco_active; | |
bee008b7 WYG |
3122 | bt_full_concurrent = priv->bt_full_concurrent; |
3123 | bt_ci_compliance = priv->bt_ci_compliance; | |
511b082d | 3124 | bt_load = priv->bt_traffic_load; |
da5dbb97 | 3125 | bt_status = priv->bt_status; |
511b082d | 3126 | |
a1174138 | 3127 | __iwl_down(priv); |
511b082d JB |
3128 | |
3129 | priv->bt_sco_active = bt_sco; | |
bee008b7 WYG |
3130 | priv->bt_full_concurrent = bt_full_concurrent; |
3131 | priv->bt_ci_compliance = bt_ci_compliance; | |
511b082d | 3132 | priv->bt_traffic_load = bt_load; |
da5dbb97 | 3133 | priv->bt_status = bt_status; |
511b082d | 3134 | |
19cc1087 | 3135 | mutex_unlock(&priv->mutex); |
a1174138 | 3136 | iwl_cancel_deferred_work(priv); |
19cc1087 JB |
3137 | ieee80211_restart_hw(priv->hw); |
3138 | } else { | |
3139 | iwl_down(priv); | |
80676518 JB |
3140 | |
3141 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3142 | return; | |
3143 | ||
3144 | mutex_lock(&priv->mutex); | |
3145 | __iwl_up(priv); | |
3146 | mutex_unlock(&priv->mutex); | |
19cc1087 | 3147 | } |
b481de9c ZY |
3148 | } |
3149 | ||
5b9f8cd3 | 3150 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 3151 | { |
c79dd5b5 TW |
3152 | struct iwl_priv *priv = |
3153 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
3154 | |
3155 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
3156 | return; | |
3157 | ||
3158 | mutex_lock(&priv->mutex); | |
54b81550 | 3159 | iwlagn_rx_replenish(priv); |
b481de9c ZY |
3160 | mutex_unlock(&priv->mutex); |
3161 | } | |
3162 | ||
b481de9c ZY |
3163 | /***************************************************************************** |
3164 | * | |
3165 | * mac80211 entry point functions | |
3166 | * | |
3167 | *****************************************************************************/ | |
3168 | ||
154b25ce | 3169 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 3170 | |
f0b6e2e8 RC |
3171 | /* |
3172 | * Not a mac80211 entry point function, but it fits in with all the | |
3173 | * other mac80211 functions grouped here. | |
3174 | */ | |
dd7a2509 JB |
3175 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
3176 | struct iwlagn_ucode_capabilities *capa) | |
f0b6e2e8 RC |
3177 | { |
3178 | int ret; | |
3179 | struct ieee80211_hw *hw = priv->hw; | |
d0fe478c JB |
3180 | struct iwl_rxon_context *ctx; |
3181 | ||
f0b6e2e8 RC |
3182 | hw->rate_control_algorithm = "iwl-agn-rs"; |
3183 | ||
3184 | /* Tell mac80211 our characteristics */ | |
3185 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
f0b6e2e8 | 3186 | IEEE80211_HW_AMPDU_AGGREGATION | |
2491fa42 | 3187 | IEEE80211_HW_NEED_DTIM_PERIOD | |
6fb5511a JB |
3188 | IEEE80211_HW_SPECTRUM_MGMT | |
3189 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
f0b6e2e8 | 3190 | |
9b768832 JB |
3191 | hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF; |
3192 | ||
7cb1b088 | 3193 | if (!priv->cfg->base_params->broken_powersave) |
f0b6e2e8 RC |
3194 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | |
3195 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
3196 | ||
ba37a3d0 JB |
3197 | if (priv->cfg->sku & IWL_SKU_N) |
3198 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | |
3199 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
3200 | ||
8d9698b3 | 3201 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
fd1af15d JB |
3202 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
3203 | ||
d0fe478c JB |
3204 | for_each_context(priv, ctx) { |
3205 | hw->wiphy->interface_modes |= ctx->interface_modes; | |
3206 | hw->wiphy->interface_modes |= ctx->exclusive_interface_modes; | |
3207 | } | |
f0b6e2e8 | 3208 | |
9b9190d9 JB |
3209 | hw->wiphy->max_remain_on_channel_duration = 1000; |
3210 | ||
f6c8f152 | 3211 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | |
274102a8 JB |
3212 | WIPHY_FLAG_DISABLE_BEACON_HINTS | |
3213 | WIPHY_FLAG_IBSS_RSN; | |
f0b6e2e8 RC |
3214 | |
3215 | /* | |
3216 | * For now, disable PS by default because it affects | |
3217 | * RX performance significantly. | |
3218 | */ | |
5be83de5 | 3219 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
f0b6e2e8 | 3220 | |
1382c71c | 3221 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; |
f0b6e2e8 | 3222 | /* we create the 802.11 header and a zero-length SSID element */ |
dd7a2509 | 3223 | hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2; |
f0b6e2e8 RC |
3224 | |
3225 | /* Default value; 4 EDCA QOS priorities */ | |
3226 | hw->queues = 4; | |
3227 | ||
3228 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | |
3229 | ||
3230 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
3231 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
3232 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
3233 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
3234 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
3235 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
3236 | ||
5ed540ae WYG |
3237 | iwl_leds_init(priv); |
3238 | ||
f0b6e2e8 RC |
3239 | ret = ieee80211_register_hw(priv->hw); |
3240 | if (ret) { | |
3241 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
3242 | return ret; | |
3243 | } | |
3244 | priv->mac80211_registered = 1; | |
3245 | ||
3246 | return 0; | |
3247 | } | |
3248 | ||
3249 | ||
2295c66b | 3250 | int iwlagn_mac_start(struct ieee80211_hw *hw) |
b481de9c | 3251 | { |
c79dd5b5 | 3252 | struct iwl_priv *priv = hw->priv; |
5a66926a | 3253 | int ret; |
b481de9c | 3254 | |
e1623446 | 3255 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
3256 | |
3257 | /* we should be verifying the device is ready to be opened */ | |
3258 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 3259 | ret = __iwl_up(priv); |
b481de9c | 3260 | mutex_unlock(&priv->mutex); |
5a66926a | 3261 | |
e655b9f0 | 3262 | if (ret) |
6cd0b1cb | 3263 | return ret; |
e655b9f0 | 3264 | |
c1842d61 TW |
3265 | if (iwl_is_rfkill(priv)) |
3266 | goto out; | |
3267 | ||
e1623446 | 3268 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 3269 | |
fe9b6b72 | 3270 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 3271 | * mac80211 will not be run successfully. */ |
154b25ce EG |
3272 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
3273 | test_bit(STATUS_READY, &priv->status), | |
3274 | UCODE_READY_TIMEOUT); | |
3275 | if (!ret) { | |
3276 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 3277 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 3278 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 3279 | return -ETIMEDOUT; |
5a66926a | 3280 | } |
fe9b6b72 | 3281 | } |
0a078ffa | 3282 | |
5ed540ae | 3283 | iwlagn_led_enable(priv); |
e932a609 | 3284 | |
c1842d61 | 3285 | out: |
0a078ffa | 3286 | priv->is_open = 1; |
e1623446 | 3287 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3288 | return 0; |
3289 | } | |
3290 | ||
2295c66b | 3291 | void iwlagn_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3292 | { |
c79dd5b5 | 3293 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3294 | |
e1623446 | 3295 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 3296 | |
19cc1087 | 3297 | if (!priv->is_open) |
e655b9f0 | 3298 | return; |
e655b9f0 | 3299 | |
b481de9c | 3300 | priv->is_open = 0; |
5a66926a | 3301 | |
5b9f8cd3 | 3302 | iwl_down(priv); |
5a66926a ZY |
3303 | |
3304 | flush_workqueue(priv->workqueue); | |
6cd0b1cb | 3305 | |
554d1d02 SG |
3306 | /* User space software may expect getting rfkill changes |
3307 | * even if interface is down */ | |
6cd0b1cb | 3308 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
554d1d02 | 3309 | iwl_enable_rfkill_int(priv); |
948c171c | 3310 | |
e1623446 | 3311 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3312 | } |
3313 | ||
2295c66b | 3314 | int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3315 | { |
c79dd5b5 | 3316 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3317 | |
e1623446 | 3318 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 3319 | |
e1623446 | 3320 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3321 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3322 | |
74bcdb33 | 3323 | if (iwlagn_tx_skb(priv, skb)) |
b481de9c ZY |
3324 | dev_kfree_skb_any(skb); |
3325 | ||
e1623446 | 3326 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 3327 | return NETDEV_TX_OK; |
b481de9c ZY |
3328 | } |
3329 | ||
2295c66b JB |
3330 | void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw, |
3331 | struct ieee80211_vif *vif, | |
3332 | struct ieee80211_key_conf *keyconf, | |
3333 | struct ieee80211_sta *sta, | |
3334 | u32 iv32, u16 *phase1key) | |
ab885f8c | 3335 | { |
9f58671e | 3336 | struct iwl_priv *priv = hw->priv; |
a194e324 JB |
3337 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
3338 | ||
e1623446 | 3339 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 3340 | |
a194e324 | 3341 | iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta, |
b3fbdcf4 | 3342 | iv32, phase1key); |
ab885f8c | 3343 | |
e1623446 | 3344 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
3345 | } |
3346 | ||
2295c66b JB |
3347 | int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
3348 | struct ieee80211_vif *vif, struct ieee80211_sta *sta, | |
3349 | struct ieee80211_key_conf *key) | |
b481de9c | 3350 | { |
c79dd5b5 | 3351 | struct iwl_priv *priv = hw->priv; |
a194e324 | 3352 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
c10afb6e | 3353 | struct iwl_rxon_context *ctx = vif_priv->ctx; |
42986796 WT |
3354 | int ret; |
3355 | u8 sta_id; | |
3356 | bool is_default_wep_key = false; | |
b481de9c | 3357 | |
e1623446 | 3358 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3359 | |
90e8e424 | 3360 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 3361 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3362 | return -EOPNOTSUPP; |
3363 | } | |
b481de9c | 3364 | |
274102a8 JB |
3365 | /* |
3366 | * To support IBSS RSN, don't program group keys in IBSS, the | |
3367 | * hardware will then not attempt to decrypt the frames. | |
3368 | */ | |
3369 | if (vif->type == NL80211_IFTYPE_ADHOC && | |
3370 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) | |
3371 | return -EOPNOTSUPP; | |
3372 | ||
a194e324 | 3373 | sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta); |
0af8bcae JB |
3374 | if (sta_id == IWL_INVALID_STATION) |
3375 | return -EINVAL; | |
b481de9c | 3376 | |
6974e363 | 3377 | mutex_lock(&priv->mutex); |
2a421b91 | 3378 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 | 3379 | |
a90178fa JB |
3380 | /* |
3381 | * If we are getting WEP group key and we didn't receive any key mapping | |
6974e363 EG |
3382 | * so far, we are in legacy wep mode (group key only), otherwise we are |
3383 | * in 1X mode. | |
a90178fa JB |
3384 | * In legacy wep mode, we use another host command to the uCode. |
3385 | */ | |
97359d12 JB |
3386 | if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || |
3387 | key->cipher == WLAN_CIPHER_SUITE_WEP104) && | |
54c8067a | 3388 | !sta) { |
6974e363 | 3389 | if (cmd == SET_KEY) |
c10afb6e | 3390 | is_default_wep_key = !ctx->key_mapping_keys; |
6974e363 | 3391 | else |
ccc038ab EG |
3392 | is_default_wep_key = |
3393 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 3394 | } |
052c4b9f | 3395 | |
b481de9c | 3396 | switch (cmd) { |
deb09c43 | 3397 | case SET_KEY: |
6974e363 | 3398 | if (is_default_wep_key) |
2995bafa | 3399 | ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key); |
deb09c43 | 3400 | else |
a194e324 JB |
3401 | ret = iwl_set_dynamic_key(priv, vif_priv->ctx, |
3402 | key, sta_id); | |
deb09c43 | 3403 | |
e1623446 | 3404 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
3405 | break; |
3406 | case DISABLE_KEY: | |
6974e363 | 3407 | if (is_default_wep_key) |
c10afb6e | 3408 | ret = iwl_remove_default_wep_key(priv, ctx, key); |
deb09c43 | 3409 | else |
c10afb6e | 3410 | ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id); |
deb09c43 | 3411 | |
e1623446 | 3412 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
3413 | break; |
3414 | default: | |
deb09c43 | 3415 | ret = -EINVAL; |
b481de9c ZY |
3416 | } |
3417 | ||
72e15d71 | 3418 | mutex_unlock(&priv->mutex); |
e1623446 | 3419 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3420 | |
deb09c43 | 3421 | return ret; |
b481de9c ZY |
3422 | } |
3423 | ||
2295c66b JB |
3424 | int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw, |
3425 | struct ieee80211_vif *vif, | |
3426 | enum ieee80211_ampdu_mlme_action action, | |
0b01f030 JB |
3427 | struct ieee80211_sta *sta, u16 tid, u16 *ssn, |
3428 | u8 buf_size) | |
d783b061 TW |
3429 | { |
3430 | struct iwl_priv *priv = hw->priv; | |
4620fefa | 3431 | int ret = -EINVAL; |
7b090687 | 3432 | struct iwl_station_priv *sta_priv = (void *) sta->drv_priv; |
d783b061 | 3433 | |
e1623446 | 3434 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 3435 | sta->addr, tid); |
d783b061 TW |
3436 | |
3437 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
3438 | return -EACCES; | |
3439 | ||
4620fefa JB |
3440 | mutex_lock(&priv->mutex); |
3441 | ||
d783b061 TW |
3442 | switch (action) { |
3443 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 3444 | IWL_DEBUG_HT(priv, "start Rx\n"); |
4620fefa JB |
3445 | ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn); |
3446 | break; | |
d783b061 | 3447 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 3448 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
619753ff | 3449 | ret = iwl_sta_rx_agg_stop(priv, sta, tid); |
5c2207c6 | 3450 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa JB |
3451 | ret = 0; |
3452 | break; | |
d783b061 | 3453 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 3454 | IWL_DEBUG_HT(priv, "start Tx\n"); |
619753ff | 3455 | ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn); |
d5a0ffa3 WYG |
3456 | if (ret == 0) { |
3457 | priv->_agn.agg_tids_count++; | |
3458 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3459 | priv->_agn.agg_tids_count); | |
3460 | } | |
4620fefa | 3461 | break; |
d783b061 | 3462 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 3463 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
619753ff | 3464 | ret = iwlagn_tx_agg_stop(priv, vif, sta, tid); |
d5a0ffa3 WYG |
3465 | if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) { |
3466 | priv->_agn.agg_tids_count--; | |
3467 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3468 | priv->_agn.agg_tids_count); | |
3469 | } | |
5c2207c6 | 3470 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
4620fefa | 3471 | ret = 0; |
7cb1b088 WYG |
3472 | if (priv->cfg->ht_params && |
3473 | priv->cfg->ht_params->use_rts_for_aggregation) { | |
94597ab2 JB |
3474 | struct iwl_station_priv *sta_priv = |
3475 | (void *) sta->drv_priv; | |
3476 | /* | |
3477 | * switch off RTS/CTS if it was previously enabled | |
3478 | */ | |
3479 | ||
3480 | sta_priv->lq_sta.lq.general_params.flags &= | |
3481 | ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
7e6a5886 JB |
3482 | iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), |
3483 | &sta_priv->lq_sta.lq, CMD_ASYNC, false); | |
94597ab2 | 3484 | } |
4620fefa | 3485 | break; |
f0527971 | 3486 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
7b090687 JB |
3487 | /* |
3488 | * If the limit is 0, then it wasn't initialised yet, | |
3489 | * use the default. We can do that since we take the | |
3490 | * minimum below, and we don't want to go above our | |
3491 | * default due to hardware restrictions. | |
3492 | */ | |
3493 | if (sta_priv->max_agg_bufsize == 0) | |
3494 | sta_priv->max_agg_bufsize = | |
3495 | LINK_QUAL_AGG_FRAME_LIMIT_DEF; | |
3496 | ||
3497 | /* | |
3498 | * Even though in theory the peer could have different | |
3499 | * aggregation reorder buffer sizes for different sessions, | |
3500 | * our ucode doesn't allow for that and has a global limit | |
3501 | * for each station. Therefore, use the minimum of all the | |
3502 | * aggregation sessions and our default value. | |
3503 | */ | |
3504 | sta_priv->max_agg_bufsize = | |
3505 | min(sta_priv->max_agg_bufsize, buf_size); | |
3506 | ||
7cb1b088 WYG |
3507 | if (priv->cfg->ht_params && |
3508 | priv->cfg->ht_params->use_rts_for_aggregation) { | |
cfecc6b4 WYG |
3509 | /* |
3510 | * switch to RTS/CTS if it is the prefer protection | |
3511 | * method for HT traffic | |
3512 | */ | |
94597ab2 JB |
3513 | |
3514 | sta_priv->lq_sta.lq.general_params.flags |= | |
3515 | LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK; | |
cfecc6b4 | 3516 | } |
7b090687 JB |
3517 | |
3518 | sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit = | |
3519 | sta_priv->max_agg_bufsize; | |
3520 | ||
3521 | iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif), | |
3522 | &sta_priv->lq_sta.lq, CMD_ASYNC, false); | |
cfecc6b4 | 3523 | ret = 0; |
d783b061 TW |
3524 | break; |
3525 | } | |
4620fefa JB |
3526 | mutex_unlock(&priv->mutex); |
3527 | ||
3528 | return ret; | |
d783b061 | 3529 | } |
9f58671e | 3530 | |
2295c66b JB |
3531 | int iwlagn_mac_sta_add(struct ieee80211_hw *hw, |
3532 | struct ieee80211_vif *vif, | |
3533 | struct ieee80211_sta *sta) | |
fe6b23dd RC |
3534 | { |
3535 | struct iwl_priv *priv = hw->priv; | |
3536 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
a194e324 | 3537 | struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; |
eafdfbd3 | 3538 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
fe6b23dd RC |
3539 | int ret; |
3540 | u8 sta_id; | |
3541 | ||
3542 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", | |
3543 | sta->addr); | |
da5ae1cf RC |
3544 | mutex_lock(&priv->mutex); |
3545 | IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n", | |
3546 | sta->addr); | |
3547 | sta_priv->common.sta_id = IWL_INVALID_STATION; | |
fe6b23dd RC |
3548 | |
3549 | atomic_set(&sta_priv->pending_frames, 0); | |
3550 | if (vif->type == NL80211_IFTYPE_AP) | |
3551 | sta_priv->client = true; | |
3552 | ||
a194e324 | 3553 | ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr, |
238d781d | 3554 | is_ap, sta, &sta_id); |
fe6b23dd RC |
3555 | if (ret) { |
3556 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
3557 | sta->addr, ret); | |
3558 | /* Should we return success if return code is EEXIST ? */ | |
da5ae1cf | 3559 | mutex_unlock(&priv->mutex); |
fe6b23dd RC |
3560 | return ret; |
3561 | } | |
3562 | ||
fd1af15d JB |
3563 | sta_priv->common.sta_id = sta_id; |
3564 | ||
fe6b23dd | 3565 | /* Initialize rate scaling */ |
91dd6c27 | 3566 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n", |
fe6b23dd RC |
3567 | sta->addr); |
3568 | iwl_rs_rate_init(priv, sta, sta_id); | |
da5ae1cf | 3569 | mutex_unlock(&priv->mutex); |
fe6b23dd | 3570 | |
fd1af15d | 3571 | return 0; |
fe6b23dd RC |
3572 | } |
3573 | ||
2295c66b JB |
3574 | void iwlagn_mac_channel_switch(struct ieee80211_hw *hw, |
3575 | struct ieee80211_channel_switch *ch_switch) | |
79d07325 WYG |
3576 | { |
3577 | struct iwl_priv *priv = hw->priv; | |
3578 | const struct iwl_channel_info *ch_info; | |
3579 | struct ieee80211_conf *conf = &hw->conf; | |
aa2dc6b5 | 3580 | struct ieee80211_channel *channel = ch_switch->channel; |
79d07325 | 3581 | struct iwl_ht_config *ht_conf = &priv->current_ht_config; |
246ed355 JB |
3582 | /* |
3583 | * MULTI-FIXME | |
3584 | * When we add support for multiple interfaces, we need to | |
3585 | * revisit this. The channel switch command in the device | |
3586 | * only affects the BSS context, but what does that really | |
3587 | * mean? And what if we get a CSA on the second interface? | |
3588 | * This needs a lot of work. | |
3589 | */ | |
3590 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS]; | |
79d07325 WYG |
3591 | u16 ch; |
3592 | unsigned long flags = 0; | |
3593 | ||
3594 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3595 | ||
3596 | if (iwl_is_rfkill(priv)) | |
3597 | goto out_exit; | |
3598 | ||
3599 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
3600 | test_bit(STATUS_SCANNING, &priv->status)) | |
3601 | goto out_exit; | |
3602 | ||
246ed355 | 3603 | if (!iwl_is_associated_ctx(ctx)) |
79d07325 WYG |
3604 | goto out_exit; |
3605 | ||
3606 | /* channel switch in progress */ | |
3607 | if (priv->switch_rxon.switch_in_progress == true) | |
3608 | goto out_exit; | |
3609 | ||
3610 | mutex_lock(&priv->mutex); | |
3611 | if (priv->cfg->ops->lib->set_channel_switch) { | |
3612 | ||
aa2dc6b5 | 3613 | ch = channel->hw_value; |
246ed355 | 3614 | if (le16_to_cpu(ctx->active.channel) != ch) { |
79d07325 | 3615 | ch_info = iwl_get_channel_info(priv, |
aa2dc6b5 | 3616 | channel->band, |
79d07325 WYG |
3617 | ch); |
3618 | if (!is_channel_valid(ch_info)) { | |
3619 | IWL_DEBUG_MAC80211(priv, "invalid channel\n"); | |
3620 | goto out; | |
3621 | } | |
3622 | spin_lock_irqsave(&priv->lock, flags); | |
3623 | ||
3624 | priv->current_ht_config.smps = conf->smps_mode; | |
3625 | ||
3626 | /* Configure HT40 channels */ | |
7e6a5886 JB |
3627 | ctx->ht.enabled = conf_is_ht(conf); |
3628 | if (ctx->ht.enabled) { | |
79d07325 | 3629 | if (conf_is_ht40_minus(conf)) { |
7e6a5886 | 3630 | ctx->ht.extension_chan_offset = |
79d07325 | 3631 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; |
7e6a5886 | 3632 | ctx->ht.is_40mhz = true; |
79d07325 | 3633 | } else if (conf_is_ht40_plus(conf)) { |
7e6a5886 | 3634 | ctx->ht.extension_chan_offset = |
79d07325 | 3635 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; |
7e6a5886 | 3636 | ctx->ht.is_40mhz = true; |
79d07325 | 3637 | } else { |
7e6a5886 | 3638 | ctx->ht.extension_chan_offset = |
79d07325 | 3639 | IEEE80211_HT_PARAM_CHA_SEC_NONE; |
7e6a5886 | 3640 | ctx->ht.is_40mhz = false; |
79d07325 WYG |
3641 | } |
3642 | } else | |
7e6a5886 | 3643 | ctx->ht.is_40mhz = false; |
79d07325 | 3644 | |
246ed355 JB |
3645 | if ((le16_to_cpu(ctx->staging.channel) != ch)) |
3646 | ctx->staging.flags = 0; | |
79d07325 | 3647 | |
246ed355 | 3648 | iwl_set_rxon_channel(priv, channel, ctx); |
79d07325 | 3649 | iwl_set_rxon_ht(priv, ht_conf); |
246ed355 | 3650 | iwl_set_flags_for_band(priv, ctx, channel->band, |
8bd413e6 | 3651 | ctx->vif); |
79d07325 WYG |
3652 | spin_unlock_irqrestore(&priv->lock, flags); |
3653 | ||
3654 | iwl_set_rate(priv); | |
3655 | /* | |
3656 | * at this point, staging_rxon has the | |
3657 | * configuration for channel switch | |
3658 | */ | |
3659 | if (priv->cfg->ops->lib->set_channel_switch(priv, | |
3660 | ch_switch)) | |
3661 | priv->switch_rxon.switch_in_progress = false; | |
3662 | } | |
3663 | } | |
3664 | out: | |
3665 | mutex_unlock(&priv->mutex); | |
3666 | out_exit: | |
3667 | if (!priv->switch_rxon.switch_in_progress) | |
8bd413e6 | 3668 | ieee80211_chswitch_done(ctx->vif, false); |
79d07325 WYG |
3669 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
3670 | } | |
3671 | ||
2295c66b JB |
3672 | void iwlagn_configure_filter(struct ieee80211_hw *hw, |
3673 | unsigned int changed_flags, | |
3674 | unsigned int *total_flags, | |
3675 | u64 multicast) | |
8b8ab9d5 JB |
3676 | { |
3677 | struct iwl_priv *priv = hw->priv; | |
3678 | __le32 filter_or = 0, filter_nand = 0; | |
246ed355 | 3679 | struct iwl_rxon_context *ctx; |
8b8ab9d5 JB |
3680 | |
3681 | #define CHK(test, flag) do { \ | |
3682 | if (*total_flags & (test)) \ | |
3683 | filter_or |= (flag); \ | |
3684 | else \ | |
3685 | filter_nand |= (flag); \ | |
3686 | } while (0) | |
3687 | ||
3688 | IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n", | |
3689 | changed_flags, *total_flags); | |
3690 | ||
3691 | CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); | |
bdb84fec JB |
3692 | /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */ |
3693 | CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); | |
8b8ab9d5 JB |
3694 | CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); |
3695 | ||
3696 | #undef CHK | |
3697 | ||
3698 | mutex_lock(&priv->mutex); | |
3699 | ||
246ed355 JB |
3700 | for_each_context(priv, ctx) { |
3701 | ctx->staging.filter_flags &= ~filter_nand; | |
3702 | ctx->staging.filter_flags |= filter_or; | |
749ff4ef SG |
3703 | |
3704 | /* | |
3705 | * Not committing directly because hardware can perform a scan, | |
3706 | * but we'll eventually commit the filter flags change anyway. | |
3707 | */ | |
246ed355 | 3708 | } |
8b8ab9d5 JB |
3709 | |
3710 | mutex_unlock(&priv->mutex); | |
3711 | ||
3712 | /* | |
3713 | * Receiving all multicast frames is always enabled by the | |
3714 | * default flags setup in iwl_connection_init_rx_config() | |
3715 | * since we currently do not support programming multicast | |
3716 | * filters into the device. | |
3717 | */ | |
3718 | *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
3719 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
3720 | } | |
3721 | ||
2295c66b | 3722 | void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop) |
716c74b0 WYG |
3723 | { |
3724 | struct iwl_priv *priv = hw->priv; | |
3725 | ||
3726 | mutex_lock(&priv->mutex); | |
3727 | IWL_DEBUG_MAC80211(priv, "enter\n"); | |
3728 | ||
3729 | /* do not support "flush" */ | |
3730 | if (!priv->cfg->ops->lib->txfifo_flush) | |
3731 | goto done; | |
3732 | ||
3733 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
3734 | IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n"); | |
3735 | goto done; | |
3736 | } | |
3737 | if (iwl_is_rfkill(priv)) { | |
3738 | IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n"); | |
3739 | goto done; | |
3740 | } | |
3741 | ||
3742 | /* | |
3743 | * mac80211 will not push any more frames for transmit | |
3744 | * until the flush is completed | |
3745 | */ | |
3746 | if (drop) { | |
3747 | IWL_DEBUG_MAC80211(priv, "send flush command\n"); | |
3748 | if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) { | |
3749 | IWL_ERR(priv, "flush request fail\n"); | |
3750 | goto done; | |
3751 | } | |
3752 | } | |
3753 | IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n"); | |
3754 | iwlagn_wait_tx_queue_empty(priv); | |
3755 | done: | |
3756 | mutex_unlock(&priv->mutex); | |
3757 | IWL_DEBUG_MAC80211(priv, "leave\n"); | |
3758 | } | |
3759 | ||
9b9190d9 JB |
3760 | static void iwlagn_disable_roc(struct iwl_priv *priv) |
3761 | { | |
3762 | struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN]; | |
3763 | struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel); | |
3764 | ||
3765 | lockdep_assert_held(&priv->mutex); | |
3766 | ||
3767 | if (!ctx->is_active) | |
3768 | return; | |
3769 | ||
3770 | ctx->staging.dev_type = RXON_DEV_TYPE_2STA; | |
3771 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
3772 | iwl_set_rxon_channel(priv, chan, ctx); | |
3773 | iwl_set_flags_for_band(priv, ctx, chan->band, NULL); | |
3774 | ||
3775 | priv->_agn.hw_roc_channel = NULL; | |
3776 | ||
3777 | iwlagn_commit_rxon(priv, ctx); | |
3778 | ||
3779 | ctx->is_active = false; | |
3780 | } | |
3781 | ||
3782 | static void iwlagn_bg_roc_done(struct work_struct *work) | |
3783 | { | |
3784 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
3785 | _agn.hw_roc_work.work); | |
3786 | ||
3787 | mutex_lock(&priv->mutex); | |
3788 | ieee80211_remain_on_channel_expired(priv->hw); | |
3789 | iwlagn_disable_roc(priv); | |
3790 | mutex_unlock(&priv->mutex); | |
3791 | } | |
3792 | ||
3793 | static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw, | |
3794 | struct ieee80211_channel *channel, | |
3795 | enum nl80211_channel_type channel_type, | |
3796 | int duration) | |
3797 | { | |
3798 | struct iwl_priv *priv = hw->priv; | |
3799 | int err = 0; | |
3800 | ||
3801 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | |
3802 | return -EOPNOTSUPP; | |
3803 | ||
3804 | if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes & | |
3805 | BIT(NL80211_IFTYPE_P2P_CLIENT))) | |
3806 | return -EOPNOTSUPP; | |
3807 | ||
3808 | mutex_lock(&priv->mutex); | |
3809 | ||
3810 | if (priv->contexts[IWL_RXON_CTX_PAN].is_active || | |
3811 | test_bit(STATUS_SCAN_HW, &priv->status)) { | |
3812 | err = -EBUSY; | |
3813 | goto out; | |
3814 | } | |
3815 | ||
3816 | priv->contexts[IWL_RXON_CTX_PAN].is_active = true; | |
3817 | priv->_agn.hw_roc_channel = channel; | |
3818 | priv->_agn.hw_roc_chantype = channel_type; | |
3819 | priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024); | |
3820 | iwlagn_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]); | |
3821 | queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work, | |
3822 | msecs_to_jiffies(duration + 20)); | |
3823 | ||
94073919 | 3824 | msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */ |
9b9190d9 JB |
3825 | ieee80211_ready_on_channel(priv->hw); |
3826 | ||
3827 | out: | |
3828 | mutex_unlock(&priv->mutex); | |
3829 | ||
3830 | return err; | |
3831 | } | |
3832 | ||
3833 | static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw) | |
3834 | { | |
3835 | struct iwl_priv *priv = hw->priv; | |
3836 | ||
3837 | if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) | |
3838 | return -EOPNOTSUPP; | |
3839 | ||
3840 | cancel_delayed_work_sync(&priv->_agn.hw_roc_work); | |
3841 | ||
3842 | mutex_lock(&priv->mutex); | |
3843 | iwlagn_disable_roc(priv); | |
3844 | mutex_unlock(&priv->mutex); | |
3845 | ||
3846 | return 0; | |
3847 | } | |
3848 | ||
b481de9c ZY |
3849 | /***************************************************************************** |
3850 | * | |
3851 | * driver setup and teardown | |
3852 | * | |
3853 | *****************************************************************************/ | |
3854 | ||
4e39317d | 3855 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3856 | { |
d21050c7 | 3857 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3858 | |
3859 | init_waitqueue_head(&priv->wait_command_queue); | |
3860 | ||
5b9f8cd3 EG |
3861 | INIT_WORK(&priv->restart, iwl_bg_restart); |
3862 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 3863 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 3864 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
65550636 | 3865 | INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush); |
bee008b7 | 3866 | INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency); |
fbba9410 | 3867 | INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config); |
4a4a9e81 TW |
3868 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
3869 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
9b9190d9 | 3870 | INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done); |
2a421b91 | 3871 | |
2a421b91 | 3872 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 3873 | |
4e39317d EG |
3874 | if (priv->cfg->ops->lib->setup_deferred_work) |
3875 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3876 | ||
3877 | init_timer(&priv->statistics_periodic); | |
3878 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3879 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 3880 | |
a9e1cb6a WYG |
3881 | init_timer(&priv->ucode_trace); |
3882 | priv->ucode_trace.data = (unsigned long)priv; | |
3883 | priv->ucode_trace.function = iwl_bg_ucode_trace; | |
3884 | ||
22de94de SG |
3885 | init_timer(&priv->watchdog); |
3886 | priv->watchdog.data = (unsigned long)priv; | |
3887 | priv->watchdog.function = iwl_bg_watchdog; | |
b74e31a9 | 3888 | |
7cb1b088 | 3889 | if (!priv->cfg->base_params->use_isr_legacy) |
ef850d7c MA |
3890 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) |
3891 | iwl_irq_tasklet, (unsigned long)priv); | |
3892 | else | |
3893 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3894 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
3895 | } |
3896 | ||
4e39317d | 3897 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3898 | { |
4e39317d EG |
3899 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3900 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3901 | |
3ae6a054 | 3902 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c | 3903 | cancel_delayed_work(&priv->alive_start); |
815e629b | 3904 | cancel_work_sync(&priv->run_time_calib_work); |
b481de9c | 3905 | cancel_work_sync(&priv->beacon_update); |
e7e16b90 SG |
3906 | |
3907 | iwl_cancel_scan_deferred_work(priv); | |
3908 | ||
bee008b7 | 3909 | cancel_work_sync(&priv->bt_full_concurrency); |
fbba9410 | 3910 | cancel_work_sync(&priv->bt_runtime_config); |
e7e16b90 | 3911 | |
4e39317d | 3912 | del_timer_sync(&priv->statistics_periodic); |
a9e1cb6a | 3913 | del_timer_sync(&priv->ucode_trace); |
b481de9c ZY |
3914 | } |
3915 | ||
89f186a8 RC |
3916 | static void iwl_init_hw_rates(struct iwl_priv *priv, |
3917 | struct ieee80211_rate *rates) | |
3918 | { | |
3919 | int i; | |
3920 | ||
3921 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { | |
3922 | rates[i].bitrate = iwl_rates[i].ieee * 5; | |
3923 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
3924 | rates[i].hw_value_short = i; | |
3925 | rates[i].flags = 0; | |
3926 | if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) { | |
3927 | /* | |
3928 | * If CCK != 1M then set short preamble rate flag. | |
3929 | */ | |
3930 | rates[i].flags |= | |
3931 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
3932 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
3933 | } | |
3934 | } | |
3935 | } | |
3936 | ||
3937 | static int iwl_init_drv(struct iwl_priv *priv) | |
3938 | { | |
3939 | int ret; | |
3940 | ||
89f186a8 RC |
3941 | spin_lock_init(&priv->sta_lock); |
3942 | spin_lock_init(&priv->hcmd_lock); | |
3943 | ||
3944 | INIT_LIST_HEAD(&priv->free_frames); | |
3945 | ||
3946 | mutex_init(&priv->mutex); | |
d2dfe6df | 3947 | mutex_init(&priv->sync_cmd_mutex); |
89f186a8 | 3948 | |
89f186a8 RC |
3949 | priv->ieee_channels = NULL; |
3950 | priv->ieee_rates = NULL; | |
3951 | priv->band = IEEE80211_BAND_2GHZ; | |
3952 | ||
3953 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
ba37a3d0 | 3954 | priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; |
a13d276f | 3955 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
d5a0ffa3 | 3956 | priv->_agn.agg_tids_count = 0; |
89f186a8 | 3957 | |
8a472da4 WYG |
3958 | /* initialize force reset */ |
3959 | priv->force_reset[IWL_RF_RESET].reset_duration = | |
3960 | IWL_DELAY_NEXT_FORCE_RF_RESET; | |
3961 | priv->force_reset[IWL_FW_RESET].reset_duration = | |
3962 | IWL_DELAY_NEXT_FORCE_FW_RELOAD; | |
89f186a8 RC |
3963 | |
3964 | /* Choose which receivers/antennas to use */ | |
3965 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
246ed355 JB |
3966 | priv->cfg->ops->hcmd->set_rxon_chain(priv, |
3967 | &priv->contexts[IWL_RXON_CTX_BSS]); | |
89f186a8 RC |
3968 | |
3969 | iwl_init_scan_params(priv); | |
3970 | ||
22bf59a0 | 3971 | /* init bt coex */ |
7cb1b088 WYG |
3972 | if (priv->cfg->bt_params && |
3973 | priv->cfg->bt_params->advanced_bt_coexist) { | |
b6e116e8 WYG |
3974 | priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT; |
3975 | priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT; | |
3976 | priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK; | |
22bf59a0 WYG |
3977 | priv->bt_on_thresh = BT_ON_THRESHOLD_DEF; |
3978 | priv->bt_duration = BT_DURATION_LIMIT_DEF; | |
3979 | priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF; | |
22bf59a0 WYG |
3980 | } |
3981 | ||
89f186a8 RC |
3982 | /* Set the tx_power_user_lmt to the lowest power level |
3983 | * this value will get overwritten by channel max power avg | |
3984 | * from eeprom */ | |
b744cb79 | 3985 | priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
a25a66ac | 3986 | priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
89f186a8 RC |
3987 | |
3988 | ret = iwl_init_channel_map(priv); | |
3989 | if (ret) { | |
3990 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3991 | goto err; | |
3992 | } | |
3993 | ||
3994 | ret = iwlcore_init_geos(priv); | |
3995 | if (ret) { | |
3996 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3997 | goto err_free_channel_map; | |
3998 | } | |
3999 | iwl_init_hw_rates(priv, priv->ieee_rates); | |
4000 | ||
4001 | return 0; | |
4002 | ||
4003 | err_free_channel_map: | |
4004 | iwl_free_channel_map(priv); | |
4005 | err: | |
4006 | return ret; | |
4007 | } | |
4008 | ||
4009 | static void iwl_uninit_drv(struct iwl_priv *priv) | |
4010 | { | |
4011 | iwl_calib_free_results(priv); | |
4012 | iwlcore_free_geos(priv); | |
4013 | iwl_free_channel_map(priv); | |
811ecc99 | 4014 | kfree(priv->scan_cmd); |
89f186a8 RC |
4015 | } |
4016 | ||
ae79d23d | 4017 | #ifdef CONFIG_IWL5000 |
dc21b545 | 4018 | struct ieee80211_ops iwlagn_hw_ops = { |
2295c66b JB |
4019 | .tx = iwlagn_mac_tx, |
4020 | .start = iwlagn_mac_start, | |
4021 | .stop = iwlagn_mac_stop, | |
5b9f8cd3 EG |
4022 | .add_interface = iwl_mac_add_interface, |
4023 | .remove_interface = iwl_mac_remove_interface, | |
d4daaea6 | 4024 | .change_interface = iwl_mac_change_interface, |
2295c66b | 4025 | .config = iwlagn_mac_config, |
8b8ab9d5 | 4026 | .configure_filter = iwlagn_configure_filter, |
2295c66b JB |
4027 | .set_key = iwlagn_mac_set_key, |
4028 | .update_tkip_key = iwlagn_mac_update_tkip_key, | |
5b9f8cd3 | 4029 | .conf_tx = iwl_mac_conf_tx, |
2295c66b JB |
4030 | .bss_info_changed = iwlagn_bss_info_changed, |
4031 | .ampdu_action = iwlagn_mac_ampdu_action, | |
6ab10ff8 | 4032 | .hw_scan = iwl_mac_hw_scan, |
2295c66b | 4033 | .sta_notify = iwlagn_mac_sta_notify, |
fe6b23dd RC |
4034 | .sta_add = iwlagn_mac_sta_add, |
4035 | .sta_remove = iwl_mac_sta_remove, | |
2295c66b JB |
4036 | .channel_switch = iwlagn_mac_channel_switch, |
4037 | .flush = iwlagn_mac_flush, | |
a85d7cca | 4038 | .tx_last_beacon = iwl_mac_tx_last_beacon, |
9b9190d9 JB |
4039 | .remain_on_channel = iwl_mac_remain_on_channel, |
4040 | .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel, | |
b481de9c | 4041 | }; |
ae79d23d | 4042 | #endif |
b481de9c | 4043 | |
3867fe04 WYG |
4044 | static void iwl_hw_detect(struct iwl_priv *priv) |
4045 | { | |
4046 | priv->hw_rev = _iwl_read32(priv, CSR_HW_REV); | |
4047 | priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG); | |
4048 | pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id); | |
49ded76b | 4049 | IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id); |
3867fe04 WYG |
4050 | } |
4051 | ||
07d4f1ad WYG |
4052 | static int iwl_set_hw_params(struct iwl_priv *priv) |
4053 | { | |
4054 | priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; | |
4055 | priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
4056 | if (priv->cfg->mod_params->amsdu_size_8K) | |
4057 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K); | |
4058 | else | |
4059 | priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K); | |
4060 | ||
4061 | priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL; | |
4062 | ||
4063 | if (priv->cfg->mod_params->disable_11n) | |
4064 | priv->cfg->sku &= ~IWL_SKU_N; | |
4065 | ||
4066 | /* Device-specific setup */ | |
4067 | return priv->cfg->ops->lib->set_hw_params(priv); | |
4068 | } | |
4069 | ||
e72f368b JB |
4070 | static const u8 iwlagn_bss_ac_to_fifo[] = { |
4071 | IWL_TX_FIFO_VO, | |
4072 | IWL_TX_FIFO_VI, | |
4073 | IWL_TX_FIFO_BE, | |
4074 | IWL_TX_FIFO_BK, | |
4075 | }; | |
4076 | ||
4077 | static const u8 iwlagn_bss_ac_to_queue[] = { | |
4078 | 0, 1, 2, 3, | |
4079 | }; | |
4080 | ||
4081 | static const u8 iwlagn_pan_ac_to_fifo[] = { | |
4082 | IWL_TX_FIFO_VO_IPAN, | |
4083 | IWL_TX_FIFO_VI_IPAN, | |
4084 | IWL_TX_FIFO_BE_IPAN, | |
4085 | IWL_TX_FIFO_BK_IPAN, | |
4086 | }; | |
4087 | ||
4088 | static const u8 iwlagn_pan_ac_to_queue[] = { | |
4089 | 7, 6, 5, 4, | |
4090 | }; | |
4091 | ||
5b9f8cd3 | 4092 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c | 4093 | { |
246ed355 | 4094 | int err = 0, i; |
c79dd5b5 | 4095 | struct iwl_priv *priv; |
b481de9c | 4096 | struct ieee80211_hw *hw; |
82b9a121 | 4097 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 4098 | unsigned long flags; |
c6fa17ed | 4099 | u16 pci_cmd, num_mac; |
b481de9c | 4100 | |
316c30d9 AK |
4101 | /************************ |
4102 | * 1. Allocating HW data | |
4103 | ************************/ | |
4104 | ||
6440adb5 CB |
4105 | /* Disabling hardware scan means that mac80211 will perform scans |
4106 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 4107 | if (cfg->mod_params->disable_hw_scan) { |
72645eff WYG |
4108 | dev_printk(KERN_DEBUG, &(pdev->dev), |
4109 | "sw scan support is deprecated\n"); | |
ae79d23d | 4110 | #ifdef CONFIG_IWL5000 |
dc21b545 | 4111 | iwlagn_hw_ops.hw_scan = NULL; |
ae79d23d | 4112 | #endif |
2295c66b JB |
4113 | #ifdef CONFIG_IWL4965 |
4114 | iwl4965_hw_ops.hw_scan = NULL; | |
4115 | #endif | |
b481de9c ZY |
4116 | } |
4117 | ||
dc21b545 | 4118 | hw = iwl_alloc_all(cfg); |
1d0a082d | 4119 | if (!hw) { |
b481de9c ZY |
4120 | err = -ENOMEM; |
4121 | goto out; | |
4122 | } | |
1d0a082d AK |
4123 | priv = hw->priv; |
4124 | /* At this point both hw and priv are allocated. */ | |
4125 | ||
246ed355 JB |
4126 | /* |
4127 | * The default context is always valid, | |
4128 | * more may be discovered when firmware | |
4129 | * is loaded. | |
4130 | */ | |
4131 | priv->valid_contexts = BIT(IWL_RXON_CTX_BSS); | |
4132 | ||
4133 | for (i = 0; i < NUM_IWL_RXON_CTX; i++) | |
4134 | priv->contexts[i].ctxid = i; | |
4135 | ||
763cc3bf JB |
4136 | priv->contexts[IWL_RXON_CTX_BSS].always_active = true; |
4137 | priv->contexts[IWL_RXON_CTX_BSS].is_active = true; | |
8f2d3d2a JB |
4138 | priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON; |
4139 | priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING; | |
4140 | priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC; | |
8dfdb9d5 | 4141 | priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM; |
2995bafa | 4142 | priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID; |
c10afb6e | 4143 | priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY; |
e72f368b JB |
4144 | priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo; |
4145 | priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue; | |
d0fe478c JB |
4146 | priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes = |
4147 | BIT(NL80211_IFTYPE_ADHOC); | |
4148 | priv->contexts[IWL_RXON_CTX_BSS].interface_modes = | |
4149 | BIT(NL80211_IFTYPE_STATION); | |
2295c66b | 4150 | priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP; |
d0fe478c JB |
4151 | priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS; |
4152 | priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS; | |
4153 | priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS; | |
ece9c4ee JB |
4154 | |
4155 | priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON; | |
4156 | priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING; | |
4157 | priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC; | |
4158 | priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM; | |
4159 | priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN; | |
4160 | priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY; | |
4161 | priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID; | |
4162 | priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION; | |
e72f368b JB |
4163 | priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo; |
4164 | priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue; | |
4165 | priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE; | |
d0fe478c JB |
4166 | priv->contexts[IWL_RXON_CTX_PAN].interface_modes = |
4167 | BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP); | |
f35c0c56 WYG |
4168 | #ifdef CONFIG_IWL_P2P |
4169 | priv->contexts[IWL_RXON_CTX_PAN].interface_modes |= | |
4170 | BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO); | |
4171 | #endif | |
d0fe478c JB |
4172 | priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP; |
4173 | priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA; | |
4174 | priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P; | |
ece9c4ee JB |
4175 | |
4176 | BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2); | |
8f2d3d2a | 4177 | |
b481de9c ZY |
4178 | SET_IEEE80211_DEV(hw, &pdev->dev); |
4179 | ||
e1623446 | 4180 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 4181 | priv->cfg = cfg; |
b481de9c | 4182 | priv->pci_dev = pdev; |
40cefda9 | 4183 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 4184 | |
bee008b7 WYG |
4185 | /* is antenna coupling more than 35dB ? */ |
4186 | priv->bt_ant_couple_ok = | |
4187 | (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ? | |
4188 | true : false; | |
4189 | ||
9f28ebc3 | 4190 | /* enable/disable bt channel inhibition */ |
f37837c9 | 4191 | priv->bt_ch_announce = iwlagn_bt_ch_announce; |
9f28ebc3 WYG |
4192 | IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n", |
4193 | (priv->bt_ch_announce) ? "On" : "Off"); | |
f37837c9 | 4194 | |
20594eb0 WYG |
4195 | if (iwl_alloc_traffic_mem(priv)) |
4196 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 4197 | |
316c30d9 AK |
4198 | /************************** |
4199 | * 2. Initializing PCI bus | |
4200 | **************************/ | |
1a7123cd JL |
4201 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | |
4202 | PCIE_LINK_STATE_CLKPM); | |
4203 | ||
316c30d9 AK |
4204 | if (pci_enable_device(pdev)) { |
4205 | err = -ENODEV; | |
4206 | goto out_ieee80211_free_hw; | |
4207 | } | |
4208 | ||
4209 | pci_set_master(pdev); | |
4210 | ||
093d874c | 4211 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 4212 | if (!err) |
093d874c | 4213 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 4214 | if (err) { |
093d874c | 4215 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 4216 | if (!err) |
093d874c | 4217 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 4218 | /* both attempts failed: */ |
316c30d9 | 4219 | if (err) { |
978785a3 | 4220 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 4221 | goto out_pci_disable_device; |
cc2a8ea8 | 4222 | } |
316c30d9 AK |
4223 | } |
4224 | ||
4225 | err = pci_request_regions(pdev, DRV_NAME); | |
4226 | if (err) | |
4227 | goto out_pci_disable_device; | |
4228 | ||
4229 | pci_set_drvdata(pdev, priv); | |
4230 | ||
316c30d9 AK |
4231 | |
4232 | /*********************** | |
4233 | * 3. Read REV register | |
4234 | ***********************/ | |
4235 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
4236 | if (!priv->hw_base) { | |
4237 | err = -ENODEV; | |
4238 | goto out_pci_release_regions; | |
4239 | } | |
4240 | ||
e1623446 | 4241 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 4242 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 4243 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 4244 | |
731a29b7 | 4245 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
4246 | * we should init now |
4247 | */ | |
4248 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 4249 | spin_lock_init(&priv->lock); |
4843b5a7 RC |
4250 | |
4251 | /* | |
4252 | * stop and reset the on-board processor just in case it is in a | |
4253 | * strange state ... like being left stranded by a primary kernel | |
4254 | * and this is now the kdump kernel trying to start up | |
4255 | */ | |
4256 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
4257 | ||
b661c819 | 4258 | iwl_hw_detect(priv); |
c11362c0 | 4259 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", |
b661c819 | 4260 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 4261 | |
e7b63581 TW |
4262 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
4263 | * PCI Tx retries from interfering with C3 CPU state */ | |
4264 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
4265 | ||
086ed117 MA |
4266 | iwl_prepare_card_hw(priv); |
4267 | if (!priv->hw_ready) { | |
4268 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
4269 | goto out_iounmap; | |
4270 | } | |
4271 | ||
91238714 TW |
4272 | /***************** |
4273 | * 4. Read EEPROM | |
4274 | *****************/ | |
316c30d9 AK |
4275 | /* Read the EEPROM */ |
4276 | err = iwl_eeprom_init(priv); | |
4277 | if (err) { | |
15b1687c | 4278 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
4279 | goto out_iounmap; |
4280 | } | |
8614f360 TW |
4281 | err = iwl_eeprom_check_version(priv); |
4282 | if (err) | |
c8f16138 | 4283 | goto out_free_eeprom; |
8614f360 | 4284 | |
21a5b3c6 WYG |
4285 | err = iwl_eeprom_check_sku(priv); |
4286 | if (err) | |
4287 | goto out_free_eeprom; | |
4288 | ||
02883017 | 4289 | /* extract MAC Address */ |
c6fa17ed WYG |
4290 | iwl_eeprom_get_mac(priv, priv->addresses[0].addr); |
4291 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr); | |
4292 | priv->hw->wiphy->addresses = priv->addresses; | |
4293 | priv->hw->wiphy->n_addresses = 1; | |
4294 | num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS); | |
4295 | if (num_mac > 1) { | |
4296 | memcpy(priv->addresses[1].addr, priv->addresses[0].addr, | |
4297 | ETH_ALEN); | |
4298 | priv->addresses[1].addr[5]++; | |
4299 | priv->hw->wiphy->n_addresses++; | |
4300 | } | |
316c30d9 AK |
4301 | |
4302 | /************************ | |
4303 | * 5. Setup HW constants | |
4304 | ************************/ | |
da154e30 | 4305 | if (iwl_set_hw_params(priv)) { |
15b1687c | 4306 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 4307 | goto out_free_eeprom; |
316c30d9 AK |
4308 | } |
4309 | ||
4310 | /******************* | |
6ba87956 | 4311 | * 6. Setup priv |
316c30d9 | 4312 | *******************/ |
b481de9c | 4313 | |
6ba87956 | 4314 | err = iwl_init_drv(priv); |
bf85ea4f | 4315 | if (err) |
399f4900 | 4316 | goto out_free_eeprom; |
bf85ea4f | 4317 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 4318 | |
316c30d9 | 4319 | /******************** |
09f9bf79 | 4320 | * 7. Setup services |
316c30d9 | 4321 | ********************/ |
0359facc | 4322 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 4323 | iwl_disable_interrupts(priv); |
0359facc | 4324 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 4325 | |
6cd0b1cb HS |
4326 | pci_enable_msi(priv->pci_dev); |
4327 | ||
e39fdee1 WYG |
4328 | if (priv->cfg->ops->lib->isr_ops.alloc) |
4329 | priv->cfg->ops->lib->isr_ops.alloc(priv); | |
4330 | ||
4331 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr, | |
ef850d7c | 4332 | IRQF_SHARED, DRV_NAME, priv); |
6cd0b1cb HS |
4333 | if (err) { |
4334 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
4335 | goto out_disable_msi; | |
4336 | } | |
316c30d9 | 4337 | |
4e39317d | 4338 | iwl_setup_deferred_work(priv); |
653fa4a0 | 4339 | iwl_setup_rx_handlers(priv); |
316c30d9 | 4340 | |
158bea07 JB |
4341 | /********************************************* |
4342 | * 8. Enable interrupts and read RFKILL state | |
4343 | *********************************************/ | |
6ba87956 | 4344 | |
554d1d02 | 4345 | /* enable rfkill interrupt: hw bug w/a */ |
6cd0b1cb HS |
4346 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); |
4347 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
4348 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
4349 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
4350 | } | |
4351 | ||
554d1d02 | 4352 | iwl_enable_rfkill_int(priv); |
6cd0b1cb | 4353 | |
6cd0b1cb HS |
4354 | /* If platform's RF_KILL switch is NOT set to KILL */ |
4355 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
4356 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
4357 | else | |
4358 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 4359 | |
a60e77e5 JB |
4360 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
4361 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 4362 | |
58d0f361 | 4363 | iwl_power_initialize(priv); |
39b73fb1 | 4364 | iwl_tt_initialize(priv); |
158bea07 | 4365 | |
a15707d8 | 4366 | init_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 4367 | |
b08dfd04 | 4368 | err = iwl_request_firmware(priv, true); |
158bea07 | 4369 | if (err) |
7d47618a | 4370 | goto out_destroy_workqueue; |
158bea07 | 4371 | |
b481de9c ZY |
4372 | return 0; |
4373 | ||
7d47618a | 4374 | out_destroy_workqueue: |
c8f16138 RC |
4375 | destroy_workqueue(priv->workqueue); |
4376 | priv->workqueue = NULL; | |
795cc0ad | 4377 | free_irq(priv->pci_dev->irq, priv); |
e39fdee1 WYG |
4378 | if (priv->cfg->ops->lib->isr_ops.free) |
4379 | priv->cfg->ops->lib->isr_ops.free(priv); | |
6cd0b1cb HS |
4380 | out_disable_msi: |
4381 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 4382 | iwl_uninit_drv(priv); |
073d3f5f TW |
4383 | out_free_eeprom: |
4384 | iwl_eeprom_free(priv); | |
b481de9c ZY |
4385 | out_iounmap: |
4386 | pci_iounmap(pdev, priv->hw_base); | |
4387 | out_pci_release_regions: | |
316c30d9 | 4388 | pci_set_drvdata(pdev, NULL); |
623d563e | 4389 | pci_release_regions(pdev); |
b481de9c ZY |
4390 | out_pci_disable_device: |
4391 | pci_disable_device(pdev); | |
b481de9c | 4392 | out_ieee80211_free_hw: |
20594eb0 | 4393 | iwl_free_traffic_mem(priv); |
d7c76f4c | 4394 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
4395 | out: |
4396 | return err; | |
4397 | } | |
4398 | ||
5b9f8cd3 | 4399 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 4400 | { |
c79dd5b5 | 4401 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 4402 | unsigned long flags; |
b481de9c ZY |
4403 | |
4404 | if (!priv) | |
4405 | return; | |
4406 | ||
a15707d8 | 4407 | wait_for_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 4408 | |
e1623446 | 4409 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 4410 | |
67249625 | 4411 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 4412 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 4413 | |
5b9f8cd3 EG |
4414 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
4415 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
4416 | * we need to set STATUS_EXIT_PENDING bit. |
4417 | */ | |
4418 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5ed540ae WYG |
4419 | |
4420 | iwl_leds_exit(priv); | |
4421 | ||
c4f55232 RR |
4422 | if (priv->mac80211_registered) { |
4423 | ieee80211_unregister_hw(priv->hw); | |
4424 | priv->mac80211_registered = 0; | |
0b124c31 | 4425 | } else { |
5b9f8cd3 | 4426 | iwl_down(priv); |
c4f55232 RR |
4427 | } |
4428 | ||
c166b25a BC |
4429 | /* |
4430 | * Make sure device is reset to low power before unloading driver. | |
4431 | * This may be redundant with iwl_down(), but there are paths to | |
4432 | * run iwl_down() without calling apm_ops.stop(), and there are | |
4433 | * paths to avoid running iwl_down() at all before leaving driver. | |
4434 | * This (inexpensive) call *makes sure* device is reset. | |
4435 | */ | |
14e8e4af | 4436 | iwl_apm_stop(priv); |
c166b25a | 4437 | |
39b73fb1 WYG |
4438 | iwl_tt_exit(priv); |
4439 | ||
0359facc MA |
4440 | /* make sure we flush any pending irq or |
4441 | * tasklet for the driver | |
4442 | */ | |
4443 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 4444 | iwl_disable_interrupts(priv); |
0359facc MA |
4445 | spin_unlock_irqrestore(&priv->lock, flags); |
4446 | ||
4447 | iwl_synchronize_irq(priv); | |
4448 | ||
5b9f8cd3 | 4449 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
4450 | |
4451 | if (priv->rxq.bd) | |
54b81550 | 4452 | iwlagn_rx_queue_free(priv, &priv->rxq); |
74bcdb33 | 4453 | iwlagn_hw_txq_ctx_free(priv); |
b481de9c | 4454 | |
073d3f5f | 4455 | iwl_eeprom_free(priv); |
b481de9c | 4456 | |
b481de9c | 4457 | |
948c171c MA |
4458 | /*netif_stop_queue(dev); */ |
4459 | flush_workqueue(priv->workqueue); | |
4460 | ||
5b9f8cd3 | 4461 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
4462 | * priv->workqueue... so we can't take down the workqueue |
4463 | * until now... */ | |
4464 | destroy_workqueue(priv->workqueue); | |
4465 | priv->workqueue = NULL; | |
20594eb0 | 4466 | iwl_free_traffic_mem(priv); |
b481de9c | 4467 | |
6cd0b1cb HS |
4468 | free_irq(priv->pci_dev->irq, priv); |
4469 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
4470 | pci_iounmap(pdev, priv->hw_base); |
4471 | pci_release_regions(pdev); | |
4472 | pci_disable_device(pdev); | |
4473 | pci_set_drvdata(pdev, NULL); | |
4474 | ||
6ba87956 | 4475 | iwl_uninit_drv(priv); |
b481de9c | 4476 | |
e39fdee1 WYG |
4477 | if (priv->cfg->ops->lib->isr_ops.free) |
4478 | priv->cfg->ops->lib->isr_ops.free(priv); | |
ef850d7c | 4479 | |
77834543 | 4480 | dev_kfree_skb(priv->beacon_skb); |
b481de9c ZY |
4481 | |
4482 | ieee80211_free_hw(priv->hw); | |
4483 | } | |
4484 | ||
b481de9c ZY |
4485 | |
4486 | /***************************************************************************** | |
4487 | * | |
4488 | * driver and module entry point | |
4489 | * | |
4490 | *****************************************************************************/ | |
4491 | ||
fed9017e | 4492 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
a3aa1884 | 4493 | static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = { |
4fc22b21 | 4494 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
4495 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
4496 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 4497 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 4498 | #ifdef CONFIG_IWL5000 |
ac592574 WYG |
4499 | /* 5100 Series WiFi */ |
4500 | {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */ | |
4501 | {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4502 | {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */ | |
4503 | {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4504 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4505 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4506 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */ | |
4507 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4508 | {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */ | |
4509 | {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4510 | {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */ | |
4511 | {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4512 | {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4513 | {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4514 | {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */ | |
4515 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4516 | {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */ | |
4517 | {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4518 | {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */ | |
4519 | {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4520 | {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4521 | {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4522 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */ | |
4523 | {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4524 | ||
4525 | /* 5300 Series WiFi */ | |
4526 | {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */ | |
4527 | {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4528 | {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */ | |
4529 | {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4530 | {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */ | |
4531 | {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4532 | {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */ | |
4533 | {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4534 | {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */ | |
4535 | {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4536 | {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */ | |
4537 | {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4538 | ||
4539 | /* 5350 Series WiFi/WiMax */ | |
4540 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */ | |
4541 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */ | |
4542 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */ | |
4543 | ||
4544 | /* 5150 Series Wifi/WiMax */ | |
4545 | {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */ | |
4546 | {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4547 | {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */ | |
4548 | {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
4549 | {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */ | |
4550 | {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4551 | ||
4552 | {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */ | |
4553 | {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4554 | {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */ | |
4555 | {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
5953a62e WYG |
4556 | |
4557 | /* 6x00 Series */ | |
5953a62e WYG |
4558 | {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)}, |
4559 | {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)}, | |
4560 | {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)}, | |
4561 | {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)}, | |
4562 | {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)}, | |
4563 | {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)}, | |
4564 | {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)}, | |
4565 | {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)}, | |
4566 | {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)}, | |
4567 | {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)}, | |
4b3e8062 | 4568 | |
003ea981 | 4569 | /* 6x05 Series */ |
8b3ee296 WYG |
4570 | {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)}, |
4571 | {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)}, | |
4572 | {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)}, | |
4573 | {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)}, | |
4574 | {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)}, | |
4575 | {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)}, | |
4576 | {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)}, | |
1808972f | 4577 | |
003ea981 | 4578 | /* 6x30 Series */ |
8b3ee296 WYG |
4579 | {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)}, |
4580 | {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)}, | |
4581 | {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)}, | |
4582 | {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)}, | |
4583 | {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)}, | |
4584 | {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)}, | |
4585 | {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)}, | |
4586 | {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)}, | |
4587 | {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)}, | |
4588 | {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)}, | |
4589 | {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)}, | |
4590 | {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)}, | |
4591 | {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)}, | |
4592 | {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)}, | |
4593 | {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)}, | |
4594 | {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)}, | |
5953a62e WYG |
4595 | |
4596 | /* 6x50 WiFi/WiMax Series */ | |
5953a62e WYG |
4597 | {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)}, |
4598 | {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)}, | |
4599 | {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)}, | |
4600 | {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)}, | |
5953a62e WYG |
4601 | {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)}, |
4602 | {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)}, | |
4603 | ||
003ea981 | 4604 | /* 6150 WiFi/WiMax Series */ |
8b3ee296 WYG |
4605 | {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)}, |
4606 | {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)}, | |
4607 | {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)}, | |
4608 | {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)}, | |
4609 | {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)}, | |
4610 | {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)}, | |
03264339 | 4611 | |
77dcb6a9 | 4612 | /* 1000 Series WiFi */ |
4bd0914f WYG |
4613 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
4614 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
4615 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
4616 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
4617 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
4618 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
4619 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
4620 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
4621 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
4622 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
4623 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
4624 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
1de19ecc | 4625 | |
58a39090 | 4626 | /* 100 Series WiFi */ |
1de19ecc | 4627 | {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)}, |
2a21ff44 | 4628 | {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)}, |
1de19ecc | 4629 | {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)}, |
2a21ff44 | 4630 | {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)}, |
1de19ecc | 4631 | {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)}, |
2a21ff44 | 4632 | {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)}, |
58a39090 WYG |
4633 | |
4634 | /* 130 Series WiFi */ | |
4635 | {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)}, | |
4636 | {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)}, | |
4637 | {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)}, | |
4638 | {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)}, | |
4639 | {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)}, | |
4640 | {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)}, | |
4641 | ||
04b8e751 WYG |
4642 | /* 2x00 Series */ |
4643 | {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)}, | |
4644 | {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)}, | |
4645 | {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)}, | |
4646 | {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)}, | |
4647 | {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)}, | |
4648 | {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)}, | |
4649 | ||
4650 | /* 2x30 Series */ | |
4651 | {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)}, | |
4652 | {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)}, | |
4653 | {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)}, | |
4654 | {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)}, | |
4655 | {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)}, | |
4656 | {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)}, | |
4657 | ||
4658 | /* 6x35 Series */ | |
4659 | {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)}, | |
4660 | {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)}, | |
4661 | {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)}, | |
4662 | {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)}, | |
4663 | {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)}, | |
4664 | {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)}, | |
4665 | {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)}, | |
4666 | {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)}, | |
4667 | {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)}, | |
4668 | ||
4669 | /* 200 Series */ | |
4670 | {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)}, | |
4671 | {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)}, | |
4672 | {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)}, | |
4673 | {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)}, | |
4674 | {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)}, | |
4675 | {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)}, | |
4676 | ||
4677 | /* 230 Series */ | |
4678 | {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)}, | |
4679 | {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)}, | |
4680 | {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)}, | |
4681 | {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)}, | |
4682 | {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)}, | |
4683 | {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)}, | |
4684 | ||
5a6a256e | 4685 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 4686 | |
fed9017e RR |
4687 | {0} |
4688 | }; | |
4689 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
4690 | ||
4691 | static struct pci_driver iwl_driver = { | |
b481de9c | 4692 | .name = DRV_NAME, |
fed9017e | 4693 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
4694 | .probe = iwl_pci_probe, |
4695 | .remove = __devexit_p(iwl_pci_remove), | |
f60dc013 | 4696 | .driver.pm = IWL_PM_OPS, |
b481de9c ZY |
4697 | }; |
4698 | ||
5b9f8cd3 | 4699 | static int __init iwl_init(void) |
b481de9c ZY |
4700 | { |
4701 | ||
4702 | int ret; | |
c96c31e4 JP |
4703 | pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); |
4704 | pr_info(DRV_COPYRIGHT "\n"); | |
897e1cf2 | 4705 | |
e227ceac | 4706 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 4707 | if (ret) { |
c96c31e4 | 4708 | pr_err("Unable to register rate control algorithm: %d\n", ret); |
897e1cf2 RC |
4709 | return ret; |
4710 | } | |
4711 | ||
fed9017e | 4712 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 4713 | if (ret) { |
c96c31e4 | 4714 | pr_err("Unable to initialize PCI module\n"); |
897e1cf2 | 4715 | goto error_register; |
b481de9c | 4716 | } |
b481de9c ZY |
4717 | |
4718 | return ret; | |
897e1cf2 | 4719 | |
897e1cf2 | 4720 | error_register: |
e227ceac | 4721 | iwlagn_rate_control_unregister(); |
897e1cf2 | 4722 | return ret; |
b481de9c ZY |
4723 | } |
4724 | ||
5b9f8cd3 | 4725 | static void __exit iwl_exit(void) |
b481de9c | 4726 | { |
fed9017e | 4727 | pci_unregister_driver(&iwl_driver); |
e227ceac | 4728 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
4729 | } |
4730 | ||
5b9f8cd3 EG |
4731 | module_exit(iwl_exit); |
4732 | module_init(iwl_init); | |
a562a9dd RC |
4733 | |
4734 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 4735 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); |
a562a9dd | 4736 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); |
4e30cb69 | 4737 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
4738 | MODULE_PARM_DESC(debug, "debug output mask"); |
4739 | #endif | |
4740 | ||
2b068618 WYG |
4741 | module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO); |
4742 | MODULE_PARM_DESC(swcrypto50, | |
4743 | "using crypto in software (default 0 [hardware]) (deprecated)"); | |
4744 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); | |
4745 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | |
4746 | module_param_named(queues_num50, | |
4747 | iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
4748 | MODULE_PARM_DESC(queues_num50, | |
4749 | "number of hw queues in 50xx series (deprecated)"); | |
4750 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
4751 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | |
4752 | module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
4753 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)"); | |
4754 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
4755 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | |
4756 | module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K, | |
4757 | int, S_IRUGO); | |
4758 | MODULE_PARM_DESC(amsdu_size_8K50, | |
4759 | "enable 8K amsdu size in 50XX series (deprecated)"); | |
4760 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, | |
4761 | int, S_IRUGO); | |
4762 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
4763 | module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
4764 | MODULE_PARM_DESC(fw_restart50, | |
4765 | "restart firmware in case of error (deprecated)"); | |
4766 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
4767 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | |
4768 | module_param_named( | |
4769 | disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO); | |
72645eff WYG |
4770 | MODULE_PARM_DESC(disable_hw_scan, |
4771 | "disable hardware scanning (default 0) (deprecated)"); | |
dd7a2509 JB |
4772 | |
4773 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, | |
4774 | S_IRUGO); | |
4775 | MODULE_PARM_DESC(ucode_alternative, | |
4776 | "specify ucode alternative to use from ucode file"); | |
bee008b7 WYG |
4777 | |
4778 | module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO); | |
4779 | MODULE_PARM_DESC(antenna_coupling, | |
4780 | "specify antenna coupling in dB (defualt: 0 dB)"); | |
f37837c9 | 4781 | |
9f28ebc3 WYG |
4782 | module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO); |
4783 | MODULE_PARM_DESC(bt_ch_inhibition, | |
4784 | "Disable BT channel inhibition (default: enable)"); |