iwlwifi: Add comments about MAC_ACCESS_REQ
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <ilw@linux.intel.com>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
118
8ccde88a 119 ret = iwl_check_rxon_cmd(priv);
43d59b32 120 if (ret) {
15b1687c 121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
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122 return -EINVAL;
123 }
124
0924e519
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125 /*
126 * receive commit_rxon request
127 * abort any previous channel switch if still in process
128 */
129 if (priv->switch_rxon.switch_in_progress &&
130 (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
131 IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
132 le16_to_cpu(priv->switch_rxon.channel));
133 priv->switch_rxon.switch_in_progress = false;
134 }
135
b481de9c 136 /* If we don't need to send a full RXON, we can use
5b9f8cd3 137 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 138 * and other flags for the current radio configuration. */
54559703 139 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
140 ret = iwl_send_rxon_assoc(priv);
141 if (ret) {
15b1687c 142 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 143 return ret;
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144 }
145
146 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
a643565e 147 iwl_print_rx_config_cmd(priv);
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148 return 0;
149 }
150
151 /* station table will be cleared */
152 priv->assoc_station_added = 0;
153
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154 /* If we are currently associated and the new config requires
155 * an RXON_ASSOC and the new config wants the associated mask enabled,
156 * we must clear the associated from the active configuration
157 * before we apply the new config */
43d59b32 158 if (iwl_is_associated(priv) && new_assoc) {
e1623446 159 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
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160 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
161
43d59b32 162 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 163 sizeof(struct iwl_rxon_cmd),
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164 &priv->active_rxon);
165
166 /* If the mask clearing failed then we set
167 * active_rxon back to what it was previously */
43d59b32 168 if (ret) {
b481de9c 169 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 170 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 171 return ret;
b481de9c 172 }
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173 }
174
e1623446 175 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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176 "* with%s RXON_FILTER_ASSOC_MSK\n"
177 "* channel = %d\n"
e174961c 178 "* bssid = %pM\n",
43d59b32 179 (new_assoc ? "" : "out"),
b481de9c 180 le16_to_cpu(priv->staging_rxon.channel),
e174961c 181 priv->staging_rxon.bssid_addr);
b481de9c 182
90e8e424 183 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
184
185 /* Apply the new configuration
186 * RXON unassoc clears the station table in uCode, send it before
187 * we add the bcast station. If assoc bit is set, we will send RXON
188 * after having added the bcast and bssid station.
189 */
190 if (!new_assoc) {
191 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 192 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 193 if (ret) {
15b1687c 194 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
195 return ret;
196 }
197 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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198 }
199
c587de0b 200 iwl_clear_stations_table(priv);
556f8db7 201
19cc1087 202 priv->start_calib = 0;
b481de9c 203
b481de9c 204 /* Add the broadcast address so we can send broadcast frames */
9a9ca65f 205 iwl_add_bcast_station(priv);
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206
207 /* If we have set the ASSOC_MSK and we are in BSS mode then
208 * add the IWL_AP_ID to the station rate table */
9185159d 209 if (new_assoc) {
05c914fe 210 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
211 ret = iwl_rxon_add_station(priv,
212 priv->active_rxon.bssid_addr, 1);
213 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
214 IWL_ERR(priv,
215 "Error adding AP address for TX.\n");
9185159d
TW
216 return -EIO;
217 }
218 priv->assoc_station_added = 1;
219 if (priv->default_wep_key &&
220 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
221 IWL_ERR(priv,
222 "Could not send WEP static key.\n");
b481de9c 223 }
43d59b32 224
47eef9bd
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225 /*
226 * allow CTS-to-self if possible for new association.
227 * this is relevant only for 5000 series and up,
228 * but will not damage 4965
229 */
230 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
231
43d59b32
EG
232 /* Apply the new configuration
233 * RXON assoc doesn't clear the station table in uCode,
234 */
235 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
236 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
237 if (ret) {
15b1687c 238 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
239 return ret;
240 }
241 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c 242 }
a643565e 243 iwl_print_rx_config_cmd(priv);
b481de9c 244
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245 iwl_init_sensitivity(priv);
246
247 /* If we issue a new RXON command which required a tune then we must
248 * send a new TXPOWER command or we won't be able to Tx any frames */
249 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
250 if (ret) {
15b1687c 251 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
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252 return ret;
253 }
254
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255 return 0;
256}
257
5b9f8cd3 258void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
259{
260
45823531
AK
261 if (priv->cfg->ops->hcmd->set_rxon_chain)
262 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 263 iwlcore_commit_rxon(priv);
5da4b55f
MA
264}
265
fcab423d 266static void iwl_clear_free_frames(struct iwl_priv *priv)
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267{
268 struct list_head *element;
269
e1623446 270 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
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271 priv->frames_count);
272
273 while (!list_empty(&priv->free_frames)) {
274 element = priv->free_frames.next;
275 list_del(element);
fcab423d 276 kfree(list_entry(element, struct iwl_frame, list));
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277 priv->frames_count--;
278 }
279
280 if (priv->frames_count) {
39aadf8c 281 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
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282 priv->frames_count);
283 priv->frames_count = 0;
284 }
285}
286
fcab423d 287static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 288{
fcab423d 289 struct iwl_frame *frame;
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290 struct list_head *element;
291 if (list_empty(&priv->free_frames)) {
292 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
293 if (!frame) {
15b1687c 294 IWL_ERR(priv, "Could not allocate frame!\n");
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295 return NULL;
296 }
297
298 priv->frames_count++;
299 return frame;
300 }
301
302 element = priv->free_frames.next;
303 list_del(element);
fcab423d 304 return list_entry(element, struct iwl_frame, list);
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305}
306
fcab423d 307static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
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308{
309 memset(frame, 0, sizeof(*frame));
310 list_add(&frame->list, &priv->free_frames);
311}
312
4bf64efd
TW
313static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
314 struct ieee80211_hdr *hdr,
73ec1cc2 315 int left)
b481de9c 316{
3109ece1 317 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
318 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
319 (priv->iw_mode != NL80211_IFTYPE_AP)))
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320 return 0;
321
322 if (priv->ibss_beacon->len > left)
323 return 0;
324
325 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
326
327 return priv->ibss_beacon->len;
328}
329
5b9f8cd3 330static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW
331 struct iwl_frame *frame, u8 rate)
332{
333 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
334 unsigned int frame_size;
335
336 tx_beacon_cmd = &frame->u.beacon;
337 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
338
339 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
340 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
341
342 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW
343 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
344
345 BUG_ON(frame_size > MAX_MPDU_SIZE);
346 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
347
348 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
349 tx_beacon_cmd->tx.rate_n_flags =
350 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
351 else
352 tx_beacon_cmd->tx.rate_n_flags =
353 iwl_hw_set_rate_n_flags(rate, 0);
354
355 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
356 TX_CMD_FLG_TSF_MSK |
357 TX_CMD_FLG_STA_RATE_MSK;
358
359 return sizeof(*tx_beacon_cmd) + frame_size;
360}
5b9f8cd3 361static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 362{
fcab423d 363 struct iwl_frame *frame;
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364 unsigned int frame_size;
365 int rc;
366 u8 rate;
367
fcab423d 368 frame = iwl_get_free_frame(priv);
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369
370 if (!frame) {
15b1687c 371 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
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372 "command.\n");
373 return -ENOMEM;
374 }
375
5b9f8cd3 376 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 377
5b9f8cd3 378 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 379
857485c0 380 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
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381 &frame->u.cmd[0]);
382
fcab423d 383 iwl_free_frame(priv, frame);
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384
385 return rc;
386}
387
7aaa1d79
SO
388static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
389{
390 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
391
392 dma_addr_t addr = get_unaligned_le32(&tb->lo);
393 if (sizeof(dma_addr_t) > sizeof(u32))
394 addr |=
395 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
396
397 return addr;
398}
399
400static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
401{
402 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
403
404 return le16_to_cpu(tb->hi_n_len) >> 4;
405}
406
407static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
408 dma_addr_t addr, u16 len)
409{
410 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
411 u16 hi_n_len = len << 4;
412
413 put_unaligned_le32(addr, &tb->lo);
414 if (sizeof(dma_addr_t) > sizeof(u32))
415 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
416
417 tb->hi_n_len = cpu_to_le16(hi_n_len);
418
419 tfd->num_tbs = idx + 1;
420}
421
422static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
423{
424 return tfd->num_tbs & 0x1f;
425}
426
427/**
428 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
429 * @priv - driver private data
430 * @txq - tx queue
431 *
432 * Does NOT advance any TFD circular buffer read/write indexes
433 * Does NOT free the TFD itself (which is within circular buffer)
434 */
435void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
436{
59606ffa 437 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
438 struct iwl_tfd *tfd;
439 struct pci_dev *dev = priv->pci_dev;
440 int index = txq->q.read_ptr;
441 int i;
442 int num_tbs;
443
444 tfd = &tfd_tmp[index];
445
446 /* Sanity check on number of chunks */
447 num_tbs = iwl_tfd_get_num_tbs(tfd);
448
449 if (num_tbs >= IWL_NUM_OF_TBS) {
450 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
451 /* @todo issue fatal error, it is quite serious situation */
452 return;
453 }
454
455 /* Unmap tx_cmd */
456 if (num_tbs)
457 pci_unmap_single(dev,
c2acea8e
JB
458 pci_unmap_addr(&txq->meta[index], mapping),
459 pci_unmap_len(&txq->meta[index], len),
96891cee 460 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
461
462 /* Unmap chunks, if any. */
463 for (i = 1; i < num_tbs; i++) {
464 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
465 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
466
467 if (txq->txb) {
468 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
469 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
470 }
471 }
472}
473
474int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
475 struct iwl_tx_queue *txq,
476 dma_addr_t addr, u16 len,
477 u8 reset, u8 pad)
478{
479 struct iwl_queue *q;
59606ffa 480 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
481 u32 num_tbs;
482
483 q = &txq->q;
59606ffa
SO
484 tfd_tmp = (struct iwl_tfd *)txq->tfds;
485 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
486
487 if (reset)
488 memset(tfd, 0, sizeof(*tfd));
489
490 num_tbs = iwl_tfd_get_num_tbs(tfd);
491
492 /* Each TFD can point to a maximum 20 Tx buffers */
493 if (num_tbs >= IWL_NUM_OF_TBS) {
494 IWL_ERR(priv, "Error can not send more than %d chunks\n",
495 IWL_NUM_OF_TBS);
496 return -EINVAL;
497 }
498
499 BUG_ON(addr & ~DMA_BIT_MASK(36));
500 if (unlikely(addr & ~IWL_TX_DMA_MASK))
501 IWL_ERR(priv, "Unaligned address = %llx\n",
502 (unsigned long long)addr);
503
504 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
505
506 return 0;
507}
508
a8e74e27
SO
509/*
510 * Tell nic where to find circular buffer of Tx Frame Descriptors for
511 * given Tx queue, and enable the DMA channel used for that queue.
512 *
513 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
514 * channels supported in hardware.
515 */
516int iwl_hw_tx_queue_init(struct iwl_priv *priv,
517 struct iwl_tx_queue *txq)
518{
a8e74e27
SO
519 int txq_id = txq->q.id;
520
a8e74e27
SO
521 /* Circular buffer (TFD queue in DRAM) physical base address */
522 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
523 txq->q.dma_addr >> 8);
524
a8e74e27
SO
525 return 0;
526}
527
b481de9c
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528/******************************************************************************
529 *
530 * Generic RX handler implementations
531 *
532 ******************************************************************************/
885ba202
TW
533static void iwl_rx_reply_alive(struct iwl_priv *priv,
534 struct iwl_rx_mem_buffer *rxb)
b481de9c 535{
2f301227 536 struct iwl_rx_packet *pkt = rxb_addr(rxb);
885ba202 537 struct iwl_alive_resp *palive;
b481de9c
ZY
538 struct delayed_work *pwork;
539
540 palive = &pkt->u.alive_frame;
541
e1623446 542 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
543 "0x%01X 0x%01X\n",
544 palive->is_valid, palive->ver_type,
545 palive->ver_subtype);
546
547 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 548 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
b481de9c
ZY
549 memcpy(&priv->card_alive_init,
550 &pkt->u.alive_frame,
885ba202 551 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
552 pwork = &priv->init_alive_start;
553 } else {
e1623446 554 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c 555 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 556 sizeof(struct iwl_alive_resp));
b481de9c
ZY
557 pwork = &priv->alive_start;
558 }
559
560 /* We delay the ALIVE response by 5ms to
561 * give the HW RF Kill time to activate... */
562 if (palive->is_valid == UCODE_VALID_OK)
563 queue_delayed_work(priv->workqueue, pwork,
564 msecs_to_jiffies(5));
565 else
39aadf8c 566 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
567}
568
5b9f8cd3 569static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 570{
c79dd5b5
TW
571 struct iwl_priv *priv =
572 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
573 struct sk_buff *beacon;
574
575 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 576 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
577
578 if (!beacon) {
15b1687c 579 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
580 return;
581 }
582
583 mutex_lock(&priv->mutex);
584 /* new beacon skb is allocated every time; dispose previous.*/
585 if (priv->ibss_beacon)
586 dev_kfree_skb(priv->ibss_beacon);
587
588 priv->ibss_beacon = beacon;
589 mutex_unlock(&priv->mutex);
590
5b9f8cd3 591 iwl_send_beacon_cmd(priv);
b481de9c
ZY
592}
593
4e39317d 594/**
5b9f8cd3 595 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
596 *
597 * This callback is provided in order to send a statistics request.
598 *
599 * This timer function is continually reset to execute within
600 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
601 * was received. We need to ensure we receive the statistics in order
602 * to update the temperature used for calibrating the TXPOWER.
603 */
5b9f8cd3 604static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
605{
606 struct iwl_priv *priv = (struct iwl_priv *)data;
607
608 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
609 return;
610
61780ee3
MA
611 /* dont send host command if rf-kill is on */
612 if (!iwl_is_ready_rf(priv))
613 return;
614
4e39317d
EG
615 iwl_send_statistics_request(priv, CMD_ASYNC);
616}
617
5b9f8cd3 618static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 619 struct iwl_rx_mem_buffer *rxb)
b481de9c 620{
0a6857e7 621#ifdef CONFIG_IWLWIFI_DEBUG
2f301227 622 struct iwl_rx_packet *pkt = rxb_addr(rxb);
2aa6ab86
TW
623 struct iwl4965_beacon_notif *beacon =
624 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 625 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 626
e1623446 627 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 628 "tsf %d %d rate %d\n",
25a6572c 629 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
630 beacon->beacon_notify_hdr.failure_frame,
631 le32_to_cpu(beacon->ibss_mgr_status),
632 le32_to_cpu(beacon->high_tsf),
633 le32_to_cpu(beacon->low_tsf), rate);
634#endif
635
05c914fe 636 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
637 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
638 queue_work(priv->workqueue, &priv->beacon_update);
639}
640
b481de9c
ZY
641/* Handle notification from uCode that card's power state is changing
642 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 643static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 644 struct iwl_rx_mem_buffer *rxb)
b481de9c 645{
2f301227 646 struct iwl_rx_packet *pkt = rxb_addr(rxb);
b481de9c
ZY
647 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
648 unsigned long status = priv->status;
649
e1623446 650 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
651 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
652 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
653
654 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
655 RF_CARD_DISABLED)) {
656
3395f6e9 657 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
658 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
659
a8b50a0a
MA
660 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
661 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
662
663 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 664 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 665 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 666 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 667 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 668 }
39b73fb1
WYG
669 if (flags & RF_CARD_DISABLED)
670 iwl_tt_enter_ct_kill(priv);
b481de9c 671 }
39b73fb1
WYG
672 if (!(flags & RF_CARD_DISABLED))
673 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
674
675 if (flags & HW_CARD_DISABLED)
676 set_bit(STATUS_RF_KILL_HW, &priv->status);
677 else
678 clear_bit(STATUS_RF_KILL_HW, &priv->status);
679
680
b481de9c 681 if (!(flags & RXON_CARD_DISABLED))
2a421b91 682 iwl_scan_cancel(priv);
b481de9c
ZY
683
684 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
685 test_bit(STATUS_RF_KILL_HW, &priv->status)))
686 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
687 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
688 else
689 wake_up_interruptible(&priv->wait_command_queue);
690}
691
5b9f8cd3 692int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 693{
e2e3c57b 694 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 695 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
696 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
697 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
698 ~APMG_PS_CTRL_MSK_PWR_SRC);
699 } else {
700 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
701 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
702 ~APMG_PS_CTRL_MSK_PWR_SRC);
703 }
704
a8b50a0a 705 return 0;
e2e3c57b
TW
706}
707
b481de9c 708/**
5b9f8cd3 709 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
710 *
711 * Setup the RX handlers for each of the reply types sent from the uCode
712 * to the host.
713 *
714 * This function chains into the hardware specific files for them to setup
715 * any hardware specific handlers as well.
716 */
653fa4a0 717static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 718{
885ba202 719 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
720 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
721 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 722 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 723 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
724 iwl_rx_pm_debug_statistics_notif;
725 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 726
9fbab516
BC
727 /*
728 * The same handler is used for both the REPLY to a discrete
729 * statistics request from the host as well as for the periodic
730 * statistics notifications (after received beacons) from the uCode.
b481de9c 731 */
8f91aecb
EG
732 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
733 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 734
21c339bf 735 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
736 iwl_setup_rx_scan_handlers(priv);
737
37a44211 738 /* status change handler */
5b9f8cd3 739 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 740
c1354754
TW
741 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
742 iwl_rx_missed_beacon_notif;
37a44211 743 /* Rx handlers */
1781a07f
EG
744 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
745 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
746 /* block ack */
747 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 748 /* Set up hardware specific Rx handlers */
d4789efe 749 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
750}
751
b481de9c 752/**
a55360e4 753 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
754 *
755 * Uses the priv->rx_handlers callback function array to invoke
756 * the appropriate handlers, including command responses,
757 * frame-received notifications, and other notifications.
758 */
a55360e4 759void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 760{
a55360e4 761 struct iwl_rx_mem_buffer *rxb;
db11d634 762 struct iwl_rx_packet *pkt;
a55360e4 763 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
764 u32 r, i;
765 int reclaim;
766 unsigned long flags;
5c0eef96 767 u8 fill_rx = 0;
d68ab680 768 u32 count = 8;
4752c93c 769 int total_empty;
b481de9c 770
6440adb5
CB
771 /* uCode's read index (stored in shared DRAM) indicates the last Rx
772 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 773 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
774 i = rxq->read;
775
776 /* Rx interrupt, but nothing sent from uCode */
777 if (i == r)
e1623446 778 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 779
4752c93c 780 /* calculate total frames need to be restock after handling RX */
7300515d 781 total_empty = r - rxq->write_actual;
4752c93c
MA
782 if (total_empty < 0)
783 total_empty += RX_QUEUE_SIZE;
784
785 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
786 fill_rx = 1;
787
b481de9c
ZY
788 while (i != r) {
789 rxb = rxq->queue[i];
790
9fbab516 791 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
792 * then a bug has been introduced in the queue refilling
793 * routines -- catch it here */
794 BUG_ON(rxb == NULL);
795
796 rxq->queue[i] = NULL;
797
2f301227
ZY
798 pci_unmap_page(priv->pci_dev, rxb->page_dma,
799 PAGE_SIZE << priv->hw_params.rx_page_order,
800 PCI_DMA_FROMDEVICE);
801 pkt = rxb_addr(rxb);
b481de9c 802
be1a71a1
JB
803 trace_iwlwifi_dev_rx(priv, pkt,
804 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
805
b481de9c
ZY
806 /* Reclaim a command buffer only if this packet is a response
807 * to a (driver-originated) command.
808 * If the packet (e.g. Rx frame) originated from uCode,
809 * there is no command buffer to reclaim.
810 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
811 * but apparently a few don't get set; catch them here. */
812 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
813 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 814 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 815 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 816 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
817 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
818 (pkt->hdr.cmd != REPLY_TX);
819
820 /* Based on type of command response or notification,
821 * handle those that need handling via function in
5b9f8cd3 822 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 823 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 824 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 825 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
a83b9141 826 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
29b1b268 827 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
b481de9c
ZY
828 } else {
829 /* No handling needed */
e1623446 830 IWL_DEBUG_RX(priv,
b481de9c
ZY
831 "r %d i %d No handler needed for %s, 0x%02x\n",
832 r, i, get_cmd_string(pkt->hdr.cmd),
833 pkt->hdr.cmd);
834 }
835
29b1b268
ZY
836 /*
837 * XXX: After here, we should always check rxb->page
838 * against NULL before touching it or its virtual
839 * memory (pkt). Because some rx_handler might have
840 * already taken or freed the pages.
841 */
842
b481de9c 843 if (reclaim) {
2f301227
ZY
844 /* Invoke any callbacks, transfer the buffer to caller,
845 * and fire off the (possibly) blocking iwl_send_cmd()
b481de9c 846 * as we reclaim the driver command queue */
29b1b268 847 if (rxb->page)
17b88929 848 iwl_tx_cmd_complete(priv, rxb);
b481de9c 849 else
39aadf8c 850 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
851 }
852
7300515d
ZY
853 /* Reuse the page if possible. For notification packets and
854 * SKBs that fail to Rx correctly, add them back into the
855 * rx_free list for reuse later. */
856 spin_lock_irqsave(&rxq->lock, flags);
2f301227 857 if (rxb->page != NULL) {
7300515d
ZY
858 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
859 0, PAGE_SIZE << priv->hw_params.rx_page_order,
860 PCI_DMA_FROMDEVICE);
861 list_add_tail(&rxb->list, &rxq->rx_free);
862 rxq->free_count++;
863 } else
864 list_add_tail(&rxb->list, &rxq->rx_used);
b481de9c 865
b481de9c 866 spin_unlock_irqrestore(&rxq->lock, flags);
7300515d 867
b481de9c 868 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
869 /* If there are a lot of unused frames,
870 * restock the Rx queue so ucode wont assert. */
871 if (fill_rx) {
872 count++;
873 if (count >= 8) {
7300515d 874 rxq->read = i;
4752c93c 875 iwl_rx_replenish_now(priv);
5c0eef96
MA
876 count = 0;
877 }
878 }
b481de9c
ZY
879 }
880
881 /* Backtrack one entry */
7300515d 882 rxq->read = i;
4752c93c
MA
883 if (fill_rx)
884 iwl_rx_replenish_now(priv);
885 else
886 iwl_rx_queue_restock(priv);
a55360e4 887}
a55360e4 888
0359facc
MA
889/* call this function to flush any scheduled tasklet */
890static inline void iwl_synchronize_irq(struct iwl_priv *priv)
891{
a96a27f9 892 /* wait to make sure we flush pending tasklet*/
0359facc
MA
893 synchronize_irq(priv->pci_dev->irq);
894 tasklet_kill(&priv->irq_tasklet);
895}
896
ef850d7c 897static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
898{
899 u32 inta, handled = 0;
900 u32 inta_fh;
901 unsigned long flags;
c2e61da2 902 u32 i;
0a6857e7 903#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
904 u32 inta_mask;
905#endif
906
907 spin_lock_irqsave(&priv->lock, flags);
908
909 /* Ack/clear/reset pending uCode interrupts.
910 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
911 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
912 inta = iwl_read32(priv, CSR_INT);
913 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
914
915 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
916 * Any new interrupts that happen after this, either while we're
917 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
918 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
919 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 920
0a6857e7 921#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 922 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
9fbab516 923 /* just for debug */
3395f6e9 924 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 925 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
926 inta, inta_mask, inta_fh);
927 }
928#endif
929
2f301227
ZY
930 spin_unlock_irqrestore(&priv->lock, flags);
931
b481de9c
ZY
932 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
933 * atomic, make sure that inta covers all the interrupts that
934 * we've discovered, even if FH interrupt came in just after
935 * reading CSR_INT. */
6f83eaa1 936 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 937 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 938 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
939 inta |= CSR_INT_BIT_FH_TX;
940
941 /* Now service all interrupt bits discovered above. */
942 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 943 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
944
945 /* Tell the device to stop sending interrupts */
5b9f8cd3 946 iwl_disable_interrupts(priv);
b481de9c 947
a83b9141 948 priv->isr_stats.hw++;
5b9f8cd3 949 iwl_irq_handle_error(priv);
b481de9c
ZY
950
951 handled |= CSR_INT_BIT_HW_ERR;
952
b481de9c
ZY
953 return;
954 }
955
0a6857e7 956#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 957 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
b481de9c 958 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 959 if (inta & CSR_INT_BIT_SCD) {
e1623446 960 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 961 "the frame/frames.\n");
a83b9141
WYG
962 priv->isr_stats.sch++;
963 }
b481de9c
ZY
964
965 /* Alive notification via Rx interrupt will do the real work */
a83b9141 966 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 967 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
968 priv->isr_stats.alive++;
969 }
b481de9c
ZY
970 }
971#endif
972 /* Safely ignore these bits for debug checks below */
25c03d8e 973 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 974
9fbab516 975 /* HW RF KILL switch toggled */
b481de9c
ZY
976 if (inta & CSR_INT_BIT_RF_KILL) {
977 int hw_rf_kill = 0;
3395f6e9 978 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
979 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
980 hw_rf_kill = 1;
981
4c423a2b 982 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 983 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 984
a83b9141
WYG
985 priv->isr_stats.rfkill++;
986
a9efa652 987 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
988 * the driver allows loading the ucode even if the radio
989 * is killed. Hence update the killswitch state here. The
990 * rfkill handler will care about restarting if needed.
a9efa652 991 */
6cd0b1cb
HS
992 if (!test_bit(STATUS_ALIVE, &priv->status)) {
993 if (hw_rf_kill)
994 set_bit(STATUS_RF_KILL_HW, &priv->status);
995 else
996 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 997 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 998 }
b481de9c
ZY
999
1000 handled |= CSR_INT_BIT_RF_KILL;
1001 }
1002
9fbab516 1003 /* Chip got too hot and stopped itself */
b481de9c 1004 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 1005 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 1006 priv->isr_stats.ctkill++;
b481de9c
ZY
1007 handled |= CSR_INT_BIT_CT_KILL;
1008 }
1009
1010 /* Error detected by uCode */
1011 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
1012 IWL_ERR(priv, "Microcode SW error detected. "
1013 " Restarting 0x%X.\n", inta);
a83b9141
WYG
1014 priv->isr_stats.sw++;
1015 priv->isr_stats.sw_err = inta;
5b9f8cd3 1016 iwl_irq_handle_error(priv);
b481de9c
ZY
1017 handled |= CSR_INT_BIT_SW_ERR;
1018 }
1019
c2e61da2
BC
1020 /*
1021 * uCode wakes up after power-down sleep.
1022 * Tell device about any new tx or host commands enqueued,
1023 * and about any Rx buffers made available while asleep.
1024 */
b481de9c 1025 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 1026 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1027 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
c2e61da2
BC
1028 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1029 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
a83b9141 1030 priv->isr_stats.wakeup++;
b481de9c
ZY
1031 handled |= CSR_INT_BIT_WAKEUP;
1032 }
1033
1034 /* All uCode command responses, including Tx command responses,
1035 * Rx "responses" (frame-received notification), and other
1036 * notifications from uCode come through here*/
1037 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1038 iwl_rx_handle(priv);
a83b9141 1039 priv->isr_stats.rx++;
1ed2a3d2 1040 iwl_leds_background(priv);
b481de9c
ZY
1041 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1042 }
1043
c72cd19f 1044 /* This "Tx" DMA channel is used only for loading uCode */
b481de9c 1045 if (inta & CSR_INT_BIT_FH_TX) {
c72cd19f 1046 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
a83b9141 1047 priv->isr_stats.tx++;
b481de9c 1048 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1049 /* Wake up uCode load routine, now that load is complete */
dbb983b7
RR
1050 priv->ucode_write_complete = 1;
1051 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1052 }
1053
a83b9141 1054 if (inta & ~handled) {
15b1687c 1055 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1056 priv->isr_stats.unhandled++;
1057 }
b481de9c 1058
40cefda9 1059 if (inta & ~(priv->inta_mask)) {
39aadf8c 1060 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1061 inta & ~priv->inta_mask);
39aadf8c 1062 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1063 }
1064
1065 /* Re-enable all interrupts */
0359facc
MA
1066 /* only Re-enable if diabled by irq */
1067 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1068 iwl_enable_interrupts(priv);
b481de9c 1069
0a6857e7 1070#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1071 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
3395f6e9
TW
1072 inta = iwl_read32(priv, CSR_INT);
1073 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1074 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1075 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1076 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1077 }
1078#endif
b481de9c
ZY
1079}
1080
ef850d7c
MA
1081/* tasklet for iwlagn interrupt */
1082static void iwl_irq_tasklet(struct iwl_priv *priv)
1083{
1084 u32 inta = 0;
1085 u32 handled = 0;
1086 unsigned long flags;
1087#ifdef CONFIG_IWLWIFI_DEBUG
1088 u32 inta_mask;
1089#endif
1090
1091 spin_lock_irqsave(&priv->lock, flags);
1092
1093 /* Ack/clear/reset pending uCode interrupts.
1094 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1095 */
1096 iwl_write32(priv, CSR_INT, priv->inta);
1097
1098 inta = priv->inta;
1099
1100#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1101 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
ef850d7c
MA
1102 /* just for debug */
1103 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1104 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1105 inta, inta_mask);
1106 }
1107#endif
2f301227
ZY
1108
1109 spin_unlock_irqrestore(&priv->lock, flags);
1110
ef850d7c
MA
1111 /* saved interrupt in inta variable now we can reset priv->inta */
1112 priv->inta = 0;
1113
1114 /* Now service all interrupt bits discovered above. */
1115 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1116 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1117
1118 /* Tell the device to stop sending interrupts */
1119 iwl_disable_interrupts(priv);
1120
1121 priv->isr_stats.hw++;
1122 iwl_irq_handle_error(priv);
1123
1124 handled |= CSR_INT_BIT_HW_ERR;
1125
ef850d7c
MA
1126 return;
1127 }
1128
1129#ifdef CONFIG_IWLWIFI_DEBUG
3d816c77 1130 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
ef850d7c
MA
1131 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1132 if (inta & CSR_INT_BIT_SCD) {
1133 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1134 "the frame/frames.\n");
1135 priv->isr_stats.sch++;
1136 }
1137
1138 /* Alive notification via Rx interrupt will do the real work */
1139 if (inta & CSR_INT_BIT_ALIVE) {
1140 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1141 priv->isr_stats.alive++;
1142 }
1143 }
1144#endif
1145 /* Safely ignore these bits for debug checks below */
1146 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1147
1148 /* HW RF KILL switch toggled */
1149 if (inta & CSR_INT_BIT_RF_KILL) {
1150 int hw_rf_kill = 0;
1151 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1152 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1153 hw_rf_kill = 1;
1154
4c423a2b 1155 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1156 hw_rf_kill ? "disable radio" : "enable radio");
1157
1158 priv->isr_stats.rfkill++;
1159
1160 /* driver only loads ucode once setting the interface up.
1161 * the driver allows loading the ucode even if the radio
1162 * is killed. Hence update the killswitch state here. The
1163 * rfkill handler will care about restarting if needed.
1164 */
1165 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1166 if (hw_rf_kill)
1167 set_bit(STATUS_RF_KILL_HW, &priv->status);
1168 else
1169 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1170 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1171 }
1172
1173 handled |= CSR_INT_BIT_RF_KILL;
1174 }
1175
1176 /* Chip got too hot and stopped itself */
1177 if (inta & CSR_INT_BIT_CT_KILL) {
1178 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1179 priv->isr_stats.ctkill++;
1180 handled |= CSR_INT_BIT_CT_KILL;
1181 }
1182
1183 /* Error detected by uCode */
1184 if (inta & CSR_INT_BIT_SW_ERR) {
1185 IWL_ERR(priv, "Microcode SW error detected. "
1186 " Restarting 0x%X.\n", inta);
1187 priv->isr_stats.sw++;
1188 priv->isr_stats.sw_err = inta;
1189 iwl_irq_handle_error(priv);
1190 handled |= CSR_INT_BIT_SW_ERR;
1191 }
1192
1193 /* uCode wakes up after power-down sleep */
1194 if (inta & CSR_INT_BIT_WAKEUP) {
1195 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1196 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1197 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1198 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1199 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1200 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1201 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1202 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1203
1204 priv->isr_stats.wakeup++;
1205
1206 handled |= CSR_INT_BIT_WAKEUP;
1207 }
1208
1209 /* All uCode command responses, including Tx command responses,
1210 * Rx "responses" (frame-received notification), and other
1211 * notifications from uCode come through here*/
40cefda9
MA
1212 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1213 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1214 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1215 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1216 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1217 iwl_write32(priv, CSR_FH_INT_STATUS,
1218 CSR49_FH_INT_RX_MASK);
1219 }
1220 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1221 handled |= CSR_INT_BIT_RX_PERIODIC;
1222 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1223 }
1224 /* Sending RX interrupt require many steps to be done in the
1225 * the device:
1226 * 1- write interrupt to current index in ICT table.
1227 * 2- dma RX frame.
1228 * 3- update RX shared data to indicate last write index.
1229 * 4- send interrupt.
1230 * This could lead to RX race, driver could receive RX interrupt
1231 * but the shared data changes does not reflect this.
1232 * this could lead to RX race, RX periodic will solve this race
1233 */
1234 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1235 CSR_INT_PERIODIC_DIS);
ef850d7c 1236 iwl_rx_handle(priv);
40cefda9
MA
1237 /* Only set RX periodic if real RX is received. */
1238 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1239 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1240 CSR_INT_PERIODIC_ENA);
1241
ef850d7c 1242 priv->isr_stats.rx++;
1ed2a3d2 1243 iwl_leds_background(priv);
ef850d7c
MA
1244 }
1245
c72cd19f 1246 /* This "Tx" DMA channel is used only for loading uCode */
ef850d7c
MA
1247 if (inta & CSR_INT_BIT_FH_TX) {
1248 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
c72cd19f 1249 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
ef850d7c
MA
1250 priv->isr_stats.tx++;
1251 handled |= CSR_INT_BIT_FH_TX;
c72cd19f 1252 /* Wake up uCode load routine, now that load is complete */
ef850d7c
MA
1253 priv->ucode_write_complete = 1;
1254 wake_up_interruptible(&priv->wait_command_queue);
1255 }
1256
1257 if (inta & ~handled) {
1258 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1259 priv->isr_stats.unhandled++;
1260 }
1261
40cefda9 1262 if (inta & ~(priv->inta_mask)) {
ef850d7c 1263 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1264 inta & ~priv->inta_mask);
ef850d7c
MA
1265 }
1266
ef850d7c
MA
1267 /* Re-enable all interrupts */
1268 /* only Re-enable if diabled by irq */
1269 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1270 iwl_enable_interrupts(priv);
ef850d7c
MA
1271}
1272
a83b9141 1273
b481de9c
ZY
1274/******************************************************************************
1275 *
1276 * uCode download functions
1277 *
1278 ******************************************************************************/
1279
5b9f8cd3 1280static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1281{
98c92211
TW
1282 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1283 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1284 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1285 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1286 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1287 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1288}
1289
5b9f8cd3 1290static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1291{
1292 /* Remove all resets to allow NIC to operate */
1293 iwl_write32(priv, CSR_RESET, 0);
1294}
1295
1296
b481de9c 1297/**
5b9f8cd3 1298 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1299 *
1300 * Copy into buffers for card to fetch via bus-mastering
1301 */
5b9f8cd3 1302static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1303{
cc0f555d 1304 struct iwl_ucode_header *ucode;
a0987a8d 1305 int ret = -EINVAL, index;
b481de9c 1306 const struct firmware *ucode_raw;
a0987a8d
RC
1307 const char *name_pre = priv->cfg->fw_name_pre;
1308 const unsigned int api_max = priv->cfg->ucode_api_max;
1309 const unsigned int api_min = priv->cfg->ucode_api_min;
1310 char buf[25];
b481de9c
ZY
1311 u8 *src;
1312 size_t len;
cc0f555d
JS
1313 u32 api_ver, build;
1314 u32 inst_size, data_size, init_size, init_data_size, boot_size;
abdc2d62 1315 u16 eeprom_ver;
b481de9c
ZY
1316
1317 /* Ask kernel firmware_class module to get the boot firmware off disk.
1318 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1319 for (index = api_max; index >= api_min; index--) {
1320 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1321 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1322 if (ret < 0) {
15b1687c 1323 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1324 buf, ret);
1325 if (ret == -ENOENT)
1326 continue;
1327 else
1328 goto error;
1329 } else {
1330 if (index < api_max)
15b1687c
WT
1331 IWL_ERR(priv, "Loaded firmware %s, "
1332 "which is deprecated. "
1333 "Please use API v%u instead.\n",
a0987a8d 1334 buf, api_max);
15b1687c 1335
e1623446 1336 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1337 buf, ucode_raw->size);
1338 break;
1339 }
b481de9c
ZY
1340 }
1341
a0987a8d
RC
1342 if (ret < 0)
1343 goto error;
b481de9c 1344
cc0f555d
JS
1345 /* Make sure that we got at least the v1 header! */
1346 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1347 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1348 ret = -EINVAL;
b481de9c
ZY
1349 goto err_release;
1350 }
1351
1352 /* Data from ucode file: header followed by uCode images */
cc0f555d 1353 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1354
c02b3acd 1355 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1356 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1357 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1358 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1359 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1360 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1361 init_data_size =
1362 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1363 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1364 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1365
a0987a8d
RC
1366 /* api_ver should match the api version forming part of the
1367 * firmware filename ... but we don't check for that and only rely
877d0310 1368 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1369
1370 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1371 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1372 "Driver supports v%u, firmware is v%u.\n",
1373 api_max, api_ver);
1374 priv->ucode_ver = 0;
1375 ret = -EINVAL;
1376 goto err_release;
1377 }
1378 if (api_ver != api_max)
978785a3 1379 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1380 "got v%u. New firmware can be obtained "
1381 "from http://www.intellinuxwireless.org.\n",
1382 api_max, api_ver);
1383
978785a3
TW
1384 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1385 IWL_UCODE_MAJOR(priv->ucode_ver),
1386 IWL_UCODE_MINOR(priv->ucode_ver),
1387 IWL_UCODE_API(priv->ucode_ver),
1388 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1389
5ebeb5a6
RC
1390 snprintf(priv->hw->wiphy->fw_version,
1391 sizeof(priv->hw->wiphy->fw_version),
1392 "%u.%u.%u.%u",
1393 IWL_UCODE_MAJOR(priv->ucode_ver),
1394 IWL_UCODE_MINOR(priv->ucode_ver),
1395 IWL_UCODE_API(priv->ucode_ver),
1396 IWL_UCODE_SERIAL(priv->ucode_ver));
1397
cc0f555d
JS
1398 if (build)
1399 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1400
abdc2d62
JS
1401 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1402 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1403 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1404 ? "OTP" : "EEPROM", eeprom_ver);
1405
e1623446 1406 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1407 priv->ucode_ver);
e1623446 1408 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1409 inst_size);
e1623446 1410 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1411 data_size);
e1623446 1412 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1413 init_size);
e1623446 1414 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1415 init_data_size);
e1623446 1416 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1417 boot_size);
1418
1419 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1420 if (ucode_raw->size !=
1421 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1422 inst_size + data_size + init_size +
1423 init_data_size + boot_size) {
1424
cc0f555d
JS
1425 IWL_DEBUG_INFO(priv,
1426 "uCode file size %d does not match expected size\n",
1427 (int)ucode_raw->size);
90e759d1 1428 ret = -EINVAL;
b481de9c
ZY
1429 goto err_release;
1430 }
1431
1432 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1433 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1434 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1435 inst_size);
1436 ret = -EINVAL;
b481de9c
ZY
1437 goto err_release;
1438 }
1439
099b40b7 1440 if (data_size > priv->hw_params.max_data_size) {
e1623446 1441 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1442 data_size);
1443 ret = -EINVAL;
b481de9c
ZY
1444 goto err_release;
1445 }
099b40b7 1446 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1447 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1448 init_size);
90e759d1 1449 ret = -EINVAL;
b481de9c
ZY
1450 goto err_release;
1451 }
099b40b7 1452 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1453 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1454 init_data_size);
1455 ret = -EINVAL;
b481de9c
ZY
1456 goto err_release;
1457 }
099b40b7 1458 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1459 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1460 boot_size);
90e759d1 1461 ret = -EINVAL;
b481de9c
ZY
1462 goto err_release;
1463 }
1464
1465 /* Allocate ucode buffers for card's bus-master loading ... */
1466
1467 /* Runtime instructions and 2 copies of data:
1468 * 1) unmodified from disk
1469 * 2) backup cache for save/restore during power-downs */
1470 priv->ucode_code.len = inst_size;
98c92211 1471 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1472
1473 priv->ucode_data.len = data_size;
98c92211 1474 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1475
1476 priv->ucode_data_backup.len = data_size;
98c92211 1477 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1478
1f304e4e
ZY
1479 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1480 !priv->ucode_data_backup.v_addr)
1481 goto err_pci_alloc;
1482
b481de9c 1483 /* Initialization instructions and data */
90e759d1
TW
1484 if (init_size && init_data_size) {
1485 priv->ucode_init.len = init_size;
98c92211 1486 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1487
1488 priv->ucode_init_data.len = init_data_size;
98c92211 1489 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1490
1491 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1492 goto err_pci_alloc;
1493 }
b481de9c
ZY
1494
1495 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1496 if (boot_size) {
1497 priv->ucode_boot.len = boot_size;
98c92211 1498 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1499
90e759d1
TW
1500 if (!priv->ucode_boot.v_addr)
1501 goto err_pci_alloc;
1502 }
b481de9c
ZY
1503
1504 /* Copy images into buffers for card's bus-master reads ... */
1505
1506 /* Runtime instructions (first block of data in file) */
cc0f555d 1507 len = inst_size;
e1623446 1508 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1509 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1510 src += len;
1511
e1623446 1512 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1513 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1514
1515 /* Runtime data (2nd block)
5b9f8cd3 1516 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1517 len = data_size;
e1623446 1518 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1519 memcpy(priv->ucode_data.v_addr, src, len);
1520 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1521 src += len;
b481de9c
ZY
1522
1523 /* Initialization instructions (3rd block) */
1524 if (init_size) {
cc0f555d 1525 len = init_size;
e1623446 1526 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1527 len);
b481de9c 1528 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1529 src += len;
b481de9c
ZY
1530 }
1531
1532 /* Initialization data (4th block) */
1533 if (init_data_size) {
cc0f555d 1534 len = init_data_size;
e1623446 1535 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1536 len);
b481de9c 1537 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1538 src += len;
b481de9c
ZY
1539 }
1540
1541 /* Bootstrap instructions (5th block) */
cc0f555d 1542 len = boot_size;
e1623446 1543 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1544 memcpy(priv->ucode_boot.v_addr, src, len);
1545
1546 /* We have our copies now, allow OS release its copies */
1547 release_firmware(ucode_raw);
1548 return 0;
1549
1550 err_pci_alloc:
15b1687c 1551 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1552 ret = -ENOMEM;
5b9f8cd3 1553 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1554
1555 err_release:
1556 release_firmware(ucode_raw);
1557
1558 error:
90e759d1 1559 return ret;
b481de9c
ZY
1560}
1561
b7a79404
RC
1562#ifdef CONFIG_IWLWIFI_DEBUG
1563static const char *desc_lookup_text[] = {
1564 "OK",
1565 "FAIL",
1566 "BAD_PARAM",
1567 "BAD_CHECKSUM",
1568 "NMI_INTERRUPT_WDG",
1569 "SYSASSERT",
1570 "FATAL_ERROR",
1571 "BAD_COMMAND",
1572 "HW_ERROR_TUNE_LOCK",
1573 "HW_ERROR_TEMPERATURE",
1574 "ILLEGAL_CHAN_FREQ",
1575 "VCC_NOT_STABLE",
1576 "FH_ERROR",
1577 "NMI_INTERRUPT_HOST",
1578 "NMI_INTERRUPT_ACTION_PT",
1579 "NMI_INTERRUPT_UNKNOWN",
1580 "UCODE_VERSION_MISMATCH",
1581 "HW_ERROR_ABS_LOCK",
1582 "HW_ERROR_CAL_LOCK_FAIL",
1583 "NMI_INTERRUPT_INST_ACTION_PT",
1584 "NMI_INTERRUPT_DATA_ACTION_PT",
1585 "NMI_TRM_HW_ER",
1586 "NMI_INTERRUPT_TRM",
1587 "NMI_INTERRUPT_BREAK_POINT"
1588 "DEBUG_0",
1589 "DEBUG_1",
1590 "DEBUG_2",
1591 "DEBUG_3",
1592 "UNKNOWN"
1593};
1594
1595static const char *desc_lookup(int i)
1596{
1597 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1598
1599 if (i < 0 || i > max)
1600 i = max;
1601
1602 return desc_lookup_text[i];
1603}
1604
1605#define ERROR_START_OFFSET (1 * sizeof(u32))
1606#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1607
1608void iwl_dump_nic_error_log(struct iwl_priv *priv)
1609{
1610 u32 data2, line;
1611 u32 desc, time, count, base, data1;
1612 u32 blink1, blink2, ilink1, ilink2;
1613
1614 if (priv->ucode_type == UCODE_INIT)
1615 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1616 else
1617 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1618
1619 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1620 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1621 return;
1622 }
1623
1624 count = iwl_read_targ_mem(priv, base);
1625
1626 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1627 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1628 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1629 priv->status, count);
1630 }
1631
1632 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1633 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1634 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1635 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1636 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1637 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1638 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1639 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1640 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1641
be1a71a1
JB
1642 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1643 blink1, blink2, ilink1, ilink2);
1644
b7a79404
RC
1645 IWL_ERR(priv, "Desc Time "
1646 "data1 data2 line\n");
1647 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1648 desc_lookup(desc), desc, time, data1, data2, line);
1649 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1650 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1651 ilink1, ilink2);
1652
1653}
1654
1655#define EVENT_START_OFFSET (4 * sizeof(u32))
1656
1657/**
1658 * iwl_print_event_log - Dump error event log to syslog
1659 *
1660 */
1661static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1662 u32 num_events, u32 mode)
1663{
1664 u32 i;
1665 u32 base; /* SRAM byte address of event log header */
1666 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1667 u32 ptr; /* SRAM byte address of log data */
1668 u32 ev, time, data; /* event log data */
e5854471 1669 unsigned long reg_flags;
b7a79404
RC
1670
1671 if (num_events == 0)
1672 return;
1673 if (priv->ucode_type == UCODE_INIT)
1674 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1675 else
1676 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1677
1678 if (mode == 0)
1679 event_size = 2 * sizeof(u32);
1680 else
1681 event_size = 3 * sizeof(u32);
1682
1683 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1684
e5854471
BC
1685 /* Make sure device is powered up for SRAM reads */
1686 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1687 iwl_grab_nic_access(priv);
1688
1689 /* Set starting address; reads will auto-increment */
1690 _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
1691 rmb();
1692
b7a79404
RC
1693 /* "time" is actually "data" for mode 0 (no timestamp).
1694 * place event id # at far right for easier visual parsing. */
1695 for (i = 0; i < num_events; i++) {
e5854471
BC
1696 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1697 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1698 if (mode == 0) {
1699 /* data, ev */
be1a71a1 1700 trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
b7a79404
RC
1701 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1702 } else {
e5854471 1703 data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
b7a79404
RC
1704 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1705 time, data, ev);
be1a71a1 1706 trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
b7a79404
RC
1707 }
1708 }
e5854471
BC
1709
1710 /* Allow device to power down */
1711 iwl_release_nic_access(priv);
1712 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
b7a79404
RC
1713}
1714
84c40692
BC
1715/* For sanity check only. Actual size is determined by uCode, typ. 512 */
1716#define MAX_EVENT_LOG_SIZE (512)
1717
b7a79404
RC
1718void iwl_dump_nic_event_log(struct iwl_priv *priv)
1719{
1720 u32 base; /* SRAM byte address of event log header */
1721 u32 capacity; /* event log capacity in # entries */
1722 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1723 u32 num_wraps; /* # times uCode wrapped to top of log */
1724 u32 next_entry; /* index of next entry to be written by uCode */
1725 u32 size; /* # entries that we'll print */
1726
1727 if (priv->ucode_type == UCODE_INIT)
1728 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1729 else
1730 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1731
1732 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1733 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1734 return;
1735 }
1736
1737 /* event log header */
1738 capacity = iwl_read_targ_mem(priv, base);
1739 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1740 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1741 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1742
84c40692
BC
1743 if (capacity > MAX_EVENT_LOG_SIZE) {
1744 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
1745 capacity, MAX_EVENT_LOG_SIZE);
1746 capacity = MAX_EVENT_LOG_SIZE;
1747 }
1748
1749 if (next_entry > MAX_EVENT_LOG_SIZE) {
1750 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
1751 next_entry, MAX_EVENT_LOG_SIZE);
1752 next_entry = MAX_EVENT_LOG_SIZE;
1753 }
1754
b7a79404
RC
1755 size = num_wraps ? capacity : next_entry;
1756
1757 /* bail out if nothing in log */
1758 if (size == 0) {
1759 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1760 return;
1761 }
1762
1763 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1764 size, num_wraps);
1765
1766 /* if uCode has wrapped back to top of log, start at the oldest entry,
1767 * i.e the next one that uCode would fill. */
1768 if (num_wraps)
1769 iwl_print_event_log(priv, next_entry,
1770 capacity - next_entry, mode);
1771 /* (then/else) start at top of log */
1772 iwl_print_event_log(priv, 0, next_entry, mode);
1773
1774}
1775#endif
1776
b481de9c 1777/**
4a4a9e81 1778 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1779 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1780 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1781 */
4a4a9e81 1782static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1783{
57aab75a 1784 int ret = 0;
b481de9c 1785
e1623446 1786 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1787
1788 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1789 /* We had an error bringing up the hardware, so take it
1790 * all the way back down so we can try again */
e1623446 1791 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1792 goto restart;
1793 }
1794
1795 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1796 * This is a paranoid check, because we would not have gotten the
1797 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1798 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1799 /* Runtime instruction load was bad;
1800 * take it all the way back down so we can try again */
e1623446 1801 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1802 goto restart;
1803 }
1804
c587de0b 1805 iwl_clear_stations_table(priv);
57aab75a
TW
1806 ret = priv->cfg->ops->lib->alive_notify(priv);
1807 if (ret) {
39aadf8c
WT
1808 IWL_WARN(priv,
1809 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1810 goto restart;
1811 }
1812
5b9f8cd3 1813 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1814 set_bit(STATUS_ALIVE, &priv->status);
1815
fee1247a 1816 if (iwl_is_rfkill(priv))
b481de9c
ZY
1817 return;
1818
36d6825b 1819 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1820
1821 priv->active_rate = priv->rates_mask;
1822 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1823
2f748dec
WYG
1824 /* Configure Tx antenna selection based on H/W config */
1825 if (priv->cfg->ops->hcmd->set_tx_ant)
1826 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
1827
3109ece1 1828 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1829 struct iwl_rxon_cmd *active_rxon =
1830 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1831 /* apply any changes in staging */
1832 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1833 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1834 } else {
1835 /* Initialize our rx_config data */
5b9f8cd3 1836 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1837
1838 if (priv->cfg->ops->hcmd->set_rxon_chain)
1839 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1840
b481de9c
ZY
1841 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1842 }
1843
9fbab516 1844 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1845 iwl_send_bt_config(priv);
b481de9c 1846
4a4a9e81
TW
1847 iwl_reset_run_time_calib(priv);
1848
b481de9c 1849 /* Configure the adapter for unassociated operation */
e0158e61 1850 iwlcore_commit_rxon(priv);
b481de9c
ZY
1851
1852 /* At this point, the NIC is initialized and operational */
47f4a587 1853 iwl_rf_kill_ct_config(priv);
5a66926a 1854
e932a609 1855 iwl_leds_init(priv);
fe00b5a5 1856
e1623446 1857 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1858 set_bit(STATUS_READY, &priv->status);
5a66926a 1859 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1860
e312c24c 1861 iwl_power_update_mode(priv, true);
c46fbefa 1862
ada17513
MA
1863 /* reassociate for ADHOC mode */
1864 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1865 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1866 priv->vif);
1867 if (beacon)
1868 iwl_mac_beacon_update(priv->hw, beacon);
1869 }
1870
1871
c46fbefa 1872 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1873 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1874
b481de9c
ZY
1875 return;
1876
1877 restart:
1878 queue_work(priv->workqueue, &priv->restart);
1879}
1880
4e39317d 1881static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1882
5b9f8cd3 1883static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1884{
1885 unsigned long flags;
1886 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1887
e1623446 1888 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1889
b481de9c
ZY
1890 if (!exit_pending)
1891 set_bit(STATUS_EXIT_PENDING, &priv->status);
1892
c587de0b 1893 iwl_clear_stations_table(priv);
b481de9c
ZY
1894
1895 /* Unblock any waiting calls */
1896 wake_up_interruptible_all(&priv->wait_command_queue);
1897
b481de9c
ZY
1898 /* Wipe out the EXIT_PENDING status bit if we are not actually
1899 * exiting the module */
1900 if (!exit_pending)
1901 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1902
1903 /* stop and reset the on-board processor */
3395f6e9 1904 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1905
1906 /* tell the device to stop sending interrupts */
0359facc 1907 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1908 iwl_disable_interrupts(priv);
0359facc
MA
1909 spin_unlock_irqrestore(&priv->lock, flags);
1910 iwl_synchronize_irq(priv);
b481de9c
ZY
1911
1912 if (priv->mac80211_registered)
1913 ieee80211_stop_queues(priv->hw);
1914
5b9f8cd3 1915 /* If we have not previously called iwl_init() then
a60e77e5 1916 * clear all bits but the RF Kill bit and return */
fee1247a 1917 if (!iwl_is_init(priv)) {
b481de9c
ZY
1918 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1919 STATUS_RF_KILL_HW |
9788864e
RC
1920 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1921 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1922 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1923 STATUS_EXIT_PENDING;
b481de9c
ZY
1924 goto exit;
1925 }
1926
6da3a13e 1927 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 1928 * bit and continue taking the NIC down. */
b481de9c
ZY
1929 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1930 STATUS_RF_KILL_HW |
9788864e
RC
1931 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1932 STATUS_GEO_CONFIGURED |
b481de9c 1933 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1934 STATUS_FW_ERROR |
1935 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1936 STATUS_EXIT_PENDING;
b481de9c 1937
ef850d7c
MA
1938 /* device going down, Stop using ICT table */
1939 iwl_disable_ict(priv);
b481de9c 1940 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1941 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1942 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
1943 spin_unlock_irqrestore(&priv->lock, flags);
1944
da1bc453 1945 iwl_txq_ctx_stop(priv);
b3bbacb7 1946 iwl_rxq_stop(priv);
b481de9c 1947
a8b50a0a
MA
1948 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1949 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
1950
1951 udelay(5);
1952
4d2ccdb9
BC
1953 /* Stop the device, and put it in low power state */
1954 priv->cfg->ops->lib->apm_ops.stop(priv);
1955
b481de9c 1956 exit:
885ba202 1957 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1958
1959 if (priv->ibss_beacon)
1960 dev_kfree_skb(priv->ibss_beacon);
1961 priv->ibss_beacon = NULL;
1962
1963 /* clear out any free frames */
fcab423d 1964 iwl_clear_free_frames(priv);
b481de9c
ZY
1965}
1966
5b9f8cd3 1967static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1968{
1969 mutex_lock(&priv->mutex);
5b9f8cd3 1970 __iwl_down(priv);
b481de9c 1971 mutex_unlock(&priv->mutex);
b24d22b1 1972
4e39317d 1973 iwl_cancel_deferred_work(priv);
b481de9c
ZY
1974}
1975
086ed117
MA
1976#define HW_READY_TIMEOUT (50)
1977
1978static int iwl_set_hw_ready(struct iwl_priv *priv)
1979{
1980 int ret = 0;
1981
1982 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1983 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1984
1985 /* See if we got it */
1986 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1987 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1988 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1989 HW_READY_TIMEOUT);
1990 if (ret != -ETIMEDOUT)
1991 priv->hw_ready = true;
1992 else
1993 priv->hw_ready = false;
1994
1995 IWL_DEBUG_INFO(priv, "hardware %s\n",
1996 (priv->hw_ready == 1) ? "ready" : "not ready");
1997 return ret;
1998}
1999
2000static int iwl_prepare_card_hw(struct iwl_priv *priv)
2001{
2002 int ret = 0;
2003
2004 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
2005
3354a0f6
MA
2006 ret = iwl_set_hw_ready(priv);
2007 if (priv->hw_ready)
2008 return ret;
2009
2010 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
2011 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2012 CSR_HW_IF_CONFIG_REG_PREPARE);
2013
2014 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2015 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2016 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2017
3354a0f6 2018 /* HW should be ready by now, check again. */
086ed117
MA
2019 if (ret != -ETIMEDOUT)
2020 iwl_set_hw_ready(priv);
2021
2022 return ret;
2023}
2024
b481de9c
ZY
2025#define MAX_HW_RESTARTS 5
2026
5b9f8cd3 2027static int __iwl_up(struct iwl_priv *priv)
b481de9c 2028{
57aab75a
TW
2029 int i;
2030 int ret;
b481de9c
ZY
2031
2032 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 2033 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
2034 return -EIO;
2035 }
2036
e903fbd4 2037 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 2038 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
2039 return -EIO;
2040 }
2041
086ed117
MA
2042 iwl_prepare_card_hw(priv);
2043
2044 if (!priv->hw_ready) {
2045 IWL_WARN(priv, "Exit HW not ready\n");
2046 return -EIO;
2047 }
2048
e655b9f0 2049 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 2050 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 2051 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2052 else
e655b9f0 2053 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 2054
c1842d61 2055 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
2056 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2057
5b9f8cd3 2058 iwl_enable_interrupts(priv);
a60e77e5 2059 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 2060 return 0;
b481de9c
ZY
2061 }
2062
3395f6e9 2063 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 2064
1053d35f 2065 ret = iwl_hw_nic_init(priv);
57aab75a 2066 if (ret) {
15b1687c 2067 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 2068 return ret;
b481de9c
ZY
2069 }
2070
2071 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
2072 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2073 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
2074 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2075
2076 /* clear (again), then enable host interrupts */
3395f6e9 2077 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 2078 iwl_enable_interrupts(priv);
b481de9c
ZY
2079
2080 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
2081 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2082 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
2083
2084 /* Copy original ucode data image from disk into backup cache.
2085 * This will be used to initialize the on-board processor's
2086 * data SRAM for a clean start when the runtime program first loads. */
2087 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 2088 priv->ucode_data.len);
b481de9c 2089
b481de9c
ZY
2090 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2091
c587de0b 2092 iwl_clear_stations_table(priv);
b481de9c
ZY
2093
2094 /* load bootstrap state machine,
2095 * load bootstrap program into processor's memory,
2096 * prepare to load the "initialize" uCode */
57aab75a 2097 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 2098
57aab75a 2099 if (ret) {
15b1687c
WT
2100 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2101 ret);
b481de9c
ZY
2102 continue;
2103 }
2104
2105 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 2106 iwl_nic_start(priv);
b481de9c 2107
e1623446 2108 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
2109
2110 return 0;
2111 }
2112
2113 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 2114 __iwl_down(priv);
64e72c3e 2115 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
2116
2117 /* tried to restart and config the device for as long as our
2118 * patience could withstand */
15b1687c 2119 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
2120 return -EIO;
2121}
2122
2123
2124/*****************************************************************************
2125 *
2126 * Workqueue callbacks
2127 *
2128 *****************************************************************************/
2129
4a4a9e81 2130static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 2131{
c79dd5b5
TW
2132 struct iwl_priv *priv =
2133 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
2134
2135 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2136 return;
2137
2138 mutex_lock(&priv->mutex);
f3ccc08c 2139 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
2140 mutex_unlock(&priv->mutex);
2141}
2142
4a4a9e81 2143static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 2144{
c79dd5b5
TW
2145 struct iwl_priv *priv =
2146 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
2147
2148 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2149 return;
2150
258c44a0
MA
2151 /* enable dram interrupt */
2152 iwl_reset_ict(priv);
2153
b481de9c 2154 mutex_lock(&priv->mutex);
4a4a9e81 2155 iwl_alive_start(priv);
b481de9c
ZY
2156 mutex_unlock(&priv->mutex);
2157}
2158
16e727e8
EG
2159static void iwl_bg_run_time_calib_work(struct work_struct *work)
2160{
2161 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2162 run_time_calib_work);
2163
2164 mutex_lock(&priv->mutex);
2165
2166 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2167 test_bit(STATUS_SCANNING, &priv->status)) {
2168 mutex_unlock(&priv->mutex);
2169 return;
2170 }
2171
2172 if (priv->start_calib) {
2173 iwl_chain_noise_calibration(priv, &priv->statistics);
2174
2175 iwl_sensitivity_calibration(priv, &priv->statistics);
2176 }
2177
2178 mutex_unlock(&priv->mutex);
2179 return;
2180}
2181
5b9f8cd3 2182static void iwl_bg_up(struct work_struct *data)
b481de9c 2183{
c79dd5b5 2184 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
2185
2186 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2187 return;
2188
2189 mutex_lock(&priv->mutex);
5b9f8cd3 2190 __iwl_up(priv);
b481de9c
ZY
2191 mutex_unlock(&priv->mutex);
2192}
2193
5b9f8cd3 2194static void iwl_bg_restart(struct work_struct *data)
b481de9c 2195{
c79dd5b5 2196 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
2197
2198 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2199 return;
2200
19cc1087
JB
2201 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2202 mutex_lock(&priv->mutex);
2203 priv->vif = NULL;
2204 priv->is_open = 0;
2205 mutex_unlock(&priv->mutex);
2206 iwl_down(priv);
2207 ieee80211_restart_hw(priv->hw);
2208 } else {
2209 iwl_down(priv);
2210 queue_work(priv->workqueue, &priv->up);
2211 }
b481de9c
ZY
2212}
2213
5b9f8cd3 2214static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2215{
c79dd5b5
TW
2216 struct iwl_priv *priv =
2217 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2218
2219 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2220 return;
2221
2222 mutex_lock(&priv->mutex);
a55360e4 2223 iwl_rx_replenish(priv);
b481de9c
ZY
2224 mutex_unlock(&priv->mutex);
2225}
2226
7878a5a4
MA
2227#define IWL_DELAY_NEXT_SCAN (HZ*2)
2228
5bbe233b 2229void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2230{
b481de9c 2231 struct ieee80211_conf *conf = NULL;
857485c0 2232 int ret = 0;
1ff50bda 2233 unsigned long flags;
b481de9c 2234
05c914fe 2235 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2236 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2237 return;
2238 }
2239
e1623446 2240 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2241 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2242
2243
2244 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2245 return;
2246
b481de9c 2247
508e32e1 2248 if (!priv->vif || !priv->is_open)
948c171c 2249 return;
508e32e1 2250
2a421b91 2251 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2252
b481de9c
ZY
2253 conf = ieee80211_get_hw_conf(priv->hw);
2254
2255 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2256 iwlcore_commit_rxon(priv);
b481de9c 2257
3195c1f3 2258 iwl_setup_rxon_timing(priv);
857485c0 2259 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2260 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2261 if (ret)
39aadf8c 2262 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2263 "Attempting to continue.\n");
2264
2265 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2266
42eb7c64 2267 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2268
45823531
AK
2269 if (priv->cfg->ops->hcmd->set_rxon_chain)
2270 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2271
b481de9c
ZY
2272 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2273
e1623446 2274 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2275 priv->assoc_id, priv->beacon_int);
2276
2277 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2278 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2279 else
2280 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2281
2282 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2283 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2284 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2285 else
2286 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2287
05c914fe 2288 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2289 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2290
2291 }
2292
e0158e61 2293 iwlcore_commit_rxon(priv);
b481de9c
ZY
2294
2295 switch (priv->iw_mode) {
05c914fe 2296 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2297 break;
2298
05c914fe 2299 case NL80211_IFTYPE_ADHOC:
b481de9c 2300
c46fbefa
AK
2301 /* assume default assoc id */
2302 priv->assoc_id = 1;
b481de9c 2303
4f40e4d9 2304 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2305 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2306
2307 break;
2308
2309 default:
15b1687c 2310 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2311 __func__, priv->iw_mode);
b481de9c
ZY
2312 break;
2313 }
2314
05c914fe 2315 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2316 priv->assoc_station_added = 1;
2317
1ff50bda
EG
2318 spin_lock_irqsave(&priv->lock, flags);
2319 iwl_activate_qos(priv, 0);
2320 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2321
04816448
GE
2322 /* the chain noise calibration will enabled PM upon completion
2323 * If chain noise has already been run, then we need to enable
2324 * power management here */
2325 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
e312c24c 2326 iwl_power_update_mode(priv, false);
c90a74ba
EG
2327
2328 /* Enable Rx differential gain and sensitivity calibrations */
2329 iwl_chain_noise_reset(priv);
2330 priv->start_calib = 1;
2331
508e32e1
RC
2332}
2333
b481de9c
ZY
2334/*****************************************************************************
2335 *
2336 * mac80211 entry point functions
2337 *
2338 *****************************************************************************/
2339
154b25ce 2340#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2341
f0b6e2e8
RC
2342/*
2343 * Not a mac80211 entry point function, but it fits in with all the
2344 * other mac80211 functions grouped here.
2345 */
2346static int iwl_setup_mac(struct iwl_priv *priv)
2347{
2348 int ret;
2349 struct ieee80211_hw *hw = priv->hw;
2350 hw->rate_control_algorithm = "iwl-agn-rs";
2351
2352 /* Tell mac80211 our characteristics */
2353 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2354 IEEE80211_HW_NOISE_DBM |
2355 IEEE80211_HW_AMPDU_AGGREGATION |
2356 IEEE80211_HW_SPECTRUM_MGMT;
2357
2358 if (!priv->cfg->broken_powersave)
2359 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2360 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2361
8d9698b3 2362 hw->sta_data_size = sizeof(struct iwl_station_priv);
f0b6e2e8
RC
2363 hw->wiphy->interface_modes =
2364 BIT(NL80211_IFTYPE_STATION) |
2365 BIT(NL80211_IFTYPE_ADHOC);
2366
2367 hw->wiphy->custom_regulatory = true;
2368
2369 /* Firmware does not support this */
2370 hw->wiphy->disable_beacon_hints = true;
2371
2372 /*
2373 * For now, disable PS by default because it affects
2374 * RX performance significantly.
2375 */
2376 hw->wiphy->ps_default = false;
2377
2378 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2379 /* we create the 802.11 header and a zero-length SSID element */
2380 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2381
2382 /* Default value; 4 EDCA QOS priorities */
2383 hw->queues = 4;
2384
2385 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2386
2387 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2388 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2389 &priv->bands[IEEE80211_BAND_2GHZ];
2390 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2391 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2392 &priv->bands[IEEE80211_BAND_5GHZ];
2393
2394 ret = ieee80211_register_hw(priv->hw);
2395 if (ret) {
2396 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2397 return ret;
2398 }
2399 priv->mac80211_registered = 1;
2400
2401 return 0;
2402}
2403
2404
5b9f8cd3 2405static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2406{
c79dd5b5 2407 struct iwl_priv *priv = hw->priv;
5a66926a 2408 int ret;
b481de9c 2409
e1623446 2410 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2411
2412 /* we should be verifying the device is ready to be opened */
2413 mutex_lock(&priv->mutex);
2414
5a66926a
ZY
2415 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2416 * ucode filename and max sizes are card-specific. */
b481de9c 2417
5a66926a 2418 if (!priv->ucode_code.len) {
5b9f8cd3 2419 ret = iwl_read_ucode(priv);
5a66926a 2420 if (ret) {
15b1687c 2421 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2422 mutex_unlock(&priv->mutex);
6cd0b1cb 2423 return ret;
5a66926a
ZY
2424 }
2425 }
b481de9c 2426
5b9f8cd3 2427 ret = __iwl_up(priv);
5a66926a 2428
b481de9c 2429 mutex_unlock(&priv->mutex);
5a66926a 2430
e655b9f0 2431 if (ret)
6cd0b1cb 2432 return ret;
e655b9f0 2433
c1842d61
TW
2434 if (iwl_is_rfkill(priv))
2435 goto out;
2436
e1623446 2437 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2438
fe9b6b72 2439 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2440 * mac80211 will not be run successfully. */
154b25ce
EG
2441 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2442 test_bit(STATUS_READY, &priv->status),
2443 UCODE_READY_TIMEOUT);
2444 if (!ret) {
2445 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2446 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2447 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2448 return -ETIMEDOUT;
5a66926a 2449 }
fe9b6b72 2450 }
0a078ffa 2451
e932a609
JB
2452 iwl_led_start(priv);
2453
c1842d61 2454out:
0a078ffa 2455 priv->is_open = 1;
e1623446 2456 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2457 return 0;
2458}
2459
5b9f8cd3 2460static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2461{
c79dd5b5 2462 struct iwl_priv *priv = hw->priv;
b481de9c 2463
e1623446 2464 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2465
19cc1087 2466 if (!priv->is_open)
e655b9f0 2467 return;
e655b9f0 2468
b481de9c 2469 priv->is_open = 0;
5a66926a 2470
5bddf549 2471 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
e655b9f0
ZY
2472 /* stop mac, cancel any scan request and clear
2473 * RXON_FILTER_ASSOC_MSK BIT
2474 */
5a66926a 2475 mutex_lock(&priv->mutex);
2a421b91 2476 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2477 mutex_unlock(&priv->mutex);
fde3571f
MA
2478 }
2479
5b9f8cd3 2480 iwl_down(priv);
5a66926a
ZY
2481
2482 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2483
2484 /* enable interrupts again in order to receive rfkill changes */
2485 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2486 iwl_enable_interrupts(priv);
948c171c 2487
e1623446 2488 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2489}
2490
5b9f8cd3 2491static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2492{
c79dd5b5 2493 struct iwl_priv *priv = hw->priv;
b481de9c 2494
e1623446 2495 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2496
e1623446 2497 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2498 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2499
e039fa4a 2500 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2501 dev_kfree_skb_any(skb);
2502
e1623446 2503 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2504 return NETDEV_TX_OK;
b481de9c
ZY
2505}
2506
60690a6a 2507void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2508{
857485c0 2509 int ret = 0;
1ff50bda 2510 unsigned long flags;
b481de9c 2511
d986bcd1 2512 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2513 return;
2514
2515 /* The following should be done only at AP bring up */
3195c1f3 2516 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2517
2518 /* RXON - unassoc (to set timing command) */
2519 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2520 iwlcore_commit_rxon(priv);
b481de9c
ZY
2521
2522 /* RXON Timing */
3195c1f3 2523 iwl_setup_rxon_timing(priv);
857485c0 2524 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2525 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2526 if (ret)
39aadf8c 2527 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2528 "Attempting to continue.\n");
2529
45823531
AK
2530 if (priv->cfg->ops->hcmd->set_rxon_chain)
2531 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2532
2533 /* FIXME: what should be the assoc_id for AP? */
2534 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2535 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2536 priv->staging_rxon.flags |=
2537 RXON_FLG_SHORT_PREAMBLE_MSK;
2538 else
2539 priv->staging_rxon.flags &=
2540 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2541
2542 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2543 if (priv->assoc_capability &
2544 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2545 priv->staging_rxon.flags |=
2546 RXON_FLG_SHORT_SLOT_MSK;
2547 else
2548 priv->staging_rxon.flags &=
2549 ~RXON_FLG_SHORT_SLOT_MSK;
2550
05c914fe 2551 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2552 priv->staging_rxon.flags &=
2553 ~RXON_FLG_SHORT_SLOT_MSK;
2554 }
2555 /* restore RXON assoc */
2556 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2557 iwlcore_commit_rxon(priv);
1ff50bda
EG
2558 spin_lock_irqsave(&priv->lock, flags);
2559 iwl_activate_qos(priv, 1);
2560 spin_unlock_irqrestore(&priv->lock, flags);
9a9ca65f 2561 iwl_add_bcast_station(priv);
e1493deb 2562 }
5b9f8cd3 2563 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2564
2565 /* FIXME - we need to add code here to detect a totally new
2566 * configuration, reset the AP, unassoc, rxon timing, assoc,
2567 * clear sta table, add BCAST sta... */
2568}
2569
5b9f8cd3 2570static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2571 struct ieee80211_key_conf *keyconf, const u8 *addr,
2572 u32 iv32, u16 *phase1key)
2573{
ab885f8c 2574
9f58671e 2575 struct iwl_priv *priv = hw->priv;
e1623446 2576 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2577
9f58671e 2578 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2579
e1623446 2580 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2581}
2582
5b9f8cd3 2583static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2584 struct ieee80211_vif *vif,
2585 struct ieee80211_sta *sta,
b481de9c
ZY
2586 struct ieee80211_key_conf *key)
2587{
c79dd5b5 2588 struct iwl_priv *priv = hw->priv;
42986796
WT
2589 const u8 *addr;
2590 int ret;
2591 u8 sta_id;
2592 bool is_default_wep_key = false;
b481de9c 2593
e1623446 2594 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2595
90e8e424 2596 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2597 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2598 return -EOPNOTSUPP;
2599 }
42986796 2600 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2601 sta_id = iwl_find_station(priv, addr);
6974e363 2602 if (sta_id == IWL_INVALID_STATION) {
e1623446 2603 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2604 addr);
6974e363 2605 return -EINVAL;
b481de9c 2606
deb09c43 2607 }
b481de9c 2608
6974e363 2609 mutex_lock(&priv->mutex);
2a421b91 2610 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2611 mutex_unlock(&priv->mutex);
2612
2613 /* If we are getting WEP group key and we didn't receive any key mapping
2614 * so far, we are in legacy wep mode (group key only), otherwise we are
2615 * in 1X mode.
2616 * In legacy wep mode, we use another host command to the uCode */
5425e490 2617 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2618 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2619 if (cmd == SET_KEY)
2620 is_default_wep_key = !priv->key_mapping_key;
2621 else
ccc038ab
EG
2622 is_default_wep_key =
2623 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2624 }
052c4b9f 2625
b481de9c 2626 switch (cmd) {
deb09c43 2627 case SET_KEY:
6974e363
EG
2628 if (is_default_wep_key)
2629 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2630 else
7480513f 2631 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2632
e1623446 2633 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2634 break;
2635 case DISABLE_KEY:
6974e363
EG
2636 if (is_default_wep_key)
2637 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2638 else
3ec47732 2639 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2640
e1623446 2641 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2642 break;
2643 default:
deb09c43 2644 ret = -EINVAL;
b481de9c
ZY
2645 }
2646
e1623446 2647 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2648
deb09c43 2649 return ret;
b481de9c
ZY
2650}
2651
5b9f8cd3 2652static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2653 enum ieee80211_ampdu_mlme_action action,
17741cdc 2654 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2655{
2656 struct iwl_priv *priv = hw->priv;
5c2207c6 2657 int ret;
d783b061 2658
e1623446 2659 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2660 sta->addr, tid);
d783b061
TW
2661
2662 if (!(priv->cfg->sku & IWL_SKU_N))
2663 return -EACCES;
2664
2665 switch (action) {
2666 case IEEE80211_AMPDU_RX_START:
e1623446 2667 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2668 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2669 case IEEE80211_AMPDU_RX_STOP:
e1623446 2670 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2671 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2672 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2673 return 0;
2674 else
2675 return ret;
d783b061 2676 case IEEE80211_AMPDU_TX_START:
e1623446 2677 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2678 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2679 case IEEE80211_AMPDU_TX_STOP:
e1623446 2680 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2681 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2682 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2683 return 0;
2684 else
2685 return ret;
d783b061 2686 default:
e1623446 2687 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2688 return -EINVAL;
2689 break;
2690 }
2691 return 0;
2692}
9f58671e 2693
5b9f8cd3 2694static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2695 struct ieee80211_low_level_stats *stats)
2696{
bf403db8
EK
2697 struct iwl_priv *priv = hw->priv;
2698
2699 priv = hw->priv;
e1623446
TW
2700 IWL_DEBUG_MAC80211(priv, "enter\n");
2701 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2702
2703 return 0;
2704}
2705
b481de9c
ZY
2706/*****************************************************************************
2707 *
2708 * sysfs attributes
2709 *
2710 *****************************************************************************/
2711
0a6857e7 2712#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2713
2714/*
2715 * The following adds a new attribute to the sysfs representation
c3a739fa 2716 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2717 * used for controlling the debug level.
2718 *
2719 * See the level definitions in iwl for details.
a562a9dd 2720 *
3d816c77
RC
2721 * The debug_level being managed using sysfs below is a per device debug
2722 * level that is used instead of the global debug level if it (the per
2723 * device debug level) is set.
b481de9c 2724 */
8cf769c6
EK
2725static ssize_t show_debug_level(struct device *d,
2726 struct device_attribute *attr, char *buf)
b481de9c 2727{
3d816c77
RC
2728 struct iwl_priv *priv = dev_get_drvdata(d);
2729 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
b481de9c 2730}
8cf769c6
EK
2731static ssize_t store_debug_level(struct device *d,
2732 struct device_attribute *attr,
b481de9c
ZY
2733 const char *buf, size_t count)
2734{
928841b1 2735 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2736 unsigned long val;
2737 int ret;
b481de9c 2738
9257746f
TW
2739 ret = strict_strtoul(buf, 0, &val);
2740 if (ret)
978785a3 2741 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
20594eb0 2742 else {
3d816c77 2743 priv->debug_level = val;
20594eb0
WYG
2744 if (iwl_alloc_traffic_mem(priv))
2745 IWL_ERR(priv,
2746 "Not enough memory to generate traffic log\n");
2747 }
b481de9c
ZY
2748 return strnlen(buf, count);
2749}
2750
8cf769c6
EK
2751static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2752 show_debug_level, store_debug_level);
2753
b481de9c 2754
0a6857e7 2755#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2756
b481de9c
ZY
2757
2758static ssize_t show_temperature(struct device *d,
2759 struct device_attribute *attr, char *buf)
2760{
928841b1 2761 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2762
fee1247a 2763 if (!iwl_is_alive(priv))
b481de9c
ZY
2764 return -EAGAIN;
2765
91dbc5bd 2766 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2767}
2768
2769static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2770
b481de9c
ZY
2771static ssize_t show_tx_power(struct device *d,
2772 struct device_attribute *attr, char *buf)
2773{
928841b1 2774 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2775
2776 if (!iwl_is_ready_rf(priv))
2777 return sprintf(buf, "off\n");
2778 else
2779 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2780}
2781
2782static ssize_t store_tx_power(struct device *d,
2783 struct device_attribute *attr,
2784 const char *buf, size_t count)
2785{
928841b1 2786 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2787 unsigned long val;
2788 int ret;
b481de9c 2789
9257746f
TW
2790 ret = strict_strtoul(buf, 10, &val);
2791 if (ret)
978785a3 2792 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
5eadd94b
WYG
2793 else {
2794 ret = iwl_set_tx_power(priv, val, false);
2795 if (ret)
2796 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2797 ret);
2798 else
2799 ret = count;
2800 }
2801 return ret;
b481de9c
ZY
2802}
2803
2804static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2805
2806static ssize_t show_flags(struct device *d,
2807 struct device_attribute *attr, char *buf)
2808{
928841b1 2809 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2810
2811 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2812}
2813
2814static ssize_t store_flags(struct device *d,
2815 struct device_attribute *attr,
2816 const char *buf, size_t count)
2817{
928841b1 2818 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2819 unsigned long val;
2820 u32 flags;
2821 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2822 if (ret)
9257746f
TW
2823 return ret;
2824 flags = (u32)val;
b481de9c
ZY
2825
2826 mutex_lock(&priv->mutex);
2827 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2828 /* Cancel any currently running scans... */
2a421b91 2829 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2830 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2831 else {
e1623446 2832 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2833 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2834 iwlcore_commit_rxon(priv);
b481de9c
ZY
2835 }
2836 }
2837 mutex_unlock(&priv->mutex);
2838
2839 return count;
2840}
2841
2842static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2843
2844static ssize_t show_filter_flags(struct device *d,
2845 struct device_attribute *attr, char *buf)
2846{
928841b1 2847 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2848
2849 return sprintf(buf, "0x%04X\n",
2850 le32_to_cpu(priv->active_rxon.filter_flags));
2851}
2852
2853static ssize_t store_filter_flags(struct device *d,
2854 struct device_attribute *attr,
2855 const char *buf, size_t count)
2856{
928841b1 2857 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2858 unsigned long val;
2859 u32 filter_flags;
2860 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2861 if (ret)
9257746f
TW
2862 return ret;
2863 filter_flags = (u32)val;
b481de9c
ZY
2864
2865 mutex_lock(&priv->mutex);
2866 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2867 /* Cancel any currently running scans... */
2a421b91 2868 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2869 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2870 else {
e1623446 2871 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2872 "0x%04X\n", filter_flags);
2873 priv->staging_rxon.filter_flags =
2874 cpu_to_le32(filter_flags);
e0158e61 2875 iwlcore_commit_rxon(priv);
b481de9c
ZY
2876 }
2877 }
2878 mutex_unlock(&priv->mutex);
2879
2880 return count;
2881}
2882
2883static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2884 store_filter_flags);
2885
b481de9c
ZY
2886
2887static ssize_t show_statistics(struct device *d,
2888 struct device_attribute *attr, char *buf)
2889{
c79dd5b5 2890 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2891 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2892 u32 len = 0, ofs = 0;
3ac7f146 2893 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2894 int rc = 0;
2895
fee1247a 2896 if (!iwl_is_alive(priv))
b481de9c
ZY
2897 return -EAGAIN;
2898
2899 mutex_lock(&priv->mutex);
49ea8596 2900 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
2901 mutex_unlock(&priv->mutex);
2902
2903 if (rc) {
2904 len = sprintf(buf,
2905 "Error sending statistics request: 0x%08X\n", rc);
2906 return len;
2907 }
2908
2909 while (size && (PAGE_SIZE - len)) {
2910 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2911 PAGE_SIZE - len, 1);
2912 len = strlen(buf);
2913 if (PAGE_SIZE - len)
2914 buf[len++] = '\n';
2915
2916 ofs += 16;
2917 size -= min(size, 16U);
2918 }
2919
2920 return len;
2921}
2922
2923static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2924
01abfbb2
WYG
2925static ssize_t show_rts_ht_protection(struct device *d,
2926 struct device_attribute *attr, char *buf)
2927{
2928 struct iwl_priv *priv = dev_get_drvdata(d);
2929
2930 return sprintf(buf, "%s\n",
2931 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
2932}
2933
2934static ssize_t store_rts_ht_protection(struct device *d,
2935 struct device_attribute *attr,
2936 const char *buf, size_t count)
2937{
2938 struct iwl_priv *priv = dev_get_drvdata(d);
2939 unsigned long val;
2940 int ret;
2941
2942 ret = strict_strtoul(buf, 10, &val);
2943 if (ret)
2944 IWL_INFO(priv, "Input is not in decimal form.\n");
2945 else {
2946 if (!iwl_is_associated(priv))
2947 priv->cfg->use_rts_for_ht = val ? true : false;
2948 else
2949 IWL_ERR(priv, "Sta associated with AP - "
2950 "Change protection mechanism is not allowed\n");
2951 ret = count;
2952 }
2953 return ret;
2954}
2955
2956static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
2957 show_rts_ht_protection, store_rts_ht_protection);
2958
b481de9c 2959
b481de9c
ZY
2960/*****************************************************************************
2961 *
2962 * driver setup and teardown
2963 *
2964 *****************************************************************************/
2965
4e39317d 2966static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2967{
d21050c7 2968 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
2969
2970 init_waitqueue_head(&priv->wait_command_queue);
2971
5b9f8cd3
EG
2972 INIT_WORK(&priv->up, iwl_bg_up);
2973 INIT_WORK(&priv->restart, iwl_bg_restart);
2974 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 2975 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 2976 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
2977 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2978 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 2979
2a421b91 2980 iwl_setup_scan_deferred_work(priv);
bb8c093b 2981
4e39317d
EG
2982 if (priv->cfg->ops->lib->setup_deferred_work)
2983 priv->cfg->ops->lib->setup_deferred_work(priv);
2984
2985 init_timer(&priv->statistics_periodic);
2986 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 2987 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 2988
ef850d7c
MA
2989 if (!priv->cfg->use_isr_legacy)
2990 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2991 iwl_irq_tasklet, (unsigned long)priv);
2992 else
2993 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2994 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
2995}
2996
4e39317d 2997static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2998{
4e39317d
EG
2999 if (priv->cfg->ops->lib->cancel_deferred_work)
3000 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 3001
3ae6a054 3002 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
3003 cancel_delayed_work(&priv->scan_check);
3004 cancel_delayed_work(&priv->alive_start);
b481de9c 3005 cancel_work_sync(&priv->beacon_update);
4e39317d 3006 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
3007}
3008
89f186a8
RC
3009static void iwl_init_hw_rates(struct iwl_priv *priv,
3010 struct ieee80211_rate *rates)
3011{
3012 int i;
3013
3014 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3015 rates[i].bitrate = iwl_rates[i].ieee * 5;
3016 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3017 rates[i].hw_value_short = i;
3018 rates[i].flags = 0;
3019 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3020 /*
3021 * If CCK != 1M then set short preamble rate flag.
3022 */
3023 rates[i].flags |=
3024 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3025 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3026 }
3027 }
3028}
3029
3030static int iwl_init_drv(struct iwl_priv *priv)
3031{
3032 int ret;
3033
3034 priv->ibss_beacon = NULL;
3035
3036 spin_lock_init(&priv->lock);
3037 spin_lock_init(&priv->sta_lock);
3038 spin_lock_init(&priv->hcmd_lock);
3039
3040 INIT_LIST_HEAD(&priv->free_frames);
3041
3042 mutex_init(&priv->mutex);
3043
3044 /* Clear the driver's (not device's) station table */
3045 iwl_clear_stations_table(priv);
3046
3047 priv->ieee_channels = NULL;
3048 priv->ieee_rates = NULL;
3049 priv->band = IEEE80211_BAND_2GHZ;
3050
3051 priv->iw_mode = NL80211_IFTYPE_STATION;
3f3e0376
WYG
3052 if (priv->cfg->support_sm_ps)
3053 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DYNAMIC;
3054 else
3055 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
89f186a8
RC
3056
3057 /* Choose which receivers/antennas to use */
3058 if (priv->cfg->ops->hcmd->set_rxon_chain)
3059 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3060
3061 iwl_init_scan_params(priv);
3062
3063 iwl_reset_qos(priv);
3064
3065 priv->qos_data.qos_active = 0;
3066 priv->qos_data.qos_cap.val = 0;
3067
3068 priv->rates_mask = IWL_RATES_MASK;
3069 /* Set the tx_power_user_lmt to the lowest power level
3070 * this value will get overwritten by channel max power avg
3071 * from eeprom */
3072 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3073
3074 ret = iwl_init_channel_map(priv);
3075 if (ret) {
3076 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3077 goto err;
3078 }
3079
3080 ret = iwlcore_init_geos(priv);
3081 if (ret) {
3082 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3083 goto err_free_channel_map;
3084 }
3085 iwl_init_hw_rates(priv, priv->ieee_rates);
3086
3087 return 0;
3088
3089err_free_channel_map:
3090 iwl_free_channel_map(priv);
3091err:
3092 return ret;
3093}
3094
3095static void iwl_uninit_drv(struct iwl_priv *priv)
3096{
3097 iwl_calib_free_results(priv);
3098 iwlcore_free_geos(priv);
3099 iwl_free_channel_map(priv);
3100 kfree(priv->scan);
3101}
3102
5b9f8cd3 3103static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
3104 &dev_attr_flags.attr,
3105 &dev_attr_filter_flags.attr,
b481de9c 3106 &dev_attr_statistics.attr,
b481de9c 3107 &dev_attr_temperature.attr,
b481de9c 3108 &dev_attr_tx_power.attr,
01abfbb2 3109 &dev_attr_rts_ht_protection.attr,
8cf769c6
EK
3110#ifdef CONFIG_IWLWIFI_DEBUG
3111 &dev_attr_debug_level.attr,
3112#endif
b481de9c
ZY
3113 NULL
3114};
3115
5b9f8cd3 3116static struct attribute_group iwl_attribute_group = {
b481de9c 3117 .name = NULL, /* put in device directory */
5b9f8cd3 3118 .attrs = iwl_sysfs_entries,
b481de9c
ZY
3119};
3120
5b9f8cd3
EG
3121static struct ieee80211_ops iwl_hw_ops = {
3122 .tx = iwl_mac_tx,
3123 .start = iwl_mac_start,
3124 .stop = iwl_mac_stop,
3125 .add_interface = iwl_mac_add_interface,
3126 .remove_interface = iwl_mac_remove_interface,
3127 .config = iwl_mac_config,
5b9f8cd3
EG
3128 .configure_filter = iwl_configure_filter,
3129 .set_key = iwl_mac_set_key,
3130 .update_tkip_key = iwl_mac_update_tkip_key,
3131 .get_stats = iwl_mac_get_stats,
3132 .get_tx_stats = iwl_mac_get_tx_stats,
3133 .conf_tx = iwl_mac_conf_tx,
3134 .reset_tsf = iwl_mac_reset_tsf,
3135 .bss_info_changed = iwl_bss_info_changed,
3136 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 3137 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
3138};
3139
5b9f8cd3 3140static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
3141{
3142 int err = 0;
c79dd5b5 3143 struct iwl_priv *priv;
b481de9c 3144 struct ieee80211_hw *hw;
82b9a121 3145 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 3146 unsigned long flags;
6cd0b1cb 3147 u16 pci_cmd;
b481de9c 3148
316c30d9
AK
3149 /************************
3150 * 1. Allocating HW data
3151 ************************/
3152
6440adb5
CB
3153 /* Disabling hardware scan means that mac80211 will perform scans
3154 * "the hard way", rather than using device's scan. */
1ea87396 3155 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 3156 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
3157 dev_printk(KERN_DEBUG, &(pdev->dev),
3158 "Disabling hw_scan\n");
5b9f8cd3 3159 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
3160 }
3161
5b9f8cd3 3162 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 3163 if (!hw) {
b481de9c
ZY
3164 err = -ENOMEM;
3165 goto out;
3166 }
1d0a082d
AK
3167 priv = hw->priv;
3168 /* At this point both hw and priv are allocated. */
3169
b481de9c
ZY
3170 SET_IEEE80211_DEV(hw, &pdev->dev);
3171
e1623446 3172 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 3173 priv->cfg = cfg;
b481de9c 3174 priv->pci_dev = pdev;
40cefda9 3175 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 3176
0a6857e7 3177#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
3178 atomic_set(&priv->restrict_refcnt, 0);
3179#endif
20594eb0
WYG
3180 if (iwl_alloc_traffic_mem(priv))
3181 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
b481de9c 3182
316c30d9
AK
3183 /**************************
3184 * 2. Initializing PCI bus
3185 **************************/
3186 if (pci_enable_device(pdev)) {
3187 err = -ENODEV;
3188 goto out_ieee80211_free_hw;
3189 }
3190
3191 pci_set_master(pdev);
3192
093d874c 3193 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 3194 if (!err)
093d874c 3195 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 3196 if (err) {
093d874c 3197 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3198 if (!err)
093d874c 3199 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 3200 /* both attempts failed: */
316c30d9 3201 if (err) {
978785a3 3202 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 3203 goto out_pci_disable_device;
cc2a8ea8 3204 }
316c30d9
AK
3205 }
3206
3207 err = pci_request_regions(pdev, DRV_NAME);
3208 if (err)
3209 goto out_pci_disable_device;
3210
3211 pci_set_drvdata(pdev, priv);
3212
316c30d9
AK
3213
3214 /***********************
3215 * 3. Read REV register
3216 ***********************/
3217 priv->hw_base = pci_iomap(pdev, 0, 0);
3218 if (!priv->hw_base) {
3219 err = -ENODEV;
3220 goto out_pci_release_regions;
3221 }
3222
e1623446 3223 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 3224 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 3225 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 3226
a8b50a0a
MA
3227 /* this spin lock will be used in apm_ops.init and EEPROM access
3228 * we should init now
3229 */
3230 spin_lock_init(&priv->reg_lock);
b661c819 3231 iwl_hw_detect(priv);
978785a3 3232 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 3233 priv->cfg->name, priv->hw_rev);
316c30d9 3234
e7b63581
TW
3235 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3236 * PCI Tx retries from interfering with C3 CPU state */
3237 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3238
086ed117
MA
3239 iwl_prepare_card_hw(priv);
3240 if (!priv->hw_ready) {
3241 IWL_WARN(priv, "Failed, HW not ready\n");
3242 goto out_iounmap;
3243 }
3244
91238714
TW
3245 /*****************
3246 * 4. Read EEPROM
3247 *****************/
316c30d9
AK
3248 /* Read the EEPROM */
3249 err = iwl_eeprom_init(priv);
3250 if (err) {
15b1687c 3251 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
3252 goto out_iounmap;
3253 }
8614f360
TW
3254 err = iwl_eeprom_check_version(priv);
3255 if (err)
c8f16138 3256 goto out_free_eeprom;
8614f360 3257
02883017 3258 /* extract MAC Address */
316c30d9 3259 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 3260 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
3261 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3262
3263 /************************
3264 * 5. Setup HW constants
3265 ************************/
da154e30 3266 if (iwl_set_hw_params(priv)) {
15b1687c 3267 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 3268 goto out_free_eeprom;
316c30d9
AK
3269 }
3270
3271 /*******************
6ba87956 3272 * 6. Setup priv
316c30d9 3273 *******************/
b481de9c 3274
6ba87956 3275 err = iwl_init_drv(priv);
bf85ea4f 3276 if (err)
399f4900 3277 goto out_free_eeprom;
bf85ea4f 3278 /* At this point both hw and priv are initialized. */
316c30d9 3279
316c30d9 3280 /********************
09f9bf79 3281 * 7. Setup services
316c30d9 3282 ********************/
0359facc 3283 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3284 iwl_disable_interrupts(priv);
0359facc 3285 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 3286
6cd0b1cb
HS
3287 pci_enable_msi(priv->pci_dev);
3288
ef850d7c
MA
3289 iwl_alloc_isr_ict(priv);
3290 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3291 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
3292 if (err) {
3293 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3294 goto out_disable_msi;
3295 }
5b9f8cd3 3296 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 3297 if (err) {
15b1687c 3298 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 3299 goto out_free_irq;
316c30d9
AK
3300 }
3301
4e39317d 3302 iwl_setup_deferred_work(priv);
653fa4a0 3303 iwl_setup_rx_handlers(priv);
316c30d9 3304
6ba87956 3305 /**********************************
09f9bf79 3306 * 8. Setup and register mac80211
6ba87956
TW
3307 **********************************/
3308
6cd0b1cb
HS
3309 /* enable interrupts if needed: hw bug w/a */
3310 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3311 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3312 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3313 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3314 }
3315
3316 iwl_enable_interrupts(priv);
3317
6ba87956
TW
3318 err = iwl_setup_mac(priv);
3319 if (err)
3320 goto out_remove_sysfs;
3321
3322 err = iwl_dbgfs_register(priv, DRV_NAME);
3323 if (err)
a75fbe8d 3324 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 3325
6cd0b1cb
HS
3326 /* If platform's RF_KILL switch is NOT set to KILL */
3327 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3328 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3329 else
3330 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3331
a60e77e5
JB
3332 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3333 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3334
58d0f361 3335 iwl_power_initialize(priv);
39b73fb1 3336 iwl_tt_initialize(priv);
b481de9c
ZY
3337 return 0;
3338
316c30d9 3339 out_remove_sysfs:
c8f16138
RC
3340 destroy_workqueue(priv->workqueue);
3341 priv->workqueue = NULL;
5b9f8cd3 3342 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3343 out_free_irq:
3344 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3345 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3346 out_disable_msi:
3347 pci_disable_msi(priv->pci_dev);
6ba87956 3348 iwl_uninit_drv(priv);
073d3f5f
TW
3349 out_free_eeprom:
3350 iwl_eeprom_free(priv);
b481de9c
ZY
3351 out_iounmap:
3352 pci_iounmap(pdev, priv->hw_base);
3353 out_pci_release_regions:
316c30d9 3354 pci_set_drvdata(pdev, NULL);
623d563e 3355 pci_release_regions(pdev);
b481de9c
ZY
3356 out_pci_disable_device:
3357 pci_disable_device(pdev);
b481de9c 3358 out_ieee80211_free_hw:
20594eb0 3359 iwl_free_traffic_mem(priv);
d7c76f4c 3360 ieee80211_free_hw(priv->hw);
b481de9c
ZY
3361 out:
3362 return err;
3363}
3364
5b9f8cd3 3365static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3366{
c79dd5b5 3367 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3368 unsigned long flags;
b481de9c
ZY
3369
3370 if (!priv)
3371 return;
3372
e1623446 3373 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3374
67249625 3375 iwl_dbgfs_unregister(priv);
5b9f8cd3 3376 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3377
5b9f8cd3
EG
3378 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3379 * to be called and iwl_down since we are removing the device
0b124c31
GG
3380 * we need to set STATUS_EXIT_PENDING bit.
3381 */
3382 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3383 if (priv->mac80211_registered) {
3384 ieee80211_unregister_hw(priv->hw);
3385 priv->mac80211_registered = 0;
0b124c31 3386 } else {
5b9f8cd3 3387 iwl_down(priv);
c4f55232
RR
3388 }
3389
c166b25a
BC
3390 /*
3391 * Make sure device is reset to low power before unloading driver.
3392 * This may be redundant with iwl_down(), but there are paths to
3393 * run iwl_down() without calling apm_ops.stop(), and there are
3394 * paths to avoid running iwl_down() at all before leaving driver.
3395 * This (inexpensive) call *makes sure* device is reset.
3396 */
3397 priv->cfg->ops->lib->apm_ops.stop(priv);
3398
39b73fb1
WYG
3399 iwl_tt_exit(priv);
3400
0359facc
MA
3401 /* make sure we flush any pending irq or
3402 * tasklet for the driver
3403 */
3404 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3405 iwl_disable_interrupts(priv);
0359facc
MA
3406 spin_unlock_irqrestore(&priv->lock, flags);
3407
3408 iwl_synchronize_irq(priv);
3409
5b9f8cd3 3410 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3411
3412 if (priv->rxq.bd)
a55360e4 3413 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3414 iwl_hw_txq_ctx_free(priv);
b481de9c 3415
c587de0b 3416 iwl_clear_stations_table(priv);
073d3f5f 3417 iwl_eeprom_free(priv);
b481de9c 3418
b481de9c 3419
948c171c
MA
3420 /*netif_stop_queue(dev); */
3421 flush_workqueue(priv->workqueue);
3422
5b9f8cd3 3423 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3424 * priv->workqueue... so we can't take down the workqueue
3425 * until now... */
3426 destroy_workqueue(priv->workqueue);
3427 priv->workqueue = NULL;
20594eb0 3428 iwl_free_traffic_mem(priv);
b481de9c 3429
6cd0b1cb
HS
3430 free_irq(priv->pci_dev->irq, priv);
3431 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3432 pci_iounmap(pdev, priv->hw_base);
3433 pci_release_regions(pdev);
3434 pci_disable_device(pdev);
3435 pci_set_drvdata(pdev, NULL);
3436
6ba87956 3437 iwl_uninit_drv(priv);
b481de9c 3438
ef850d7c
MA
3439 iwl_free_isr_ict(priv);
3440
b481de9c
ZY
3441 if (priv->ibss_beacon)
3442 dev_kfree_skb(priv->ibss_beacon);
3443
3444 ieee80211_free_hw(priv->hw);
3445}
3446
b481de9c
ZY
3447
3448/*****************************************************************************
3449 *
3450 * driver and module entry point
3451 *
3452 *****************************************************************************/
3453
fed9017e
RR
3454/* Hardware specific file defines the PCI IDs table for that hardware module */
3455static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3456#ifdef CONFIG_IWL4965
fed9017e
RR
3457 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3458 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3459#endif /* CONFIG_IWL4965 */
5a6a256e 3460#ifdef CONFIG_IWL5000
47408639
EK
3461 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3462 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3463 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3464 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3465 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3466 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3467 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3468 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3469 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3470 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3471/* 5350 WiFi/WiMax */
3472 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3473 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3474 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3475/* 5150 Wifi/WiMax */
3476 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3477 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
5953a62e
WYG
3478
3479/* 6x00 Series */
5953a62e
WYG
3480 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3481 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3482 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3483 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3484 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3485 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3486 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3487 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3488 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3489 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3490
3491/* 6x50 WiFi/WiMax Series */
3492 {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)},
3493 {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)},
3494 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3495 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3496 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3497 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3498 {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)},
3499 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3500 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3501
77dcb6a9 3502/* 1000 Series WiFi */
4bd0914f
WYG
3503 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3504 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3505 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3506 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3507 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3508 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3509 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3510 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3511 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3512 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3513 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3514 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
5a6a256e 3515#endif /* CONFIG_IWL5000 */
7100e924 3516
fed9017e
RR
3517 {0}
3518};
3519MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3520
3521static struct pci_driver iwl_driver = {
b481de9c 3522 .name = DRV_NAME,
fed9017e 3523 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3524 .probe = iwl_pci_probe,
3525 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3526#ifdef CONFIG_PM
5b9f8cd3
EG
3527 .suspend = iwl_pci_suspend,
3528 .resume = iwl_pci_resume,
b481de9c
ZY
3529#endif
3530};
3531
5b9f8cd3 3532static int __init iwl_init(void)
b481de9c
ZY
3533{
3534
3535 int ret;
3536 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3537 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3538
e227ceac 3539 ret = iwlagn_rate_control_register();
897e1cf2 3540 if (ret) {
a3139c59
SO
3541 printk(KERN_ERR DRV_NAME
3542 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3543 return ret;
3544 }
3545
fed9017e 3546 ret = pci_register_driver(&iwl_driver);
b481de9c 3547 if (ret) {
a3139c59 3548 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3549 goto error_register;
b481de9c 3550 }
b481de9c
ZY
3551
3552 return ret;
897e1cf2 3553
897e1cf2 3554error_register:
e227ceac 3555 iwlagn_rate_control_unregister();
897e1cf2 3556 return ret;
b481de9c
ZY
3557}
3558
5b9f8cd3 3559static void __exit iwl_exit(void)
b481de9c 3560{
fed9017e 3561 pci_unregister_driver(&iwl_driver);
e227ceac 3562 iwlagn_rate_control_unregister();
b481de9c
ZY
3563}
3564
5b9f8cd3
EG
3565module_exit(iwl_exit);
3566module_init(iwl_init);
a562a9dd
RC
3567
3568#ifdef CONFIG_IWLWIFI_DEBUG
4e30cb69 3569module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
a562a9dd 3570MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4e30cb69 3571module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
a562a9dd
RC
3572MODULE_PARM_DESC(debug, "debug output mask");
3573#endif
3574
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