Commit | Line | Data |
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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
1f447808 | 3 | * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
b481de9c ZY |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
b481de9c ZY |
32 | #include <linux/init.h> |
33 | #include <linux/pci.h> | |
34 | #include <linux/dma-mapping.h> | |
35 | #include <linux/delay.h> | |
d43c36dc | 36 | #include <linux/sched.h> |
b481de9c ZY |
37 | #include <linux/skbuff.h> |
38 | #include <linux/netdevice.h> | |
39 | #include <linux/wireless.h> | |
40 | #include <linux/firmware.h> | |
b481de9c ZY |
41 | #include <linux/etherdevice.h> |
42 | #include <linux/if_arp.h> | |
43 | ||
b481de9c ZY |
44 | #include <net/mac80211.h> |
45 | ||
46 | #include <asm/div64.h> | |
47 | ||
a3139c59 SO |
48 | #define DRV_NAME "iwlagn" |
49 | ||
6bc913bd | 50 | #include "iwl-eeprom.h" |
3e0d4cb1 | 51 | #include "iwl-dev.h" |
fee1247a | 52 | #include "iwl-core.h" |
3395f6e9 | 53 | #include "iwl-io.h" |
b481de9c | 54 | #include "iwl-helpers.h" |
6974e363 | 55 | #include "iwl-sta.h" |
f0832f13 | 56 | #include "iwl-calib.h" |
a1175124 | 57 | #include "iwl-agn.h" |
b481de9c | 58 | |
416e1438 | 59 | |
b481de9c ZY |
60 | /****************************************************************************** |
61 | * | |
62 | * module boiler plate | |
63 | * | |
64 | ******************************************************************************/ | |
65 | ||
b481de9c ZY |
66 | /* |
67 | * module name, copyright, version, etc. | |
b481de9c | 68 | */ |
d783b061 | 69 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
b481de9c | 70 | |
0a6857e7 | 71 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
72 | #define VD "d" |
73 | #else | |
74 | #define VD | |
75 | #endif | |
76 | ||
81963d68 | 77 | #define DRV_VERSION IWLWIFI_VERSION VD |
b481de9c | 78 | |
b481de9c ZY |
79 | |
80 | MODULE_DESCRIPTION(DRV_DESCRIPTION); | |
81 | MODULE_VERSION(DRV_VERSION); | |
a7b75207 | 82 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); |
b481de9c | 83 | MODULE_LICENSE("GPL"); |
4fc22b21 | 84 | MODULE_ALIAS("iwl4965"); |
b481de9c | 85 | |
b481de9c | 86 | /** |
5b9f8cd3 | 87 | * iwl_commit_rxon - commit staging_rxon to hardware |
b481de9c | 88 | * |
01ebd063 | 89 | * The RXON command in staging_rxon is committed to the hardware and |
b481de9c ZY |
90 | * the active_rxon structure is updated with the new data. This |
91 | * function correctly transitions out of the RXON_ASSOC_MSK state if | |
92 | * a HW tune is required based on the RXON structure changes. | |
93 | */ | |
e0158e61 | 94 | int iwl_commit_rxon(struct iwl_priv *priv) |
b481de9c ZY |
95 | { |
96 | /* cast away the const for active_rxon in this function */ | |
c1adf9fb | 97 | struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon; |
43d59b32 EG |
98 | int ret; |
99 | bool new_assoc = | |
100 | !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); | |
b481de9c | 101 | |
fee1247a | 102 | if (!iwl_is_alive(priv)) |
43d59b32 | 103 | return -EBUSY; |
b481de9c ZY |
104 | |
105 | /* always get timestamp with Rx frame */ | |
106 | priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK; | |
107 | ||
8ccde88a | 108 | ret = iwl_check_rxon_cmd(priv); |
43d59b32 | 109 | if (ret) { |
15b1687c | 110 | IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); |
b481de9c ZY |
111 | return -EINVAL; |
112 | } | |
113 | ||
0924e519 WYG |
114 | /* |
115 | * receive commit_rxon request | |
116 | * abort any previous channel switch if still in process | |
117 | */ | |
118 | if (priv->switch_rxon.switch_in_progress && | |
119 | (priv->switch_rxon.channel != priv->staging_rxon.channel)) { | |
120 | IWL_DEBUG_11H(priv, "abort channel switch on %d\n", | |
121 | le16_to_cpu(priv->switch_rxon.channel)); | |
122 | priv->switch_rxon.switch_in_progress = false; | |
123 | } | |
124 | ||
b481de9c | 125 | /* If we don't need to send a full RXON, we can use |
5b9f8cd3 | 126 | * iwl_rxon_assoc_cmd which is used to reconfigure filter |
b481de9c | 127 | * and other flags for the current radio configuration. */ |
54559703 | 128 | if (!iwl_full_rxon_required(priv)) { |
43d59b32 EG |
129 | ret = iwl_send_rxon_assoc(priv); |
130 | if (ret) { | |
15b1687c | 131 | IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret); |
43d59b32 | 132 | return ret; |
b481de9c ZY |
133 | } |
134 | ||
135 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
a643565e | 136 | iwl_print_rx_config_cmd(priv); |
b481de9c ZY |
137 | return 0; |
138 | } | |
139 | ||
b481de9c ZY |
140 | /* If we are currently associated and the new config requires |
141 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
142 | * we must clear the associated from the active configuration | |
143 | * before we apply the new config */ | |
43d59b32 | 144 | if (iwl_is_associated(priv) && new_assoc) { |
e1623446 | 145 | IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); |
b481de9c ZY |
146 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
147 | ||
43d59b32 | 148 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, |
c1adf9fb | 149 | sizeof(struct iwl_rxon_cmd), |
b481de9c ZY |
150 | &priv->active_rxon); |
151 | ||
152 | /* If the mask clearing failed then we set | |
153 | * active_rxon back to what it was previously */ | |
43d59b32 | 154 | if (ret) { |
b481de9c | 155 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; |
15b1687c | 156 | IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret); |
43d59b32 | 157 | return ret; |
b481de9c | 158 | } |
2c810ccd | 159 | iwl_clear_ucode_stations(priv); |
7e246191 | 160 | iwl_restore_stations(priv); |
335348b1 JB |
161 | ret = iwl_restore_default_wep_keys(priv); |
162 | if (ret) { | |
163 | IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret); | |
164 | return ret; | |
165 | } | |
b481de9c ZY |
166 | } |
167 | ||
e1623446 | 168 | IWL_DEBUG_INFO(priv, "Sending RXON\n" |
b481de9c ZY |
169 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
170 | "* channel = %d\n" | |
e174961c | 171 | "* bssid = %pM\n", |
43d59b32 | 172 | (new_assoc ? "" : "out"), |
b481de9c | 173 | le16_to_cpu(priv->staging_rxon.channel), |
e174961c | 174 | priv->staging_rxon.bssid_addr); |
b481de9c | 175 | |
90e8e424 | 176 | iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto); |
43d59b32 EG |
177 | |
178 | /* Apply the new configuration | |
7e246191 RC |
179 | * RXON unassoc clears the station table in uCode so restoration of |
180 | * stations is needed after it (the RXON command) completes | |
43d59b32 EG |
181 | */ |
182 | if (!new_assoc) { | |
183 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
c1adf9fb | 184 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); |
43d59b32 | 185 | if (ret) { |
15b1687c | 186 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
187 | return ret; |
188 | } | |
91dd6c27 | 189 | IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n"); |
43d59b32 | 190 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); |
2c810ccd | 191 | iwl_clear_ucode_stations(priv); |
7e246191 | 192 | iwl_restore_stations(priv); |
335348b1 JB |
193 | ret = iwl_restore_default_wep_keys(priv); |
194 | if (ret) { | |
195 | IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret); | |
196 | return ret; | |
197 | } | |
b481de9c ZY |
198 | } |
199 | ||
19cc1087 | 200 | priv->start_calib = 0; |
9185159d | 201 | if (new_assoc) { |
47eef9bd WYG |
202 | /* |
203 | * allow CTS-to-self if possible for new association. | |
204 | * this is relevant only for 5000 series and up, | |
205 | * but will not damage 4965 | |
206 | */ | |
207 | priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN; | |
208 | ||
43d59b32 EG |
209 | /* Apply the new configuration |
210 | * RXON assoc doesn't clear the station table in uCode, | |
211 | */ | |
212 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON, | |
213 | sizeof(struct iwl_rxon_cmd), &priv->staging_rxon); | |
214 | if (ret) { | |
15b1687c | 215 | IWL_ERR(priv, "Error setting new RXON (%d)\n", ret); |
43d59b32 EG |
216 | return ret; |
217 | } | |
218 | memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon)); | |
b481de9c | 219 | } |
a643565e | 220 | iwl_print_rx_config_cmd(priv); |
b481de9c | 221 | |
36da7d70 ZY |
222 | iwl_init_sensitivity(priv); |
223 | ||
224 | /* If we issue a new RXON command which required a tune then we must | |
225 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
226 | ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true); | |
227 | if (ret) { | |
15b1687c | 228 | IWL_ERR(priv, "Error sending TX power (%d)\n", ret); |
36da7d70 ZY |
229 | return ret; |
230 | } | |
231 | ||
b481de9c ZY |
232 | return 0; |
233 | } | |
234 | ||
5b9f8cd3 | 235 | void iwl_update_chain_flags(struct iwl_priv *priv) |
5da4b55f MA |
236 | { |
237 | ||
45823531 AK |
238 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
239 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
e0158e61 | 240 | iwlcore_commit_rxon(priv); |
5da4b55f MA |
241 | } |
242 | ||
fcab423d | 243 | static void iwl_clear_free_frames(struct iwl_priv *priv) |
b481de9c ZY |
244 | { |
245 | struct list_head *element; | |
246 | ||
e1623446 | 247 | IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n", |
b481de9c ZY |
248 | priv->frames_count); |
249 | ||
250 | while (!list_empty(&priv->free_frames)) { | |
251 | element = priv->free_frames.next; | |
252 | list_del(element); | |
fcab423d | 253 | kfree(list_entry(element, struct iwl_frame, list)); |
b481de9c ZY |
254 | priv->frames_count--; |
255 | } | |
256 | ||
257 | if (priv->frames_count) { | |
39aadf8c | 258 | IWL_WARN(priv, "%d frames still in use. Did we lose one?\n", |
b481de9c ZY |
259 | priv->frames_count); |
260 | priv->frames_count = 0; | |
261 | } | |
262 | } | |
263 | ||
fcab423d | 264 | static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv) |
b481de9c | 265 | { |
fcab423d | 266 | struct iwl_frame *frame; |
b481de9c ZY |
267 | struct list_head *element; |
268 | if (list_empty(&priv->free_frames)) { | |
269 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); | |
270 | if (!frame) { | |
15b1687c | 271 | IWL_ERR(priv, "Could not allocate frame!\n"); |
b481de9c ZY |
272 | return NULL; |
273 | } | |
274 | ||
275 | priv->frames_count++; | |
276 | return frame; | |
277 | } | |
278 | ||
279 | element = priv->free_frames.next; | |
280 | list_del(element); | |
fcab423d | 281 | return list_entry(element, struct iwl_frame, list); |
b481de9c ZY |
282 | } |
283 | ||
fcab423d | 284 | static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) |
b481de9c ZY |
285 | { |
286 | memset(frame, 0, sizeof(*frame)); | |
287 | list_add(&frame->list, &priv->free_frames); | |
288 | } | |
289 | ||
47ff65c4 | 290 | static u32 iwl_fill_beacon_frame(struct iwl_priv *priv, |
4bf64efd | 291 | struct ieee80211_hdr *hdr, |
73ec1cc2 | 292 | int left) |
b481de9c | 293 | { |
3109ece1 | 294 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
05c914fe JB |
295 | ((priv->iw_mode != NL80211_IFTYPE_ADHOC) && |
296 | (priv->iw_mode != NL80211_IFTYPE_AP))) | |
b481de9c ZY |
297 | return 0; |
298 | ||
299 | if (priv->ibss_beacon->len > left) | |
300 | return 0; | |
301 | ||
302 | memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len); | |
303 | ||
304 | return priv->ibss_beacon->len; | |
305 | } | |
306 | ||
47ff65c4 DH |
307 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ |
308 | static void iwl_set_beacon_tim(struct iwl_priv *priv, | |
309 | struct iwl_tx_beacon_cmd *tx_beacon_cmd, | |
310 | u8 *beacon, u32 frame_size) | |
311 | { | |
312 | u16 tim_idx; | |
313 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
314 | ||
315 | /* | |
316 | * The index is relative to frame start but we start looking at the | |
317 | * variable-length part of the beacon. | |
318 | */ | |
319 | tim_idx = mgmt->u.beacon.variable - beacon; | |
320 | ||
321 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
322 | while ((tim_idx < (frame_size - 2)) && | |
323 | (beacon[tim_idx] != WLAN_EID_TIM)) | |
324 | tim_idx += beacon[tim_idx+1] + 2; | |
325 | ||
326 | /* If TIM field was found, set variables */ | |
327 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
328 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
329 | tx_beacon_cmd->tim_size = beacon[tim_idx+1]; | |
330 | } else | |
331 | IWL_WARN(priv, "Unable to find TIM Element in beacon\n"); | |
332 | } | |
333 | ||
5b9f8cd3 | 334 | static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv, |
47ff65c4 | 335 | struct iwl_frame *frame) |
4bf64efd TW |
336 | { |
337 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | |
47ff65c4 DH |
338 | u32 frame_size; |
339 | u32 rate_flags; | |
340 | u32 rate; | |
341 | /* | |
342 | * We have to set up the TX command, the TX Beacon command, and the | |
343 | * beacon contents. | |
344 | */ | |
4bf64efd | 345 | |
47ff65c4 | 346 | /* Initialize memory */ |
4bf64efd TW |
347 | tx_beacon_cmd = &frame->u.beacon; |
348 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
349 | ||
47ff65c4 | 350 | /* Set up TX beacon contents */ |
4bf64efd | 351 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, |
4bf64efd | 352 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
47ff65c4 DH |
353 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) |
354 | return 0; | |
4bf64efd | 355 | |
47ff65c4 | 356 | /* Set up TX command fields */ |
4bf64efd | 357 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); |
47ff65c4 DH |
358 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; |
359 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
360 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | |
361 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK; | |
4bf64efd | 362 | |
47ff65c4 DH |
363 | /* Set up TX beacon command fields */ |
364 | iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame, | |
365 | frame_size); | |
4bf64efd | 366 | |
47ff65c4 DH |
367 | /* Set up packet rate and flags */ |
368 | rate = iwl_rate_get_lowest_plcp(priv); | |
369 | priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant); | |
370 | rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant); | |
371 | if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE)) | |
372 | rate_flags |= RATE_MCS_CCK_MSK; | |
373 | tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate, | |
374 | rate_flags); | |
4bf64efd TW |
375 | |
376 | return sizeof(*tx_beacon_cmd) + frame_size; | |
377 | } | |
5b9f8cd3 | 378 | static int iwl_send_beacon_cmd(struct iwl_priv *priv) |
b481de9c | 379 | { |
fcab423d | 380 | struct iwl_frame *frame; |
b481de9c ZY |
381 | unsigned int frame_size; |
382 | int rc; | |
b481de9c | 383 | |
fcab423d | 384 | frame = iwl_get_free_frame(priv); |
b481de9c | 385 | if (!frame) { |
15b1687c | 386 | IWL_ERR(priv, "Could not obtain free frame buffer for beacon " |
b481de9c ZY |
387 | "command.\n"); |
388 | return -ENOMEM; | |
389 | } | |
390 | ||
47ff65c4 DH |
391 | frame_size = iwl_hw_get_beacon_cmd(priv, frame); |
392 | if (!frame_size) { | |
393 | IWL_ERR(priv, "Error configuring the beacon command\n"); | |
394 | iwl_free_frame(priv, frame); | |
395 | return -EINVAL; | |
396 | } | |
b481de9c | 397 | |
857485c0 | 398 | rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size, |
b481de9c ZY |
399 | &frame->u.cmd[0]); |
400 | ||
fcab423d | 401 | iwl_free_frame(priv, frame); |
b481de9c ZY |
402 | |
403 | return rc; | |
404 | } | |
405 | ||
7aaa1d79 SO |
406 | static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
407 | { | |
408 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
409 | ||
410 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
411 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
412 | addr |= | |
413 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
414 | ||
415 | return addr; | |
416 | } | |
417 | ||
418 | static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) | |
419 | { | |
420 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
421 | ||
422 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
423 | } | |
424 | ||
425 | static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, | |
426 | dma_addr_t addr, u16 len) | |
427 | { | |
428 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
429 | u16 hi_n_len = len << 4; | |
430 | ||
431 | put_unaligned_le32(addr, &tb->lo); | |
432 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
433 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
434 | ||
435 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
436 | ||
437 | tfd->num_tbs = idx + 1; | |
438 | } | |
439 | ||
440 | static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd) | |
441 | { | |
442 | return tfd->num_tbs & 0x1f; | |
443 | } | |
444 | ||
445 | /** | |
446 | * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
447 | * @priv - driver private data | |
448 | * @txq - tx queue | |
449 | * | |
450 | * Does NOT advance any TFD circular buffer read/write indexes | |
451 | * Does NOT free the TFD itself (which is within circular buffer) | |
452 | */ | |
453 | void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |
454 | { | |
59606ffa | 455 | struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds; |
7aaa1d79 SO |
456 | struct iwl_tfd *tfd; |
457 | struct pci_dev *dev = priv->pci_dev; | |
458 | int index = txq->q.read_ptr; | |
459 | int i; | |
460 | int num_tbs; | |
461 | ||
462 | tfd = &tfd_tmp[index]; | |
463 | ||
464 | /* Sanity check on number of chunks */ | |
465 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
466 | ||
467 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
468 | IWL_ERR(priv, "Too many chunks: %i\n", num_tbs); | |
469 | /* @todo issue fatal error, it is quite serious situation */ | |
470 | return; | |
471 | } | |
472 | ||
473 | /* Unmap tx_cmd */ | |
474 | if (num_tbs) | |
475 | pci_unmap_single(dev, | |
c2acea8e JB |
476 | pci_unmap_addr(&txq->meta[index], mapping), |
477 | pci_unmap_len(&txq->meta[index], len), | |
96891cee | 478 | PCI_DMA_BIDIRECTIONAL); |
7aaa1d79 SO |
479 | |
480 | /* Unmap chunks, if any. */ | |
481 | for (i = 1; i < num_tbs; i++) { | |
482 | pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i), | |
483 | iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE); | |
484 | ||
485 | if (txq->txb) { | |
486 | dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]); | |
487 | txq->txb[txq->q.read_ptr].skb[i - 1] = NULL; | |
488 | } | |
489 | } | |
490 | } | |
491 | ||
492 | int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, | |
493 | struct iwl_tx_queue *txq, | |
494 | dma_addr_t addr, u16 len, | |
495 | u8 reset, u8 pad) | |
496 | { | |
497 | struct iwl_queue *q; | |
59606ffa | 498 | struct iwl_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
499 | u32 num_tbs; |
500 | ||
501 | q = &txq->q; | |
59606ffa SO |
502 | tfd_tmp = (struct iwl_tfd *)txq->tfds; |
503 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
504 | |
505 | if (reset) | |
506 | memset(tfd, 0, sizeof(*tfd)); | |
507 | ||
508 | num_tbs = iwl_tfd_get_num_tbs(tfd); | |
509 | ||
510 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
511 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
512 | IWL_ERR(priv, "Error can not send more than %d chunks\n", | |
513 | IWL_NUM_OF_TBS); | |
514 | return -EINVAL; | |
515 | } | |
516 | ||
517 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
518 | if (unlikely(addr & ~IWL_TX_DMA_MASK)) | |
519 | IWL_ERR(priv, "Unaligned address = %llx\n", | |
520 | (unsigned long long)addr); | |
521 | ||
522 | iwl_tfd_set_tb(tfd, num_tbs, addr, len); | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
a8e74e27 SO |
527 | /* |
528 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
529 | * given Tx queue, and enable the DMA channel used for that queue. | |
530 | * | |
531 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
532 | * channels supported in hardware. | |
533 | */ | |
534 | int iwl_hw_tx_queue_init(struct iwl_priv *priv, | |
535 | struct iwl_tx_queue *txq) | |
536 | { | |
a8e74e27 SO |
537 | int txq_id = txq->q.id; |
538 | ||
a8e74e27 SO |
539 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
540 | iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), | |
541 | txq->q.dma_addr >> 8); | |
542 | ||
a8e74e27 SO |
543 | return 0; |
544 | } | |
545 | ||
b481de9c ZY |
546 | /****************************************************************************** |
547 | * | |
548 | * Generic RX handler implementations | |
549 | * | |
550 | ******************************************************************************/ | |
885ba202 TW |
551 | static void iwl_rx_reply_alive(struct iwl_priv *priv, |
552 | struct iwl_rx_mem_buffer *rxb) | |
b481de9c | 553 | { |
2f301227 | 554 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
885ba202 | 555 | struct iwl_alive_resp *palive; |
b481de9c ZY |
556 | struct delayed_work *pwork; |
557 | ||
558 | palive = &pkt->u.alive_frame; | |
559 | ||
e1623446 | 560 | IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision " |
b481de9c ZY |
561 | "0x%01X 0x%01X\n", |
562 | palive->is_valid, palive->ver_type, | |
563 | palive->ver_subtype); | |
564 | ||
565 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
e1623446 | 566 | IWL_DEBUG_INFO(priv, "Initialization Alive received.\n"); |
b481de9c ZY |
567 | memcpy(&priv->card_alive_init, |
568 | &pkt->u.alive_frame, | |
885ba202 | 569 | sizeof(struct iwl_init_alive_resp)); |
b481de9c ZY |
570 | pwork = &priv->init_alive_start; |
571 | } else { | |
e1623446 | 572 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c | 573 | memcpy(&priv->card_alive, &pkt->u.alive_frame, |
885ba202 | 574 | sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
575 | pwork = &priv->alive_start; |
576 | } | |
577 | ||
578 | /* We delay the ALIVE response by 5ms to | |
579 | * give the HW RF Kill time to activate... */ | |
580 | if (palive->is_valid == UCODE_VALID_OK) | |
581 | queue_delayed_work(priv->workqueue, pwork, | |
582 | msecs_to_jiffies(5)); | |
583 | else | |
39aadf8c | 584 | IWL_WARN(priv, "uCode did not respond OK.\n"); |
b481de9c ZY |
585 | } |
586 | ||
5b9f8cd3 | 587 | static void iwl_bg_beacon_update(struct work_struct *work) |
b481de9c | 588 | { |
c79dd5b5 TW |
589 | struct iwl_priv *priv = |
590 | container_of(work, struct iwl_priv, beacon_update); | |
b481de9c ZY |
591 | struct sk_buff *beacon; |
592 | ||
593 | /* Pull updated AP beacon from mac80211. will fail if not in AP mode */ | |
e039fa4a | 594 | beacon = ieee80211_beacon_get(priv->hw, priv->vif); |
b481de9c ZY |
595 | |
596 | if (!beacon) { | |
15b1687c | 597 | IWL_ERR(priv, "update beacon failed\n"); |
b481de9c ZY |
598 | return; |
599 | } | |
600 | ||
601 | mutex_lock(&priv->mutex); | |
602 | /* new beacon skb is allocated every time; dispose previous.*/ | |
603 | if (priv->ibss_beacon) | |
604 | dev_kfree_skb(priv->ibss_beacon); | |
605 | ||
606 | priv->ibss_beacon = beacon; | |
607 | mutex_unlock(&priv->mutex); | |
608 | ||
5b9f8cd3 | 609 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
610 | } |
611 | ||
4e39317d | 612 | /** |
5b9f8cd3 | 613 | * iwl_bg_statistics_periodic - Timer callback to queue statistics |
4e39317d EG |
614 | * |
615 | * This callback is provided in order to send a statistics request. | |
616 | * | |
617 | * This timer function is continually reset to execute within | |
618 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
619 | * was received. We need to ensure we receive the statistics in order | |
620 | * to update the temperature used for calibrating the TXPOWER. | |
621 | */ | |
5b9f8cd3 | 622 | static void iwl_bg_statistics_periodic(unsigned long data) |
4e39317d EG |
623 | { |
624 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
625 | ||
626 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
627 | return; | |
628 | ||
61780ee3 MA |
629 | /* dont send host command if rf-kill is on */ |
630 | if (!iwl_is_ready_rf(priv)) | |
631 | return; | |
632 | ||
ef8d5529 | 633 | iwl_send_statistics_request(priv, CMD_ASYNC, false); |
4e39317d EG |
634 | } |
635 | ||
a9e1cb6a WYG |
636 | |
637 | static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base, | |
638 | u32 start_idx, u32 num_events, | |
639 | u32 mode) | |
640 | { | |
641 | u32 i; | |
642 | u32 ptr; /* SRAM byte address of log data */ | |
643 | u32 ev, time, data; /* event log data */ | |
644 | unsigned long reg_flags; | |
645 | ||
646 | if (mode == 0) | |
647 | ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32)); | |
648 | else | |
649 | ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32)); | |
650 | ||
651 | /* Make sure device is powered up for SRAM reads */ | |
652 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
653 | if (iwl_grab_nic_access(priv)) { | |
654 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
655 | return; | |
656 | } | |
657 | ||
658 | /* Set starting address; reads will auto-increment */ | |
659 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
660 | rmb(); | |
661 | ||
662 | /* | |
663 | * "time" is actually "data" for mode 0 (no timestamp). | |
664 | * place event id # at far right for easier visual parsing. | |
665 | */ | |
666 | for (i = 0; i < num_events; i++) { | |
667 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
668 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
669 | if (mode == 0) { | |
670 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
671 | 0, time, ev); | |
672 | } else { | |
673 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
674 | trace_iwlwifi_dev_ucode_cont_event(priv, | |
675 | time, data, ev); | |
676 | } | |
677 | } | |
678 | /* Allow device to power down */ | |
679 | iwl_release_nic_access(priv); | |
680 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
681 | } | |
682 | ||
875295f1 | 683 | static void iwl_continuous_event_trace(struct iwl_priv *priv) |
a9e1cb6a WYG |
684 | { |
685 | u32 capacity; /* event log capacity in # entries */ | |
686 | u32 base; /* SRAM byte address of event log header */ | |
687 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
688 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
689 | u32 next_entry; /* index of next entry to be written by uCode */ | |
690 | ||
691 | if (priv->ucode_type == UCODE_INIT) | |
692 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); | |
693 | else | |
694 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
695 | if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
696 | capacity = iwl_read_targ_mem(priv, base); | |
697 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
698 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
699 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
700 | } else | |
701 | return; | |
702 | ||
703 | if (num_wraps == priv->event_log.num_wraps) { | |
704 | iwl_print_cont_event_trace(priv, | |
705 | base, priv->event_log.next_entry, | |
706 | next_entry - priv->event_log.next_entry, | |
707 | mode); | |
708 | priv->event_log.non_wraps_count++; | |
709 | } else { | |
710 | if ((num_wraps - priv->event_log.num_wraps) > 1) | |
711 | priv->event_log.wraps_more_count++; | |
712 | else | |
713 | priv->event_log.wraps_once_count++; | |
714 | trace_iwlwifi_dev_ucode_wrap_event(priv, | |
715 | num_wraps - priv->event_log.num_wraps, | |
716 | next_entry, priv->event_log.next_entry); | |
717 | if (next_entry < priv->event_log.next_entry) { | |
718 | iwl_print_cont_event_trace(priv, base, | |
719 | priv->event_log.next_entry, | |
720 | capacity - priv->event_log.next_entry, | |
721 | mode); | |
722 | ||
723 | iwl_print_cont_event_trace(priv, base, 0, | |
724 | next_entry, mode); | |
725 | } else { | |
726 | iwl_print_cont_event_trace(priv, base, | |
727 | next_entry, capacity - next_entry, | |
728 | mode); | |
729 | ||
730 | iwl_print_cont_event_trace(priv, base, 0, | |
731 | next_entry, mode); | |
732 | } | |
733 | } | |
734 | priv->event_log.num_wraps = num_wraps; | |
735 | priv->event_log.next_entry = next_entry; | |
736 | } | |
737 | ||
738 | /** | |
739 | * iwl_bg_ucode_trace - Timer callback to log ucode event | |
740 | * | |
741 | * The timer is continually set to execute every | |
742 | * UCODE_TRACE_PERIOD milliseconds after the last timer expired | |
743 | * this function is to perform continuous uCode event logging operation | |
744 | * if enabled | |
745 | */ | |
746 | static void iwl_bg_ucode_trace(unsigned long data) | |
747 | { | |
748 | struct iwl_priv *priv = (struct iwl_priv *)data; | |
749 | ||
750 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
751 | return; | |
752 | ||
753 | if (priv->event_log.ucode_trace) { | |
754 | iwl_continuous_event_trace(priv); | |
755 | /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */ | |
756 | mod_timer(&priv->ucode_trace, | |
757 | jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD)); | |
758 | } | |
759 | } | |
760 | ||
5b9f8cd3 | 761 | static void iwl_rx_beacon_notif(struct iwl_priv *priv, |
a55360e4 | 762 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 763 | { |
0a6857e7 | 764 | #ifdef CONFIG_IWLWIFI_DEBUG |
2f301227 | 765 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
2aa6ab86 TW |
766 | struct iwl4965_beacon_notif *beacon = |
767 | (struct iwl4965_beacon_notif *)pkt->u.raw; | |
e7d326ac | 768 | u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
b481de9c | 769 | |
e1623446 | 770 | IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d " |
b481de9c | 771 | "tsf %d %d rate %d\n", |
25a6572c | 772 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
b481de9c ZY |
773 | beacon->beacon_notify_hdr.failure_frame, |
774 | le32_to_cpu(beacon->ibss_mgr_status), | |
775 | le32_to_cpu(beacon->high_tsf), | |
776 | le32_to_cpu(beacon->low_tsf), rate); | |
777 | #endif | |
778 | ||
05c914fe | 779 | if ((priv->iw_mode == NL80211_IFTYPE_AP) && |
b481de9c ZY |
780 | (!test_bit(STATUS_EXIT_PENDING, &priv->status))) |
781 | queue_work(priv->workqueue, &priv->beacon_update); | |
782 | } | |
783 | ||
b481de9c ZY |
784 | /* Handle notification from uCode that card's power state is changing |
785 | * due to software, hardware, or critical temperature RFKILL */ | |
5b9f8cd3 | 786 | static void iwl_rx_card_state_notif(struct iwl_priv *priv, |
a55360e4 | 787 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 788 | { |
2f301227 | 789 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
b481de9c ZY |
790 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
791 | unsigned long status = priv->status; | |
792 | ||
3a41bbd5 | 793 | IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n", |
b481de9c | 794 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
3a41bbd5 WYG |
795 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", |
796 | (flags & CT_CARD_DISABLED) ? | |
797 | "Reached" : "Not reached"); | |
b481de9c ZY |
798 | |
799 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | | |
3a41bbd5 | 800 | CT_CARD_DISABLED)) { |
b481de9c | 801 | |
3395f6e9 | 802 | iwl_write32(priv, CSR_UCODE_DRV_GP1_SET, |
b481de9c ZY |
803 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
804 | ||
a8b50a0a MA |
805 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
806 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | |
b481de9c ZY |
807 | |
808 | if (!(flags & RXON_CARD_DISABLED)) { | |
3395f6e9 | 809 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c | 810 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
a8b50a0a | 811 | iwl_write_direct32(priv, HBUS_TARG_MBX_C, |
b481de9c | 812 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
b481de9c | 813 | } |
3a41bbd5 | 814 | if (flags & CT_CARD_DISABLED) |
39b73fb1 | 815 | iwl_tt_enter_ct_kill(priv); |
b481de9c | 816 | } |
3a41bbd5 | 817 | if (!(flags & CT_CARD_DISABLED)) |
39b73fb1 | 818 | iwl_tt_exit_ct_kill(priv); |
b481de9c ZY |
819 | |
820 | if (flags & HW_CARD_DISABLED) | |
821 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
822 | else | |
823 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
824 | ||
825 | ||
b481de9c | 826 | if (!(flags & RXON_CARD_DISABLED)) |
2a421b91 | 827 | iwl_scan_cancel(priv); |
b481de9c ZY |
828 | |
829 | if ((test_bit(STATUS_RF_KILL_HW, &status) != | |
a60e77e5 JB |
830 | test_bit(STATUS_RF_KILL_HW, &priv->status))) |
831 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, | |
832 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
b481de9c ZY |
833 | else |
834 | wake_up_interruptible(&priv->wait_command_queue); | |
835 | } | |
836 | ||
5b9f8cd3 | 837 | int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
e2e3c57b | 838 | { |
e2e3c57b | 839 | if (src == IWL_PWR_SRC_VAUX) { |
3fdb68de | 840 | if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) |
e2e3c57b TW |
841 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
842 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
843 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
844 | } else { | |
845 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
846 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | |
847 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
848 | } | |
849 | ||
a8b50a0a | 850 | return 0; |
e2e3c57b TW |
851 | } |
852 | ||
b481de9c | 853 | /** |
5b9f8cd3 | 854 | * iwl_setup_rx_handlers - Initialize Rx handler callbacks |
b481de9c ZY |
855 | * |
856 | * Setup the RX handlers for each of the reply types sent from the uCode | |
857 | * to the host. | |
858 | * | |
859 | * This function chains into the hardware specific files for them to setup | |
860 | * any hardware specific handlers as well. | |
861 | */ | |
653fa4a0 | 862 | static void iwl_setup_rx_handlers(struct iwl_priv *priv) |
b481de9c | 863 | { |
885ba202 | 864 | priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive; |
5b9f8cd3 EG |
865 | priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error; |
866 | priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa; | |
81963d68 RC |
867 | priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] = |
868 | iwl_rx_spectrum_measure_notif; | |
5b9f8cd3 | 869 | priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif; |
b481de9c | 870 | priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] = |
5b9f8cd3 EG |
871 | iwl_rx_pm_debug_statistics_notif; |
872 | priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif; | |
b481de9c | 873 | |
9fbab516 BC |
874 | /* |
875 | * The same handler is used for both the REPLY to a discrete | |
876 | * statistics request from the host as well as for the periodic | |
877 | * statistics notifications (after received beacons) from the uCode. | |
b481de9c | 878 | */ |
ef8d5529 | 879 | priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics; |
8f91aecb | 880 | priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics; |
2a421b91 TW |
881 | |
882 | iwl_setup_rx_scan_handlers(priv); | |
883 | ||
37a44211 | 884 | /* status change handler */ |
5b9f8cd3 | 885 | priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif; |
b481de9c | 886 | |
c1354754 TW |
887 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = |
888 | iwl_rx_missed_beacon_notif; | |
37a44211 | 889 | /* Rx handlers */ |
8d801080 WYG |
890 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy; |
891 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx; | |
653fa4a0 | 892 | /* block ack */ |
74bcdb33 | 893 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba; |
9fbab516 | 894 | /* Set up hardware specific Rx handlers */ |
d4789efe | 895 | priv->cfg->ops->lib->rx_handler_setup(priv); |
b481de9c ZY |
896 | } |
897 | ||
b481de9c | 898 | /** |
a55360e4 | 899 | * iwl_rx_handle - Main entry function for receiving responses from uCode |
b481de9c ZY |
900 | * |
901 | * Uses the priv->rx_handlers callback function array to invoke | |
902 | * the appropriate handlers, including command responses, | |
903 | * frame-received notifications, and other notifications. | |
904 | */ | |
a55360e4 | 905 | void iwl_rx_handle(struct iwl_priv *priv) |
b481de9c | 906 | { |
a55360e4 | 907 | struct iwl_rx_mem_buffer *rxb; |
db11d634 | 908 | struct iwl_rx_packet *pkt; |
a55360e4 | 909 | struct iwl_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
910 | u32 r, i; |
911 | int reclaim; | |
912 | unsigned long flags; | |
5c0eef96 | 913 | u8 fill_rx = 0; |
d68ab680 | 914 | u32 count = 8; |
4752c93c | 915 | int total_empty; |
b481de9c | 916 | |
6440adb5 CB |
917 | /* uCode's read index (stored in shared DRAM) indicates the last Rx |
918 | * buffer that the driver may process (last buffer filled by ucode). */ | |
8d86422a | 919 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
b481de9c ZY |
920 | i = rxq->read; |
921 | ||
922 | /* Rx interrupt, but nothing sent from uCode */ | |
923 | if (i == r) | |
e1623446 | 924 | IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i); |
b481de9c | 925 | |
4752c93c | 926 | /* calculate total frames need to be restock after handling RX */ |
7300515d | 927 | total_empty = r - rxq->write_actual; |
4752c93c MA |
928 | if (total_empty < 0) |
929 | total_empty += RX_QUEUE_SIZE; | |
930 | ||
931 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
5c0eef96 MA |
932 | fill_rx = 1; |
933 | ||
b481de9c ZY |
934 | while (i != r) { |
935 | rxb = rxq->queue[i]; | |
936 | ||
9fbab516 | 937 | /* If an RXB doesn't have a Rx queue slot associated with it, |
b481de9c ZY |
938 | * then a bug has been introduced in the queue refilling |
939 | * routines -- catch it here */ | |
940 | BUG_ON(rxb == NULL); | |
941 | ||
942 | rxq->queue[i] = NULL; | |
943 | ||
2f301227 ZY |
944 | pci_unmap_page(priv->pci_dev, rxb->page_dma, |
945 | PAGE_SIZE << priv->hw_params.rx_page_order, | |
946 | PCI_DMA_FROMDEVICE); | |
947 | pkt = rxb_addr(rxb); | |
b481de9c | 948 | |
be1a71a1 JB |
949 | trace_iwlwifi_dev_rx(priv, pkt, |
950 | le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK); | |
951 | ||
b481de9c ZY |
952 | /* Reclaim a command buffer only if this packet is a response |
953 | * to a (driver-originated) command. | |
954 | * If the packet (e.g. Rx frame) originated from uCode, | |
955 | * there is no command buffer to reclaim. | |
956 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
957 | * but apparently a few don't get set; catch them here. */ | |
958 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
959 | (pkt->hdr.cmd != REPLY_RX_PHY_CMD) && | |
857485c0 | 960 | (pkt->hdr.cmd != REPLY_RX) && |
7dddaf1a | 961 | (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) && |
cfe01709 | 962 | (pkt->hdr.cmd != REPLY_COMPRESSED_BA) && |
b481de9c ZY |
963 | (pkt->hdr.cmd != STATISTICS_NOTIFICATION) && |
964 | (pkt->hdr.cmd != REPLY_TX); | |
965 | ||
966 | /* Based on type of command response or notification, | |
967 | * handle those that need handling via function in | |
5b9f8cd3 | 968 | * rx_handlers table. See iwl_setup_rx_handlers() */ |
b481de9c | 969 | if (priv->rx_handlers[pkt->hdr.cmd]) { |
e1623446 | 970 | IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r, |
f3d67999 | 971 | i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); |
a83b9141 | 972 | priv->isr_stats.rx_handlers[pkt->hdr.cmd]++; |
29b1b268 | 973 | priv->rx_handlers[pkt->hdr.cmd] (priv, rxb); |
b481de9c ZY |
974 | } else { |
975 | /* No handling needed */ | |
e1623446 | 976 | IWL_DEBUG_RX(priv, |
b481de9c ZY |
977 | "r %d i %d No handler needed for %s, 0x%02x\n", |
978 | r, i, get_cmd_string(pkt->hdr.cmd), | |
979 | pkt->hdr.cmd); | |
980 | } | |
981 | ||
29b1b268 ZY |
982 | /* |
983 | * XXX: After here, we should always check rxb->page | |
984 | * against NULL before touching it or its virtual | |
985 | * memory (pkt). Because some rx_handler might have | |
986 | * already taken or freed the pages. | |
987 | */ | |
988 | ||
b481de9c | 989 | if (reclaim) { |
2f301227 ZY |
990 | /* Invoke any callbacks, transfer the buffer to caller, |
991 | * and fire off the (possibly) blocking iwl_send_cmd() | |
b481de9c | 992 | * as we reclaim the driver command queue */ |
29b1b268 | 993 | if (rxb->page) |
17b88929 | 994 | iwl_tx_cmd_complete(priv, rxb); |
b481de9c | 995 | else |
39aadf8c | 996 | IWL_WARN(priv, "Claim null rxb?\n"); |
b481de9c ZY |
997 | } |
998 | ||
7300515d ZY |
999 | /* Reuse the page if possible. For notification packets and |
1000 | * SKBs that fail to Rx correctly, add them back into the | |
1001 | * rx_free list for reuse later. */ | |
1002 | spin_lock_irqsave(&rxq->lock, flags); | |
2f301227 | 1003 | if (rxb->page != NULL) { |
7300515d ZY |
1004 | rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page, |
1005 | 0, PAGE_SIZE << priv->hw_params.rx_page_order, | |
1006 | PCI_DMA_FROMDEVICE); | |
1007 | list_add_tail(&rxb->list, &rxq->rx_free); | |
1008 | rxq->free_count++; | |
1009 | } else | |
1010 | list_add_tail(&rxb->list, &rxq->rx_used); | |
b481de9c | 1011 | |
b481de9c | 1012 | spin_unlock_irqrestore(&rxq->lock, flags); |
7300515d | 1013 | |
b481de9c | 1014 | i = (i + 1) & RX_QUEUE_MASK; |
5c0eef96 MA |
1015 | /* If there are a lot of unused frames, |
1016 | * restock the Rx queue so ucode wont assert. */ | |
1017 | if (fill_rx) { | |
1018 | count++; | |
1019 | if (count >= 8) { | |
7300515d | 1020 | rxq->read = i; |
54b81550 | 1021 | iwlagn_rx_replenish_now(priv); |
5c0eef96 MA |
1022 | count = 0; |
1023 | } | |
1024 | } | |
b481de9c ZY |
1025 | } |
1026 | ||
1027 | /* Backtrack one entry */ | |
7300515d | 1028 | rxq->read = i; |
4752c93c | 1029 | if (fill_rx) |
54b81550 | 1030 | iwlagn_rx_replenish_now(priv); |
4752c93c | 1031 | else |
54b81550 | 1032 | iwlagn_rx_queue_restock(priv); |
a55360e4 | 1033 | } |
a55360e4 | 1034 | |
0359facc MA |
1035 | /* call this function to flush any scheduled tasklet */ |
1036 | static inline void iwl_synchronize_irq(struct iwl_priv *priv) | |
1037 | { | |
a96a27f9 | 1038 | /* wait to make sure we flush pending tasklet*/ |
0359facc MA |
1039 | synchronize_irq(priv->pci_dev->irq); |
1040 | tasklet_kill(&priv->irq_tasklet); | |
1041 | } | |
1042 | ||
ef850d7c | 1043 | static void iwl_irq_tasklet_legacy(struct iwl_priv *priv) |
b481de9c ZY |
1044 | { |
1045 | u32 inta, handled = 0; | |
1046 | u32 inta_fh; | |
1047 | unsigned long flags; | |
c2e61da2 | 1048 | u32 i; |
0a6857e7 | 1049 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
1050 | u32 inta_mask; |
1051 | #endif | |
1052 | ||
1053 | spin_lock_irqsave(&priv->lock, flags); | |
1054 | ||
1055 | /* Ack/clear/reset pending uCode interrupts. | |
1056 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1057 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
3395f6e9 TW |
1058 | inta = iwl_read32(priv, CSR_INT); |
1059 | iwl_write32(priv, CSR_INT, inta); | |
b481de9c ZY |
1060 | |
1061 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
1062 | * Any new interrupts that happen after this, either while we're | |
1063 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
3395f6e9 TW |
1064 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); |
1065 | iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh); | |
b481de9c | 1066 | |
0a6857e7 | 1067 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1068 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
9fbab516 | 1069 | /* just for debug */ |
3395f6e9 | 1070 | inta_mask = iwl_read32(priv, CSR_INT_MASK); |
e1623446 | 1071 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", |
b481de9c ZY |
1072 | inta, inta_mask, inta_fh); |
1073 | } | |
1074 | #endif | |
1075 | ||
2f301227 ZY |
1076 | spin_unlock_irqrestore(&priv->lock, flags); |
1077 | ||
b481de9c ZY |
1078 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not |
1079 | * atomic, make sure that inta covers all the interrupts that | |
1080 | * we've discovered, even if FH interrupt came in just after | |
1081 | * reading CSR_INT. */ | |
6f83eaa1 | 1082 | if (inta_fh & CSR49_FH_INT_RX_MASK) |
b481de9c | 1083 | inta |= CSR_INT_BIT_FH_RX; |
6f83eaa1 | 1084 | if (inta_fh & CSR49_FH_INT_TX_MASK) |
b481de9c ZY |
1085 | inta |= CSR_INT_BIT_FH_TX; |
1086 | ||
1087 | /* Now service all interrupt bits discovered above. */ | |
1088 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1089 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
b481de9c ZY |
1090 | |
1091 | /* Tell the device to stop sending interrupts */ | |
5b9f8cd3 | 1092 | iwl_disable_interrupts(priv); |
b481de9c | 1093 | |
a83b9141 | 1094 | priv->isr_stats.hw++; |
5b9f8cd3 | 1095 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1096 | |
1097 | handled |= CSR_INT_BIT_HW_ERR; | |
1098 | ||
b481de9c ZY |
1099 | return; |
1100 | } | |
1101 | ||
0a6857e7 | 1102 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1103 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
b481de9c | 1104 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
a83b9141 | 1105 | if (inta & CSR_INT_BIT_SCD) { |
e1623446 | 1106 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " |
25c03d8e | 1107 | "the frame/frames.\n"); |
a83b9141 WYG |
1108 | priv->isr_stats.sch++; |
1109 | } | |
b481de9c ZY |
1110 | |
1111 | /* Alive notification via Rx interrupt will do the real work */ | |
a83b9141 | 1112 | if (inta & CSR_INT_BIT_ALIVE) { |
e1623446 | 1113 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); |
a83b9141 WYG |
1114 | priv->isr_stats.alive++; |
1115 | } | |
b481de9c ZY |
1116 | } |
1117 | #endif | |
1118 | /* Safely ignore these bits for debug checks below */ | |
25c03d8e | 1119 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); |
b481de9c | 1120 | |
9fbab516 | 1121 | /* HW RF KILL switch toggled */ |
b481de9c ZY |
1122 | if (inta & CSR_INT_BIT_RF_KILL) { |
1123 | int hw_rf_kill = 0; | |
3395f6e9 | 1124 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & |
b481de9c ZY |
1125 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
1126 | hw_rf_kill = 1; | |
1127 | ||
4c423a2b | 1128 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
c3056065 | 1129 | hw_rf_kill ? "disable radio" : "enable radio"); |
b481de9c | 1130 | |
a83b9141 WYG |
1131 | priv->isr_stats.rfkill++; |
1132 | ||
a9efa652 | 1133 | /* driver only loads ucode once setting the interface up. |
6cd0b1cb HS |
1134 | * the driver allows loading the ucode even if the radio |
1135 | * is killed. Hence update the killswitch state here. The | |
1136 | * rfkill handler will care about restarting if needed. | |
a9efa652 | 1137 | */ |
6cd0b1cb HS |
1138 | if (!test_bit(STATUS_ALIVE, &priv->status)) { |
1139 | if (hw_rf_kill) | |
1140 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1141 | else | |
1142 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1143 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
edb34228 | 1144 | } |
b481de9c ZY |
1145 | |
1146 | handled |= CSR_INT_BIT_RF_KILL; | |
1147 | } | |
1148 | ||
9fbab516 | 1149 | /* Chip got too hot and stopped itself */ |
b481de9c | 1150 | if (inta & CSR_INT_BIT_CT_KILL) { |
15b1687c | 1151 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); |
a83b9141 | 1152 | priv->isr_stats.ctkill++; |
b481de9c ZY |
1153 | handled |= CSR_INT_BIT_CT_KILL; |
1154 | } | |
1155 | ||
1156 | /* Error detected by uCode */ | |
1157 | if (inta & CSR_INT_BIT_SW_ERR) { | |
15b1687c WT |
1158 | IWL_ERR(priv, "Microcode SW error detected. " |
1159 | " Restarting 0x%X.\n", inta); | |
a83b9141 WYG |
1160 | priv->isr_stats.sw++; |
1161 | priv->isr_stats.sw_err = inta; | |
5b9f8cd3 | 1162 | iwl_irq_handle_error(priv); |
b481de9c ZY |
1163 | handled |= CSR_INT_BIT_SW_ERR; |
1164 | } | |
1165 | ||
c2e61da2 BC |
1166 | /* |
1167 | * uCode wakes up after power-down sleep. | |
1168 | * Tell device about any new tx or host commands enqueued, | |
1169 | * and about any Rx buffers made available while asleep. | |
1170 | */ | |
b481de9c | 1171 | if (inta & CSR_INT_BIT_WAKEUP) { |
e1623446 | 1172 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); |
a55360e4 | 1173 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); |
c2e61da2 BC |
1174 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1175 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
a83b9141 | 1176 | priv->isr_stats.wakeup++; |
b481de9c ZY |
1177 | handled |= CSR_INT_BIT_WAKEUP; |
1178 | } | |
1179 | ||
1180 | /* All uCode command responses, including Tx command responses, | |
1181 | * Rx "responses" (frame-received notification), and other | |
1182 | * notifications from uCode come through here*/ | |
1183 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
a55360e4 | 1184 | iwl_rx_handle(priv); |
a83b9141 | 1185 | priv->isr_stats.rx++; |
b481de9c ZY |
1186 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
1187 | } | |
1188 | ||
c72cd19f | 1189 | /* This "Tx" DMA channel is used only for loading uCode */ |
b481de9c | 1190 | if (inta & CSR_INT_BIT_FH_TX) { |
c72cd19f | 1191 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
a83b9141 | 1192 | priv->isr_stats.tx++; |
b481de9c | 1193 | handled |= CSR_INT_BIT_FH_TX; |
c72cd19f | 1194 | /* Wake up uCode load routine, now that load is complete */ |
dbb983b7 RR |
1195 | priv->ucode_write_complete = 1; |
1196 | wake_up_interruptible(&priv->wait_command_queue); | |
b481de9c ZY |
1197 | } |
1198 | ||
a83b9141 | 1199 | if (inta & ~handled) { |
15b1687c | 1200 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); |
a83b9141 WYG |
1201 | priv->isr_stats.unhandled++; |
1202 | } | |
b481de9c | 1203 | |
40cefda9 | 1204 | if (inta & ~(priv->inta_mask)) { |
39aadf8c | 1205 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1206 | inta & ~priv->inta_mask); |
39aadf8c | 1207 | IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh); |
b481de9c ZY |
1208 | } |
1209 | ||
1210 | /* Re-enable all interrupts */ | |
0359facc MA |
1211 | /* only Re-enable if diabled by irq */ |
1212 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
5b9f8cd3 | 1213 | iwl_enable_interrupts(priv); |
b481de9c | 1214 | |
0a6857e7 | 1215 | #ifdef CONFIG_IWLWIFI_DEBUG |
3d816c77 | 1216 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
3395f6e9 TW |
1217 | inta = iwl_read32(priv, CSR_INT); |
1218 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1219 | inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS); | |
e1623446 | 1220 | IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
b481de9c ZY |
1221 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); |
1222 | } | |
1223 | #endif | |
b481de9c ZY |
1224 | } |
1225 | ||
ef850d7c MA |
1226 | /* tasklet for iwlagn interrupt */ |
1227 | static void iwl_irq_tasklet(struct iwl_priv *priv) | |
1228 | { | |
1229 | u32 inta = 0; | |
1230 | u32 handled = 0; | |
1231 | unsigned long flags; | |
8756990f | 1232 | u32 i; |
ef850d7c MA |
1233 | #ifdef CONFIG_IWLWIFI_DEBUG |
1234 | u32 inta_mask; | |
1235 | #endif | |
1236 | ||
1237 | spin_lock_irqsave(&priv->lock, flags); | |
1238 | ||
1239 | /* Ack/clear/reset pending uCode interrupts. | |
1240 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
1241 | */ | |
48a6be6a SZ |
1242 | /* There is a hardware bug in the interrupt mask function that some |
1243 | * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if | |
1244 | * they are disabled in the CSR_INT_MASK register. Furthermore the | |
1245 | * ICT interrupt handling mechanism has another bug that might cause | |
1246 | * these unmasked interrupts fail to be detected. We workaround the | |
1247 | * hardware bugs here by ACKing all the possible interrupts so that | |
1248 | * interrupt coalescing can still be achieved. | |
1249 | */ | |
0f2df9ea | 1250 | iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask); |
ef850d7c | 1251 | |
a4c8b2a6 | 1252 | inta = priv->_agn.inta; |
ef850d7c MA |
1253 | |
1254 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1255 | if (iwl_get_debug_level(priv) & IWL_DL_ISR) { |
ef850d7c MA |
1256 | /* just for debug */ |
1257 | inta_mask = iwl_read32(priv, CSR_INT_MASK); | |
1258 | IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ", | |
1259 | inta, inta_mask); | |
1260 | } | |
1261 | #endif | |
2f301227 ZY |
1262 | |
1263 | spin_unlock_irqrestore(&priv->lock, flags); | |
1264 | ||
a4c8b2a6 JB |
1265 | /* saved interrupt in inta variable now we can reset priv->_agn.inta */ |
1266 | priv->_agn.inta = 0; | |
ef850d7c MA |
1267 | |
1268 | /* Now service all interrupt bits discovered above. */ | |
1269 | if (inta & CSR_INT_BIT_HW_ERR) { | |
58dba728 | 1270 | IWL_ERR(priv, "Hardware error detected. Restarting.\n"); |
ef850d7c MA |
1271 | |
1272 | /* Tell the device to stop sending interrupts */ | |
1273 | iwl_disable_interrupts(priv); | |
1274 | ||
1275 | priv->isr_stats.hw++; | |
1276 | iwl_irq_handle_error(priv); | |
1277 | ||
1278 | handled |= CSR_INT_BIT_HW_ERR; | |
1279 | ||
ef850d7c MA |
1280 | return; |
1281 | } | |
1282 | ||
1283 | #ifdef CONFIG_IWLWIFI_DEBUG | |
3d816c77 | 1284 | if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) { |
ef850d7c MA |
1285 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
1286 | if (inta & CSR_INT_BIT_SCD) { | |
1287 | IWL_DEBUG_ISR(priv, "Scheduler finished to transmit " | |
1288 | "the frame/frames.\n"); | |
1289 | priv->isr_stats.sch++; | |
1290 | } | |
1291 | ||
1292 | /* Alive notification via Rx interrupt will do the real work */ | |
1293 | if (inta & CSR_INT_BIT_ALIVE) { | |
1294 | IWL_DEBUG_ISR(priv, "Alive interrupt\n"); | |
1295 | priv->isr_stats.alive++; | |
1296 | } | |
1297 | } | |
1298 | #endif | |
1299 | /* Safely ignore these bits for debug checks below */ | |
1300 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
1301 | ||
1302 | /* HW RF KILL switch toggled */ | |
1303 | if (inta & CSR_INT_BIT_RF_KILL) { | |
1304 | int hw_rf_kill = 0; | |
1305 | if (!(iwl_read32(priv, CSR_GP_CNTRL) & | |
1306 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
1307 | hw_rf_kill = 1; | |
1308 | ||
4c423a2b | 1309 | IWL_WARN(priv, "RF_KILL bit toggled to %s.\n", |
ef850d7c MA |
1310 | hw_rf_kill ? "disable radio" : "enable radio"); |
1311 | ||
1312 | priv->isr_stats.rfkill++; | |
1313 | ||
1314 | /* driver only loads ucode once setting the interface up. | |
1315 | * the driver allows loading the ucode even if the radio | |
1316 | * is killed. Hence update the killswitch state here. The | |
1317 | * rfkill handler will care about restarting if needed. | |
1318 | */ | |
1319 | if (!test_bit(STATUS_ALIVE, &priv->status)) { | |
1320 | if (hw_rf_kill) | |
1321 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
1322 | else | |
1323 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
a60e77e5 | 1324 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill); |
ef850d7c MA |
1325 | } |
1326 | ||
1327 | handled |= CSR_INT_BIT_RF_KILL; | |
1328 | } | |
1329 | ||
1330 | /* Chip got too hot and stopped itself */ | |
1331 | if (inta & CSR_INT_BIT_CT_KILL) { | |
1332 | IWL_ERR(priv, "Microcode CT kill error detected.\n"); | |
1333 | priv->isr_stats.ctkill++; | |
1334 | handled |= CSR_INT_BIT_CT_KILL; | |
1335 | } | |
1336 | ||
1337 | /* Error detected by uCode */ | |
1338 | if (inta & CSR_INT_BIT_SW_ERR) { | |
1339 | IWL_ERR(priv, "Microcode SW error detected. " | |
1340 | " Restarting 0x%X.\n", inta); | |
1341 | priv->isr_stats.sw++; | |
1342 | priv->isr_stats.sw_err = inta; | |
1343 | iwl_irq_handle_error(priv); | |
1344 | handled |= CSR_INT_BIT_SW_ERR; | |
1345 | } | |
1346 | ||
1347 | /* uCode wakes up after power-down sleep */ | |
1348 | if (inta & CSR_INT_BIT_WAKEUP) { | |
1349 | IWL_DEBUG_ISR(priv, "Wakeup interrupt\n"); | |
1350 | iwl_rx_queue_update_write_ptr(priv, &priv->rxq); | |
8756990f BC |
1351 | for (i = 0; i < priv->hw_params.max_txq_num; i++) |
1352 | iwl_txq_update_write_ptr(priv, &priv->txq[i]); | |
ef850d7c MA |
1353 | |
1354 | priv->isr_stats.wakeup++; | |
1355 | ||
1356 | handled |= CSR_INT_BIT_WAKEUP; | |
1357 | } | |
1358 | ||
1359 | /* All uCode command responses, including Tx command responses, | |
1360 | * Rx "responses" (frame-received notification), and other | |
1361 | * notifications from uCode come through here*/ | |
40cefda9 MA |
1362 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX | |
1363 | CSR_INT_BIT_RX_PERIODIC)) { | |
ef850d7c | 1364 | IWL_DEBUG_ISR(priv, "Rx interrupt\n"); |
40cefda9 MA |
1365 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { |
1366 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); | |
1367 | iwl_write32(priv, CSR_FH_INT_STATUS, | |
1368 | CSR49_FH_INT_RX_MASK); | |
1369 | } | |
1370 | if (inta & CSR_INT_BIT_RX_PERIODIC) { | |
1371 | handled |= CSR_INT_BIT_RX_PERIODIC; | |
1372 | iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC); | |
1373 | } | |
1374 | /* Sending RX interrupt require many steps to be done in the | |
1375 | * the device: | |
1376 | * 1- write interrupt to current index in ICT table. | |
1377 | * 2- dma RX frame. | |
1378 | * 3- update RX shared data to indicate last write index. | |
1379 | * 4- send interrupt. | |
1380 | * This could lead to RX race, driver could receive RX interrupt | |
74ba67ed BC |
1381 | * but the shared data changes does not reflect this; |
1382 | * periodic interrupt will detect any dangling Rx activity. | |
40cefda9 | 1383 | */ |
74ba67ed BC |
1384 | |
1385 | /* Disable periodic interrupt; we use it as just a one-shot. */ | |
1386 | iwl_write8(priv, CSR_INT_PERIODIC_REG, | |
40cefda9 | 1387 | CSR_INT_PERIODIC_DIS); |
ef850d7c | 1388 | iwl_rx_handle(priv); |
74ba67ed BC |
1389 | |
1390 | /* | |
1391 | * Enable periodic interrupt in 8 msec only if we received | |
1392 | * real RX interrupt (instead of just periodic int), to catch | |
1393 | * any dangling Rx interrupt. If it was just the periodic | |
1394 | * interrupt, there was no dangling Rx activity, and no need | |
1395 | * to extend the periodic interrupt; one-shot is enough. | |
1396 | */ | |
40cefda9 | 1397 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) |
74ba67ed | 1398 | iwl_write8(priv, CSR_INT_PERIODIC_REG, |
40cefda9 MA |
1399 | CSR_INT_PERIODIC_ENA); |
1400 | ||
ef850d7c | 1401 | priv->isr_stats.rx++; |
ef850d7c MA |
1402 | } |
1403 | ||
c72cd19f | 1404 | /* This "Tx" DMA channel is used only for loading uCode */ |
ef850d7c MA |
1405 | if (inta & CSR_INT_BIT_FH_TX) { |
1406 | iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); | |
c72cd19f | 1407 | IWL_DEBUG_ISR(priv, "uCode load interrupt\n"); |
ef850d7c MA |
1408 | priv->isr_stats.tx++; |
1409 | handled |= CSR_INT_BIT_FH_TX; | |
c72cd19f | 1410 | /* Wake up uCode load routine, now that load is complete */ |
ef850d7c MA |
1411 | priv->ucode_write_complete = 1; |
1412 | wake_up_interruptible(&priv->wait_command_queue); | |
1413 | } | |
1414 | ||
1415 | if (inta & ~handled) { | |
1416 | IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled); | |
1417 | priv->isr_stats.unhandled++; | |
1418 | } | |
1419 | ||
40cefda9 | 1420 | if (inta & ~(priv->inta_mask)) { |
ef850d7c | 1421 | IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n", |
40cefda9 | 1422 | inta & ~priv->inta_mask); |
ef850d7c MA |
1423 | } |
1424 | ||
ef850d7c MA |
1425 | /* Re-enable all interrupts */ |
1426 | /* only Re-enable if diabled by irq */ | |
1427 | if (test_bit(STATUS_INT_ENABLED, &priv->status)) | |
1428 | iwl_enable_interrupts(priv); | |
ef850d7c MA |
1429 | } |
1430 | ||
872c8ddc WYG |
1431 | /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */ |
1432 | #define ACK_CNT_RATIO (50) | |
1433 | #define BA_TIMEOUT_CNT (5) | |
1434 | #define BA_TIMEOUT_MAX (16) | |
1435 | ||
1436 | /** | |
1437 | * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries. | |
1438 | * | |
1439 | * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding | |
1440 | * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal | |
1441 | * operation state. | |
1442 | */ | |
1443 | bool iwl_good_ack_health(struct iwl_priv *priv, | |
1444 | struct iwl_rx_packet *pkt) | |
1445 | { | |
1446 | bool rc = true; | |
1447 | int actual_ack_cnt_delta, expected_ack_cnt_delta; | |
1448 | int ba_timeout_delta; | |
1449 | ||
1450 | actual_ack_cnt_delta = | |
1451 | le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) - | |
a2064b7a | 1452 | le32_to_cpu(priv->_agn.statistics.tx.actual_ack_cnt); |
872c8ddc WYG |
1453 | expected_ack_cnt_delta = |
1454 | le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) - | |
a2064b7a | 1455 | le32_to_cpu(priv->_agn.statistics.tx.expected_ack_cnt); |
872c8ddc WYG |
1456 | ba_timeout_delta = |
1457 | le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) - | |
a2064b7a | 1458 | le32_to_cpu(priv->_agn.statistics.tx.agg.ba_timeout); |
872c8ddc WYG |
1459 | if ((priv->_agn.agg_tids_count > 0) && |
1460 | (expected_ack_cnt_delta > 0) && | |
1461 | (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta) | |
1462 | < ACK_CNT_RATIO) && | |
1463 | (ba_timeout_delta > BA_TIMEOUT_CNT)) { | |
1464 | IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d," | |
1465 | " expected_ack_cnt = %d\n", | |
1466 | actual_ack_cnt_delta, expected_ack_cnt_delta); | |
1467 | ||
1468 | #ifdef CONFIG_IWLWIFI_DEBUG | |
1469 | IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n", | |
a2064b7a | 1470 | priv->_agn.delta_statistics.tx.rx_detected_cnt); |
872c8ddc WYG |
1471 | IWL_DEBUG_RADIO(priv, |
1472 | "ack_or_ba_timeout_collision delta = %d\n", | |
a2064b7a | 1473 | priv->_agn.delta_statistics.tx. |
872c8ddc WYG |
1474 | ack_or_ba_timeout_collision); |
1475 | #endif | |
1476 | IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n", | |
1477 | ba_timeout_delta); | |
1478 | if (!actual_ack_cnt_delta && | |
1479 | (ba_timeout_delta >= BA_TIMEOUT_MAX)) | |
1480 | rc = false; | |
1481 | } | |
1482 | return rc; | |
1483 | } | |
1484 | ||
a83b9141 | 1485 | |
b481de9c ZY |
1486 | /****************************************************************************** |
1487 | * | |
1488 | * uCode download functions | |
1489 | * | |
1490 | ******************************************************************************/ | |
1491 | ||
5b9f8cd3 | 1492 | static void iwl_dealloc_ucode_pci(struct iwl_priv *priv) |
b481de9c | 1493 | { |
98c92211 TW |
1494 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code); |
1495 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data); | |
1496 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup); | |
1497 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init); | |
1498 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data); | |
1499 | iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot); | |
b481de9c ZY |
1500 | } |
1501 | ||
5b9f8cd3 | 1502 | static void iwl_nic_start(struct iwl_priv *priv) |
edcdf8b2 RR |
1503 | { |
1504 | /* Remove all resets to allow NIC to operate */ | |
1505 | iwl_write32(priv, CSR_RESET, 0); | |
1506 | } | |
1507 | ||
dd7a2509 JB |
1508 | struct iwlagn_ucode_capabilities { |
1509 | u32 max_probe_length; | |
1510 | }; | |
edcdf8b2 | 1511 | |
b08dfd04 | 1512 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context); |
dd7a2509 JB |
1513 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
1514 | struct iwlagn_ucode_capabilities *capa); | |
b08dfd04 JB |
1515 | |
1516 | static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first) | |
1517 | { | |
1518 | const char *name_pre = priv->cfg->fw_name_pre; | |
1519 | ||
1520 | if (first) | |
1521 | priv->fw_index = priv->cfg->ucode_api_max; | |
1522 | else | |
1523 | priv->fw_index--; | |
1524 | ||
1525 | if (priv->fw_index < priv->cfg->ucode_api_min) { | |
1526 | IWL_ERR(priv, "no suitable firmware found!\n"); | |
1527 | return -ENOENT; | |
1528 | } | |
1529 | ||
1530 | sprintf(priv->firmware_name, "%s%d%s", | |
1531 | name_pre, priv->fw_index, ".ucode"); | |
1532 | ||
1533 | IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n", | |
1534 | priv->firmware_name); | |
1535 | ||
1536 | return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name, | |
1537 | &priv->pci_dev->dev, GFP_KERNEL, priv, | |
1538 | iwl_ucode_callback); | |
1539 | } | |
1540 | ||
0e9a44dc JB |
1541 | struct iwlagn_firmware_pieces { |
1542 | const void *inst, *data, *init, *init_data, *boot; | |
1543 | size_t inst_size, data_size, init_size, init_data_size, boot_size; | |
1544 | ||
1545 | u32 build; | |
b2e640d4 JB |
1546 | |
1547 | u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr; | |
1548 | u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr; | |
0e9a44dc JB |
1549 | }; |
1550 | ||
1551 | static int iwlagn_load_legacy_firmware(struct iwl_priv *priv, | |
1552 | const struct firmware *ucode_raw, | |
1553 | struct iwlagn_firmware_pieces *pieces) | |
1554 | { | |
1555 | struct iwl_ucode_header *ucode = (void *)ucode_raw->data; | |
1556 | u32 api_ver, hdr_size; | |
1557 | const u8 *src; | |
1558 | ||
1559 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1560 | api_ver = IWL_UCODE_API(priv->ucode_ver); | |
1561 | ||
1562 | switch (api_ver) { | |
1563 | default: | |
1564 | /* | |
1565 | * 4965 doesn't revision the firmware file format | |
1566 | * along with the API version, it always uses v1 | |
1567 | * file format. | |
1568 | */ | |
1569 | if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) != | |
1570 | CSR_HW_REV_TYPE_4965) { | |
1571 | hdr_size = 28; | |
1572 | if (ucode_raw->size < hdr_size) { | |
1573 | IWL_ERR(priv, "File size too small!\n"); | |
1574 | return -EINVAL; | |
1575 | } | |
1576 | pieces->build = le32_to_cpu(ucode->u.v2.build); | |
1577 | pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size); | |
1578 | pieces->data_size = le32_to_cpu(ucode->u.v2.data_size); | |
1579 | pieces->init_size = le32_to_cpu(ucode->u.v2.init_size); | |
1580 | pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size); | |
1581 | pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size); | |
1582 | src = ucode->u.v2.data; | |
1583 | break; | |
1584 | } | |
1585 | /* fall through for 4965 */ | |
1586 | case 0: | |
1587 | case 1: | |
1588 | case 2: | |
1589 | hdr_size = 24; | |
1590 | if (ucode_raw->size < hdr_size) { | |
1591 | IWL_ERR(priv, "File size too small!\n"); | |
1592 | return -EINVAL; | |
1593 | } | |
1594 | pieces->build = 0; | |
1595 | pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size); | |
1596 | pieces->data_size = le32_to_cpu(ucode->u.v1.data_size); | |
1597 | pieces->init_size = le32_to_cpu(ucode->u.v1.init_size); | |
1598 | pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size); | |
1599 | pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size); | |
1600 | src = ucode->u.v1.data; | |
1601 | break; | |
1602 | } | |
1603 | ||
1604 | /* Verify size of file vs. image size info in file's header */ | |
1605 | if (ucode_raw->size != hdr_size + pieces->inst_size + | |
1606 | pieces->data_size + pieces->init_size + | |
1607 | pieces->init_data_size + pieces->boot_size) { | |
1608 | ||
1609 | IWL_ERR(priv, | |
1610 | "uCode file size %d does not match expected size\n", | |
1611 | (int)ucode_raw->size); | |
1612 | return -EINVAL; | |
1613 | } | |
1614 | ||
1615 | pieces->inst = src; | |
1616 | src += pieces->inst_size; | |
1617 | pieces->data = src; | |
1618 | src += pieces->data_size; | |
1619 | pieces->init = src; | |
1620 | src += pieces->init_size; | |
1621 | pieces->init_data = src; | |
1622 | src += pieces->init_data_size; | |
1623 | pieces->boot = src; | |
1624 | src += pieces->boot_size; | |
1625 | ||
1626 | return 0; | |
1627 | } | |
1628 | ||
dd7a2509 JB |
1629 | static int iwlagn_wanted_ucode_alternative = 1; |
1630 | ||
1631 | static int iwlagn_load_firmware(struct iwl_priv *priv, | |
1632 | const struct firmware *ucode_raw, | |
1633 | struct iwlagn_firmware_pieces *pieces, | |
1634 | struct iwlagn_ucode_capabilities *capa) | |
1635 | { | |
1636 | struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data; | |
1637 | struct iwl_ucode_tlv *tlv; | |
1638 | size_t len = ucode_raw->size; | |
1639 | const u8 *data; | |
1640 | int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp; | |
1641 | u64 alternatives; | |
1642 | ||
1643 | if (len < sizeof(*ucode)) | |
1644 | return -EINVAL; | |
1645 | ||
1646 | if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) | |
1647 | return -EINVAL; | |
1648 | ||
1649 | /* | |
1650 | * Check which alternatives are present, and "downgrade" | |
1651 | * when the chosen alternative is not present, warning | |
1652 | * the user when that happens. Some files may not have | |
1653 | * any alternatives, so don't warn in that case. | |
1654 | */ | |
1655 | alternatives = le64_to_cpu(ucode->alternatives); | |
1656 | tmp = wanted_alternative; | |
1657 | if (wanted_alternative > 63) | |
1658 | wanted_alternative = 63; | |
1659 | while (wanted_alternative && !(alternatives & BIT(wanted_alternative))) | |
1660 | wanted_alternative--; | |
1661 | if (wanted_alternative && wanted_alternative != tmp) | |
1662 | IWL_WARN(priv, | |
1663 | "uCode alternative %d not available, choosing %d\n", | |
1664 | tmp, wanted_alternative); | |
1665 | ||
1666 | priv->ucode_ver = le32_to_cpu(ucode->ver); | |
1667 | pieces->build = le32_to_cpu(ucode->build); | |
1668 | data = ucode->data; | |
1669 | ||
1670 | len -= sizeof(*ucode); | |
1671 | ||
1672 | while (len >= sizeof(*tlv)) { | |
1673 | u32 tlv_len; | |
1674 | enum iwl_ucode_tlv_type tlv_type; | |
1675 | u16 tlv_alt; | |
1676 | const u8 *tlv_data; | |
1677 | ||
1678 | len -= sizeof(*tlv); | |
1679 | tlv = (void *)data; | |
1680 | ||
1681 | tlv_len = le32_to_cpu(tlv->length); | |
1682 | tlv_type = le16_to_cpu(tlv->type); | |
1683 | tlv_alt = le16_to_cpu(tlv->alternative); | |
1684 | tlv_data = tlv->data; | |
1685 | ||
1686 | if (len < tlv_len) | |
1687 | return -EINVAL; | |
1688 | len -= ALIGN(tlv_len, 4); | |
1689 | data += sizeof(*tlv) + ALIGN(tlv_len, 4); | |
1690 | ||
1691 | /* | |
1692 | * Alternative 0 is always valid. | |
1693 | * | |
1694 | * Skip alternative TLVs that are not selected. | |
1695 | */ | |
1696 | if (tlv_alt != 0 && tlv_alt != wanted_alternative) | |
1697 | continue; | |
1698 | ||
1699 | switch (tlv_type) { | |
1700 | case IWL_UCODE_TLV_INST: | |
1701 | pieces->inst = tlv_data; | |
1702 | pieces->inst_size = tlv_len; | |
1703 | break; | |
1704 | case IWL_UCODE_TLV_DATA: | |
1705 | pieces->data = tlv_data; | |
1706 | pieces->data_size = tlv_len; | |
1707 | break; | |
1708 | case IWL_UCODE_TLV_INIT: | |
1709 | pieces->init = tlv_data; | |
1710 | pieces->init_size = tlv_len; | |
1711 | break; | |
1712 | case IWL_UCODE_TLV_INIT_DATA: | |
1713 | pieces->init_data = tlv_data; | |
1714 | pieces->init_data_size = tlv_len; | |
1715 | break; | |
1716 | case IWL_UCODE_TLV_BOOT: | |
1717 | pieces->boot = tlv_data; | |
1718 | pieces->boot_size = tlv_len; | |
1719 | break; | |
1720 | case IWL_UCODE_TLV_PROBE_MAX_LEN: | |
1721 | if (tlv_len != 4) | |
1722 | return -EINVAL; | |
1723 | capa->max_probe_length = | |
1724 | le32_to_cpup((__le32 *)tlv_data); | |
1725 | break; | |
b2e640d4 JB |
1726 | case IWL_UCODE_TLV_INIT_EVTLOG_PTR: |
1727 | if (tlv_len != 4) | |
1728 | return -EINVAL; | |
1729 | pieces->init_evtlog_ptr = | |
1730 | le32_to_cpup((__le32 *)tlv_data); | |
1731 | break; | |
1732 | case IWL_UCODE_TLV_INIT_EVTLOG_SIZE: | |
1733 | if (tlv_len != 4) | |
1734 | return -EINVAL; | |
1735 | pieces->init_evtlog_size = | |
1736 | le32_to_cpup((__le32 *)tlv_data); | |
1737 | break; | |
1738 | case IWL_UCODE_TLV_INIT_ERRLOG_PTR: | |
1739 | if (tlv_len != 4) | |
1740 | return -EINVAL; | |
1741 | pieces->init_errlog_ptr = | |
1742 | le32_to_cpup((__le32 *)tlv_data); | |
1743 | break; | |
1744 | case IWL_UCODE_TLV_RUNT_EVTLOG_PTR: | |
1745 | if (tlv_len != 4) | |
1746 | return -EINVAL; | |
1747 | pieces->inst_evtlog_ptr = | |
1748 | le32_to_cpup((__le32 *)tlv_data); | |
1749 | break; | |
1750 | case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE: | |
1751 | if (tlv_len != 4) | |
1752 | return -EINVAL; | |
1753 | pieces->inst_evtlog_size = | |
1754 | le32_to_cpup((__le32 *)tlv_data); | |
1755 | break; | |
1756 | case IWL_UCODE_TLV_RUNT_ERRLOG_PTR: | |
1757 | if (tlv_len != 4) | |
1758 | return -EINVAL; | |
1759 | pieces->inst_errlog_ptr = | |
1760 | le32_to_cpup((__le32 *)tlv_data); | |
1761 | break; | |
dd7a2509 JB |
1762 | default: |
1763 | break; | |
1764 | } | |
1765 | } | |
1766 | ||
1767 | if (len) | |
1768 | return -EINVAL; | |
1769 | ||
1770 | return 0; | |
1771 | } | |
1772 | ||
b481de9c | 1773 | /** |
b08dfd04 | 1774 | * iwl_ucode_callback - callback when firmware was loaded |
b481de9c | 1775 | * |
b08dfd04 JB |
1776 | * If loaded successfully, copies the firmware into buffers |
1777 | * for the card to fetch (via DMA). | |
b481de9c | 1778 | */ |
b08dfd04 | 1779 | static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context) |
b481de9c | 1780 | { |
b08dfd04 | 1781 | struct iwl_priv *priv = context; |
cc0f555d | 1782 | struct iwl_ucode_header *ucode; |
0e9a44dc JB |
1783 | int err; |
1784 | struct iwlagn_firmware_pieces pieces; | |
a0987a8d RC |
1785 | const unsigned int api_max = priv->cfg->ucode_api_max; |
1786 | const unsigned int api_min = priv->cfg->ucode_api_min; | |
0e9a44dc | 1787 | u32 api_ver; |
3e4de761 | 1788 | char buildstr[25]; |
0e9a44dc | 1789 | u32 build; |
dd7a2509 JB |
1790 | struct iwlagn_ucode_capabilities ucode_capa = { |
1791 | .max_probe_length = 200, | |
1792 | }; | |
0e9a44dc JB |
1793 | |
1794 | memset(&pieces, 0, sizeof(pieces)); | |
b481de9c | 1795 | |
b08dfd04 JB |
1796 | if (!ucode_raw) { |
1797 | IWL_ERR(priv, "request for firmware file '%s' failed.\n", | |
1798 | priv->firmware_name); | |
1799 | goto try_again; | |
b481de9c ZY |
1800 | } |
1801 | ||
b08dfd04 JB |
1802 | IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", |
1803 | priv->firmware_name, ucode_raw->size); | |
b481de9c | 1804 | |
22adba2a JB |
1805 | /* Make sure that we got at least the API version number */ |
1806 | if (ucode_raw->size < 4) { | |
15b1687c | 1807 | IWL_ERR(priv, "File size way too small!\n"); |
b08dfd04 | 1808 | goto try_again; |
b481de9c ZY |
1809 | } |
1810 | ||
1811 | /* Data from ucode file: header followed by uCode images */ | |
cc0f555d | 1812 | ucode = (struct iwl_ucode_header *)ucode_raw->data; |
b481de9c | 1813 | |
0e9a44dc JB |
1814 | if (ucode->ver) |
1815 | err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces); | |
1816 | else | |
dd7a2509 JB |
1817 | err = iwlagn_load_firmware(priv, ucode_raw, &pieces, |
1818 | &ucode_capa); | |
22adba2a | 1819 | |
0e9a44dc JB |
1820 | if (err) |
1821 | goto try_again; | |
b481de9c | 1822 | |
0e9a44dc JB |
1823 | api_ver = IWL_UCODE_API(priv->ucode_ver); |
1824 | build = pieces.build; | |
a0987a8d | 1825 | |
0e9a44dc JB |
1826 | /* |
1827 | * api_ver should match the api version forming part of the | |
1828 | * firmware filename ... but we don't check for that and only rely | |
1829 | * on the API version read from firmware header from here on forward | |
1830 | */ | |
a0987a8d | 1831 | if (api_ver < api_min || api_ver > api_max) { |
15b1687c | 1832 | IWL_ERR(priv, "Driver unable to support your firmware API. " |
a0987a8d RC |
1833 | "Driver supports v%u, firmware is v%u.\n", |
1834 | api_max, api_ver); | |
b08dfd04 | 1835 | goto try_again; |
a0987a8d | 1836 | } |
b08dfd04 | 1837 | |
a0987a8d | 1838 | if (api_ver != api_max) |
978785a3 | 1839 | IWL_ERR(priv, "Firmware has old API version. Expected v%u, " |
a0987a8d RC |
1840 | "got v%u. New firmware can be obtained " |
1841 | "from http://www.intellinuxwireless.org.\n", | |
1842 | api_max, api_ver); | |
1843 | ||
3e4de761 JB |
1844 | if (build) |
1845 | sprintf(buildstr, " build %u", build); | |
1846 | else | |
1847 | buildstr[0] = '\0'; | |
1848 | ||
1849 | IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n", | |
1850 | IWL_UCODE_MAJOR(priv->ucode_ver), | |
1851 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1852 | IWL_UCODE_API(priv->ucode_ver), | |
1853 | IWL_UCODE_SERIAL(priv->ucode_ver), | |
1854 | buildstr); | |
a0987a8d | 1855 | |
5ebeb5a6 RC |
1856 | snprintf(priv->hw->wiphy->fw_version, |
1857 | sizeof(priv->hw->wiphy->fw_version), | |
3e4de761 | 1858 | "%u.%u.%u.%u%s", |
5ebeb5a6 RC |
1859 | IWL_UCODE_MAJOR(priv->ucode_ver), |
1860 | IWL_UCODE_MINOR(priv->ucode_ver), | |
1861 | IWL_UCODE_API(priv->ucode_ver), | |
3e4de761 JB |
1862 | IWL_UCODE_SERIAL(priv->ucode_ver), |
1863 | buildstr); | |
cc0f555d | 1864 | |
b08dfd04 JB |
1865 | /* |
1866 | * For any of the failures below (before allocating pci memory) | |
1867 | * we will try to load a version with a smaller API -- maybe the | |
1868 | * user just got a corrupted version of the latest API. | |
1869 | */ | |
1870 | ||
0e9a44dc JB |
1871 | IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n", |
1872 | priv->ucode_ver); | |
1873 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n", | |
1874 | pieces.inst_size); | |
1875 | IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n", | |
1876 | pieces.data_size); | |
1877 | IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n", | |
1878 | pieces.init_size); | |
1879 | IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n", | |
1880 | pieces.init_data_size); | |
1881 | IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n", | |
1882 | pieces.boot_size); | |
b481de9c ZY |
1883 | |
1884 | /* Verify that uCode images will fit in card's SRAM */ | |
0e9a44dc JB |
1885 | if (pieces.inst_size > priv->hw_params.max_inst_size) { |
1886 | IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n", | |
1887 | pieces.inst_size); | |
b08dfd04 | 1888 | goto try_again; |
b481de9c ZY |
1889 | } |
1890 | ||
0e9a44dc JB |
1891 | if (pieces.data_size > priv->hw_params.max_data_size) { |
1892 | IWL_ERR(priv, "uCode data len %Zd too large to fit in\n", | |
1893 | pieces.data_size); | |
b08dfd04 | 1894 | goto try_again; |
b481de9c | 1895 | } |
0e9a44dc JB |
1896 | |
1897 | if (pieces.init_size > priv->hw_params.max_inst_size) { | |
1898 | IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n", | |
1899 | pieces.init_size); | |
b08dfd04 | 1900 | goto try_again; |
b481de9c | 1901 | } |
0e9a44dc JB |
1902 | |
1903 | if (pieces.init_data_size > priv->hw_params.max_data_size) { | |
1904 | IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n", | |
1905 | pieces.init_data_size); | |
b08dfd04 | 1906 | goto try_again; |
b481de9c | 1907 | } |
0e9a44dc JB |
1908 | |
1909 | if (pieces.boot_size > priv->hw_params.max_bsm_size) { | |
1910 | IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n", | |
1911 | pieces.boot_size); | |
b08dfd04 | 1912 | goto try_again; |
b481de9c ZY |
1913 | } |
1914 | ||
1915 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
1916 | ||
1917 | /* Runtime instructions and 2 copies of data: | |
1918 | * 1) unmodified from disk | |
1919 | * 2) backup cache for save/restore during power-downs */ | |
0e9a44dc | 1920 | priv->ucode_code.len = pieces.inst_size; |
98c92211 | 1921 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code); |
b481de9c | 1922 | |
0e9a44dc | 1923 | priv->ucode_data.len = pieces.data_size; |
98c92211 | 1924 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data); |
b481de9c | 1925 | |
0e9a44dc | 1926 | priv->ucode_data_backup.len = pieces.data_size; |
98c92211 | 1927 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup); |
b481de9c | 1928 | |
1f304e4e ZY |
1929 | if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr || |
1930 | !priv->ucode_data_backup.v_addr) | |
1931 | goto err_pci_alloc; | |
1932 | ||
b481de9c | 1933 | /* Initialization instructions and data */ |
0e9a44dc JB |
1934 | if (pieces.init_size && pieces.init_data_size) { |
1935 | priv->ucode_init.len = pieces.init_size; | |
98c92211 | 1936 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init); |
90e759d1 | 1937 | |
0e9a44dc | 1938 | priv->ucode_init_data.len = pieces.init_data_size; |
98c92211 | 1939 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data); |
90e759d1 TW |
1940 | |
1941 | if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr) | |
1942 | goto err_pci_alloc; | |
1943 | } | |
b481de9c ZY |
1944 | |
1945 | /* Bootstrap (instructions only, no data) */ | |
0e9a44dc JB |
1946 | if (pieces.boot_size) { |
1947 | priv->ucode_boot.len = pieces.boot_size; | |
98c92211 | 1948 | iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot); |
b481de9c | 1949 | |
90e759d1 TW |
1950 | if (!priv->ucode_boot.v_addr) |
1951 | goto err_pci_alloc; | |
1952 | } | |
b481de9c | 1953 | |
b2e640d4 JB |
1954 | /* Now that we can no longer fail, copy information */ |
1955 | ||
1956 | /* | |
1957 | * The (size - 16) / 12 formula is based on the information recorded | |
1958 | * for each event, which is of mode 1 (including timestamp) for all | |
1959 | * new microcodes that include this information. | |
1960 | */ | |
1961 | priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr; | |
1962 | if (pieces.init_evtlog_size) | |
1963 | priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12; | |
1964 | else | |
1965 | priv->_agn.init_evtlog_size = priv->cfg->max_event_log_size; | |
1966 | priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr; | |
1967 | priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr; | |
1968 | if (pieces.inst_evtlog_size) | |
1969 | priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12; | |
1970 | else | |
1971 | priv->_agn.inst_evtlog_size = priv->cfg->max_event_log_size; | |
1972 | priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr; | |
1973 | ||
b481de9c ZY |
1974 | /* Copy images into buffers for card's bus-master reads ... */ |
1975 | ||
1976 | /* Runtime instructions (first block of data in file) */ | |
0e9a44dc JB |
1977 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", |
1978 | pieces.inst_size); | |
1979 | memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size); | |
cc0f555d | 1980 | |
e1623446 | 1981 | IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
b481de9c ZY |
1982 | priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr); |
1983 | ||
0e9a44dc JB |
1984 | /* |
1985 | * Runtime data | |
1986 | * NOTE: Copy into backup buffer will be done in iwl_up() | |
1987 | */ | |
1988 | IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", | |
1989 | pieces.data_size); | |
1990 | memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size); | |
1991 | memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size); | |
1992 | ||
1993 | /* Initialization instructions */ | |
1994 | if (pieces.init_size) { | |
e1623446 | 1995 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n", |
0e9a44dc JB |
1996 | pieces.init_size); |
1997 | memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size); | |
b481de9c ZY |
1998 | } |
1999 | ||
0e9a44dc JB |
2000 | /* Initialization data */ |
2001 | if (pieces.init_data_size) { | |
e1623446 | 2002 | IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n", |
0e9a44dc JB |
2003 | pieces.init_data_size); |
2004 | memcpy(priv->ucode_init_data.v_addr, pieces.init_data, | |
2005 | pieces.init_data_size); | |
b481de9c ZY |
2006 | } |
2007 | ||
0e9a44dc JB |
2008 | /* Bootstrap instructions */ |
2009 | IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", | |
2010 | pieces.boot_size); | |
2011 | memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size); | |
b481de9c | 2012 | |
b08dfd04 JB |
2013 | /************************************************** |
2014 | * This is still part of probe() in a sense... | |
2015 | * | |
2016 | * 9. Setup and register with mac80211 and debugfs | |
2017 | **************************************************/ | |
dd7a2509 | 2018 | err = iwl_mac_setup_register(priv, &ucode_capa); |
b08dfd04 JB |
2019 | if (err) |
2020 | goto out_unbind; | |
2021 | ||
2022 | err = iwl_dbgfs_register(priv, DRV_NAME); | |
2023 | if (err) | |
2024 | IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err); | |
2025 | ||
b481de9c ZY |
2026 | /* We have our copies now, allow OS release its copies */ |
2027 | release_firmware(ucode_raw); | |
a15707d8 | 2028 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 JB |
2029 | return; |
2030 | ||
2031 | try_again: | |
2032 | /* try next, if any */ | |
2033 | if (iwl_request_firmware(priv, false)) | |
2034 | goto out_unbind; | |
2035 | release_firmware(ucode_raw); | |
2036 | return; | |
b481de9c ZY |
2037 | |
2038 | err_pci_alloc: | |
15b1687c | 2039 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
5b9f8cd3 | 2040 | iwl_dealloc_ucode_pci(priv); |
b08dfd04 | 2041 | out_unbind: |
a15707d8 | 2042 | complete(&priv->_agn.firmware_loading_complete); |
b08dfd04 | 2043 | device_release_driver(&priv->pci_dev->dev); |
b481de9c | 2044 | release_firmware(ucode_raw); |
b481de9c ZY |
2045 | } |
2046 | ||
b7a79404 RC |
2047 | static const char *desc_lookup_text[] = { |
2048 | "OK", | |
2049 | "FAIL", | |
2050 | "BAD_PARAM", | |
2051 | "BAD_CHECKSUM", | |
2052 | "NMI_INTERRUPT_WDG", | |
2053 | "SYSASSERT", | |
2054 | "FATAL_ERROR", | |
2055 | "BAD_COMMAND", | |
2056 | "HW_ERROR_TUNE_LOCK", | |
2057 | "HW_ERROR_TEMPERATURE", | |
2058 | "ILLEGAL_CHAN_FREQ", | |
2059 | "VCC_NOT_STABLE", | |
2060 | "FH_ERROR", | |
2061 | "NMI_INTERRUPT_HOST", | |
2062 | "NMI_INTERRUPT_ACTION_PT", | |
2063 | "NMI_INTERRUPT_UNKNOWN", | |
2064 | "UCODE_VERSION_MISMATCH", | |
2065 | "HW_ERROR_ABS_LOCK", | |
2066 | "HW_ERROR_CAL_LOCK_FAIL", | |
2067 | "NMI_INTERRUPT_INST_ACTION_PT", | |
2068 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
2069 | "NMI_TRM_HW_ER", | |
2070 | "NMI_INTERRUPT_TRM", | |
2071 | "NMI_INTERRUPT_BREAK_POINT" | |
2072 | "DEBUG_0", | |
2073 | "DEBUG_1", | |
2074 | "DEBUG_2", | |
2075 | "DEBUG_3", | |
a7fce6ee | 2076 | "ADVANCED SYSASSERT" |
b7a79404 RC |
2077 | }; |
2078 | ||
2079 | static const char *desc_lookup(int i) | |
2080 | { | |
2081 | int max = ARRAY_SIZE(desc_lookup_text) - 1; | |
2082 | ||
2083 | if (i < 0 || i > max) | |
2084 | i = max; | |
2085 | ||
2086 | return desc_lookup_text[i]; | |
2087 | } | |
2088 | ||
2089 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
2090 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
2091 | ||
2092 | void iwl_dump_nic_error_log(struct iwl_priv *priv) | |
2093 | { | |
2094 | u32 data2, line; | |
2095 | u32 desc, time, count, base, data1; | |
2096 | u32 blink1, blink2, ilink1, ilink2; | |
461ef382 | 2097 | u32 pc, hcmd; |
b7a79404 | 2098 | |
b2e640d4 | 2099 | if (priv->ucode_type == UCODE_INIT) { |
b7a79404 | 2100 | base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr); |
b2e640d4 JB |
2101 | if (!base) |
2102 | base = priv->_agn.init_errlog_ptr; | |
2103 | } else { | |
b7a79404 | 2104 | base = le32_to_cpu(priv->card_alive.error_event_table_ptr); |
b2e640d4 JB |
2105 | if (!base) |
2106 | base = priv->_agn.inst_errlog_ptr; | |
2107 | } | |
b7a79404 RC |
2108 | |
2109 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2110 | IWL_ERR(priv, |
2111 | "Not valid error log pointer 0x%08X for %s uCode\n", | |
2112 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
b7a79404 RC |
2113 | return; |
2114 | } | |
2115 | ||
2116 | count = iwl_read_targ_mem(priv, base); | |
2117 | ||
2118 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
2119 | IWL_ERR(priv, "Start IWL Error Log Dump:\n"); | |
2120 | IWL_ERR(priv, "Status: 0x%08lX, count: %d\n", | |
2121 | priv->status, count); | |
2122 | } | |
2123 | ||
2124 | desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32)); | |
461ef382 | 2125 | pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32)); |
b7a79404 RC |
2126 | blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32)); |
2127 | blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32)); | |
2128 | ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32)); | |
2129 | ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32)); | |
2130 | data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32)); | |
2131 | data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32)); | |
2132 | line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32)); | |
2133 | time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32)); | |
461ef382 | 2134 | hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32)); |
b7a79404 | 2135 | |
be1a71a1 JB |
2136 | trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line, |
2137 | blink1, blink2, ilink1, ilink2); | |
2138 | ||
b7a79404 RC |
2139 | IWL_ERR(priv, "Desc Time " |
2140 | "data1 data2 line\n"); | |
2141 | IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n", | |
2142 | desc_lookup(desc), desc, time, data1, data2, line); | |
461ef382 WYG |
2143 | IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n"); |
2144 | IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", | |
2145 | pc, blink1, blink2, ilink1, ilink2, hcmd); | |
b7a79404 RC |
2146 | } |
2147 | ||
2148 | #define EVENT_START_OFFSET (4 * sizeof(u32)) | |
2149 | ||
2150 | /** | |
2151 | * iwl_print_event_log - Dump error event log to syslog | |
2152 | * | |
2153 | */ | |
b03d7d0f WYG |
2154 | static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx, |
2155 | u32 num_events, u32 mode, | |
2156 | int pos, char **buf, size_t bufsz) | |
b7a79404 RC |
2157 | { |
2158 | u32 i; | |
2159 | u32 base; /* SRAM byte address of event log header */ | |
2160 | u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */ | |
2161 | u32 ptr; /* SRAM byte address of log data */ | |
2162 | u32 ev, time, data; /* event log data */ | |
e5854471 | 2163 | unsigned long reg_flags; |
b7a79404 RC |
2164 | |
2165 | if (num_events == 0) | |
b03d7d0f | 2166 | return pos; |
b2e640d4 JB |
2167 | |
2168 | if (priv->ucode_type == UCODE_INIT) { | |
b7a79404 | 2169 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
b2e640d4 JB |
2170 | if (!base) |
2171 | base = priv->_agn.init_evtlog_ptr; | |
2172 | } else { | |
b7a79404 | 2173 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); |
b2e640d4 JB |
2174 | if (!base) |
2175 | base = priv->_agn.inst_evtlog_ptr; | |
2176 | } | |
b7a79404 RC |
2177 | |
2178 | if (mode == 0) | |
2179 | event_size = 2 * sizeof(u32); | |
2180 | else | |
2181 | event_size = 3 * sizeof(u32); | |
2182 | ||
2183 | ptr = base + EVENT_START_OFFSET + (start_idx * event_size); | |
2184 | ||
e5854471 BC |
2185 | /* Make sure device is powered up for SRAM reads */ |
2186 | spin_lock_irqsave(&priv->reg_lock, reg_flags); | |
2187 | iwl_grab_nic_access(priv); | |
2188 | ||
2189 | /* Set starting address; reads will auto-increment */ | |
2190 | _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr); | |
2191 | rmb(); | |
2192 | ||
b7a79404 RC |
2193 | /* "time" is actually "data" for mode 0 (no timestamp). |
2194 | * place event id # at far right for easier visual parsing. */ | |
2195 | for (i = 0; i < num_events; i++) { | |
e5854471 BC |
2196 | ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
2197 | time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); | |
b7a79404 RC |
2198 | if (mode == 0) { |
2199 | /* data, ev */ | |
b03d7d0f WYG |
2200 | if (bufsz) { |
2201 | pos += scnprintf(*buf + pos, bufsz - pos, | |
2202 | "EVT_LOG:0x%08x:%04u\n", | |
2203 | time, ev); | |
2204 | } else { | |
2205 | trace_iwlwifi_dev_ucode_event(priv, 0, | |
2206 | time, ev); | |
2207 | IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", | |
2208 | time, ev); | |
2209 | } | |
b7a79404 | 2210 | } else { |
e5854471 | 2211 | data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT); |
b03d7d0f WYG |
2212 | if (bufsz) { |
2213 | pos += scnprintf(*buf + pos, bufsz - pos, | |
2214 | "EVT_LOGT:%010u:0x%08x:%04u\n", | |
2215 | time, data, ev); | |
2216 | } else { | |
2217 | IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n", | |
b7a79404 | 2218 | time, data, ev); |
b03d7d0f WYG |
2219 | trace_iwlwifi_dev_ucode_event(priv, time, |
2220 | data, ev); | |
2221 | } | |
b7a79404 RC |
2222 | } |
2223 | } | |
e5854471 BC |
2224 | |
2225 | /* Allow device to power down */ | |
2226 | iwl_release_nic_access(priv); | |
2227 | spin_unlock_irqrestore(&priv->reg_lock, reg_flags); | |
b03d7d0f | 2228 | return pos; |
b7a79404 RC |
2229 | } |
2230 | ||
c341ddb2 WYG |
2231 | /** |
2232 | * iwl_print_last_event_logs - Dump the newest # of event log to syslog | |
2233 | */ | |
b03d7d0f WYG |
2234 | static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity, |
2235 | u32 num_wraps, u32 next_entry, | |
2236 | u32 size, u32 mode, | |
2237 | int pos, char **buf, size_t bufsz) | |
c341ddb2 WYG |
2238 | { |
2239 | /* | |
2240 | * display the newest DEFAULT_LOG_ENTRIES entries | |
2241 | * i.e the entries just before the next ont that uCode would fill. | |
2242 | */ | |
2243 | if (num_wraps) { | |
2244 | if (next_entry < size) { | |
b03d7d0f WYG |
2245 | pos = iwl_print_event_log(priv, |
2246 | capacity - (size - next_entry), | |
2247 | size - next_entry, mode, | |
2248 | pos, buf, bufsz); | |
2249 | pos = iwl_print_event_log(priv, 0, | |
2250 | next_entry, mode, | |
2251 | pos, buf, bufsz); | |
c341ddb2 | 2252 | } else |
b03d7d0f WYG |
2253 | pos = iwl_print_event_log(priv, next_entry - size, |
2254 | size, mode, pos, buf, bufsz); | |
c341ddb2 | 2255 | } else { |
b03d7d0f WYG |
2256 | if (next_entry < size) { |
2257 | pos = iwl_print_event_log(priv, 0, next_entry, | |
2258 | mode, pos, buf, bufsz); | |
2259 | } else { | |
2260 | pos = iwl_print_event_log(priv, next_entry - size, | |
2261 | size, mode, pos, buf, bufsz); | |
2262 | } | |
c341ddb2 | 2263 | } |
b03d7d0f | 2264 | return pos; |
c341ddb2 WYG |
2265 | } |
2266 | ||
c341ddb2 WYG |
2267 | #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20) |
2268 | ||
b03d7d0f WYG |
2269 | int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, |
2270 | char **buf, bool display) | |
b7a79404 RC |
2271 | { |
2272 | u32 base; /* SRAM byte address of event log header */ | |
2273 | u32 capacity; /* event log capacity in # entries */ | |
2274 | u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */ | |
2275 | u32 num_wraps; /* # times uCode wrapped to top of log */ | |
2276 | u32 next_entry; /* index of next entry to be written by uCode */ | |
2277 | u32 size; /* # entries that we'll print */ | |
b2e640d4 | 2278 | u32 logsize; |
b03d7d0f WYG |
2279 | int pos = 0; |
2280 | size_t bufsz = 0; | |
b7a79404 | 2281 | |
b2e640d4 | 2282 | if (priv->ucode_type == UCODE_INIT) { |
b7a79404 | 2283 | base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr); |
b2e640d4 JB |
2284 | logsize = priv->_agn.init_evtlog_size; |
2285 | if (!base) | |
2286 | base = priv->_agn.init_evtlog_ptr; | |
2287 | } else { | |
b7a79404 | 2288 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); |
b2e640d4 JB |
2289 | logsize = priv->_agn.inst_evtlog_size; |
2290 | if (!base) | |
2291 | base = priv->_agn.inst_evtlog_ptr; | |
2292 | } | |
b7a79404 RC |
2293 | |
2294 | if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) { | |
212fb575 WYG |
2295 | IWL_ERR(priv, |
2296 | "Invalid event log pointer 0x%08X for %s uCode\n", | |
2297 | base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
937c397e | 2298 | return -EINVAL; |
b7a79404 RC |
2299 | } |
2300 | ||
2301 | /* event log header */ | |
2302 | capacity = iwl_read_targ_mem(priv, base); | |
2303 | mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32))); | |
2304 | num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32))); | |
2305 | next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32))); | |
2306 | ||
b2e640d4 | 2307 | if (capacity > logsize) { |
84c40692 | 2308 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n", |
b2e640d4 JB |
2309 | capacity, logsize); |
2310 | capacity = logsize; | |
84c40692 BC |
2311 | } |
2312 | ||
b2e640d4 | 2313 | if (next_entry > logsize) { |
84c40692 | 2314 | IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n", |
b2e640d4 JB |
2315 | next_entry, logsize); |
2316 | next_entry = logsize; | |
84c40692 BC |
2317 | } |
2318 | ||
b7a79404 RC |
2319 | size = num_wraps ? capacity : next_entry; |
2320 | ||
2321 | /* bail out if nothing in log */ | |
2322 | if (size == 0) { | |
2323 | IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n"); | |
b03d7d0f | 2324 | return pos; |
b7a79404 RC |
2325 | } |
2326 | ||
c341ddb2 | 2327 | #ifdef CONFIG_IWLWIFI_DEBUG |
521d9bce | 2328 | if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log) |
c341ddb2 WYG |
2329 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) |
2330 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2331 | #else | |
2332 | size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES) | |
2333 | ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size; | |
2334 | #endif | |
2335 | IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n", | |
2336 | size); | |
b7a79404 | 2337 | |
c341ddb2 | 2338 | #ifdef CONFIG_IWLWIFI_DEBUG |
b03d7d0f WYG |
2339 | if (display) { |
2340 | if (full_log) | |
2341 | bufsz = capacity * 48; | |
2342 | else | |
2343 | bufsz = size * 48; | |
2344 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
2345 | if (!*buf) | |
937c397e | 2346 | return -ENOMEM; |
b03d7d0f | 2347 | } |
c341ddb2 WYG |
2348 | if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) { |
2349 | /* | |
2350 | * if uCode has wrapped back to top of log, | |
2351 | * start at the oldest entry, | |
2352 | * i.e the next one that uCode would fill. | |
2353 | */ | |
2354 | if (num_wraps) | |
b03d7d0f WYG |
2355 | pos = iwl_print_event_log(priv, next_entry, |
2356 | capacity - next_entry, mode, | |
2357 | pos, buf, bufsz); | |
c341ddb2 | 2358 | /* (then/else) start at top of log */ |
b03d7d0f WYG |
2359 | pos = iwl_print_event_log(priv, 0, |
2360 | next_entry, mode, pos, buf, bufsz); | |
c341ddb2 | 2361 | } else |
b03d7d0f WYG |
2362 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2363 | next_entry, size, mode, | |
2364 | pos, buf, bufsz); | |
c341ddb2 | 2365 | #else |
b03d7d0f WYG |
2366 | pos = iwl_print_last_event_logs(priv, capacity, num_wraps, |
2367 | next_entry, size, mode, | |
2368 | pos, buf, bufsz); | |
b7a79404 | 2369 | #endif |
b03d7d0f | 2370 | return pos; |
c341ddb2 | 2371 | } |
b7a79404 | 2372 | |
b481de9c | 2373 | /** |
4a4a9e81 | 2374 | * iwl_alive_start - called after REPLY_ALIVE notification received |
b481de9c | 2375 | * from protocol/runtime uCode (initialization uCode's |
4a4a9e81 | 2376 | * Alive gets handled by iwl_init_alive_start()). |
b481de9c | 2377 | */ |
4a4a9e81 | 2378 | static void iwl_alive_start(struct iwl_priv *priv) |
b481de9c | 2379 | { |
57aab75a | 2380 | int ret = 0; |
b481de9c | 2381 | |
e1623446 | 2382 | IWL_DEBUG_INFO(priv, "Runtime Alive received.\n"); |
b481de9c ZY |
2383 | |
2384 | if (priv->card_alive.is_valid != UCODE_VALID_OK) { | |
2385 | /* We had an error bringing up the hardware, so take it | |
2386 | * all the way back down so we can try again */ | |
e1623446 | 2387 | IWL_DEBUG_INFO(priv, "Alive failed.\n"); |
b481de9c ZY |
2388 | goto restart; |
2389 | } | |
2390 | ||
2391 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
2392 | * This is a paranoid check, because we would not have gotten the | |
2393 | * "runtime" alive if code weren't properly loaded. */ | |
b0692f2f | 2394 | if (iwl_verify_ucode(priv)) { |
b481de9c ZY |
2395 | /* Runtime instruction load was bad; |
2396 | * take it all the way back down so we can try again */ | |
e1623446 | 2397 | IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n"); |
b481de9c ZY |
2398 | goto restart; |
2399 | } | |
2400 | ||
57aab75a TW |
2401 | ret = priv->cfg->ops->lib->alive_notify(priv); |
2402 | if (ret) { | |
39aadf8c WT |
2403 | IWL_WARN(priv, |
2404 | "Could not complete ALIVE transition [ntf]: %d\n", ret); | |
b481de9c ZY |
2405 | goto restart; |
2406 | } | |
2407 | ||
5b9f8cd3 | 2408 | /* After the ALIVE response, we can send host commands to the uCode */ |
b481de9c ZY |
2409 | set_bit(STATUS_ALIVE, &priv->status); |
2410 | ||
b74e31a9 WYG |
2411 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
2412 | /* Enable timer to monitor the driver queues */ | |
2413 | mod_timer(&priv->monitor_recover, | |
2414 | jiffies + | |
2415 | msecs_to_jiffies(priv->cfg->monitor_recover_period)); | |
2416 | } | |
2417 | ||
fee1247a | 2418 | if (iwl_is_rfkill(priv)) |
b481de9c ZY |
2419 | return; |
2420 | ||
36d6825b | 2421 | ieee80211_wake_queues(priv->hw); |
b481de9c | 2422 | |
470ab2dd | 2423 | priv->active_rate = IWL_RATES_MASK; |
b481de9c | 2424 | |
2f748dec WYG |
2425 | /* Configure Tx antenna selection based on H/W config */ |
2426 | if (priv->cfg->ops->hcmd->set_tx_ant) | |
2427 | priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant); | |
2428 | ||
3109ece1 | 2429 | if (iwl_is_associated(priv)) { |
c1adf9fb GG |
2430 | struct iwl_rxon_cmd *active_rxon = |
2431 | (struct iwl_rxon_cmd *)&priv->active_rxon; | |
019fb97d MA |
2432 | /* apply any changes in staging */ |
2433 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
b481de9c ZY |
2434 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
2435 | } else { | |
2436 | /* Initialize our rx_config data */ | |
1dda6d28 | 2437 | iwl_connection_init_rx_config(priv, NULL); |
45823531 AK |
2438 | |
2439 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
2440 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2441 | ||
b481de9c ZY |
2442 | memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN); |
2443 | } | |
2444 | ||
9fbab516 | 2445 | /* Configure Bluetooth device coexistence support */ |
65b52bde | 2446 | priv->cfg->ops->hcmd->send_bt_config(priv); |
b481de9c | 2447 | |
4a4a9e81 TW |
2448 | iwl_reset_run_time_calib(priv); |
2449 | ||
b481de9c | 2450 | /* Configure the adapter for unassociated operation */ |
e0158e61 | 2451 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
2452 | |
2453 | /* At this point, the NIC is initialized and operational */ | |
47f4a587 | 2454 | iwl_rf_kill_ct_config(priv); |
5a66926a | 2455 | |
e932a609 | 2456 | iwl_leds_init(priv); |
fe00b5a5 | 2457 | |
e1623446 | 2458 | IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n"); |
a9f46786 | 2459 | set_bit(STATUS_READY, &priv->status); |
5a66926a | 2460 | wake_up_interruptible(&priv->wait_command_queue); |
b481de9c | 2461 | |
e312c24c | 2462 | iwl_power_update_mode(priv, true); |
7e246191 RC |
2463 | IWL_DEBUG_INFO(priv, "Updated power mode\n"); |
2464 | ||
c46fbefa | 2465 | |
b481de9c ZY |
2466 | return; |
2467 | ||
2468 | restart: | |
2469 | queue_work(priv->workqueue, &priv->restart); | |
2470 | } | |
2471 | ||
4e39317d | 2472 | static void iwl_cancel_deferred_work(struct iwl_priv *priv); |
b481de9c | 2473 | |
5b9f8cd3 | 2474 | static void __iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2475 | { |
2476 | unsigned long flags; | |
2477 | int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status); | |
b481de9c | 2478 | |
e1623446 | 2479 | IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n"); |
b481de9c | 2480 | |
b481de9c ZY |
2481 | if (!exit_pending) |
2482 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
2483 | ||
2c810ccd JB |
2484 | iwl_clear_ucode_stations(priv); |
2485 | iwl_dealloc_bcast_station(priv); | |
db125c78 | 2486 | iwl_clear_driver_stations(priv); |
b481de9c ZY |
2487 | |
2488 | /* Unblock any waiting calls */ | |
2489 | wake_up_interruptible_all(&priv->wait_command_queue); | |
2490 | ||
b481de9c ZY |
2491 | /* Wipe out the EXIT_PENDING status bit if we are not actually |
2492 | * exiting the module */ | |
2493 | if (!exit_pending) | |
2494 | clear_bit(STATUS_EXIT_PENDING, &priv->status); | |
2495 | ||
2496 | /* stop and reset the on-board processor */ | |
3395f6e9 | 2497 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
b481de9c ZY |
2498 | |
2499 | /* tell the device to stop sending interrupts */ | |
0359facc | 2500 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 2501 | iwl_disable_interrupts(priv); |
0359facc MA |
2502 | spin_unlock_irqrestore(&priv->lock, flags); |
2503 | iwl_synchronize_irq(priv); | |
b481de9c ZY |
2504 | |
2505 | if (priv->mac80211_registered) | |
2506 | ieee80211_stop_queues(priv->hw); | |
2507 | ||
5b9f8cd3 | 2508 | /* If we have not previously called iwl_init() then |
a60e77e5 | 2509 | * clear all bits but the RF Kill bit and return */ |
fee1247a | 2510 | if (!iwl_is_init(priv)) { |
b481de9c ZY |
2511 | priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2512 | STATUS_RF_KILL_HW | | |
9788864e RC |
2513 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2514 | STATUS_GEO_CONFIGURED | | |
052ec3f1 MA |
2515 | test_bit(STATUS_EXIT_PENDING, &priv->status) << |
2516 | STATUS_EXIT_PENDING; | |
b481de9c ZY |
2517 | goto exit; |
2518 | } | |
2519 | ||
6da3a13e | 2520 | /* ...otherwise clear out all the status bits but the RF Kill |
a60e77e5 | 2521 | * bit and continue taking the NIC down. */ |
b481de9c ZY |
2522 | priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) << |
2523 | STATUS_RF_KILL_HW | | |
9788864e RC |
2524 | test_bit(STATUS_GEO_CONFIGURED, &priv->status) << |
2525 | STATUS_GEO_CONFIGURED | | |
b481de9c | 2526 | test_bit(STATUS_FW_ERROR, &priv->status) << |
052ec3f1 MA |
2527 | STATUS_FW_ERROR | |
2528 | test_bit(STATUS_EXIT_PENDING, &priv->status) << | |
2529 | STATUS_EXIT_PENDING; | |
b481de9c | 2530 | |
ef850d7c MA |
2531 | /* device going down, Stop using ICT table */ |
2532 | iwl_disable_ict(priv); | |
b481de9c | 2533 | |
74bcdb33 | 2534 | iwlagn_txq_ctx_stop(priv); |
54b81550 | 2535 | iwlagn_rxq_stop(priv); |
b481de9c | 2536 | |
309e731a BC |
2537 | /* Power-down device's busmaster DMA clocks */ |
2538 | iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
b481de9c ZY |
2539 | udelay(5); |
2540 | ||
309e731a BC |
2541 | /* Make sure (redundant) we've released our request to stay awake */ |
2542 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | |
2543 | ||
4d2ccdb9 BC |
2544 | /* Stop the device, and put it in low power state */ |
2545 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
2546 | ||
b481de9c | 2547 | exit: |
885ba202 | 2548 | memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp)); |
b481de9c ZY |
2549 | |
2550 | if (priv->ibss_beacon) | |
2551 | dev_kfree_skb(priv->ibss_beacon); | |
2552 | priv->ibss_beacon = NULL; | |
2553 | ||
2554 | /* clear out any free frames */ | |
fcab423d | 2555 | iwl_clear_free_frames(priv); |
b481de9c ZY |
2556 | } |
2557 | ||
5b9f8cd3 | 2558 | static void iwl_down(struct iwl_priv *priv) |
b481de9c ZY |
2559 | { |
2560 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2561 | __iwl_down(priv); |
b481de9c | 2562 | mutex_unlock(&priv->mutex); |
b24d22b1 | 2563 | |
4e39317d | 2564 | iwl_cancel_deferred_work(priv); |
b481de9c ZY |
2565 | } |
2566 | ||
086ed117 MA |
2567 | #define HW_READY_TIMEOUT (50) |
2568 | ||
2569 | static int iwl_set_hw_ready(struct iwl_priv *priv) | |
2570 | { | |
2571 | int ret = 0; | |
2572 | ||
2573 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2574 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); | |
2575 | ||
2576 | /* See if we got it */ | |
2577 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2578 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2579 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
2580 | HW_READY_TIMEOUT); | |
2581 | if (ret != -ETIMEDOUT) | |
2582 | priv->hw_ready = true; | |
2583 | else | |
2584 | priv->hw_ready = false; | |
2585 | ||
2586 | IWL_DEBUG_INFO(priv, "hardware %s\n", | |
2587 | (priv->hw_ready == 1) ? "ready" : "not ready"); | |
2588 | return ret; | |
2589 | } | |
2590 | ||
2591 | static int iwl_prepare_card_hw(struct iwl_priv *priv) | |
2592 | { | |
2593 | int ret = 0; | |
2594 | ||
91dd6c27 | 2595 | IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n"); |
086ed117 | 2596 | |
3354a0f6 MA |
2597 | ret = iwl_set_hw_ready(priv); |
2598 | if (priv->hw_ready) | |
2599 | return ret; | |
2600 | ||
2601 | /* If HW is not ready, prepare the conditions to check again */ | |
086ed117 MA |
2602 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
2603 | CSR_HW_IF_CONFIG_REG_PREPARE); | |
2604 | ||
2605 | ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG, | |
2606 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
2607 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
2608 | ||
3354a0f6 | 2609 | /* HW should be ready by now, check again. */ |
086ed117 MA |
2610 | if (ret != -ETIMEDOUT) |
2611 | iwl_set_hw_ready(priv); | |
2612 | ||
2613 | return ret; | |
2614 | } | |
2615 | ||
b481de9c ZY |
2616 | #define MAX_HW_RESTARTS 5 |
2617 | ||
5b9f8cd3 | 2618 | static int __iwl_up(struct iwl_priv *priv) |
b481de9c | 2619 | { |
57aab75a TW |
2620 | int i; |
2621 | int ret; | |
b481de9c ZY |
2622 | |
2623 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { | |
39aadf8c | 2624 | IWL_WARN(priv, "Exit pending; will not bring the NIC up\n"); |
b481de9c ZY |
2625 | return -EIO; |
2626 | } | |
2627 | ||
e903fbd4 | 2628 | if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) { |
15b1687c | 2629 | IWL_ERR(priv, "ucode not available for device bringup\n"); |
e903fbd4 RC |
2630 | return -EIO; |
2631 | } | |
2632 | ||
2c810ccd JB |
2633 | ret = iwl_alloc_bcast_station(priv, true); |
2634 | if (ret) | |
2635 | return ret; | |
2636 | ||
086ed117 MA |
2637 | iwl_prepare_card_hw(priv); |
2638 | ||
2639 | if (!priv->hw_ready) { | |
2640 | IWL_WARN(priv, "Exit HW not ready\n"); | |
2641 | return -EIO; | |
2642 | } | |
2643 | ||
e655b9f0 | 2644 | /* If platform's RF_KILL switch is NOT set to KILL */ |
c1842d61 | 2645 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
e655b9f0 | 2646 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2647 | else |
e655b9f0 | 2648 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
3bff19c2 | 2649 | |
c1842d61 | 2650 | if (iwl_is_rfkill(priv)) { |
a60e77e5 JB |
2651 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, true); |
2652 | ||
5b9f8cd3 | 2653 | iwl_enable_interrupts(priv); |
a60e77e5 | 2654 | IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n"); |
c1842d61 | 2655 | return 0; |
b481de9c ZY |
2656 | } |
2657 | ||
3395f6e9 | 2658 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
b481de9c | 2659 | |
74bcdb33 | 2660 | ret = iwlagn_hw_nic_init(priv); |
57aab75a | 2661 | if (ret) { |
15b1687c | 2662 | IWL_ERR(priv, "Unable to init nic\n"); |
57aab75a | 2663 | return ret; |
b481de9c ZY |
2664 | } |
2665 | ||
2666 | /* make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2667 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2668 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, | |
b481de9c ZY |
2669 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
2670 | ||
2671 | /* clear (again), then enable host interrupts */ | |
3395f6e9 | 2672 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
5b9f8cd3 | 2673 | iwl_enable_interrupts(priv); |
b481de9c ZY |
2674 | |
2675 | /* really make sure rfkill handshake bits are cleared */ | |
3395f6e9 TW |
2676 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
2677 | iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
b481de9c ZY |
2678 | |
2679 | /* Copy original ucode data image from disk into backup cache. | |
2680 | * This will be used to initialize the on-board processor's | |
2681 | * data SRAM for a clean start when the runtime program first loads. */ | |
2682 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | |
5a66926a | 2683 | priv->ucode_data.len); |
b481de9c | 2684 | |
b481de9c ZY |
2685 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2686 | ||
b481de9c ZY |
2687 | /* load bootstrap state machine, |
2688 | * load bootstrap program into processor's memory, | |
2689 | * prepare to load the "initialize" uCode */ | |
57aab75a | 2690 | ret = priv->cfg->ops->lib->load_ucode(priv); |
b481de9c | 2691 | |
57aab75a | 2692 | if (ret) { |
15b1687c WT |
2693 | IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n", |
2694 | ret); | |
b481de9c ZY |
2695 | continue; |
2696 | } | |
2697 | ||
2698 | /* start card; "initialize" will load runtime ucode */ | |
5b9f8cd3 | 2699 | iwl_nic_start(priv); |
b481de9c | 2700 | |
e1623446 | 2701 | IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n"); |
b481de9c ZY |
2702 | |
2703 | return 0; | |
2704 | } | |
2705 | ||
2706 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
5b9f8cd3 | 2707 | __iwl_down(priv); |
64e72c3e | 2708 | clear_bit(STATUS_EXIT_PENDING, &priv->status); |
b481de9c ZY |
2709 | |
2710 | /* tried to restart and config the device for as long as our | |
2711 | * patience could withstand */ | |
15b1687c | 2712 | IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i); |
b481de9c ZY |
2713 | return -EIO; |
2714 | } | |
2715 | ||
2716 | ||
2717 | /***************************************************************************** | |
2718 | * | |
2719 | * Workqueue callbacks | |
2720 | * | |
2721 | *****************************************************************************/ | |
2722 | ||
4a4a9e81 | 2723 | static void iwl_bg_init_alive_start(struct work_struct *data) |
b481de9c | 2724 | { |
c79dd5b5 TW |
2725 | struct iwl_priv *priv = |
2726 | container_of(data, struct iwl_priv, init_alive_start.work); | |
b481de9c ZY |
2727 | |
2728 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2729 | return; | |
2730 | ||
2731 | mutex_lock(&priv->mutex); | |
f3ccc08c | 2732 | priv->cfg->ops->lib->init_alive_start(priv); |
b481de9c ZY |
2733 | mutex_unlock(&priv->mutex); |
2734 | } | |
2735 | ||
4a4a9e81 | 2736 | static void iwl_bg_alive_start(struct work_struct *data) |
b481de9c | 2737 | { |
c79dd5b5 TW |
2738 | struct iwl_priv *priv = |
2739 | container_of(data, struct iwl_priv, alive_start.work); | |
b481de9c ZY |
2740 | |
2741 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2742 | return; | |
2743 | ||
258c44a0 MA |
2744 | /* enable dram interrupt */ |
2745 | iwl_reset_ict(priv); | |
2746 | ||
b481de9c | 2747 | mutex_lock(&priv->mutex); |
4a4a9e81 | 2748 | iwl_alive_start(priv); |
b481de9c ZY |
2749 | mutex_unlock(&priv->mutex); |
2750 | } | |
2751 | ||
16e727e8 EG |
2752 | static void iwl_bg_run_time_calib_work(struct work_struct *work) |
2753 | { | |
2754 | struct iwl_priv *priv = container_of(work, struct iwl_priv, | |
2755 | run_time_calib_work); | |
2756 | ||
2757 | mutex_lock(&priv->mutex); | |
2758 | ||
2759 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
2760 | test_bit(STATUS_SCANNING, &priv->status)) { | |
2761 | mutex_unlock(&priv->mutex); | |
2762 | return; | |
2763 | } | |
2764 | ||
2765 | if (priv->start_calib) { | |
a2064b7a | 2766 | iwl_chain_noise_calibration(priv, &priv->_agn.statistics); |
16e727e8 | 2767 | |
a2064b7a | 2768 | iwl_sensitivity_calibration(priv, &priv->_agn.statistics); |
16e727e8 EG |
2769 | } |
2770 | ||
2771 | mutex_unlock(&priv->mutex); | |
2772 | return; | |
2773 | } | |
2774 | ||
5b9f8cd3 | 2775 | static void iwl_bg_restart(struct work_struct *data) |
b481de9c | 2776 | { |
c79dd5b5 | 2777 | struct iwl_priv *priv = container_of(data, struct iwl_priv, restart); |
b481de9c ZY |
2778 | |
2779 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2780 | return; | |
2781 | ||
19cc1087 JB |
2782 | if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) { |
2783 | mutex_lock(&priv->mutex); | |
2784 | priv->vif = NULL; | |
2785 | priv->is_open = 0; | |
2786 | mutex_unlock(&priv->mutex); | |
2787 | iwl_down(priv); | |
2788 | ieee80211_restart_hw(priv->hw); | |
2789 | } else { | |
2790 | iwl_down(priv); | |
80676518 JB |
2791 | |
2792 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2793 | return; | |
2794 | ||
2795 | mutex_lock(&priv->mutex); | |
2796 | __iwl_up(priv); | |
2797 | mutex_unlock(&priv->mutex); | |
19cc1087 | 2798 | } |
b481de9c ZY |
2799 | } |
2800 | ||
5b9f8cd3 | 2801 | static void iwl_bg_rx_replenish(struct work_struct *data) |
b481de9c | 2802 | { |
c79dd5b5 TW |
2803 | struct iwl_priv *priv = |
2804 | container_of(data, struct iwl_priv, rx_replenish); | |
b481de9c ZY |
2805 | |
2806 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2807 | return; | |
2808 | ||
2809 | mutex_lock(&priv->mutex); | |
54b81550 | 2810 | iwlagn_rx_replenish(priv); |
b481de9c ZY |
2811 | mutex_unlock(&priv->mutex); |
2812 | } | |
2813 | ||
7878a5a4 MA |
2814 | #define IWL_DELAY_NEXT_SCAN (HZ*2) |
2815 | ||
1dda6d28 | 2816 | void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 2817 | { |
b481de9c | 2818 | struct ieee80211_conf *conf = NULL; |
857485c0 | 2819 | int ret = 0; |
b481de9c | 2820 | |
1dda6d28 JB |
2821 | if (!vif || !priv->is_open) |
2822 | return; | |
2823 | ||
2824 | if (vif->type == NL80211_IFTYPE_AP) { | |
15b1687c | 2825 | IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__); |
b481de9c ZY |
2826 | return; |
2827 | } | |
2828 | ||
b481de9c ZY |
2829 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
2830 | return; | |
2831 | ||
2a421b91 | 2832 | iwl_scan_cancel_timeout(priv, 200); |
052c4b9f | 2833 | |
b481de9c ZY |
2834 | conf = ieee80211_get_hw_conf(priv->hw); |
2835 | ||
2836 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 2837 | iwlcore_commit_rxon(priv); |
b481de9c | 2838 | |
1dda6d28 | 2839 | iwl_setup_rxon_timing(priv, vif); |
857485c0 | 2840 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 2841 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 2842 | if (ret) |
39aadf8c | 2843 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
2844 | "Attempting to continue.\n"); |
2845 | ||
2846 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2847 | ||
42eb7c64 | 2848 | iwl_set_rxon_ht(priv, &priv->current_ht_config); |
4f85f5b3 | 2849 | |
45823531 AK |
2850 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
2851 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
2852 | ||
1dda6d28 | 2853 | priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid); |
b481de9c | 2854 | |
e1623446 | 2855 | IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n", |
1dda6d28 | 2856 | vif->bss_conf.aid, vif->bss_conf.beacon_int); |
b481de9c | 2857 | |
1dda6d28 | 2858 | if (vif->bss_conf.assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE) |
b481de9c ZY |
2859 | priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; |
2860 | else | |
2861 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2862 | ||
2863 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
1dda6d28 JB |
2864 | if (vif->bss_conf.assoc_capability & |
2865 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
b481de9c ZY |
2866 | priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK; |
2867 | else | |
2868 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2869 | ||
1dda6d28 | 2870 | if (vif->type == NL80211_IFTYPE_ADHOC) |
b481de9c | 2871 | priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK; |
b481de9c ZY |
2872 | } |
2873 | ||
e0158e61 | 2874 | iwlcore_commit_rxon(priv); |
b481de9c | 2875 | |
fe6b23dd | 2876 | IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n", |
1dda6d28 | 2877 | vif->bss_conf.aid, priv->active_rxon.bssid_addr); |
fe6b23dd | 2878 | |
1dda6d28 | 2879 | switch (vif->type) { |
05c914fe | 2880 | case NL80211_IFTYPE_STATION: |
b481de9c | 2881 | break; |
05c914fe | 2882 | case NL80211_IFTYPE_ADHOC: |
5b9f8cd3 | 2883 | iwl_send_beacon_cmd(priv); |
b481de9c | 2884 | break; |
b481de9c | 2885 | default: |
15b1687c | 2886 | IWL_ERR(priv, "%s Should not be called in %d mode\n", |
1dda6d28 | 2887 | __func__, vif->type); |
b481de9c ZY |
2888 | break; |
2889 | } | |
2890 | ||
04816448 GE |
2891 | /* the chain noise calibration will enabled PM upon completion |
2892 | * If chain noise has already been run, then we need to enable | |
2893 | * power management here */ | |
2894 | if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE) | |
e312c24c | 2895 | iwl_power_update_mode(priv, false); |
c90a74ba EG |
2896 | |
2897 | /* Enable Rx differential gain and sensitivity calibrations */ | |
2898 | iwl_chain_noise_reset(priv); | |
2899 | priv->start_calib = 1; | |
2900 | ||
508e32e1 RC |
2901 | } |
2902 | ||
b481de9c ZY |
2903 | /***************************************************************************** |
2904 | * | |
2905 | * mac80211 entry point functions | |
2906 | * | |
2907 | *****************************************************************************/ | |
2908 | ||
154b25ce | 2909 | #define UCODE_READY_TIMEOUT (4 * HZ) |
5a66926a | 2910 | |
f0b6e2e8 RC |
2911 | /* |
2912 | * Not a mac80211 entry point function, but it fits in with all the | |
2913 | * other mac80211 functions grouped here. | |
2914 | */ | |
dd7a2509 JB |
2915 | static int iwl_mac_setup_register(struct iwl_priv *priv, |
2916 | struct iwlagn_ucode_capabilities *capa) | |
f0b6e2e8 RC |
2917 | { |
2918 | int ret; | |
2919 | struct ieee80211_hw *hw = priv->hw; | |
2920 | hw->rate_control_algorithm = "iwl-agn-rs"; | |
2921 | ||
2922 | /* Tell mac80211 our characteristics */ | |
2923 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | |
f0b6e2e8 RC |
2924 | IEEE80211_HW_AMPDU_AGGREGATION | |
2925 | IEEE80211_HW_SPECTRUM_MGMT; | |
2926 | ||
2927 | if (!priv->cfg->broken_powersave) | |
2928 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | | |
2929 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | |
2930 | ||
ba37a3d0 JB |
2931 | if (priv->cfg->sku & IWL_SKU_N) |
2932 | hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | |
2933 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
2934 | ||
8d9698b3 | 2935 | hw->sta_data_size = sizeof(struct iwl_station_priv); |
fd1af15d JB |
2936 | hw->vif_data_size = sizeof(struct iwl_vif_priv); |
2937 | ||
f0b6e2e8 RC |
2938 | hw->wiphy->interface_modes = |
2939 | BIT(NL80211_IFTYPE_STATION) | | |
2940 | BIT(NL80211_IFTYPE_ADHOC); | |
2941 | ||
f6c8f152 | 2942 | hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY | |
5be83de5 | 2943 | WIPHY_FLAG_DISABLE_BEACON_HINTS; |
f0b6e2e8 RC |
2944 | |
2945 | /* | |
2946 | * For now, disable PS by default because it affects | |
2947 | * RX performance significantly. | |
2948 | */ | |
5be83de5 | 2949 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
f0b6e2e8 | 2950 | |
1382c71c | 2951 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; |
f0b6e2e8 | 2952 | /* we create the 802.11 header and a zero-length SSID element */ |
dd7a2509 | 2953 | hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2; |
f0b6e2e8 RC |
2954 | |
2955 | /* Default value; 4 EDCA QOS priorities */ | |
2956 | hw->queues = 4; | |
2957 | ||
2958 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | |
2959 | ||
2960 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | |
2961 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
2962 | &priv->bands[IEEE80211_BAND_2GHZ]; | |
2963 | if (priv->bands[IEEE80211_BAND_5GHZ].n_channels) | |
2964 | priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
2965 | &priv->bands[IEEE80211_BAND_5GHZ]; | |
2966 | ||
2967 | ret = ieee80211_register_hw(priv->hw); | |
2968 | if (ret) { | |
2969 | IWL_ERR(priv, "Failed to register hw (error %d)\n", ret); | |
2970 | return ret; | |
2971 | } | |
2972 | priv->mac80211_registered = 1; | |
2973 | ||
2974 | return 0; | |
2975 | } | |
2976 | ||
2977 | ||
5b9f8cd3 | 2978 | static int iwl_mac_start(struct ieee80211_hw *hw) |
b481de9c | 2979 | { |
c79dd5b5 | 2980 | struct iwl_priv *priv = hw->priv; |
5a66926a | 2981 | int ret; |
b481de9c | 2982 | |
e1623446 | 2983 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c ZY |
2984 | |
2985 | /* we should be verifying the device is ready to be opened */ | |
2986 | mutex_lock(&priv->mutex); | |
5b9f8cd3 | 2987 | ret = __iwl_up(priv); |
b481de9c | 2988 | mutex_unlock(&priv->mutex); |
5a66926a | 2989 | |
e655b9f0 | 2990 | if (ret) |
6cd0b1cb | 2991 | return ret; |
e655b9f0 | 2992 | |
c1842d61 TW |
2993 | if (iwl_is_rfkill(priv)) |
2994 | goto out; | |
2995 | ||
e1623446 | 2996 | IWL_DEBUG_INFO(priv, "Start UP work done.\n"); |
e655b9f0 | 2997 | |
fe9b6b72 | 2998 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from |
5a66926a | 2999 | * mac80211 will not be run successfully. */ |
154b25ce EG |
3000 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
3001 | test_bit(STATUS_READY, &priv->status), | |
3002 | UCODE_READY_TIMEOUT); | |
3003 | if (!ret) { | |
3004 | if (!test_bit(STATUS_READY, &priv->status)) { | |
15b1687c | 3005 | IWL_ERR(priv, "START_ALIVE timeout after %dms.\n", |
154b25ce | 3006 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
6cd0b1cb | 3007 | return -ETIMEDOUT; |
5a66926a | 3008 | } |
fe9b6b72 | 3009 | } |
0a078ffa | 3010 | |
e932a609 JB |
3011 | iwl_led_start(priv); |
3012 | ||
c1842d61 | 3013 | out: |
0a078ffa | 3014 | priv->is_open = 1; |
e1623446 | 3015 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3016 | return 0; |
3017 | } | |
3018 | ||
5b9f8cd3 | 3019 | static void iwl_mac_stop(struct ieee80211_hw *hw) |
b481de9c | 3020 | { |
c79dd5b5 | 3021 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3022 | |
e1623446 | 3023 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
948c171c | 3024 | |
19cc1087 | 3025 | if (!priv->is_open) |
e655b9f0 | 3026 | return; |
e655b9f0 | 3027 | |
b481de9c | 3028 | priv->is_open = 0; |
5a66926a | 3029 | |
5bddf549 | 3030 | if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) { |
e655b9f0 ZY |
3031 | /* stop mac, cancel any scan request and clear |
3032 | * RXON_FILTER_ASSOC_MSK BIT | |
3033 | */ | |
5a66926a | 3034 | mutex_lock(&priv->mutex); |
2a421b91 | 3035 | iwl_scan_cancel_timeout(priv, 100); |
fde3571f | 3036 | mutex_unlock(&priv->mutex); |
fde3571f MA |
3037 | } |
3038 | ||
5b9f8cd3 | 3039 | iwl_down(priv); |
5a66926a ZY |
3040 | |
3041 | flush_workqueue(priv->workqueue); | |
6cd0b1cb HS |
3042 | |
3043 | /* enable interrupts again in order to receive rfkill changes */ | |
3044 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | |
3045 | iwl_enable_interrupts(priv); | |
948c171c | 3046 | |
e1623446 | 3047 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c ZY |
3048 | } |
3049 | ||
5b9f8cd3 | 3050 | static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
b481de9c | 3051 | { |
c79dd5b5 | 3052 | struct iwl_priv *priv = hw->priv; |
b481de9c | 3053 | |
e1623446 | 3054 | IWL_DEBUG_MACDUMP(priv, "enter\n"); |
b481de9c | 3055 | |
e1623446 | 3056 | IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e039fa4a | 3057 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
b481de9c | 3058 | |
74bcdb33 | 3059 | if (iwlagn_tx_skb(priv, skb)) |
b481de9c ZY |
3060 | dev_kfree_skb_any(skb); |
3061 | ||
e1623446 | 3062 | IWL_DEBUG_MACDUMP(priv, "leave\n"); |
637f8837 | 3063 | return NETDEV_TX_OK; |
b481de9c ZY |
3064 | } |
3065 | ||
1dda6d28 | 3066 | void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif) |
b481de9c | 3067 | { |
857485c0 | 3068 | int ret = 0; |
b481de9c | 3069 | |
d986bcd1 | 3070 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
b481de9c ZY |
3071 | return; |
3072 | ||
3073 | /* The following should be done only at AP bring up */ | |
3195c1f3 | 3074 | if (!iwl_is_associated(priv)) { |
b481de9c ZY |
3075 | |
3076 | /* RXON - unassoc (to set timing command) */ | |
3077 | priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 3078 | iwlcore_commit_rxon(priv); |
b481de9c ZY |
3079 | |
3080 | /* RXON Timing */ | |
1dda6d28 | 3081 | iwl_setup_rxon_timing(priv, vif); |
857485c0 | 3082 | ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING, |
b481de9c | 3083 | sizeof(priv->rxon_timing), &priv->rxon_timing); |
857485c0 | 3084 | if (ret) |
39aadf8c | 3085 | IWL_WARN(priv, "REPLY_RXON_TIMING failed - " |
b481de9c ZY |
3086 | "Attempting to continue.\n"); |
3087 | ||
f513dfff DH |
3088 | /* AP has all antennas */ |
3089 | priv->chain_noise_data.active_chains = | |
3090 | priv->hw_params.valid_rx_ant; | |
3091 | iwl_set_rxon_ht(priv, &priv->current_ht_config); | |
45823531 AK |
3092 | if (priv->cfg->ops->hcmd->set_rxon_chain) |
3093 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
b481de9c | 3094 | |
1dda6d28 JB |
3095 | priv->staging_rxon.assoc_id = 0; |
3096 | ||
3097 | if (vif->bss_conf.assoc_capability & | |
3098 | WLAN_CAPABILITY_SHORT_PREAMBLE) | |
b481de9c ZY |
3099 | priv->staging_rxon.flags |= |
3100 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
3101 | else | |
3102 | priv->staging_rxon.flags &= | |
3103 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
3104 | ||
3105 | if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) { | |
1dda6d28 JB |
3106 | if (vif->bss_conf.assoc_capability & |
3107 | WLAN_CAPABILITY_SHORT_SLOT_TIME) | |
b481de9c ZY |
3108 | priv->staging_rxon.flags |= |
3109 | RXON_FLG_SHORT_SLOT_MSK; | |
3110 | else | |
3111 | priv->staging_rxon.flags &= | |
3112 | ~RXON_FLG_SHORT_SLOT_MSK; | |
3113 | ||
1dda6d28 | 3114 | if (vif->type == NL80211_IFTYPE_ADHOC) |
b481de9c ZY |
3115 | priv->staging_rxon.flags &= |
3116 | ~RXON_FLG_SHORT_SLOT_MSK; | |
3117 | } | |
3118 | /* restore RXON assoc */ | |
3119 | priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
e0158e61 | 3120 | iwlcore_commit_rxon(priv); |
e1493deb | 3121 | } |
5b9f8cd3 | 3122 | iwl_send_beacon_cmd(priv); |
b481de9c ZY |
3123 | |
3124 | /* FIXME - we need to add code here to detect a totally new | |
3125 | * configuration, reset the AP, unassoc, rxon timing, assoc, | |
3126 | * clear sta table, add BCAST sta... */ | |
3127 | } | |
3128 | ||
5b9f8cd3 | 3129 | static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw, |
b3fbdcf4 JB |
3130 | struct ieee80211_vif *vif, |
3131 | struct ieee80211_key_conf *keyconf, | |
3132 | struct ieee80211_sta *sta, | |
3133 | u32 iv32, u16 *phase1key) | |
ab885f8c | 3134 | { |
ab885f8c | 3135 | |
9f58671e | 3136 | struct iwl_priv *priv = hw->priv; |
e1623446 | 3137 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
ab885f8c | 3138 | |
bdbb612f | 3139 | iwl_update_tkip_key(priv, keyconf, sta, |
b3fbdcf4 | 3140 | iv32, phase1key); |
ab885f8c | 3141 | |
e1623446 | 3142 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
ab885f8c EG |
3143 | } |
3144 | ||
5b9f8cd3 | 3145 | static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
dc822b5d JB |
3146 | struct ieee80211_vif *vif, |
3147 | struct ieee80211_sta *sta, | |
b481de9c ZY |
3148 | struct ieee80211_key_conf *key) |
3149 | { | |
c79dd5b5 | 3150 | struct iwl_priv *priv = hw->priv; |
42986796 WT |
3151 | int ret; |
3152 | u8 sta_id; | |
3153 | bool is_default_wep_key = false; | |
b481de9c | 3154 | |
e1623446 | 3155 | IWL_DEBUG_MAC80211(priv, "enter\n"); |
b481de9c | 3156 | |
90e8e424 | 3157 | if (priv->cfg->mod_params->sw_crypto) { |
e1623446 | 3158 | IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n"); |
b481de9c ZY |
3159 | return -EOPNOTSUPP; |
3160 | } | |
b481de9c | 3161 | |
0af8bcae JB |
3162 | sta_id = iwl_sta_id_or_broadcast(priv, sta); |
3163 | if (sta_id == IWL_INVALID_STATION) | |
3164 | return -EINVAL; | |
b481de9c | 3165 | |
6974e363 | 3166 | mutex_lock(&priv->mutex); |
2a421b91 | 3167 | iwl_scan_cancel_timeout(priv, 100); |
6974e363 | 3168 | |
a90178fa JB |
3169 | /* |
3170 | * If we are getting WEP group key and we didn't receive any key mapping | |
6974e363 EG |
3171 | * so far, we are in legacy wep mode (group key only), otherwise we are |
3172 | * in 1X mode. | |
a90178fa JB |
3173 | * In legacy wep mode, we use another host command to the uCode. |
3174 | */ | |
3175 | if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) { | |
6974e363 EG |
3176 | if (cmd == SET_KEY) |
3177 | is_default_wep_key = !priv->key_mapping_key; | |
3178 | else | |
ccc038ab EG |
3179 | is_default_wep_key = |
3180 | (key->hw_key_idx == HW_KEY_DEFAULT); | |
6974e363 | 3181 | } |
052c4b9f | 3182 | |
b481de9c | 3183 | switch (cmd) { |
deb09c43 | 3184 | case SET_KEY: |
6974e363 EG |
3185 | if (is_default_wep_key) |
3186 | ret = iwl_set_default_wep_key(priv, key); | |
deb09c43 | 3187 | else |
7480513f | 3188 | ret = iwl_set_dynamic_key(priv, key, sta_id); |
deb09c43 | 3189 | |
e1623446 | 3190 | IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n"); |
b481de9c ZY |
3191 | break; |
3192 | case DISABLE_KEY: | |
6974e363 EG |
3193 | if (is_default_wep_key) |
3194 | ret = iwl_remove_default_wep_key(priv, key); | |
deb09c43 | 3195 | else |
3ec47732 | 3196 | ret = iwl_remove_dynamic_key(priv, key, sta_id); |
deb09c43 | 3197 | |
e1623446 | 3198 | IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n"); |
b481de9c ZY |
3199 | break; |
3200 | default: | |
deb09c43 | 3201 | ret = -EINVAL; |
b481de9c ZY |
3202 | } |
3203 | ||
72e15d71 | 3204 | mutex_unlock(&priv->mutex); |
e1623446 | 3205 | IWL_DEBUG_MAC80211(priv, "leave\n"); |
b481de9c | 3206 | |
deb09c43 | 3207 | return ret; |
b481de9c ZY |
3208 | } |
3209 | ||
5b9f8cd3 | 3210 | static int iwl_mac_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 3211 | struct ieee80211_vif *vif, |
832f47e3 JB |
3212 | enum ieee80211_ampdu_mlme_action action, |
3213 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) | |
d783b061 TW |
3214 | { |
3215 | struct iwl_priv *priv = hw->priv; | |
5c2207c6 | 3216 | int ret; |
d783b061 | 3217 | |
e1623446 | 3218 | IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n", |
e174961c | 3219 | sta->addr, tid); |
d783b061 TW |
3220 | |
3221 | if (!(priv->cfg->sku & IWL_SKU_N)) | |
3222 | return -EACCES; | |
3223 | ||
3224 | switch (action) { | |
3225 | case IEEE80211_AMPDU_RX_START: | |
e1623446 | 3226 | IWL_DEBUG_HT(priv, "start Rx\n"); |
619753ff | 3227 | return iwl_sta_rx_agg_start(priv, sta, tid, *ssn); |
d783b061 | 3228 | case IEEE80211_AMPDU_RX_STOP: |
e1623446 | 3229 | IWL_DEBUG_HT(priv, "stop Rx\n"); |
619753ff | 3230 | ret = iwl_sta_rx_agg_stop(priv, sta, tid); |
5c2207c6 WYG |
3231 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
3232 | return 0; | |
3233 | else | |
3234 | return ret; | |
d783b061 | 3235 | case IEEE80211_AMPDU_TX_START: |
e1623446 | 3236 | IWL_DEBUG_HT(priv, "start Tx\n"); |
619753ff | 3237 | ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn); |
d5a0ffa3 WYG |
3238 | if (ret == 0) { |
3239 | priv->_agn.agg_tids_count++; | |
3240 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3241 | priv->_agn.agg_tids_count); | |
3242 | } | |
3243 | return ret; | |
d783b061 | 3244 | case IEEE80211_AMPDU_TX_STOP: |
e1623446 | 3245 | IWL_DEBUG_HT(priv, "stop Tx\n"); |
619753ff | 3246 | ret = iwlagn_tx_agg_stop(priv, vif, sta, tid); |
d5a0ffa3 WYG |
3247 | if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) { |
3248 | priv->_agn.agg_tids_count--; | |
3249 | IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n", | |
3250 | priv->_agn.agg_tids_count); | |
3251 | } | |
5c2207c6 WYG |
3252 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) |
3253 | return 0; | |
3254 | else | |
3255 | return ret; | |
f0527971 WYG |
3256 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
3257 | /* do nothing */ | |
3258 | return -EOPNOTSUPP; | |
d783b061 | 3259 | default: |
e1623446 | 3260 | IWL_DEBUG_HT(priv, "unknown\n"); |
d783b061 TW |
3261 | return -EINVAL; |
3262 | break; | |
3263 | } | |
3264 | return 0; | |
3265 | } | |
9f58671e | 3266 | |
6ab10ff8 JB |
3267 | static void iwl_mac_sta_notify(struct ieee80211_hw *hw, |
3268 | struct ieee80211_vif *vif, | |
3269 | enum sta_notify_cmd cmd, | |
3270 | struct ieee80211_sta *sta) | |
3271 | { | |
3272 | struct iwl_priv *priv = hw->priv; | |
3273 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
3274 | int sta_id; | |
3275 | ||
6ab10ff8 | 3276 | switch (cmd) { |
6ab10ff8 JB |
3277 | case STA_NOTIFY_SLEEP: |
3278 | WARN_ON(!sta_priv->client); | |
3279 | sta_priv->asleep = true; | |
3280 | if (atomic_read(&sta_priv->pending_frames) > 0) | |
3281 | ieee80211_sta_block_awake(hw, sta, true); | |
3282 | break; | |
3283 | case STA_NOTIFY_AWAKE: | |
3284 | WARN_ON(!sta_priv->client); | |
49dcc819 DH |
3285 | if (!sta_priv->asleep) |
3286 | break; | |
6ab10ff8 | 3287 | sta_priv->asleep = false; |
2a87c26b | 3288 | sta_id = iwl_sta_id(sta); |
6ab10ff8 JB |
3289 | if (sta_id != IWL_INVALID_STATION) |
3290 | iwl_sta_modify_ps_wake(priv, sta_id); | |
3291 | break; | |
3292 | default: | |
3293 | break; | |
3294 | } | |
3295 | } | |
3296 | ||
fe6b23dd RC |
3297 | static int iwlagn_mac_sta_add(struct ieee80211_hw *hw, |
3298 | struct ieee80211_vif *vif, | |
3299 | struct ieee80211_sta *sta) | |
3300 | { | |
3301 | struct iwl_priv *priv = hw->priv; | |
3302 | struct iwl_station_priv *sta_priv = (void *)sta->drv_priv; | |
eafdfbd3 | 3303 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
fe6b23dd RC |
3304 | int ret; |
3305 | u8 sta_id; | |
3306 | ||
fd1af15d JB |
3307 | sta_priv->common.sta_id = IWL_INVALID_STATION; |
3308 | ||
fe6b23dd RC |
3309 | IWL_DEBUG_INFO(priv, "received request to add station %pM\n", |
3310 | sta->addr); | |
3311 | ||
3312 | atomic_set(&sta_priv->pending_frames, 0); | |
3313 | if (vif->type == NL80211_IFTYPE_AP) | |
3314 | sta_priv->client = true; | |
3315 | ||
3316 | ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap, | |
3317 | &sta_id); | |
3318 | if (ret) { | |
3319 | IWL_ERR(priv, "Unable to add station %pM (%d)\n", | |
3320 | sta->addr, ret); | |
3321 | /* Should we return success if return code is EEXIST ? */ | |
3322 | return ret; | |
3323 | } | |
3324 | ||
fd1af15d JB |
3325 | sta_priv->common.sta_id = sta_id; |
3326 | ||
fe6b23dd | 3327 | /* Initialize rate scaling */ |
91dd6c27 | 3328 | IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n", |
fe6b23dd RC |
3329 | sta->addr); |
3330 | iwl_rs_rate_init(priv, sta, sta_id); | |
3331 | ||
fd1af15d | 3332 | return 0; |
fe6b23dd RC |
3333 | } |
3334 | ||
b481de9c ZY |
3335 | /***************************************************************************** |
3336 | * | |
3337 | * sysfs attributes | |
3338 | * | |
3339 | *****************************************************************************/ | |
3340 | ||
0a6857e7 | 3341 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3342 | |
3343 | /* | |
3344 | * The following adds a new attribute to the sysfs representation | |
c3a739fa | 3345 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) |
b481de9c ZY |
3346 | * used for controlling the debug level. |
3347 | * | |
3348 | * See the level definitions in iwl for details. | |
a562a9dd | 3349 | * |
3d816c77 RC |
3350 | * The debug_level being managed using sysfs below is a per device debug |
3351 | * level that is used instead of the global debug level if it (the per | |
3352 | * device debug level) is set. | |
b481de9c | 3353 | */ |
8cf769c6 EK |
3354 | static ssize_t show_debug_level(struct device *d, |
3355 | struct device_attribute *attr, char *buf) | |
b481de9c | 3356 | { |
3d816c77 RC |
3357 | struct iwl_priv *priv = dev_get_drvdata(d); |
3358 | return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv)); | |
b481de9c | 3359 | } |
8cf769c6 EK |
3360 | static ssize_t store_debug_level(struct device *d, |
3361 | struct device_attribute *attr, | |
b481de9c ZY |
3362 | const char *buf, size_t count) |
3363 | { | |
928841b1 | 3364 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
3365 | unsigned long val; |
3366 | int ret; | |
b481de9c | 3367 | |
9257746f TW |
3368 | ret = strict_strtoul(buf, 0, &val); |
3369 | if (ret) | |
978785a3 | 3370 | IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf); |
20594eb0 | 3371 | else { |
3d816c77 | 3372 | priv->debug_level = val; |
20594eb0 WYG |
3373 | if (iwl_alloc_traffic_mem(priv)) |
3374 | IWL_ERR(priv, | |
3375 | "Not enough memory to generate traffic log\n"); | |
3376 | } | |
b481de9c ZY |
3377 | return strnlen(buf, count); |
3378 | } | |
3379 | ||
8cf769c6 EK |
3380 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, |
3381 | show_debug_level, store_debug_level); | |
3382 | ||
b481de9c | 3383 | |
0a6857e7 | 3384 | #endif /* CONFIG_IWLWIFI_DEBUG */ |
b481de9c | 3385 | |
b481de9c ZY |
3386 | |
3387 | static ssize_t show_temperature(struct device *d, | |
3388 | struct device_attribute *attr, char *buf) | |
3389 | { | |
928841b1 | 3390 | struct iwl_priv *priv = dev_get_drvdata(d); |
b481de9c | 3391 | |
fee1247a | 3392 | if (!iwl_is_alive(priv)) |
b481de9c ZY |
3393 | return -EAGAIN; |
3394 | ||
91dbc5bd | 3395 | return sprintf(buf, "%d\n", priv->temperature); |
b481de9c ZY |
3396 | } |
3397 | ||
3398 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | |
3399 | ||
b481de9c ZY |
3400 | static ssize_t show_tx_power(struct device *d, |
3401 | struct device_attribute *attr, char *buf) | |
3402 | { | |
928841b1 | 3403 | struct iwl_priv *priv = dev_get_drvdata(d); |
91f39e8e JS |
3404 | |
3405 | if (!iwl_is_ready_rf(priv)) | |
3406 | return sprintf(buf, "off\n"); | |
3407 | else | |
3408 | return sprintf(buf, "%d\n", priv->tx_power_user_lmt); | |
b481de9c ZY |
3409 | } |
3410 | ||
3411 | static ssize_t store_tx_power(struct device *d, | |
3412 | struct device_attribute *attr, | |
3413 | const char *buf, size_t count) | |
3414 | { | |
928841b1 | 3415 | struct iwl_priv *priv = dev_get_drvdata(d); |
9257746f TW |
3416 | unsigned long val; |
3417 | int ret; | |
b481de9c | 3418 | |
9257746f TW |
3419 | ret = strict_strtoul(buf, 10, &val); |
3420 | if (ret) | |
978785a3 | 3421 | IWL_INFO(priv, "%s is not in decimal form.\n", buf); |
5eadd94b WYG |
3422 | else { |
3423 | ret = iwl_set_tx_power(priv, val, false); | |
3424 | if (ret) | |
3425 | IWL_ERR(priv, "failed setting tx power (0x%d).\n", | |
3426 | ret); | |
3427 | else | |
3428 | ret = count; | |
3429 | } | |
3430 | return ret; | |
b481de9c ZY |
3431 | } |
3432 | ||
3433 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power); | |
3434 | ||
01abfbb2 WYG |
3435 | static ssize_t show_rts_ht_protection(struct device *d, |
3436 | struct device_attribute *attr, char *buf) | |
3437 | { | |
3438 | struct iwl_priv *priv = dev_get_drvdata(d); | |
3439 | ||
3440 | return sprintf(buf, "%s\n", | |
3441 | priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self"); | |
3442 | } | |
3443 | ||
3444 | static ssize_t store_rts_ht_protection(struct device *d, | |
3445 | struct device_attribute *attr, | |
3446 | const char *buf, size_t count) | |
3447 | { | |
3448 | struct iwl_priv *priv = dev_get_drvdata(d); | |
3449 | unsigned long val; | |
3450 | int ret; | |
3451 | ||
3452 | ret = strict_strtoul(buf, 10, &val); | |
3453 | if (ret) | |
3454 | IWL_INFO(priv, "Input is not in decimal form.\n"); | |
3455 | else { | |
3456 | if (!iwl_is_associated(priv)) | |
3457 | priv->cfg->use_rts_for_ht = val ? true : false; | |
3458 | else | |
3459 | IWL_ERR(priv, "Sta associated with AP - " | |
3460 | "Change protection mechanism is not allowed\n"); | |
3461 | ret = count; | |
3462 | } | |
3463 | return ret; | |
3464 | } | |
3465 | ||
3466 | static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO, | |
3467 | show_rts_ht_protection, store_rts_ht_protection); | |
3468 | ||
b481de9c | 3469 | |
b481de9c ZY |
3470 | /***************************************************************************** |
3471 | * | |
3472 | * driver setup and teardown | |
3473 | * | |
3474 | *****************************************************************************/ | |
3475 | ||
4e39317d | 3476 | static void iwl_setup_deferred_work(struct iwl_priv *priv) |
b481de9c | 3477 | { |
d21050c7 | 3478 | priv->workqueue = create_singlethread_workqueue(DRV_NAME); |
b481de9c ZY |
3479 | |
3480 | init_waitqueue_head(&priv->wait_command_queue); | |
3481 | ||
5b9f8cd3 EG |
3482 | INIT_WORK(&priv->restart, iwl_bg_restart); |
3483 | INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish); | |
5b9f8cd3 | 3484 | INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update); |
16e727e8 | 3485 | INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work); |
4a4a9e81 TW |
3486 | INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start); |
3487 | INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start); | |
2a421b91 | 3488 | |
2a421b91 | 3489 | iwl_setup_scan_deferred_work(priv); |
bb8c093b | 3490 | |
4e39317d EG |
3491 | if (priv->cfg->ops->lib->setup_deferred_work) |
3492 | priv->cfg->ops->lib->setup_deferred_work(priv); | |
3493 | ||
3494 | init_timer(&priv->statistics_periodic); | |
3495 | priv->statistics_periodic.data = (unsigned long)priv; | |
5b9f8cd3 | 3496 | priv->statistics_periodic.function = iwl_bg_statistics_periodic; |
b481de9c | 3497 | |
a9e1cb6a WYG |
3498 | init_timer(&priv->ucode_trace); |
3499 | priv->ucode_trace.data = (unsigned long)priv; | |
3500 | priv->ucode_trace.function = iwl_bg_ucode_trace; | |
3501 | ||
b74e31a9 WYG |
3502 | if (priv->cfg->ops->lib->recover_from_tx_stall) { |
3503 | init_timer(&priv->monitor_recover); | |
3504 | priv->monitor_recover.data = (unsigned long)priv; | |
3505 | priv->monitor_recover.function = | |
3506 | priv->cfg->ops->lib->recover_from_tx_stall; | |
3507 | } | |
3508 | ||
ef850d7c MA |
3509 | if (!priv->cfg->use_isr_legacy) |
3510 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3511 | iwl_irq_tasklet, (unsigned long)priv); | |
3512 | else | |
3513 | tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long)) | |
3514 | iwl_irq_tasklet_legacy, (unsigned long)priv); | |
b481de9c ZY |
3515 | } |
3516 | ||
4e39317d | 3517 | static void iwl_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c | 3518 | { |
4e39317d EG |
3519 | if (priv->cfg->ops->lib->cancel_deferred_work) |
3520 | priv->cfg->ops->lib->cancel_deferred_work(priv); | |
b481de9c | 3521 | |
3ae6a054 | 3522 | cancel_delayed_work_sync(&priv->init_alive_start); |
b481de9c | 3523 | cancel_delayed_work(&priv->scan_check); |
88be0264 | 3524 | cancel_work_sync(&priv->start_internal_scan); |
b481de9c | 3525 | cancel_delayed_work(&priv->alive_start); |
b481de9c | 3526 | cancel_work_sync(&priv->beacon_update); |
4e39317d | 3527 | del_timer_sync(&priv->statistics_periodic); |
a9e1cb6a | 3528 | del_timer_sync(&priv->ucode_trace); |
b74e31a9 WYG |
3529 | if (priv->cfg->ops->lib->recover_from_tx_stall) |
3530 | del_timer_sync(&priv->monitor_recover); | |
b481de9c ZY |
3531 | } |
3532 | ||
89f186a8 RC |
3533 | static void iwl_init_hw_rates(struct iwl_priv *priv, |
3534 | struct ieee80211_rate *rates) | |
3535 | { | |
3536 | int i; | |
3537 | ||
3538 | for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) { | |
3539 | rates[i].bitrate = iwl_rates[i].ieee * 5; | |
3540 | rates[i].hw_value = i; /* Rate scaling will work on indexes */ | |
3541 | rates[i].hw_value_short = i; | |
3542 | rates[i].flags = 0; | |
3543 | if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) { | |
3544 | /* | |
3545 | * If CCK != 1M then set short preamble rate flag. | |
3546 | */ | |
3547 | rates[i].flags |= | |
3548 | (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ? | |
3549 | 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
3550 | } | |
3551 | } | |
3552 | } | |
3553 | ||
3554 | static int iwl_init_drv(struct iwl_priv *priv) | |
3555 | { | |
3556 | int ret; | |
3557 | ||
3558 | priv->ibss_beacon = NULL; | |
3559 | ||
89f186a8 RC |
3560 | spin_lock_init(&priv->sta_lock); |
3561 | spin_lock_init(&priv->hcmd_lock); | |
3562 | ||
3563 | INIT_LIST_HEAD(&priv->free_frames); | |
3564 | ||
3565 | mutex_init(&priv->mutex); | |
d2dfe6df | 3566 | mutex_init(&priv->sync_cmd_mutex); |
89f186a8 | 3567 | |
89f186a8 RC |
3568 | priv->ieee_channels = NULL; |
3569 | priv->ieee_rates = NULL; | |
3570 | priv->band = IEEE80211_BAND_2GHZ; | |
3571 | ||
3572 | priv->iw_mode = NL80211_IFTYPE_STATION; | |
ba37a3d0 | 3573 | priv->current_ht_config.smps = IEEE80211_SMPS_STATIC; |
a13d276f | 3574 | priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF; |
d5a0ffa3 | 3575 | priv->_agn.agg_tids_count = 0; |
89f186a8 | 3576 | |
8a472da4 WYG |
3577 | /* initialize force reset */ |
3578 | priv->force_reset[IWL_RF_RESET].reset_duration = | |
3579 | IWL_DELAY_NEXT_FORCE_RF_RESET; | |
3580 | priv->force_reset[IWL_FW_RESET].reset_duration = | |
3581 | IWL_DELAY_NEXT_FORCE_FW_RELOAD; | |
89f186a8 RC |
3582 | |
3583 | /* Choose which receivers/antennas to use */ | |
3584 | if (priv->cfg->ops->hcmd->set_rxon_chain) | |
3585 | priv->cfg->ops->hcmd->set_rxon_chain(priv); | |
3586 | ||
3587 | iwl_init_scan_params(priv); | |
3588 | ||
89f186a8 RC |
3589 | /* Set the tx_power_user_lmt to the lowest power level |
3590 | * this value will get overwritten by channel max power avg | |
3591 | * from eeprom */ | |
b744cb79 | 3592 | priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN; |
89f186a8 RC |
3593 | |
3594 | ret = iwl_init_channel_map(priv); | |
3595 | if (ret) { | |
3596 | IWL_ERR(priv, "initializing regulatory failed: %d\n", ret); | |
3597 | goto err; | |
3598 | } | |
3599 | ||
3600 | ret = iwlcore_init_geos(priv); | |
3601 | if (ret) { | |
3602 | IWL_ERR(priv, "initializing geos failed: %d\n", ret); | |
3603 | goto err_free_channel_map; | |
3604 | } | |
3605 | iwl_init_hw_rates(priv, priv->ieee_rates); | |
3606 | ||
3607 | return 0; | |
3608 | ||
3609 | err_free_channel_map: | |
3610 | iwl_free_channel_map(priv); | |
3611 | err: | |
3612 | return ret; | |
3613 | } | |
3614 | ||
3615 | static void iwl_uninit_drv(struct iwl_priv *priv) | |
3616 | { | |
3617 | iwl_calib_free_results(priv); | |
3618 | iwlcore_free_geos(priv); | |
3619 | iwl_free_channel_map(priv); | |
811ecc99 | 3620 | kfree(priv->scan_cmd); |
89f186a8 RC |
3621 | } |
3622 | ||
5b9f8cd3 | 3623 | static struct attribute *iwl_sysfs_entries[] = { |
b481de9c | 3624 | &dev_attr_temperature.attr, |
b481de9c | 3625 | &dev_attr_tx_power.attr, |
01abfbb2 | 3626 | &dev_attr_rts_ht_protection.attr, |
8cf769c6 EK |
3627 | #ifdef CONFIG_IWLWIFI_DEBUG |
3628 | &dev_attr_debug_level.attr, | |
3629 | #endif | |
b481de9c ZY |
3630 | NULL |
3631 | }; | |
3632 | ||
5b9f8cd3 | 3633 | static struct attribute_group iwl_attribute_group = { |
b481de9c | 3634 | .name = NULL, /* put in device directory */ |
5b9f8cd3 | 3635 | .attrs = iwl_sysfs_entries, |
b481de9c ZY |
3636 | }; |
3637 | ||
5b9f8cd3 EG |
3638 | static struct ieee80211_ops iwl_hw_ops = { |
3639 | .tx = iwl_mac_tx, | |
3640 | .start = iwl_mac_start, | |
3641 | .stop = iwl_mac_stop, | |
3642 | .add_interface = iwl_mac_add_interface, | |
3643 | .remove_interface = iwl_mac_remove_interface, | |
3644 | .config = iwl_mac_config, | |
5b9f8cd3 EG |
3645 | .configure_filter = iwl_configure_filter, |
3646 | .set_key = iwl_mac_set_key, | |
3647 | .update_tkip_key = iwl_mac_update_tkip_key, | |
5b9f8cd3 EG |
3648 | .conf_tx = iwl_mac_conf_tx, |
3649 | .reset_tsf = iwl_mac_reset_tsf, | |
3650 | .bss_info_changed = iwl_bss_info_changed, | |
3651 | .ampdu_action = iwl_mac_ampdu_action, | |
6ab10ff8 JB |
3652 | .hw_scan = iwl_mac_hw_scan, |
3653 | .sta_notify = iwl_mac_sta_notify, | |
fe6b23dd RC |
3654 | .sta_add = iwlagn_mac_sta_add, |
3655 | .sta_remove = iwl_mac_sta_remove, | |
b481de9c ZY |
3656 | }; |
3657 | ||
5b9f8cd3 | 3658 | static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
b481de9c ZY |
3659 | { |
3660 | int err = 0; | |
c79dd5b5 | 3661 | struct iwl_priv *priv; |
b481de9c | 3662 | struct ieee80211_hw *hw; |
82b9a121 | 3663 | struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data); |
0359facc | 3664 | unsigned long flags; |
6cd0b1cb | 3665 | u16 pci_cmd; |
b481de9c | 3666 | |
316c30d9 AK |
3667 | /************************ |
3668 | * 1. Allocating HW data | |
3669 | ************************/ | |
3670 | ||
6440adb5 CB |
3671 | /* Disabling hardware scan means that mac80211 will perform scans |
3672 | * "the hard way", rather than using device's scan. */ | |
1ea87396 | 3673 | if (cfg->mod_params->disable_hw_scan) { |
a562a9dd | 3674 | if (iwl_debug_level & IWL_DL_INFO) |
bf403db8 EK |
3675 | dev_printk(KERN_DEBUG, &(pdev->dev), |
3676 | "Disabling hw_scan\n"); | |
5b9f8cd3 | 3677 | iwl_hw_ops.hw_scan = NULL; |
b481de9c ZY |
3678 | } |
3679 | ||
5b9f8cd3 | 3680 | hw = iwl_alloc_all(cfg, &iwl_hw_ops); |
1d0a082d | 3681 | if (!hw) { |
b481de9c ZY |
3682 | err = -ENOMEM; |
3683 | goto out; | |
3684 | } | |
1d0a082d AK |
3685 | priv = hw->priv; |
3686 | /* At this point both hw and priv are allocated. */ | |
3687 | ||
b481de9c ZY |
3688 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3689 | ||
e1623446 | 3690 | IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n"); |
82b9a121 | 3691 | priv->cfg = cfg; |
b481de9c | 3692 | priv->pci_dev = pdev; |
40cefda9 | 3693 | priv->inta_mask = CSR_INI_SET_MASK; |
316c30d9 | 3694 | |
0a6857e7 | 3695 | #ifdef CONFIG_IWLWIFI_DEBUG |
b481de9c ZY |
3696 | atomic_set(&priv->restrict_refcnt, 0); |
3697 | #endif | |
20594eb0 WYG |
3698 | if (iwl_alloc_traffic_mem(priv)) |
3699 | IWL_ERR(priv, "Not enough memory to generate traffic log\n"); | |
b481de9c | 3700 | |
316c30d9 AK |
3701 | /************************** |
3702 | * 2. Initializing PCI bus | |
3703 | **************************/ | |
3704 | if (pci_enable_device(pdev)) { | |
3705 | err = -ENODEV; | |
3706 | goto out_ieee80211_free_hw; | |
3707 | } | |
3708 | ||
3709 | pci_set_master(pdev); | |
3710 | ||
093d874c | 3711 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); |
316c30d9 | 3712 | if (!err) |
093d874c | 3713 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); |
cc2a8ea8 | 3714 | if (err) { |
093d874c | 3715 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3716 | if (!err) |
093d874c | 3717 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
cc2a8ea8 | 3718 | /* both attempts failed: */ |
316c30d9 | 3719 | if (err) { |
978785a3 | 3720 | IWL_WARN(priv, "No suitable DMA available.\n"); |
316c30d9 | 3721 | goto out_pci_disable_device; |
cc2a8ea8 | 3722 | } |
316c30d9 AK |
3723 | } |
3724 | ||
3725 | err = pci_request_regions(pdev, DRV_NAME); | |
3726 | if (err) | |
3727 | goto out_pci_disable_device; | |
3728 | ||
3729 | pci_set_drvdata(pdev, priv); | |
3730 | ||
316c30d9 AK |
3731 | |
3732 | /*********************** | |
3733 | * 3. Read REV register | |
3734 | ***********************/ | |
3735 | priv->hw_base = pci_iomap(pdev, 0, 0); | |
3736 | if (!priv->hw_base) { | |
3737 | err = -ENODEV; | |
3738 | goto out_pci_release_regions; | |
3739 | } | |
3740 | ||
e1623446 | 3741 | IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n", |
316c30d9 | 3742 | (unsigned long long) pci_resource_len(pdev, 0)); |
e1623446 | 3743 | IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base); |
316c30d9 | 3744 | |
731a29b7 | 3745 | /* these spin locks will be used in apm_ops.init and EEPROM access |
a8b50a0a MA |
3746 | * we should init now |
3747 | */ | |
3748 | spin_lock_init(&priv->reg_lock); | |
731a29b7 | 3749 | spin_lock_init(&priv->lock); |
4843b5a7 RC |
3750 | |
3751 | /* | |
3752 | * stop and reset the on-board processor just in case it is in a | |
3753 | * strange state ... like being left stranded by a primary kernel | |
3754 | * and this is now the kdump kernel trying to start up | |
3755 | */ | |
3756 | iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); | |
3757 | ||
b661c819 | 3758 | iwl_hw_detect(priv); |
c11362c0 | 3759 | IWL_INFO(priv, "Detected %s, REV=0x%X\n", |
b661c819 | 3760 | priv->cfg->name, priv->hw_rev); |
316c30d9 | 3761 | |
e7b63581 TW |
3762 | /* We disable the RETRY_TIMEOUT register (0x41) to keep |
3763 | * PCI Tx retries from interfering with C3 CPU state */ | |
3764 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
3765 | ||
086ed117 MA |
3766 | iwl_prepare_card_hw(priv); |
3767 | if (!priv->hw_ready) { | |
3768 | IWL_WARN(priv, "Failed, HW not ready\n"); | |
3769 | goto out_iounmap; | |
3770 | } | |
3771 | ||
91238714 TW |
3772 | /***************** |
3773 | * 4. Read EEPROM | |
3774 | *****************/ | |
316c30d9 AK |
3775 | /* Read the EEPROM */ |
3776 | err = iwl_eeprom_init(priv); | |
3777 | if (err) { | |
15b1687c | 3778 | IWL_ERR(priv, "Unable to init EEPROM\n"); |
316c30d9 AK |
3779 | goto out_iounmap; |
3780 | } | |
8614f360 TW |
3781 | err = iwl_eeprom_check_version(priv); |
3782 | if (err) | |
c8f16138 | 3783 | goto out_free_eeprom; |
8614f360 | 3784 | |
02883017 | 3785 | /* extract MAC Address */ |
316c30d9 | 3786 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
e1623446 | 3787 | IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr); |
316c30d9 AK |
3788 | SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr); |
3789 | ||
3790 | /************************ | |
3791 | * 5. Setup HW constants | |
3792 | ************************/ | |
da154e30 | 3793 | if (iwl_set_hw_params(priv)) { |
15b1687c | 3794 | IWL_ERR(priv, "failed to set hw parameters\n"); |
073d3f5f | 3795 | goto out_free_eeprom; |
316c30d9 AK |
3796 | } |
3797 | ||
3798 | /******************* | |
6ba87956 | 3799 | * 6. Setup priv |
316c30d9 | 3800 | *******************/ |
b481de9c | 3801 | |
6ba87956 | 3802 | err = iwl_init_drv(priv); |
bf85ea4f | 3803 | if (err) |
399f4900 | 3804 | goto out_free_eeprom; |
bf85ea4f | 3805 | /* At this point both hw and priv are initialized. */ |
316c30d9 | 3806 | |
316c30d9 | 3807 | /******************** |
09f9bf79 | 3808 | * 7. Setup services |
316c30d9 | 3809 | ********************/ |
0359facc | 3810 | spin_lock_irqsave(&priv->lock, flags); |
5b9f8cd3 | 3811 | iwl_disable_interrupts(priv); |
0359facc | 3812 | spin_unlock_irqrestore(&priv->lock, flags); |
316c30d9 | 3813 | |
6cd0b1cb HS |
3814 | pci_enable_msi(priv->pci_dev); |
3815 | ||
ef850d7c MA |
3816 | iwl_alloc_isr_ict(priv); |
3817 | err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr, | |
3818 | IRQF_SHARED, DRV_NAME, priv); | |
6cd0b1cb HS |
3819 | if (err) { |
3820 | IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq); | |
3821 | goto out_disable_msi; | |
3822 | } | |
5b9f8cd3 | 3823 | err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group); |
316c30d9 | 3824 | if (err) { |
15b1687c | 3825 | IWL_ERR(priv, "failed to create sysfs device attributes\n"); |
795cc0ad | 3826 | goto out_free_irq; |
316c30d9 AK |
3827 | } |
3828 | ||
4e39317d | 3829 | iwl_setup_deferred_work(priv); |
653fa4a0 | 3830 | iwl_setup_rx_handlers(priv); |
316c30d9 | 3831 | |
158bea07 JB |
3832 | /********************************************* |
3833 | * 8. Enable interrupts and read RFKILL state | |
3834 | *********************************************/ | |
6ba87956 | 3835 | |
6cd0b1cb HS |
3836 | /* enable interrupts if needed: hw bug w/a */ |
3837 | pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd); | |
3838 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { | |
3839 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
3840 | pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd); | |
3841 | } | |
3842 | ||
3843 | iwl_enable_interrupts(priv); | |
3844 | ||
6cd0b1cb HS |
3845 | /* If platform's RF_KILL switch is NOT set to KILL */ |
3846 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | |
3847 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | |
3848 | else | |
3849 | set_bit(STATUS_RF_KILL_HW, &priv->status); | |
6ba87956 | 3850 | |
a60e77e5 JB |
3851 | wiphy_rfkill_set_hw_state(priv->hw->wiphy, |
3852 | test_bit(STATUS_RF_KILL_HW, &priv->status)); | |
6cd0b1cb | 3853 | |
58d0f361 | 3854 | iwl_power_initialize(priv); |
39b73fb1 | 3855 | iwl_tt_initialize(priv); |
158bea07 | 3856 | |
a15707d8 | 3857 | init_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 3858 | |
b08dfd04 | 3859 | err = iwl_request_firmware(priv, true); |
158bea07 JB |
3860 | if (err) |
3861 | goto out_remove_sysfs; | |
3862 | ||
b481de9c ZY |
3863 | return 0; |
3864 | ||
316c30d9 | 3865 | out_remove_sysfs: |
c8f16138 RC |
3866 | destroy_workqueue(priv->workqueue); |
3867 | priv->workqueue = NULL; | |
5b9f8cd3 | 3868 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
795cc0ad HS |
3869 | out_free_irq: |
3870 | free_irq(priv->pci_dev->irq, priv); | |
ef850d7c | 3871 | iwl_free_isr_ict(priv); |
6cd0b1cb HS |
3872 | out_disable_msi: |
3873 | pci_disable_msi(priv->pci_dev); | |
6ba87956 | 3874 | iwl_uninit_drv(priv); |
073d3f5f TW |
3875 | out_free_eeprom: |
3876 | iwl_eeprom_free(priv); | |
b481de9c ZY |
3877 | out_iounmap: |
3878 | pci_iounmap(pdev, priv->hw_base); | |
3879 | out_pci_release_regions: | |
316c30d9 | 3880 | pci_set_drvdata(pdev, NULL); |
623d563e | 3881 | pci_release_regions(pdev); |
b481de9c ZY |
3882 | out_pci_disable_device: |
3883 | pci_disable_device(pdev); | |
b481de9c | 3884 | out_ieee80211_free_hw: |
20594eb0 | 3885 | iwl_free_traffic_mem(priv); |
d7c76f4c | 3886 | ieee80211_free_hw(priv->hw); |
b481de9c ZY |
3887 | out: |
3888 | return err; | |
3889 | } | |
3890 | ||
5b9f8cd3 | 3891 | static void __devexit iwl_pci_remove(struct pci_dev *pdev) |
b481de9c | 3892 | { |
c79dd5b5 | 3893 | struct iwl_priv *priv = pci_get_drvdata(pdev); |
0359facc | 3894 | unsigned long flags; |
b481de9c ZY |
3895 | |
3896 | if (!priv) | |
3897 | return; | |
3898 | ||
a15707d8 | 3899 | wait_for_completion(&priv->_agn.firmware_loading_complete); |
562db532 | 3900 | |
e1623446 | 3901 | IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n"); |
b481de9c | 3902 | |
67249625 | 3903 | iwl_dbgfs_unregister(priv); |
5b9f8cd3 | 3904 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
67249625 | 3905 | |
5b9f8cd3 EG |
3906 | /* ieee80211_unregister_hw call wil cause iwl_mac_stop to |
3907 | * to be called and iwl_down since we are removing the device | |
0b124c31 GG |
3908 | * we need to set STATUS_EXIT_PENDING bit. |
3909 | */ | |
3910 | set_bit(STATUS_EXIT_PENDING, &priv->status); | |
c4f55232 RR |
3911 | if (priv->mac80211_registered) { |
3912 | ieee80211_unregister_hw(priv->hw); | |
3913 | priv->mac80211_registered = 0; | |
0b124c31 | 3914 | } else { |
5b9f8cd3 | 3915 | iwl_down(priv); |
c4f55232 RR |
3916 | } |
3917 | ||
c166b25a BC |
3918 | /* |
3919 | * Make sure device is reset to low power before unloading driver. | |
3920 | * This may be redundant with iwl_down(), but there are paths to | |
3921 | * run iwl_down() without calling apm_ops.stop(), and there are | |
3922 | * paths to avoid running iwl_down() at all before leaving driver. | |
3923 | * This (inexpensive) call *makes sure* device is reset. | |
3924 | */ | |
3925 | priv->cfg->ops->lib->apm_ops.stop(priv); | |
3926 | ||
39b73fb1 WYG |
3927 | iwl_tt_exit(priv); |
3928 | ||
0359facc MA |
3929 | /* make sure we flush any pending irq or |
3930 | * tasklet for the driver | |
3931 | */ | |
3932 | spin_lock_irqsave(&priv->lock, flags); | |
5b9f8cd3 | 3933 | iwl_disable_interrupts(priv); |
0359facc MA |
3934 | spin_unlock_irqrestore(&priv->lock, flags); |
3935 | ||
3936 | iwl_synchronize_irq(priv); | |
3937 | ||
5b9f8cd3 | 3938 | iwl_dealloc_ucode_pci(priv); |
b481de9c ZY |
3939 | |
3940 | if (priv->rxq.bd) | |
54b81550 | 3941 | iwlagn_rx_queue_free(priv, &priv->rxq); |
74bcdb33 | 3942 | iwlagn_hw_txq_ctx_free(priv); |
b481de9c | 3943 | |
073d3f5f | 3944 | iwl_eeprom_free(priv); |
b481de9c | 3945 | |
b481de9c | 3946 | |
948c171c MA |
3947 | /*netif_stop_queue(dev); */ |
3948 | flush_workqueue(priv->workqueue); | |
3949 | ||
5b9f8cd3 | 3950 | /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes |
b481de9c ZY |
3951 | * priv->workqueue... so we can't take down the workqueue |
3952 | * until now... */ | |
3953 | destroy_workqueue(priv->workqueue); | |
3954 | priv->workqueue = NULL; | |
20594eb0 | 3955 | iwl_free_traffic_mem(priv); |
b481de9c | 3956 | |
6cd0b1cb HS |
3957 | free_irq(priv->pci_dev->irq, priv); |
3958 | pci_disable_msi(priv->pci_dev); | |
b481de9c ZY |
3959 | pci_iounmap(pdev, priv->hw_base); |
3960 | pci_release_regions(pdev); | |
3961 | pci_disable_device(pdev); | |
3962 | pci_set_drvdata(pdev, NULL); | |
3963 | ||
6ba87956 | 3964 | iwl_uninit_drv(priv); |
b481de9c | 3965 | |
ef850d7c MA |
3966 | iwl_free_isr_ict(priv); |
3967 | ||
b481de9c ZY |
3968 | if (priv->ibss_beacon) |
3969 | dev_kfree_skb(priv->ibss_beacon); | |
3970 | ||
3971 | ieee80211_free_hw(priv->hw); | |
3972 | } | |
3973 | ||
b481de9c ZY |
3974 | |
3975 | /***************************************************************************** | |
3976 | * | |
3977 | * driver and module entry point | |
3978 | * | |
3979 | *****************************************************************************/ | |
3980 | ||
fed9017e | 3981 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
a3aa1884 | 3982 | static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = { |
4fc22b21 | 3983 | #ifdef CONFIG_IWL4965 |
fed9017e RR |
3984 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
3985 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | |
4fc22b21 | 3986 | #endif /* CONFIG_IWL4965 */ |
5a6a256e | 3987 | #ifdef CONFIG_IWL5000 |
ac592574 WYG |
3988 | /* 5100 Series WiFi */ |
3989 | {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */ | |
3990 | {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3991 | {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */ | |
3992 | {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3993 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */ | |
3994 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
3995 | {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */ | |
3996 | {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
3997 | {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */ | |
3998 | {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
3999 | {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */ | |
4000 | {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4001 | {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4002 | {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4003 | {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */ | |
4004 | {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4005 | {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */ | |
4006 | {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4007 | {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */ | |
4008 | {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */ | |
4009 | {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */ | |
4010 | {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */ | |
4011 | {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */ | |
4012 | {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */ | |
4013 | ||
4014 | /* 5300 Series WiFi */ | |
4015 | {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */ | |
4016 | {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4017 | {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */ | |
4018 | {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4019 | {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */ | |
4020 | {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4021 | {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */ | |
4022 | {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4023 | {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */ | |
4024 | {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4025 | {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */ | |
4026 | {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */ | |
4027 | ||
4028 | /* 5350 Series WiFi/WiMax */ | |
4029 | {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */ | |
4030 | {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */ | |
4031 | {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */ | |
4032 | ||
4033 | /* 5150 Series Wifi/WiMax */ | |
4034 | {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */ | |
4035 | {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4036 | {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */ | |
4037 | {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
4038 | {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */ | |
4039 | {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4040 | ||
4041 | {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */ | |
4042 | {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */ | |
4043 | {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */ | |
4044 | {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */ | |
5953a62e WYG |
4045 | |
4046 | /* 6x00 Series */ | |
5953a62e WYG |
4047 | {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)}, |
4048 | {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)}, | |
4049 | {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)}, | |
4050 | {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)}, | |
4051 | {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)}, | |
4052 | {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)}, | |
4053 | {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)}, | |
4054 | {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)}, | |
4055 | {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)}, | |
4056 | {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)}, | |
4b3e8062 | 4057 | |
95b13014 SZ |
4058 | /* 6x00 Series Gen2a */ |
4059 | {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)}, | |
4060 | {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)}, | |
4061 | {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)}, | |
5953a62e WYG |
4062 | |
4063 | /* 6x50 WiFi/WiMax Series */ | |
5953a62e WYG |
4064 | {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)}, |
4065 | {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)}, | |
4066 | {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)}, | |
4067 | {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)}, | |
5953a62e WYG |
4068 | {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)}, |
4069 | {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)}, | |
4070 | ||
77dcb6a9 | 4071 | /* 1000 Series WiFi */ |
4bd0914f WYG |
4072 | {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)}, |
4073 | {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)}, | |
4074 | {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)}, | |
4075 | {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)}, | |
4076 | {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)}, | |
4077 | {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)}, | |
4078 | {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)}, | |
4079 | {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)}, | |
4080 | {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)}, | |
4081 | {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)}, | |
4082 | {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)}, | |
4083 | {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)}, | |
5a6a256e | 4084 | #endif /* CONFIG_IWL5000 */ |
7100e924 | 4085 | |
fed9017e RR |
4086 | {0} |
4087 | }; | |
4088 | MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids); | |
4089 | ||
4090 | static struct pci_driver iwl_driver = { | |
b481de9c | 4091 | .name = DRV_NAME, |
fed9017e | 4092 | .id_table = iwl_hw_card_ids, |
5b9f8cd3 EG |
4093 | .probe = iwl_pci_probe, |
4094 | .remove = __devexit_p(iwl_pci_remove), | |
b481de9c | 4095 | #ifdef CONFIG_PM |
5b9f8cd3 EG |
4096 | .suspend = iwl_pci_suspend, |
4097 | .resume = iwl_pci_resume, | |
b481de9c ZY |
4098 | #endif |
4099 | }; | |
4100 | ||
5b9f8cd3 | 4101 | static int __init iwl_init(void) |
b481de9c ZY |
4102 | { |
4103 | ||
4104 | int ret; | |
4105 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
4106 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | |
897e1cf2 | 4107 | |
e227ceac | 4108 | ret = iwlagn_rate_control_register(); |
897e1cf2 | 4109 | if (ret) { |
a3139c59 SO |
4110 | printk(KERN_ERR DRV_NAME |
4111 | "Unable to register rate control algorithm: %d\n", ret); | |
897e1cf2 RC |
4112 | return ret; |
4113 | } | |
4114 | ||
fed9017e | 4115 | ret = pci_register_driver(&iwl_driver); |
b481de9c | 4116 | if (ret) { |
a3139c59 | 4117 | printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n"); |
897e1cf2 | 4118 | goto error_register; |
b481de9c | 4119 | } |
b481de9c ZY |
4120 | |
4121 | return ret; | |
897e1cf2 | 4122 | |
897e1cf2 | 4123 | error_register: |
e227ceac | 4124 | iwlagn_rate_control_unregister(); |
897e1cf2 | 4125 | return ret; |
b481de9c ZY |
4126 | } |
4127 | ||
5b9f8cd3 | 4128 | static void __exit iwl_exit(void) |
b481de9c | 4129 | { |
fed9017e | 4130 | pci_unregister_driver(&iwl_driver); |
e227ceac | 4131 | iwlagn_rate_control_unregister(); |
b481de9c ZY |
4132 | } |
4133 | ||
5b9f8cd3 EG |
4134 | module_exit(iwl_exit); |
4135 | module_init(iwl_init); | |
a562a9dd RC |
4136 | |
4137 | #ifdef CONFIG_IWLWIFI_DEBUG | |
4e30cb69 | 4138 | module_param_named(debug50, iwl_debug_level, uint, S_IRUGO); |
a562a9dd | 4139 | MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)"); |
4e30cb69 | 4140 | module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR); |
a562a9dd RC |
4141 | MODULE_PARM_DESC(debug, "debug output mask"); |
4142 | #endif | |
4143 | ||
2b068618 WYG |
4144 | module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO); |
4145 | MODULE_PARM_DESC(swcrypto50, | |
4146 | "using crypto in software (default 0 [hardware]) (deprecated)"); | |
4147 | module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO); | |
4148 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); | |
4149 | module_param_named(queues_num50, | |
4150 | iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
4151 | MODULE_PARM_DESC(queues_num50, | |
4152 | "number of hw queues in 50xx series (deprecated)"); | |
4153 | module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO); | |
4154 | MODULE_PARM_DESC(queues_num, "number of hw queues."); | |
4155 | module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
4156 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)"); | |
4157 | module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO); | |
4158 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); | |
4159 | module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K, | |
4160 | int, S_IRUGO); | |
4161 | MODULE_PARM_DESC(amsdu_size_8K50, | |
4162 | "enable 8K amsdu size in 50XX series (deprecated)"); | |
4163 | module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K, | |
4164 | int, S_IRUGO); | |
4165 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); | |
4166 | module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
4167 | MODULE_PARM_DESC(fw_restart50, | |
4168 | "restart firmware in case of error (deprecated)"); | |
4169 | module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO); | |
4170 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); | |
4171 | module_param_named( | |
4172 | disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO); | |
4173 | MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)"); | |
dd7a2509 JB |
4174 | |
4175 | module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int, | |
4176 | S_IRUGO); | |
4177 | MODULE_PARM_DESC(ucode_alternative, | |
4178 | "specify ucode alternative to use from ucode file"); |